FASTFRAME 1300
Contents
1. 22 23 1 Byte A OR On 29 2 BO e eee EeEeEeEGLUEEL eee MERE EEE CERES EMPEROR EE AUEE EEE MERE E 23 B IPC 23 1 jj Ve 23 2 BYTE xxm 24 XL CONNECTOR 5 24 A Headers and Jumpers leeee eese esee esee nennen nennt nnne nnnm rane nmn antennes 24 B VHDGI Connectots ree rr cione ce Irene rebel ccna steceebcenecentesueesetcenseoue 25 C L VDS TTE CON HEO O S 27 COMPONENTS replacement S 1 1cssscccseencsecccsnecceseensssenssnenceanensssennssenessnansasenesesenssnanessaas 28 A PCI Components Placements ccseeeeeeeeeeseeeeseeeeneeeeeeeeeesnaesesneeeneneeseeseseaeensneeeeeees 28 B PMC Component Placements eeseeeeeseeeeeeeeeen nennen entes nn nnn n nnns 29 XIII THOUBLESHOOTING 5 iterata sees eaa cuts euslseatevdariieevdosrscessactniees eteleede 30 XIV ALACRON TECHNICAL 5 31 A Contacting Technical Support eeeeeeeeeeeeseeesesessee ee enen nennt nnn nnne nnn nennen 31 Returning Products For Repair Or Replacement2. seen 32 Reportitig Bu gs Dre re iedees 33 MANUAL FIGURES AND TABLES Figure Subject Page 1 PCI Block Diagram 3 2 PMC Block Diagram 4 3 FastFrame 1300 PCI Bridge Data Flow 10 4 DMA Engine Block Diagram 15 5 DMA Address Counter Registers 17 6 Interrupt Connections 21 7 PMC Component Placement 28 8 PMC Component Placement 29 Table Subject Page 1 Local PCI Registers 13 2 DMA Engine Register Definitions 16 3 DMA Engine Register Locations 18 4 FastFrame 1300 Power Dissipation 19 5 FastFrame 1300 Cables 19 6 Clock Signals 20 7 Control Bits Defined 23 8 Headers and Jumpers 24 9 VHDCI Connector Pin out 26 10 LVDS Fast Channel Connector Pin out 27 OTHER ALACRON MANUALS Alacron manuals cover all aspects of FastSeries hardware and software installation and operation Call Alacron at 603 891 2750 and ask for the appropriate manuals from the list below if they did not come in your FastSeries shipment 30002 00146 30002 00148 30002 00150 30002 00153 30002 00155 30002 00169 30002 00170 30002 00171 30002 00172 30002 00173 30002 00174 30002 00180 30002 00184 30002 00185 30002 00186 30002 00188 Fastlmage and FastFrame HW Installation for PCI Systems ALFAST Runtime Software Programmer s Guide amp Reference FastSeries Library User s Manual Fast I O Hardware User s Guide FastMem Hardware User s
3. ps2i19 515 5 T T jmd D UDA1344 26C31 NS 100 OHM SIP Audi b 8016 i 1 H a l 16C32 e wo 100 OHM SIP x x I ps2119 om DS90CR 16032 16c3 TSSOP56 SO16 SO16 KR KR 100 OHM SIP ou Hoo 109 100 OHM SIF 5 l 5 T00 OHM SIP 0 a So L Sx 090 090 090 8 JAT JB1 Toaz 5 gq Ww E VG 8016 7 d Dual 68 pin vH CI dg g 787962 1 boe gs gI 4 io 0 o ESS s 29 it S D0 iral e c9 E 2 28 PMC Component Placements B 74mm A A TSSOP54 SDRAM TSSOP54 3 E E 6 A e E 060315 E 26031 26031 6032 16032 5016 5016 x l pan B 100 OHM SIP z 5 E 8 DSsocn 3 E TSSOP56 e E uoiBeJ ajoy n g I0OH Nn4U4L 5 yY Y 69 5mm Z 9pIS OWd 0603x5 4 n E SS gs sx6090 TSSOP54 oud 0603x5 SOIC8 F EA T T Sxc090 xe090 D 50108 SP721 EIA e 16
4. ALACRON FASTFRAME 1300 HARDWARE MANUAL SPEED AND FLEXIBILITY 30002 00187 COPYRIGHT NOTICE Copyright 2001 by Alacron Inc All rights reserved This document in whole or in part may not be copied photocopied reproduced translated or reduced to any other electronic medium or machine readable form without the express written consent of Alacron Inc Alacron makes no warranty for the use of its products assumes no responsibility for any error which may appear in this document and makes no commitment to update the information contained herein Alacron Inc retains the right to make changes to this manual at any time without notice Document Name FastFrame 1300 Hardware Manual Document Number 30002 00187 Revision History 2 0 April 22 2003 Trademarks Alacron is a registered trademark of Alacron Inc AltiVec is a trademark of Motorola Inc Channel Link is a trademark of National Semiconductor CodeWarrior is a registered trademark of Metrowerks Corp FastChannel is a registered trademark of Alacron Inc FastSeries is a registered trademark of Alacron Inc Fast4 FastFrame 13006 Fastlmage6 Fastl O and FastVision are registered trademarks of Alacron Inc FireWire is a registered trademark of Apple Computer Inc 3M is a trademark of 3M Company MS DOS6 is a registered trademark of Microsoft Corporation SelectRAM is a trademark of Xilinx Inc Solaris is a trademark of
5. 35 w D co 7 AA GND IGND PINI PIN1 fa a 38 39 40 41 42 49 TS a T1 YINTA IN IN A 3 as ES O1 zl ds N EN D2 CIN1A 1 D2 Jonia A joo ds Ko 6 8 o9 D4 EN XA0 IGND pni a IND IN2A C C C 1 D5 D bard ba IO m S fo EI ano GPIN2 RS 232A_RXD GPIN2 RS 232A_TXD X TRIG1 61 D D I DigInPin Pin TROBE3 TROBES TROBE4 38 srROBE4 39 cka 40 CK3 41 MSTR CK4 4 MsTR CK4 J1B Pinout DiginPin AnalogPin Cam Link Pin 35 36 3 FVAL 3 PXCK 3 PXCK PIN3 IGND IB co co 9 P o GND T3 50 YINSA c el EN A D7 Em as FS O1 m Uu ES D6 D6 E ds N ds co 1 gt ds Ko D D o1 jc o1 ion D o1 j o1 jc O1 D5 D4 AQUTR D4 AGND D3 D3 IN OUT4B D2 IN4A D2 IN4A D1 IN OUT4B D1 DO DO BIB ion iO em XB0 IGND IND lt lt lOlololo gt gt e gt gt zs E C o lO Iz oz 5 IRIS lt Z C Z 5 2Z 5 m lI Q O
6. Strobe_Out 4 GP Out 4 MCIk_Out 4 imeraLink inputs B CPU CLK var 33 MHz PCI 4 CVBS Y C inputs 24 576 MHz EVIP 100 MHz FB RAM VID CLK 30 60MHz 2 5 or 1 8V 3 3v 1 5A LDO Vint for 2 5V 1 5A LDO gt Vint for 16 128MB SDRAM TM1300 FPGAs FastFrame 1300 PCI Block Diagram 04 Jun 01 Audio Video Out In Out VHDCI VHDCI optional ays 100MHz k VID CLK a 5 E SDRAM Controller Auge Codec 2 4 or 8M x 16 bit 2x16Mx16 for TM1310 SDRAMs i 120 Alacron FastChannel PMC Connector ea Figure 1 PCI Block Diagram 3 E Eo 58 2 XC2S150 5FG456C S3 9 MCLK Outs 4 23 80 Prog CLK 5 25100 5 4566 CuK 2 je Low Cost Version ik 3 BlockRam FIFO __ 32x32 Bits 4 Blocks iod z sae m 2oz Er EET gees igi p Strobe_Out 4 8 ao v 34 E599 lal 8 Ll EM NNO GPL 8 DMA Old CPLD i i Controller Functions i 1 v XC2S150 5FG456C i z FPGA B go 64 Bit PCI Core v 2 BlockRam 22 LUTS lam m FIFO 8x64 Bits FIFO 8x32 Bits 8 Blocks 12 FFs 28 JN 9 _y 3 e gu LEDs
7. ST3 END 16 Bits STRB34 ENDPD ST34 PERIOD 16 Bits 5 4 END 16 Bits 16 DMA_TGT ADDR 1 4 A B PCI Target Address 30 Bits DMA TGT CNTRL 1 4 A B RSVD PCIERROS DONE GO DMA Length 24 Bits Table 2 DMA Engine Register Definitions Host Interrupts can be selected or disabled Interrupt A through Interrupt D When interrupts are disabled the host may poll the DONE bit to determine when a transfer has completed Note that polling cycles reduce effective DMA bandwidth accordingly The ID is a field used by driver software to identify customized FPGA design variations The LED field can be used to interrogate or set LEDs on the board Other application specific registers may be added as required Details of the PCI Initiator Address Register are in the diagram below Buffer Select l 33MHz NM PCI Address Counter 30 Bits up Target Addr Transfer Count LM 24 Bits down Done z euog euog y euog XNW L c Done 1 DMA Length 33MHz gr PCI Address Counter 30 Bits up XAN L c Target Addr Transfer Count Po 24 Bits down Done DMA Length Same for DMA Channels 2 thru 4 DMA 2 30 Bit Addr DMA 230 Bit Addr DMA 230 Bit Addr DMA 1 30 Bit Addr XNW Lc y N Figure 5
8. DMA Address Counter Registers Chan Se 1 0 XFER_DONE 30 Bit PCI Addr The DMA interface is accessible from the PCI interface through PCI Base Address Register windows The control registers are located in BAR 0 0x10 which is 32 bit memory mapped and non prefetchable 17 Data is mastered PCI initiator from the DMA controller and thus does not require a Base Address allocation Base Address Register 1 BAR 1 0x14 allows optional access to frame buffer memory It is 32 bit memory mapped and non prefetchable This access is limited to 4KB windows A segment register must be set to select the desired 4KB region for random access The following table shows the memory offsets of the DMA registers at BAR 0 Other application specific registers may be added as required in the space from 0x004 thru OxOOFC These specific designs can be identified via the 8 bit ID register BAR 0 Offset Register 0x0000 DMA_ID_STATUS 0x0010 FE_CONFIG download 0x0020 FE_CONTROL 0x0030 FE_SDRAM_SEG 0x0040 UART 126 0x0050 GPIO_REG 0x0060 STB1 4CTL 0x0070 STB PRE SW 0x0090 STRB12 START 0x00A0 STRB12 ENDPD STRB34_START 0x00CO STRB34 ENDPD 0x0100 DMA ADDR1A 0x0110 DMA TGT CTL1A 0x0120 DMA TGT ADDR2A 0x0130 DMA TGT CTL2A 0x0140 DMA TGT ADDR3A 0x0150 TGT CTL3A 0x0160 DMA TGT ADDR4A 0x0170 DMA TGT
9. The four DMA engines share the PCI interface via a round robin arbitration scheme Arbitration is performed after each PCI burst The burst length is specified in the BRST LEN field in each DMA length Register This field specifies the number of 4 byte transfers that the initiator will attempt when capture data is available 4 through 64 bytes supported In general it should match the destination CacheLineSize configuration register value A Zero 0 value is treated as 16 14 C D DMA Engine Block Diagram BET DMA Arbiter Other Regs DMA ADDR1 DMA ADDR2 abil INTER FPGA Interface 32 Bit Data DMA_ADDR3 DMA_ADDR4 Initiator Machine 32 Bits DMA Engine Registers o L PPY 19d lp 1119 ALana Data Flow Machine ZHWSZ 419 GIA a em z loc E g a mN C 9 32 Bit Register 32 Bit Register je 32 Bits j ge 2 m N e 32 Bit Register 2 m S BlockRam FIFO 64Bits x 256 2 i en uu ecu or us A4 BIOGKS ios eoo io B 2 co ucc SME DT Uu a V ADDR31 0 ADIO63 0 PCI CMD etc Xilinx PCI 64 PCI Core Interface 33MHz AD63 0 CBE7 0 FRAME etc Figure 4 DMA Engine Block Diag
10. XC2S150 5FG456C mt o 2 d 8 Po 2 2 CameraLink inputs E aame 64 Bit PCI Core AS 2 BlockRam 22 LUTS BlockRam vv FIFO 8x64 Bits t FIFO 8x32 Bits 8 Blocks 12 FFs 2 Blocks S yoat ies 6 To 5 282 af ROI MID a a XC17S150A D S vosc ay A Strobe Out 4 Ss Out 4 a GP_Out 4 120 Alacron FastChannel P4 Connector PMC P1 P2 amp P3 Connectors Indicates MCIk Out 4 Clock Signal Figure 2 PMC Block Diagram Il DATA ACCESS CAPTURE The FastFrame1300 supports two configurations of data access e Direct DMA based Frame Grabber e TriMedia based image processing The DMA based mode is used in the simplified version of the FastFrame 1300 and is intended for host based image processing The TriMedia based mode is more flexible allowing some data manipulation before the data goes off board Because the TriMedia processor and any device attached to the PMC site is behind a non transparent bridge the host s PCI scan does not see devices behind the bridge including video display adapters etc Alacron writes device drivers specifically to initialize and communicate with these devices Contact Alacron for assistance from the engineering staff if your application s call for additional specific device drivers A TriMedia Based Capture In TriMedia based capture video data is buffered by the TriMedia processor which can access images in random acce
11. 4 Ill DATA ACCESS CAP TURE 5 TriMedia Based Capture 5 PCI Bridging LOGIC 5 C DMA Based Captu te curta antata idi cse see dabaa aida caper Cua 5 IV INPUT OUTPUT FORMATS eerie rente nao si t2 ren amps aeta ni de Ryo SE KE am de oaia 7 A Analog CVBS laf e 7 B Digital H8 422 uuu caa 7 C Digital LVDS 7 D 7 8 1 Optional Video EfRCOGGr 5i 8 2 Optional A dio 8 3 Optional FastChannel 8 V PCI BRIDGE TRIMEDIA BASED 9 A Bridge Features 9 1 S pport d 9 2 Features Not Supported ssssssssssssssssssssseeeeeeneeenn nennen nnns nnns nnns 9 B Secondary Bus Arbiter 10 C PCI Bridge Transactions eeeeeeeeieeseseeeeeeeeeeeee sienne nnne nnn tn sani n nnnm nn nnns 11 1 Post
12. 6 2 ak ae 8 Fo E 64 Bit PCI Edge Connector In addition to the image processing capabilities of the optional on board TriMedia TM1300 processor the FastFrame 1300 provides image data capture from up to four analog CVBS or Y C sources or from digital sources Camera Link or LVDS of up to 32 bits The on board FPGA provides data buffering formatting and steering Camera strobes can be generated from software or from external inputs to the board The analog front end is configured using l C either by the on board TriMedia processor or from the host via the J4 connector The data path FPGA is configured either directly from the PCI interface or by the TriMedia processor Input output to the board in either configuration with processor or without processor uses Alacron s FastSeries 68 pin VHDCI system and a Camera Link cable designed specifically for use with the FastFrame 1300 The FastFrame 1300 provides two on board UARTs implemented in an FPGA and used to communicate with external devices including CameraLink cameras There is no handshaking support The board can also be configured to allow external RS 232 control of a Camera Link device which is usually connected to the host PC to allow PC based applications to control and configure the camera A PMC Design The PMC design is simplified a configuration without a TriMedia processor in which the only components on the board are the four analog inputs and one
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14. FPGA In this configuration the analog front end is configured by the host system FastFrame 1300 PMC y RS 232 CPU_CLK var 3 3V 2 5 or 1 8V _y vint for TM1300 1 Driver lt gt To FPGA L 33 MHz PCI i 1 54 LDO a Block Diagram Sper o 70595 Cee gt 24 576 MHz EVIP 25V Jun CLK a 100 MHz FB RAM 15ALDO Vint for FPGAs 04 Jun 01 Gen e VID CLK 30 60MHz SE aues 4 CVBS Y C inputs i 16 128MBSDRAM 5 i optional I Audio Or Video Out In Out Ro o BIULLILILIlI JP l VHDCI VHDCI d 100MHz E VID_CLK a LEDs 6 i i 8 BGR i JL O Wik a 8 a SDRAM e 2 4 or 8 M x 16 bit a Controller 2x16Mx16 for TM1310 8 SDRAMs 8 55 z g 2 XC2S150 5FG456C z 53 FPGA 9 MCLK Outs 4 B H EE E 3 Zo Prog CLK XC2S100 5FG456C aa Low Cost Version 2s l om BlockRam FIFO 8 lt i 32x32 Bits 4 Blocks rig 4 i S P 26 Ct 4 ratas w a i 5 z e Siibe Out 4 898 8 4 8 bit LVDS or vse ZRS E RS422 inputs 8 Je 8888 T 5 N 8 DMA Old CPLD Ni e g Controller Functions 32 Biv33MHz PCI i i E N y D Lien H
15. allowing address translation between primary and secondary side devices Type 0 configuration registers for each direction 3 Base Address Registers BARO through BAR2 on both primary and secondary interface BARO Used by the bridge as the 1K memory mapped CSR space BAR1 Can be configured as memory or I O window BAR2 Memory window Direct Offset address translation for memory and I O in both directions Memory block size adjustable from 256K bytes to 2G bytes I O window size adjustable from 64 to 256 bytes PCI spec maximum for Type 0 256 bytes of Posted Write data buffering in both directions for one transaction 256 bytes of Read data buffering in both directions for one transaction Supports single delayed transactions I O and configuration in both directions Can generate Type 0 and Type 1 configuration cycles from either interface via CSR accesses BAR sizes types stored in TriMedia Boot EEPROM for configuration flexibility 2 Features Not Supported The FastFrame 1300 Bridge does not support the following Subtractive Decoding which is not needed for a non transparent bridge Exclusive LOCK access is not supported in the FastFrame 1300 Multiple delayed transactions Only one active transaction per side others are retried Dual address cycles Ignores as target and does not initiate as master Fast back to back cycles Concatenation or merging of separate contiguous data transactions into one transaction or
16. burst Direct VGA Support Does not support VGA Palette snooping or I O which must be explicitly mapped through a window B Secondary Bus Arbiter The PCI FPGA also provides a Secondary Bus Arbiter This logic arbitrates between the three devices on the secondary side of the bridge the TriMedia the PMC and the bridge itself The arbiter operates in a round robin fashion parking the secondary PCI bus with the last master to use the bus Downstream Posted Write 256 Bytes Upstream Read Buffer 256 Bytes Downstream Read Buffer 256 Bytes Upstream Posted Write 256 Bytes Downstream Delayed Buffer 4 Bytes Upstream Delayed Buffer 4 Bytes CSR Registers 128B Bridge Control REQ lt 0 2 gt Secondary Bus Arbiter lt 2 07LND 32 Bit 33MHz PCI 32 Bit 33MHz PCI Side Primary Si Config Registers Primary Side Master Control Target Control Primary Side Secondary Side Config Registers Secondary Side Target Control Secondary Side Master Control Figure 3 FastFrame 1300 PCI Bridge Data Flow 10 C PCI Bridge Transactions The Fast Frame PCI Bridge handles four types of PCI transactions The behavior of the bridge during each of these transactions is described on the following pages Transactions are performed in the following order e Posted Writes must complete before an
17. by the host processor The FastFrame 1300 provides DMA master functions On board SDRAM buffers allow buffer storage up to 128MB DMA block lengths of up to 16MB are supported and individual PCI transactions can burst up to 256 bytes The DMA controller has two sets of control registers and thus can double buffer transfers interrupting the host when a programmed DMA transfer have been completed and immediately switching to the other DMA buffer Alternatively the host can poll a register to interrogate the DMA status Additional features include e PCI master DMA engine with two 2 buffer pointers allows uninterrupted data flow e DMA transfer sizes from 16 bytes to 4MB must be 4 byte aligned The video data on the FastFrame 1300 is available only in streaming serial format not in a random access fashion The data can go off board via the host PCI bus or in the PCI version via an optional LVDS Fast Channel connector In the DMA based capture configuration only the FastFrame 1300 DMA registers are available from the PCI bus The PMC site option is not supported IV INPUT OUTPUT FORMATS The FastFrame1300 is usually configured for your particular application s to support one of the input types listed below although special applications requiring a mix of these inputs may be supported after consultation with the Alacron engineering staff A Analog CVBS or Y C The FastFrame1300 board supports simultaneous capture of up to fou
18. e Four 4 PCI Master DMA engines to support up to four independent video sources e Each DMA engine supports double buffering using two buffer pointers for uninterrupted data flow e DMA transfer sizes 16 bytes to 64MB must be 4 byte aligned e Message Passing Mode like option for frame per buffer capability B DMA Operation 1 Double Buffering The FastFrame 1300 DMA engine uses a double buffering scheme to allow uninterrupted data flow to the host Initially the host programs the first buffer pointer for the first transfer and the second to continue where the first buffer ends When the DMA completes the count specified in the first buffer it optionally sends an interrupt to the host and switches ping pong fashion to the second buffer This allows the host to have a full buffer transfer time to set up the first pointer in time for the next transfer When the second buffer DMA completes an optional interrupt is again sent to the host and the DMA engine switches back to buffer number one If at any time the buffer is not valid i e not initialized after use the DMA transfer stops 2 Front end FPGA Data from separate front end TAPs can be assembled by the front end FPGA for the DMA engines to stream to the host The DMA engines indicate which of buffer memory regions they are reading from The front end FPGA translates these region selects into SDRAM address regions allowing the buffer architecture to be flexible
19. o 5 o Llc Ic r D D pary par w Co T E m D loo gt 1 61 6 4 GPIN4 4 LVAL 4 LVAL 4 FVAL 4 4 PXCK 4 PXCK D jo D D I Pin 6 8 9 Table 9 Pinout of J1A J1B VHDCI Connector 26 C LVDS TTL Connectors Fast Channel Connector Pin Out J2Pin Signal J2 Pin Signal__ 6 FC DAT2N 31 FC 4 8 FC DATSN 33 FC DATtsP 9 FC DAT4P 34 FC DATISN J3 Pin Signal J3Pin Signa O 4 FC DATZN C DAT29P 5 rc C DAT29N 6 FC DATeN C DAT30P 7 rcDAT9P C DAT3ON 8 Fc DATION C DAT31P 9 FC DAT20P C DATSIN 10 FC DAT20N 11 FC 2 12 FC DAT2iN C 4 18 FC DAT22P C CTLAN 14 15 16 18 19 20 21 22 7 ND C_CTL5P C CTL5N C CTL6P C CTL6N C CTL7P C CTL7N C PXCK3P C PXCK3N C PXCK3P 23 FC DAT26P 48 FC PXCKSN 25 FC DArz7P 5 C C zu 01 m m m m m m m m m m 6 C9 n 7n on n n 1 Z Z S 4 5 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 ND Table 10 Pinout of LVDS FastChannel Connectors 27 PCI Components Placements COMPONENTS REPLACEMENTS Xil A J3 50 Pin Vert Header 26081 26081 26031 5016 5016 01
20. output stream from a CCIR 656 data stream The encoder chip can also generate NABTS Teletext encoded data on the video signal The video output signal replaces the secondary video input of the last CVBS input channel on the VHDCI connector This design uses a Philips SAA7121 and is configured via C at address 0x88 2 Optional Audio Codec The FastFrame1300 board supports an optional 24 bit stereo Audio CODEC to allow analog audio signals to be encoded or decoded into an 2 8 format serial stream for processing by the TriMedia or by the on board FPGA The CODEC can handle sampling at up to 48KHz The audio channels appear on the VHDCI connector The design uses a Texas Instruments TAS3002 device and is configured via at address 0 3 Optional FastChannel Header The FastFrame1300 board optionally supports up to 32 bits of LVDS or TTL Fast Channel data via dual 50 pin headers The direction of this Fast Channel interface is selectable on a byte 8 bit boundary via C at address 0x40 amp 0x42 This option prevents normal operation of the PMC Fast Channel although the PMC PCI operation is not affected V PCIBRIDGE TRIMEDIA BASED CONFIGURATION A Bridge Features 1 Supported Features The PCI Bridge logic on the Fast Frame 1300 implements a 32 bit S3MHz non transparent PCI bridge supporting the following features 3 3V operation with 5 0V tolerant I O Non transparent bridge Appears as a single Type 0 Device
21. 032 5 5449 26031 06036 016 016 16032 16032 5016 282119 soie SAA7111All 16C32 100 OHM SIP soie C100 OHMSIP_ LIO OFM SIP 16C32 910S 9016 6699 0603x5 DS90CR TSSOP56 JA1 JB1 pin VHDCI 9pIS OWd Figure 8 PMC Components Placements 29 XII TROUBLESHOOTING There are several things you can try before you call Alacron Technical Support for help Make sure the computer is plugged in Make sure the power source is on Go back over the hardware installation to make sure you didn t miss a page or a section Go back over the software installation to make sure you have installed all necessary software Run the Installation User Test to verify correct installation of both hardware and software Run the user diagnostics test for your main board to make sure it s working properly Insert the Alacron CD ROM and check the various Release Notes to see if there is any information relevant to the problem you are experiencing The release notes are available in the directory usr alacron alinfo Compile and run the example programs found in the directory usr alacron src examples Find the appropriate section of the Programmer s Guide amp Reference or the Library User s Manual for the particular library and problem you are experiencing Go back over the steps in the guide Check the program
22. 44 The FastFrame1300 board supports up to 32 bits of RS 644 format LVDS digital input data The data can be in the form of four 4 individual 8 bit TAPs two 2 16 bit TAPs one 1 32 Bit TAP or any combination The data can then be assembled into the desired format by the front end FPGA Each of the TAPs has individual clock frame valid and line valid inputs On board 1000hm termination is provided for LVDS inputs Alacron digital input cable P N 10024 00161 or 10024 00224 is used with this type of input setup D Camera Link The FastFrame 1300 board supports up to two 2 Camera Link interfaces each of which represents the base configuration described in the October 2000 Camera Link specifications Each interface can run at up to 66MHz Each Camera Link interface supports 24 bits of data and four bits of control as well as the bi directional serial communications interface and CC1 through CC4 signals Termination for all Camera Link signals is provided on board Alacron supplies a special Camera Link cable to be used only with the FastFrame 1300 The FastFrame 1300 Camera Link cable can be used for either of the board s Camera Link interfaces It connects to a standard 26 pin 3M MDR connector Alacron Camera Link cable 10024 00250 is used with the Camera Link setup E Other Options 1 Optional Video Encoder The FastFrame1300 board supports an optional NTSC PAL Video Encoder which will generate a CVBS or Y C S video
23. 6 50 Pin Vert Header SOR AD FCT162244 TSSOP 48 N OWd j eNCOWd EA FCT162244 SDRAM ease I ge ne TSSOP 48 S53 gj IN ona 3 O up 2 Od BEN t Mn 7 x 3 E E LNF OWd SDRAM S TSSOP54 a c E o s Q E 8 3 4 Analog 26c31 26081 N ET Planes 8016 8016 6016 x x 16682 E
24. 6 bits are desired 22 A FC Address 0 x 40 1 Byte 1 Bit Signal Name Meaning 7 FC3_IN When 0 connects FC data bits D7 thru DO to FPGA inputs 31 24 6 FC2_IN When 0 connects FC data bits D7 thru DO to FPGA inputs 23 16 5 FC1_IN When 0 connects FC data bits D7 thru DO to FPGA inputs 15 08 4 FCO_IN When 0 connects FC data bits D7 thru DO to FPGA inputs 07 00 3 FC3_OUT When 0 connects FPGA bits 31 24 to FC data bits D7 thru DO 2 FC2_OUT When 0 connects FPGA bits 23 16 to FC data bits C7 thru CO 1 FC1_OUT When 0 connects FPGA bits 15 08 to FC data bits B7 thru BO 0 FCO_OUT When 0 connects FPGA bits 07 00 to FC data bits A7 thru AO 2 Byte 2 Bit Signal Name Meaning 7 FC_CKC7 When 0 connects VID CLK to FC CLKD input OR output 6 FC CKC6 When 0 connects TM VOCLK to FC CLKC input OR output 5 FC CKC5 When connects VID CLK to FC CLKB input OR output 4 FC_CKC4 When 0 connects TM_VOCLK to FC_CLKA input OR output 3 FC_CKC3 When 0 connects FCHAN CKD to FC_CLKD input OR output 2 FC_CKC2 When 0 connects FCHAN_CKC to FC_CLKC input OR output 1 FC CKC1 When connects FCHAN CKB to CLKB input OR output 0 FC CKCO When connects FCHAN CKA to CLKA input OR output B FC Address 0 x 42 1 Byte 1 Bit Signal Name Meaning 7
25. CTL4A 0x0200 DMA TGT ADDR1B 0x0210 DMA TGT CTL1B 0x0220 DMA TGT ADDR2B 0x0230 DMA TGT CTL2B 0x0240 DMA TGT ADDR3B 0x0250 DMA_TGT_CTL3B 0x0260 DMA_TGT_ADDR4B 0x0270 DMA_TGT_CTL4B Table 3 DMA Engine Register Locations BAR 0 18 VII POWER UP SEQUENCE The FastFrame 1300 software controlled procedure for power up and module initialization follows this sequence A 3 3V and 5 0V Power Applied 2 5 1 8V power stabilizes The time this takes depends on the 3 3V ramp rate PCI FPGA configures from EPROM TM1300 reads EEP configuration data Host processor performs BIOS scan and configures TM1300 PCI resources if present Host processor loads TriMedia program into TriMedia RAM and runs TriMedia initialization code configures front end FPGA optional EEPROM configuration Software initializes on board registers via TriMedia lC controller Data capture may begin Power Dissipation The FastFrame 1300 will dissipate power approximately as shown below Version 45V Power 3 3V Power 12V PCI 16W 11W 30mA PMC 5W 10W 30mA Table 4 Approximate Power Dissipation Both the PCI and PMC versions of FastFrame 1300 have auxiliary power connectors The PMC auxiliary power connector is for use in systems that cannot supply 3 3V via the PMC connector The PCI auxiliary power connector is used to provide supplemental power when the PMC site is used See the Installation Manua
26. FC TRM ENA When 0 enables LVDS termination of FCHAN B7 thru BO 1 6 FC TRM When 0 enables LVDS termination of FCHAN A7 thru AO 0 5 FX5 OUT When 0 enables C03 and C07 outputs from FPGA 4 FX4 OUT When enables C02 and C06 outputs from FPGA 3 FX3 OUT When 0 enables PIXCK4 and PIXCK2 outputs 2 FX2_OUT When enables C01 and C05 outputs from FPGA 1 FX1_OUT When enables C00 and C04 outputs from FPGA 0 FXO_OUT When 0 enables PIXCK3 and PIXCK1 outputs 23 2 Byte 2 Bit Signal Name Meaning 7 FC TRM When 0 enables LVDS termination of FCHAN D7 thru DO 3 6 FC TRM ENA When 0 enables LVDS termination of FCHAN C7 thru CO 2 5 FX5 IN When enables C03 and C07 inputs to FPGA 4 FX4_IN When 0 enables C02 and C06 inputs to FPGA 3 FX3_IN When enables PIXCK4 and 2 inputs to FPGA 2 FX2_IN When 0 enables C01 and C05 inputs to FPGA 1 FX1_IN When enables C00 and C04 inputs to FPGA 0 FXO IN When 0 enables PIXCK3 and PIXCK1 inputs to FPGA CONNECTOR PIN OUTS The pin out of the FastFrame 1300 dual 68 pin VHDCI connector retains the same pin assignments for digital inputs 4 TAPs including GPINs and GPOUTS Strobes and Trig Ins as are found on Alacron s Fastlmage 1300 board Analog inputs retain the original Alacron FastSeries pin out for the CVBS in
27. Manual ALRT Runtime Software Programmer s Guide amp Reference ALRT ALFAST amp FASTLIB Software Installation Manual for Linux ALRT ALFAST amp FASTLIB Software Installation for Windows NT Fastlmage 1300 Hardware User s Guide FastMem Programmer s Guide amp Reference FastMem Hardware Installation Manual Fast4 1300 Hardware User s Guide FastSeries Getting Started Manual FastVision Hardware Installation Manual FastVision Software Installation Manual FOIL FastSeries Object Imaging Library SYSTEM REQUIREMENTS Windows NT with service pack 6 or Windows 2000 with service pack 2 operating systems fully installed Minimum 128MB memory installed Software Development Environment SDE WinZip software Acrobat Reader Software FastFrame 1300 runtime software is available for Linux Solaris and Windows NT and Windows NT 2000 operating systems Air circulation of at least 200 LFM is required for the Alacron FastFrame 1300 boards The operating temperature range of the FastFrame 1300 boards is 0 Celsius to 40 Celsius vi FASTFRAME 1300 FEATURES The Alacron FastFrame 1300 is for original equipment manufacturers and end users who anticipate a demand for diverse I O requirements and high bandwidth Available in both analog digital and digital only configurations the FastFrame 1300 with optional Philips TriMedia microprocessor provides for complex image and digital signal processing A FastFram
28. Sun Microsystems Inc TriMedia is a trademark of Philips Electronics North America Corp Unix is a registered trademark of Sun Microsystems Inc Virtex is a trademark of Xilinx Inc Windows Windows 95 Windows 98 Windows 2000 and Windows are trademarks of Microsoft Corporation All trademarks are the property of their respective holders Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Telephone 603 891 2750 Fax 603 891 2745 Web Site http www alacron com Email sales alacron com or support alacron com TABLE OF CONTENTS Copyright Notice 3 3 REEL cae E I Ere deas ii Table of iii Manual Figures amp Tables eme enemies eene V Other Alacron Manuals sss heh emen renes vi System Requirements erii eee en Lv tuu dre Doa Ehe cbe ed de cO D PR oL E PED Ts vi L FASTFRAME 1300 5 1 A FastFrame 1300 Features eese esee nnne entnehmen nnn r anne nnn annnm 1 B Optional Features mM 2 C 2 I INTRODUCTION TO FASTFRAME 1300 1ccssccssseecsseensnencssnenssseonssseeesnancasseseseensnsnesasanes 3 A
29. T ALFAST or FASTLIB software that you are using You can find this information in a file in the directory usr alfast alinfo The type and version of the host operating system i e Windows 98 Note the types and numbers of all your software revisions daughter card libraries the application library and the compiler The piece of code that exhibits the problem if applicable If you email Alacron the piece of code our Technical Support team can try to reproduce the error It is necessary though for all the information listed above to be included so Technical Support can duplicate your hardware and system environment 31 B Returning Products For Repair Or Replacement Our first concern is that you be pleased with your Alacron products If after trying everything you can do yourself and after contacting Alacron Technical Support you feel your hardware or software is not functioning properly you can return the product to Alacron for service or replacement Service or replacement may be covered by your warranty depending upon your warranty The first step is to call Alacron and request a Return Materials Authorization RMA number This is the number assigned both to your returning product and to all records of your communications with Technical Support When an Alacron technician receives your returned hardware or software he will match its RMA number to the on file information you have given us so he can solve the proble
30. TM_AIOSCK 1 40MHz S W Select TM1300 gt FE FPGA TM AOSCK 1 40MHz S W Select TM1300 gt FE FPGA AUDIO CODEC FECLK1 1 75MHZ per Conf ChanLnk1 PixClk1 or FchanCIkA gt FE FPGA FECLK2 1 75MHZ per Cont ChanLnk2 PixClk4 or VID gt FE FPGA PIX CLK 2 3 1 75MHz Analog Dig Vid In gt FPGA l O FchanCIk B C 1 75MHz FastChan gt FPGA l O Table 6 Clock Signals Clocks above with one asterisk are multiplexed CMOS switch selectable by the FPGA Only one of the two selections is available at any given time Channel Link Camera Link differential and analog inputs are mutually exclusive population options Clocks above with two asterisks connect to FPGA I O pins not to dedicated global clocks So care must be taken to prevent problems due to clock skew in the FPGA logic using these clocks The Front End FPGA has the following clock inputs available e PIX CLK1 thru PIX CLKA from video inputs e SDRAM Clock approx 100MHz for Frame Buffer e TriMedia VO CLK e FastChannel Clks From J4 VID CLK Selectable Video Clock from CLK Generator The PCI FPGA has the following clock inputs available nter FPGA CLK from FPGA e V 34 CLK 20MHz from ClkGen 20 e VID CLK Selectable Video Clock from CLK Generator e PCI CLK 33MHz for secondary PCI interface or Primary Master UART_CLK 6 144 MHz for UART timing IX INTERRUPTS The interr
31. dentical address C BE and Data with a Cycle Complete The response to the initiator depends on the outcome of the target transfer A normal TRDY response indicates a normal transfer Target Abort and Master Abort are reported as Target Abort to the initiator If the initiator does not retry within 2 clocks the posted write is discarded and any written data is lost although the target write may have been performed In this case SERR is asserted if enabled 3 Delayed Reads The bridge treats I O reads and CSR generated configuration writes as single cycle Delayed Reads The sequence of a Delayed Read is as follows The bridge accepts the read address and C BEs and then terminates the initiator cycle as a Retry 11 The bridge attempts to complete the cycle on the target bus Responds to initiator with Retry The bridge responds to initiator retry of identical address and C BE with a Cycle Complete The response to the initiator depends on the outcome of the target transfer A normal TRDY response indicates a normal transfer Target Abort and Master Abort are reported as Target Abort to the initiator If the initiator does not retry within 2 clocks the posted read is discarded and any data read from the target is lost 4 Prefetchable Reads The following types of transactions are considered prefetchable Memory Read Read Line Read Multiple to prefetchable regions I O and configuratio
32. e TriMedia as PCI bus master e Optional stereo Audio Codec up to 20 bit format up to 48K samples sec e Optional color Video Encoder PAL or NTSC from CCIR 656 data C PCl Version Options e Optional PMC Site 32Bit 33MHz PCI 32 bit Alacron Fast Channel e Optional LVDS or TTL Alacron Fast Channel headers Il INTRODUCTION TO FASTFRAME 1300 Alacron s FastFrame 1300 is available in both analog digital and digital only configurations for considerable flexibility at a reasonable cost Depending upon your specific needs and your anticipated applications your FastFrame 1300 has been configured either with or without a Philips TriMedia TM1300 series microprocessor an option designed to keep your costs down while providing you with the tools you need either for complex image and signal processing or for frame storage and buffering The FastFrame 1300 design enables Alacron to offer either the half length PCI board with TM1300 processor or a simplified setup wherein the board components include four analog inputs one FPGA and no processor In this latter form the analog front end is configured by the host system FastChannelHeaders E Ni gi Y Qi os 2 3 Lower VHDCI 68 Connector Upper VHDCI 68 Connector 28 lt 88 lt 58 RS 232 Driver Revr I To FPGA p MG 4 8 bit LVDS or RS422 inputs Channel Link
33. e 1300 Features PMC and PCI Form Factors available Optional on board TriMedia TM1300 180MHz processor or higher with 16 or 32MB of SDRAM Will support future TM1310 20 processors with 64MB Capable of over 720 MFLOPS of computational power 64 or 32 bit 33MHz PCI interface Input Output via dual stacked 68 pin VHDCI connector Collects data from up to four 4 simultaneous CVBS or Y C S Video analog inputs Collects data from up to 32 bits of LVDS digital input Collects data from two 2 Camera Link Channel Link inputs Two 2 RS 232C serial port interfaces Four 4 general purpose inputs Four 4 general purpose outputs Two 2 trigger inputs Four 4 strobe outputs Four 4 clock outputs Selectable termination Allows daisy chaining of boards On board image buffering and formatting FPGA with optional 16 to 128MB of frame memory SDRAM operates at 160MB s in full duplex mode or operates at 320MB s in half duplex mode DMA Engine allows direct to host image capture on FastFrame 1300 without TriMedia processor 32 bit Fast Channel interface link to Alacron Fastlmage 1300 or Alacron FastVision capable of 320MB s peak throughput Twelve 12 general purpose LEDs FPGA controlled One 1 TriMedia controlled Philips SAA7111A Enhanced Video Input Processor B Optional Features e Optional local TriMedia boot for embedded systems using 2 4MB of on board FLASH accessible via the TriMedia s X I O interface
34. ed memory 8 11 2 Delayed 11 3 Delayed REAS ccccccceeceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeas 11 4 Prefetchable REads ccccccccccccccecsceseecseeceueeeecsueeeeeeeeceuueeeeeeaseueeeeuueuesuueeaeeeaeeaeueass 12 D Local Registers 19 V DMA BASED CONFIGURATION 221 12 ccscccerccerceseeseecssncesncnsncnsnansnansnanensecnaeeessensseneseeees 14 A D 14 me 14 1 Double Buffering AE AS A 14 2 Front end 14 C DMA Engine Block Diagram e eeeeeeeeeeeeeenee eene nennen nnn nnnm annees 15 D DMA Engine Registers uode Loan e ran oee Eu E nane ee is 15 VI POWER UP 5 19 A Power 19 FastFrame 1300 Cables e tutti tedio ecce eite sana aa aC ea aacra aoa 19 VIII CLOCK SCHEME iinis aranana iaaiaee an aa denai aaie aa diaaa aa dana aa da iaaa aaa 20 DC INTEHRHRUPTS iudi Ae ia CU eM 21 X FASTCHANNEL
35. l 30002 00185 for installation assistance B FastFrame 1300 Cables The appropriate cables from the list below have been included in your FastFrame 1300 shipment If you need additional cables contact Alacron Sales or Technical Support Alacron Part Number Cable Use 100024 00160 DC Power Cable 100024 00161 Digital Input Cable 100024 00162 Analog Input Cable 100024 00224 Digital In Adapter Cable 100024 00250 Camera Link Cable Table 5 FastFrame 1300 Cables 19 Vill CLOCK SCHEME The FastFrame 1300 design takes advantage of the high data rates possible with the TM1300 processor while enabling tight control of the timing on high speed buses especially when utilizing the Alacron Fast Channel connector The clocks are selected and generated through the FPGAs The on board clock generator chips Cypress CY2292 generate the following clocks Clock Signal Frequency Used by SDRAM Clk 100 00MHz Buffer SDRAM FPGA CPU_CLK 47 666MHz Selectable TM1300 EVIP_CLK 24 576MHz SAA7111A s V34_CLK 20 000MHz TM1300 PCI FPGA VID CLK 2 40 80MHz Selectable FPGAs TM1300 FastChan VideoOut PCI CLK 33MHz PCI FPGA TriMedia PMC Site UART CLK 6 144MHz PCI FPGA The following clocks are also available on the FastFrame 1300 board Clock Signal Freq Sourced by gt Used By TM_VOCLK 1 80MHz S W Select TM1300 gt FE_FPGA FastChan VideoOut
36. m you ve cited When calling for an RMA number please have the following information ready Serial numbers and descriptions of product s being shipped back A listing including revision numbers for all software libraries applications daughter cards etc A clear and detailed description of the problem and when it occurs Exact code that will cause the failure A description of any environmental condition that can cause the problem All of this information will be logged into the RMA report so it s there for the technician when your product arrives at Alacron Put boards inside their anti static protective bags Then pack the product s securely in the original shipping materials if possible and ship to Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Clearly mark the outside of your package Attention RMA 80XXX Remember to include your return address and the name and number of the person who should be contacted if we have questions 32 C Reporting Bugs We at Alacron are continually improving our products to ensure the success of your projects In addition to ongoing improvements every Alacron product is put through extensive and varied testing Even so occasionally situations can come up in the fields that were not encountered during our testing at Alacron If you encounter a software or hardware problem or anomaly please contact us immediately for assistance If a fix is not available right away of
37. ming examples supplied with the runtime software to see if you are using the software according to the examples Review the return status from functions and any input arguments Simplify the program as much as possible until you can isolate the problem Turning off any operations not directly related may help isolate the problem Finally first save your original work Then remove any extraneous code that doesn t directly contribute to the problem or failure 30 XIV ALACRON TECHNICAL SUPPORT Alacron offers technical support to any licensed user during the normal business hours of 9 a m to 5 p m EST We offer assistance on all aspects of processor board and PMC installation and operation A Contacting Technical Support To speak with a Technical Support Representative on the telephone call the number below and ask for Technical Support Telephone 603 891 2750 If you would rather FAX a written description of the problem make sure you address the FAX to Technical Support and send it to Fax 603 891 2745 You can email a description of the problem to support alacron com Before you can contact technical support have the following information ready Serial numbers and hardware revision numbers of all of your boards This information is written on the invoice that was shipped with your products Also each board has its serial number and revision number written on either in ink or in bar code form The version of the ALR
38. n transactions or reads from non prefetchable regions will NOT be prefetched The bridge will perform limited speculative reads to prefetchable regions It will fill up to a cache line boundary and then terminate the target transfer If the bridge is still delivering data to the initiator at the same time it is accepting data from the target the bridge enters Flow Through mode In this mode the bridge will continue to transfer data until the buffer is empty for more than 7 cycles or until a 4KB address alignment boundary is reached 12 D Local Registers In addition to the configuration registers required by the PCI Bridge specification the following local registers are defined They have the same designation as in the DMA configuration BAR 0 Offset Register 0x0000 DMA_ID_STATUS 0x0010 FE_CONFIG download 0x0020 FE_CONTROL 0x0030 FE_SDRAM_SEG 0x0040 UART 1260 0x0050 GPIO_REG 0x0060 STB_CTL 0x0070 STB_PRE_SW 0x0090 STRB12_START 0x00A0 STRB12 ENDPD 0x00BO STRB34 START 0x00CO STRB34 ENDPD Table 1 Local PCI Registers 13 VI DMA BASED CONFIGURATION In the FastFrame 1300 DMA based configuration there is no TriMedia or PMC secondary PCl bus Captured data is sent via DMA to host memory for host processing In this configuration the primary PCI interface supports 64 or 32 Bit 33MHz PCls to allow the highest average PCI throughput to the host A DMA Features
39. put extended to four positions The biggest difference between the FastFrame 1300 and Alacron s Fastlmage 1300 connectors is in the Camera Link pin out Rather than having a separate J2 connector Camera link signals replace digital input signals on the FastFrame 1300 J1A B connector The FastFrame 1300 has a new straightforward pin out configuration The RS 232 interfaces are optional and replace GPIN pins when they are used The LVDS TTL Fast Channel connectors use the same connectors and pin out as Alacron s Fastlmage 1300 However control of their direction and enables have changed A Headers and Jumpers Conn Use Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 P1 Aux 3 3VDC in GND GND 5 0VDC in N A Power P2 LED Test LEDO1 LEDO3 LEDO04 LEDO9 LED10 GND Points P3 Xilinx TRST TCK TMS TDI TDO GND JTAG P4 TM1300 Jumper 1 2 for Write N C Jumper 5 6 for Default EEProm Enable no EEProm P5 TM1300 TRST TCK TMS TDI TDO GND JTAG P6 J1A B Jumper 1 2 to N C Jumper 5 6 to Term Ena terminate Taps 1 amp 2 terminate Taps 3 amp 4 Table 8 FastFrame 1300 Headers and Jumpers 24 B VHDCI Connectors The pin out of the FastFrame 1300 dual 68 pin VHDCI connector is shown in Table 9 on the next page 25 1A Pinout Diqin Pin AnalogPin Cam LinkPin Ti vas PP mvae 0 p TH EVAL PPT PP IGND IDiginPin AnalogPin Cam Link Pin
40. r 4 analog CVBS or Y C inputs Each of these input channels can come from one of four 4 CVBS or two 2 Y C input sources for a total of sixteen 16 possible analog inputs The inputs are terminated into 75 ohms and A C coupled to a Philips SAA7111A video decoder All four SAA7111A decoders on the FastFrame 1300 provide 8 bit CCIR 656 style data or two of them can be configured to generate RGB format data which is multiplexed into a 16 bit data bus This bus can then be de multiplexed into three 3 8 bit channels by the front end FPGA The SAA7111As are configured by lC from the PMC J4 connector directly or from the on board TriMedia processor Since the SAA7111As respond to a single address only the on board FPGA is used to select which SAA7111A device the TriMedia communicates with Alacron analog input cable 10024 00162 is used with this type of input setup B Digital RS 422 The FastFrame1300 board supports up to 32 bits of RS 422 format digital input data The data can be in the form of four 4 individual 8 bit TAPs two 2 16 bit TAPs one 1 32 bit TAP or a Suitable combination The data can then be assembled into the desired format by the front end FPGA Each of the possible TAPs has individual clock frame valid and line valid inputs On board 100o0hm termination is provided for RS 422 inputs Alacron digital input cable P N 10024 00161 or 10024 00224 is used with this type of input setup C Digital LVDS RS 6
41. ram Each of the four DMA engines has two target address and DMA length control registers for double buffering The length control registers provide status bits Error Done and the count remaining in the transfer The Error field will indicate the type of PCI error that was encountered if any 15 ZHWee 410 10d DMA_ID_STATUS RSVD ID 7 0 ANY ERROR ANY BUSY ANY DONE CLK SEL 2 0 BRST_LEN 3 0 LED 5 0 INT ENA Int 1 Int 0 FE_CONFIG download CS EN CCLK PROG DONE R INIT R RSVD ONE R O R O RW RW R W FE CONTROL RSVD TBD MSG PASS CAPTURE ON REG R W REG 4 REG DATA 16 FE SDRAM SEG RSVD SDRAM SEGMENT 15 Bits 00 UART I2C DO UART UART UART DO PC 3 EC lC R W UART RW ADDR 4 DATA 8 C ADDR 7 c DATA 8 GPIO REG RSVD GPIN 3 0 R O GPOUT 3 0 R W STB CTL STB3 RSVD Nc STB4ENA STB4POL STB3ENA STB3POL EDGE3 amp 4 TRG_SRC 4 3 STB1 FONG STB2ENA STB2POL STB1ENA STB1POL EDGE182 TRG_SRC 2 1 STB PRE SW RSVD SW TRIG3 amp 4 SW TRIG1 amp 2 PRESCALE 11 Bits STRB12 START ST2 START 16 Bits ST1 END 16 Bits STRB12 ENDPD ST12 PERIOD 16 Bits ST2 END 16 Bits STRB34 START 5 4 START 16 Bits
42. ss fashion Data can be transformed or compacted before going off board Via the PCI bus to the PMC site via PCI or Fast Channel or in the PCI version of the board via an optional LVDS Fast Channel connector The TriMedia based version of FastFrame 1300 supports a 32 bit PCI bus interface B PCI Bridging Logic In the TriMedia based FastFrame 1300 both the processor and an optional device found on the PMC site are accessible from the host PCI bus This accessibility is provided by PCI bridging logic in the PCI FPGA The on board PCI bridge is designed to function as a non transparent PCI bridge Thus it does NOT respond to Type 1 configuration cycles It only responds to Type 0 cycles to the bridge device itself The Fast Frame 1300 device appears to the host as a single PCI device with memory windows These windows must be configured to be large enough to allow host access to all devices behind the FastFrame 1300 PCI bridge Downstream configuration cycles to PCI devices on the backside of this bridge are supported via configuration registers The PCI Bridge supported features are listed in Section V C DMA Based Capture In Direct Memory Access based capture the captured video data is simply buffered or possibly packed and made available to a PCI host based processing engine This version of the FastFrame 1300 supports 32 and 64 bit PCI interfaces 33MHz Captured data is sent via DMA to a buffer in host memory where it is processed
43. ten we can devise a work around that allows you to move forward with your project while we continue to work on the problem you ve encountered It is important that we are able to reproduce your error in an isolated test case You can help if you create a stand alone code module that is isolated from your application and yet clearly demonstrates the anomaly or flaw Describe the error that occurs with the particular code module and email the file to us at support alacron com We will compile and run the module to track down the anomaly you ve found If you do not have Internet access or if it is inconvenient for you to get to access copy the code to a disk describe the error and mail the disk to Technical Support at the Alacron address below If the code is small enough you can also FAX the code module to us at 603 891 2745 If you are faxing the code write everything large and legibly and remember to include your description of the error When you are describing a software problem include revision numbers of all associated software For documentation errors photocopy the passages in question mark on the page the number and title of the manual and either FAX or mail the photocopy to Alacron Remember to include the name and telephone number of the person we should contact if we have questions Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Telephone 603 891 2750 Fax 603 891 2745 Web site http
44. upts from the various devices on the FastFrame 1300 board are connected as shown below PMC Site A C 2 gt A 2 S 8 e g 5 PCI FPGA C o C x D LED y Figure 6 Interrupt Connections e This configuration allows flexible connection between host PMC and TriMedia interrupt sources open drain and handlers via the PCI FPGA e The TriMedia interrupt D pin is also connected to an LED for debugging purposes 21 X FASTCHANNEL CONTROL Alacron s Fast Channel is a mechanism for Alacron s FastSeries components like those found on the FastFrame 1300 to communicate with the processing environment without impacting the PCI bus When implemented within a high performance DSP or imaging application the bus form of data transfer can be subject to bus saturation and contention However point to point communication directly from the data source to the data sink with each interconnection supporting its own data transfer isolated from any other data transfer can prevent such contention and bus saturation Fast Channel is Alacron s implementation of a point to point or point to many points connection between a data source and its data sinks Fast Channel is a cost effective interconnects solution It is configurable at startup and no special hardware is needed for source and destination addresses arbitration or control of the channel Simple soft
45. ware protocols can be implemented because the only operation allowed is the transfer of one word of data The Fast Channel is composed of a parallel data path from 1 to 32 bits a clock and a data valid Specifications will vary with environment and usage An input data rate of 320 MB or anything over 133 MB is too high for transfer over the PCI bus but it can be transferred over the Fast Channel at 80 MHz with the additional benefits of isolating the transfer from the host CPU and without impacting PCI activity In data intensive applications Fast Channel s higher bandwidth will provide significant user savings over using the PCI bus even if additional CPUs and cameras are installed to achieve the higher rates the Fast Channel is designed to handle The FastFrame 1300 configuration allows 8 bit granularity in data path direction The byte lane and control signals are configured via C address 0x40 and 0x42 using a Philips PCF8575 device These registers also control which clock signals are connected to the Fast Channel The control registers are implemented in two IC devices Each device provides 16 control bits that can be written or read via lC All register bits power up as 1 effectively disabling all active low signals The control bits are defined starting on the next page Writes to either device must be done as a single multi byte write Reads can be either single or multi byte depending on whether the first 8 or all 1
46. y other transactions other than Delayed Write Completion are accepted e Since the bridge has only single transaction pipelines transactions on either side are accepted in the order they are presented with the exception of Posted Writes Posted memory Writes The bridge accepts burst write data into a 256 byte 64 data phases buffer without wait states until the buffer is full or a cache line boundary is crossed i e 4 8 16 or 32 D words per configuration space The bridge responds with Target Disconnect if the buffer is filled The bridge accepts only ONE posted write transaction up to 256 bytes at a time Once all or at least the CacheLineSize bytes have been written the target write may begin If the target exceeds the max number of retries 27 the transaction is terminated and SERR is asserted if enabled on the initiating bus If the target aborts the transfer SERR is also asserted Memory Write and Invalidate MWI commands are treated the same as MW commands 2 Delayed Writes The bridge treats I O writes and CSR generated configuration writes as single cycle Delayed Writes The sequence of a Delayed Write is as follows The bridge accepts the write address C BEs and data and then terminates the initiator cycle as a Retry The bridge attempts to complete the cycle on the target bus and responds to the initiator with Retry The bridge responds to initiator retry of i
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