SMT374 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. sees ees JTAG VIRTEX Il HEADER CORE VOLTAGE REGULATORS Version 2 2 Virtex Memory Map The memory mapping is as follows define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define DSPA_CPO DSPA CPI DSPA CBZ DSPA CP3 DSPA CP4 DSPA CPS DSPA CPO STAT DSPACP1 STAT DSPA CPZ STAT DSPA CP3 STAT DSPA CP4 STAT DSPA CP5 STAT DSPA GBSTAT DSPA SDBSTAT DSPA STAT DSPA SDBA DSPA SDBA STAT DSPA SDBA INPUTFLAG DSPA SDBA OUTPUTFLAG DSPA SDBB DSPA SDBB STAT DSPA SDBB INPUTEFLAG DSPA SDBB OUTPUTFLAG DSPA SDBC DSPA SDBC STAT DSPA SDBC INPUTFLAG DSPA SDBC OUTPUTFLAG DSPA GLOBAL BUS DSPA GLOBAL BUS CTRL DSPA GLOBAL BUS START DSPA GLOBAL BUS LENGTH DSPA TCLK DSPA TIMCONFIG DSPA LED DSPA TIOF Page 20 of 29 volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned2. Enable TIM TCLK1 as an output If the TIM TCLKx pin is selected as an output the DSP TOUTX signal will be used to drive it The TIM TCLKx pin will always drive the DSP TINPx input The Timer control register is described in the SMT6400 help file Version 2 2 Page 17 of 29 SMT374 User Manual Code Composer This module is fully compatible with the Code Composer Studio debug and development environment This extends to both the software and JTAG debugging hardware The driver to use is the tixds6x1x dvr and each SMT374 should be declared as two DSPs The ROM reprogramming utility SMT6001 requires CCS version 3 0 or later Application Development Depending on the complexity of your application you can develop code for SMT374 modules in several ways SMT6400 For simple applications the Sundance SMT6400 software support package project examples and its associated header files SmtTim h and ModSup h can suffice The SMT6400 product is installed by the Sundance Wizard and it is free of charge 3L Diamond This module is fully supported by 3L Diamond which Sundance recommends for all but the simplest of applications An SMT374 has to be declared in configuration files as two processors of type SMT374 6711 or SMT374 6713 as appropriate SMT6500 This is the support package for the FPGA It may be used to develop your application in the FPGA of the module Version 2 2 Page 18 of 29 SMT374 User Manual Operating Cond
3. input input output input output input DSPA MCBSP DX1 DSPA MCBSP FSR1 Bes Steam DSPA MCBSP FSX1 ia input input output Tech WH input output input DSPB MCBSP DX1 DSPB MCBSP FSR1 PV pep reen DSPB MCBSP FSX1 3 3V ea a is psesme osems EG DSPA GPIOO DSPA GPIO1 WE EC DSPA GPIO2 DSPA GPIO3 24 Version 2 2 Page 24 of 29 SMT374 User Manual SHB generic pin out QSH Pin number QSH Pin number USERDEF2 Note Wis a short for Full Word i e 32 bit Word Hw is a short for Half word i e 16 bit Word Version 2 2 Page 25 of 29 SMT374 User Manual SHBA pin out Pin Signal Signal Pin 1 SDBO CLK SDBO DO 2 SDBoDs pp 6 7 SDBoDs Sp 8 Sp SDBoD8 10 SDBO D12 Not implemented Version 2 2 Page 26 of 29 SMT374 User Manual SHBB pin out Pin Signal Signal Pin 1 SDB2 CLK SDB2 DO 2 SDB2D3 Sp 6 7 SDB2 DS Sp 8 _SDB2D7 SDB2D8 10 SDB2_D12 Not implemented Version 2 2 Page 27 of 29 SMT374 User Manual This standard is implemented using SAMTEG QSTRIP 0 50mm Hi speed connectors To improve electrical performances a ground plane is embedded in each QSTRIP connector For long distances micro coax ribbon cable is used to connect 2 QSTRIP connectors An SHB interface can be 8 16 or 32 bit wide FPGA PROG Pin Control JP3 connector PROG asserted Out PROG under control of DSP FPGA JTAG The following shows the pin outs for JP4 FP
4. TIM is connected to the processor s IlIDF3 pin On the SMT374 the CONFIG signal is asserted after power on and can be released by writing the value 1 lt lt 6 to the config register Conversely CONFIG may be re asserted by writing 0 to this bit It is not possible for software to read the state of the CONFIG signal The NMI signal from the TIM connector can be routed to the DSP NMI pin WARNING Several software components include code sequences that assume setting GIE 0 in the DSP CSR will inhibit all interrupts NMI violates that assumption If an NMI occurs during such code sequences it may not be safe to return from the interrupt This may be particularly significant if you are using the compiler s software pipelining facility Each DSP has access to a separate config register Config Register 31 8 7 6 5 0 Field Description drive CONFIG low tri state CONFIG 0 Disconnect NMI from the DSP Connect NMI from TIM to the DSP CONFIG NMI Config and NMI DSP lines are described in the SMT6400 help file Version 2 2 Page 16 of 29 SMT374 User Manual Timer The TIM TCLKO and TCLK1 signals can be routed to the DSP s TOUT TINP pins The signal direction must be specified together with the routing information in the timer control register Timer Control Register 31 6 5 4 3 0 Field Description TIM TCLKO i TCLKO CLKO is an input Enable TIM TCLKO as an output TIM TCLK i TOLK 0 C is an input
5. a firmware upgrade If LED D6 on the SMT374 remains illuminated once the TIM is plugged in and powered up the SMT327 needs the upgrade The latest firmware is supplied with all new boards shipped Please contact Sundance directly if you have an older board and need the upgrade The external ambient temperature must remain between 0 C and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I O activity The maximum power consumption is 6W Version 2 2 Page 19 of 29 SMT374 User Manual Connector Positions SHB pan terre ere ere ere e e LE E E E E E re SJETTE eee Zgggegegeggegegeeeeggegeggeggg KEKEKEKKEKKEEEKEKEKKEEEKEKKEKEKKE Seege gegegegeeeeegegegeeegeegg S eeeeeeeegeegeeeeeeeeeeeeegeeege ggegegegegegeeeeegegegeegeggeeeg KEKEKEKEKKKKEEEEKKEKKEKEEEKEKEKEEKEKAKE zeeeeeegegeeegeeeeggegeeeeseegege SSL SJOA te 0040 ee eeeestoese eee tertee LE E E E E eee verte tte ree SEE ree ss tetee KEE GPIO ssssseeedesssessse McBSP 66000060663406080568 EAD eeeeeee eee CRW H ER none eee 9000 SHS HEHEHESEHE HES ee de r ss ee tees EERE BS TITT UIT eeee eee eee RR nt TTT TTT ee e LA JJ eee LA JE e eseee TE eee eee eee eee CRW
6. unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned LE int LE INE int int int LAL LNE inr LE LAT IE Ine int int int int int LME LME LE LE INE int int ADE int int int int int Int LTE LNE SMT374 User Manual 0xB0000000 0xB0008000 OxBOO10000 0xBO0018000 0xB0020000 0xB0028000 0xB0004000 0xBO00CO00 0xBO014000 UXBOOLEO000 0xB0024000 0xB002C000 0xB0034000 0xB0038000 OBO O3COO0 OxBOO40000 0xB0048000 0xB0044000 0OxBO04C000 0xBO0050000 sI OXB0056000 0xB0054000 0xBO005C000 0xB0060000 0xB0068000 0xB0064000 0xB006C000 0OxBOOA0000 0xB0080000 0xB0088000 0xB0090000 QxBOOCO000 OxBOOC8000 OxBOODOOOO 0xBO0D8000 Version 2 2 define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define DSPA_INTCTRL4 DSPA SDBINTCTRL4 DSPA INTECTRES DSPA SDBINTCTRL5 DSPA INTCTRL6 DSPA SDBINTCTRL6 DSPA
7. 00030 SDRAM 128MB SDRAM 128MB 0x80000000 0x87FFFFFF OxFFFFFF23 Flash 8MB Virtex 2KB 0x90000000 0x901FFFFF divided in DPRAM with the 4x2MB pages Virtex CE2 0x00100020 Control I register SS 0xA0000000 0xA0000010 CE3 0x00000030 0xB0000000 0xB7FFFFFF SDRAM Memory spaces CEO are used to access 128MB of SDRAM over the EMIF The speed of the SDRAM is dependent on the processor variant Using the C6x11 the SDRAM will operate at 100MHz Using the C6713 the SDRAM operates at a programmable rate up to the maximum allowed on the EMIF TI data sheet TBD The EMIF CEO amp CE3 memory space control registers should be programmed with the value 0x00000030 FLASH An 8MB Flash ROM is connected to DSP A in the EMIF CE1 memory space It cannot be accessed by DSP B The ROM holds boot code for the DSP configuration data for the FPGA and optional user defined code A software protection algorithm is in place to prevent programs accidentally altering the ROM s contents Please contact Sundance for further information about re programming this device The CE1 memory space control register should be programmed with the value OxFFFFFF23 This is the same value for DSP B even though this DSP does not have access to the flash When DSP B accesses memory on CE1 the Virtex will respond with data within its internal dual port RAM using the standard Sundance Virtex configuration 1 To Be Defined Version
8. 11 integer processors running at 150MHz TMS320C6711 floating point processors running at 150MHz TMS320C6713 floating point processors running at 225MHz TMS320C6713 300 floating point processors running at 300MHz Six 20MB s external communication ports Comports 256MB of SDRAM 100MHz 128MB per DSP 8MB Flash ROM Global Bus connector Do O 0 0 UU UO 0 2 SHB connectors for high speed data transfer Intended Audience There are two existing versions of the firmware for the SMT374 These two versions differ by the number and the type of communication resources comport and SDB interfaces provided For each of the versions of the different firmware is loaded in the FPGA Firmware version 1 8 or Firmware version 2 0 This user manual covers the version 2 0 of the firmware for the SMT374 implemented with the model described in the SMT6500 help file The changes between the firmware version 1 8 and version 2 0 are described in the section Firmware versions Version 2 2 Page 7 of 29 SMT374 User Manual Block Diagram The following drawing shows the block diagram of the SMT374 module The main components of the SM1 374 are Two Texas Instruments DSPs One Xilinx FPGA Virtex Il device 256MB of SDRAM Linear regulators for DSP and FPGA cores J1 TOP Primary TIM connector Comport 0 amp 3 Timer amp Control 15 I O pins FPGA Controller Virtex l XC2V2000 FF896 516 I O p
9. 2 2 Page 11 of 29 SMT374 User Manual FPGA The FPGA Field Programmable Gate Array is a Xilinx Virtex Il device It implements the following communication resources e Six comport interfaces e Two 32 bit Sundance digital bus interfaces e One global bus interface Version control Revision numbers for both the boot code and FPGA firmware are stored in the Flash ROM during programming as zero terminated ASCII strings The SMT6001 utility can be used to display the version numbers of the bootloader and the FPGA data Firmware versions The SMT6001 utility includes the latest version of the bootloader and the latest version of the FPGA data that implements the FPGA architecture described in the SMT6500 help file Note that the new firmware does not support the DSPA SWITCH only two 32 bit SDB interfaces are presented on the TIM connectors and their configuration is fixed The configuration of the six internal comports is also fixed Customers whom wish to use the old firmware that supported the 16 bit options and the DSPA SWITCH can obtain it from our support web forum Reprogramming the firmware and boot code The contents of the flash ROM are managed using the SMT6001 utility This includes the latest firmware and bootloader along with complete documentation on how to reprogram the ROM The utility assumes that you have Code Composer Studio installed and that it has been configured correctly for the installed TIMs The Sundance Wi
10. B Block Diagram 7 Board Control Registers 9 Board not working firmware version numbers I I Boot Mode 8 C Code Composer 17 Comports 12 CONFIG amp NMI 15 Connector Pin outs 23 Connector Positions 19 Contacting Sundance 4 D Data Sheets 28 Diamond 17 DPRAM 9 DSPs 8 E EMIF Control Registers 9 F Firmware versions 11 Flash 10 FPGA 10 G Global Bus 14 Page 29 of 29 SMT374 User Manual Index L LEDs 14 memory space CEO to CE3 9 N Notational Conventions 5 O Operating Conditions 18 P Power Consumption 18 R Register Descriptions 5 Reprogramming 11 revision numbers boot code I I FPGA firmware 11 S SDRAM 10 SHB 13 SMT6400 17 SMT6500 17 T Table of Contents 3 Timer 16 V Version Control 11 Virtex Memory Map 20
11. ENECGER DSPA_SDBINTCTRL DSPA DPRAM DSPE LP DSPB CP 1 DSPB CP2 DSPB CPS DSPB CP4 DSPB CPS DSEB POSTAT DSPB CP1_ STAT DSPB CPZ STAT DSPB CPS STAT DSPB CP4 5STAT DSPB CPS SAT DSPB STAT DSPB_SDBSTAT DSPB_SDBA DSPB_SDBA_STAT DSPB SDBA INPUTFLAG DSPB SDBA OUTPUTFLAG PSPP SDBB DSPB SDBB STAT DSPB SDBB INPUTFLAG PDSPB 5SDPBB OUITPULF LAG ENEE ODBC DSPB SDBC STAT DSPB SDBC INPUTFLAG DSPB SDBC OUTPUTFLAG DSPB TCLK DSPB TIMCONFIG DSPB LED Page 21 of 29 volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned int int LE int LE INE LE int int int NE NE LE LE LE Ine ie int int int int int rnt LME LE INE INE int Te int int int int int int Int Int INE SM
12. GA JTAG connector 1 2 3 4 5 6 The JTAG chain includes the FPGA and the CPLD XC9636XL Version 2 2 Page 28 of 29 SMT374 User Manual Data Sheets Hyperlinks 8 d Sundance help file TMS320C6201 C6701 Peripherals Reference Guide literature number SPRU190 It describes the common peripherals available on the TMS320C6201 C6701 digital signal processors This book includes information on the internal data and program memories the external memory interface EMIF the host port multichannel buffered serial ports direct memory access DMA clocking and phase locked loop PLL and the power down modes OMT6400 help file and SMT6500 help file TIM 40 MODULE SPECIFICATION Including TMS320C44 Addendum SDB Technical Specification SHB Technical Specification TMS320C4x User s Guide literature number SPRU063 It describes the C4x 32 bit floating point processor developed for digital signal processing as well as parallel processing applications Covered are its architecture internal register structure instruction set pipeline specifications and operation of its six DMA channels and six communication ports Software and hardware applications are included Xilinx Virtex Il data sheet Texas Instruments TMS320C6211B data sheet 10 Texas Instruments TMS320C6711 data sheet 11 Texas Instruments TMS320C6713 data sheet Version 2 2 A Application Development 17 Architecture 13 Architecture Description 8
13. SMIT 374 User Manual GAR IK MAMMAL LML M I Certificate Number FM 55022 User Manual QCF42 Version 3 0 5 2 01 Sundance Multiprocessor Technology Ltd 2001 Version 2 2 Page 2 of 29 Revision History Date Comments 07 07 03 DSP named corrected to DSPA and DSPB Comport performances V1 6 of the firmware 06 08 03 Update Comport naming Update reprogramming and external interface switch register to use the SMT6001 software 22 08 03 Clarify EMIF register table i e memory map Links added to firmware description document Version converted to 3 digits number 26 08 03 SDBC memory map corrected 04 02 04 Reference to SMT376 page 26 removed 14 04 04 Update to the external interface switch register to add a warning about dynamic setting in multiprocessor systems 29 09 04 Added address of the DPRAM for each processor 04 08 05 Update the user manual supports the new firmware implementation 18 10 05 Corrected SHB architecture 14 02 06 Minor change SHB architecture 19 07 06 Updates for the SMT374 300 SMT374 User Manual Engineer c lt GP GP lt lt lt lt lt JV J Gesi E lt V SM SM SM EW Version 1 0 0 1 0 1 1 0 1 1 0 3 1 0 4 zech O1 h O 1 0 7 1 0 8 1 0 9 NPN N ES w D Version 2 2 Page 3 of 29 SMT374 User Manual Table of Contents REVISION e TEEN e Tu E 2 ofres leg o
14. T374 User Manual OxBOOEOOOO 0XB00E4000 0XBOOE8000 OxBOOECOOO OxBOOFOOOO OxBOOF4000 0xBO0F8000 0OXxBOOFCOO00 0OxBOOFCOO00 0xBO0000000 0xB0008000 YOXBOO10000 UXBOOL8000 OXBI020000 0xB0028000 0xB0004000 0xBO00CO00 0xBO014000 OXBOOICO00 0xB0024000 0xB002C000 OxBO003C000 ORB 0xB0040000 0xB0048000 0xB0044000 0xBO04C000 0xB0050000 0xB0058000 0xB0054000 0xB005C000 0xB0060000 0xB0068000 0xB0064000 0xB006C000 0xB00C0000 0xBO0C8000 0xBO0D0000 Version 2 2 define define define define define define define define define Fdefin DSPB LIOF DSPB INTCTRIA ER SDBINFCTRLA DoPB INTC TRS HSPE SDBINTETRES DSPB AINE TREG DSPB SPBBINTCTRL6 DSEBe ENDGER LE ER SDBINTCTRE DSPB DPRAM Page 22 of 29 volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned int int LE int LE INE LE int int int SMT374 User Manual 0xB00D8000 OxBOOEOQOOO 0xB00E4000 x yY 0XB00E8000 OxXBOOECOOO OxBOOFOOOO OxBOOF4000 0xBO0F8000 0OXxBOOFCOO00 0x90000000 Version 2 2 Page 23 of 29 SMT374 User Manual Connector Pin outs Serial Ports amp Other DSP 1 0 JP2 connector Pin Signal Signal Pin number number
15. ins 1 5V Global Bus 74 I O pins J2 Bottom Primary TIM connector Comport 1 2 4 amp 5 ho d J3 Global Bus connector Version 2 2 Page 8 of 29 SMT374 User Manual Architecture Description DSPs The two Texas Instruments DSPs can run up to 300MHz Each of them is doted of 128MB of Synchronous DRAM SDRAM The DSPs can be of two types e TMS320C6211 or C6711 This is a fixed point digital signal processor provided by Texas Instruments The processor will run with zero wait states from internal SRAM The internal memory is 64KB in size and can be partitioned between normal SRAM and L2 cache 37 5MHz on board crystal oscillator provides the clock used for the DSP which then multiplies this by four internally So the DSPs run at 150MHz e TMS320C6713 The processor will run with zero wait states from internal SRAM The internal memory is 256KB in size and can be partitioned between normal SRAM and L2 cache 37 5MHz on board crystal oscillator provides the clock used for the DSP which then multiplies this by a programmable amount internally to provide the required core and EMIF clocks In this case the DSPs will run at 225MHz e TMS320C6713 300 The processor will run with zero wait states from internal SRAM The internal memory is 256KB in size and can be partitioned between normal SRAM and L2 cache 50MHZ on board crystal oscillator provides
16. itions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to a TIM40 compliant carrier board The SMT374 TIM is in a range of modules that must be supplied with a 3 3V power source In addition to the 5V supply specified in the TIM specification these new generation modules require an additional 3 3V supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3V power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended This module is not directly compatible with earlier generations of TIM motherboards although the 3 3V supply can be provided from a separate source It is however compatible with the latest generation of Sundance TIM carrier boards such as the SMT310Q and subsequent versions PCI and SMT328 VME which present the 3 3V via conductive mounting pillars Use of the TIM on SMT327 cPCI motherboards may require
17. le ESTE go RINGS EN UM 4 Notational Conventions secrete eneen emeente 5 Dn 5 D E E See sdeon ae asian andy ava anoeeeeenaderavessueranaeane soe assees e 5 FE ste 5 He la e A te el este ele sue 5 Outline DESerIDHON 4 6 Tu ET eo EN 6 BIOCK DAMN Lade 7 Architecture DESCHNN NON eege 8 DPS une 8 SONO ME 9 Board Control Registers BCRS cccccccseccceseeeeneeteeeeseeeeseeeesaeeeteaeetseetseetaeeeas 9 DRE aanta deense E RAe 9 EPLENE 9 SEE ennesne sncaneesessense ses eeenese mme 10 RS enen 10 RO E E E E E ES 11 Version Control 11 FENG Le enn 11 Reprogramming the firmware and boot code rrnnvrnnnvvnnnuvnnnuvnnnnnnnnuennnvennnvennnuennn 11 OTN OS EE NE EE EN MS RE 12 RE eee eee eee eee ccc eet 13 eee JE EE EE ETA TT TE 13 GIODA CC 14 EED SENG ect er cence esteen cows E E S eeccedessaccceeeescanees 14 LED Register DSP A annen ennen en venenvenenvenenvenenvenenvenenvenenvenenvenenvenenveneneenen 14 LE REJSO Dn 14 CONFIG amp TE 15 So pl lo RGO IET EEE 15 Version 2 2 Page 4 of 29 SMT374 User Manual Uu E PAPERS eee RE een nes 16 TIME ele gel REJI O 16 Gode CNN 17 Application Development n ranurnnnnnnnvnnnuvnnuvnnnvnnnunnnuennnvnnnvnnnvennnvnnnvnnnvnnnvennnvennnvnnnuen 17 On 17 SE DIMONA EE 17 AV 01010 eege 17 Opera GONdINONS aa aa 18 D ey eeesueneu E E T 18 EM E E 18 General Requirements sise 18 Power GONSUMDUOR DEE 18 Connector EU e esse nan an 19 VITE MEMORY NN 20 Connector GET E 23 Serial Por
18. nfigured to boot from this DPRAM and this leaves both DSPs executing their own copies of the Comport boot procedure The DPRAM is managed by writing to one of the board control registers BCR implemented in a CPLD The BCR bit functions are described in the SMT6001 help file Board Control Registers BCRs DSP A will take approximately 800ms to configure the FPGA following reset assuming a 150MHz clock The external devices implemented in the FPGA such as comports must not be used during this configuration It is safest to wait for the configuration to complete Note that comports will appear to be not ready until the FPGA has been configured The FPGA programming algorithm is not described here It can be found in the boot code DPRAM The DPRAM in the FPGA is only intended to be used during this boot process more general use is not recommended The DPRAM is accessible from the following locations e DSPA has access to the DPRAM from address 0xB0100000 e DSPB has access to the DPRAM from address 0x90000000 EMIF Control Registers The DSP has a single external memory interface EMIF which is 32 bits wide Version 2 2 Page 10 of 29 SMT374 User Manual A full description of the registers used to control the EMIF can be found in the DSP C6000 Peripherals Reference Guide The standard bootstrap will initialise these registers to use the following resources Memory Resource Resource Address range space DSP A DSP B En 0x000
19. the clock used for the DSP which then multiplies this by a programmable amount internally to provide the required core and EMIF clocks In this case the DSPs will run at 300MHz Remark SMT374 300 built before june 2006 may be fitted with a 37 5MHz instead of a 50MHz crystal oscillator The DSPs will then run at 225MHz with the default bootloader The SMT374 300 can be programmed with a special bootloader to make the DSPs run at 300MHz Sundance will provide this special bootloader on demand http support sundance com viewtopic php p 19911 1991 1 Version 2 2 Page 9 of 29 SMT374 User Manual Boot Mode The two DSPs are called DSP A and DSP B DSP A is connected to the on board flash ROM that contains the Sundance bootloader and the FPGA bitstream Following reset DSP A will automatically load the first 1KB from the flash ROM into its internal memory at address 0 and then start executing from there DSP B remains held in reset DSP A now explicitly loads the next 3KB from ROM giving the effect of an initial load of 4KB All this code is the Sundance bootloader and it is made up of three parts FPGA configuration processor configuration and the Comport boot procedure FPGA configuration uses data in the ROM to configure the FPGA Processor configuration sets the processor into a standard state copies its comport boot procedure into a 2KB dual port RAM DPRAM implemented in the FPGA and releases DSP B from reset DSP B is co
20. tion Global bus The SMT374 provides a single global bus interface This is only accessible from DSP A The addresses of the global bus registers are shown in the Virtex Memory Map and are described in the SMT6400 help file LED Setting The SMT374 has 5 LEDs One shows the FPGA configuration status and the other 4 are under DSP control 2 each Two output TTL I O pins are available on connector JP2 for control or debugging Their values can be controlled by bits in the LED register LED D2 always displays the state of the FPGA DONE pin This LED is off when the FPGA is configured DONE 1 and on when it is not configured DONE 0 This LED should go on when the board is first powered up and go off when the FPGA has been successfully programmed this is the standard operation of the boot code resident in the flash memory device If the LED does not light at power on check that you have the mounting pillars and screws fitted properly If it stays on the DSP is not booting correctly or is set to boot in a non standard way LED Register DSP A 0xBO00D0000 31 4 3 2 1 0 ZA it mo uen Leone RW 0 RW 0 RW 0 RW 0 LED Register DSP B OxBOODOO000 31 4 3 2 1 0 DEN ma me ove Les RW 0 RW 0 RW 0 RW 0 Version 2 2 Page 15 of 29 SMT374 User Manual CONFIG amp NMI The TIM specification describes the operation of an open collector type signal CONFIG that is driven low after reset This signal on a standard C4x based
21. ts amp Other DSP I O JP2 connector an oeeneneneen eneen eenen 23 SHB generic PINOUT EO EE 24 FEAT 25 SHBB om ag OL 26 PEGA les ee nu e 27 FF aen 27 Data Sheets Hyperlinks BE 28 INGEN EE 29 Contacting Sundance You can contact Sundance for additional information by login onto the Sundance support forum Version 2 2 Page 5 of 29 SMT374 User Manual Notational Conventions DSP The term DSP will be used throughout this document in place of TMS320C6211 6711 or 6713 SDB The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface SHB The term SHB will be used throughout this document to refer to the Sundance High speed Bus interface Register Descriptions The format of registers is described using diagrams of the following form 31 24 23 16 15 8 7 0 H 00000000 RW 10000000 R 00000000 R 10000000 The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after reset Shaded fields are reserved and should only ever be written with zeroes R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset Version 2 2 Page 6 of 29 SMT374 User Manual Outline Description The SMT374 is a dual DSP size 1 TIM offering the following features TMS320C62
22. zard can help you with this Version 2 2 Page 12 of 29 SMT374 User Manual As DSP B has no connection to the ROM the programming must be done using DSP A To confirm that the ROM has been programmed correctly you should run the confidence test in the Boardinfo utility SMT6300 Comports Both DSP A and DSP B have six Comports numbered 0 to 5 Each DSP has three Comports connected to the other DSP and three connected to the TIM connectors as shown in the following diagram 3 0 4 1 5 2 The addresses of the Comport registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Version 2 2 Page 13 of 29 SMT374 User Manual SHB The SMT374 has two SHB connectors These interfaces operate with a fixed clock rate of 100MHz Architecture SDBO on DSP A and SDB1 on DSP B are presented on the TIM s SHB connectors SHBA and SHBB respectively SDB2 of DSP A has a fixed internal connection to SDB2 of DSP B gt W Co UJ W L OD Version 2 2 Page 14 of 29 SMT374 User Manual The addresses of the SDB registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Note that Tl s C6713 processors are unable to move data fast enough to use the full bandwidth of 32 bit SDBs Observed maximum transfer rates using EDMA are 340MB s internal memory and 130MB s external memory TI claims a potential bandwidth of 400MB s This is currently under investiga
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