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1. Taw nom _coarse coarse_bandwidth_code 3 0 min typ max MHz MHz MHz 0000 3 948 5 6 050 0001 5 527 7 8 470 0010 7 896 10 12 100 0011 11 054 14 16 940 0100 15 792 20 24 200 0101 22 109 28 33 880 0110 31 584 40 48 400 0111 39 480 50 60 500 1000 56 851 72 87 120 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HmawzsLPsE MICROWAVE CORPORATION v01 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Table 12 Calibration Code Look up Table fine tune ratio fine bandwidth code 3 0 min typ max MHz MHz MHz MHz MHz MHz 0000 0 790 0 803 0 818 0001 0 818 0 832 0 846 0010 0 846 0 862 0 878 0011 0 878 0 893 0 909 0100 0 909 0 926 0 943 0101 0 943 0 959 0 976 0110 0 976 0 994 1 012 0111 1 012 1 030 1 048 1000 1 048 1 063 1 078 1001 1 078 1 097 1 116 1010 1 116 1 136 1 155 1011 1 155 1 183 1 210 To reprogram the HMC1023LP5E to any other bandwidth simply repeat the steps above Filter Bandwidth Setting After Calibration In cases where ctune is unknown but the calibrated and programmed bandwidth is known it is possible to estimate the value of ctune based on the values of Coarse Bandwi
2. N lt u nuwctozasipse MICROWAVE CORPORATION vo01 0113 RoHSv 72 MHz DUAL PROGRAMMABLE E LOW PASS FILTER WITH DRIVER Evaluation PCB El Del et 1X 72 UJ 26 17 19 29 IR Yy e The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Table 7 Evaluation Order Information Item Contents Part Number HMC1023LP5E Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKITO1 HMC1023LP5E CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Sttite uwctozaspse MICROWAVE CORPORATION 1 0113 ROHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Evaluation PCB Schematic To view Evaluation PCB Schematic please visit www hittite com and choose HMC1
3. lt QD LLI Q A Z lt N lt uL nuwctozsipse MICROWAVE CORPORATION 101 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY 3 HMC1023LP5E registers the data bits D23 DO on the next 23 rising edges of SCK total of 24 data bits 4 Host places the 5 register address bits A4 A0 on the next 5 falling edges of SCK MSB to LSB while the HMC1023LP5E reads the address bits on the corresponding rising edge of SCK 5 Host places the chip address bits CA2 CA0 101 on the next falling edges of SCK MSB to LSB Note the HMC1023LP5E chip address is fixed as 5d or 101b 6 SEN goes from low to high after the 32nd rising edge of SCK This completes the WRITE cycle 7 HMC1023LP5E also exports data back on the Serial Data Out SDO line For details see the section on READ operation Serial Port READ Operation The Read data is available on SDO line This line itself is tri stated when the device is not being addressed However when the device is active and has been addressed by the SPI the HMC1023LP5E controls the SDO line and exports data on this line during the next SPI cycle HMC1023LP5E changes the data to the host on the rising edge of SCK and the host reads the data from HMC1023LP5E on the falling edge A typical READ cycle is shown in Figure 38 Read cycle is 32 clock cycles long To specifically read a register the
4. NP ES 4 50 gt 400 s amp E 0 Sige LT cuerda 200 5 72 MHz Bandwidth Setting o E Filter Bypassed x opas 100 n iar 1 10 100 1000 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz 10000 4000 1000 11 and OIP2 measured from 100 differential source into 400 differential load Used recommended OpAmp bias settings Reg 02h 1 0 in Table 9 OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 lt QD LLI Q O A m 2 lt N lt uL EJ Hittite MICROWAVE CORPORATION 1 0113 RoHS EARTH FRIENDLY Table 3 Absolute Maximum Ratings Nominal 5V Supply to GND Range VDDCAL VDDI VDDQ VDDBG 0 3 to 5 5 V DVDD Common Mode Inputs Pins CMI CMQ 0 3 to 5 5 V Input and Output Pins IIP IIN IQP IQN OIP OIN OQP 0 3 to 5 5 V OQN Digital Pins SEN SDI SCK SDO CALCK 0 3 to 5 5 V SDO min load impedance 1kO Operating Ambient Temperature 40 to 85 C Storage Temperature 65 to 150 C Maximum Junction Temperature 150 C Thermal Res
5. EARTH FRIENDLY Outline Drawing TOP VIEW BOTTOM VIEW PATTERN Table 5 Package Information 3201 5 10 016 0 40 REF m 1193 4 90 7 008 0 20 1 1 gt 52 25 0D E UUUUUUD 1 24 UE L3 CI L1 CN pt PIN 1 a H1023 eq Z PAE QD XXXX z _ 022 0 56 E H 017 0 44 T L1 Cy 8 17 15 lt T O annnnnrn 9 16 LOT NUMBER L338 388 sone e 039 1 00 m 031 0 80 NOTES 002 0 05 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC e 000 0 00 SILICA AND SILICON IMPREGNATED 2 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY i HHHHHHH v SEATING 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN lt PLANE 4 DIMENSIONS ARE IN INCHES MILLIMETERS C 003 0 08 C C 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15mm PAD BURR HEIGHT SHALL BE 0 25m MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05mm dp 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GOUND lt 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND LL Part Number Package Body Material Lead Finish MSL Rating Package Marking 121 HMC1023LP5E RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 E 1 Max peak reflow temperature of 260 C 2
6. 10 RegO2h 1 0 01 Figure 21 Output IP2 vs Output Common Mode Voltage 50 MHz Input i9 80 70 60 50 OUTPUT IP2 dBm 40 COMMON MODE VOLTAGE V RegO2h 1 0 00 RegO2h 1 0 10 Reg02h 1 0 01 Figure 23 Output IP2 vs Output Common Mode Voltage 70 MHz Input 191 60 50 OUTPUT IP2 dBm 40 JJ COMMON MODE VOLTAGE V RegO2h 1 0 00 Reg02h 1 0 10 RegO2h 1 0 01 HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 20 Output IP3 vs Output Common Mode Voltage 50 MHz Input 19 50 40 30 20 OUTPUT IP3 dBm COMMON MODE VOLTAGE V Reg02h 1 0 00 RegO02h 1 0 10 RegO2h 1 0 01 Figure 22 Output IP3 vs Output Common Mode Voltage 70 MHz Input I9 50 40 30 20 UD ote eee ets OUTPUT IP3 dBm COMMON MODE VOLTAGE V RegO02h 1 0 00 RegO2h 1 0 10 Reg02h 1 0 01 Figure 24 In band Output IP3 amp Output IP2 vs Filter Bandwidth amp Impedance 110 90 Internal Input Impedance Setting OUTPUT IP3 dBm edi LAdLNO 5 7 10 14 20 28 40 50 72 FILTER BANDWIDTH MHz 1000 0 400 0 1000 9 72 MHz Filter Bandwidth selected OIP3 and OIP2 measured from 100 O differential source into 400 O differential load OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows IPx d
7. 4 Digit lot number XXXX For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER E Hittite MICROWAVE CORPORATION v01 0113 RoHS v EARTH FRIENDLY Table 6 Pin Descriptions Pin Number Function Description Interface Schematic The pins are not connected internally however all data H 1 3 8 10 N C shown herein was measured with these pins connected to 17 24 25 32 RF DC ground externally dp Quadrature Q Channel 5V Supply 4 YEO Must be locally decoupled to GND owm JE 5 CMQ Quadrature Q channel output common mode level LLI VDD iti i i i a 6 7 Quadrature channel positive and negative differential pro or au outputs EN Z vob T 11 CALCK Calibration clock input CALCK O T rL aa VDD r1 pe SDI LL 12 14 15 SCK SDI SEN SPI Data clock data input and enable respectively OT VDD 13 SDO SPI Data Output 4 0 500 16 DVDD Digital 5V Supply Must be locally decoupled to GND VDD s _ mE 18 19 OIN OIP Inphase I channel negative and positive differential pr oon ou
8. 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L nuwetozsipse MICROWAVE CORPORATION 1 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY b program the measurement adjustment setting Reg 06h c program the threshold adjustment settings 3 enable BIST mode Reg OEh 4 start the BIST by writing any data to the BIST strobe register Reg 04h Note that the BIST will take 2 8 260k clock cycles to complete 5 read the result of the BIST test Read the value in the BIST Out register Reg OF Bit 16 is the busy flag and will be set when the BIST is still running When this bit is reset then the BIST output value in bits 15 0 are valid Note that the value of the BIST output must be compared to the expected result depending on values programmed into the registers in step 2 The BIST procedure can be repeated as desired to ensure adequate test coverage for the RC Calibration engine The suggested register settings to maximize test coverage with BIST is provided below Table 14 Test Conditions Register Settings Expected Result Reg 05h 14 0 265 Reg 06h 8 0 2255 Reg10h 4 0 to eg1Ah 4 0 0d or Oh Reg OFh 15 0 36092 Reg 09h 23 0 14942167 Reg 05h 14 0 232702 Reg 06
9. SEN from Master SCK from Master SDI from Master SDO from Master Figure 38 SPI Timing Diagram Table 13 Main SPI Timing Characteristics DVDD 5V 5 GND 0V Parameter Conditions Min Typ Max Units ty SDI to SCK Setup Time 8 nsec to SDI to SCK Hold Time 8 nsec tg SCK High Duration 18 10 nsec t4 SCK Low Duration 10 nsec t5 SEN Low Duration 20 nsec te SEN High Duration 20 nsec t7 SCK to SEN Ib 8 nsec tg SCK to SDO Out 8 nsec a The SPI is relative insensitive to the duty cycle of SCK b SEN must rise after the 32nd falling edge of SCK but before the next rising SCK edge If SCK is shared amongst several devices this timing must be respected c Typical load to SDO 10pF max 20pF Built In Self Test RC BIST The HMC1023LP5E RC Calibration state machine features built in self test RC BIST to facilitate improved device testing The RC BIST can be exercised as follows 1 Apply reset to the chip via a power cycle hard reset or via the SPI soft reset Soft reset is accomplished by writing Reg 00h 20h followed by writing Reg 00h Oh 2 Setup the RCCAL input parameters if desired Note that the RC BIST will work with the default settings from power up however test coverage will improve if the following SPI registers are also accessed a program the RC clock period Reg 05h For price delivery and to place orders Hittite Microwave Corporation
10. address of that register must be written to dedicated Reg OOh This requires two full cycles one to write the required address and a 2nd to retrieve the data A read cycle can then be initiated as follows 1 The host sets SEN line low followed by a rising edge SCK 2 HMC1023LP5E reads SDI MSB first on the 1 rising edge of SCK after SEN is set low 3 HMC1023LP5E registers the data bits in the next 23 rising edges of SCK total of 24 data bits The LSBs of the data bits represent the address of the register that is intended to be read 4 Host places the 5 register address bits on the next 5 falling edges of SCK MSB to LSB while the HMC1023LP5E reads the address bits on the corresponding rising edge of SCK For a read operation this is 00000 b 5 Host places the 3 chip address bits lt 101 gt on the next 3 falling edges of SCK MSB to LSB Note the HMC1023LP5E chip address is fixed as 5d or 101b 6 SEN goes from low to high after the 32 rising edge of SCK This completes the first portion of the READ cycle in which the address of the register to be read on the next Read Write cycle is written to Reg 00h 7 The host sets SEN line low followed by a rising edge SCK 8 HMC1023LP5E places the 24 data bits 5 address bits and 3 Chip ID bits on the SDO on each rising edge of the SCK commencing with the first rising edge beginning with MSB 9 The host sets SEN line high after reading the 32 bits from the SDO o
11. by linearity Output IP2 and Output IP3 and bandwidth accuracy it is recommended to use OpAmp bias settings Reg O2h 1 0 outlined in Table 9 Table 9 shows that higher OpAmp bias setting and thereby higher current consumption is required to maintain maximum linearity performance as well as bandwidth accuracy 2 596 bandwidth error at bandwidth settings 2 10 MHz Figure 12 to Figure 23 show the effect of OpAmp bias setting Reg 02h 1 0 on linearity OIP2 and OIP3 performance of the HMC1023LP5E Table 9 HMC1023LP5E Bias Table Coarse Recommended Bandwidth OpAmp Bias HMC1023LP5E Coarse Bandwidth MHz GE Setting For Best Typical Current Reg 02h en Performance Consumption mA ease Reg 02h 1 0 0000 00 172 7 0001 00 172 10 0010 00 172 14 0011 01 227 20 0100 01 227 28 0101 01 227 40 0110 01 227 50 0111 01 227 72 1000 10 260 Figure 12 to Figure 23 show that the higher OpAmp bias setting typically increases linearity OIP3 amp OIP2 by 5 to 10 dB at high bandwidth setting However they also show that the HMC1023LP5E maintains excellent linearity performance 60 dBm OIP2 amp 30 dBm OIP3 even at minimum OpAmp bias setting Reg 02h 1 0 0 Figure 35 shows typical calibrated filter bandwidth error accuracy vs OpAmp bias setting Reg O2h 1 0 It shows that higher OpAmp bias is required at filter bandwidth settings gt 10 MHz in order to achieve lt 2 5 bandwidth accur
12. code 3 0 4 0000 23 4 unused For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION 101 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Table 20 Reg 04h Calibration RC BIST Strobe Calibration strobe register is used only to initialize a calibration cycle Writing any value to this register serves to request a new calibration cycle Note that this register is also used to start the Built In Self Test RC BIST mode and this is used to test the fault coverage of the RC calibration engine Bit Name Width Default Description 23 0 Request calibration 1 0 Writing to any bit in this register starts a calibration cycle Table 21 Reg 05h Clk Period Bit Name Width Default Description Sets the clock period for the RC calibration circuit Clock period entered is in 14 0 clock_period 14 0 15 0000h pico seconds i e 1 40 MHz clock 25000ps 110000110101000b 61A8h 23 15 unused Table 22 Reg 06h Measure Adjust Correction value used to adjust RC Calibration result Value is in 1 024ns increments Bit Name Width Default Description Correction v
13. half scale tones at 2fc and 3fc Output IP3 out of band NE ls m 5 fc 72 MHz 17 20 dBm half scale tones at 0 8fc and Output IP2 inband pen oe ele E m fe 72 MHz 21 55 60 dBm For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt T lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q A Z lt N lt uL nwctozu ese MICROWAVE CORPORATION 1 0113 Bone 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Electrical Specifications TA 25 C Continued Parameter Conditions Min Typ Units Output IP2 out of band 60 65 dBm Sideband Suppression Uncalibrated ibd e em at 35 45 dB Channel Balance magnitude 0 04 dB phase 0 5 9 Channel Isolation 60 80 dB Analog I O Differential Input Impedance Programmable Q Full Scale Differential Input min gain 2 Vppd 400 Differential Load max gain 0 613 Vppd Full Scale Differential Input min gain 0 5 Vppd 100 Differential Load max gain 0 156 Vppd Input Common Mode Voltage Range 1 4 V
14. 0 20 FREQUENCY MHz FREQUENCY MHz S Mi 20 40C 25C 85C 10 MHz 50 MHz 14 MHz 72 MHz 20 MHz Bypass Figure 5 Noise Figure 100 Source Figure 6 Noise Figure 1 kO Source Impedance 1 Impedance Selected 21 Impedance 1 Impedance Selected 21 26 24 T T Rc V dB Gain NOISE FIGURE dB NOISE FIGURE dB 5 7 10 14 20 28 40 50 72 5 7 10 14 20 28 40 50 72 FILTER BANDWIDTH MHz FILTER BANDWIDTH MHz 40C 25 85 1 Degrated stop band rejection at frequencies gt 100 MHz caused by the test fixture 2 1 input impedance into the HMC1023LP5E selected by writing Reg 02h 10 0 and Reg 01h 9 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A 2 lt N lt uL EJ Hittite MICROWAVE CORPORATION v01 0113 RoHS EARTH FRIENDLY Figure 7 Noise Figure 1 Source Impedance 100 Impedance Selected NOISE FIGURE dB 5 mA 10 14 20 28 40 50 72 FILTER BANDWIDTH MHz 40C 25 85 Figure 9 Uncalibrated Sideband Rejection 0 dB Gain 60 55 Internal Input Impedance S
15. 023LP5E from the Search by Part Number pull down menu to view the product splash page Evaluation Setup Agilent E3630A Power Supply Agilent N5182 BBQ Agilent N9020 HMC1023LP5E Eval Board MXA Interface Board H gt 0 2 Q O A Z lt 0 lt u PC Control Figure 31 Characterization Setup Block Diagram For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt uL Hittite MICROWAVE CORPORATION v01 0113 RoHS EARTH FRIENDLY HMC1023LP5E Usage Information The HMC1023LP5E addresses different filter applications such as fixed frequency or variable bandwidth implementations dependent on the part selected see HMC1023LP5E Ordering Information and the control provided to the HMC1023LP5E These modes provide the user with different filter options depending on the system implementation HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER An overview of these trade offs are shown below Table 8 HMC1023LP5E Modes of Operation Function Unprogrammed Pre p
16. ANALOG Mittite DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK H gt lt QD LLI Q O A 2 lt N lt uL EJ Hittite MICROWAVE CORPORATION v01 0113 RoHS v EARTH FRIENDLY Typical Applications The HMC1023LP5E is ideal for Baseband filtering before or after data converters for point to point fixed wireless and cellular infrastructure transceivers Software defined radio applications Anti aliasing and reconstruction filters Test and measurement equipment ADC driver applications Functional Diagram Oo ea e any 2 Bocca e Jol le Jol JNJ ko S IN IN IN N NI N 24 N C VDDQ 2 BG is 23 VDDI N C 3 22 VDDCAL VDDQ 4 LX ea pe 2 21 VDDI 5 20 CMI 6 19 OIP 7 SPI EFROM 18 OIN 82 IL Q7 ed e Heye 229929090 5 e GND HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Features Low Noise Figure 10 dB High linearity In Band Outp
17. BVrms IPx dBm 4 dB 10 and OIP2 measured from 100 differential source into 400 differential load Used recommended OpAmp bias settings Reg 02h 1 0 in Table 9 OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION 01 0113 RoHSv 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Figure 25 In band Output IP3 amp Output IP2 Figure 26 5 MHz Bandwidth Filter vs Bandwidth amp Temperature 11 Magnitude and Group Delay 7 5 T 7 150 8 i z o X gt 9 8 3 m 6 te ur E z 2 5 7 10 14 40 m 72 Er Sen FILTER BANDWIDTH MHz FREQUENCY MHz op 40C 25C 85 Figure 27 72 MHz Bandwidth Filter Figure 28 HMC1023LP5E Filter I Q Magnitude and Group Delay Channel Isolation A a 5 Z v E lt 29 E E x Z m 8 S 0 m 8 lt 20 100 LL FREQUENCY MHz FREQUENCY MHz 72 MHz Bandwidth Filter Bypassed Figure 29 Input Impedance Figure 30 Output Impedance 1000 200 Tam mE Rego2h i0 10 800 150
18. ENCY MHz RegO2h 1 0 00 Reg02h 1 0 10 Reg02h 1 0 01 Figure 18 Output IP3 vs Output Common Mode Voltage 30 MHz Input t81 50 40 30 OUTPUT IP3 dBm COMMON MODE VOLTAGE V RegO2h 1 0 00 RegO2h 1 0 10 RegO2h 1 0 01 7 OIP3 and OIP2 measured from 100 differential source into 400 differential load Used recommended OpAmp bias settings Reg 02h 1 0 in Table 9 and OIP2 measurements can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB 8 72 MHz Filter Bandwidth Selected OIP3 and OIP2 measured from 100 O differential source into 400 O differential load OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q A Z lt N lt uL EJ Hittite MICROWAVE CORPORATION v01 0113 RoHS EARTH FRIENDLY Figure 19 Output IP2 vs Output Common Mode Voltage 30 MHz Input 19 80 70 60 50 OUTPUT IP2 dBm 40 COMMON MODE VOLTAGE V RegO2h 1 0 00 RegO2h 1 0
19. Full Scale Differential Output 400 O Differential Load 2 Vppd Full Scale Differential Output 100 Differential Load 0 5 Vppd Output Voltage Range 0 5 Vdd 0 5 V Output Common Mode Voltage Range 0 9 3 V Digital I O CALCK Frequency he as Nee ADM 20 40 MHz CALCK Duty Cycle 40 50 60 SCLK Frequency 20 30 MHz Digital Input Low Level VIL 0 4 V Digital Input High Level VIH 1 5 Digital Output Low Level VOL 0 4 Digital Output High Level VOH Vdd 0 4 Power Supply Analog amp Digital Supplies 4 75 5 5 25 V Supply Current Dependent on Bias 240 mA Power on Reset 250 us 1 The attenuation of the filter transfer function can be calculated directly at any frequency f as attenuation 10 l0g19 1 f fg 8 where fp is the 3 dB bandwidth or corner frequency for the filter Similarly for a given maximum attenuation and 3 dB bandwidth fo the frequency at which the attenuation is achieved can be calculated as f 10 8ttenuatior 10 4 A 1 2 6 t Note that for a 6th order Butterworth filter the 1 dB bandwidth is at 89 of the filter bandwidth and 0 5 dB bandwidth is at 84 of the filter bandwidth 2 Specified distortion is measured with opamp bias Reg 02h 1 0 settings recommended in Table 9 Table 2 Test Conditions Unless otherwise specified the following test conditions were used Parameter Condition Temperature 25 Reg 06h Setting 150 Gain Setting 0 dB
20. OTP values 7 When completed disable OTP write mode Reg OBh Power on Reset and Soft Reset The HMC1023LP5E has a built in Power On Reset and also a serial port accessible Soft Reset Power On Reset is accomplished when power is cycled to the HMC1023LP5E while Soft Reset is accomplished via the SPI by writing Reg OOh 5 1 followed by writing Reg OOh 5 0 All chip registers will be reset to default states approximately 250us after power up Serial Port Interface The HMC1023LP5E features a four wire SPI Four wires SEN SCK SDI SDO are necessary to implement a SPI Read Write functionality while a Write only functionality can be implemented with 3 wires SEN SCK SDI The HMC1023LP5E SPI features a 3 bit Chip ID that enables operation of up to 8 devices on the same SPI bus Chip ID of HMC1023LP5E is set to 101 b Please note that every SPI operation is both a Read and a Write Data is written to the HMC1023LP5E on the SDI line and read from the HMC1023LP5E on the SDO line every Read Write cycle as shown in Figure 38 Every SPI write the HMC1023LP5E returns the data contained in the register whose address is specified in Reg 00h 4 0 prior to the Write Read cycle Hence to read from a particular HMC1023LP5E register it is necessary to initially write the address of that register to Register 0 ie Reg OOh 4 0 REG ADDR where REG ADDR is the address of the register to be read on the next Read Write cycle The desired register wi
21. Width Default Description Opamp bias setting 00 min bias 1 0 opamp bias 1 0 2 01 11 max bias opamp_bias 1 0 01 standard bias characterized value opamp_bias 1 0 10 high linearity bias Driver bias setting 00 min bias 11 max bias drvr_bias 1 0 10 standard bias characterized value 32 bias 1 0 2 10 VGA gain setting 4 gain_10dB 1 0 0 OdB VGA gain 1 10dB VGA gain Filter bypass setting 5 bypass_filter 1 0 0 Filter bypass disabled 1 Filter bypass enabled Sets filter coarse tuning range 0000 5 MHz 0001 7 MHz 0010 10 MHz 0011 14 MHz 0100 20 MHz 0101 28 MHz 0110 40 MHz 0111 50 MHz 1000 72 MHz 9 6 coarse bandwidth code 3 0 4 0000 Sets the and Q channel input impedances together with Reg O1h 9 Reg 02h 10 RegO1h 9 impedance 0 0 1000 default 10 MSB Zinput select 1 0 0 1 4000 1 x 1000 H gt lt QD LLI Q O A Z lt N lt uL Reg 02h 10 and One Time Programmable memory Reg OAh 15 select between 100 and 1000 400 23 11 unused Table 19 Reg 03h Calibration Bit Name Width Default Description fine bandwidth setting override bits register 01 bit 4 force cal code must be set 0000 Minimum frequency 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Maximum frequency 3 0 fine bandwidth
22. acy However it also shows that excellent bandwidth accuracy x 5 5 96 is achievable at all filter bandwidth settings with even the lowest OpAmp bias setting Reg 02h 1 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q O A 2 lt N lt uL nuwctozsipse MICROWAVE CORPORATION 1 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY dB BANDWIDTH ERROR 0 10 20 30 40 50 60 70 80 FILTER BANDWIDTH SETTING MHz Figure 35 Calibrated HMC1023LP5E Bandwidth Error vs OpAmp Bias Reg O2h 1 0 Hence for applications in which current consumption is an important performance criteria it is possible to reduce the HMC1023LP5E current consumption by 90 mA or 450 mW at a cost of 5 dB lower linearity performance and lower but still excellent bandwidth accuracy performance of lt 5 5 96 Non Volatile One Time Programmable OTP Memory The HMC1023LP5E includes OTP One Time Programmable memory that enables the user to program the default configuration of the HMC1023LP5E on start up The programmable settings are s
23. alue to ADD to counter output before counter is decoded for calibration setting Number is in 2 s complement format Note this applies to all settings universally 8 0 meas adj 8 0 9 000h 23 9 unused Table 23 Reg 07h Unused Table 24 Reg 08h Calibration Status read only Bit Name Width Default Description fine bandwidth setting must run a calibration cycle to get valid data 8 0 fine_bandwidth_codef3 0 4 9000 Valid states are 0000 to 1011 see Table 3 Reg 03h Calibration 4 cal busy 1 Calibration active flag 5 OPT write busy 1 OTP write active flag 23 6 unused Table 25 Reg 09h Calibration Count read only Bit Name Width Default Description 23 0 count read 23 0 24 Output of calibration counter in pico seconds unadjusted For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD A z lt N lt L EJ Hittite MICROWAVE CORPORATION 107 0113 RoHS v HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER H gt lt QD LLI Q O A 2 lt N lt uL EARTH FRIENDLY Ta
24. ated Automatic Bandwidth Configuration In Automatic bandwidth setting the user simply selects from a choice of Coarse Bandwidths in Table 11 via Reg O2h 9 6 and the HMC1023LP5E automatically programs Reg O3h 3 0 during calibration so that the selected bandwidth is accurate to within 2 5 Example to select bandwidth of 14 MHz simply write Reg O2h 9 6 0011 b then write Reg Oth 4 1 to instruct the HMC1023LP5E to use provided settings For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q O A Z lt N lt uL nuwetosipse MICROWAVE CORPORATION 1 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Calibrated Manual Bandwidth Configuration Manual bandwidth setting enables arbitrary user defined bandwidths between 5 MHz and 72 MHz accurate to within 2 5 The coarse bandwidth is selected from Table 11 via Reg 02h 9 6 and that bandwidth is further refined using selections in Table 12 via Reg OSh 3 0 Initially the calibration result is read from Reg 09h 23 0 Then required Coarse Bandwidth selection is calculated as f
25. bias settings opamp bias Reg O2h 1 0 drvr bias Reg O2h 3 2 00 10 Input Signal Level 2 Vppd Input Output Common Mode Level 2V Output Load 200 Q Output Supply Analog 5V Digital 5V For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION 01 0113 RoHSv 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Figure 1 Filter Attenuation all Bandwidths 11 Figure 2 Filter Passband Gain Response m 0 3 0 2 0 1 0 1 5 amp Po 0 3 0 4 FERES Lo L ree 0 5 0 1 1 10 100 1000 0 1 1 FREQUENCY MHz FREQUENCY MHz 5 MHz 28 MHz 5 MHz 28 MHz 7 Mhz 40 MHz 7 MHz 40 MHz 10 MHz 50 MHz 10 MHz 50 MHz 14MHz 72 MHz 14MHz 72 2 20 MHz Bypass 20 MHz Figure 4 Filter 3 dB Cutoff vs Figure 3 Filter Attenuation 10dB Gain 11 Temperature 10 MHz Bandwidth 5 H gt lt QD LLI Q O A m 2 lt N lt L 8 oL ILLA Lee z E O m 10 i 0 3 0 1 1 10 100 1000 5 6 7 8 9 1
26. ble 26 Reg 0Ah OTP Values read only Bit Name Width Default Description fine bandwidth Non volatile fine bandwidth code 3 0 Definition is same as per Reg O3h 8 0 4 code 3 0 Calibration 6 4 OTP course_bandwidth_ 3 Non volatile version of SPI values found in Reg 02h 6 8 code 2 0 7 OTP_Gain_10dB 1 8 OTP bypass filter 1 Non volatile version of SPI values found in Reg 02h Settings 10 9 opamp bias 1 0 2 12 11 OTP_drvr_bias 1 0 2 This flag must be set if the OTP values are to be used and must be set by the 13 OTP_prg_flag 1 user If not set this flag overrides bit 0 of Reg Oth 14 OTP Coarse Bandwidth 3 Non volatile version of SPI values found in Reg O2h 9 15 Zinput select 1 Non volatile version of SPI value found in Reg O2h 10 23 16 unused Table 27 Reg 0Bh OTP Write Enable Bit l Name Width Default Description 0 EFR_Write_enable 1 0 Enables OTP Programming 23 1 unused Table 28 Reg OCh OTP Write OTP address register is used in programming of OTP Bit Name Width Default Description 3 0 OTP Address 4 0 Address of OTP bit to be set 23 4 unused Table 29 Reg 0Dh OTP Write Pulse OTP strobe register is used in programming of OTP Bit Name Width Default Description 23 0 reserved 1 0 reserved Table 30 Reg OEh RC BIST Enable B
27. d the bandwidth is further refined via Reg OSh 3 0 according to Table 12 where Re O3h 3 0 fwanteD fsw_norm_coarse_typ where few norm coarse typ Corresponds to the selected typical coarse bandwidth setting in Table 11 programmed via Reg O2h 9 6 Example to select the bandwidth of 13 MHz select the closest typical value in Table 11 and program Reg O2h 9 6 accordingly ie Reg O2h 9 6 0011 b then Heg O3h 3 0 fwawrep few norm coarse 19 MHz 14 MHz 0 9286 Hence from Table 12 Reg OSh 3 0 0100 Finally write Reg O1h 4 1 to instruct the HMC1023LP5E to use provided settings In all cases when uncalibrated the bandwidth is accurate to within 20 of the programmed bandwidth Calibrated Bandwidth Configuration The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E Once executed if the calibration settings are remembered they are always valid for that specific HMC1023LP5E Detailed instructions of how to calibrate the HMC1023LP5E are available in RC Calibration Circuit section When calibrated the programmed bandwidth is accurate to 2 5 The HMC1023LP5E calibrated bandwidth can be programmed in two ways Automatic or Manual The automatic calibration supports only Coarse Bandwidth Settings in Table 11 whereas the Manual calibration supports arbitrary bandwidths from 5 MHz to 72 MHz In both cases the bandwidth is accurate to within 2 5 Calibr
28. dered from the factory precalibrated The OTP memory is programmed via the standard 4 wire serial port SPI as follows For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com J MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY 1 enable OTP write mode see Reg OBh bit 0 enables OTP programming 2 read the status of the OTP active flag see Reg 08h bit 5 is the OTP active flag The Write Pulse Status OTP active flag must be 0 to allow the OTP to be programmed 3 write the OTP bit address to be set Reg OCh This address is a 4 bit number representing the address of the bit to be programmed Note that when programming a bit we change its state from 0 to 1 and this operation cannot be reversed OTP bit addresses can be found in Reg 08h 4 start the OTP Write operation Write any data to the OTP strobe register Reg ODh 5 read the status of the OTP active flag Reg 08h bit 5 is the OTP active flag If bit 5 is set then the Write pulse is still high Repeat until bit 5 is O which indicates that the write pulse is finished 6 Repeat steps 3 to 5 to program the remaining desired bits Note that bit 13 OTP prg flag must be set by the user to use
29. dth Code and Fine Bandwidth Code and the corresponding values in Table 11 and Table 12 For example if the 3 dB bandwidth for the HMC1023LP5E was factory pre programmed to a customer defined requirement of 34 MHz and Reg O2h 9 6 0110 Coarse Bandwidth Code and Reg OSh 3 0 0010 Fine Bandwidth Code as determined from Reg OAh for a pre programmed part or from Reg 02h amp Reg 03h for a non programmed part then ctune can be estimated as follows 1 Lookup the nominal coarse bandwidth and fine bandwidth frequencies a From Table 11 the nominal coarse frequency is 40 MHz b From Table 12 the nominal fine normalized frequency is 0 862 MHz MHz or simply 0 862 2 Estimate ctune as ctune 40 MHz 0 862 34 MHz 1 0141 This value of ctune can now be used to calculate any arbitrary filter frequency as described above RC Calibration Circuit The RC Calibration block uses a known user supplied clock to measure an on chip RC time constant This measurement is representative of the uncorrected corner frequency error for a given bandwidth for the HMC1023LP5E Calibration is normally done at room temperature Refer to Table 1 Electrical Specifications for further details on the variation of the 3 dB cutoff point with temperature Typically programmed bandwidth varies 0 03 C With this information the HMC1023LP5E can correctly fine tune the LPF by adjusting the resistors in the LPF to center the corner frequency to the de
30. e delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q O A 2 lt N lt uL uwctozasipse MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY HHO HMC1035LP6GE HMC832LP6GE HMC1023LPSE HMC1097LP4E SPI CONTROL Figure 33 Typical Transmit Path Block DiagramHMC1023LP5E Ordering Information Input Interface Input stage features a programmable input impedance 100 Q 400 1 differential or 50 Q 200 0 500 Q single ended that is configured via Reg O1h 9 and Reg 02h 10 Programmable impedance enables a configurable interface tailored to the requirements of the component driving the HMC1023LP5E It enables maximum Noise Figure NF performance regardless of the device driving the HMC1023LP5E NF of the HMC1023LP5E with various input impedance settings is provided in Figure 5 Figure 6 and Figure 7 Actual input impedance over frequency is shown in Figure 29 Wide input common mode voltage range further simplifies input interface The HMC1023LP5E does n
31. e resistors Note that all Op Amps in the LPF are class AB for minimum power consumption in the filter while maintaining excellent distortion characteristics even in large signal swing conditions The attenuation due to the LPF can be calculated for any frequency f from the standard Butterworth transfer function for a 6th order filter Specifically the attenuation of the filter in dB can be calculated as attenuation 10 log 1 f f where f is the 3 dB bandwidth or corner frequency for the filter Note that for a 6th order Butterworth filter the 1 dB bandwidth is 90 of f and the 0 3 dB bandwidth is 80 of f Filter Bandwidth Setting The 3 dB bandwidth of the HMC1023LP5E is programmable anywhere within the range from 5 MHz to 72 MHz When calibrated filter bandwidth is accurate to within 2 5 of the programmed bandwidth if not calibrated it is accurate to within 20 of the programmed bandwidth The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E Once For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com J MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY executed if the calibration set
32. etting SIBEBAND REJECTION dBc 0 1 2 3 4 5 6 7 8 FILTER BANDWIDTH MHz 1000 Q 400 0 1000 Figure 11 Arbitrary Bandwidth Setting 3 dB Cutoff Frequency Error 51 4 Opamp Bias 00 __ Opamp Bias 01 dB CUTOFF FREQUENCY ERROR o 0 10 20 30 40 50 60 70 80 ARBITRARY FILTER BANDWIDTH MHz HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 8 Filter Output Noise 3 100 RN i E E Q o z 2 a E 2 10 0 001 0 01 0 1 1 10 100 FREQUENCY MHz 5MHz 28 MHz 7 MHz 40 MHz 10 MHz _ _ 50 MHz 14 MHz 72 MHz 20 MHz Figure 10 UncalibratedSideband Rejection 10 dB Gain 60 55 SIBEBAND REJECTION dBc 0 1 2 3 4 5 6 Y 8 FILTER BANDWIDTH MHz 10000 4000 1000 Figure 12 Output IP3 72 MHz Bandwidth Setting 0 dB Gain 61 50 40 30 20 OUTPUT IP3 dBm 0 10 20 30 40 50 60 70 FREQUENCY MHz RegO2h 1 0 00 Reg02h 1 0 10 Reg02h 1 0 01 3 100 source impedance used and input impedanceo of HMC1023LP5E set to 1 4 100 input impedance into the HMC1023LP5E selected by writing Reg O2h 10 1 5 Used recommended OpAmp bias settings Reg O2h 1 0 in Table 9 6 OIP3 and OIP2 measured from 100 differential source into 400 differential load Used recommended OpAmp bias settings Reg 02h 1 0 in Table 9 OIP3 and OIP2 meas
33. g O8h 3 0 Once calibrated the HMC1023LP5E automatically writes the calibrated fine Fine Bandwidth values to Reg 03h 3 0 ie Reg O3h 3 0 Reg 08h 3 0 as explained in Calibrated Automatic Bandwidth Configuration section If desired the calibration results can be overridden via Reg O3h 3 0 as explained in Calibrated Manual Bandwidth Configuration section Output Driver The HMC1023LP5E output driver consists of a differential class AB driver which is designed to drive typical ADC loads directly or can drive up to 200 O in parallel with 50 pF to AC ground per differential output Note that the output common mode of the driver is controlled directly via the CMI CMQ pin and can be set as per Table 1 Electrical Specifications Also note that driver loading does not impact filter transfer responses A block diagram showing output connections is presented below PADDLE GND ESD 10kQ CMI ESD NO EXTERNAL ADC DRIVER VDDI REQUIRED esp N 100 ESD PADDLE GND 3 ADC esp 100 OIN esp O VDDI Figure 37 Output Driver Block Diagram Bias Circuit A band gap reference circuit generates the reference currents used by the different sections The bias circuit is enabled or disabled as required with the or Q channel as appropriate One Time Programmable Memory OTP The HMC1023LP5E features one time programmable memory which can be programmed by the end user or or
34. ge Bypass mode 75 100 MHz uncalibrated 20 3 dB corner frequency variation calibrated 2 5 3 5 3 dB corner frequency variation vs temperature over 40 C to 85 C 0 03 1 C Max passband gain error vs ideal 6th order LPF H s 0 5 dB at 0 1 dB BW 0 73 fc 0 250 at 0 5 dB BW 0 83 fc at 1 0 dB BW 0 89 fc at 3 0 dB BW at fc 0 400 min gain fc 5 MHz 22 nV rtHz min gain fc 28 MHz 22 nV rtHz Output Noise f 1 MHz max gain fc 5 MHz 25 nV rtHz max gain fc 28 MHz 25 nV rtHz min gain fc 5 MHz 8 nV rtHz max gain 5 MHz 8 nV rtHz Output noise f gt 10 fc z min gain fc 28 MHz 8 nV rtHz max gain fc 28 MHz 8 nV rtHz Noise Figure 100 source min gain dB Input referred Out of Band IM3 half scale tones at 2fc and 3fc IMS product at 0 5fc max gain min gain 19 dB Noise Figure 1 kQ source 12 half scale tones at 0 8fc and 0 6fc Input referred Passband IM3 fc 20 MHz 60 dBc fc 72 MHz 50 dBc half scale tones at 1 2fc and 1 6fc IM3 product at 0 8fc Input referred Out of Band IMS fc 20 MHz 60 dBc fc 72 MHz 2 fc 20 MHz 50 dBc fc 72 MHz 21 45 dBc half scale tones at 0 8fc and Output IP3 inband fc ix 25 30 dBm fc 72 MHz 17 20 dBm half scale tones at 1 2fc and Output IP3 out of band iN ete 25 30 dBm fe 72 MHz 21 17 20 dBm
35. h 8 0 36 Reg10h 4 0 to Reg1Ah 4 0 231d or 1Fh Reg OFh 15 0 55027 Reg 09h 23 0 14143649 Reg 05h 14 0 10922 Reg 06h 8 0 170 Reg10h 4 0 to Reg1Ah 4 0 10d or Ah Reg OFh 15 0 28618 Reg 09h 23 0 8907563 Reg 05h 14 0 221845 Reg06h 8 0 2853 Reg10h 4 0 to Reg1Ah 4 0 21d or 15h Reg oFg 15 0 16368 Reg 09h 23 0 23396981 H gt T Z QD Q O or A 2 lt N lt L For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com nwctozs ese MICROWAVE CORPORATION 101 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Register Map Table 15 Reg 00h Chip_ID Read Only Bit Name Width Default Description 23 0 Chip_ID 24 D7780 HMC1023LP5E Chip ID Table 16 Reg 00h Read Address Write Only 0 Doubler Disabled RC Calibration clock 40 MHz RC calibration clock lt 80 MHz 5 doubler enable 1 0 1 Doubler Enabled RC Calibration clock 20 MHz RC calibration clock lt 40 MHz LL gt Bit Name Width Default Description 4 0 Register Read Address 5 Address of the register to be read on the next read write cycle 22 Soft Reset 5 Sof
36. hown in Reg OAh they include e Bandwidth e Filter bypass enable e Gain e Input impedance 100 or 1kQ differential 400 Q differential is also available but can only be set via SPI interface e OpAmp bias e Driver bias Once the OTP memory is programmed by default on power up the HMC1023LP5E enters the state programmed in OTP memory However even after the OTP memory is programmed HMC1023LP5E retains full functionality and can be re configured to any other state via Serial Port Interface Therefore the configuration burned in OTP memory is only a default configuration of the HMC1023LP5E on power up which can be changed to any user defined configuration after power up using the SPI Detailed instructions on programming the OTP memory are provided in One Time Programmable Memory OTP section Filter Programming amp Calibration Detailed description of filter bandwidth programming is provided in Filter Bandwidth Setting section To achieve the rated accuracy each HMC1023LP5E device requires calibration at least once Once calibrated the settings are always valid for that particular HMC1023LP5E Filter calibration requires an input clock More information about calibration clock and calibration procedure is provided in RC Calibration Circuit section The calibration clock is only required during calibration It is not required for the operation of the HMC1023LP5E For price delivery and to place order
37. istance junction to ground paddle TOSGAN Reflow Soldering Peak Temperature 260 C Time at Peak Temperature 40 us ESD Sensitivity HBM 1 kV Class 1C Table 4 Recommended Operating Conditions HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTROSTATIC SENSITIVE DEVICE A OBSERVE HANDLING PRECAUTIONS Parameter Condition Min Typ Units Temperature Junction Temperature 125 C Ambient Temperature 40 85 C Supply Voltage VDDCAL VDDI VDDQ VDDBG DVDD 4 75 5 5 25 V 1 Layout design guidelines set out in Qualification Test Report are strongly recommended For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com nwctozz ese MICROWAVE CORPORATION 1 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER
38. it Name Width Default Description 0 enable RCBIST mode 1 0 RC BIST mode enable 23 1 unused For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Application Support Phone 978 250 3343 or apps hittite com Fax 978 250 3373 Order On line at www hittite com CHIC HmcozaLPsE MICROWAVE CORPORATION v01 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Table 31 Reg OFh RC BIST Out Bit Name Width Default Description 15 0 crc BIST 15 0 16 0 RC BIST CRC check result RC BIST busy flag Indicates that BIST cycle is not completed and data crc_ BIST 15 0 is invalid 16 crc RC BIST busy flag 1 0 23 17 unused Table 32 Reg 10h to Reg1A Window Threshold OTP strobe register is used in programming of OTP Bit Name Width Default Description 23 0 reserved reserved H gt 0 Z QD Q O A 2 lt N lt u For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com
39. ittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q O A 2 lt N lt uL HmawzLPsE MICROWAVE CORPORATION 1 0113 ROHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Theory of Operation The HMC1023LP5E consists of the following functional blocks 1 Input Gain Stage 2 6th Order Butterworth LPF 3 Output Driver 4 RC Calibration Circuit 5 Bias Circuit 6 One Time Programmable Memory 7 Serial Port interface 8 Built in Self Test RC BIST Input Gain Stage The HMC1023LP5E input stage consists of a programmable 0 or 10 dB gain stage which in turn drives the 6th order LPF A block diagram showing input impedance of the channel is presented below Q channel is similar VDDI ESD 5000 5000 1 5kON BE 1000 PADDLE GND 34 or4000 c or1000Q ESD IIN 5000 5000 1 5kO ESD VDDI Figure 36 Input Stage Block Diagram 6 Order Low Pass Filter LPF The LPF allows for coarse bandwidth tuning by varying the capacitive elements in the filter while the fine bandwidth tuning is accomplished by varying th
40. ll be read on the next 2nd Write Read cycle If nothing additional is desired to be written to the HMC1023LP5E on the 2nd Write Read cycle simply rewrite Reg 00h 4 0 REG ADDR on the second Read Write cycle to conclude the register read In summary the Read cycle uses indirect addressing where Reg 00h contains the pointer to the address of the register to be Read Note that in any SPI cycle the Write data is stored in the register at the end of the cycle when SEN goes high This means that the address pointer Reg OOh 4 0 must be set prior to the Read Write cycle in which the desired data is read Typical serial port operation can be run with SCK at speeds up to 30 MHz Serial Port WRITE Operation The host changes the data on the falling edge of SCK and the HMC1023LP5E reads the data on the rising edge A typical WRITE cycle is shown in Figure 38 It is 32 clock cycles long 1 The host sets Serial Port Enable SEN low and places the MSB of the data on Serial Data Input SDI followed by a rising edge on SCK 2 HMC1023LP5E reads SDI MSB first on the 1st rising edge of SCK after SEN For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt
41. ollows few nom coarse fwanten Reg O9h 23 0 153600 10370000 EQ 1 where fwantep is the desired arbitrary bandwidth The Coarse Bandwidth nearest to calculated fay norm coarse is selected from Table 11 and written to Reg O2h 9 6 To calculate the Fine Bandwidth Setting fine tune ratio is calculated as shown in EQ 2 fine tune ratio wass faw_norm_coarse_typ EQ 2 where the few norm_coarse IS given in EQ 1 and faw S the nearest corresponding bandwidth in Table 11 Then Fine Bandwidth Setting is selected from a nearest column in Table 12 that corresponds to the calculated fine tune ratio and programmed to Reg O3h 3 0 Example to select the bandwidth of 13 MHz initially read Reg O9h 23 0 in this example Reg O9h 23 0 10470000 Then according to EQ 1 few coarse 13 MHZ 10470000 153600 10370000 13 318 MHz Select the closest typical value in Table 11 to 13 318 MHz and program Reg 02h 9 6 accordingly ie Reg O2h 9 6 0011 b then Reg O3h 3 0 fwanrep faw nom coarse 13 317917 MHz 14 MHz 0 95128 Hence from Table 12 Heg OSh 3 0 0107 Finally write Reg Oth 4 1 to instruct the HMC1023LP5E to use provided settings Please note that the HMC1023LP5E Evaluation Software distributed with HMC1023LP5E Evaluation Kits implements this Calibrated Arbitrary Bandwidth algorithm Table 11 Normalized Bandwidth Look up Table
42. on regarding changing the bandwidth after calibration when further calibration is not possible For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Phone 978 250 3343 Fax 978 250 3373 J MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY HMC1023LP5E Application Information Accurate arbitrary user defined bandwidths programmable gain and flexible programmable IO interface provide the HMC1023LP5E with unmatched flexibility This flexibility together with market leading performance in terms of linearity Noise Figure and bandwidth accuracy enable a universal solution capable of supporting numerous radio standards frequencies and or bandwidths with a single hardware platform The HMC1023LP5E is relevant in both transmitter and receiver applications Figure 32 and Figure 33 In transmitter applications the HMC1023LP5E serves as an anti aliasing filter that rejects Digital to Analog Converter aliases and ensures the desired transmitted spectral mask In receiver applications the HMC1023LP5E serves as an Analog to Digital converter driver an anti aliasing filter and a blocker rejection filter all in one In both transmitter and receiver applications excellent 6th order but
43. ot require any configuration for input common mode voltage as long as the part is operated within the specifications outlined in Table 1 The HMC1023LP5E does not require any specific impedance at the input Input interface should be designed according to the demands of the device driving the HMC1023LP5E while programmable input impedance of the HMC1023LP5E permits optimal matching and or NF performance Both ac coupled and dc coupled interfaces are supported at the input Output Interface Output common mode voltage of the HMC1023LP5E is set via CMI and CMQ pins for the in phase and quadrature outputs respectively Wide output common mode voltage range simplifies interface with numerous devices The HMC1023LP5E s 0 9 V to 3 V output common mode voltage range is specified with a 2 Vppd output signal swing Lower common mode output voltage is supported with lower signal swing The key requirement is that the signal swing in combination with common mode voltage does not go below 0 5 V single ended Hence as an example a 0 7 V output common mode voltage level is supported with 0 8 Vppd signal swing Figure 18 to Figure 23 show the effect of output common mode voltage on linearity performance Output IP2 amp Output IP3 of the HMC1023LP5E The plots indicate that even for a large output signal swing of 2 Vppd the HMC1023LP5E typically maintains high linearity performance below 0 9 V nominal output common mode limit Figure 34 shows measured ou
44. r set and forget parameters like gain and bandwidth setting Housed in a compact 5x5 mm SMT QFN package the HMC1023LP5E is pin and register compatible to the existing HMC900LP5E programmable bandwidth Low Pass Filter It requires minimal external components and provides a low cost alternative to more complicated Switched discrete filter architectures The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com E Hittite MICROWAVE CORPORATION 01 0113 RoHS EARTH FRIENDLY Table 1 Electrical Specifications HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER T 25 C VDDI VDDQ VDDCAL VDDBG DVDD 5V 5 GND OV 400 load unless otherwise stated Parameter Conditions Min Typ Max Units Analog Performance p 1 min gain setting 0 dB Passband Gain max gain setting 10 dB 3 dB corner frequency fc 1 Max passband group delay variation group delay 3 dB frequency fc e g for 1 0 dB BW of 40 MHz fc 44 9 MHz max group delay variation 0 400 44 9 MHz 8 9 ns Programmable to any frequency in this ran
45. rogrammed SPI CALCK Comments HMC1023LP5E 00000 HMC1023LP5E BBBGL Req d Req d Fixed Bandwidth Filter Yes Yes Default Bandwidth and Gain Derault Bandwidth Bandwidth and Pre programmed gain and bandwidth _ and Gain as defined Gain as defined by setting after Power On Reset by register defaults pre programming at No No are defined when ordering the part See POR 5 MHz OdB gain factory HMC1023LP5E Ordering Information Typical Corner Frequency Ac 5 Accuracy is with respect to bandwidth curacy at Default Bandwidth HEN after POR Variable Bandwidth Filter Yes Yes requires access via the digital serial port SPI Default Bandwidth and Gain Bandwidth Bandwidth arid Pre programmed gain and bandwidth _ and Gain as defined Gain as defined by setting after Power On Reset by register defaults pre programming at are defined when ordering the part See POR 5 MHz OdB gain factory HMC1023LP5E Ordering Information i No is wi i Typical Corner Frequency Ac 20 96 4J 2 5 96 Accuracy is with respect to bandwidth curacy at Default Bandwidth after POR Accuracy is with respect to the desired Typical Corner Frequency bandwidth Accuracy at all other Band 20 5 0 See Filter Bandwidth Setting for informa widths tion regarding changing the bandwidth after when calibration is not possible Variable Bandwidth Filter Full control over HMC1023LP5E require
46. s m access via the digital serial port SPI with ability to execute User F AEN i Yes Yes Filter calibration requires valid calibration Calibration to calibrate filter clock via CALCK See RC Calibra bandwidth i fics hae tion Circuit Default Bandwidth and Gain Def di Bandwidth Bandwidth and Pre programmed gain and bandwidth and Gain as defined Gain as defined by setting after Power On Reset by register defaults pre programming at are defined when ordering the part See POR 5 MHz 0dB gain factory HMC1023LP5E Ordering Information 20 Typical Corner Frequency Accuracy is with respect to bandwidth Accuracy after POR before 20 2 5 A after POR User Calibration Accuracy is with respect to calibrated Typical Corner Frequency Ac Yen is bandwidth 4 User Calibration requires access to the curacy after User Calibration 2 5 2 5 a HMC1023LP5E via the digital serial port at calibrated bandwidth SPI and requires a valid calibration clock via CALCK pin Accuracy is with respect to the desired bandwidth User Calibration requires access to the HMC1023LP5E via the digital serial port Typical Corner Frequency Ac SPI and requires a valid calibration clock curacy after User Calibration 5 0 5 0 at non calibrated bandwidths via pin GALCK See Filter Bandwidth Setting for informa ti
47. s Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com uwctozaspse MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY HMC1023LP5E Ordering Information The HMC1023LP5E is available as product that is either un programmed or pre programmed Programming is available to a variety of filter bandwidths defined in this context as the 3dB bandwidth Other options available for pre programmed product include the single path gain and bias state as described below Gain and bias settings are described in Reg 02h When placing an order for the HMC1023LP5E please observe the following guidelines 1 Toorderthe un programmed standard part please place order using the part number HMC1023LP5E 000000 2 Toorder a pre programmed HMC1023LP5E please determine the part number as described below and then contact Hittite Sales at sales hittite com or call 978 250 3343 2 1 Minimum quantity order for the pre programmed HMC1023LP5E BBBGLL is 500 pieces 3 Pre Programmed part number description HMC1023LP5E BBBGL 3 1 BBB represents a three digit number from the Table 10 that represents the desired bandwidth setting 8 dB bandwidth from 5 MHz to 72 MHz for example BBB 050 specifies a 5 MHz corner frequency 3 2 G represent
48. s the gain setting of either 0 dB G 0 or 10 dB G 1 3 3 LL represents the OpAmp bias setting of the HMC1023LP5E For more information please see Linearity Bandwidth Accuracy and Current Consumption section For example to order the HMC1023LP5E pre programmed for 72 MHz 3 dB frequency 10 dB gain and standard low 00 OpAmp bias setting please specify part number HMC1023LP5E 720100 Table 10 Custom Part Frequency Options BBB frequency for custom part actual frequency is BBB x 0 1 MHz 050 069 093 128 171 229 307 411 554 709 052 070 095 131 175 235 315 422 565 720 053 071 098 134 179 240 322 432 576 054 073 100 137 180 246 330 443 587 056 075 102 140 184 253 338 454 598 057 076 105 141 188 259 347 465 609 058 078 108 144 193 265 355 476 621 060 080 110 148 198 272 364 488 632 061 082 118 151 203 278 3738 500 643 063 084 116 155 208 280 382 510 654 064 086 119 159 213 285 392 521 665 066 088 121 163 218 292 400 532 676 068 091 124 167 224 300 401 543 687 For additional information or inquiries please contact Hittite Apps Support at apps hittite com 1 The Output IP2 and Output IP3 for the two linearity settings are shown in Figure 13 and Figure 14 High linearity setting improves linearity for bandwidths greater than 30 MHz at the cost of increased current consumption additional 25 mA For price delivery and to place orders H
49. sired bandwidth To calibrate the HMC1023LP5E proceeds as follows 1 Apply a clock signal of frequency between 20 MHz and 100 MHz on the CALCK pin pin 11 of the HMC1023LP5E The clock signal only needs to be applied during the calibration procedure and is not For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt lt QD LLI Q O A m 2 lt N lt L H gt lt QD LLI Q O A 2 lt N lt uL CJHIHHCE nuwetosipse MICROWAVE CORPORATION 1 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY required at other time Please note that an integrated clock doubler must be enabled for clock frequencies less than 40 MHz To enable the clock doubler simply write Reg O1h 5 1 2 Write the applied clock signal period to Reg 05h 14 0 in picoseconds 3 Enable the RC calibration circuit by writing Reg O1h 1 1 4 Write Reg O6h 8 0 152d 96h 5 Write Reg 04h 0 to initialize the calibration cycle The HMC1023LP5E indicates that the calibration is in process when Reg 08h 4 1 When Reg 08h 4 0 calibration has finished When complete the calibration Fine Bandwidth Value can be retrieved from Re
50. t Reset 1 ud Fespa iur ae to set this bit to O after soft reset event ie after 0 23 6 Not Defined 1 Don t Care X Table 17 Reg 01h Enable A Bit Width Default Description Q 0 OTP_DontUse 1 0 Default use stored OTP values only if OTP is programmed z 1 cal enable 1 0 Enable RC Calibration circuit lt 2 filter_l_enable 1 1 Enable channel gain stage filter and driver 3 filter_Q_enable 1 1 Enable Q channel gain stage filter and driver 4 force_cal_code 1 0 Force calibration setting to use SPI values Reg 03h Calibration A aa LL Note calibration clock duty cycle must be within 50 10 8 6 reserved 3 000 Sets the and Q channel input impedances together with Reg O1h 9 Reg 02h 10 Reg 01h 9 impedance 0 0 1000 default 9 LSB Zinput select 1 0 0 1 4000 1 x 1000 Reg 02h 10 and One Time Programmable memory Reg OAh 15 select between 100 and 1000 400 23 10 unused For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION 101 0113 RoHSv 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Table 18 Reg 02h Settings Bit Name
51. terworth filter response with virtually no pass band ripple and exceptional 2 5 bandwidth accuracy enables simple modem designs that need not utilize complex adaptive equalization schemes to compensate for filter ripple and group delay variation In such applications together with Hittite s Wideband PLLVCOs the HMC1023LP5E enables truly wideband multi standard multi carrier hardware platforms software configurable to the demands of each particular application Compared to discrete filters the HMC1023LP5E saves valuable board area and cost Typically higher order discrete filters are required to achieve comparable rejection as the HMC1023LP5E due to the inherent error tolerances in the value of each individual component In addition discrete filters are fixed in bandwidth typically requiring multiple band specific hardware versions that tends to increase the cost relative to supporting only one hardware version for all bands supported by the HMC1023LP5E The HMC1023LP5E overcomes the matching problem that discrete filters present with respect to baseband signal processing The matched dual filter paths provide excellent gain and phase balance between the two channels eliminating the image problem which results from poor matching HMC832LP6GE HMCS97LP4E HMC960LP4E HMC1023LP6GE HMCAD1520 SPI CONTROL Figure 32 Typical Receive Path Block Diagram showing HMC1023LP5E For pric
52. tings are remembered they are always valid for a specific HMC1023LP5E Please note that best bandwidth accuracy is achieved when the HMC1023LP5E is calibrated at its typical operating temperature Programmed bandwidth varies 0 03 C Filter Bandwidth Configuration The HMC1023LP5E bandwidths are configured using Coarse Bandwidth Settings in Reg O2h 9 6 and Fine Bandwidth Settings in Reg O03h 3 0 Coarse Bandwidth Settings select from a choice of coarse bandwidth options in Table 11 and the Fine Bandwidth Settings further refine the selected coarse bandwidth settings according to Table 12 In all cases once the Reg 02h 9 6 and or Reg 03h 3 0 have been programmed it is required to set Reg O1h 4 1 in order to instruct the HMC1023LP5E to use provided settings After calculating the settings for a given device they can be stored permanently in the non volatile memory See One Time Programmable Memory OTP for more information Uncalibrated Bandwidth Configuration When not calibrated the coarse bandwidth is selected via Reg 02h 9 6 according to the desired coarse bandwidth setting in Table 11 Example to select bandwidth of 14 MHz simply write Reg O2h 9 6 0011 b then write Reg Oth 4 1 to instruct the HMC1023LP5E to use provided settings If desired it is possible to tune to an arbitrary bandwidth choice not provided in Table 11 In that case nearest coarse bandwidth is selected via Reg 02h 9 6 according to Table 11 an
53. tput common mode voltage as a function of input common mode setting on CMI amp CMQ pins The plot is generated with 2 Vppd output signal and shows that output common mode voltage follows the settings on CMI amp CMQ pins well beyond the rated 0 9 V to 3 V For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION v01 0113 Bone 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY OUTPUT COMMON MODE V 0 1 2 3 4 5 COMMON MODE SETTING CMI amp CMQ PIN V Figure 34 Output vs Input Common Mode Voltage Output impedance of the HMC1023LP5E is nominally 10 single ended or 20 differential The HMC1023LP5E does not require any special impedance matching at the output The output of the HMC1023LP5E is an OpAmp driver capable of driving small and large loads alike Output interface of the HMC1023LP5E should be designed according to the demands of the device the HMC1023LP5E is driving Linearity Bandwidth Accuracy and Current Consumption As shown in Figure 25 the HMC1023LP5E is a high linearity device typically exhibiting in excess of 30 dBm Output IP3 and over 60 dBm Output IP2 throughout the operating range of the part To maintain maximum performance as measured
54. tputs respectively For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Order On line at www hittite com Phone 978 250 3343 Fax 978 250 3373 Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION vo01 0113 RoHS v 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY Table 6 Pin Descriptions Continued Pin Number Function Description Interface Schematic Ov R gt 20 CMI Inphase I channel output common mode level dp Inphase I Channel 5V Supply Must be locally decoupled 21 23 VDDi GNO A 22 VDDCAL Calibration 5V Supply Must be locally decoupled to GND ep Q Inphase 1 channel positive and negative differential 26 27 IIN Q inputs respectively 28 VDDBG Bias 5V Supply Must be locally decoupled to GND Q VBG 29 VBG 1 2V Bandgap output testing only LU 19 IQN 30 31 ION IQP Quadrature Q channel negative and positive differential inputs respectively For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt Z QD Q O A Z lt
55. urements can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite MICROWAVE CORPORATION vor ons RoHSv EARTH FRIENDLY Figure 13 Output IP2 72 MHz Bandwidth Setting 0 dB Gain 71 90 80 70 60 OUTPUT IP2 dBm 50 0 10 20 30 40 50 60 70 FREQUENCY MHz RegO2h 1 0 00 RegO2h 1 0 10 RegO2h 1 0 01 Figure 15 Output IP2 Filter Bypass Mode Enabled 0 dB Gain 171 OUTPUT IP2 dBm 0 10 20 30 40 50 60 70 80 90 FREQUENCY MHz RegO2h 1 0 00 RegO2h 1 0 10 RegO2h 1 0 01 Figure 17 Output IP2 Filter Bypass Enabled 10 dB Gain 171 90 80 70 OUTPUT IP2 dBm 60 50 0 10 20 30 40 50 60 70 80 90 FREQUENCY MHz RegO02h 1 0 00 RegO2h 1 0 10 RegO02h 1 0 01 HMC1023LP5E 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 14 Output IP3 Filter Bypass Enabled 0 dB Gain OUTPUT IP3 dBm 0 10 20 30 40 50 60 70 80 90 FREQUENCY MHz Reg02h 1 0 00 RegO2h 1 0 10 RegO2h 1 0 01 Figure 16 Output IPS Filter Bypass Enabled 10 dB Gain 171 50 40 30 20 OUTPUT IP3 dBm 0 10 20 30 40 50 60 70 80 90 FREQU
56. ut IP3 gt 30 dBm In Band Output IP2 gt 60 dBm Pre programmed and or Programmable Bandwidth 5 MHz to 72 MHz Please see HMC1023LP5E Ordering Information Exceptional 3 dB Bandwidth Accuracy 2 5 Programmable Gain 0 or 10 dB Integrated ADC Driver Amplifier 6 order Butterworth Magnitude amp Phase Response Automatic Filter Calibration Externally Controlled Common Mode Output Level Filter Bypass Option Pin amp Register Compatible to HMC900LP5E Read Write Serial Port Interface SPI 32 Lead 5x5 mm SMT Package 25 mm General Description The HMC1023LP5E is a 6th order programmable bandwidth fully calibrated dual low pass filter It features programmable 0 or 10 dB gain and supports arbitrary bandwidths from 5 MHz to 72 MHz When calibrated the bandwidth is accurate to 2 5 Built in filter bypass option enables wider bandwidths while maintaining programmed gain and common mode control settings Integrated ADC driver programmable input impedance and adjustable output common mode voltage from 0 9 V to 3 V with 2 Vppd signal or lower than 0 9 V common mode with lower signal swing enables simple interface while achieving maximum performance Programmable bias settings enable performance power dissipation trade off optimized for each application Filter calibration is accomplished with any reference clock rate from 20 to 80 MHz One time programmable OTP memory offers unsurpassed flexibility allowing the use
57. utput The 32 bits consists of 24 data bits 5 address bits and the 3 chip id bits 10 This completes the READ cycle Note that the second Read Write cycle is also both a Read and a Write Hence if it is not desired to write anything new to the HMC1023LP5E on the second Read Write cycle simply rewrite the same data to Reg 00h that was written on the previous cycle Serial Port Bus Operation with Multiple Devices The SPI bus architecture supports multiple devices on the same SPI bus Each HMC1023LP5E on the bus requires a dedicated SEN line to enable the appropriate device The SDO line is normally driven by the HMC1023LP5E during and after an SPI read write which is addressed directly to the HMC1023LP5E chip address 5d or 101 b A write to the HMC1023LP5E where chip address is set to any value other than 5d or 101 b is required in order to ensure that the SDO pin remains tri stated by the HMC1023LP5E For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com uctus MICROWAVE CORPORATION 1 0113 RoHS 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER EARTH FRIENDLY after accessing the HMC1023LP5E Such a write will not result in any change in the HMC1023LP5E configuration because of the incorrect chip address

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