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USER`S MANUAL

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1. Table 1 1 Maximum Video Modes Bit Depth Colors Vertical Refresh Supported Resolution 640x480 24 bit 16M color 100 Hz 800x600 24 bit 16M color 100 Hz 1024x768 24 bit 16M color 100 Hz 1280x1024 24 bit 16M color 75 Hz 1600x1200 16 bit 65k color 60 Hz Ethernet Controller The 82571EB dual Giga bit Ethernet controller provides a pair of 10 100 1000baseT Ethernet interfaces The 82571EB contains both the MAC and the physical layer The RJ 45 connectors on the module s front panel provide auto sensing for 10Base T 100Base and 1000Base TX connections Each RJ 45 connector has two indicator lights When mounted vertically the top light is the link activity light and the bottom light the one closer to the COM ports is the 10Base T 100Base TX indicator When it is off the connection is 10Base T when it is on the connection is 100Base TX When the Ethernet is switched to the rear optional PO no lights are available to indicate link or speed The use of the XVME 990 is required to connect RJ 45 cables to the rear of the XVME 6200 processor boards Memory Layout Basic Memory Regions There are five basic regions of memory in the system memory below 1 MB memory between 1 MB and the Top of Low Memory TOLM register memory between the TOLM register and 4 GB memory above 4 GB and the high PCI memory range between the top of main memory and 64 GB The high PCI memory range is added with the MCH and was not available in previous
2. Installation and Setup Jumper and Switch Settings The following table Lists XVME6200 jumpers their default positions and their functions SW2 On the back side of the module See Fig 2 X Position Setting Description SW2 1 ON VGA Front ON Back off select SW2 2 OFF RTCRST resets RTC when on SW2 3 OFF NC SW2 4 OFF NC SW3 On the back side of the module See Fig 2 X Position Setting Description SW2 1 OFF VRSYSRESET to SW VRSYSRESET SW2 2 OFF MROUT to VMEREST SW2 3 OFF VDB27 to pull SW2 4 ON MROUT wired to Front panel reset SW2 5 OFF VMESYSFAIL_CNT to GND SW2 6 OFF System Controller enabled Pullup to VBGSIN SW2 7 OFF VSYSRESETX ot VSYSRESET SW2 8 OFF VSYSRESETX to pullup JP1 Top side of the module See Fig 2 X IN Connects Front Panel to GND JP2 Top side of the module See Fig 2 X IN Connects battery Powering CMOS Setup Storage P4 Top side of the module See Fig 2 X Position Setting Description 1 2 ON RXDO to RXD2320 default 3 4 OFF RXDO to RXD422 5 6 OFF RXDO to RXD485 P5 Top side of the module See Fig 2 X Position Setting Description 1 2 ON DSROC to DSROC 485RXD 2 9 OFF 485RXD to DSROC 485RXD 4 5 ON RXDOC to RXDOC 485RXD 5 6 OFF 485RXD to RXDOC 485RXD 7 8 ON TXDOC to TXDOC 485TXD 8 9 OFF 485TXD to TXDOC 485TXD 10 11 ON DT
3. eee 3 27 Software Support esses 1 6 specifications hardware ueste 1 10 Switch settings esee 2 2 System resources eeeeeeeeeee 3 43 4 5 Universal Serial Bus USB port 2 8 5 7 Universe chip 4 5 4 7 4 8 4 10 VGA connector eeseseeee 2 7 5 10 VME interface s earnen in 4 5 VMEbus compliance ee 1 10 InterfaCe ds ss dee tbe bte eerta 1 5 interrrupt handling 4 6 interrupt generation 4 7 reset options 4 7 VMEbus connectors esses 2 11 VMEbus master interface 3 44 VMEbus slave interface 3 45 VMEbus system resources 3 43 watchdog timer eee 1 5 watchdog timer register ss 2 3 XVME 9000 EXF eere 1 10 XVME 973 1 see 1 3 1 10 5 1 XVMBE 973 5 i Bein gs EE Ne Pos ie EES 1 10 XVME 976 eee 1 5 1 10 XVMB 9071 etate 1 3 1 10 XV ME 979 EE EE sedie reda 1 3 1 10
4. Keyboard Mouse KEYBD MOUSE Display cable VGA USB PMC Note The floppy drive and hard drive are either cabled across P2 to an XVME 977 or an XVME 979 mass storage module or they are connected to the XVME 990 1 or XVME 990 2 board Refer to Chapter 5 for more information on the XVME 990 Enabling the PCI Ethernet Controller Loading the Ethernet Driver To enable the Ethernet controller you must load the applicable Ethernet driver for your operating system from the Documentation and Support Library CD included with the XVME 6200 For best results always use the supplied drivers Ethernet RJ 45 10 100 1000 BaseT Connector P12 2 20 Installation and Setup Table 2 23 RJ 45 10 100 1000 BaseT Connector Pin out 2 21 Programming Chapter 3 BIOS Setup Menus The XVME 6200 customized BIOS is designed to surpass the functionality provided for normal PCs The custom BIOS allow access the value added features on the XVME 6200 module without interfacing to the hardware directly Use the BIOS setup to control the two Gigabyte Ethernet ports to front or rear Vita 31 1 or rear Ethernet XVME 990 required connectors Use the setup to select front or rear Video output XVME 990 is required for this connection Chapter 4 Programming Memory Map The preliminary memory map of the XVME 6200 as seen by the CPU is shown below The I O designation refers to memory which is viewed as part of the AT bus or as part of VMEbus d
5. Programming INTEL MOTOROLA Low Byte High Byte High Byte Low Byte Figure 4 1 Byte Ordering Schemes Note The two architectures differ only in the way in which they store data into memory not in the way in which they place data on the shared data bus The XVME 6200 contains a Universe chip that performs address invariant translation between the PCI bus Intel architecture and the VMEbus Motorola architecture and byte swapping hardware to reverse the Universe chip byte lane swapping Contact Tundra at www tundra com for a PDF version of the Universe manual Figure 4 2 shows address invariant translation between a PCI bus and a VMEbus Pentium Register 32 bit Address M M 1 M 2 M 3 XVME 689 690 VMEbus Figure 4 2 Address Invariant Translation Notice that the internal data storage scheme for the PCI Intel bus is different from that of the VME Motorola bus For example the byte 78 the least significant byte is stored at location M on the PCI machine while the byte 78 is stored at the location M 3 on the VMEbus machine Therefore the data bus connections between the architectures must be mapped correctly 4 8 Programming Numeric Consistency Numeric consistency or data consistency refers to communications between the XVME 6200 and the VMEbus in which the byte ordering scheme described above is maintained during the transfer of a 16 bit or 32 bit quant
6. Storage Devices Hard Drive Floppy Compact PCI and On Board Drive EIDE and Floppy Drives The XVME 6200 primary IDE and floppy drive signals are routed through the P2 connector inner three rows available in a legacy 96 pin back plane providing a simplified method of connecting up to two IDE devices and one external floppy drive The secondary IDE master signals support the optional on board hard drive or on board Compact Flash site and the secondary IDE slave signals are not supported When used with the XVME 977 and or the XVME 979 mass storage modules the IDE devices and floppy drives do not need to be located next to the processor Using the supplied six inch ribbon cable which connects the XVME boards J2 VME backplane connectors the XVME 977 or the XVME 979 can be installed up to four slots away from the XVME 6200 on the VME backplane This allows greater flexibility in configuring the VMEbus card cage Introduction For applications that require mass storage outside the VMEbus chassis the XVME 990 rear transition module plugs onto the VMEbus J2 connector This module provides industry standard connections for IDE and floppy signals One floppy drive can be connected to the XVME 990 This drive may be 2 88 MB 1 44 MB 1 2 MB or 720 KB 360 KB in size For more information on the XVME 990 refer to Chapter 5 Core 2 Duo amp Core Duo uBGA479 um 1 5GHz to 2 18 GHz 857 MHz F58 VGA P2 CK409B ITP clock FLEX
7. Parallel Port 1 note 1 Available VGA EGA2 Available Primary Floppy disk controller Primary IDE Controller Generates CS3 Serial port 1 note 1 Industry Pack IP VO Industry Pack IP ID ELCR1 Edge or level triggered ELCR2 Edge or level triggered PCI configuration address register note 4 Reset Control Register PCI configuration data register note 4 Note 1 The serial and parallel port addresses may be changed or the port may be disabled Therefore these address maybe used for some applications and not for others Note 2 Reference the Intel 7520 datasheet for detailed information Note 3 Reference the Intel 6300ESB datasheet for detailed information Note 4 Reference The PCI local bus specification rev 2 3 6300ESB datasheet for PCI configuration information 4 2 IRQ Map INT Function IROO System Timer IRQ1 Keyboard IRQ2 Interrupt Cascade reserved IRQ3 COM2 IRQ4 COM1 IRQ5 Ethernet 1 IRQ5 PCI Expansion to PMC 2 IRO6 Floppy IRQ7 Parallel Port LPT1 IRO8 Real Time Clock IRQ9 Universe IID IRQ9 PCI X Video IRQ10 Onboard PMC X IRQ11 PCI Expansion to PMC 1 IRQ11 Ethernet 2 IRQ12 Mouse IRQ13 Math Coprocessor reserved IRQ14 Primary IDE IRQ15 Secondary IDE Programming The above interrupt mapping is one possible scenario The user or operating system may choose a different mapping for some of these i
8. Pentium Register 32 bit VMEbus Byte swapping Hardware Address M M 1 M 2 M 3 VMEbus Figure 4 4 Maintaining Address Consistency Notice that the data byte at each address is identical To achieve this the data bytes need to be swapped as they are passed from the PCI bus to the VMEbus To maintain address consistency enable the byte swapping buffers by setting bits 6 and 7 of the Flash Paging and Byte Swap register register 234h to 0 see p 2 5 4 10 Rear Transition Module Chapter 5 XVME 990 Rear Transition Module The XVME 990 rear transition module is available in two configurations a XVME 990 1 with the PO connector and the User I O connector and a XVME 990 2 without the PO connector and the User I O connector This module can be used to connect to external not in the rack hard drive floppy drives or to the XVME 977 or XVME 979 mass storage units Please consult the separate XVME 977 and XVME 979 manuals for more information on those products It should be noted that the XVME 973 and XVME 974 rear transition modules can be used with the XVME 6200 If one of these RTMs are used with the XV ME 6200 some functions normally available at the rear or will not be available The XVME 990 Drive Adapter Module is used to connect an external DVD CD ROM or hard drive and a floppy drive or use the SATA interface to your XVME 6200 module It has a single edge connector labeled P2 which connects to the P2 backplane connec
9. shield ground drain wires alone are not adequate VME panel mount connectors that provide interface to external cables e g RS232 USB keyboard mouse etc must have metal housings and provide direct connection to the metal VME chassis Connector ground drain wires are not adequate Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the components used structural parts printed circuit boards connectors batteries etc are capable of being recycled Final disposition of this product after its service life must be accomplished in accordance with applicable country state or local laws or regulations Table of Contents Table of Contents Piu opi EE H H M N i Tableof C Ontents se se v Table of FirureS ninien R ee ee AE NE ei e ede AAA tere vii Chapter 1 InitrodUucll nh eiie dime de dici de De GE ee De ae inva Ge de be Ke Saadia aa AA de 1 1 Module Features ss ee ells away be ple Ree eene e mk ee Ee ee kg se deans 1 1 Architecture i RE ecce eate et io ent hee ee ineo TER ud GE eet eene etude 1 2 XVME 6200 Memory Map iese sesse esse ee esse dese dee ee ge ee ee Ge de ee Ad ee a ee ee aab ei 1 4 XVME 06200 I O Map itr te e rre pex e dee EE OR N hens 1 5 Intetrupt USape 255 ced on Aire tee m crue o oreste dp tee Io dele EE eere cede Peers 1 6 Software Support ce
10. 2 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 D D D D D 3 PMC RSVD PN2 52 4 E PMC RSVD PN2 54 Z Z UO 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Z 5 5 5 IDSEL l D 30 29 D AD 24 V 23 N o AD G G N 1 3 3V 28 AD 20 6 64 CPU Fan Power Connector The fan 12 V and 5 V supplies are protected with a polyswitch This device will open up if 12 V or 5 V is shorted to GND Once the shorting condition is removed the polyswitch will allow current flow to resume 5 NC 5 N 6 NC ACK64 6 6 D D 1 1 1 8 3V D 3V D 4 3 0 N 29 30 31 32 Table 2 21 CPU Fan Power Connector Pinout Pin Signa 12V fused 5V pullup 2 18 Installation and Setup Installing the XVME 6200 into a Backplane This section provides the information necessary to install the XVME 6200 into the VMEbus backplane The XVME 6200 is a double high single slot VMEbus module Note Xembedded modules are designed to comply with all physical and electrical VMEbus backplane specifications of VME64x Note The XVME 6200 is available from the factory in two basic configurations with PO and without PO The without PO would normally be used in a legacy system since most of these racks are equipped with a stiffener bar in the PO location Also note that to use the extended featu
11. Hardware The VMEbus can be used to communicate to either Intel based modules or a Motorola based modules these two companies have created data transaction that use different byte ordering in their data storage A hardware approach to swapping these byte orders is a faster solution when compared to a software only byte swapping method Software selectable byte swapping hardware is integrated into the XVME 6200 to allow for the difference between the Intel and Motorola byte ordering schemes allowing easy communication over the VMEbus The byte swapping package incorporates several buffers either to pass data straight through or to swap the data bytes as they are passed through Note The configurable byte swapping hardware does not support 64 bit byte swapping If needed this should be implemented through software Byte Ordering Schemes The Motorola family of processors stores data with the least significant byte located at the highest address and the most significant byte at the lowest address This is referred to as a big endian bus and is the VMEbus standard The Intel family of processors stores data in the opposite way with the least significant byte located at the lowest address and the most significant byte located at the highest address This is referred to as a little endian or PCT bus This fundamental difference is illustrated in Figure 4 1 which shows a 32 bit quantity stored by both architectures starting at address M 4 7
12. Intel Core2 Duo processors have a new micro architecture but remains software compatible with previous members of the Intel microprocessor family The Intel Core2 Duo has a 4MB L2 cache which boosts performance The two cores can run independent processes potentially doubling performance With a junction temperature range of 0 to 100C the Intel Core2 Duo processors are capable of with standing a great deal of thermal stress The 17 watt L7400 Intel Core2 Duo 1 5Ghz processors provide low power options and T7400 Intel Core2 Duo 2 16GHz processor provide higher performance options PCI Local Bus Interface The Intel E7520 6300ESB chipset supports the Intel Core2 Duo processors with up to 400MHz front side bus The XVME 6200 incorporates one PCIe and PCI X buses which is used to service the two Intel 82546EB Ethernet controllers and the on board PMC site The PMC site supports both 32 bit 33MHz and 64 bit 66MHz bus speeds with 5V I O support The XVME 6200 supports on PCI bus for 32 bit 33MHz operation this bus services the PCI to VME bridge chip known as the tundra Universe II chip and the 38 pin expansion connector used to connect to the XVME 9076 Dual PMC carrier module PCI X or PCI extended is an enhanced version of PCI Peripheral Component Interconnect computer bus Although PCI X is backward compatible with traditional 3 3V PCI 2 0 devices and systems this specification implements additional features and performance i
13. Intermitted hard drive functions can be traced back to the use of a standard 40 conductor 40 pin cable The IDE controller supports enhanced PIO modes which reduce the cycle times for 16 bit data transfers to the hard drive Check with your drive manual to see if the drive you are using supports these modes The higher the PIO mode the shorter the cycle time As the IDE cable length increases this reduced cycle time can lead to erratic operation As a result it is in your best interest to keep the IDE cable as short as possible The PIO modes can be selected in the BIOS setup The Auto configuration will attempt to classify the connected drive if the drive supports the auto ID command If you experience problems change the Transfer Mode to Standard Caution 5 6 Rear Transition Module The total cable length must not exceed 12 inches Also if two drives are connected they must be no more than six inches apart USB Port Connector USB provides an expandable hot pluggable Plug and Play serial interface that ensures a standard low cost connection for peripheral devices Devices suitable for USB range from simple input devices such as keyboards mice and joysticks to advanced devices such as printers scanners storage devices modems and video conferencing cameras USB 2 0 has a raw data rate at 480Mbps and it is rated 40 times faster than its predecessor interface USB 1 1 which tops at 12Mbps USB port 1 is av
14. fabric connections on the back plane Fig 5 4 2 RJ 45 Connector Table 5 11 RJ 45 10 100 1000 Base T Connector Pin out 5 9 Rear Transition Module COM 2 Communications port 2 is a RS 232 serial communication port using a standard DB 9 connector Figure 5 5 Com 2 DB 9 Table 5 12 Showing pin out of DB 9 to VMEbus P2 DB 9 Pin Location Signal Name VMEbus P2 Pin Location 1 DCD2 Row a 12 2 RXD2 Row a 11 3 TXD2 Row a 10 4 DTR2 Row a 9 2 GND Row a 8 6 DSR2 Row a 7 7 RTS2 Row a 6 8 CTS2 Row a 5 9 RD Row a 4 VGA Connector The video is BIOS selectable and is available on either the front panel or out the VMEbus P2 The table below shows the pin out of the standard video connector and also the VMEbus P2 pin out for the rear access of video The XVME 990 rear transition module connects to the rear of the VMEbus in the same slot as the XVME 6200 and allows for standard connections to off board devices The XVME 990 provides a standard SVGA connector for rear access Figure 5 6 Table 5 13 VGA Connector Pin out to VMEbus P2 SVGA Signal VMEbus P2 Pin out N C Row d Pin 31 Row d Pin 31 5 10 Rear Transition Module 9 25MIL VIDA N C 10 GND Row d Pin 31 11 NC N C 12 LDDCDAT Row d Pin 26 13 HSYNC Row d Pin 23 14 VSYNC Row d Pin 24 15 LDDCCLK Row d Pin 25 LPT 1 The 26 pin header connector brings out the signals for the LPT
15. of 80h amp 86h consecutively then it writes to WDT TIMEOUT bit 9 hence the value of 0200 MACRO UNLOCK W B D7EFE7FC 80 W B D7EFE7FC 86 W w D7EFE7FC 0200 UNLOCK 2 Now load Preload2 counter first command defines macro 2nd one executes it MACRO PRELOAD2 W B D7EFE7FC 80 W B D7EFE7FC 86 W d D7EFE7F4 0AAAA PRELOAD2 3 Enable WDT and run in free running mode with preload2 PW B is PCI config space write byte command PW B 0 1D 04 68 06 4 To kick the watchdog and prevent it from resetting you just need to disable and enable via WDT ENABLE Every time you do this Preload Value 2 is reloaded into the down counter and it starts over counting down PW B 0 1D 04 68 04 Disable PW B 0 1D 04 68 06 Re enable NOTE The 6300ESB Watchdog has another mode called Watchdog Timer Mode Offset 68h of device where it utilizes a two stage timer scheme and the first stage fires an interrupt while the 2nd one drives WDT TOUT This mode is not supported contact Xembedded Support for more information Introduction Software Support The XVME 6200 is fully PC compatible and will run off the shelf PC software but most packages will not be able to access the features of the VMEbus To solve this problem Xembedded has developed extensive Board Support Packages BSPs that simplify the integration of VMEbus data into PC software applications Xembedded s BSPs provide users with an efficient high level interface between their applica
16. 00 Hz peak to peak displacement 5 g maximum displacement 2 5 g acceleration maximum acceleration Emissions EN 55022 EN 55022 Immunity EN 50082 2 EN 50082 2 The XVME 6200 will meet the following environmental requirements Introduction Hardware Specifications Characteristic Specification Power Specifications 5 4 A typical 10 5 A maximum Voltage Specifications 5V 12V 12V all 5 2 5 Only 5VDC required CPU speed Intel Core2 Duo and Core Duo Low 2 16 GHz T7400 Power Processor L2 Cache Intel Core2 Duo and Core Duo Low MB Power Processor Onboard memory SDRAM up to 8 GB dual channel 200 pin SODIMM Graphics Controller 1600 x 1200 maximum resolution 24 bit color maximum 4 MB video memory Ethernet Controllers 2 Intel 82571EB 10 100 1000Base TX Gigabit Ethernet RJ 45 Mass Storage Integrated SATA 150 Controller SATAO and SATA1 via P2 EIDE Ultra DMA 100 interface 2 channels via P2 One 1 8 on board EIDE via optional carrier module Compact Flash One on board Compact flash site via optional carrier module Floppy Drive Via P2 to XVME 977 PMC Site On board 66 MHz 64 Bit PMC PCI X with front and PO I O Access Site is 3 3V interface level Optional 64 bit 133MHZ sites available via XVME 9076 2 sites total 3 AD1981B AC97 CODEC Line Level Stereo Input and Output Via P2 USB Two USB 2 0 via Front panel Two USB 2 0 via P2 RS 232C 16550 compatible 3 COM1 Com 2 Com3
17. 000000 3 EF Donun ou0on0on 0000000 C i EE OE E N ME 4 e m DUQODUDDDUDDOUUDODUDU D i j V A LODODODOROCEODRIOOOCODCODOROU OOOCEDREGCROREGOROREDRDOODO H Tn 00000000000D00DODDODODDODO ODODO 1 DDOREOOGIOGOROOGQDOEOOOQO LM Fig 2 1 shows the jumper switch and connector locations on the XVME 6200 2 1 Installation and Setup Fig 2 X shows the jumper switch and connector locations on the back side of the XVME 6200 OO uu uu ED Niue DON M m gt dek ME aa SEXE SERE N N ES Art is D Orl 2 IC O O TII n DULL LRL E ccn SEE okoo i B OO d Spee ENE oe TO D a SES M ar d OBO conc HNN LL As n us 15 l E mr oer or u60 u58 5 57 D m w a YC Enn o mw l l q n Bm nuni J 15 15 15 SEED NTO oreo m QUUD 1 prm TT 5 o 5c 3300 T co
18. 000C0000 000C7FFF 32K VGA BIOS 000A0000 000BFFFF 128K VGA DRAM MEMORY 00000000 0009FFFF 640K DRAM See Intel 6300ESB data sheet for description for optional settings for memory holes or gaps within Memory map area The PCI devices are located at the very top of memory just below the system BIOS XVME 6200 I O Map I O map for the XVME 6200 contains I O ports of the IBM AT architecture plus some additions for PCI I O registers and Xycom specific I O registers Hex Range 000 01F 020 021 022 023 024 02D 02E 02F 030 03D 040 042 043 O4E O4F 050 052 060 06F 070 07F 080 091 92 93 9F 0A0 0B1 0B2 0B3 OBA OBF 0CO O0DF OFO OF1 OF2 OFF 170 177 1F0 1F7 219 234 235 277 278 27F 280 2F7 2F8 2FF 300 36F 376 378 37F 380 3BF 3C0 3DF 3E8 3EF 3F0 3F5 3F6 3F8 3FF 4DOh 4D1h CF8 CF9 Device DMA controller 1 8237A 5 equivalent Interrupt controller 1 8259 equivalent Available Interrupt controllers LPC SIO More interrupt controllers Timer Counter 8254 2 equivalent Timer Counter write only LPC SIO Timer Counter 8742 equivalent keyboard Real Time Clock bit 7 NMI mask DMA page register Fast GateA20 and Fast CPU Init DMA page register Interrupt controller 2 8259 equivalent Power Management Interrupt controller 2 8259 equivalent DMA controller 2 8237A 5 equivalent FERR IGNNE Interrupt Controller N A N A Secondary IDE Controller Generates CS1 Primary IDE Controller Genera
19. 700 Channel amp Voltage Regulator IMVP Vi DDR2 SDRAM 200 pin SODIMM DOR 400 MHz PCle x1 E7520 DDR2 ECC SDRAM VGA MCH 200 pin SODIMM PLX 512MB 1 2 4GB SM722 8111 Poea PCle x4 1 8inch IDE PCI X bus Hard Drive or PMC Compact Flash ME PCI Mezzanine P2 IDE 6300ESB 82571EB HD CD j 10710071000 VO Controller Hub imi Pca TEER SATAOP2 P2 ME ene asem je TERT it VITA 31 1 USB0 amp 1 front panel 1 mus e ACST CODEC P2 PCI bus FWH Universe IID Flash PCI to VME BIOS LPC Bus interface SCH3114 Super VO F52 keybeard cow coma I Mu Ed Mouse Front Panel Reset Abort Front Pane FrontPane P2 LEDs Switch Byte Swapping VMEbus buffers VMEbus P1 and P2 Introduction Caution The IDE controller supports enhanced PIO modes which reduce the cycle times for 16 bit data transfers to the hard drive Check with your drive manual to see if the drive you are using supports these modes The higher the PIO mode the shorter the cycle time As the IDE cable length increases this reduced cycle time can lead to erratic operation As a result it is in your best interest to keep the IDE cable as short as possible The PIO modes can be selected in the BIOS setup The Auto configuration will attempt to classify the connected drive if the drive supports the auto ID command If you experience problems change the Transfer Mode to Standard Caution The total cable length must
20. A15 RSVBUS 3 24 GND A07 IRQ7 A14 MERE SG A13 RSVBU4 26 GND A05 IRQ5 A12 28 GND Aos mot At 30 GND A0 or A08 Some pins in columns Z and D are use internally as test points these are denoted by italics These pins are not intended to drive any external devices and MUST not be used for any purpose 2 14 Installation and Setup VMEbus P2 Connector Row z Row b Row c Pin Number SATA_TXPO 5V IDERST1 GND HDO NC i3 SATA TXNO VME RETRY HD1 PSR mi l a RI2 A24 SATA_RXNO CTS2 A25 HD2 PPACK HD3 PPBUSY NIO GND RTS2 A26 SATA_RXPO DSR2 A27 HD4 PPE HD5 PSELECT CO Oo GND GND A28 SATA TXP1 DTR2 A29 HD6 PAUTOFEED HD7 PPERROR 15 SATA RXP1 AUD_GND VDi7 HDi3 PDS VD25 IOCS16 NC VD31 IDEATP NC Table 2 17 VMEbus P2 Connector 2 15 Installation and Setup 38 pin PCle connector P6 Pin Number Signal Pin Signal Num ber GND GND PCIE_XMT_LNO_DN PCIE_RCV_LNO_DN PCIE XMT LNO DP PCIE RCV LNO0 DP 2 4 6 GND 8 GND 1 1 1 1 PCIE XMT LNI DN PCIE RCV LNI DN PCIE XMT LNI DP PCIE RCV LNI DP 0 2 GND 4 GND PCIE XMT LN2 DN 6 PCIE RCV LN2 DN 0 PCIE XMT LN2 DP GND PCIE XMT LN3 DN PCIE XMT LN3 GND GND GND GND CK 100M PCIE DP CK 100M PCIE D GND GND center bus GND center bus GND center bus ND
21. Acromag kd THE LEADER IN INDUSTRIAL VO XVME 6200 6U VME Intel Core 2 Duo Processor Board USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 980D Revision Description A Init B Updates C and D Updates Part Number 746200 Trademark Information Brand or product names are trademarks or registered trademarks of their respective owners Intel and Pentium are registered trademarks and Celeron is a trademark of Intel Corporation Windows Windows 2000 and Windows XP are registered trademarks of Microsoft Corporation in the US and in other countries Copyright Information This document is copyrighted by Xembedded Incorporated Xembedded and shall not be reproduced or copied without expressed written authorization from Xembedded The information contained within this document is subject to change without notice Xembedded does not guarantee the accuracy of the information WARNING This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures Warning for European Users Electromagnetic Compatibility European Union Directive 89 336 EEC requires that this apparatus comply with relevant
22. Com 1 can be configured for RS 232 422 485 Com 2 and 3 are RS 232 only Parallel Interface EPP ECP compatible 1 Keyboard and Mouse Via Front Panel Regulatory Compliance European Union CE Electromagnetic Compatibility 89 336 EEC RoHS Compliant product available 1 14 Introduction VMEbus Specification VMEbus Compliance Complies with VMEbus Specification ANSI VITA 1 1994 A32 A24 A16 D64 D32 D16 D08 EO DTB Master A32 A24 A16 D64 D32 D16 D08 EO DTB Slave R 0 3 Bus Requester Interrupter I 1 I 7 DYN IH 1 IH 7 Interrupt Handler SYSCLK and SYSRESET Driver PRI SGL RRS Arbiter RWD ROR bus release Form Factor DOUBLE 233 7 mm x 160 mm 9 2 x 6 3 System Configuration and Expansion Options Tables Table 1 2 XVME 6200 CPU configurations Ordering CPU Type Number XVME 6200 8XY Intel 1 5GHz L7400 XVME 6200 9XY Intel 2 16GHz T7400 Handle and PO configurations Memory configurations total on board memory Y 1 VME 64 IEEE 1101 1 Std legacy handles w o X 1 for 512MB ECC DRR2 SDRAM VMEbus PO Y 2 VME 64 IEEE 1101 10 Compact PCI type handles X z2 for 1GB ECC DRR2 SDRAM w o VMEbus PO Y 2 3 VME 64 IEEE 1101 1 Std legacy handles with the X 2 3 for 2GB ECC DRR2 SDRAM VMEbus PO Y 4 VME 64 IEEE 1101 10 Compact PCI type handles Xz4 for 4 GB ECC DRR2 SDRAM with the VMEbus PO X25 for 8 GB ECC DRR2 SDRAM Note Some features on t
23. Drive Optional module XVME 913 The on board hard drive resides as a master on the secondary EIDE port The XVME 913 is a kit of parts including 1 8 hard drive cable 4 brackets screws and standoffs There are no unique drivers required The XVME 6200 can be booted from the on board hard drive if configured in the BIOS Boot menu NOTE The XVME 6200 module can accept either an on board 1 8 hard drive XVME 913 or the Compact Flash carrier XVME 912 but not both Compact Flash Site Optional module XVME 912 The compact flash socket on the optional carrier module will support type I or type II Compact Flash cards The compact flash resides as a master on the secondary IDE port There are no unique drivers required The XVME 6200 can be booted from the compact flash drive if configured in the BIOS Boot menu NOTE The XVME 6200 module can accept either an on board 1 8 hard drive XVME 913 or the Compact Flash carrier XVME 912 but not both 1 8 Introduction VMEbus Interface The XVME 6200 uses the PCI local bus to interface to the VMEbus via a PCI to VME bridge device Tundra Universe IID The VMEbus interface supports full DMA to and from the VMEbus integral FIFOs for posted writes block mode transfers and read modify write operations The interface contains one master and eight slave images that can be programmed in a variety of modes to allow the VMEbus to be mapped into the XVME 6200 local memory This makes it easy to con
24. ERA de RR RAK EER AA GERAAK AN KERR AAR AE kk Rae dee 3 1 Chapter 4 ProdramImIN d ie se sees imde es eed Rd eN ac dee vd we vee ed Ed AN o Ne ed ee ee 4 1 Memory Map MEE 4 1 I O Map EA EE IN De rre irte ti n P a e ET 4 1 IROQ Mape OR N e ie tet pe pb AE RE EO 4 3 PCT Device Map eene Urso ei e t elt EE tre ti tee Ven EE deg o 4 4 basia AMT 4 5 Software Selectable B yte Swapping Hardware seen eene 4 7 Chapter 5 XVME 990 Rear Transition Module esse ees ese ee KERR RE EER Ge ERK RR RR ER RR KERK Re EER 5 1 COMME CLONS m EES EE Ge ee ee EER eg Re Ee cough SE ea Eg ee ee Ee Re ee Ge GE Ge ee Es Ee ee 5 2 Serial ATA hard drive Interfac 1 caede eee Ee Ese ede ine dean tee to Pe de unie 5 3 vi Table of Contents Table of Contents Table of Figures Figure 1 1 XVME 6200 Block Diagram eise see esse dese ese ee ke ee ge ee ee ee ee de ke Re ee ee 1 13 Figure 4 1 Byte Ordering Schemes ute edd Re nel Ke e tee espe days 4 8 Figure 4 2 Address Invariant Translation eese eene nene 4 8 Figure 4 3 Maintaining Numeric Consistency eeseeeeeeeeeeeeeeeee neret 4 9 Figure 4 4 Maintaining Address Consistency eessesseeeeeeeeeee eene nre 4 10 Figure 5 1 XVME 990 X Installation XVME 990 001 shown eee 5 1 vii Introduction Chapter 1 Introduction The XVME 6200 VMEbus Intel Core2 Duo and Core Duo PC compatible VMEbus processor module combines th
25. I X or PCI extended is an enhanced version of PCI Peripheral Component Interconnect computer bus Although PCI X is backward compatible with traditional PCI devices and systems this specification implements additional features and performance improvements include 3 3V signaling increased speed grades and adaptation to other form factors PCI X effectively doubles the speed and amount of data exchanged between the computer processor and peripherals PCI X bus was designed for and is ideally suited for server cards such as FPGA DSP Fibre Channel RAID high speed networking and other demanding devices If a standard PCI PMC card is fitted on the XVME 6200 PMC site the on board PCI X bus reverts to the PCI bus speed Additional PMC Expansion Options The XVME 6200 supports optional PMC PCI Mezzanine Card expansion using XVME 9076 expansion module The XVME 9076 provides two PCI Mezzanine Card PMC sites The XVME 9076 module is designed to plug directly into the XVME 6200 using the 38 pin expansion board connector 1 9 Introduction Watchdog Timer The XVME 6200 has a long duration watchdog timer which can count from 1 to 255 seconds or from 1 to 255 minutes The BIOS supports various system events which can be routed to the watchdog timer The timer when enabled can generate either an interrupt or a master reset depending on how the watchdog timer is configured Note The timeout range is from 1 0 second to 2 25 seconds it will typic
26. ITE EMC standards EMC compliance demands that this apparatus is installed within a VME enclosure designed to contain electromagnetic radiation and which will provide protection for the apparatus with regard to electromagnetic immunity This enclosure must be fully shielded An example of such an enclosure is a Schroff 7U EMC RFI VME System chassis which includes a front cover to complete the enclosure The connection of non shielded equipment interface cables to this equipment will invalidate European Free Trade Area EFTA EMC compliance and may result in electromagnetic interference and or susceptibility levels that are in violation of regulations which apply to the legal operation of this device It is the responsibility of the system integrator and or user to apply the following directions as well as those in the user manual which relate to installation and configuration All interface cables should be shielded both inside and outside of the VME enclosure Braid foil type shields are recommended for serial parallel and SCSI interface cables Where as external mouse cables are not generally shielded an internal mouse interface cable must either be shielded or looped 1 turn through a ferrite bead at the enclosure point of exit bulkhead connector External cable connectors must be metal with metal back shells and provide 360 degree protection about the interface wires The cable shield must be terminated directly to the metal connector shell
27. ROC to DTROC 485TXD 11 12 OFF 485TXD to DTROC A85TXD 2 3 Installation and Setup Registers The XVME 6200 modules contain the following Xembedded defined I O registers 218h 219h 233h and 234h Register 218h Abort CMOS Clear Register This register controls the abort toggle switch and allows you to read the CMOS clear jumper main board J21 Table 2 3 Abort CMOS Clear Register Settings cet Signal Re fw 0 RESERVED Resev 1 RESERVED Reewd 2 RESERVED Reewd 3 RESERVED Reewd O ABORT STS 1 Abort toggle switch caused interrupt R 5 ABORT CLR 0 Clear and disable abort R W 1 Enable abort 6 RESERVED Reseved 000 o 7 CLRCMOS 0 Clear CMOS 1 CMOS okay 2 4 Installation and Setup Register 219h Flash Control Register This register controls the following LEDs and signals Table 2 4 LED BIOS Register Settings Bit LED Signal FAULT 0 Fault LED on 1 Fault LED off 1 PASS 02 PASS LED off 12 PASS LED on N A N A N A RESERVED Reserved RESERVED Reserved 6 RESERVED Reserved 7 RESERVED Reserved Register 233h Watchdog Timer Register This register controls watchdog timer operation Table 2 5 Watchdog Timer Register Settings Bit Signal 0 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved 5 MRESET EN 1 Timeout generates 0 Timeout gene
28. ailable on the front panel using a standard connector as shown in Figure 2 10 below The other two USB ports USB 2 and 3 are routed out the VMEbus P2 connector and can be accesses either directly off the VMEbus P2 connector using the pin assignment shown in Fig 5 3 and table 5 4 The USB 5 V supplies are protected with a polyswitch This device will open up if 5 V is shorted to GND Once the shorting condition is removed the polyswitch will allow current flow to resume Table 5 7 USB Port Connector Pin out Figure 5 3 showing the USB connector Table 5 8 USB Port Connector Pin out from P2 P2 row z 17 USB3 GND P2 row z 22 GND P2 row z 24 P2 row z 25 USB2 GND 5 7 Rear Transition Module PO VMEbus connector This connector is used to distribute the on board PMC rear I O and the rear Ethernet ports if Vita 31 1 is not in use Table 5 9 showing pin out of the VMEbus PO Pin RowA Row B Row C Row D Row E Row F Numb er GN MDIAX0 MDIAXO MDIAX2 MDIAX2 Q MDIAX1 MDIAXI MDIBX0 MDIBXO MDIBX1 MDIBXI MDIAX3 MDIAX3 MDIBX2 MDIBX2 MDIBX3 MDIBX3 T ZZ 4 6 NC NC USER VO Connector This is a 68 pin SCSI type connector that brings out the rear PMC site I O from the XVME 6200 PMC site to the PO to the XVME 990 PO to this USER VO NC NC PMC IO12 PMC_IO11 PMC_IO17 PMC_IO16 PMC IO22 PMC_IO21 MC_1027 Table 5 10 Showing pin out of the User I O
29. ally be 1 6 seconds USING THE WATCHDOG Timer The xvme6200 has a watchdog function on the Intel 6300ESB alias ICH or Southbridge The output of the watchdog function is the WDT_TOUT pin For this feature to work you must first have the correct PLD firmware loaded on the xvme6200 since WDT_TOUT goes through the PLD to drive system reset If you are in doubt about the state of this PLD logic contact Xembedded only Xembedded can update this firmware For specifics of the watchdog of the xvme6200 see the Intel 6300ESB I O Controller Hub datasheet from Intel There are multiple modes and various configurations This description only discusses the free running mode and how it was tested using a PCI debug tool called PCIscope http www tssc de index htm PCIscope has a debugger that let s the user interactively read write to PCI config registers and memory mapped locations hence the commands below Of course any debugger could do the same Following is a high level description of what your watchdog application driver would need to do to utilize the watchdog in free running mode Initially your application needs to get PCI bus dev fun of 6300ESB watchdog Device ID is 25ABh In our example below PCI bus dev fun is 00 1d 04 nn where nn offset The Preload2 register is memory mapped at Offsetbase 04h so the app needs to know what this is too via the PCI config space of the device our system was at D7EF_E7FO 1 When application in
30. center bus GND center bus PELLE LIED ED PMC Host Connectors PMC Host Connector 1 Table 2 19 XVME 6200 Daughterboard PMC Host Connector 1 Pin out Installation and Setup n O A ZINIO O N gt DIOIO aiziz X O o INTB INTC BUSMODE1 DEVSEL 5V G N N C2 Co C2 o CD 10 11 12 13 14 15 16 17 PCI RSVD14B ND PCI RSVD14A CICLK ND ND NT EQ 5V VO AD U 4 Q mE D gt 19 lt O Co ak D 1 olololols O Zh Als g N eo MI U U gt DIS NIY sie gt AD PAD 25 54 AD D R D 15 12 11 9 5 4 D 3 2 1 0 Q OJO ziz ojo lt O UJ m gt _BE 3 AD 22 AD 21 AD 19 5V V VO AD 17 N 40 41 42 43 5 6 7 8 9 0 1 2 3 5 6 7 8 9 0 1 2 3 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 C2 eo R Pin 5 6 7 vs o 10 d n 12 13 d 15 36 4 A EE 20 30 ES 32 Installation and Setup PMC Host Connector 2 Table 2 201 XVME 6200 PMC Host Connector 2 Pinout TRST PMC RSVD_PN2 34 T TDO T TRDY 3 3V G N STOP GN MS D D GND EET BUSMODE2 V IO C BET hae UJ Pim GND i BUSMODES GND FADUM FADIS zZ UO A A A T eo io lt 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 5 6 7 8 9 0 1
31. connector MC IO26 PMC 1O63 PMC IO62 PMC IO61 Pin Number Signal Name Pin Number Signal Name 1 PMC I O 1 35 PMC VO 2 2 PMC VO 3 36 PMC VO 4 3 PMC VO 5 37 PMC VO 6 4 PMC VO 7 38 PMC VO 8 5 PMC I O 9 39 PMC VO 10 6 PMC VO 11 40 PMC VO 12 7 PMC VO 13 41 PMC VO 14 8 PMC VO 15 42 PMC VO 16 9 PMC VO 17 43 PMC VO 18 10 PMC VO 19 44 PMC VO 20 11 PMC VO 21 45 PMC VO 22 12 PMC VO 23 46 PMC VO 24 13 PMC VO 25 47 PMC VO 26 14 PMC VO 27 48 PMC VO 28 15 PMC VO 29 49 PMC VO 30 16 PMC VO 31 50 PMC VO 32 17 PMC VO 33 51 PMC I O 34 18 52 PMC I O 19 GND using jumper 53 GND using jumper 20 PMC VO 35 54 PMC VO 36 T ZZ T Zi azzaz2Z u zzz g gsgsgsg oe EIEIEIEIEoEEEEIEIE oo Zz Z 5 8 Rear Transition Module 21 PMC VO 37 55 PMC VO 38 22 PMC VO 39 56 PMC VO 40 23 PMC VO 41 57 PMC VO 42 24 PMC VO 43 58 PMC I O 44 25 PMC VO 45 59 PMC VO 46 26 PMC VO 47 60 PMC I O 48 27 PMC VO 49 61 PMC VO 50 28 PMC VO 51 62 PMC VO 52 29 PMC VO 53 63 PMC VO 54 30 PMC VO 55 64 PMC I O 56 31 PMC VO 57 65 PMC VO 58 32 PMC VO 59 66 PMC VO 60 33 PMC VO 61 67 PMC I O 62 34 PMC VO 63 68 PMC VO 64 Ethernet RJ 45 Two Gigabyte Ethernet ports are available on the XVME 990 If the VMEbus has Vita 31 1 Capability the rear Ethernet ports can not be used they will conflict with the VMEbus switch
32. e high performance and ruggedized packaging of the VMEbus with the broad application software base of the IBM PC AT standard It integrates the latest processor and chipset technology The only difference between the various versions of the XVME 6200 is the CPU used The L7400 is the lowest power draw of any of our processors while maintaining a very high level of processing power The T7400 offers the highest performance Module Features The XVME 6200 offers the following features Intel Core2 Duo Processor All processor models can be configured with 1GB to 8GB SDRAM show as total memory on board Level 2 cache on Intel Core2 Duo is 4MB T7400 and L7400 Video controller with 4MB of VRAM Silicon Motion 722 Enhanced IDE controller capable of driving two EIDE devices on P2 Compatible with X VME 977 Hard drive Floppy drive unit and XVME 979 Hard Drive DVD CDROM drive unit Two channels of SATA 150 out P2 Use the XVME 990 to provide the connectors needed to connect external SATA drives Floppy disk controller capable of driving one floppy drive on P2 Compatible with XVME 977 Hard drive Floppy drive unit or XVME 979 CD ROM DVD drive and Hard Drive with external drive Dual 10 100 1000 Base T Ethernet controllers with front panel RJ 45 connectors with isolated ground or selectable out the PO to support rear Ethernet or Vita 31 1 Type I II Compact Flash site using our XVME 912 optional carrier This mounts in the PMC site and d
33. e pin out of the standard video connector and also the VMEbus P2 pin out for the rear access of video The XVME 990 rear transition module connects to the rear of the VMEbus in the same slot as the X VME 6200 and allows for standard connections to off board devices The XVME 990 provides a standard SVGA connector for rear access Figure 2 9 Table 2 9 VGA Connector Pin out SVGA Signal Pin out GND Row d Pin 31 25MIL VIDA N C GND Row d Pin 31 NC N C a f 2 9 Installation and Setup USB Port Connector J5 USB provides an expandable hot pluggable Plug and Play serial interface that ensures a standard low cost connection for peripheral devices Devices suitable for USB range from simple input devices such as keyboards mice and joysticks to advanced devices such as printers scanners storage devices modems and video conferencing cameras USB 2 0 has a raw data rate at 480Mbps and it is rated 40 times faster than its predecessor interface USB 1 1 which tops at 12Mbps USB port 1 is available on the front panel using a standard connector as shown in Figure 2 10 below The other two USB ports USB 2 and 3 are routed out the VMEbus P2 connector and can be accesses either directly off the VMEbus P2 connector using the pin assignment shown in Fig 2 10 The USB 5 V supplies are protected with a polyswitch This device will open up if 5 V is shorted to GND Once the shorting condition is removed the polyswitch w
34. e the cable is only 64 pins the row b of this connector is not carried across but is bused on the VMEbus back plane ci IOCS16 NC DAC VSYNC QICIQ l Table 5 4 shows pin out of the interconnect of VMEbus P2 to P3 GND HDO VME_RETRY HD1 RR E 3 tes 45 Hb 6 Rt 4 Hb4 EIER E BREER 3v 5 4 Rear Transition Module 31 FWP GND FHS 32 FRDD 45V DCHG FDD1 Connector FDD1 connects a single 3 5 floppy drive Only one drive is supported Power for this external drive is not supplied by the X VME 990 Table 5 5 XVME 990 FDD1 Connector Pin out Pin Sia Pin Signal c OD AB z eo Oo oc1 9 GND FTKO 10 MOT 5 5 IDE1 Connector Rear Transition Module IDEI connects up to two hard drives primary master and slave Power for the drives is not supplied by the XVME 990 Table 5 6 XVME 990 IDE Connector Pin out 3 HO7 D Pin Signal 1 HDRSTDRV 2 GND 0 Ecl s up E DIOR GND IORDY ALE HDACK GND IRQ14 1IOCS16 13 3 11 HD 12 HD12 HD D 7 8 6 6 HD9 3 2 1 0 Dr Caution CS1P CS3P IDEATP It is recommended that only an 80 conductor 40 pin EIDE cable is used with the XVME 6200 This cable type has additional ground planes that can handle the faster interface speeds
35. epending on how the Universe is programmed XVME 6200 MEMORY MAP See Intel 6300ESB data sheet for a description for optional settings for setting memory holes or gaps within Memory map area The PCI devices are located at the very top of memory just below the system BIOS VO Map This Preliminary VO map for the XVME 6200 contains I O ports of the IBM AT architecture plus some additions for PCI VO registers and Xembedded specific VO registers Hex Range Device 000 01F DMA controller 1 8237A 5 equivalent 020 021 Interrupt controller 1 8259 equivalent 022 023 Available 025 02F Interrupt controller 1 8259 equivalent note 3 040 05F Timer 8254 2 equivalent 060 06F 8742 equivalent keyboard 070 07F Real Time Clock bit 7 NMI mask note 3 080 091 DMA page register note 3 92 Fast GateA20 and Fast CPU Init 93 9F DMA page register note 3 OAO OBF Interrupt controller 2 8259 equivalent note 3 0CO O0DF DMA controller 2 8237A 5 equivalent note 3 OFO N A OF1 N A OF2 OFF N A 4 1 170 177 1FO 1F7 219 234 235 277 278 27F 280 2F7 2F8 2FF 300 36F 376 378 37F 380 3BF 3C0 3DF 3E0 3EF 3F0 3F5 3F6 3F8 3FF 400 47F 480 4BF 4D0h 4D1h CF8 CF9 CFC Programming Secondary IDE Controller Generates CS1 Primary IDE Controller Generates CS1 Xembedded LED control register Byte Swap port Available Parallel Port 2 note 1 Available Serial Port 2 note 1 Available Secondary IDE Controller Generates CS3
36. erratic operation As a result it is in your best interest to keep the IDE cable as short as possible The PIO modes can be selected in the BIOS setup The Auto configuration will attempt to classify the connected drive if the drive supports the auto ID command If you experience problems change the Transfer Mode to Standard 28 ALE 30 GND HD12 HD2 HD13 HD1 HD14 HDO HD15 GND KEY NC Caution 5 2 Rear Transition Module Caution The total cable length for EIDE drives must not exceed 12 inches Also if two drives are connected they must be no more than six inches apart Use the SATA drive interface if longer cabling is required Serial ATA hard drive Interface The use of the XVME 990 rear transition module allows for connection to one or two SATA 150 drives Table 5 2 shows pin out of SATA interface VMEbus Signal Name SATA connector SATA Signal Name P2 Pin on P2 on the xvme 990 Fig 5 2 SATA connector Row z T ka IE z2 GND SATAlpin1 GND alrTTTTTTT qj ci Lx z4 GND CT SATA1 pind GND __ _ ze GND CT SATA1 pin 7 GND pza END ur rcc o grs o Zi0 GND SATA2pin1 GND _ SATA2 pin 4 GND SATA RXN1 SATA2 pin 5 SATA2 pin 7 GND SATA RXP1 SATA2 pin 6 The mating connector on the XVME 990 is Molex 67489 9005 SATA TXN1 _ SATA2 pin 3 P2 Connector The XVME 990 P2 connector connects directly to the XVME 6200 P2 connector throu
37. es for more system protection Caution When setting up slave images the address and other parameters should be set first Then only after the VMEbus slave image is set up correctly should the VMEbus slave image be enabled If a slave image is going to be remapped disable the slave image first then reset the address After the image is configured correctly enable the image again The VMEbus slave cycle becomes a master cycle on the PCI bus The PCI bus arbiter is the 6300ESB chip It arbitrates between the various PCI masters the Pentium and the Local bus IDE bus mastering controller Because the VMEbus can not be retried all VMEbus slave cycles must be allowed to be processed This becomes a problem when a Pentium cycle to the PCI slave image is in progress while a VMEbus slave cycle to the onboard DRAM is in progress The Pentium cycle will not give up the PCI bus and the VMEbus slave cycle will not give up the VMEbus thus the XVME 6200 becomes deadlocked If the X VME 6200 is to be used as a master and a slave at the same time the VMEbus master cycles must obtain the VMEbus prior to initiating VMEbus cycles All Slave interface cycles are byte swapped to maintain address coherency VMEbus Interrupt Handling The XVME 6200 can service IRQ 7 1 A register in the Universe enables which interrupt levels will be serviced by the XVME 6200 When a VMEbus IRQ is asserted the Universe requests the VMEbus and generates and IACK cycle Once the IACK c
38. figure VMEbus resources in protected and real mode programs The XVME 6200 also incorporates onboard hardware byte swapping see Table 1 2 For a complete API the Xembedded Board Support Packages tailored to your operating system will allow quick programming of your application Serial and Parallel Ports XVME 6200 includes three high speed 16550 compatible serial ports RS 232C with Com 1 capable of RS 232 and RS 422 485 configurations The Parallel port can be configured for ECP or EPP parallel port This is done in the SMC SCH3114 LPC Super I O and programmed via the BIOS Com ports 1 and 3 are RJ 45 s on the front panel and Com2 is available out the P2 VMEbus connector and requires the use of the XVME990 which provides a standard DB 9 connection Keyboard Mouse Interface A combined keyboard and mouse port PS 2 connector is provided on the front panel A PS 2 splitter cable part number 140232 provided with the module may be used to separate the two ports so that both devices may be simultaneously connected to the module IF a mouse is not required a keyboard can be connected directly to the PS 2 port The keyboard and mouse are controlled in the SMC SCH3114 LPC Super I O PMC Expansion The XVME 6200 provides an on board PMC site for use with standard 32 64 bit 33 66MHz PMC and PMC X modules The PMC site is serviced by the on board PCI X bus For electrical isolation the PMC front panel bezel is not connected to the main CPU ground PC
39. generations of Intel Architecture 32 bit MCHs Note that the DRAM that physically overlaps the low PCI Memory Address Range between TOLM and the 4 GB boundary may be recovered for use by the system For example if there is 4 GB of physical DRAM and 1 GB of PCI space then the system can address a total of 5 GB In this instance the top GB of physical DRAM physically located from 3 GB to 4 GB is addressed between 4 GB and 5 GB by the system 1 3 High PCI Memory Address Range Unpopulated Gap Additional Main Memory Address Range Low PCI Memory Address Range Main Memory Address Range DOS Legacy Address Range Introduction 64GB PCI Express Upper Memory Bottom of Hi Fang MMIO 4GB APIC PCI Express HI non overlapping windows Top Of Low TT Memory 1MB XVME 6200 Memory Map The memory map of the XVME 6200 as seen by the CPU is shown below The I O designation refers to memory which is viewed as part of the AT bus or as part of VMEbus depending on how the Universe is programmed XVME 6200 MEMORY MAP ADDRESS RANGE SIZE DEVICE HEX FFFC0000 FFFFFFFF 256K SYSTEM BIOS end of DRAM FFFBFFFF xxxK I O MEMORY 00100000 end of DRAM xxxK DRAM 000F0000 000FFFFF 64K SYSTEM BIOS 000E0000 000EFFFFE 64K SYSTEM BIOS 000D8000 000DFFFF 32K Universe Real Mode Window 000D0000 000D7FFF 32K Open memory block 000CC000 000CFFFF 16K Open memory block
40. gh the VME chassis backplane If the backplane used is NOT a 5 row 160 pin connector type of back plane the outer rows of signals will not connect to the functions of the XVME 990 and therefore will not be available Table 5 3 XVME 990 P2 Connector Pin out SATA_TXPO s5V IDERSTI 2 Too J GND DD J NC 3 1 SATATXNO 1 VMERETRY HDI PSTROBE 6 1 11 GND RIS A250 X HD4 PPE 8 GND GND ACT DG PAUTOFEED 9 1 SATALTXPI DTRO A29 HD7 PPERROR 9 11 SATA TXNI RXD2 A31 HD9 PSELIN 13 SATA RXNI AUD LINE IN L 5V HD11 PPD 1 14 15 GND AUD_LINE_IN_R VD16 HD12 PPD 2 SATA_RXP1 AUD_GND VDI7 HD13 PPD 3 Rear Transition Module G AUD_LINE_OUT_L VD18 HD14 PPD 4 USB1_GND AUD_LINE_OUT_R VD19 HD15 PPD 5 G ND ND DMA66 PDIAG VD20 GND PPD 6 SB1 GND VD21 DIOW PPD 7 FRWC VD22 DIOR DAC RED VD23 IORDY DAC GREEN clola Pulled up to 5V__ DAC BLUE SB1_PWR HDRQO VD24 IRQ14 DAC_HSYNC ao ao SBO_GND HDAKO VD26 DDC_CLK FDIRC VD27 DDC DAT Q ND SBO PWR EV P3 Interconnect connector The P3 connector on the XVME 990 is used to pass the P2 signals through to an adjacent XVME 977 or XVME 979 drive card It has the same pin out as rows A B and C of P2 The required interconnect 64 pin cable is included with the XVME 977 or XVME 979 modules Note sinc
41. he XVME 6200 are only available in a 160 pin 5 Row VMEbus P2 backplane The ordering number is broken into two parts The model number is the 6200 The tab number is the three digits after the slash For the XVME 6200 the tab number indicates the CPU type amount of SDRAM memory the middle digit and the ejector handle type and optional PO connector There are also several expansion module options for the XVME 6200 Table 1 3 XVME 6200 Expansion Module Options Ordering Number Description XVME 990 1 Drive Adapter Module for external drives cables out back of VME backplane Primary PIDE 2 PIDE Floppy COM2 Only RS 232 two ports of SATA 150 LPT1 1 USB port Audio in out and Analog Video out plus PO for rear I O from PMC site and Ethernet 31 1 or rear RJ 45 Ethernet XVME 990 2 Drive Adapter Module for external drives cables out back of VME backplane Primary PIDE 2 PIDE Floppy COM2 Only RS 232 two ports of SATA 150 LPT1 1 USB port Audio in out and Analog Video out XVME 9076 PMC Carrier module with two PMC module sites XVME 977 011 Single slot Mass Storage Module with hard drive and floppy drive XVME 979 1 Single slot Mass Storage System with CD ROM and external floppy connector XVME 979 2 Single slot Mass Storage System with CD ROM hard drive and external floppy connector XVME 979 3 Single slot Mass Storage System with RW CD ROM and external floppy connector XVME 979 4 Si
42. ill allow current flow to resume USB Connector Figure 2 10 VMEbus P2 Signal Name P2 row z 17 USB3_GND P2 row z 18 GND P2 row z 19 USB3 P2 row z 20 GND P2 row z 21 USB3 P2 row z 22 GND P2 row z 23 USB3 PWR P2 row z 24 GND USBPO P2 row z 25 USB2 GND USBPO P2 row z 26 GND GND Table 2 10 USB Port Connector Pin out Table 2 11 Rear USB ports 2 and 3 USB Port Connector Pin out on VMEbus P2 2 10 Installation and Setup COM1 and COMG J4 Pin Definitions The XVME 6200 has one serial port out the front panel Com 1 this com port uses the RJ 45 connector The second com port is out the VMEbus P2 connector and when the XVME 990 rear transition module is in place com port 2 uses a DB 9 connector See below for connector layout and pin descriptions Figure 2 11 RJ 45 Serial Port Connector COM Pin Definitions PinNumber RS2322 1 1 1 HS422 RS485 1 0 HS J Z3 HIS RTS 2 TR J DIR RED Ef 9 O TD TXD REDE j 4 GND X GND GND 5 J GND X GND GND k 6 RD RED TXDe 8 deos 3JGBU A cs CS Table 2 12 Serial Port Connector Pin out for Comm 1 2 11 Installation and Setup P4 Position Setting Description 1 2 ON RXDO to RXD2320 default 3 4 OFF RXDO to RXD422 5 6 OFF RXDO to RXD485 P5 Position Setting Desc
43. imize the chance of damaging the EE j XVME 6200 and its components 2 Power off the XVME 6200 remove it from the VME backplane and place it on a safe antistatic grounded surface 3 Remove all connectors if not already removed p 4 Locate the sockets on the XVME 6200 slightly in pcr t front of the P1 VME backplane connector 5 Pull the metal clips on either side of the SODIMM until it pops up at an angle roughly 30 from horizontal 6 Grasping the upper two corners or the edges of the SODIMM gently pull it out of the socket and set it to the side 7 Insert the new SODIMM until seated into the connector assuring it fits snugly into the connector retainer clips Both sockets must use the same type and size memory module 8 Gently push the SODIMM down until the metal clips snap into place to hold it If you cannot gently push the SODIMM into position you may need to redo step 7 9 Replace the XVME 6200 module reconnect all connectors etc 10 Power up the unit and make sure that the memory is recognized during boot up on the Boot time diagnostic screen that can be turned on in the BIOS Module Battery Installation During battery replacement polarity must be observed in installing the coin battery Please be sure to dispose of the spent battery in an environmentally correct manner The replacement battery must be a BR 1632 or equivalent type 0 Appendix A SDRAM and Battery Installa
44. itially comes up it should check to see if the system was reset due to a previous watchdog event There is a persistent status bit that gets saved in the 6300 s RELOAD register section 16 4 21 of Intel doc OffsetBase OCh This bit is WDT TIMEOUT It will remain set between resets not hard power down though So this bit should be checked If it is set then it needs to be cleared using the register unlocking sequence see code below it s three separate commands in a specific order 2 Load timeout value into Preload2 counter By default this is a 1kHz clock so each tick is 1msec In our example code below we load a value of OAAAAh into preload2 This is equivalent to 43 690 decimal therefore 43 69 seconds 3 Enable free running mode and enable watchdog via offset 68h and WDT TOUT CNF and WDT ENABLE bits The counter loaded with preload2 value immediately starts counting down 4 To prevent watchdog from tripping you disable enable watchdog again Every time you do this it automatically reloads value from preload2 and starts counting down again Introduction Commands for Watch Dog Timer in PClscope THESE ARE THE COMMANDS USED TO RUN IN FREE RUNNING MODE from PCIscope 1 To check WDT_TIMEOUT to see if previous WDT occurred If 0200 you need to unlock DW D7EFE7FC The next command is a macro that writes to the Offset Base address in our case D7EFE7FO OCh to perform the register unlocking sequence writing commands
45. ity Numeric consistency is achieved by setting the XVME 6200 buffers to pass data straight through which allows the Universe chip to perform address invariant byte lane swapping Numeric consistency is desirable for transferring integer data floating point data pointers etc Consider the long word value 12345678h stored at address M by both the XVME 6200 and the VMEbus as shown in Figure 4 3 Pentium Register 32 bit VMEbus Byte swapping Hardware XVME 690 VMEbus Figure 4 3 Maintaining Numeric Consistency Due to the Universe chip the data must be passed straight through the byte swapping hardware To do this maintaining numeric consistency enable the straight through buffers by setting bits 6 and 7 of the Flash Paging and Byte Swap register register 234h to 1 see p 2 5 Note With the straight through buffers enabled the XVME 6200 does not support unaligned transfers Sixteen bit or 32 bit transfers must have an even address 4 9 Programming Address Consistency Address consistency or address coherency refers to communications between the XVME 6200 and the VMEbus in which both architectures addresses are the same for each byte In other words the XVME 6200 and the VMEbus memory images appear the same Address consistency is desirable for byte oriented data such as strings or video image data Consider the example of transferring the string Text to the VMEbus memory using a 32 bit transfer in Figure 4 4
46. mprovements include 3 3V signaling increased speed grades and adaptation to other form factors PCI X effectively doubles the speed and amount of data exchanged between the computer processor and peripherals PCI X bus was designed for and is ideally suited for server cards such as Fibre Channel RAID high speed networking and other demanding devices Onboard Memory SDRAM Memory The XVME 6200 is configured with dual channel memory each CPU core has it s own path to the memory modules The two memory sockets are 200 pin SODIMM providing 512MB 1GB 2GB and 4GB of ECC DDR 466MHz SDRAM Approved SDRAM suppliers are listed in 0 Flash BIOS The XVME 6200 system BIOS is contained in a 1MB flash device to facilitate system BIOS updates Contact Xembedded support for available updates at support xembedded com if needed Be sure to record your current version number and the reason for the request Video Controller The Silicon Graphics 722 graphics controller has a built in 2D 3D The maximum video modes supported are listed in the following table The highest supported interlaced monitor mode is 1280x1024 16 bit 65k color and 43 Hz Video output is available on the front panel through a standard 15 pin D shell connector The 722 graphics 1 2 Introduction controller uses up to 128MB of on board video memory The SG 722 has a built in 3D graphics engine and its display render core frequency is up to 200MHz
47. n Pin Description Pin Description 40 factory use 30 DD4 20 GROUND 10 DAI 39 factory use 29 DD11 19 DMARQ 9 PDIAG 38 RESET 28 DD3 18 GROUND 8 DAO 37 GROUND 27 DD12 17 DIOW 7 DA2 36 DD7 26 DD2 16 DIOR 6 CS0 35 DD8 25 DD13 15 GROUND 5 CS1 34 DD6 24 DD1 14 IORDY 4 DASP 33 DD9 23 DD14 13 GROUND 3 3 3V 32 DD5 22 DDO 12 DMACK 2 3 3V 31 DD10 21 DD15 11 INTRQ 1 DEVADR 2 13 VMEbus Connectors VMEbus P1 Connector Table 2 16 P1 Connector Pin out Installation and Setup P A B p o gt in Z 1 MPR D00 BBSY D08 5V 2 GND D01 BCLR D09 GND MCLK D02 ACFAIL D10 3 4 GND D03 BGOIN 5 6 7 MSD GND MMD D04 D05 D06 BGOOUT BG1IN BG1OUT D11 V2 D12 RSVU1 D13 8 GND D07 BG2IN D14 V2 D15 RSVU2 9 MCTL GND BG20UT GND 10 GND SYSCLK BGSIN SYSFAIL GAO 11 RESP GND BGSOUT BERR GA1 12 GND DS1 BRO SYSRESET 18 SDB14 DSO BR1 LWORD GA2 14 5 6 GND GND WRITE DTACK BR2 AMO AMS 1 SDB15 GND BR3 A23 i A22 17 18 19 SDBP1 GND RSVBUS5 GND AS GND AM1 AM2 AM3 A21 GA4 A20 OO A19 RSVBU1 2 GND GND IACK IACKOUT GND NC A18 0 21 RSVBUS6 IACKIN NC A17 RSVBU2 22 A16 2 25 RSVBUS7 RSVBUS8 AMA A06 GND IRQ6
48. nce VMEbus 1 10 connectors CPU fan power seen 2 15 keyboard port 2 5 PM coepta amd 2 14 RJ 45 10 100 Base T 2 18 5 9 Univeral Serial Bus USB 2 8 5 7 MEE tees 2 1 5 10 VMBDUS 5 EE EE 2 11 Index XVME 973 1 PD AE EE GE eee neue 5 2 RE EE a 5 5 P4 sc tibt retten etes 5 6 CPU fan power connector sees 2 15 drivers loading Bthernet 2 17 drives Compact Flash sesse sesse ee ee ee 1 4 POPPY 25 EE 1 3 5 5 hard avers nate 1 3 5 2 5 6 Ethernet driver loading 2 17 expansion IDE devices e 1 3 PC7104 st p ig tn 1 5 PCI in EE OE E 1 5 Ke EE bar dated 1 5 PMG uet 1 5 AK AR nete tiere 1 5 Expansion Options eene 1 10 Flash Paging and Byte Swap register 2 4 4 9 4 10 floppy drive esse ee ee ee 1 3 3 21 front panel XVME 660 2 17 hard drive sirinin ee ee ee 1 3 3 23 hardware specificatHOnS iese sees sees 1 10 VO EO EE ET 4 1 IDE devices 1 3 3 23 3 30 3 40 installation SDRAM is tanien tester S A 1 XVME 660 ennn ninian 2 16 XVME 973 1 see 5 1 interrupt generation VMEbus 4 7 interrupt handling VME b s rer rete 4 6 IRO maparin En etis es 4 2 AE ea eines 4 6 jumper settings J3 mainboard 3 43 4 5 keyboard interface ses
49. ned off This is an indication the XVME 6200 has passed the POST The blue SYS Controller LED is lit when the XVME 6200 is configured as the VMEbus system controller This is the function that grants bus ownership to multiple bus VME masters and provides the 16MHz clock signal on the back plane 2 6 Installation and Setup Connectors This section provides pin outs for the XVME 6200 connectors Refer to the EMC warning at the beginning of this manual before attaching cables Keyboard Mouse Port Connector Pin Signal Mouse Data GND 5V Ee an 6 MouseCiock Installation and Setup Front panel Ethernet The Ethernet ports on the XVME 6200 are switch able between the front and the rear of the XVME 6200 When in the rear mode the Ethernet ports can use the optional available at order time only PO connector for either Vita 31 1 switch fabric over the Vita 31 1 compliant backplane or Ethernet out the XVME 990 2 rear transition module The Vita 31 1 and the rear transition module can not supply Ethernet at the same time if a Vita 31 1 compliant backplane is in use then the rear transition module RJ 45s must not be used Table 2 8 RJ 45 10 100 1000 BaseT Connector Pin out Figure 2 8 RJ 45 10 100 1000Mbps 2 8 Installation and Setup VGA Connector P9 The video is BIOS selectable and is available on either the front panel on a standard SVGA connector or out the VMEbus P2 The table below shows th
50. ngle slot Mass Storage System with RW CD ROM hard drive and external floppy connector XVME 979 5 Single slot Mass Storage System with RW DVD CD ROM and external floppy connector XVME 979 6 Single slot Mass Storage System with RW DVD CD ROM hard drive and external floppy connector XVME 9000 EXF External Floppy Drive for use with XVME 979 Introduction The XVME 9076 XVME 977 and XVME 979 expansion modules are described in their own manuals The XVME 990 is described in Chapter 5 1 16 Installation and Setup Chapter 2 Installation and Setup Board Layout This chapter provides information on configuring the XVME 6200 modules It also provides information on installing the X VME 6200 into a backplane and enabling the Ethernet controller C Q 3 SD E Ba Fo E N E T 7 N E B N 2 A 2 E BT so E E NL A J J XMC Connecter BV EM 74 TUTTI Uil A TOERE OON DS d XL OOTDORERODCIDOREDORIDOREOORIDIOT 3 00000000000000000000000000
51. not exceed 18 inches Also if two drives are connected they must be no more than six inches apart See SATA below for longer cable lengths Serial ATA Hard Drive The XVME 6200 features two 2 SATA 150 drive interfaces out the rear P2 VMEbus connector The use of the optional rear transition module XVME 990 allows for the connection of two drives using standard SATA cables If your application requires the external drives to be mounted in a location that requires a long cable run the SATA drives are better suited to that application SATA cable can be up to meters or 39 long EIDE have be less than 18 long Serial ATA 7 pin connector The 0 5 wide cable connector directly connects the 4 signal wires and 3 ground lines to the receiving terminal in a single row Because the connector includes the shielding ground pins very little crosstalk is introduced Note that the receiving terminal uses extended connectors for the 3 ground signals so that the ground reference between the device and host can be shared prior to signals being applied at the input A similar mating sequence is enforced with the new 7 8 wide 15 pin single row power connector This feature is necessary to accommodate hot plugging The 7 pin plugs from both channels of the SATA 150 are on the XVME 990 the use of this rear transition module make it possible to connect to a SATA drive Contact www serialata org for more information on the SATA interface On Board Hard
52. nterrupts based on what devices are actually in the system and require interrupts If COM2 or LPT are not used then these would free up IRQ3 and IRQ7 respectively 4 3 PCI Device Map Programming 4 4 Programming VME Interface The VME interface is the Tundra Universe IID chip which is a PCI bus to VMEbus bridge device The XVME 6200 implements a 32 bit PCI bus and a 32 64 bit VMEbus interface The Universe chip configuration registers are located in a 4 KB block of PCI memory space This memory location is programmable and defined by PCI configuration cycles The VMEbus controller has four main functions System Resources or the traffic cop of the bus Master interface which starts conversation on the bus Slave interface which responds to a bus master s question and the interrupt functions which uses seven 7 levels of interrupt control Note For your frame of reference the left side below is the XVME 6200 board and the right side below is the VMEbus PCI memory slave access VMEbus master access PCI memory master access VMEbus slave access System Resources The XVME 6200 automatically provides slot 1 system resource functions also referenced as SysCon if the Bus Grant 3 jumpers are set correctly on the VMEbus backplane The system resource functions are explained in the Universe manual Contact Tundra at www tundra com for a PDF version of the Universe manual This function can be disabled using
53. oes not allow for a PMC module to be used On Board Hard Drive using our XVME 913 1 8 hard drive This mounts in the PMC site and does not allow for a PMC module to be used VME64X VMEbus interface with programmable hardware byte swapping Support for Vita 31 1 Switch Fabric in complaint back planes Three serial ports e One RS 222 serial port on front panel Com 1 with electrical isolation Com port 1 can be configured for RS 232 422 485 e One RS 232 serial port Com 2 on P2 use our XVME 990 to access Four Universal Serial Bus USB 2 0 ports 1 and 2 on front and 3 and 4 out P2 use our XVME 990 to access EPP ECP configurable parallel port P2 on 26 pin header on the XVME 990 Combined PS 2 compatible keyboard mouse port on front panel Use USB for rear keyboard mouse PCIe 38 pin Expansion Connector NOT Compatible with X VME 976 01 thru XMVE 976 205 Carriers must use the XVME 9076 PMC PCI Mezzanine Card site with front panel I O 32 64 bit 33 66MHz with rear I O using optional PO connector This site is on the internal PCI X bus Front panel ABORT RESET switch with indicating lights Red for fail and green for pass 1 1 Introduction e Electrical isolation and noise immunity on the Ethernet ports Serial Port and PMC site e Ejector type handles in IEEE 1101 10 Compact PCI type or IEEE 1101 1 legacy VME type e VME64 VMEbus interface with programmable hardware byte swapping Architecture CPU Chip The
54. or printer port The use of a standard 26 pin ribbon cable to 25 pin D Shell will be required to cable to a standard printer Table 5 14 Parallel Port Connector Pin out showing connections to VMEbus P2 and 26 pin header on the XVME 990 P2 VMEbus 26 Pin P2 VMEbus 26 Pin Connector header Connector header Dos D12 2 PDOUTO DO 15 PERROR D14 4 PDOUT2 D11 17 SELIN Di 6 PDOUT4 si t9 GND Di8 amp 8 PDOUT D3 2 GND Dio 9 PDOU7 D3 22 GND D04 D05 po 12 PE fst 25 GND D07 26 NC 5 11 Rear Transition Module Audio Input and Output The audio connects on the rear transition module are line level inputs and outputs To drive a speaker an amplifier will be needed Table 5 15 Showing VMEbus P2 to Audio plugs AUD_LINE_IN_R AUD_GND 14 15 AUD_LINE_OUT_L AUD_LINE_OUT_R 5 12 0 Appendix A SDRAM and Battery Installation Appendix A SDRAM and Battery Installation Memory Type DRAM Memory The XVME 6200 has a two ECC Registered SODIMM sockets to accommodate from 2x256 MB 51MB total to 2x4 GBytes 8GB total DDR2 400MHz PC2700 ECC registered SODIMMs An additional pair of Chip Select lines are routed to the SODIMM socket in order to accommodate the 4GB registered SODIMMs Installing SDRAM Follow these steps to install the SODIMM n7 d 1 Follow standard antistatic procedures using a wrist strap to min
55. rates IRQ10 6 WDOG_STS Watchdog timer status bit 7 WDOG CLR Toggling this bit clears the watchdog timer back to a zero count Note Before enabling the watchdog timer for the first time it is necessary to reset the count back to zero by toggling bit 7 WDOG CLR Toggling implies changing the state of bit 0 to 1 or 1 to 0 2 5 Installation and Setup Register 234h Flash Paging and Byte Swap Register This register controls access to the Flash paging and byte swapping functions Table 2 6 Flash Paging and Byte Swap Register Settings Signal Result FLB_A15 Flash address 15 page control bit FLB_A16 Flash address 16 page control bit je au Oo j lt a an Qo Qo M l M c Do m wm S D Un a5 5 ay E d qa i T C N GA Lu Lu x OON PMC Site C N i Fall LED ass LED SATA Activity L Fig 2 X shows the front panel connector locations indicator LEDs Panel LEDs and Switch The reset switch can be enabled to reset see the setup of Sw 1 shown in Figure 2 2 and table 2 2 This switch can be configured to either just reset the XVME 6200 or to reset both the VMEbus and the XVME 6200 The green pass and red fail LEDs are used as an indication of board health during the BIOS boot up Both the green pass and red fail LEDs will light during the POST of the board As the BIOS complete the POST the red fail LED will be tur
56. res of the XVME 6200 the backplane must use 160 pin P1 and P2 Caution Do not install the XVME 6200 on a VMEbus system without a P2 backplane Warning Never install or remove any boards before turning off the power to the bus and all related external power supplies 1 Disconnect all power supplies to the backplane and the card cage Disconnect the power cable Make sure backplane 5 rows 160 pin connectors P1 and P2 are available Verify that all jumper settings are correct Verify that the card cage slot is clear and accessible cio pe p D Install the XVME 6200 in the card cage by centering the unit on the plastic guides in the slots P1 connector facing up Push the board slowly toward the rear of the chassis until the P1 and P2 connectors engage The board should slide freely in the plastic guides Caution Do not use excessive force or pressure to engage the connectors If the boards do not properly connect with the backplane remove the module and inspect all connectors and guide slots for damage or obstructions 6 Secure the module to the chassis by tightening the machine screws at the top and bottom of the board 7 Connect all remaining peripherals by attaching each interface cable into the appropriate connector on the front of the XVME 6200 board as shown in Table 2 2 19 Installation and Setup 8 Turn on power to the VMEbus card cage Table 2 22 Front Panel Connector Labels Connector Label
57. ription 1 2 ON DSROC to DSROC 485RXD 2 9 OFF 485RXD to DSROC 485RXD 4 5 ON RXDOC to RXDOC 485RXD 5 6 OFF 485RXD to RXDOC 485RXD 7 8 ON TXDOC to TXDOC 485TXD 8 9 OFF 485TXD to TXDOC 485TXD 10 11 ON DTROC to DTROC 485TXD 11 12 OFF 485TXD to DTROC A85TXD Table 2 13 Switch Setup for Com Port 1 On Board Hard Drive Compact Flash Site A horizontal ZIF connector is used on the board Samtec part number ZF5 40 01 TM WT The connector on the board has a reverse pin out because of the connector orientation relative to the hard drive This allows the flex cable to loop up to the hard drive with the connector side facing the board Table 2 14 On Board storage devices us the J17 1 8inch Hard Drive Connector pin assignment Pin Description Pin Description Pin Description Pin Description 1 factory use 11 DD4 21 GROUND 31 DA1 2 factory use 12 DD11 22 DMARQ 32 PDIAG 3 RESET 13 DD3 23 GROUND 33 DAO 4 GROUND 14 DD12 24 DIOW 34 DA2 5 DD7 15 DD2 25 DIOR 35 CS0 6 DD8 16 DD13 26 GROUND 36 CS1 7 DD6 17 DD1 27 IORDY 37 DASP 8 DD9 18 DD14 28 GROUND 38 3 3V 9 DD5 19 DDO 29 DMACK 39 3 3V 10 DD10 20 DD15 30 INTRQ 40 DEVADR 2 12 The Hitachi C4K60 CE has a 40 pin ZIF connector Table 2 15 1 8inch Hard Drive Connector pin assignment on hard drive Installation and Setup Pin Description Pin Descriptio
58. s 1 5 keyboard port connector 2 5 LED BIOS register eese 2 3 memory map 4 1 memory SDRAM eese 1 10 P1 connector XVME 973 1 5 2 P3 connector XVME 973 1 5 5 P4 connector XVME 973 1 5 6 parallel port eene 1 5 passwords cessere 3 37 PETOA n n rete re EE N 1 5 PCI Ethernet controller enabling 2 17 pinouts CPU fan POWET ese seke se ee 2 15 keyboard DOE cee see ee ee 2 5 P1 connector XVME 973 1 5 2 P3 connector XVME 973 1 5 5 P4 connector XVME 973 1 5 6 PME dae eter elie 2 14 Univeral Serial Bus USB 2 8 5 7 NGA iiec ertet 2 7 5 10 VMEbus PI eee 2 11 PMO iieri pense 1 5 PMC connectors eee eee ee see ee 2 14 ports keyboard eet 1 5 parallel tees 1 5 Serial MEE EE EE 1 5 registers Abort Clear CMOS 2 2 Abort Clear CMOS register 2 2 Flash Paging and Byte Swap2 4 4 9 4 10 LED BIOS ie erts 2 3 LED BIOS register 2 3 watchdog timer eese 2 3 reset options VMEbus 4 7 RJ 45 10 100 Base T Connector 2 18 5 9 Index SDRAM ics ce ined ictal rere i eerie 1 10 installation esee A 1 Serial ports iler 1 5 shadow memory
59. te he b nte d esed e ten CL EE onte tu fue dte 1 10 Operational Description ii dete e ine RE pecie du tee D Dee ker inde 1 12 Environmental Specifications eese ener entente AA ee nnns 1 13 Hardware Specifications iessen er aaar e teta fes x ue iie p Leer ER LER ee 1 14 VMEb s Specification oci EE ii deci EE EE ger edi ded 1 15 System Configuration and Expansion Options Tables eene 1 15 Chapter 2 Installation and Setup eeeeeeeeeeeeeeeeeeee essei ERGE GR RE EE EG Ge 2 1 Jumper and Switch Settings eese E A enne tenen eren ek ee ee 2 2 Jumper and Switch Settings nece edet eed dde eds ee 2 3 SEA EE 2 4 Front Panel Layout tier e t idonee te ene eee e e EE iD deep 2 6 Silence PL EUER 2 7 COMI and COM3 J4 Pin DefiniHOnS ees ee ee ee RR RR Re Re ee nnne nnne nennen nen enne 2 11 Figure 2 11 RJ 45 Serial Port Connector iese sees see ee n Ge ee nennen nennen nene 2 11 VMEbus P2 COfineetOT esse ES audigy ERG Ge Ee prre Ee be ese et gee c Ei ede n ge ares 2 14 Table 2 17 VMEbus P2 Connector sninen ee se ee ee se ee se de Se Ad Re eniai ee ee ge ee ed ee 2 15 Installing the XVME 6200 into a Backplane iese sesse esse se se ee ee ee Re Re ee Ge ee ee 2 19 Enabling the PCI Ethernet Controller se ee ee ee AA Ge ee Re ee ee nre ee ee 2 20 Chapter 3 BIOS Setup Menus sus saans ee se EK R AAR RE RAGE RA AA EE
60. ted on the XVME 6200 The slave can respond to A16 A24 A32 VMEbus cycles for each VMEbus slave 4 5 Programming image The address mode and type are also programmed on a VMEbus slave image basis The VMEbus memory address location for the VMEbus slave cycle is specified by the Base and Bound address The PCI address is calculated by adding the Base address to the Translation offset address The XVME 6200 DRAM memory is based on the PC AT architecture and is not contiguous The VMEbus Slave Images may be setup to allow this DRAM to appear as one Contiguous block The first VMEbus slave Image must have Base and Bound register set to 640K Example VMEbus Slave Image 0 BS 0000000h BD A0000h TO 0000000h The second VMEbus Slave Image must have the Base register set to be contiguous with the Bound register from the first VMEbus Slave Image The Bound register is limited by the Total XVME 6200 DRAM The Translation Offset register is offset by 384K which is equivalent to the A0000h FFFFFh range on the XVME 6200 board Example VMEbus Slave Image 1 BS A0000h BD 400000h TO 060000h This rather awkward mapping defined by the PC AT architecture can also be over come if the VMEbus Slave Image window is always configured with a IMbyte Translation Offset From a user and software standpoint this is always more desirable because the interrupt vector table system parameters and communication buffers keyboard are placed in low DRAM This provid
61. tes CS1 Xycom LED control register Byte Swap LAN select Video select port Available Parallel Port 2 Available CONZ Serial Port Available Secondary IDE Controller Generates CS3 Parallel Port 1 Available VGA EGA2 CONG Serial Port Primary Floppy disk controller Primary IDE Controller Generates CS3 COMI Serial port ELCR1 Edge or level triggered ELCR2 Edge or level triggered PCI configuration address register Reset Control Register Introduction 1 5 CFC PCI configuration data register Interrupt Usage INT Function IRQO System Timer IRQ1 Keyboard IRQ2 Interrupt Cascade reserved IRQS COM2 IRQ4 COM1 IRQ5 IRO6 Floppy IRO7 Parallel Port LPT1 IRQ8 Real Time Clock IRO9 Universe IID IRO9 Video IRQ10 Onboard PMC X IRQ11 Ethernet 1 and 2 IRQ12 Mouse IRQ13 Math Coprocessor reserved IRQ14 Primary IDE IRQ15 Secondary IDE Introduction The above interrupt mapping is one possible scenario The user or operating system may choose a different mapping for some of these interrupts based on what devices are actually in the system and require interrupts If COM2 or LPT1 are not used then these would free up IRQ3 and IRQ7 respectively Only one of COMI or COMG can function at a time since IRQ4 is edge triggered The default BIOS has the following settings Interrupt Processing Use APIC MP Tables Enabled
62. the XVME 6200 s jumper J3 See Jumper Settings in Chapter 2 p 2 2 VMEbus Master Interface The XVME 6200 can be either a VMEbus master by accessing a PCI slave channel or the DMA channel initiates a transaction There are 8 PCI slave images The first PCI slave image has a 4K resolution the other have 64K resolution The master can generate A16 A24 A32 VMEbus cycles for each PCI slave image The address mode and type are also programmed on a PCI slave image basis The PCI memory address location for the VMEbus master cycle is specified by the Base and Bound address The VME address is calculated by adding the Base address to the Translation offset address All PCI slave images are located in the PCI bus Memory Space The master cycles are all byte swapped maintaining address coherency Caution PCI slave images mapped to a system DRAM area will access the system DRAM not the PCI slave image Also the Universe configuration register has a higher priority than the PCI slave images This means if the PCI slave image and the Universe configuration registers are mapped in to the same memory area the configuration registers will take precedence VMEbus Slave Interface The XVME 6200 can be either a VMEbus slave by being accessing a VMEbus slave image or the DMA channel initiates a transaction There are eight PCI slave images The first slave image has a 4K resolution the others 2 4 6 8 have 64K resolution Slave images 1 8 have been implemen
63. tion dib no out __ S X A ie sae Ba o u a ue ts E ponte Index Abort toggle switch ee 4 6 Abort Clear CMOS register 2 2 backplane installing the XVME 660 2 16 BIOS compatibility 3 47 BIOS menus Advanced menu esee 3 28 Advanced Chipset Control submenu 3 32 Daughter PMC 1 PCI and Daughter PMC 2 PCI submenus 3 34 I O Device Configuration submenu3 30 PCI Configuration submenu 3 33 PCI PNP ISA IRQ Resource Exclusion SUBMENU esse ese ee 3 36 PCI PNP ISA UMB Region Exclusion submenu ees se ee ee ee 3 35 Boot ER OR OR EE tes 3 41 Exit me Us ss eiie needs 3 47 general navigation information 3 20 Main MENU ee ee RA ee 3 21 Cache RAM submenu 3 25 IDE Primary and Secondary Master and Slave submenus 3 23 Shadow RAM submenu 3 27 Power MENU sesse see ee ee 3 39 Device Monitoring submenu 3 40 Security menu 3 37 VMEbus menu iese esse sesse ee ee ese 3 42 Master Interface submenu 3 44 Slave Interface submenus 3 45 System Controller submenu 3 43 block diagram eee 1 7 byte swapping 2 4 4 7 4 8 4 10 e Vel a eE EE OE 3 25 Compact Flash drive ss 1 4 compatibility BIOS 3 47 complia
64. tions and the VMEbus to PCI bridge device Board Support Packages are available for MS DOS Windows 2000 Windows XP Windows XP Embedded Linux VxWorks and QNX Operational Description Core 2 Duo aan ITP Vol oltage pow did npa u IMVP Vi 1 5GHz to 2 16 GHz 667 MHz FS Video DDR2 SDRAM DDR2 400 MH voa pal Channel amp 200 pin SODIMM z VGA P2 PCle x1 E7520 DDR2 ECC SDRAM MCH r 200 pin SODIMM VGA PLX 512MB 1 2 4GB SM722 8111 PCle x1 PCle x4 1 8inch IDE PCI X bus Hard Drive or PMC Compact Flash um PCI Mezzanine P2IDE 6300ESB 82571EB IHD CD VO Controller Hub TORING BasaT Ethernet SATAO P2 SATA1 P2 User VO VMEbus PO Gbit LAN VITA 31 1 L m Switches amp User VO USBO amp 1 sad occa VENUE as s US52 3 P2 RJ 45 RJ 45 ACST PCI bus CODEC P2 FWH Universe IID Flash PCI to VME BIOS LPC Bus interface SCH3114 Super VO eer Swapping eer buffers j reg com COM2 Cd O VMEbus P1 and P2 Front Panel Reset Abort Front Pane FrontPanel P2 LEDs Switch Introduction Figure 1 1 XVME 6200 Block Diagram Environmental Specifications Environmental Specification Operating Non Operating Thermal 40 to 85 C Humidity 1096 to 9096 RH non 1096 to 9096 RH non condensing condensing Shock 30 g peak 50 g peak acceleration acceleration 11 msec 11 msec duration duration Vibration 0 015 0 38mm 0 030 0 76mm peak to peak 5 20
65. tor on the rear of the VME chassis Figure 5 1 illustrates how to connect the X VME 990 to the VME chassis backplane P2 connector Fig amp uB Bug Bud Bul es cu EI T ERTA es E gaan FDDI e Bama m 8 peiie B vi ad ETETE EEEREENI gageBpecpa S 3 FEL RS ae LINE DIUTLINE IH Figure 5 1 XVME 990 X Installation XVME 990 001 shown The XVME 990 X module has two connectors on it for the connection of up to two IDE hard drives and one 3 5 floppy drive Pin outs for all of the connectors are in this chapter 5 1 Rear Transition Module Similarly the IDE1 connector connects one or two standard hard drives The connector IDE1 uses a standard 80 conductor 40pin EIDE cable This cable can not exceed a cable length of 12 Connectors This section describes the pin outs for each of the fifth teen connectors on the XVME 990 X IDE1 Connector The P1 connector connects up to two EIDE hard drives Power for the drives is not supplied by the XVME 990 X Table 5 1 XVME 990 IDEI Connector Pin out Pin Signal Pin Signal O OD i co GND HD7 HD8 HD6 HD9 HD5 The IDE controller supports enhanced PIO modes which reduce the cycle times for 16 bit data transfers to the hard drive Check with your drive manual to see if the drive you are using supports these modes The higher the PIO mode the shorter the cycle time As the IDE cable length increases this reduced cycle time can lead to
66. ycle is complete a PCI bus interrupt is generated to allow the proper ISR Interrupt service routine to be executed The Universe connects to all 4 PCI bus interrupts These interrupts may be shared by other PCI bus devices The BIOS maps the PCI bus interrupts to the AT bus Interrupt controllers The AT bus interrupts must be uniquely mapped to each device Because the PCI devices share interrupt lines all ISR routines must be prepared to chain the interrupt vector to allow the other devices to be serviced 4 6 Programming Note The 6300ESB allows multiple PCI bus Interrupts to be mapped to one AT bus interrupt Example In the BIOS setup menu map the VMEbus IRQ 1 to PCI IRQ 11 VMEbus Interrupt Generation The XVME 6200 can generate VMEbus interrupts on all 7 levels There is a unique STATUS ID associated with each level The upper bits are programmed in the STATUS ID register The lowest bit is cleared if the source of the interrupt is a software Interrupt and set for all other interrupt sources Consult the Universe Users Manual for a more in depth explanation VMEbus Reset Options When the front panel Reset switch is toggled the XVME 6200 can perform the following reset options 1 Reset the VME backplane only 2 Reset the XVME 6200 CPU only 3 Reset both 4 Reset neither See Switch Settings in section 3 of this manual for information on how to configure SW1 for the Reset options Software Selectable Byte Swapping

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