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Technical Data Sheet

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1. 5 6 11 1 Reserved Bits 15 13 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 11 2 Interrupt Vector Base Address VECTOR BASE ADDRESS Bits 12 0 The contents of this register determine the location of the Vector Address Table The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus VAB 20 0 The lower eight bits are determined based upon the highest priority interrupt They are then appended onto VBA before presenting the full VAB to the 56800E core see Part 5 3 1 for details 56F8366 Technical Data Rev 7 Freescale Semiconductor 105 Preliminary 5 6 12 Fast Interrupt 0 Match Register FIMO Base B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 14 Fast Interrupt 0 Match Register FIMO 5 6 12 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 12 2 Fast Interrupt 0 Vector Number FAST INTERRUPT 0 Bits 6 0 This value determines which IRQ will be a Fast Interrupt 0 Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first see Part 5 3 3 IRQs used as fast interr
2. Add Register Offset Name 12 11 10 R o PRO 7 BKPT_UO IPL STPCNT IPL R 1 PRI TX_REG IPL TRBUF IPL R 2 IPR2 FMCBE IPL FMCCIPL FMERR IPL IRQB IPL IRQA IPL R GPIOD GPIOE GPIOF 3 IPR3 7 A Ay dl FCERR IPL FCBOFF IPL R SPI1_RCV GPIOA GPIOB GPIOC 4 IPR4 SPIO_RCV IPL SPIt_XMIT IPL Si B IBU ee ss prs U Jpect_xiraipt DECI HIRO 1PL SCM_ZROV sci RERRIPL SCI1_TIDLIPL SCI4_XMIT IPL SPIO_XMIT IPL W gt 4 IPL m E R 6 IPR6 H TMRCOIPL TMRD3IPL TMROZIPL TMRD1IPL TMRDO IPL DECO_XIRQ IPL DECO_HIRQ IPL R 7 IPR7 TMRAOIPL TMRBSIPL TMRS2IPL TMRB1IPL TMRBOIPL TMRC3IPL TMRC2IPL TMRC1 IPL R se IPRS scio_RCVIPL soreer ir EBRO SCIO_TIDL IPL SCIO_XMITIPL TMRA3IPL TMRAZ IPL TMRA IPL R PWMA_RL 9 IPRO PWMAFIPL PWMBF IPL tens PWMB_RLIPL ADCA_ZCIPL ABCB_ZCIPL ADCA_cCIPL ADCB_CC IPL R A VBA VECTOR BASE ADDRESS R B FIMO 7 FAST INTERRUPT O R FAST INTERRUPT O C FIVALO y VECTOR ADDRESS LOW R FAST INTERRUPT 0 SE EIMABO NET VECTOR ADDRESS HIGH R se rim E FAST INTERRUPT 1 R FAST INTERRUPT 1 SF FIVAL1 y VECTOR ADDRESS LOW R 0 0 0 0 o 0 0 0 0 0 FAST INTERRUPT 4 R PENDING 16 2 ll CON OE ee o W R PENDING 32 17 12 IROP1 posta W R PENDING 48 33 13 IRQP2 per W R PENDING 64 49 14 IRQP3 64 45 W R PENDING 80 65 15 IRQP4 W
3. V gt DDA_OSC_PLL Vpp PH Vopa anc Ma Vel VREFH REG REG L VREFP 1 0 ADC PVREFMID CORE VREFN OSC VREFLO DH Vss 4 Vssa ADC Figure 12 1 Power Management Part 13 Ordering Information Table 13 1 lists the pertinent information needed to place an order Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts Table 13 1 Ordering Information Supply Pin Frequency Ambient Part Voltage Package Type Count MHz Temperature Order Number Range MC56F8366 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 60 40 to 105 C MC56F8366VFV60 MC56F8366 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 60 40 to 125 C MC56F8366MFV60 MC56F8166 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 40 40 to 105 C MC56F8166VFV MC56F8366 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 60 40 to 105 C MC56F8366VFVE MC56F8366 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 60 40 to 125 C MC56F8366MFVE MC56F8166 3 0 3 6 V Low Profile Quad Flat Pack LQFP 144 40 40 to 105 C MC56F8166VFVE This package is RoHS compliant 56F8366 Technical Data Rev 7 Freescale Semiconductor 181 Preliminary How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Li
4. E SIM_ISALL CAN2 m SM R ONCE sw STOP_ WAIT_ CONTROL MW EBL RST DISABLE DISABLE SM R 1 RStSTS W SWR COPR EXTR POR K R 2 SIM_SCRO FIELD W R 3 SIM_SCR1 FIELD W R 4 SIM_SCR2 FIELD W R 5 SIM_SCR3 FIELD W SIM_MSH_ R 6 ID W m R 1 0 1 0 0 SIM_LSH_ID hy R PWMA EMI_ 5 gt PWMA 8 SIM_PUDR eE RESET Ra xBoor pwmB PYA CTRL Reserved sim R 0 0 0 0 0 SA CLKOSR fw A23 CLKOSEL R 0 0 0 B SIM_GPS 7 br po c3 c2 c co R c SIM_PCE 7 ADCB ADOA CAN DEC1 DECO TMRD TMRC Ture Ta sc ele R 1 1 1 1 1 1 1 1 1 1 D SIM_ISALH 7 ISAL 23 22 R W R W F SIM_PCE2 Reserved Figure 6 2 SIM Register Map Summary 6 5 1 SIM Control Register SIM_CONTROL Base 0 15 14 13 112 1 A A 6 a 3 2 1 0 Read ONCE sw STOP _ WAIT_ Write EBL RST DISABLE DISABLE RESET 0 0 0 0 0 0 ollo 0 0 0 0 0 0 0 Figure 6 3 SIM Control Register SIM_CONTROL 6 5 1 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 56F8366 Technical Data Rev 7 118 Freescale Semiconductor Preliminary Register Descriptions 6 5 1 2 EMI_MODE EMI_MODE Bit 6 This bit reflects the current non clocked state of the EMI MODE pin During reset this bit coupled with the EXTBOOT sig
5. 5 6 2 Interrupt Priority Register 1 IPR1 Base 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 RX_REG IPL TX_REG IPL TRBUF IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 4 Interrupt Priority Register 1 IPR1 56F8366 Technical Data Rev 7 88 Freescale Semiconductor Preliminary Register Descriptions 5 6 2 1 Reserved Bits 15 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 2 2 EOnCE Receive Register Full Interrupt Priority Level RX_REG IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 10 IRQ is priority level 2 e 11 IRQ is priority level 3 5 6 2 3 EOnCE Transmit Register Empty Interrupt Priority Level TX_REG IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 10 IRQ is priority level 2 11 IRQ is priority level 3 5 6 2 4 EOnCE Trace Buffer Interrupt Priority Level TRBUF IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disa
6. State Signal Name Pin No Type During Signal Description Reset ANBO 104 Input Analog ANBO 3 Analog inputs to ADC B channel 0 Input ANB1 105 ANB2 106 ANB3 107 ANB4 108 Input Analog ANB4 7 Analog inputs to ADC B channel 1 Input ANB5 109 ANB6 110 ANB7 111 TEMP_SENSE 96 Output Analog Temperature Sense Diode This signal connects to an on chip Output diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die Must be bypassed with a 0 01uF capacitor CAN_RX 127 Schmitt Input FlexCAN Receive Data This is the CAN input This pin has an Input pull up internal pull up resistor enabled To deactivate the internal pull up resistor set the CAN bit in the SIM_PUDR register CAN_TX 126 Open Open FlexCAN Transmit Data CAN output with internal pull up Drain Drain enable at reset Output Output Note If a pin is configured as open drain output mode internal pull up will automatically be disabled when it outputs low Internal pull up will be enabled unless it has been manually disabled by clearing the corresponding bit in the PUREN register of the GPIO module when it outputs high If a pin is configured as push pull output mode internal pull up will automatically be disabled whether it outputs low or high TCO 118 Schmitt Input TCO Timer C Channel 0 Input pull up Output enabled GPIOE8 Schmitt Port E GPIO These GPIO pin
7. MISO Output Slave LSB out m tp F Figure 10 14 SPI Slave Timing CPHA 1 MOSI Input 56F8366 Technical Data Rev 7 Freescale Semiconductor 161 Preliminary 10 11 Quad Timer Timing Table 10 19 Timer Timing 2 Characteristic Symbol Min Max Unit See Figure Timer input period Pin 2T 6 ns 10 15 Timer input high low period PiNHL 1T 3 ns 10 15 Timer output period Pout 1T 3 ns 10 15 Timer output high low period PouTHL 0 5T 3 ns 10 15 2 Parameters listed are guaranteed by design 1 In the formulas listed T the clock cycle For 60MHz operation T 16 67ns Timer inputs Z NO ASA Kf ye gt PIN A E o P PINHL e Aaa a Pout gt J POUTHL gt lt POUTHL Figure 10 15 Timer Timing 10 12 Quadrature Decoder Timing Table 10 20 Quadrature Decoder Timing 2 Characteristic Symbol Min Max Unit See Figure Quadrature input period Pin 4T 12 ns 10 16 Quadrature input high low period PHL 2T 6 ns 10 16 Quadrature phase period Poy 1T 3 ns 10 16 1 In the formulas listed T the clock cycle For 6OMHz operation T 16 67ns 2 Parameters listed are guaranteed by design 56F8366 Technical Data Rev 7 162 Freescale Semiconductor Preliminary Serial Communication Interface SCI Timing
8. Pph Pen Pen Pen e a p lt Phase A Input PHL E P gt gt A PHL Phase B P Input gt yom e A PIN PHL Figure 10 16 Quadrature Decoder Timing 10 13 Serial Communication Interface SCI Timing Table 10 21 SCI Timing Characteristic Symbol Min Max Unit See Figure Baud Rate BR fuax 16 Mbps RXD Pulse Width RXDpw 0 965 BR 1 04 BR ns 10 17 TXD Pulse Width TXDpw 0 965 BR 1 04 BR ns 10 18 1 Parameters listed are guaranteed by design 2 fmax is the frequency of operation of the system clock ZCLK in MHz which is 6OMHz for the 56F8366 device and 40MHz for the 56F8166 device 3 The RXD pin in SCIO is named RXDO and the RXD pin in SCI1 is named RXD1 4 The TXD pin in SCIO is named TXDO and the TXD pin in SCI1 is named TXD1 RXD SCI receive data pin Input RXDpw Figure 10 17 RXD Pulse Width 56F8366 Technical Data Rev 7 Freescale Semiconductor 163 Preliminary TXD SCI receive data pin Input TXDpw Figure 10 18 TXD Pulse Width 10 14 Controller Area Network CAN Timing Note CAN is NOT available in the 56F 8166 device Table 10 22 CAN Timing Characteristic Symbol Min Max Unit See Figure Baud Rate BRecan 1 Mbps Bus Wake Up detection T WAKEUP 5 us 10 19 1 Parameters listed are guaranteed by design CAN_RX CAN receive data pin Input T WAKEUP Figure 10 19 Bus
9. 143 P 10 2 DC Electrical Characteristics 147 Part 3 On Chip Clock Synthesis OCCS 38 10 3 AC Electrical Characteristics 151 elo modun con ron Error 38 10 4 Flash Memory Characteristics 152 3 2 External Clock Operation 38 10 5 External Clock Operation Timing 152 Sod Regte cosarroparas dieras 40 10 6 Phase Locked Loop Timing 153 10 7 Crystal Oscillator Timing 153 Part 4 Memory Map 40 10 8 External Memory Interface Timing 154 41 INTO ocios 40 10 9 Reset Stop Wait Mode Select and 4 2 Program Map ciscccckevescsoaeak ease 41 Interrupt Timing 156 4 3 Intemupt Vector Table iisi ecie as cee rea 44 10 10 Serial Peripheral Interface SPI 44 Data Map 0503 2sea Sek cee e 47 A 159 4 5 Flash Memory Map csoirrsrsiresrriros 47 10 11 Quad Timer Timing 162 4 6 EOnCE Memory Map 49 10 12 Quadrature Decoder Timing 162 4 7 Peripheral Memory Mapped Registers 50 10 13 Serial Communication Interface SCI 4 8 Factory Programmed Memory 82 TM secas data 163 10 14 Controller Area Network CAN Timing 164 Part 5 Interrupt Controller ITCN 83 10 15 STNG TWO cn 164 S1 es dbus seeeliedutedan 83 10 16 Analog to Digital Converter ADC E ore i eteks unos ducks eweshous 83 Parameters sscsesecaense 166 5 3 Functional Description
10. 56F8366 Technical Data Rev 7 172 Freescale Semiconductor Preliminary 56F8366 Package and Pin Out Information Table 11 1 56F8366 144 Pin LQFP Package Identification by Pin Number Pin No eee Pin No Signal Name Pin No Signal Name Pin No Signal Name 13 A4 49 GPIOD1 85 RSTO 121 TCK 14 A5 50 ISBO 86 RESET 122 TMS 15 Veapt 51 Veapl 87 CLKMODE 123 TDI 16 VDD I0 52 ISB1 88 ANAO 124 TDO 17 A6 53 ISB2 89 ANA1 125 Vpp1 18 A7 54 IRQA 90 ANA2 126 CAN_TX 19 A8 55 IRQB 91 ANA3 127 CAN_RX 20 AQ 56 FAULTBO 92 ANA4 128 Voap2 21 A10 57 FAULTB1 93 ANA5 129 sso 22 A11 58 FAULTB2 94 ANA6 130 SCLKO 23 A12 59 DO 95 ANA7 131 MISOO 24 A13 60 D1 96 TEMP_SENSE 132 MOSIO 25 A14 61 FAULTB3 97 VREFLO 133 D11 26 A15 62 PWMAO 98 VREFN 134 D12 27 Vss 63 Vss 99 VREFMID 135 D13 28 D7 64 PWMA1 100 VREFP 136 D14 29 D8 65 PWMA2 101 VREFH 137 D15 30 D9 66 VDD lo 102 VDDA ADC 138 AO 31 Vop_ lo 67 PWMA3 103 Vssa_ADC 139 PHASEAO 32 D10 68 PWMA4 104 ANBO 140 PHASEBO 33 GPIOBO 69 Vss 105 ANB1 141 INDEXO 34 PWMBO 70 PWMA5 106 ANB2 142 HOMEO 35 PWMB1 71 FAULTAO 107 ANB3 143 EMI_MODE 36 PWMB2 72 D2 108 ANB4 144 Vss 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 173 11 2 56F8166 Package and Pin Out Information This section contains package and pin out information for the 56F8166 This device comes in a 144 pin L
11. Characteristic Symbol Min Typ Max Unit Program time Tprog 20 us Erase time Terase 20 ms Mass erase time Tme 100 ms 1 There is additional overhead which is part of the programming sequence See the 56F8300 Peripheral User Manual for details Program time is per 16 bit word in Flash memory Two words at a time can be programmed within the Pro gram Flash module as it contains two interleaved memories 2 Specifies page erase time There are 512 bytes per page in the Data and Boot Flash memories The Program Flash module uses two interleaved Flash memories increasing the effective page size to 1024 bytes 10 5 External Clock Operation Timing Table 10 13 External Clock Operation Timing Requirements Characteristic Symbol Min Typ Max Unit Frequency of operation external clock driver fosc 0 E 120 MHz Clock Pulse Width tpw 3 0 ns External clock input rise time tise z 10 ns External clock input fall time tall 10 ns 1 Parameters listed are guaranteed by design 2 See Figure 10 4 for details on using the recommended connection of an external clock driver 3 The high or low pulse width must be no smaller than 8 0ns or the chip will not function 4 External clock input rise time is measured from 10 to 90 5 External clock input fall time is measured from 90 to 10 56F8366 Technical Data Rev 7 152 Freescale Semicondu
12. Register Acronym Address Offset Register Description TMRAO_CMPLD1 8 Comparator Load Register 1 TMRAO_CMPLD2 9 Comparator Load Register 2 TMRAO_COMSCR A Comparator Status and Control Register TMRA1_CMP1 10 Compare Register 1 TMRA1_CMP2 11 Compare Register 2 TMRA1_CAP 12 Capture Register TMRA1_LOAD 13 Load Register TMRA1_HOLD 14 Hold Register TMRA1_CNTR 15 Counter Register TMRA1_CTRL 16 Control Register TMRA1_SCR 17 Status and Control Register TMRA1_CMPLD1 18 Comparator Load Register 1 TMRA1_CMPLD2 19 Comparator Load Register 2 TMRA1_COMSCR 1A Comparator Status and Control Register TMRA2_CMP1 20 Compare Register 1 TMRA2_CMP2 21 Compare Register 2 TMRA2_CAP 22 Capture Register TMRA2_LOAD 23 Load Register TMRA2_HOLD 24 Hold Register TMRA2_CNTR 25 Counter Register TMRA2_CTRL 26 Control Register TMRA2_SCR 27 Status and Control Register TMRA2_CMPLD1 28 Comparator Load Register 1 TMRA2_CMPLD2 29 Comparator Load Register 2 TMRA2_COMSCR 2A Comparator Status and Control Register TMRA3_CMP1 30 Compare Register 1 TMRA3_CMP2 31 Compare Register 2 TMRA3_CAP 32 Capture Register TMRA3_LOAD 33 Load Register TMRA3_HOLD 34 Hold Register 56F8366 Technical Data Rev 7 Freescale Semiconductor 53 Preliminary Table 4 11 Quad Timer A Registers Address Map Continued TMRA_BASE 00 F040 Register Acronym Address Offset Register Description TMRA3_CNTR 35 Coun
13. Table 2 1 Functional Group Pin Allocations Number of Pins in Package Functional Group 56F8366 56F8166 Power Vpp or Vopa 9 9 Power Option Control 1 1 Ground Vss or Vasa 6 6 Supply Capacitors 8 Vpp 6 6 PLL and Clock 4 4 Address Bus 17 17 Data Bus 16 16 Bus Control 6 6 Interrupt and Program Control 6 6 Pulse Width Modulator PWM Ports 25 13 Serial Peripheral Interface SPI Port O 4 4 Serial Peripheral Interface SPI Port 1 4 Quadrature Decoder Port 0 4 4 Quadrature Decoder Port 1 4 Serial Communications Interface SCI Ports 4 4 CAN Ports 2 Analog to Digital Converter ADC Ports 21 21 Quad Timer Module Ports 3 1 JTAG Enhanced On Chip Emulation EOnCE 5 5 Temperature Sense 1 Dedicated GPIO 5 1 If the on chip regulator is disabled the Vcap pins serve as 2 5V Vpp_core Power inputs 2 Alternately can function as Quad Timer pins or GPIO 3 Pins in this section can function as Quad Timer SPI 1 or GPIO 56F8366 Technical Data Rev 7 Freescale Semiconductor 15 Preliminary Power Power Power Ground Ground Other Supply Ports PLL and Clock External Address Bus or GPIO External Data Bus or GPIO External Bus Control or GPIO SCI 0 or GPIO SCI 1 or GPIO JTAG EOnCE Port GPIODO CS2 CAN2_TX GPIOD1 CS3 CAN2_RX Vpp_Io VDDA_ADC Vppa_OSC_PL
14. ANAO 7 VREF qANBO 7 TCO GPIOE8 GPIOE10 11 pa IRQA pan IRQB EXTBOOT EMI_MODE pg a RESET RSTO Introduction Quadrature Decoder 0 or Quad Timer A or GPIO SPIO or GPIO SPI 1 or GPIO GPIO PWMB or GPIO ADCA ADCB QUAD TIMER C or GPIO Interrupt Program Control Figure 2 2 56F8166 Signals Identified by Functional Group 144 pin LQFP 1 Alternate pin functionality is shown in parenthesis pin direction type shown is the default functionality 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 17 2 2 Signal Pins After reset each pin is configured for its primary function listed first Any alternate functionality must be programmed Note Signals in italics are NOT available in the 56F8166 device If the State During Reset lists more than one state for a pin the first state is the actual reset state Other states show the reset condition of the alternate function which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral For example the AS GPIOAO pin shows that it is tri stated during reset If the GPIOA_PER is changed to select the GPIO function of the pin it will become an input if no other registers are changed Table 2 2 Signal and Package Information for the 144 Pin LQFP
15. 83 10 17 Equivalent Circuit for ADC Inputs 168 SA BIGCK D AG AM sscrericrrsiredrirres 85 10 18 Power Consumption 169 55 Operating Modes 52 64 ghee sdhae od 85 5 6 Register Descriptions 86 Part 11 Packaging 171 Of ROG cciceaeassa puita priid tipigi 114 11 1 56F8366 Package and Pin Out MONDANO cas etm eteew ened e 171 Part 6 System Integration Module SIM 114 11 2 56F8166 Package and Pin Out AA OVEIVIEW oosariorariodacideos pide 114 Information 174 A A O E EES 115 6 3 Operating Modes oo 115 Part 12 Design Considerations 178 6 4 Operating Mode Register 116 12 1 Thermal Design Considerations 178 6 5 Register Descriptions 117 12 2 Electrical Design Considerations 179 6 6 Clock Generation Overview 132 12 3 Power Distribution and I O Ring 6 7 Power Down Modes Overview 132 Implementation 180 6 8 Stop and Wait Mode Disable Function 133 0 ROSSI isc rar 133 Part 13 Ordering Information 181 Part 7 Security Features 134 7 1 Operation with Security Enabled 134 7 2 Flash Access Blocking Mechanisms 134 56F8366 Technical Data Rev 7 4 Freescale Semiconductor Preliminary 56F8366 56F 8166 Features Part 1 Overview 1 1 56F8366 56F8166 Features 1 1 1 Core e Efficient 16 bit 56800E family controller engine with du
16. Added the following note to the description of the TRST signal in Table 2 2 Note For normal operation connect TRST directly to Vgg If the design is to be used in a debugging environment TRST may be tied to Vgg through a 1K resistor Rev 7 e Remove pullup comment from PWM pins in Table 2 2 Add Figure 10 1 showing current voltage characteristics In Table 10 24 correct interpretation of Calibration Factors to be viewed as worst case factors Please see http www freescale com for the most current data sheet revision 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 56F8366 56F8166 General Description Note Features in italics are NOT available in the 56F8166 device C efficient architecture SRA 512KB of Program Flash 4KB of Program RAM 32KB of Data Flash 32KB of Data RAM 32KB of Boot Flash Up to two 6 channel PWM modules Four 4 channel 12 bit ADCs Up to 60 MIPS at 60MHz core frequency DSP and MCU functionality in a unified Access up to 1MB of off chip program and data memory Chip Select Logic for glueless interface to ROM and M Temperature Sensor Up to two Quadrature Decoders Optional On Chip Regulator Up to two FlexCAN modules Two Serial Communication Interfaces SCIs Up to two Serial Peripheral Interfaces SPIs Up to four General Purpose Quad Timers Computer Operating Properly COP Watchdog JTAG Enhanced On Chip Emulation
17. The 56F8366 56F8166 architecture is shown in Figure 1 1 and Figure 1 2 Figure 1 1 illustrates how the 56800E system buses communicate with internal memories the external memory interface and the IPBus Bridge Table 1 2 lists the internal buses in the 56800E architecture and provides a brief description of their function Figure 1 2 shows the peripherals and control blocks connected to the IPBus Bridge The figures do not show the on board regulator and power and ground signals They also do not show the multiplexing between peripherals or the dedicated GPIOs Please see Part 2 Signal Connection Descriptions to see which signals are multiplexed with those of other peripherals Also shown in Figure 1 2 are connections between the PWM Timer C and ADC blocks These connections allow the PWM and or Timer C to control the timing of the start of ADC conversions The Timer C channel indicated can generate periodic start SYNC signals to the ADC to start its conversions In another operating mode the PWM load interrupt SYNC output signal is routed internally to the Timer C input channel as indicated The timer can then be used to introduce a controllable delay before generating its output signal The timer output then triggers the ADC To fully understand this interaction please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals 56F8366 Technical Data Rev 7 10 Freescale Semiconductor Pre
18. 2 135 0 25 DCAEO WWSH RWSS ns RD RD RWSS RWSH RD Deasserted to RD Asserted teorD 0 4832 0 00 pane 4 ns WR Deasserted to WR Asserted MEE WWS 0 1 608 0 75 DCAEO WWSS WWSH ns WWS gt 0 0 918 1 00 RD Deasserted to WR Asserted ee WWS 0 0 096 0 50 RWSH WWSS he WWS gt 0 0 084 0 75 DCAOE MDAR 1 N A since device captures data before it deasserts RD 2 If RWSS RWSH 0 and the chip select does not change then RD does not deassert during back to back reads 3 Substitute BMDAR for MDAR if there is no chip select 4 MDAR is active in this calculation only when the chip select changes 10 9 Reset Stop Wait Mode Select and Interrupt Timing Table 10 17 Reset Stop Wait Mode Select and Interrupt Timing Characteristic Symbol ng Unit See Figure RESET Assertion to Address Data and Control traz 21 ns 10 6 Signals High Impedance Minimum RESET Assertion Duration tra 16T ns 10 6 56F8366 Technical Data Rev 7 156 Freescale Semiconductor Preliminary Reset Stop Wait Mode Select and Interrupt Timing Table 10 17 Reset Stop Wait Mode Select and Interrupt Timing Continued ds Typical Typical E Characteristic Symbol Min Max Unit See Figure RESET Deassertion to First External Address Output tRDA 63T 64T ns 10 6 Edge sensitive Interrupt Request Width tirw 1 51 ns 10 7 IRQA IRQB Assertion to External Data Memory tom 18T
19. FC2MB10_DATA 93 Message Buffer 10 Data Register FC2MB10_DATA 94 Message Buffer 10 Data Register FC2MB10_DATA 95 Message Buffer 10 Data Register FC2MB10_DATA 96 Message Buffer 10 Data Register FC2MB11_CONTROL 98 Message Buffer 11 Control Status Register FC2MB11_ID_HIGH 99 Message Buffer 11 ID High Register FC2MB11_ID_LOW 9A Message Buffer 11 ID Low Register FC2MB11_DATA 9B Message Buffer 11 Data Register FC2MB11_DATA 9C Message Buffer 11 Data Register FC2MB11_DATA 9D Message Buffer 11 Data Register FC2MB11_DATA 9E Message Buffer 11 Data Register FC2MB12_CONTROL A0 Message Buffer 12 Control Status Register FC2MB12_ID_HIGH A1 Message Buffer 12 ID High Register FC2MB12_ID_LOW A2 Message Buffer 12 ID Low Register FC2MB12_DATA A3 Message Buffer 12 Data Register FC2MB12_DATA A4 Message Buffer 12 Data Register FC2MB12_DATA A5 Message Buffer 12 Data Register FC2MB12_DATA A6 Message Buffer 12 Data Register FC2MB13_ CONTROL A8 Message Buffer 13 Control Status Register FC2MB13_ID_HIGH A9 Message Buffer 13 ID High Register FC2MB13_ID_LOW SAA Message Buffer 13 ID Low Register FC2MB13_DATA SAB Message Buffer 13 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor 81 Preliminary Table 4 39 FlexCAN2 Registers Address Map Continued FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MB13_ DATA AC Mess
20. IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 2 PWM B Fault Interrupt Priority Level PWMB_F IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freescale Semiconductor 103 Preliminary 5 6 10 3 Reload PWM A Interrupt Priority Level PWMA_RL IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 4 Reload PWM B Interrupt Priority Level PWMB_RL IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 5 ADC A Zero Crossing or Limit Error Interrupt Priority Level ADCA_ZC IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is
21. Note Nested interrupts may cause this field to be updated before the original interrupt service routine can read it e 00 Required nested exception priority levels are 0 1 2 or 3 01 Required nested exception priority levels are 1 2 or 3 e 10 Required nested exception priority levels are 2 or 3 e 11 Required nested exception priority level is 3 5 6 30 3 Vector Number Vector Address Bus VAB Bits 12 6 This read only field shows the vector number VAB 7 1 used at the time the last IRQ was taken This field is only updated when the 56800E core jumps to a new interrupt service routine Note Nested interrupts may cause this field to be updated before the original interrupt service routine can read it 5 6 30 4 Interrupt Disable INT_DIS Bit 5 This bit allows all interrupts to be disabled 0 Normal operation default e 1 All interrupts disabled 56F8366 Technical Data Rev 7 Freescale Semiconductor 111 Preliminary 5 6 30 5 Reserved Bit 4 This bit field is reserved or not implemented It is read as 1 and cannot be modified by writing 5 6 30 6 IRQB State Pin IRQB STATE Bit 3 This read only bit reflects the state of the external IRQB pin 5 6 30 7 IRQA State Pin IRQA STATE Bit 2 This read only bit reflects the state of the external IRQA pin 5 6 30 8 IRQB Edge Pin IRQB Edg Bit 1 This bit controls whether the external IRQB interrupt is edge or level sensitive During Stop and
22. PS CS0 GPIOD8 4 Quad y lL DS CS1 GPIOD9 lt 4 timer Bor IPBus Bridge IPBB SP11 or GPIO or ag gt GPIODO CS2 or CAN2_TX GPIOC Peripheral pane EMI CS or a Quad Decoding Device Selects FlexCAN2 l gt GPIOD1 CS3 or CAN2_RX lt gt Timer Cor GPIOE _ Peripherals Quad y 2 7 Clock EA TMe DST t resets PLL 2 Samal FlexCAN P SPIO or SCI1 or SCIO or COP Interrupt System o Clock O by XTAL Integration R GPIOE GPIOD GPIOE Watchdog Controller ED Maile de z Y EXTAL a 2 gt EXA y IRQA RQB CLKO CLKMODE 56F8366 56F8166 Block Diagram 144 LQFP 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Table of Contents Part 1 Overview 20000eeeeee 5 Part 8 General Purpose Input Output GPIO 1 1 56F8366 56F8166 Features A Baca we Baler eed A A 137 1 2 Device Description 7 GA WiOGlh iicvsicsvatesesuseeesens 137 1 3 Award Winning Development Environment 9 8 2 Memory Maps ee 137 1 4 Architecture Block Diagram 10 8 3 Configuration oooooooooo 137 1 5 Product Documentation cocociro s 14 1 6 Data Sheet Conventions 14 Part 9 Joint Test Action Group JTAG 142 9 1 JTAG Information o o oooooo 142 Part 2 Signal Connection Descriptions 15 2 1s TIO AMCION ci a 15 Part 10 Specifications A 143 2 2 Signal Pins oooooococccococnc 18 10 1 General Characteristics
23. Package case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user controls the thermal environment to change the case to ambient thermal resistance Reca For instance the user can change the size of the heat sink the air flow around the device the interface material the mounting arrangement on printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device To determine the junction temperature of the device in the application when heat sinks are not used the Thermal Characterization Parameter PY yy can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation Ty Tr YyT x Pp where Tr Thermocouple temperature on top of package C 56F8366 Technical Data Rev 7 178 Freescale Semiconductor Preliminary Electrical Design Considerations Yir Thermal characterization parameter C W Pp Power dissipation in package W The thermal characterization parameter is measured per JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction The thermocouple wire is placed flat again
24. Se 90 0 3 Volts Figure 10 1 Maximum Current Schmitt Input DC Response 40 C 3 6 V Table 10 6 Power on Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1 75 1 8 1 9 V LVI 2 5 volt Supply trip point Ve 2 5 2 14 v LVI 3 3 volt supply trip point VEI3 3 2 7 M Bias Current l bias 110 130 uA 1 When Vpp core drops below Vey 5 an interrupt is generated 2 When Vpp core drops below Ve z 3 an interrupt is generated Table 10 7 Current Consumption per Power Supply Pin Typical On Chip Regulator Enabled OCR_DIS Low Mode Ipp_10 Ipp_ADc Ipp_osc_PLL Test Conditions RUN1_MAC 155mA 50mA 2 5mA 60MHz Device Clock All peripheral clocks are enabled All peripherals running Continuous MAC instructions with fetches from Data RAM ADC powered on and clocked Wait3 91mA 70A 2 5mA 60MHz Device Clock All peripheral clocks are enabled ADC powered off 56F8366 Technical Data Rev 7 148 Freescale Semiconductor Preliminary DC Electrical Characteristics Table 10 7 Current Consumption per Power Supply Pin Typical On Chip Regulator Enabled OCR_DIS Low Mode l 1 DD_IO Ipp_ADC lbo_osc_PLL Test Conditions Stop1 6mA OA 1654A e 8MHz Device Clock All peripheral clocks are off ADC powered off e PLL powered off Stop2 5 1mA OA 1554A External Clock is off All peripheral clocks are off ADC powered off e PLL pow
25. State Signal Name Pin No Type During Signal Description Reset Vop_lo 1 Supply I O Power This pin supplies 3 3V power to the chip I O interface and also the Processor core throught the on chip voltage regulator Vop_o 16 if it is enabled Vpp_Io 31 Vpp_10 38 Vpp_10 66 Vpp_10 84 Vop_io 119 VDDA ADC 102 Supply ADC Power This pin supplies 3 3V power to the ADC modules a It must be connected to a clean analog power supply VDDA OSC PLL 80 Supply Oscillator and PLL Power This pin supplies 3 3V power to the nae OSC and to the internal regulator that in turn supplies the Phase Locked Loop It must be connected to a clean analog power supply Vss 27 Supply Vss These pins provide ground for chip logic and I O drivers Vss 37 Vss 63 Vss 69 Vss 144 56F8366 Technical Data Rev 7 18 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP Signal Name Pin No Type State During Reset Signal Description Vssa_ADC 103 Supply ADC Analog Ground This pin supplies an analog ground to the ADC modules OCR_DIS 79 Input Input On Chip Regulator Disable Tie this pin to Vss to enable the on chip regulator Tie this pin to Vpp to disable the on chip regulator This pin is intended to be a static DC signal from power up to shut down Do not try to toggle this pin for power savings during operation Vcap1 Vcap2 51 1
26. This must be done explicitly before entering Stop mode since there is no automatic mechanism for this When the PLL is shut down the 56800E system clock must be set equal to the prescaler output Some applications require the 56800E STOP and WAIT instructions be disabled To disable those instructions write to the SIM control register SIM CONTROL described in Part 6 5 1 This procedure can be on either a permanent or temporary basis Permanently assigned applications last only until their next reset 6 9 Resets The SIM supports four sources of reset The two asynchronous sources are the external RESET pin and the Power On Reset POR The two synchronous sources are the software reset which is generated within the SIM itself by writing to the SIM CONTROL register and the COP reset Reset begins with the assertion of any of the reset sources Release of reset to various blocks is sequenced to permit proper operation of the device A POR reset is first extended for 27 clock cycles to permit stabilization of the clock source followed by a 32 clock window in which SIM clocking is initiated It is then followed by a 32 clock window in which peripherals are released to implement Flash security and finally followed by a 32 clock window in which the core is initialized After completion of the described reset sequence application code will begin execution Resets may be asserted asynchronously but they are always released internally on a ris
27. m PENDING 16 IRQP5 81 W Reserved IRQA EDG Reserved se aes FLEXCAN2 FLEXCAN2 FLEXCAN2 FLEXCAN2 MSGBUF IPL WKUP IPL ERR IPL BOFF IPL P Reserved Figure 5 2 ITCN Register Map Summary 56F8366 Technical Data Rev 7 Freescale Semiconductor 87 Preliminary 5 6 1 Interrupt Priority Register 0 IPRO Base 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 3 Interrupt Priority Register 0 IPRO 5 6 1 1 Reserved Bits 15 14 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 1 2 EOnCE Breakpoint Unit 0 Interrupt Priority Level BKPT_U0 IPL Bits13 12 This field is used to set the interrupt priority levels for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 10 IRQ is priority level 2 11 IRQ is priority level 3 5 6 1 3 EOnCE Step Counter Interrupt Priority Level STPCNT IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 10 IRQ is priority level 2 5 6 1 4 11 IRQ is priority level 3 Reserved Bits 9 0 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing
28. x 1 to 128 gt 2 1 2 4 8 Postscaler CLK O co Bus in Bus Interface amp Control lt terface Z H Lock LCK Detector Y Loss of Loss of Reference Reference Clock Interrupt gt Clock ai Detector Figure 3 1 OCCS Block Diagram 3 2 External Clock Operation The system clock can be derived from an external crystal ceramic resonator or an external system clock signal To generate a reference frequency using the internal oscillator a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins 3 2 1 Crystal Oscillator The internal oscillator is designed to interface with a parallel resonant crystal resonator in the frequency range specified for the external crystal in Table 10 15 A recommended crystal oscillator circuit is shown in Figure 3 2 Follow the crystal supplier s recommendations when selecting a crystal since crystal parameters determine the component values required to provide maximum stability and reliable start up 56F8366 Technical Data Rev 7 38 Freescale Semiconductor Preliminary External Clock Operation The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start up stabilization time Crystal Frequency 4 8MHz optimized for 8MHz EXTAL XTAL EXTAL XTAL Sample External Crystal Parameters Rz Rz R 750 KQ CLKMODE 0 E Not
29. 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 102 Freescale Semiconductor Preliminary Register Descriptions 5 6 9 7 Timer A Channel 2 Interrupt Priority Level TMRA2 IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 8 Timer A Channel 1 Interrupt Priority Level TMRA1 IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 Interrupt Priority Register 9 IPR9 Base 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PWMA_F IPL PWMB_F IPL is PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL Saar ans ar Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 12 Interrupt Priority Register 9 IPR9 5 6 10 1 PWM A Fault Interrupt Priority Level PWMA_F IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01
30. ADCB_LLMT 6 17 Low Limit Register 6 ADCB_LLMT 7 18 Low Limit Register 7 ADCB_HLMT 0 19 High Limit Register 0 ADCB_HLMT 1 1A High Limit Register 1 ADCB_HLMT 2 1B High Limit Register 2 ADCB_HLMT 3 1C High Limit Register 3 ADCB_HLMT 4 1D High Limit Register 4 ADCB_HLMT 5 1E High Limit Register 5 ADCB_HLMT 6 1F High Limit Register 6 ADCB_HLMT 7 20 High Limit Register 7 ADCB_OFSO 21 Offset Register 0 ADCB_OFS 1 22 Offset Register 1 ADCB_OFS 2 23 Offset Register 2 ADCB_OFS 3 24 Offset Register 3 ADCB_OFS 4 25 Offset Register 4 ADCB_OFS 5 26 Offset Register 5 ADCB_OFS 6 27 Offset Register 6 ADCB_OFS 7 28 Offset Register 7 ADCB_POWER 29 Power Control Register ADCB_CAL 2A ADC Calibration Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 65 Table 4 22 Temperature Sensor Register Address Map TSENSOR_BASE 00 F270 Temperature Sensor is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TSENSOR_CNTL 0 Control Register Table 4 23 Serial Communication Interface 0 Registers Address Map SCIO_ BASE 00 F280 Register Acronym Address Offset Register Description SCIO_SCIBR 0 Baud Rate Register SCIO_SCICR SCIO_SCISR 1 3 Control Register Reserved Status Register SCIO_SCIDR 4 Data Register Table 4 24 Serial Communication Interface 1 Re
31. Address Offset Register Description FCMB13_DATA AC Message Buffer 13 Data Register FCMB13_ DATA AD Message Buffer 13 Data Register FCMB13_DATA AE Message Buffer 13 Data Register Reserved FCMB14_CONTROL B0 Message Buffer 14 Control Status Register FCMB14_ID_HIGH B1 Message Buffer 14 ID High Register FCMB14_ID_LOW B2 Message Buffer 14 ID Low Register FCMB14_DATA B3 Message Buffer 14 Data Register FCMB14_DATA B4 Message Buffer 14 Data Register FCMB14_DATA B5 Message Buffer 14 Data Register FCMB14_DATA B6 Message Buffer 14 Data Register Reserved FCMB15_CONTROL B8 Message Buffer 15 Control Status Register FCMB15_ID_HIGH B9 Message Buffer 15 ID High Register FCMB15_ID_LOW BA Message Buffer 15 ID Low Register FCMB15_ DATA BB Message Buffer 15 Data Register FCMB15_ DATA BC Message Buffer 15 Data Register FCMB15_ DATA BD Message Buffer 15 Data Register FCMB15_ DATA BE Message Buffer 15 Data Register Reserved Table 4 39 FlexCAN2 Registers Address Map FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MCR 0 Module Configuration Register Reserved FC2CTLO 3 Control Register 0 Register FC2CTL1 4 Control Register 1 Register FC2TMR 5 Free Running Timer Register FC2MAXMB 6 Maximum Message Buffer Configuration Register 56F8366 Technical Data
32. BLOCK 0 Odd 2 Bytes 00_0001 PROG_FLASH_START 00_0000 BLOCK 0 Even 2 Bytes 00_0000 Figure 4 1 Flash Array Memory Maps Table 4 7 shows the page and sector sizes used within each Flash memory block on the chip Note Data Flash is NOT available on the 56F8166 device Table 4 7 Flash Memory Partitions Flash Size Sectors Sector Size Page Size Program Flash 512KB 16 16K x 16 bits 1024 x 16 bits Data Flash 32KB 16 1024 x 16 bits 256 x 16 bits Boot Flash 32KB 4 4K x 16 bits 512 x 16 bits Please see 56F8300 Peripheral User Manual for additional Flash information 56F8366 Technical Data Rev 7 48 Freescale Semiconductor Preliminary 4 6 EOnCE Memory Map Table 4 8 EOnCE Memory Map EOnCE Memory Map Address Register Acronym Register Name X FF FF8A X FF FF8E OESCR OBCNTR Reserved External Signal Control Register Reserved Breakpoint Unit 0 Counter Reserved X FF FF90 OBMSK 32 bits Breakpoint 1 Unit 0 Mask Register X FF FF91 Breakpoint 1 Unit 0 Mask Register X FF FF92 OBAR2 32 bits Breakpoint 2 Unit 0 Address Register X FF FF93 Breakpoint 2 Unit 0 Address Register X FF FF94 OBAR1 24 bits Breakpoint 1 Unit 0 Address Register X FF FF95 Breakpoint 1 Unit 0 Address Register X FF FF96 OBCR 24 bits Breakpoint Unit 0 Control Register X FF FF97 Breakpoint Unit 0
33. Control Register X FF FF98 OTB 21 24 bits stage Trace Buffer Register Stages X FF FF99 Trace Buffer Register Stages X FF FF9A OTBPR 8 bits Trace Buffer Pointer Register X FF FF9B OTBCR Trace Buffer Control Register X FF FF9C OBASE 8 bits Peripheral Base Address Register X FF FF9D OSR Status Register X FF FF9E OSCNTR 24 bits Instruction Step Counter X FF FF9F Instruction Step Counter X FF FFAO OCR bits Control Register Reserved X FF FFFC OCLSR 8 bits Core Lock Unlock Status Register X FF FFFD OTXRXSR 8 bits Transmit and Receive Status and Control Register X FF FFFE OTX ORX 32 bits Transmit Register Receive Register X FF FFFF OTX1 ORX1 Transmit Register Upper Word Receive Register Upper Word 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 49 4 7 Peripheral Memory Mapped Registers On chip peripheral registers are part of the data memory map on the 56800E series These locations may be accessed with the same addressing modes used for ordinary Data memory except all peripheral registers should be read written using word accesses only Table 4 9 summarizes base addresses for the set of peripherals on the 56F8366 and 56F8166 devices Peripherals are listed in order of the base address The following tables list all of the peripheral registers required to control or access the peripherals Note Features in italics are NOT availabl
34. DIV value of 19 for a clock of 200kHz and a DIV value of 20 for a clock of 190kHz This translates into an FM CLKDIV 6 0 value of 13 or 14 respectively SYS_CLK 150 kHz A 2 200 kHz DIV 1 EXAMPLE 2 In this example the system clock has been set up with a value of 32MHz making the FM input clock 16MHz Because that is greater than 12 8MHz PRDIV8 FM_CLKDIV 6 1 Using the following equation yields a DIV value of 9 for a clock of 200kHz and a DIV value of 10 for a clock of 181kHz This translates to an FM CLKDIV 6 0 value of 49 or 4A respectively SYS_CLK 150 kHz ak 28 200 kHz DIV 1 Once the LOCKOUT RECOVERY instruction has been shifted into the instruction register the clock divider value must be shifted into the corresponding 7 bit data register After the data register has been updated the user must transition the TAP controller into the RUN TEST IDLE state for the lockout sequence to commence The controller must remain in this state until the erase sequence has completed For details see the JTAG Section in the 56F8300 Peripheral User Manual Note Once the lockout recovery sequence has completed the user must reset both the JTAG TAP controller by asserting TRST and the device by asserting external chip reset to return to normal unsecured operation 56F8366 Technical Data Rev 7 136 Freescale Semiconductor Preliminary Introduction 7 2 4 Product Analysis The recommended
35. FlexCAN2_WKUP IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 32 4 FlexCAN2 Error Interrupt Priority Level FlexCAN2_ERR IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 11 IRQ is priority level 2 5 6 32 5 FlexCAN2 Bus Off Interrupt Priority Level FlexCAN2_BOFF IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freescale Semiconductor 113 Preliminary 5 7 Resets 5 7 1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted The reset vector will be presented until the second rising clock edge after RESET is released 5 7 2 ITCN After Reset After reset all of the ITCN registers are in their default states This means all interrupts are disabled except the core IRQs with fixed
36. IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 Interrupt Priority Register 3 IPR3 Base 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read GPIOD GPIOE GPIOF FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL A IPL IPL IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 6 Interrupt Priority Register 3 IPR3 56F8366 Technical Data Rev 7 Freescale Semiconductor 91 Preliminary 5 6 4 1 GPIOD Interrupt Priority Level GPIOD IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 2 GPIOE Interrupt Priority Level GPIOE IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 3 GPIOF Interrupt Priority Level GPIOF IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2two They are disab
37. Peripheral Enable Register 0 x 1FCO GPIOD_IAR 4 Interrupt Assert Register 0 x 0000 GPIOD_IENR 5 Interrupt Enable Register 0 x 0000 GPIOD_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOD_IPR 7 Interrupt Pending Register 0 x 0000 GPIOD_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOD_PPMODE 9 Push Pull Mode Register 0 x 1FFF GPIOD_RAWDATA A Raw Data Input Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 69 Table 4 33 GPIOE Registers Address Map GPIOE_BASE 00 F330 Register Acronym Address Offset Register Description Reset Value GPIOE_PUR 0 Pull up Enable Register 0 x 3FFF GPIOE_DR 1 Data Register 0 x 0000 GPIOE_DDR 2 Data Direction Register 0 x 0000 GPIOE_PER 3 Peripheral Enable Register 0 x 3FFF GPIOE_IAR 4 Interrupt Assert Register 0 x 0000 GPIOE_IENR 5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOE_IPR 7 Interrupt Pending Register 0 x 0000 GPIOE_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOE_PPMODE 9 Push Pull Mode Register 0 x 3FFF GPIOE_RAWDATA A Raw Data Input Register Table 4 34 GPIOF Registers Address Map GPIOF_BASE 00 F340 Register Acronym Address Offset Register Description Reset Value GPIOF_PUR 0 Pull up Enable Register 0 x FFFF GPIOF_DR 1 Data Register 0 x 0000 GPIOF_DDR 2 Data Direction Register
38. Position Hold Register DECO_UIR B Upper Initialization Register DECO_LIR C Lower Initialization Register DECO_IMR D Input Monitor Register Table 4 18 Quadrature Decoder 1 Registers Address Map DEC1_BASE 00 F190 Quadrature Decoder 1 is NOT available on the 56F8166 device Register Acronym Address Offset Register Description DEC1_DECCR 0 Decoder Control Register DEC1_FIR 1 Filter Interval Register DEC1_WTR 2 Watchdog Time out Register DEC1_POSD 3 Position Difference Counter Register DEC1_POSDH 4 Position Difference Counter Hold Register DEC1_REV 5 Revolution Counter Register DEC1_REVH 6 Revolution Hold Register DEC1_UPOS 7 Upper Position Counter Register DEC1_LPOS 8 Lower Position Counter Register DEC1_UPOSH 9 Upper Position Hold Register DEC1_LPOSH A Lower Position Hold Register DEC1_UIR B Upper Initialization Register DEC1_LIR C Lower Initialization Register DEC1_IMR D Input Monitor Register 56F8366 Technical Data Rev 7 Freescale Semiconductor 61 Preliminary Table 4 19 Interrupt Control Registers Address Map ITCN_BASE 00 F1A0 Register Acronym Address Offset Register Description IPRO 0 Interrupt Priority Register 0 IPR 1 1 Interrupt Priority Register 1 IPR 2 2 Interrupt Priority Register 2 IPR 3 3 Interrupt Priority Register 3 IPR 4 4 Interrupt Pr
39. Rev 7 Freescale Semiconductor Preliminary Table 4 39 FlexCAN2 Registers Address Map Continued FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2IMASK2 7 Interrupt Masks 2 Register FC2RXGMASK_H 8 Receive Global Mask High Register FC2RXGMASK_L 9 Receive Global Mask Low Register FC2RX14MASK_H A Receive Buffer 14 Mask High Register FC2RX14MASK_L B Receive Buffer 14 Mask Low Register FC2RX15MASK_H C Receive Buffer 15 Mask High Register FC2RX15MASK_L D Receive Buffer 15 Mask Low Register Reserved FC2IFLAG 2 1B FC2STATUS 10 Error and Status Register FC2IMASK1 11 Interrupt Masks 1 Register FC2IFLAG1 12 Interrupt Flags 1 Register FC2R T_ERROR_CNTRS 13 Receive and Transmit Error Counters Register Reserved Interrupt Flags 2 Register Reserved FC2MBO_CONTROL 40 Message Buffer 0 Control Status Register FC2MBO_ID_HIGH 41 Message Buffer 0 ID High Register FC2MBO_ID_LOW 42 Message Buffer 0 ID Low Register FC2MBO_DATA 43 Message Buffer O Data Register FC2MBO_DATA 44 Message Buffer O Data Register FC2MBO_DATA 45 Message Buffer O Data Register FC2MBO_DATA 46 Message Buffer O Data Register FC2MSB1_CONTROL 48 Message Buffer 1 Control Status Register FC2MSB1_ID_HIGH 49 Message Buffer 1 ID High Register FC2MSB1_ID_LOW 4A Message Buffer 1 ID Low Register FC2MB1_D
40. Technical Data Rev 7 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset PHASEA1 6 Schmitt Input Phase A1 Quadrature Decoder 1 PHASEA input for decoder 1 Input pull up enabled TBO Schmitt TBO Timer B Channel 0 Input Output SCLK1 Schmitt SPI 1 Serial Clock In the master mode this pin serves as an Input output clocking slaved listeners In slave mode this pin serves as Output the data clock input To activate the SPI function set the PHSA_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOCO Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output In the 56F8366 the default state after reset is PHASEA1 In the 56F8166 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit O in the GPIOC_PUR register PHASEB1 7 Schmitt Input Phase B1 Quadrature Decoder 1 PHASEB input for decoder 1 Input pull up enabled TB1 Schmitt TB1 Timer B Channel 1 Input Output MOSI1 Schmitt SPI 1 Master Out Slave In This serial data pin is an output from Input a master device and an input to a slave device The master device Output places data on the MOSI line a half cycle before the clock edge the slave d
41. Wake Up Detection 10 15 JTAG Timing Table 10 23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation fop DC SYS_CLK 8 MHz 10 20 using EOnCE TCK frequency of operation not fop DC SYS_CLK 4 MHz 10 20 using EOnCE TCK clock pulse width tpw 50 ns 10 20 TMS TDI data set up time tos 5 ns 10 21 TMS TDI data hold time ton 5 ns 10 21 56F8366 Technical Data Rev 7 164 Freescale Semiconductor Preliminary JTAG Timing Table 10 23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK low to TDO data valid tov 30 ns 10 21 TCK low to TDO tri state tts 30 ns 10 21 TRST assertion time TRST 272 ns 10 22 1 TCK frequency of operation must be less than 1 8 the processor rate 2 T processor clock period nominally 1 60MHz TCK Input Vu Vi Vin Vit 2 Figure 10 20 Test Clock Input Timing Diagram TCK Input ON tos toH E gt gt TDI TMS SS Input Data Valid Input toy E gt TDO Output Output Data Valid trs TDO gt Output a tov TDO Output Output Data Valid Figure 10 21 Test Access Port Timing Diagram 56F8366 Technical Data Rev 7 Freescale Semiconductor 165 Preliminary TRST Input ttrst Figure 10 22 TRST Timing Diagram 10 16 Analog to Digital Converter ADC Parameters Table 10 24 ADC P
42. can be individually programmed Input as an input or output pin Outpu At reset this pin defaults to timer functionality To deactivate the internal pull up resistor clear bit 8 of the GPIOE_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor 35 Preliminary Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset TDO 116 Schmitt Input TDO TD1 Timer D Channels 0 and 1 Input pull up Output enabled GPIOE10 Schmitt Port E GPIO These GPIO pins can be individually programmed Input as input or output pins GPIOE11 At reset these pins default to Timer functionality To deactivate the internal pull up resistor clear the appropriate bit of the GPIOE_PUR register See Part 6 5 6 for details IRQA 54 Schmitt Input External Interrupt Request A and B The IRQA and IRQB Input pull up inputs are asynchronous external interrupt requests during Stop IRQB 55 enabled and Wait mode operation During other operating modes they are synchronized external interrupt requests which indicate an external device is requesting service They can be programmed to be level sensitive or negative edge triggered To deactivate the internal pull up resistor set the IRQ bit in the SIM_PUDR register See Part 6 5 6 for details RESET 86 Schmitt Input Reset This input is a direct hardware reset on the processor Input p
43. deactivate the internal pull up resistor set the JTAG bit in the SIM_PUDR register Note For normal operation connect TRST directly to Vgg If the design is to be used in a debugging environment TRST may be tied to Vss through a 1K resistor PHASEAO 139 Schmitt Input Phase A Quadrature Decoder 0 PHASEA input Input pull up enabled TAO Schmitt TAO Timer A Channel 0 Input Output GPIOC4 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After reset the default state is PHASEAO To deactivate the internal pull up resistor clear bit 4 of the GPIOC_PUR register PHASEBO 140 Schmitt Input Phase B Quadrature Decoder 0 PHASEB input Input pull up enabled TA1 Schmitt TA1 Timer A Channel Input Output GPIOC5 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After reset the default state is PHASEBO To deactivate the internal pull up resistor clear bit 5 of the GPIOC_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset INDEXO 141 Schmitt Input Index Quadrature Decoder 0 INDEX input Input pull up enabled TA2 Schmitt TA2 Timer
44. enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product c
45. method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash Additionally the KEYEN bit that allows backdoor key access must be set An alternative method for performing analysis on a secured hybrid controller would be to mass erase and reprogram the Flash with the original code but modify the security bytes To insure that a customer does not inadvertently lock himself out of the device during programming it is recommended that he program the backdoor access key first his application code second and the security bytes within the FM configuration field last Part 8 General Purpose Input Output GPIO 8 1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip specific information This information supercedes the generic information in the 56F8300 Peripheral User Manual 8 2 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers Based on this and the default function of each of the GPIO pins the reset values of the GPIOx_PUR and GPIOx_PER registers change from port to port Tables 4 29 through 4 34 define the actual reset values of these registers 8 3 Configuration There are six GPIO ports defined on the 56F8366 5
46. priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 6 ADC B Zero Crossing or Limit Error Interrupt Priority Level ADCB_ZC IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 104 Freescale Semiconductor Preliminary Register Descriptions 5 6 10 7 ADC A Conversion Complete Interrupt Priority Level ADCA_CC IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 8 ADC B Conversion Complete Interrupt Priority Level ADCB_CC IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 11 Vector Base Address Register VBA Base A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read VECTOR BASE ADDRESS Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 13 Vector Base Address Register VBA
47. registers Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers The top nine words of the Program Memory Flash are treated as special memory locations The content of these words is used to control the operation of the Flash Controller Because these words are part of the Flash Memory content their state is maintained during power down and reset During chip initialization the content of these memory locations is loaded into Flash Memory control registers detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual These configuration parameters are located between 03_FFF7 and 03_FFFF 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 47 Program Memory Data Memory BOOT_FLASH_START 3FFF FM_BASE 14 Banked Registers 32KB Boot FM_BASE 00 Unbanked Registers BOOT_FLASH_START 04 _0000 PROG_FLASH_START 03_FFFF Configure Field FM_PROG_MEM_TOP 01_FFFF DATA_FLASH_START 3FFF 256KB Program 32KB DATA_FLASH_START 0000 Note Data Flash is NOT available in the 56F8166 device ES BLOCK 1 Odd 2 Bytes 02_0003 BLOCK 1 Even 2 Bytes 02_0002 ES BLOCK 1 Odd 2 Bytes 02_0001 PROG_FLASH_START 02_0000 BLOCK 1 Even 2 Bytes 02_0000 PROG_FLASH_START 01_FFFF 256KB Program IE BLOCK 0 Odd 2 Bytes 00_0003 BLOCK 0 Even 2 Bytes 00_0002 IN
48. reset Data Bus D7 D14 specify part of the data for external program Output output is or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR D7 D14 are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOF0 Input Port F GPIO These eight GPIO pins can be individually Output programmed as input or output pins D8 29 GPIOF1 At reset these pins default to Data Bus functionality D9 30 To deactivate the internal pull up resistor clear the appropriate GPIOF2 GPIO bit in the GPIOF_PUR register ie a2 E le GPIOFO clear bit 0 in the GPIOF_PUR regist GPIOF3 xample Clear bit O in the a register D11 133 GPIOF4 D12 134 GPIOF5 D13 135 GPIOF6 D14 136 GPIOF7 D15 137 Input In reset Data Bus D15 specifies part of the data for external program or Output output is data memory accesses disabled pull up is Most designs will want to change the DRV state to DRV 1 instead of enabled using the default setting GPIOF8 Input Port F GPIO This GPIO pin can be individually programmed as Output an input or output pin At reset this pin defaults to the data bus function To deactivate the internal pull up resistor set bit 8 in the GPIOF_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor 23 Preliminary Table 2 2 Signal and Pac
49. ton 10 11 10 12 Master 0 ns 10 13 10 14 Slave 2 ns Access time time to data active from ta 10 14 high impedance state 4 8 15 ns Slave Disable time hold time to high impedance state tp 10 14 Slave 3 7 15 2 ns Data Valid for outputs tpv 10 11 10 12 Master 4 5 ns 10 13 10 14 Slave after enable edge 20 4 ns Data invalid tpi 10 11 10 12 Master 0 ns 10 13 Slave 0 ns Rise time tr 10 11 10 12 Master 11 5 ns 10 13 10 14 Slave 10 0 ns Fall time tr 10 11 10 12 Master 9 7 ns 10 13 10 14 Slave 9 0 ns Freescale Semiconductor Preliminary 159 SS Input SS is held High on master tc tr lt gt tf SCLK CPOL 0 Output SCLK CPOL 1 Output MOSI Output Figure 10 11 SPI Master Timing CPHA 0 SS Input te La gt SS is held High on master pt gt H tr Z teL SCLK CPOL 0 Output teH SCLK CPOL 1 Output MISO Input MOSI Output Figure 10 12 SPI Master Timing CPHA 1 56F8366 Technical Data Rev 7 160 Freescale Semiconductor Preliminary Serial Peripheral Interface SPI Timing Input SCLK CPOL 0 Input SCLK CPOL 1 Input MISO Output MOSI Input ss Input SCLK CPOL 0 Input SCLK CPOL 1 Input
50. when the external bus is inactive CS1 resets to provide the DS function as defined on the 56F80x devices GPIOD9 Input Port D GPIO This GPIO pin can be individually programmed as Output an input or output pin To deactivate the Internal pull up resistor clear bit 9 in the GPIOD_PUR register GPIODO 48 Input Input Port D GPIO This GPIO pin can be individually programmed as Output pull up an input or output pin enabled CS2 Output Chip Select CS2 may be programmed within the EMI module to act as a chip select for specific areas of the external memory map Depending upon the state of the DRV bit in the EMI Bus Control Register BCR CS2 is tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting CAN2_TX Open FlexCAN2 Transmit Data CAN output Drain Output At reset this pin is configured as GPIO This configuration can be changed by setting bit 0 in the GPIO_D_PER register Then change bit 4 in the SIM_GPS register to select the desired peripheral function To deactivate the internal pull up resistor clear bit O in the GPIOD_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 25 Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset GPIOD1 49 Schmitt Input Port D GPIO This GPIO pin can be indiv
51. 0 F360 Register Acronym Address Offset Register Description LVI_CONTROL 0 Control Register LVI_STATUS 1 Status Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 71 Table 4 37 Flash Module Registers Address Map FM_BASE 00 F400 Register Acronym Address Offset Register Description FMCLKD 0 Clock Divider Register FMMCR FMSECH 1 Module Control Register Security High Half Register FMSECL Security Low Half Register Reserved Reserved FMPROT 10 Protection Register Banked FMPROTB FMUSTAT 11 13 Protection Boot Register Banked User Status Register Banked FMCMD 14 Command Register Banked Reserved Reserved FMOPT 0 1A 16 Bit Information Option Register 0 Hot temperature ADC reading of Temperature Sensor value set during factory test FMOPT 1 FMOPT 2 1B 10 16 Bit Information Option Register 1 Not used 16 Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor value set during factory test Table 4 38 FlexCAN Registers Address Map FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMCR 0 Module Configuration Register FCCTLO 3 Co
52. 0 x 0000 GPIOF_PER 3 Peripheral Enable Register 0 x FFFF GPIOF_IAR 4 Interrupt Assert Register 0 x 0000 GPIOF_IENR 5 Interrupt Enable Register 0 x 0000 GPIOF_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOF_IPR 7 Interrupt Pending Register 0 x 0000 GPIOF_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOF_PPMODE 9 Push Pull Mode Register 0 x FFFF GPIOF_RAWDATA A Raw Data Input Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary C Peripheral Memory Mapped Registers Table 4 35 System Integration Module Registers Address Map SIM_BASE 00 F350 Register Acronym Address Offset Register Description SIM_CONTROL 0 Control Register SIM_RSTSTS 1 Reset Status Register SIM_SCRO 2 Software Control Register 0 SIM_SCR1 3 Software Control Register 1 SIM_SCR2 4 Software Control Register 2 SIM_SCR3 5 Software Control Register 3 SIM_MSH_ID 6 Most Significant Half JTAG ID SIM_LSH_ID 7 Least Significant Half JTAG ID SIM_PUDR 8 Pull up Disable Register SIM_CLKOSR A Clock Out Select Register SIM_GPS B Quad Decoder 1 Timer B SPI 1 Select Register SIM_PCE C Peripheral Clock Enable Register SIM_ISALH D 1 0 Short Address Location High Register SIM_ISALL E 1 0 Short Address Location Low Register SIM_PCE2 F Peripheral Clock Enable Register 2 Table 4 36 Power Supervisor Registers Address Map LVI_BASE 0
53. 06F8366 56F 8166 Data Sheet Preliminary Technical Data 56F8300 16 bit Digital Signal Controllers MC56F8366 Rev 7 11 2009 freescale com freescale semiconductor Document Revision History Version History Description of Change Rev 0 Pre release Alpha customers only Rev 1 0 Rev 2 0 Initial Public Release Added output voltage maximum value and note to clarify in Table 10 1 also removed overall life expectancy note since life expectancy is dependent on customer usage and must be determined by reliability engineering Clarified value and unit measure for Maximum allowed Pp in Table 10 3 Corrected note about average value for Flash Data Retention in Table 10 4 Added new RoHS compliant orderable part numbers in Table 13 1 Rev 3 0 Deleted formula for Max Ambient Operating Temperature Automotive and Max Ambient Operating Temperature Industrial and corrected Flash Endurance to 10 000 in Table 10 4 Added RoHS compliance and pb free language to back cover Rev 4 0 Added information corrected state during reset in Table 2 2 Clarified external reference crystal frequency for PLL in Table 10 14 by increasing maximum value to 8 4MHz Rev 5 0 Rev 6 Replaced Tri stated with an explanation in State During Reset column in Table 2 2 Added the following note to the description of the TMS signal in Table 2 2 Note Always tie the TMS pin to Vpp through a 2 2K resistor
54. 1 Control Registers a a W Q N Pin Function a a a Comments O a O l O O o oO N 0 Oo GPIO Input 0 0 GPIO Output 0 1 EMI I O 1 0 EMI CSn pins are always outputs CAN2 1 1 CAN2_TX is always an output CAN2_RX is always an input 1 This applies to the two pins that serve as EMI CSn CAN2 GPIOD functions A separate set of control bits is used for each pin 56F8366 Technical Data Rev 7 126 Freescale Semiconductor Preliminary Register Descriptions Base B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 10 0 0 10 10 D1 DO C3 C2 C1 co Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 12 GPIO Peripheral Select Register SIM_GPS 6 5 8 1 Reserved Bits 15 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 8 2 GPIOD1 D1 Bit 5 This bit selects the alternate function for GPIOD1 e 0 CS3 1 CAN2 RX 6 5 8 3 GPIODO D0 Bit 4 e 0 CS82 1 CAN2 TX 6 5 8 4 GPIOC3 C3 Bit 3 This bit selects the alternate function for GPIOC3 0 HOME TB3 default see Switch Matrix Mode bits of the Quad Decoder DECCR register in the 56F8300 Peripheral User Manual e 1 SSI 6 5 8 5 GPIOC2 C2 Bit 2 This bit selects the alternate function for GPIOC2 e 0 INDEX1 TB2 default e 1 MISO1l 6 5 8 6 GPIOC1 C1 Bit 1 This
55. 14 1 Reserved Bits 15 5 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 14 2 Fast Interrupt 0 Vector Address High FIVAHO Bits 4 0 The upper five bits of the vector address used for Fast Interrupt 0 This register is combined with FIVALO to form the 21 bit vector address for Fast Interrupt 0 defined in the FIMO register 5 6 15 Fast Interrupt 1 Match Register FIM1 Base E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 17 Fast Interrupt 1 Match Register FIM1 5 6 15 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 but cannot be modified by writing 5 6 15 2 Fast Interrupt 1 Vector Number FAST INTERRUPT 1 Bits 6 0 This value determines which IRQ will be a Fast Interrupt 1 Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first see Part 5 3 3 IRQs used as fast interrupts must be set to priority level 2 Unexpected results will occur if a fast interrupt vector is set to any other priority Fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt Fast Interrupt 0 has priority over Fast Interrupt 1 To determine the vector n
56. 28 Vcap3 83 Vcap4 15 Supply Supply Vcap1 4 When OCR_DIS is tied to Vgs regulator enabled connect each pin to a 2 2uF or greater bypass capacitor in order to bypass the core logic voltage regulator required for proper chip operation When OCR_DIS is tied to Vpp regulator disabled these pins become Vpp core and should be connected to a regulated 2 5V power supply Note This bypass is required even if the chip is powered with an external supply Vpp1 125 Vpp2 Input Input Vpp1 2 These pins should be left unconnected as an open circuit for normal functionality CLKMODE 87 Input Input Clock Input Mode Selection This input determines the function of the XTAL and EXTAL pins 1 External clock input on XTAL is used to directly drive the input clock of the chip The EXTAL pin should be grounded 0 A crystal or ceramic resonator should be connected between XTAL and EXTAL EXTAL 82 Input Input External Crystal Oscillator Input This input can be connected to an 8MHz external crystal Tie this pin low if XTAL is driven by an external clock source XTAL 81 Input Output Chip driven Crystal Oscillator Output This output connects the internal crystal oscillator output to an external crystal If an external clock is used XTAL must be used as the input and EXTAL connected to GND The input clock can be selected
57. 2s2p test boards is frequently lower than would be observed in an application Determined on 2s2p ther mal test board 2 Junction to ambient thermal resistance Theta JA Roja was simulated to be equivalent to the JEDEC specification JESD51 2 in a horizontal configuration in natural convection Theta JA was also simulated on a thermal test board with two internal planes 2s2p where s is the number of signal layers and p is the number of planes per JESD51 6 and JESD51 7 The correct name for Theta JA for forced convection or with the non single layer boards is Theta JMA 3 Junction to case thermal resistance Theta JC Rgjc was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the case temperature The basic cold plate measurement technique is described by MIL STD 883D Method 1012 1 This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink 4 Thermal Characterization Parameter Psi JT Y y is the resistance from junction to reference point thermocouple on top cen ter of case as defined in JESD51 2 Vj is a useful value to use to estimate junction temperature in steady state customer en vironments 5 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of othe
58. 3_CMP1 30 Compare Register 1 TMRC3_CMP2 31 Compare Register 2 TMRC3_CAP 32 Capture Register TMRC3_LOAD 33 Load Register TMRC3_HOLD 34 Hold Register TMRC3_CNTR 35 Counter Register TMRC3_CTRL 36 Control Register TMRC3_SCR 37 Status and Control Register TMRC3_CMPLD1 38 Comparator Load Register 1 TMRC3_CMPLD2 39 Comparator Load Register 2 TMRC3_COMSCR 3A Comparator Status and Control Register Table 4 14 Quad Timer D Registers Address Map TMRD_BASE 00 F100 Quad Timer D is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRDO_CMP1 0 Compare Register 1 TMRDO_CMP2 1 Compare Register 2 TMRDO_CAP 2 Capture Register TMRDO_LOAD 3 Load Register TMRDO_HOLD 4 Hold Register TMRDO_CNTR 5 Counter Register TMRDO_CTRL 6 Control Register TMRDO_SCR 7 Status and Control Register TMRDO_CMPLD1 8 Comparator Load Register 1 TMRDO_CMPLD2 9 Comparator Load Register 2 TMRDO_COMSCR A Comparator Status and Control Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 57 Table 4 14 Quad Timer D Registers Address Map Continued TMRD_BASE 00 F100 Quad Timer D is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRD1_CMP1 10 Compare Register 1 TMRD1_CMP2 11 Compare Register 2 TMRD1_CAP 12 Capture Register TMRD1_LOAD 13 Load R
59. 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 16 2 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 20 IRQ Pending 0 Register IRQPO 5 6 18 1 IRQ Pending PENDING Bits 16 2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 18 2 Reserved Bit 0 This bit is reserved or not implemented It is read as 1 and cannot be modified by writing 5 6 19 IRQ Pending 1 Register IRQP1 Base 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 32 17 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 21 IRQ Pending 1 Register IRQP1 56F8366 Technical Data Rev 7 108 Freescale Semiconductor Preliminary Register Descriptions 5 6 19 1 IRQ Pending PENDING Bits 32 17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 20 IRQ Pending 2 Register IRQP2 Base 13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 5 22 IRQ Pending 2 Register IRQP2 5 6 20 1 IRQ Pending PENDING Bits 48 33 This register combines with the other five to represe
60. 4 PLACES SSN VIEW B Ve 0 1 A 144x Ma X B C or D L_ 140X e NOTES A gt A A A gt VNUNW3T1U A ALL DIMENSIONS ARE IN MILLIMETERS NTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 DATUMS B C AND D TO BE DETERMINED AT DATUM THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM F 0 1 mm MENSIONS D1 AND E1 DO NOT INCLUDE MOLD ROTRUSIONS THE MAXIMUM ALLOWABLE RUSION IS 0 25 mm PER SIDE D1 AND E1 ARE JAXIMUM BODY SIZE DIMENSIONS INCLUDING MOLD SMATCH MENSION b DOES NOT INCLUDE DAMBAR ROTRUSION PROTRUSIONS SHALL NOT CAUSE HE LEAD WIDTH TO EXCEED 0 35 MINIMUM SPACE ETWEEN PROTRUSION AND AN ADJACENT LEAD HALL BE 0 07 mm MENSIONS D AND E TO BE DETERMINED AT THE EATING PLANE DATUM A ZZUVUUVUO pe Oo MILLIMETERS DIM MIN MAX 1 60 A1 0 05 0 15 A2 1 35 1 45 b 0 17 0 27 b1 0 17 0 23 R2 c 009 0 20 ci 009 0 16 7 D 22 00 BSC R1 D1 20 00 BSC e 0 50 BSC E 22 00 BSC 0 25 El 20 00 BSC GAGE PLANE L 045 075 ES BO L1 1 00 REF j AMOS L2 0 50 REF T R1 0 13 0 20 L2 sf R2 0 13 A1 S 0 25 REF L 0 9 0 7 Ss 91 0 O os 02 12 REF Figure 11 3 144 pin LQFP Mechanical Information 56F8366 Technical Data Rev 7 Freescale Semicon
61. 5 First Interrupt Instruction Execution tom IRQA IRQB a First Interrupt Instruction Execution General _ __ Purpose 1 0 Pin _ es tic IRQA j __ IRQB b General Purpose I O Figure 10 8 External Level Sensitive Interrupt Timing IRQA IRQB _ tii A0 A15 First Interrupt Vector Instruction Fetch Figure 10 9 Interrupt from Wait State Timing Se tiw IRQA tir A0O A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10 10 Recovery from Stop State Using Asynchronous Interrupt Timing 56F8366 Technical Data Rev 7 158 Freescale Semiconductor Preliminary 10 10 Serial Peripheral Interface SPI Timing Table 10 18 SPI Timing Serial Peripheral Interface SPI Timing 1 Parameters listed are guaranteed by design 56F8366 Technical Data Rev 7 Characteristic Symbol Min Max Unit See Figure Cycle time tc 10 11 10 12 Master 50 ns 10 13 10 14 Slave 50 ns Enable lead time teLp 10 14 Master ns Slave 25 ns Enable lag time teELc 10 14 Master ns Slave 100 ns Clock SCK high time tcH 10 11 10 12 Master 17 6 ns 10 13 10 14 Slave 25 ns Clock SCK low time teL 10 14 Master 24 1 ns Slave 25 ns Data set up time required for inputs tos 10 11 10 12 Master 20 ns 10 13 10 14 Slave 0 ns Data hold time required for inputs
62. 5 7 6 Clockout Disable CLKDIS Bit 5 e 0 CLKOUT output is enabled and will output the signal indicated by CLKOSEL e 1 CLKOUT is tri stated 6 5 7 7 CLockout Select CLKOSEL Bits 4 0 Selects clock to be muxed out on the CLKO pin 00000 SYS_CLK from OCCS DEFAULT e 00001 Reserved for factory test 56800E clock e 00010 Reserved for factory test XRAM clock e 00011 Reserved for factory test PFLASH odd clock e 00100 Reserved for factory test PFLASH even clock e 00101 Reserved for factory test BFLASH clock e 00110 Reserved for factory test DFLASH clock e 00111 Oscillator output e 01000 Fout from OCCS e 01001 Reserved for factory test IPB clock e 01010 Reserved for factory test Feedback from OCCS this is path to PLL e 01011 Reserved for factory test Prescaler clock from OCCS e 01100 Reserved for factory test Postscaler clock from OCCS e 01101 Reserved for factory test SYS_CLK2 from OCCS e 01110 Reserved for factory test SYS_CLK_DIV2 e 01111 Reserved for factory test SYS_CLK_D e 10000 ADCA clock e 10001 ADCB clock 6 5 8 GPIO Peripheral Select Register SIM_GPS Some GPIO pads can have more than one peripheral selected as the alternate function instead of GPIO For these pads this register selects which of the alternate peripherals are actually selected for the GPIO peripheral function This applies to GPIOC pins 0 3 and to GPIOD pins 0 and 1 The GPIO
63. 5 8 Lig AL ZTE Z oo ooaSsERB SIS PEER FEPPPanHaHZZ2 v O Orientation Mark N DD_IO ANB4 Vpp2 Taa 1 ANB3 CLKO Pin 1 109 ANB2 TXDO n ANB1 RXDO C ANBO PHASEA1 E Vessa Apc PHASEB1 Voie INDEX1 i HOME1 Veep o VREFMID Ka Vrern VeerLO E E Temp_Sense ANA7 Vcap4 ANAG Vooo E E ANAS A6 ANA4 A7 HL ANA3 A8 ANA2 A9 ANA1 A10 E ANAO A11 I CLKMODE A12 RESET A13 RSTO aia Vpp_Io Me E Vcap3 ss N EXTAL E XTAL Da VpDA_OSC_PLL V OCR_DIS DD_o EE D6 D10 DE GPIOBO D4 PWMBO 37 73 D3 PWMB1 FAULTA2 PWMB2 CT ra FAULTA1 aom NAT MT KIAINJINOT 27 NLM or NOTMO NTN ONY NIHON 2 2m AnA D reana saa manaa Ge IIIA FEEF EEEE E REE RERE gt sesz Ll ao gt PTOS 53 s235 22 2 Figure 11 1 Top View 56F8366 144 Pin LQFP Package 56F8366 Technical Data Rev 7 Freescale Semiconductor 171 Preliminary Table 11 1 56F8366 144 Pin LQFP Package Identification by Pin Number Pin No ei Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 Vpp_10 37 Vss 73 FAULTA1 109 ANB5 2 Vpp2 38 Vpp_Io 74 FAULTA2 110 ANB6 3 CLKO 39 PWMB3 75 D3 111 ANB7 4 TXDO 40 PWMB4 76 D4 112 EXTBOOT 5 RXDO 41 PWMB5 77 D5 113 ISAO 6 PHASEA1 42 TXD1 78 D6 114 ISA1 7 PHASEB1 43 RXD1 79 OCR_DIS 115 ISA2 8 INDEX1 44 WR 80 Vppa_OSC_PLL 116 TDO 9 HOME1 45 RD 81 XTAL 117 TD1 10 A1 46 PS 82 EXTAL 118 TCO 11 A2 47 DS 83 Vcap3 119 Vop_lo 12 A3 48 GPIODO 84 Vpp_10 120 TRST
64. 6F8166 The width of each port and the associated peripheral function is shown in Table 8 1 and Table 8 2 The specific mapping of GPIO port pins is shown in Table 8 3 56F8366 Technical Data Rev 7 Freescale Semiconductor 137 Preliminary Table 8 1 56F8366 GPIO Ports Configuration Available er a Pins in Peripheral Function Reset Function 56F8366 A 14 14 14 pins EMI Address pins EMI Address B 8 1 1 pin EMI Address pin EMI Address 7 pins EMI Address pins Not available in this package N A C 11 11 4 pins DEC1 TMRB SP11 DEC1 TMRB 4 pins DECO TMRA DECO TMRA 3 pins PWMA current sense PWMA current sense D 13 9 2 pins EMI CSn EMI Chip Selects 4 pins EMI CSn Not available in this package N A 2 pins SCI1 Sci 2 pins EMI CSn EMI Chip Selects 3 pins PWMB current sense PWMB current sense E 14 11 2 pins SCIO SCIO 2 pins EMI Address pins EMI Address 4 pins SPIO SPIO 1 pin TMRC TMRC 1 pin TMRC Not available in this package N A 2 pins TMRD TMRD 2 pins TMRD Not available in this package N A F 16 16 16 pins EMI Data EMI Data Table 8 2 56F8166 GPIO Ports Configuration Available ear T Pins in Peripheral Function Reset Function 56F8166 A 14 14 14 pins EMI Address pins EMI Address B 8 1 1 pin EMI Address pin EMI Address 7 pins EMI Address pins Not available in this package N A C 11 11 4 pins SP11 SP11 4 pins DECO TMRA DECO
65. 8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 45 Table 4 5 Interrupt Vector Table Contents Continued Peripheral E T eae ae Interrupt Function TMRC 56 0 2 P 70 Timer C Channel 0 TMRC 57 0 2 P 72 Timer C Channel 1 TMRC 58 0 2 P 74 Timer C Channel 2 TMRC 59 0 2 P 76 Timer C Channel 3 TMRB 60 0 2 P 78 Timer B Channel 0 TMRB 61 0 2 P 7A Timer B Channel 1 TMRB 62 0 2 P 7C Timer B Channel 2 TMRB 63 0 2 P 7E Timer B Channel 3 TMRA 64 0 2 P 80 Timer A Channel 0 TMRA 65 0 2 P 82 Timer A Channel 1 TMRA 66 0 2 P 84 Timer A Channel 2 TMRA 67 0 2 P 86 Timer A Channel 3 SCIO 68 0 2 P 88 SCI 0 Transmitter Empty SCIO 69 0 2 P 8A SCI 0 Transmitter Idle SCIO 71 0 2 P 8E SCI 0 Receiver Error SCIO 72 0 2 P 90 SCI 0 Receiver Full ADCB 73 0 2 P 92 ADC B Conversion Compete End of Scan ADCA 74 0 2 P 94 ADC A Conversion Complete End of Scan ADCB 75 0 2 P 96 ADC B Zero Crossing or Limit Error ADCA 76 0 2 P 98 ADC A Zero Crossing or Limit Error PWMB 77 0 2 P 9A Reload PWM B PWMA 78 0 2 P 9C Reload PWM A PWMB 79 0 2 P 9E PWM B Fault PWMA 80 0 2 P A0 PWM A Fault core 81 1 P A2 SW Interrupt LP FLEXCAN2 82 0 2 P A4 FlexCAN Bus Off FLEXCAN2 83 0 2 P A6 FlexCAN Error FLEXCAN2 84 0 2 P A8 FlexCAN Wake Up FLEXCAN2 85 0 2 P SAA FlexCAN Message Buffer Interrupt 1 Two words are allocated for each e
66. A Channel 2 Input Output GPOPC6 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After reset the default state is INDEXO To deactivate the internal pull up resistor clear bit 6 of the GPIOC_PUR register HOMEO 142 Schmitt Input Home Quadrature Decoder 0 HOME input Input pull up enabled TA3 Schmitt TA3 Timer A Channel 3 Input Output GPIOC7 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After reset the default state is HOMEO To deactivate the internal pull up resistor clear bit 7 of the GPIOC_PUR register SCLKO 130 Schmitt Input SPI 0 Serial Clock In the master mode this pin serves as an Input pull up output clocking slaved listeners In slave mode this pin serves as Output enabled the data clock input GPIOE4 Schmitt Port E GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After reset the default state is SCLKO To deactivate the internal pull up resistor clear bit 4 in the GPIOE_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor 29 Preliminary Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset MOSIO 132 Input In reset SPI 0 Master Out Slave In This serial data pin is an output from Output output is a master devi
67. A12 59 DO 95 ANA7 131 MISOO 24 A13 60 D1 96 NC 132 MOSIO 25 A14 61 FAULTB3 97 VREFLO 133 D11 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 175 Table 11 2 56F8166 144 Pin LQFP Package Identification by Pin Number Continued Pin No ta Pin No Signal Name Pin No Signal Name Pin No Signal Name 26 A15 62 NC 98 VREEN 134 D12 27 Vss 63 Vss 99 VREFMID 135 D13 28 D7 64 NC 100 VREFP 136 D14 29 D8 65 NC 101 VREFH 137 D15 30 D9 66 Vpp_10 102 Vppa_ADC 138 AO 31 Vpp_10 67 NC 103 VssA_ADC 139 PHASEAO 32 D10 68 NC 104 ANBO 140 PHASEBO 33 GPIOBO 69 Vss 105 ANB1 141 INDEXO 34 PWMBO 70 NC 106 ANB2 142 HOMEO 35 PWMB1 71 NC 107 ANB3 143 EMI_MODE 36 PWMB2 72 D2 108 ANB4 144 Vss 56F8366 Technical Data Rev 7 176 Freescale Semiconductor Preliminary 4x O 0 20 H B C D PIN 1 144 INDEX gt 0 20 A B C D 4X 36 TIPS 109 108 D1 D 2 37 e D D1 2 56F8166 Package and Pin Out Information 4x e 2 Fe E1 2 D A TOP VIEW SIDE VIEW PLATING Es FS bt c1 A gt gt gt ZZ Al b METAL 0 08 A B C D SECTION A A ROTATED 90 14
68. ATA 4B Message Buffer 1 Data Register FC2MB1_DATA 4C Message Buffer 1 Data Register FC2MB1_DATA 4D Message Buffer 1 Data Register FC2MB1_DATA 4E Message Buffer 1 Data Register Reserved 56F8366 Technical Data Rev 7 78 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 39 FlexCAN2 Registers Address Map Continued FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MB2_CONTROL 50 Message Buffer 2 Control Status Register FC2MB2_ID_HIGH 51 Message Buffer 2 ID High Register FC2MB2_ID_LOW 52 Message Buffer 2 ID Low Register FC2MB2_DATA 53 Message Buffer 2 Data Register FC2MB2_DATA 54 Message Buffer 2 Data Register FC2MB2_DATA 55 Message Buffer 2 Data Register FC2MB2_DATA 56 Message Buffer 2 Data Register Reserved FC2MB3_CONTROL 58 Message Buffer 3 Control Status Register FC2MB3_ID_HIGH 59 Message Buffer 3 ID High Register FC2MB3_ID_LOW 5A Message Buffer 3 ID Low Register FC2MB3_DATA 5B Message Buffer 3 Data Register FC2MB3_DATA 5C Message Buffer 3 Data Register FC2MB3_DATA 5D Message Buffer 3 Data Register FC2MB3_DATA 5E Message Buffer 3 Data Register Reserved FC2MB4_CONTROL 60 Message Buffer 4 Control Status Register FC2MB4_ID_HIGH 61 Message Buffer 4 ID High Register FC2MB4_ID_LOW 62 Message Buffer 4 ID Low Register FC2MB4_DA
69. Base Address VBA register Please see Part 5 6 12 for the reset value of the VBA In some configurations the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table In these instances the first two locations in the vector table must contain branch or JMP instructions All other entries must contain JSR instructions Note PWMA FlexCAN Quadrature Decoder I and Quad Timers B and D are NOT available on the 56F8166 device Table 4 5 Interrupt Vector Table Contents Vector Priority Vector Base Peripheral Number Level Address Interrupt Function Reserved for Reset Overlay Reserved for COP Reset Overlay core 2 3 P 04 Illegal Instruction core 3 3 P 06 SW Interrupt 3 core 4 3 P 08 HW Stack Overflow core 5 3 P 0A Misaligned Long Word Access core 6 1 3 P 0C OnCE Step Counter core 7 1 3 P 0E OnCE Breakpoint Unit 0 core 9 1 3 P 12 OnCE Trace Buffer core 10 1 3 P 14 OnCE Transmit Register Empty core 11 1 3 P 16 OnCE Receive Register Full core 14 2 P 1C SW Interrupt 2 core 15 1 P 1E SW Interrupt 1 core 16 0 P 20 SW Interrupt 0 core 17 0 2 P 22 IRQA core 18 0 2 P 24 IRQB Reserved LVI 20 0 2 P 28 Low Voltage Detector power sense 56F8366 Technical Data Rev 7 44 Freescale Semiconductor Preliminary Interrupt Vector Table Table 4 5 Interrupt Vector Table C
70. C Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC The default peripheral is Quad Decoder I and Quad Timer B NOT available in the 56F 8166 device these peripherals work together The four I O pins associated with GPIOC can function as GPIO Quad Decoder I Quad Timer B or as SPI 1 signals GPIO is not the default and is enabled disabled via the GPIOC_PER as shown in Figure 6 10 and Table 6 2 When GPIOC 3 0 are programmed to operate as peripheral I O then the choice between decoder timer and SPI inputs outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers SCR The default state is for the peripheral function of GPIOC 3 0 to be programmed as decoder functions This can be changed by altering the appropriate controls in the indicated registers 56F8366 Technical Data Rev 7 124 Freescale Semiconductor Preliminary Register Descriptions GPIOC_PER Register GPIO Controlled 1 0 Pad Control SIM_ GPS Register Quad Timer Controlled SPI Controlled 1 Figure 6 10 Overall Control of GPIOC Pads Using SIM_GPS Control Table 6 2 Control of GPIOC Pads Using SIM_GPS Control 1 Control Registers X x o Ww E N on Pin Function a a A Eos Comments oO Fo 2 Oo oO I z O O By E a a D 3 0 O O og GPIO Input 0 0 GPIO Output 0 1 Quad Time
71. Clocks Description Run Active Active Device is fully functional Wait Core and memory Active Peripherals are active and can product interrupts if they clocks disabled have not been masked off Interrupts will cause the core to come out of its suspended state and resume normal operation Typically used for power conscious applications Stop System clocks continue to be generated in The only possible recoveries from Stop mode are the SIM but most are gated prior to 1 CAN traffic 1st message will be lost reaching memory core and peripherals 2 Non clocked interrupts 3 COP reset 4 External reset 5 Power on reset All peripherals except the COP watchdog timer run off the IPbus clock frequency which is the same as the main processor frequency in this architecture The maximum frequency of operation is SYS_CLK 60MHz 56F8366 Technical Data Rev 7 132 Freescale Semiconductor Preliminary Stop and Wait Mode Disable Function 6 8 Stop and Wait Mode Disable Function Permanent Disable _ D Q J D FLOP C 56800E Reprogrammable le gt Disable gt D Q E DS ia D FLOP Clock c Select R Note Wait disable circuit is Reset A similar Figure 6 17 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions Both put the CPU to sleep For lowest power consumption in Stop mode the PLL can be shut down
72. Hold Register TMRCO_CNTR 5 Counter Register TMRCO_CTRL 6 Control Register TMRCO_SCR 7 Status and Control Register TMRCO_CMPLD1 8 Comparator Load Register 1 TMRCO_CMPLD2 9 Comparator Load Register 2 TMRCO_COMSCR A Comparator Status and Control Register TMRC1_CMP1 10 Compare Register 1 TMRC1_CMP2 11 Compare Register 2 TMRC1_CAP 12 Capture Register TMRC1_LOAD 13 Load Register TMRC1_HOLD 14 Hold Register TMRC1_CNTR 15 Counter Register TMRC1_CTRL 16 Control Register TMRC1_SCR 17 Status and Control Register TMRC1_CMPLD1 18 Comparator Load Register 1 TMRC1_CMPLD2 19 Comparator Load Register 2 TMRC1_COMSCR 1A Comparator Status and Control Register TMRC2_CMP1 20 Compare Register 1 TMRC2_CMP2 21 Compare Register 2 TMRC2_CAP 22 Capture Register TMRC2_LOAD 23 Load Register TMRC2_HOLD 24 Hold Register TMRC2_CNTR 25 Counter Register TMRC2_CTRL 26 Control Register 56F8366 Technical Data Rev 7 56 Freescale Semiconductor Preliminary Table 4 13 Quad Timer C Registers Address Map Continued Peripheral Memory Mapped Registers TMRC_BASE 00 FOCO Register Acronym Address Offset Register Description TMRC2_SCR 27 Status and Control Register TMRC2_CMPLD1 28 Comparator Load Register 1 TMRC2_CMPLD2 29 Comparator Load Register 2 TMRC2_COMSCR 2A Comparator Status and Control Register TMRC
73. INTERRUPT PROGRAM CONTROL Figure 2 1 56F8366 Signals Identified by Functional Group 144 pin LQFP 1 Alternate pin functionality is shown in parenthesis pin direction type shown is the default functionality 56F8366 Technical Data Rev 7 16 Freescale Semiconductor Preliminary Power Power Power Ground Ground Other Supply Ports PLL and Clock External Address Bus or GPIO External Data Bus or GPIO External Bus Control or GPIO SCI 0 or GPIO SCI 1 or GPIO JTAG EOnCE Port Vpp_Io gt VDDA_ADC gt VpDA_OSC_PLL Vss Vssa_ADC gt OCR_DIS z Veapt Veap4 a Vpp1 amp Vpp2 PP PP2 CLKMODE EXTAL XTAL e E a CLKO _f0 A5 GPIOAS AG A7 GPIOE2 3 A8 A15 GPIOAO 7 GPIOBO A16 DQ D6 GPIOF9 15 D7 D15 GPIOFO RD WR lt a PS CS0 GPIOD8 _ e DS CS1 GPIOD9 GPIODO 1 CS2 3 gt TXDO GPIOEO RXDO GPIOE1 TXD1 GPIOD6 RXD1 GPIOD7 TCK TMS PHASEAO TAO GPIOC4 PHASEBO TA1 GPIOC5 INDEXO TA2 GPIOC6 HOMEO TA3 GPIOC7 56F8166 SCLKO qa MOSIO MISOO SS0 GPIOE7 q SCLK1 GPIOCO MOS GPIOC1 q MISO1 GPIOC2 ES GPIOC3 A AAA Cee GPIOCE 10 PVWMBO 5 ne iq SB0 2 GPIOD10 12 _ FAULTBO 3
74. IRQ is priority level 2 5 6 7 8 Quadrature Decoder 0 HOME Signal Transition or Watchdog Timer Interrupt Priority Level DECO_HIRQ IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 Interrupt Priority Register 7 IPR7 Base 7 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read a TMRAO IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRBO IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL rite RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 10 Interrupt Priority Register IPR7 5 6 8 1 Timer A Channel 0 Interrupt Priority Level TMRAO IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freescale Semiconductor 99 Preliminary 5 6 8 2 Timer B Channel 3 Interrupt Priority Level TMRB3 IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is p
75. L eS vyyyyy Vssa_ADC OCR_DIS Vcap1 Vcap4 Vpp1 8 Vpp2 PP BPA CLKMODE EXTAL XTAL CLKO AQ A5 GPIOAS 13 AS A7 GPIOE2 3 A8 A15 GPIOAO 7 GPIOBO A16 DO D6 GPIOF9 15 et ee D7 D15 GPIOFO 8 RD WR 7 PS CSO GPIOD8 DS CS1 GPIOD9 q mM TXDO GPIOEO RXDO GPIOE1 TXD1 GPIOD6 RXD1 GPIOD7 TCK TMS Tol TDO TRST E E ee ed pe 56F 8366 Aes RN PHASEAO TAO GPIOC4 PHASEBO TA1 GPIOC5 INDEXO TA2 GPIOC6 AAAA HOMEO TA3 GPIOC7 SCLKO GPIOE4 MOSIO GPIOE5 MISOO GPIOE6 SSO GPIOE7 PHASEA1 TB0 SCLK1 GPIOCO PHASEB1 TB1 MOSI1 GPIOC1 INDEX1_ TB2 MISO1 GPIOC2 A A A A HOME1 TB3 SS1 GPIOC3 PWMAO 5 me SAO 2 GPIOC8 10 FAULTAO 2 a PWMBO 5 SB 2 GPIOD10 12 FAULTBO 3 lt a ANAO 7 y a REF ANBO 7 TEMP_SENSE q gt CAN_RX CAN_TX TCO GPIOE8 TDO 1 GPIOE10 11 A AAAA IRQA IRQB EXTBOOT EMI_MODE RESET RSTO Quadrature Decoder 0 or Quad Timer A or GPIO SPIO or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or _ GPIO PWMA or GPIO PWMB or GPIO ADCA ADCB Temperature Sensor FlexCAN QUAD TIMER C and D or GPIO
76. Limit Status Register ADCA_ZCSTAT 8 Zero Crossing Status Register ADCA_RSLT 0 9 Result Register 0 ADCA_RSLT 1 A Result Register 1 ADCA_RSLT 2 B Result Register 2 ADCA_RSLT 3 C Result Register 3 ADCA_RSLT 4 D Result Register 4 ADCA_RSLT 5 E Result Register 5 ADCA_RSLT 6 F Result Register 6 ADCA_RSLT 7 10 Result Register 7 ADCA_LLMT 0 11 Low Limit Register 0 ADCA_LLMT 1 12 Low Limit Register 1 ADCA_LLMT 2 13 Low Limit Register 2 ADCA_LLMT 3 14 Low Limit Register 3 ADCA_LLMT 4 15 Low Limit Register 4 ADCA_LLMT 5 16 Low Limit Register 5 ADCA_LLMT 6 17 Low Limit Register 6 ADCA_LLMT 7 18 Low Limit Register 7 ADCA_HLMT 0 19 High Limit Register 0 ADCA_HLMT 1 1A High Limit Register 1 ADCA_HLMT 2 1B High Limit Register 2 ADCA_HLMT 3 1C High Limit Register 3 ADCA_HLMT 4 1D High Limit Register 4 ADCA_HLMT 5 1E High Limit Register 5 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 63 Table 4 20 Analog to Digital Converter Registers Address Map Continued ADCA_BASE 00 F200 Register Acronym Address Offset Register Description ADCA_HLMT 6 1F High Limit Register 6 ADCA_HLMT 7 20 High Limit Register 7 ADCA_OFS 0 21 Offset Register 0 ADCA_OFS 1 22 Offset Register 1 ADCA_OFS 2 23 Offset Register 2 ADCA_OFS 3 24 Offset Register 3 ADCA_OFS 4 25 Offset Register 4 ADCA_OFS 5 26 Offset Register 5 ADCA_OFS 6 27 Offset Register 6 ADCA_OFS 7 28 Of
77. MA0 Bit 7 This bit controls the pull up resistors on the FAULTAO FAULTAI and FAULTA2 pins 6 5 6 10 Reserved Bit 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 6 11 CTRL Bit 5 This bit controls the pull up resistors on the WR and RD pins 6 5 6 12 Reserved Bit 4 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 6 13 JTAG Bit 3 This bit controls the pull up resistors on the TRST TMS and TDI pins 56F8366 Technical Data Rev 7 122 Freescale Semiconductor Preliminary Register Descriptions 6 5 6 14 Reserved Bit 2 0 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 7 CLKO Select Register SIM_CLKOSR The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules The default value is SYS_CLK All other clocks primarily muxed out are for test purposes only and are subject to significant unspecified latencies at high frequencies The upper four bits of the GPIOB register can function as GPIO A 23 20 or as additional clock output signals GPIO has priority and is enabled disabled via the GPIOB_PER If GPIO B 7 4 are programmed to operate as peripheral outputs then the choice between A 23 20 and additional clock outputs is done here in the CLKOSR The default state is for the periphera
78. O 2 ISA0 2 TCO SCLKO Pin Group 3 RSTO TDO Pin Group 4 CAN_TX OE Pin Group 5 A0 5 D0 15 GPIODO 1 PS DS Pin Group 6 A6 15 GPIOBO TDO 1 Pin Group 7 CLKO WR RD Pin Group 8 PWMAO 5 PWMBO 5 Pin Group 9 IRQA IRQB RESET EXTBOOT TRST TMS TDI CAN_RX EMI_MODE FAULTAO 3 FAULTBO 3 Pin Group 10 TCK Pin Group 11 XTAL EXTAL Pin Group 12 ANAO 7 ANBO 7 Pin Group 13 OCR_DIS CLKMODE 56F8366 Technical Data Rev 7 144 Freescale Semiconductor Preliminary General Characteristics Table 10 2 56F8366 56F8166 ElectroStatic Discharge ESD Protection Characteristic Min Typ Max Unit ESD for Human Body Model HBM 2000 V ESD for Machine Model MM 200 V ESD for Charge Device Model CDM 500 V Table 10 3 Thermal Characteristics Value Characteristic Comments Symbol Unit Notes 144 pin LQFP Junction to ambient Rosa 47 1 C W 2 Natural convection Junction to ambient 1m sec Regma 43 8 C W 2 Junction to ambient Four layer board 2s2p RoJMA 40 8 C W 1 2 Natural convection 2s2p Junction to ambient 1m sec Four layer board 2s2p RoJMA 39 2 C W 1 2 Junction to case Roc 11 8 C W 3 Junction to center of case Por 1 C W 4 5 I O pin power dissipation P o User determined W Power dissipation Pp P p lbp X Vop P 1 0 W Maximum allowed Pp Ppmax TJ TA ROJA Ww 1 Theta JA determined on
79. OP is disabled and PWM outputs are optionally switched off to disable any motor from being driven see the PWM chapter in the 56F8300 Peripheral User Manual for details Wait Mode In Wait mode the core clock and memory clocks are disabled Optionally the COP can be stopped Similarly it is an option to switch off PWM outputs to disable any motor from being driven All other peripherals continue to run 56F8366 Technical Data Rev 7 Freescale Semiconductor 115 Preliminary Stop Mode When in Stop mode the 56800E core memory and most peripheral clocks are shut down Optionally the COP and CAN can be stopped For lowest power consumption in Stop mode the PLL can be shut down This must be done explicitly before entering Stop mode since there is no automatic mechanism for this The CAN along with any non gated interrupt is capable of waking the chip up from Stop mode but is not fully functional in Stop mode 6 4 Operating Mode Register Bit Type RESET 8 7 6 5 4 1 0 CM XP SD R SA MB MA RW RW RW RW RW RW R W 0 0 0 0 0 0 0 0 X X Figure 6 1 OMR The reset state for MB and MA will depend on the Flash secured state See Part 4 2 and Part 7 for detailed information on how the Operating Mode Register OMR MA and MB bits operate in this device For additional information see the DSP56800E Reference Manual Not
80. OnCE for unobtrusive real time debugging Up to 62 GPIO lines 144 pin LQFP Package 5 OCR_DIS sora EMI MODE RSTO Ej Vep Vcap Voo Vss Voma Vssa A EXTBOOT 5 mene of of ob of p A PWM Outputs PWMA Elio Digital Reg Analog Reg n 3 gt Suten Sense Inputs Port 16 Bit o Voltage 3 56800E Core aes arama Fault Inputs 6 Program Controller Address Data ALU Bit lt 7 PWM Outputs PWMB and Generation Unit 16x 16 36 gt 36 BitMAC Manipulation 3 Hardware Looping Unit Three 16 bit Input Registers Unit gt Current Sense Inputs Four 36 bit Accumulators 4 or GPIOD S Fault Inputs Vv AA PAB A iat A PDB 24 CDBR 1 L 4 y Y CDB 4 Y 5 yen Control 7 gt XDB2 6 4y ADO Program Memory XAB1 2 Eeinal gt A0 5 or GPIOA8 13 4 ap ADCB PA xe paS lt XAB2 1 Address Bus 272 A6 7 or GPIOE2 3 A4 x i z Boot ROM lt 4 PRE System Bus a Switch 852 A8 15 or GPIOA0 7 Tr x emp Sense 46K x 16 Flash BDB y Control a gt Pd GPIOBO oF A16 ene Data Memory CDBR Ji 3 8 External Data Baud DO 6 or GPIOF9 15 44 gt Quad 16K x 16 Flash CDBW 3 Bus Switch 9 D7 15 or GPIOF0 8 panai 1 A Timer A or 16K x 16 RAM ge gt 1 GPIOC sisena PRD Adras yy us Control gt
81. Operating Modes The ITCN module design contains two major modes of operation Functional Mode The ITCN is in this mode by default Wait and Stop Modes During Wait and Stop modes the system clocks and the 56800E core are turned off The ITCN will signal a pending IRQ to the System Integration Module SIM to restart the clocks and service the IRQ An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode Also the IRQA and IRQB signals automatically become low level sensitive in these modes even if the control register bits are set to make them falling edge sensitive This is because there is no clock available to detect the falling edge A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode The FlexCAN module can wake the device from Stop mode and a reset will do just that or IRQA and IRQB can wake it up 56F8366 Technical Data Rev 7 Freescale Semiconductor 85 Preliminary 5 6 Register Descriptions A register address is the sum of a base address and an address offset The base address is defined at the system level and the address offset is defined at the module level The ITCN peripheral has 24 registers Table 5 3 ITCN Register Summary ITCN_BASE 00 F1A0 e Base Address Register Name Section Location IPRO 0 Interrupt Priority Register 0 5 6 1 IPR1 1 Interrupt
82. Priority Register 1 5 6 2 IPR2 2 Interrupt Priority Register 2 5 6 3 IPR3 3 Interrupt Priority Register 3 5 6 4 IPR4 4 Interrupt Priority Register 4 5 6 5 IPR5 5 Interrupt Priority Register 5 5 6 6 IPR6 6 Interrupt Priority Register 6 5 6 7 IPR7 7 Interrupt Priority Register 7 5 6 8 IPR8 8 Interrupt Priority Register 8 5 6 9 IPR9 9 Interrupt Priority Register 9 5 6 10 VBA A Vector Base Address Register 5 6 11 FIMO B Fast Interrupt 0 Match Register 5 6 12 FIVALO C Fast Interrupt O Vector Address Low Register 5 6 13 FIVAHO D Fast Interrupt 0 Vector Address High Register 5 6 14 FIM1 E Fast Interrupt 1 Match Register 5 6 15 FIVAL1 F Fast Interrupt 1 Vector Address Low Register 5 6 16 FIVAH1 10 Fast Interrupt 1 Vector Address High Register 5 6 17 IRQPO 11 IRQ Pending Register 0 5 6 18 IRQP1 12 IRQ Pending Register 1 5 6 19 IRQP2 13 IRQ Pending Register 2 5 6 20 IRQP3 14 IRQ Pending Register 3 5 6 21 IRQP4 15 IRQ Pending Register 4 5 6 22 IRQP5 16 IRQ Pending Register 5 5 6 23 ICTL 1D Interrupt Control Register 5 6 30 IPR10 1F Interrupt Priority Register 10 5 6 32 Note The IPR10 register is NOT available in the 56F8166 device 56F8366 Technical Data Rev 7 86 Freescale Semiconductor Preliminary Register Descriptions
83. Q is priority level 1 e 11 IRQ is priority level 2 5 6 6 4 SCI 1 Receiver Error Interrupt Priority Level SCI1_RERR IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 5 Reserved Bits 7 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 6 6 SCI 1 Transmitter Idle Interrupt Priority Level SCI1_TIDL IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 96 Freescale Semiconductor Preliminary Register Descriptions 5 6 6 7 SCI 1 Transmitter Empty Interrupt Priority Level SCI1_XMIT IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 8 SPI 0 Transmitter Empty Interrupt Priority Level SPIO_XMIT IPL Bits 1 0 This field is used to set the interrupt p
84. R bit indicates an external system reset has occurred This bit will be cleared by a Power On Reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it Basically when the EXTR bit is 1 the previous system reset was caused by the external RESET pin being asserted low 6 5 2 5 Power On Reset POR Bit 2 When 1 the POR bit indicates a Power On Reset occurred some time in the past This bit can be cleared only by software or by another type of reset Writing a 0 to this bit will set the bit while writing a 1 to the bit position will clear the bit In summary if the bit is 1 the previous system reset was due to a Power On Reset 6 5 2 6 Reserved Bits 1 0 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 3 SIM Software Control Registers SIM_SCRO SIM_SCR1 SIM_SCR2 and SIM_SCR3 Only SIM_SCRO is shown below SIM_SCR1 SIM_SCR2 and SIM_SCR3 are identical in functionality Base 2 15 14 13 12 11 10 9 8 If 6 5 4 3 2 1 0 Read FIELD Write POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 5 SIM Software Control Register 0 SIM_SCRO 56F8366 Technical Data Rev 7 120 Freescale Semiconductor Preliminary Register Descriptions 6 5 3 1 Software Control Data 1 FIELD Bits 15 0 This register is reset
85. Register PWMB_PWMCM 5 Counter Modulo Register PWMB_PWMVALO 6 Value Register 0 PWMB_PWMVAL1 7 Value Register 1 PWMB_PWMVAL2 8 Value Register 2 PWMB_PWMVAL3 9 Value Register 3 PWMB_PWMVAL4 A Value Register 4 PWMB_PWMVAL5 B Value Register 5 PWMB_PMDEADTM C Dead Time Register PWMB_PMDISMAP1 D Disable Mapping Register 1 PWMB_PMDISMAP2 E Disable Mapping Register 2 PWMB_PMCFG F Configure Register PWMB_PMCCR 10 Channel Control Register PWMB_PMPORT 11 Port Register PWMB_PMICCR 12 PWM Internal Correction Control Register Table 4 17 Quadrature Decoder 0 Registers Address Map DECO_BASE 00 F180 Register Acronym Address Offset Register Description DECO_DECCR 0 Decoder Control Register DECO_FIR 1 Filter Interval Register DECO_WTR 2 Watchdog Time out Register DECO_POSD 3 Position Difference Counter Register DECO_POSDH 4 Position Difference Counter Hold Register DECO_REV 5 Revolution Counter Register DECO_REVH 6 Revolution Hold Register 56F8366 Technical Data Rev 7 60 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 17 Quadrature Decoder 0 Registers Address Map Continued DECO_BASE 00 F180 Register Acronym Address Offset Register Description DECO_UPOS 7 Upper Position Counter Register DECO_LPOS 8 Lower Position Counter Register DECO_UPOSH 9 Upper Position Hold Register DECO_LPOSH A Lower
86. Sampling capacitor at the sample and hold circuit Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time 1pf PONS Figure 10 24 Equivalent Circuit for A D Loading 10 18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application Power consumption is given by the following equation Total power A internal static component B internal state dependent component C internal dynamic component D external dynamic component E external static A the internal static component is comprised of the DC bias currents for the oscillator leakage current PLL and voltage references These sources operate independently of processor state or operating frequency B the internal state dependent component reflects the supply current required by certain on chip resources only when those resources are in use These include RAM Flash memory and the ADCs C the internal dynamic component is classic C V7 F CMOS power dissipation corresponding to the 56800E core and standard cell logic 56F8366 Technical Data Rev 7 Freescale Semiconductor 169 Preliminary D the external dynamic component reflects power dissipated on chip as a result of capacitive loading on the external pins of the chip This is also commonly described as C V7 F although simulations on two of the IO cell types used on the devic
87. TA 63 Message Buffer 4 Data Register FC2MB4_DATA 64 Message Buffer 4 Data Register FC2MB4_DATA 65 Message Buffer 4 Data Register FC2MB4_DATA 66 Message Buffer 4 Data Register Reserved FC2MB5_CONTROL 68 Message Buffer 5 Control Status Register FC2MB5_ID_HIGH 69 Message Buffer 5 ID High Register FC2MB5_ID_LOW 6A Message Buffer 5 ID Low Register FC2MB5_DATA 6B Message Buffer 5 Data Register FC2MB5_DATA 6C Message Buffer 5 Data Register FC2MB5_DATA 6D Message Buffer 5 Data Register FC2MB5_DATA 6E Message Buffer 5 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 79 Table 4 39 FlexCAN2 Registers Address Map Continued FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description Reserved FC2MB6_CONTROL 70 Message Buffer 6 Control Status Register FC2MB6_ID_HIGH 71 Message Buffer 6 ID High Register FC2MB6_ID_LOW 72 Message Buffer 6 ID Low Register FC2MB6_DATA 73 Message Buffer 6 Data Register FC2MB6_DATA 74 Message Buffer 6 Data Register FC2MB6_DATA 75 Message Buffer 6 Data Register FC2MB6_DATA 76 Message Buffer 6 Data Register Reserved FC2MB7_CONTROL 78 Message Buffer 7 Control Status Register FC2MB7_ID_HIGH 79 Message Buffer 7 ID High Register FC2MB7_ID_LOW 7A Message Buffer 7 ID Low Register FC2MB7_DATA 7B Message Buffer 7 Data Regist
88. TMRA 3 pins Dedicated GPIO GPIO D 13 9 2 pins EMI CSn EMI Chip Selects 4 pins EMI CSn Not available in this package N A 2 pins SCI1 Sci 2 pins EMI CSn EMI Chip Selects 3 pins PWMB current sense PWMB current sense 56F8366 Technical Data Rev 7 138 Freescale Semiconductor Preliminary Table 8 2 56F8166 GPIO Ports Configuration Continued Configuration Available ee nibs Pins in Peripheral Function Reset Function 56F8166 E 14 11 2 pins SCIO SCIO 2 pins EMI Address pins EMI Address 4 pins SPIO SPIO 1 pin TMRC TMRC 1 pin TMRC Not available in this package N A 2 pins Dedicated GPIO GPIO 2 pins TMRD Not available in this package N A F 16 16 16 pins EMI Data EMI Data Table 8 3 GPIO External Signals Map Pins in shaded rows are not available in 56F8366 56F8166 Pins in italics are NOT available in the 56F8166 device a Reset 3 A GPIO Port GPIO Bit Functional Signal Package Pln Function 0 Peripheral A8 19 1 Peripheral A9 20 2 Peripheral A10 21 3 Peripheral A11 22 4 Peripheral A12 23 5 Peripheral A13 24 6 Peripheral A14 25 GPIOA 7 Peripheral A15 26 8 Peripheral AO 138 9 Peripheral A1 10 10 Peripheral A2 11 11 Peripheral A3 12 12 Peripheral A4 13 13 Peripheral A5 14 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 139 Table 8 3 GPIO Ext
89. This module incorporates three complementary individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality Complementary operation permits programmable dead time insertion distortion correction via current sensing by software and separate top and bottom output polarity control The up counter value is programmable to support a continuously variable PWM frequency Edge aligned and center aligned synchronous pulse width control 0 to 100 modulation is supported The device is capable of controlling most motor types ACIM AC Induction Motors both BDC and BLDC Brush and Brushless DC motors SRM and VRM Switched and Variable Reluctance Motors and stepper motors The PWM incorporates fault protection and cycle by cycle current limiting with sufficient output drive capability to directly drive standard optoisolators A smoke inhibit write once protection feature for key parameters is also included A patented PWM waveform distortion correction circuit is also provided Each PWM is double buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16 The PWM module provides reference outputs to synchronize the Analog to Digital Converters through two channels of Quad Timer C The 56F8166 incorporates a Quadrature Decoder capable of capturing all four transitions on the two phase inputs permitting generation of a number propor
90. Wait modes it is automatically level sensitive e 0 IRQB interrupt is a low level sensitive default 1 IRQB interrupt is falling edge sensitive 5 6 30 9 IRQA Edge Pin IRQA Edg Bit 0 This bit controls whether the external IRQA interrupt is edge or level sensitive During Stop and Wait modes it is automatically level ensitive e 0 IRQA interrupt is a low level sensitive default 1 RQA interrupt is falling edge sensitive 5 6 31 Reserved Base 1E 5 6 32 Interrupt Priority Register 10 IPR10 Base 1F 15 14 13 12 11 10 9 8 7 6 5 4 3 a 1 0 0 Read 0 o popoJ poJo FLECAN2_ FLECAN2_ FLECAN2_ FLECAN2_ TG MSGBUF IPL WKUP IPL ERR IPL BOFF IPL RESET 0 0 0 0 0 0 0 0 Note This register is NOT available in the 56F8166 device 5 6 32 1 Reserved Bits 15 8 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 56F8366 Technical Data Rev 7 112 Freescale Semiconductor Preliminary Register Descriptions 5 6 32 2 FlexCAN2 Message Buffer Interrupt Priority Level FlexCAN2_MSGBUF IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 32 3 FlexCAN2 Wake Up Interrupt Priority Level
91. XDO 5 2 Peripheral A6 17 3 Peripheral A7 18 4 Peripheral SCLKO 130 5 Peripheral MOSIO 132 6 Peripheral MISOO 131 GPIOE 7 Peripheral SS0 129 8 Peripheral TCO 118 9 N A 10 Peripheral TDO 116 11 Peripheral TD1 117 12 N A 13 N A 56F8366 Technical Data Rev 7 Freescale Semiconductor 141 Preliminary Table 8 3 GPIO External Signals Map Continued Pins in shaded rows are not available in 56F8366 56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIO Bit nta Functional Signal Package Pin 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 133 5 Peripheral D12 134 6 Peripheral D13 135 7 Peripheral D14 136 GPIOF 8 Peripheral D15 137 9 Peripheral DO 59 10 Peripheral D1 60 11 Peripheral D2 72 12 Peripheral D3 75 13 Peripheral D4 76 14 Peripheral D5 77 15 Peripheral D6 78 1 See Part 6 5 8 to determine how to select peripherals from this set DEC1 is the selected peripheral at reset Part 9 Joint Test Action Group JTAG 9 1 JTAG Information Please contact your Freescale marketing representative or authorized distributor for device package specific BSDL information 56F8366 Technical Data Rev 7 142 Freescale Semiconductor Preliminary General Characteristics Part 10 Specifications 10 1 General Characteristics The 56F8366 56F8166 are fabricated in high d
92. XTAL ae E Vppa_osc_PLL OCR DIS Vpp_lo D6 D10 D5 GPIOBO DA PWMBO 37 73 D3 PWMB1 C NC PWMB2 ri os NG Y ov tO HK MIAINIMOT OM NAIIMOo Nor MOH ROO 000 OUONA Beha alglelelas 28 73 Aaa Sana 2 329 0228220 a Cer ar a Ll gt gt pr a gt see aon gt 5355 gt gt aoe ojo ZII x UL i LL Ww Figure 11 2 Top View 56F8166 144 Pin LQFP Package 56F8366 Technical Data Rev 7 174 Freescale Semiconductor Preliminary 56F8166 Package and Pin Out Information Table 11 2 56F8166 144 Pin LQFP Package Identification by Pin Number Pin No eae Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 VDD lo 37 Vss 73 NC 109 ANB5 2 Vpp2 38 Vpp_10 74 NC 110 ANB6 3 CLKO 39 PWMB3 75 D3 111 ANB7 4 TXDO 40 PWMB4 76 D4 112 EXTBOOT 5 RXDO 41 PWMB5 77 D5 113 GPIOC8 6 SCLK1 42 TXD1 78 D6 114 GPIOC9 7 MOSI1 43 RXD1 79 OCR_DIS 115 GPIOC10 8 MISO1 44 WR 80 VDDA_OSC_PLL 116 GPIOE10 9 Sst 45 RD 81 XTAL 117 GPIOE11 10 A1 46 PS 82 EXTAL 118 TCO 11 A2 47 DS 83 Vcap3 119 VDD 1o 12 A3 48 GPIODO 84 Vop io 120 TRST 13 A4 49 GPIOD1 85 RSTO 121 TCK 14 A5 50 ISBO 86 RESET 122 TMS 15 Voap4 51 Voapt 87 CLKMODE 123 TDI 16 Vop_ lo 52 ISB1 88 ANAO 124 TDO 17 A6 53 ISB2 89 ANA1 125 Vpp1 18 A7 54 IRQA 90 ANA2 126 NC 19 A8 55 IRQB 91 ANA3 127 NC 20 A9 56 FAULTBO 92 ANA4 128 Vcap2 21 A10 57 FAULTB1 93 ANA5 129 sso 22 A11 58 FAULTB2 94 ANAG 130 SCLKO 23
93. XTBOOT EMI_MODE and the Flash security setting See Table 4 4 for further information on when this pin is configured as an address pin at reset In all cases this state may be changed by writing to GPIOB_PER To deactivate the internal pull up resistor set bit O in the GPIOB_PUR register DO 59 Input In reset Data Bus DO D6 specify part of the data for external program or Output output is data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR DO D6 are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOF9 Input Port F GPIO These seven GPIO pins can be individually Output programmed as input or output pins D1 60 GPIOF10 At reset these pins default to the EMI Data Bus function D2 72 To deactivate the internal pull up resistor set the appropriate GPIOF11 GPIO bit in the GPIOF_PUR register D3 75 A GPIOF12 Example GPIOF9 set bit 9 in the GPIOF_PUR register D4 76 GPIOF13 D5 77 GPIOF14 D6 78 GPIOF15 56F8366 Technical Data Rev 7 22 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset D7 28 Input In
94. age Buffer 13 Data Register FC2MB13_ DATA AD Message Buffer 13 Data Register FC2MB13_ DATA AE Message Buffer 13 Data Register Reserved FC2MB14_CONTROL BO Message Buffer 14 Control Status Register FC2MB14_ID_HIGH B1 Message Buffer 14 ID High Register FC2MB14_ID_LOW B2 Message Buffer 14 ID Low Register FC2MB14_DATA B3 Message Buffer 14 Data Register FC2MB14_DATA B4 Message Buffer 14 Data Register FC2MB14_DATA B5 Message Buffer 14 Data Register FC2MB14_DATA B6 Message Buffer 14 Data Register Reserved FC2MB15_ CONTROL B8 Message Buffer 15 Control Status Register FC2MB15_ID_HIGH B9 Message Buffer 15 ID High Register FC2MB15_ID_LOW BA Message Buffer 15 ID Low Register FC2MB15_DATA BB Message Buffer 15 Data Register FC2MB15_DATA BC Message Buffer 15 Data Register FC2MB15_DATA BD Message Buffer 15 Data Register FC2MB15_DATA BE Message Buffer 15 Data Register Reserved 4 8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program The Serial Bootloader application can be used to load a user application into the Program and Data Flash NOT available in the 56F8166 device memories of the device The 56F83xx SCI CAN Bootloader User Manual MC56F83xxBLUM provides detailed information on this firmware An application note Production Flash Programming AN1973 details how the Serial Bootloader program can be used to per
95. age Veommon VrerH VrerLO 2 V Signal to noise ratio SNR 64 6 db Signal to noise plus distortion ratio SINAD 59 1 db Total Harmonic Distortion THD 60 6 db Spurious Free Dynamic Range SFDR 61 1 db Effective Number Of Bits ENOB 9 6 Bits 1 INL measured from Vin 1VREFH to Vin 9VREFH 10 to 90 Input Signal Range LSB Least Significant Bit ADC clock cycles o A O N Assumes each voltage reference pin is bypassed with 0 1uF ceramic capacitors to ground The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC This allows the ADC to operate in noisy industrial environments where inductive flyback is possible o 8 ENOB SINAD 1 76 6 02 Absolute error includes the effects of both gain error and offset error 7 Please see the 56F8300Peripheral User s Manual for additional information on ADC calibration 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 167 ADC absolute error before calibration and after calibration VDCin 0 60V i cfi 0 002289 before calibration cf2 25 591943 aN A An a a ee AAR e after calibration percent reduction of range of error 24 2 mean before cal 38 0 mean after cal 1 2 li ADC absolute error LSBs 100 l 0 10 20 30 40 50 60 70 serial number ADC absolute error before calibration and afte
96. al Harvard architecture e Up to 60 Million Instructions Per Second MIPS at 60MHz core frequency e Single cycle 16 x 16 bit parallel Multiplier Accumulator MAC e Four 36 bit accumulators including extension bits e Arithmetic and logic multi bit shifter e Parallel instruction set with unique DSP addressing modes e Hardware DO and REP loops e Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions e Controller style addressing modes and instructions for compact code e Efficient C compiler and local variable support e Software subroutine and interrupt stack with depth limited only by memory e JTAG EOnCE debug programming interface 1 1 2 Differences Between Devices Table 1 1 outlines the key differences between the 56F8366 and 56F8166 devices Table 1 1 Device Differences Feature 56F8366 56F8166 Guaranteed Speed 60MHz 60 MIPS 40MHz 40 MIPS Program RAM 4KB Not Available Data Flash 8KB Not Available PWM 2x6 1x6 CAN 2 Not Available Quad Timer 4 2 Quadrature Decoder 2x4 1x4 Temperature Sensor 1 Not Available Dedicated GPIO 5 56F8366 Technical Data Rev 7 Freescale Semiconductor 5 Preliminary 1 13 Memory Note Features in italics are NOT available in the 56F8166 device e Harvard architecture permits as many as three simultaneous accesses to program and data memory e Flash security protection feature e On chip memory in
97. aler is set to 1 the EMI quadrature clock is generated using both edges of the EXTAL clock input In this situation only parameter values must be adjusted for the duty cycle at XTAL DCAOE and DCAEO are used to make this duty cycle adjustment where needed DCAOE and DCAEO are calculated as follows DCAOE DCAEO 0 5 MAX XTAL duty cycle if ZSRC selects prescaler clock and the prescaler is set to 1 0 0 all other cases MIN XTAL duty cycle 0 5 if ZSRC selects prescaler clock and the prescaler is set to 1 0 0 all other cases Example of DCAOE and DCAEO calculation Assuming prescaler is set for 1 and prescaler clock is selected by ZSRC if XTAL duty cycle ranges between 45 and 60 high DCAOE 50 60 0 1 DCAEO 45 50 0 05 56F8366 Technical Data Rev 7 154 Freescale Semiconductor Preliminary External Memory Interface Timing The timing of write cycles is different when WWS 0 than when WWS gt 0 Therefore some parameters contain two sets of numbers to account for this difference Use the Wait States Configuration column of Table 10 16 to make the appropriate selection A0 Axx CS DO D15 Note During read modify write instructions and internal instructions the address lines do not change state Figure 10 5 External Memory Interface Timing Note When multiple lines are given for the same wait state configuration calculate each and then select the smal
98. arameters Characteristic Symbol Min Typ Max Unit Input voltages VADIN VREFL VREFH V Resolution Res 12 12 Bits Integral Non Linearity INL 2 4 3 2 LSB Differential Non Linearity DNL 0 7 lt 1 LSB2 Monotonicity GUARANTEED ADC internal clock fapic 0 5 5 MHz Conversion range Rap VREFL VREFH V ADC channel power up time tappu 5 6 16 taic cycles ADC reference circuit power up time tVREF 25 ms Conversion time tapc 6 tait cycles Sample time taps 1 tages cycles Input capacitance Capi 5 pF Input injection current per pin lapi 3 mA Input injection current total lapIt 20 mA VrEFH Current IVREFH 1 2 3 mA ADC A current lADCA 25 mA ADC B current laca 25 mA Quiescent current lapca 0 10 HA Uncalibrated Gain Error ideal 1 EGAIN 004 01 Uncalibrated Offset Voltage VOFFSET 27 40 mV Calibrated Absolute Error AEcaL See Figure 10 23 LSBs 56F8366 Technical Data Rev 7 166 Freescale Semiconductor Preliminary Table 10 24 ADC Parameters Continued Analog to Digital Converter ADC Parameters Characteristic Symbol Min Typ Max Unit Calibration Factor 17 CF1 0 002289 Calibration Factor 2 CF2 25 6 Crosstalk between channels 60 dB Common Mode Volt
99. ata Rev 7 134 Freescale Semiconductor Preliminary Flash Access Blocking Mechanisms 7 2 2 Disabling EOnCE Access On chip Flash can be read by issuing commands across the EOnCE port which is the debug interface for the 56800E core The TRST TCLK TMS TDO and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped When the device boots the chip level JTAG TAP Test Access Port is active and provides the chip s boundary scan capability and access to the ID register Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled The 56800E core has an input which disables reading of internal memory via the JTAG EOnCE The FM sets this input at reset to a value determined by the contents of the FM security bytes 7 2 3 Flash Lockout Recovery If a user inadvertently enables Flash security on the device a built in lockout recovery mechanism can be used to reenable access to the device This mechanism completely reases all on chip Flash thus disabling Flash security Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration cfg files Add or uncomment the following configuration command unlock_flash_on_connect 1 For more information please see Code Warrior MC56F83xx DSP5685x Family Targeting Manual The LOCKOUT_ RECOVERY instruction has an associated 7 bit Data Register DR that is used to con
100. ation Registers Address Map EMI_BASE 00 F020 Register Acronym Address Offset Register Description Reset Value CSBAR 0 0 Chip Select Base Address Register 0 0x0004 64K when EXTBOOT 0 or EMI_MODE 0 0x0008 1M when EMI_Mode 1 Selects entire program space for CS0 Note that A17 A19 are not available in this package CSBAR 1 1 Chip Select Base Address Register 1 0x0004 64K when EMI_MODE 0 0x0008 1M when EMI_MODE 1 Selects AO A19 addressable data space for CS1 Note that A17 A19 are not available in this package CSBAR 2 2 Chip Select Base Address Register 2 CSBAR 3 3 Chip Select Base Address Register 3 CSBAR 4 4 Chip Select Base Address Register 4 CSBAR 5 5 Chip Select Base Address Register 5 CSBAR 6 6 Chip Select Base Address Register 6 CSBAR 7 7 Chip Select Base Address Register 7 CSOR 0 8 Chip Select Option Register 0 Ox5FCB programmed for chip select for program space word wide read and write 11 waits 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 51 Table 4 10 External Memory Integration Registers Address Map Continued EMI_BASE 00 F020 Register Acronym Address Offset Register Description Reset Value CSOR 1 9 Chip Select Option Register 1 Ox5FAB programmed for chip select for data space word wide read and write 11 waits CSOR 2 A Chi
101. bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 6 Clock Generation Overview The SIM uses an internal master clock from the OCCS CLKGEN module to produce the peripheral and system core and memory clocks The maximum master clock frequency is 120MHz Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz The SIM provides power modes Stop Wait and clock enables SIM_PCE register CLK_ DIS ONCE_EBL to control which clocks are in operation The OCCS power modes and clock enables provide a flexible means to manage power consumption Power utilization can be minimized in several ways In the OCCS crystal oscillator and PLL may be shut down when not in use When the PLL is in use its prescaler and postscaler can be used to limit PLL and master clock frequency Power modes permit system and or peripheral clocks to be disabled when unused Clock enables provide the means to disable individual clocks Some peripherals provide further controls to disable unused subfunctions Refer to the Part 3 On Chip Clock Synthesis OCCS and the 56F8300 Peripheral User Manual for further details 6 7 Power Down Modes Overview The 56F8366 56F8166 devices operate in one of three power down modes as shown in Table 6 4 Table 6 4 Clock Operation in Power Down Modes Mode Core Clocks Peripheral
102. bit selects the alternate function for GPIOC1 e 0 PHASEB1 TBI default e 1 MOSTI1 6 5 8 7 GPIOCO C0 Bit 0 This bit selects the alternate function for GPIOCO 0 PHASEAI TBO default 1 SCLKI 56F8366 Technical Data Rev 7 Freescale Semiconductor 127 Preliminary 6 5 9 Peripheral Clock Enable Register SIM_PCE The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature The clocks can be individually controlled for each peripheral on the chip Base C 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 Read w EMI ADCB ADCA CAN DEC1 DECO TMRD TMRC TMRB TMRA SCI 1 SCIO SPI1 SPIO PWMB PWMA rite RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 13 Peripheral Clock Enable Register SIM_PCE 6 5 9 1 External Memory Interface Enable EMI Bit 15 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 2 Analog to Digital Converter B Enable ADCB Bit 14 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 3 Analog to Digital Converter A Enable ADCA Bit 13 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provid
103. bled default e 01 IRQis priority level 1 e 10 IRQ is priority level 2 11 IRQ is priority level 3 5 6 3 Interrupt Priority Register 2 IPR2 Base 2 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read FMCBE IPL FMCCIPL FMERRIPL LOCK IPL LVI IPL IRQB IPL IRQA IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 5 Interrupt Priority Register 2 IPR2 56F8366 Technical Data Rev 7 Freescale Semiconductor 89 Preliminary 5 6 3 1 Flash Memory Command Data Address Buffers Empty Interrupt Priority Level FMCBE IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 2 Flash Memory Command Complete Priority Level FMCC IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 3 Flash Memory Error Interrupt Priority Level FMERR IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 It is disabled by default e 00 IRQ disabled defaul
104. br_m Also used to access memory mapped 1 O Secondary Data Memory Interface xdb2_m 15 0 Secondary data bus used for secondary data address bus xab2 in the dual memory reads 1 Byte accesses can only occur in the bottom half of the memory address space The MSB of the address will be forced to 0 xab2 23 0 Secondary data address bus used for the second of two simultaneous accesses Capable of addressing only words Data is returned on xdb2_m Peripheral Interface Bus IPBus 15 0 Peripheral bus accesses all on chip peripherals registers This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor Write data is obtained from cdbw Read data is provided to cdbr_m 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 13 1 5 Product Documentation The documents in Table 1 3 are required for a complete description and proper design with the 56F8366 56F8166 devices Documentation is available from local Freescale distributors Freescale semiconductor sales offices Freescale Literature Distribution Centers or online at http www freescale com Table 1 3 Chip Documentation Topic Description Order Number DSP56800E Detailed description of the 56800E family architecture DSP56800ERM Reference Manual and 16 bit controller core processor and the instruction set 56F8300 Peripheral User Manual Detail
105. ce and an input to a slave device The master device disabled places data on the MOSI line a half cycle before the clock edge the pull up is slave device uses to latch the data enabled GPIOE5 Input Port E GPIO This GPIO pin can be individually programmed as Output an input or output pin After reset the default state is MOSIO To deactivate the internal pull up resistor clear bit 5 in the GPIOE_PUR register MISOO 131 Input Input SPI 0 Master In Slave Out This serial data pin is an input to a Output pull up master device and an output from a slave device The MISO line of enabled a slave device is placed in the high impedance state if the slave device is not selected The slave device places data on the MISO line a half cycle before the clock edge the master device uses to latch the data GPIOE6 Input Port E GPIO This GPIO pin can be individually programmed as Output an input or output pin After reset the default state is MISOO To deactivate the internal pull up resistor clear bit 6 in the GPIOE_PUR register SS0 129 Input Input SPI 0 Slave Select SSO is used in slave mode to indicate to the pull up SPI module that the current transfer is to be received enabled GPIOE7 Input Port E GPIO This GPIO pin can be individually programmed as Output input or output pin After reset the default state is SSO To deactivate the internal pull up resistor clear bit 7 in the GPIOE_PUR register 56F8366
106. cluding a low cost high volume Flash solution 512KB of Program Flash 4KB of Program RAM 32KB of Data Flash 32KB of Data RAM 32KB of Boot Flash e Off chip memory expansion capabilities programmable for 0 30 wait states Access up to 1MB of program memory or 1MB of data memory Chip select logic for glueless interface to ROM and SRAM EEPROM emulation capability 1 1 4 Peripheral Circuits for 56F8366 Note Features in italics are NOT available in the 56F8166 device e Pulse Width Modulator Inthe 56F8366 two Pulse Width Modulator modules each with six PWM outputs three Current Sense inputs and three Fault inputs fault tolerant design with dead time insertion supports both center aligned and edge aligned modes Inthe 56F8166 one Pulse Width Modulator module with six PWM outputs three Current Sense inputs and three Fault inputs fault tolerant design with dead time insertion supports both center aligned and edge aligned modes e Four 12 bit Analog to Digital Converters ADCs which support four simultaneous conversions with quad 4 pin multiplexed inputs ADC and PWM modules can be synchronized through Timer C channels 2 and 3 e Quadrature Decoder In the 56F8366 two four input Quadrature Decoders or two additional Quad Timers Inthe 56F8166 one four input Quadrature Decoder which works in conjunction with Quad Timer A e Temperature Sensor diode can be connected on the board to any
107. ctor Preliminary External Clock Note The midpoint is Vip V y V L 2 Figure 10 4 External Clock Timing 10 6 Phase Locked Loop Timing Table 10 14 PLL Timing Phase Locked Loop Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL fosc 4 8 8 4 MHz PLL output frequency fout fop 160 260 MHz PLL stabilization time 40 to 125 C tolls 1 10 ms 1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly The PLL is optimized for 8MHz input crystal 2 ZCLK may not exceed 60MHz For additional information on ZCLK and foy7 2 please refer to the OCCS chapter in the 56F8300 Peripheral User Manual 3 This is the minimum time required after the PLL set up is changed to ensure reliable operation 10 7 Crystal Oscillator Timing Table 10 15 Crystal Oscillator Parameters 56F8366 Technical Data Rev 7 Characteristic Symbol Min Typ Max Unit Crystal Start up time Tes 4 5 10 ms Resonator Start up time Trs 0 1 0 18 1 ms Crystal ESR Resr 120 ohms Crystal Peak to Peak Jitter To 70 250 ps Crystal Min Max Period Variation Try 0 12 1 5 ns Resonator Peak to Peak Jitter Try 300 ps Resonator Min Max Period Variation Trp 300 ps Bias Current high drive mode IBIASH 250 290 uA Freescale Semico
108. d unnecessary system clock operation Run mode supports full part operation Controls to enable disable the 56800E core WAIT and STOP instructions Calculates base delay for reset extension based upon POR or RESET operations Reset delay will be either 3 x 32 clocks phased release of reset for reset except for POR which is 2 clock cycles Controls reset sequencing after reset Software initiated reset Four 16 bit registers reset only by a Power On Reset usable for general purpose software control System Control Register Registers for software access to the JTAG ID of the chip Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip it must understand the various chip operating modes and take appropriate action These are Reset Mode which has two submodes POR and RESET operation The 56800E core and all peripherals are reset This occurs when the internal POR is asserted or the RESET pin is asserted COP reset and software reset operation The 56800E core and all peripherals are reset The MA bit within the OMR is not changed This allows the software to determine the boot mode internal or external boot to be used on the next reset Run Mode This is the primary mode of operation for this device In this mode the 56800E controls chip operation Debug Mode The 56800E is controlled via JTAG EOnCE when in debug mode All peripherals except the COP and PWMs continue to run C
109. deactivate the internal pull up resistor clear bit 1 in the GPIOE_PUR register 56F8366 Technical Data Rev 7 26 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset TXD1 42 Output In reset Transmit Data SCI1 transmit data output output is GPIOD6 Input disabled Port D GPIO This GPIO pin can be individually programmed as Output pull up is an input or output pin enabled After reset the default state is SCI output To deactivate the internal pull up resistor clear bit 6 in the GPIOD_PUR register RXD1 43 Input Input Receive Data SCI1 receive data input pull up GPIOD7 Input enabled Port D GPIO This GPIO pin can be individually programmed as Output an input or output pin After reset the default state is SCI input To deactivate the internal pull up resistor clear bit 7 in the GPIOD_PUR register TCK 121 Schmitt Input Test Clock Input This input pin provides a gated clock to Input pulled low synchronize the test logic and shift serial data to the JTAG EOnCE internally port The pin is connected internally to a pull down resistor TMS 122 Schmitt Input Test Mode Select Input This input pin is used to sequence the Input pulled high JTAG TAP controller s state machine It is sampled on the rising internally edge of TCK and has an on chi
110. dently of RESET Designs that do not require debugging functionality such as consumer products should tie these pins together e Because the Flash memory is programmed through the JTAG EOnCE port the designer should provide an interface to this port to allow in circuit Flash programming 12 3 Power Distribution and I O Ring Implementation Figure 12 1 illustrates the general power control incorporated in the 56F8366 56F8166 This chip contains two internal power regulators One of them is powered from the Vppa osc pLL pin and cannot be turned off This regulator controls power to the internal clock generation circuitry The other regulator is powered from the Vpp jo pins and provides power to all of the internal digital logic of the core all peripherals and the internal memories This regulator can be turned off if an external Vpp core voltage is externally applied to the Vcap pins p In summary the entire chip can be supplied from a single 3 3 volt supply if the large core regulator is enabled If the regulator is not enabled a dual supply 3 3V 2 5V configuration can also be used Notes e Flash RAM and internal logic are powered from the core regulator output Vppl and Vpp2 are not connected in the customer system e All circuitry analog and digital shares a common Vgg bus 56F8366 Technical Data Rev 7 180 Freescale Semiconductor Preliminary Power Distribution and I O Ring Implementation
111. dress lines 1 1 Mode 1 External Boot Flash Memory is not secured EMI configuration is determined by the state of the EMI_MODE pin 1 This bit is only configured at reset If the Flash secured state changes this will not be reflected in MB until the next reset 2 Changing MB in software will not affect Flash memory security 56F8366 Technical Data Rev 7 Freescale Semiconductor 41 Preliminary Table 4 3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P space memory map configuration 1 effect Use external P space memory map configuration If MB 0 at reset changing this bit has no The device s external memory interface EMI can operate much like the 56F80x family s EMI or it can be operated in a mode similar to that used on other products in the 56800E family Initially CSO and CS1 are configured as PS and DS in a mode compatible with earlier 56800 devices Eighteen address lines are required to shadow the first 192K of internal program space when booting externally for development purposes Therefore the entire complement of on chip memory cannot be accessed using a 16 bit 56800 compatible address bus To address this situation the EMI MODE pin can be used to configure four GPIO pins as Address 19 16 upon reset only one of these pins A16 is usable in the 56F8366 56F8166 The EMI MODE pin also affects the reset
112. ductor Preliminary 177 Please see www freescale com for the most current case outline Part 12 Design Considerations 12 1 Thermal Design Considerations An estimation of the chip junction temperature Ty can be obtained from the equation Ty Ta Roya x Po where T Ambient temperature for the package C Reja Junction to ambient thermal resistance C W Pp Power dissipation in the package W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance Unfortunately there are two values in common usage the value determined on a single layer board and the value obtained on a board with two planes For packages such as the PBGA these values can be different by a factor of two Which value is closer to the application depends on the power dissipated by other components on the board The value obtained on a single layer board is appropriate for the tightly packed printed circuit board The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated When a heat sink is used the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Roya Rosc Reca where Reja Package junction to ambient thermal resistance C W Rejc Package junction to case thermal resistance C W Reca
113. e 56F8366 Technical Data Rev 7 The OMR is not a Memory Map register it is directly accessible in code through the acronym OMR 116 Freescale Semiconductor Preliminary Register Descriptions 6 5 Register Descriptions Table 6 1 SIM Registers SIM_BASE 00 F350 Address Offset Address Acronym Register Name Section Location Base 0 SIM_CONTROL Control Register 6 5 1 Base 1 SIM_RSTSTS Reset Status Register 6 5 2 Base 2 SIM_SCRO Software Control Register 0 6 5 3 Base 3 SIM_SCR1 Software Control Register 1 6 5 3 Base 4 SIM_SCR2 Software Control Register 2 6 5 3 Base 5 SIM_SCR3 Software Control Register 3 6 5 3 Base 6 SIM_MSH_ID Most Significant Half of JTAG ID 6 5 4 Base 7 SIM_LSH_ID Least Significant Half of JTAG ID 6 5 5 Base 8 SIM_PUDR Pull up Disable Register 6 5 6 Base A SIM_CLKOSR CLKO Select Register 6 5 7 Base B SIM_GPS GPIO Peripheral Select Register 6 5 7 Base C SIM_PCE Peripheral Clock Enable Register 6 5 8 Base D SIM_ISALH 1 0 Short Address Location High Register 6 5 9 Base E SIM_ISALL 1 0 Short Address Location Low Register 6 5 10 Base F SIM_PCE2 Peripheral Clock Enable Register 2 6 5 11 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 117 Add Register Offset Name 6 5 4 3 2 1 0
114. e If the operating temperature range is limited to below 85 C 105 C junction then R 10 Meg Q CL1 CL2 Figure 3 2 Connecting to a Crystal Oscillator Note The OCCS_COHL bit must be set to 1 when a crystal oscillator is used The reset condition on the OCCS_COHL bit is 0 Please see the COHL bit in the Oscillator Control OSCTL register discussed in the 56F8300 Peripheral User Manual 3 2 2 Ceramic Resonator Default It is also possible to drive the internal oscillator with a ceramic resonator assuming the overall system design can tolerate the reduced signal integrity A typical ceramic resonator circuit is shown in Figure 3 3 Refer to the supplier s recommendations when selecting a ceramic resonator and associated components The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins Resonator Frequency 4 8MHz optimized for 8MHz 2 Terminal 3 Terminal EXTAL XTAL EXTAL XTAL Sample External Ceramic Resonator Parameters R 750 KQ Rz Rz CL1 CL2 CLKMODE 0 C1 HLH C2 Figure 3 3 Connecting a Ceramic Resonator Note The OCCS_COHL bit must be set to 0 when a ceramic resonator is used The reset condition on the OCCS_COHL bit is 0 Please see the COHL bit in the Oscillator Control OSCTL register discussed in the 56F8300 Peripheral User Manual 56F8366 Technical Data Rev 7 Freescale Semiconductor 39 Preli
115. e When this pin is tied low the customer boot software should disable the internal pull up resistor by setting the XBOOT bit of the SIM_PUDR see Part 6 5 6 EMI_MODE 143 Schmitt Input External Memory Mode The EMI_MODE input is internally tied Input pull up low to Vss This device will boot from internal Flash memory enabled under normal operation This function is also affected by EXTBOOT and the Flash security mode For details see Table 4 4 If a 20 bit address bus is not desired then this pin is tied to ground Note When this pin is tied low the customer boot software should disable the internal pull up resistor by setting the EMI_MODE bit of the SIM_PUDR see Part 6 5 6 56F8366 Technical Data Rev 7 Freescale Semiconductor 37 Preliminary Part 3 On Chip Clock Synthesis OCCS 3 1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS The material contained here identifies the specific features of the OCCS design Figure 3 1 shows the specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual CLKMODE A XTAL LE al Crystal ZSRC osc ij Prescaler CLK SYS CLK2 EXTAL Source to SIM PLLCID PLLDB PLLCOD LL Prescaler a PLL Four Fouti2 Postscaler uw R Ea 1 2 4 8
116. e The minimum bypass requirement is to place six 0 01 0 1 uF capacitors positioned as close as possible to the package supply pins The recommended bypass configuration is to place one bypass capacitor on each of the Vpp Vss pairs including Vppa Vssa Ceramic and tantalum capacitors tend to provide better performance tolerances 56F8366 Technical Data Rev 7 Freescale Semiconductor 179 Preliminary e Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vpp and Vss GND pins are less than 0 5 inch per capacitor lead e Use at least a four layer Printed Circuit Board PCB with two inner layers for Vpp and Vgg e Bypass the Vpp and Vgg layers of the PCB with approximately 100 uF preferably with a high grade capacitor such as a tantalum capacitor e Because the device s output signals have fast rise and fall times PCB trace lengths should be minimal e Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance This is especially critical in systems with higher capacitive loads that could create higher transient currents in the Vpp and Vg circuits e Take special care to minimize noise levels on the Vrep Vppa and Vsga pins Designs that utilize the TRST pin for JTAG port or EOnCE module functionality such as development or debugging systems should allow a means to assert TRST whenever RESET is asserted as well as a means to assert TRST indepen
117. e on the 56F8166 device Table 4 9 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number External Memory Interface EMI X 00 F020 4 10 Timer A TMRA X 00 F040 4 11 Timer B TMRB X 00 F080 4 12 Timer C TMRC X 00 FOCO 4 13 Timer D TMRD X 00 F100 4 14 PWM A PWMA X 00 F140 4 15 PWM B PWMB X 00 F160 4 16 Quadrature Decoder 0 DECO X 00 F180 4 17 Quadrature Decoder 1 DEC1 X 00 F190 4 18 ITCN ITCN X 00 F1A0 4 19 ADCA ADCA X 00 F200 4 20 ADC B ADCB X 00 F240 4 21 Temperature Sensor TSENSOR X 00 F270 4 22 SCI 0 SCIO X 00 F280 4 23 SCI 1 SCl1 X 00 F290 4 24 SPI 0 SPIO X 00 F2A0 4 25 SPI 1 SPI1 X 00 F2B0 4 26 COP COP X 00 F2CO 4 27 PLL OSC CLKGEN X 00 F2D0 4 28 GPIO Port A GPIOA X 00 F2E0 4 29 GPIO Port B GPIOB X 00 F300 4 30 GPIO Port C GPIOC X 00 F310 4 31 GPIO Port D GPIOD X 00 F320 4 32 GPIO Port E GPIOE X 00 F330 4 33 GPIO Port F GPIOF X 00 F340 4 34 56F8366 Technical Data Rev 7 50 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 9 Data Memory Peripheral Base Address Map Summary Continued Peripheral Prefix Base Address Table Number SIM SIM X 00 F350 4 35 Power Supervisor LVI X 00 F360 4 36 FM FM X 00 F400 4 37 FlexCAN FC X 00 F800 4 38 FlexCAN2 FC X 00 FA00 4 39 Table 4 10 External Memory Integr
118. e reveal that the power versus load curve does have a non zero Y intercept Table 10 25 IO Loading Coefficients at 10MHz Intercept Slope PDU08DGZ_ME 1 3 0 11mW pF PDU04DGZ_ME 1 15mW 0 11mW pF Power due to capacitive loading on output pins is first order a function of the capacitive load and frequency at which the outputs change Table 10 25 provides coefficients for calculating power dissipated in the IO cells as a function of capacitive load In these cases TotalPower X Intercept Slope Cload frequency 10MHz where e Summation is performed over all output pins with capacitive loads e TotalPower is expressed in mW e Cload is expressed in pF Because of the low duty cycle on most device pins power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate In this case power from these buses can be significant E the external static component reflects the effects of placing resistive loads on the outputs of the device Sum the total of all V R or IV to arrive at the resistive load contribution to power Assume V 0 5 for the purposes of these rough calculations For instance if there is a total of 8 PWM outputs driving 10mA into LEDs then P 8 5 01 40mW In previous discussions power consumption due to para
119. e voltage 2 The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPTO and FMOPT1 3 See Application Note AN1980 for methods to increase accuracy 4 Assuming a 12 bit range from OV to 3 3V 5 Typical resolution calculated using equation 10 3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10 5 Unless otherwise specified propagation delays are measured from the 50 to the 50 point and rise and fall times are measured between the 10 and 90 points as shown in Figure 10 2 90 Input Signal Midpoint Fall Time Rise Time Note The midpoint is V V y V 2 Figure 10 2 Input Signal Measurement References Figure 10 3 shows the definitions of the following signal states e Active state when a bus or signal is driven and enters a low impedance state e Tri stated when a bus or signal is placed in a high impedance state e Data Valid state when a signal level has reached Vo or Voy e Data Invalid state when a signal level is in transition between Vo and Voy 56F8366 Technical Data Rev 7 Freescale Semiconductor 151 Preliminary Data1 Valid Data2 Valid Data3 Valid Data Data Invalid State Tri stated Data Active Data Active Figure 10 3 Signal States 10 4 Flash Memory Characteristics Table 10 12 Flash Timing Parameters
120. ed description of peripherals of the 56F8300 MC56F8300UM devices 56F8300 SCI CAN Bootloader Detailed description of the SCI CAN Bootloaders MC56F83xxBLUM User Manual 56F8300 family of devices 56F8366 56F8166 Electrical and timing specifications pin descriptions and MC56F8366 Technical Data Sheet package descriptions this document 56F8366 Details any chip issues that might be present MC56F8366E Errata MC56F8166E 1 6 Data Sheet Conventions This data sheet uses the following conventions OVERBAR This is used to indicate a signal that is active when pulled low For example the RESET pin is active when low asserted A high true active high signal is high or a low true active low signal is low deasserted A high true active high signal is low or a low true active low signal is high Examples Signal Symbol Logic State Signal State Voltage PIN True Asserted Vi VoL PIN False Deasserted ViH VoH PIN True Asserted Vin Vou PIN False Deasserted Vi VoL 1 Values for VIL VOL VIH and VOH are defined by individual product specifications 56F8366 Technical Data Rev 7 14 Freescale Semiconductor Preliminary Introduction Part 2 Signal Connection Descriptions 2 1 Introduction The input and output signals of the 56F8366 and 56F8166 are organized into functional groups as detailed in Table 2 1 and as illustrated in Figure 2 1 In Table 2 2 each table row describes the signal or signals present on a pin
121. ed to the peripheral the peripheral is disabled 6 5 9 4 FlexCAN Enable CAN Bit 12 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 5 Decoder 1 Enable DEC1 Bit 11 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 56F8366 Technical Data Rev 7 128 Freescale Semiconductor Preliminary Register Descriptions 6 5 9 6 Decoder 0 Enable DECO Bit 10 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 7 Quad Timer D Enable TMRD Bit 9 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 8 Quad Timer C Enable TMRC Bit 8 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 9 Quad Timer B Enable TMRB Bit 7 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 10 Quad Timer A Enable TMRA Bit 6 Each bit controls clocks to the indicated peripheral e 1 Cl
122. egister TMRD1_HOLD 14 Hold Register TMRD1_CNTR 15 Counter Register TMRD1_CTRL 16 Control Register TMRD1_SCR 17 Status and Control Register TMRD1_CMPLD1 18 Comparator Load Register 1 TMRD1_CMPLD2 19 Comparator Load Register 2 TMRD1_COMSCR 1A Comparator Status and Control Register TMRD2_CMP1 20 Compare Register 1 TMRD2_CMP2 21 Compare Register 2 TMRD2_CAP 22 Capture Register TMRD2_LOAD 23 Load Register TMRD2_HOLD 24 Hold Register TMRD2_CNTR 25 Counter Register TMRD2_CTRL 26 Control Register TMRD2_SCR 27 Status and Control Register TMRD2_CMPLD1 28 Comparator Load Register 1 TMRD2_CMPLD2 29 Comparator Load Register 2 TMRD2_COMSCR 2A Comparator Status and Control Register TMRD3_CMP1 30 Compare Register 1 TMRD3_CMP2 31 Compare Register 2 TMRD3_CAP 32 Capture Register TMRD3_LOAD 33 Load Register TMRD3_HOLD 34 Hold Register TMRD3_CNTR 35 Counter Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 14 Quad Timer D Registers Address Map Continued TMRD_BASE 00 F100 Quad Timer D is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRD3_CTRL 36 Control Register TMRD3_SCR 37 Status and Control Register TMRD3_CMPLD1 38 Comparator Load Register 1 TMRD3_CMPLD2 39 Comparator Load Register 2 TMRD3_COMSCR 3A Com
123. egister Acronym Address Offset Register Description TMRB1_CMPLD2 19 Comparator Load Register 2 TMRB1_COMSCR 1A Comparator Status and Control Register TMRB2_CMP1 20 Compare Register 1 TMRB2_CMP2 21 Compare Register 2 TMRB2_CAP 22 Capture Register TMRB2_LOAD 23 Load Register TMRB2_HOLD 24 Hold Register TMRB2_CNTR 25 Counter Register TMRB2_CTRL 26 Control Register TMRB2_SCR 27 Status and Control Register TMRB2_CMPLD1 28 Comparator Load Register 1 TMRB2_CMPLD2 29 Comparator Load Register 2 TMRB2_COMSCR 2A Comparator Status and Control Register TMRB3_CMP1 30 Compare Register 1 TMRB3_CMP2 31 Compare Register 2 TMRB3_CAP 32 Capture Register TMRB3_LOAD 33 Load Register TMRB3_HOLD 34 Hold Register TMRB3_CNTR 35 Counter Register TMRB3_CTRL 36 Control Register TMRB3_SCR 37 Status and Control Register TMRB3_CMPLD1 38 Comparator Load Register 1 TMRB3_CMPLD2 39 Comparator Load Register 2 TMRB3_COMSCR 3A Comparator Status and Control Register 56F8366 Technical Data Rev 7 Freescale Semiconductor 55 Preliminary Table 4 13 Quad Timer C Registers Address Map TMRC_BASE 00 FOCO Register Acronym Address Offset Register Description TMRCO_CMP1 0 Compare Register 1 TMRCO_CMP2 1 Compare Register 2 TMRCO_CAP 2 Capture Register TMRCO_LOAD 3 Load Register TMRCO_HOLD 4
124. ensity CMOS with 5V tolerant TTL compatible digital inputs The term 5V tolerant refers to the capability of an I O pin built on a 3 3V compatible process technology to withstand a voltage up to 5 5V without damaging the device Many systems have a mixture of devices designed for 3 3V and 5V power supplies In such systems a bus may carry both 3 3V and 5V compatible I O voltage levels a standard 3 3V I O is designed to receive a maximum voltage of 3 3V 10 during normal operation without causing damage This 5V tolerant capability therefore offers the power savings of 3 3V I O levels combined with the ability to receive 5V levels without damage Absolute maximum ratings in Table 10 1 are stress ratings only and functional operation at the maximum is not guaranteed Stress beyond these ratings may affect device reliability or cause permanent damage to the device Note All specifications meet both Automotive and Industrial requirements unless individual specifications are listed Note The 56F 8166 device is guaranteed to 40MHz and specified to meet Industrial requirements only CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage l
125. er FC2MB7_DATA 7C Message Buffer 7 Data Register FC2MB7_DATA 7D Message Buffer 7 Data Register FC2MB7_DATA 7E Message Buffer 7 Data Register Reserved FC2MB8_CONTROL 80 Message Buffer 8 Contro Status Register FC2MB8_ID_HIGH 81 Message Buffer 8 ID High Register FC2MB8_ID_LOW 82 Message Buffer 8 ID Low Register FC2MB8_DATA 83 Message Buffer 8 Data Register FC2MB8_DATA 84 Message Buffer 8 Data Register FC2MB8_DATA 85 Message Buffer 8 Data Register FC2MB8_DATA 86 Message Buffer 8 Data Register Reserved FC2MB9_CONTROL 88 Message Buffer 9 Control Status Register FC2MB9_ID_HIGH 89 Message Buffer 9 ID High Register FC2MB9_ID_LOW 8A Message Buffer 9 ID Low Register FC2MB9_DATA 8B Message Buffer 9 Data Register FC2MB9_DATA 8C Message Buffer 9 Data Register FC2MB9_DATA 8D Message Buffer 9 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 39 FlexCAN2 Registers Address Map Continued FC2_BASE 00 FA00 FlexCAN2 is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FC2MB9_DATA 8E Message Buffer 9 Data Register FC2MB10_ CONTROL 90 Message Buffer 10 Control Status Register FC2MB10_ID_HIGH 91 Message Buffer 10 ID High Register FC2MB10_ID_LOW 92 Message Buffer 10 ID Low Register
126. ered off 1 No Output Switching 2 Includes Processor Core current supplied by internal voltage regulator Table 10 8 Current Consumption per Power Supply Pin Typical On Chip Regulator Disabled OCR_DIS High Mode lbD_Core l 1 DD_IO Ipp_ADC lbo_osc_PLL Test Conditions RUN1_MAC 150mA 134A 50mA 2 5mA 60MHz Device Clock All peripheral clocks are enabled All peripherals running Continuous MAC instructions with fetches from Data RAM ADC powered on and clocked Wait3 86mA 134A 70A 2 5mA 60MHz Device Clock All peripheral clocks are enabled ADC powered off Stop1 950A 134A OA 1654A 8MHz Device Clock All peripheral clocks are off ADC powered off PLL powered off Stop2 1004A 134A OA 1554A External Clock is off All peripheral clocks are off ADC powered off PLL powered off 1 No Output Switching 56F8366 Technical Data Rev 7 Freescale Semiconductor 149 Preliminary Table 10 9 Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage VRNL 2 25 2 75 V OmA Load Loaded Output Voltage VRL 2 25 2 75 V 200mA load Line Regulation 250mA load VR 2 25 2 75 V Vpp33 ranges from 3 0V to 3 6V Short Circuit Current Iss 700 mA output shorted to ground Bias Current l bias 5 8 7 mA Power down Current lod 0 2 HA Short Circui
127. ernal Signal s Map Continued Pins in shaded rows are not available in 56F8366 56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIO Bit Reset Functional Signal Package Pln Function 0 GPIO1 A16 33 1 N A 2 N A 3 N A GPIOB 4 N A 5 N A 6 N A 7 N A TThis is a function of the EMI_MODE EXTBOOT and Flash security settings at reset 0 Peripheral PhaseA1 TBO SCLK1 6 1 Peripheral PhaseB1 TB1 MOSI1 7 2 Peripheral Index1 TB2 MISO1 8 3 Peripheral Home1 TB3 5811 9 4 Peripheral PHASEAO TAO 139 GPIOC 5 Peripheral PHASEBO TA1 140 6 Peripheral Index0 TA2 141 7 Peripheral Homeo0 TA3 142 8 Peripheral ISAO 113 9 Peripheral ISA1 114 10 Peripheral ISA2 115 56F8366 Technical Data Rev 7 140 Freescale Semiconductor Preliminary Configuration Table 8 3 GPIO External Signals Map Continued Pins in shaded rows are not available in 56F8366 56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIO Bit ee Functional Signal Package Pin 0 GPIO CS2 CAN2_TX 48 1 GPIO CS3 CAN2_RX 49 2 N A 3 N A 4 N A 5 N A GPIOD 6 Peripheral TXD1 42 7 Peripheral RXD1 43 8 Peripheral PS CS0 46 9 Peripheral DS CS1 47 10 Peripheral ISBO 50 11 Peripheral ISB1 52 12 Peripheral ISB2 53 0 Peripheral TXDO 4 1 Peripheral R
128. essage Buffer 4 ID High Register FCMB4_ID_LOW 62 Message Buffer 4 ID Low Register FCMB4_DATA 63 Message Buffer 4 Data Register FCMB4_DATA 64 Message Buffer 4 Data Register FCMB4_DATA 65 Message Buffer 4 Data Register FCMB4_DATA 66 Message Buffer 4 Data Register Reserved FCMB5_CONTROL 68 Message Buffer 5 Control Status Register FCMB5_ID_HIGH 69 Message Buffer 5 ID High Register FCMB5_ID_LOW 6A Message Buffer 5 ID Low Register FCMB5_DATA 6B Message Buffer 5 Data Register FCMB5_DATA 6C Message Buffer 5 Data Register FCMB5_DATA 6D Message Buffer 5 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMB5_DATA 6E Message Buffer 5 Data Register Reserved FCMB6_CONTROL 70 Message Buffer 6 Control Status Register FCMB6_ID_HIGH 71 Message Buffer 6 ID High Register FCMB6_ID_LOW 72 Message Buffer 6 ID Low Register FCMB6_DATA 73 Message Buffer 6 Data Register FCMB6_DATA 74 Message Buffer 6 Data Register FCMB6_DATA 75 Message Buffer 6 Data Register FCMB6_DATA 76 Message Buffer 6 Data Register Reserved FCMB7_CONTROL 78 Message Buffer 7 Control Status Register FCMB7_ID_HIGH 79 Message B
129. etting this register set and using short I O addressing with the new value is three cycles Base D 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read ISAL 23 22 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 15 I O Short Address Location High Register SIM_ISALH 6 5 10 1 Input Output Short Address Low ISAL 23 22 Bit 1 0 This field represents the upper two address bits of the hard coded I O short address Base E 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read ISAL 21 6 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 16 I O Short Address Location Low Register SIM_ISAL 6 5 10 2 Input Output Short Address Low ISAL 21 6 Bit 15 0 This field represents the lower 16 address bits of the hard coded I O short address 6 5 11 Peripheral Clock Enable Register 2 SIM_PCE2 The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a power saving feaure The clocks can be individually controller for each peripheral on the chip Base D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 6 5 11 1 Reserved Bits 15 1 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 56F8366 Technical Data Rev 7 Freescale Semiconductor 131 Preliminary 6 5 11 2 CAN2 Enable Bit 0 Each
130. evel 56F8366 Technical Data Rev 7 Freescale Semiconductor 143 Preliminary Note The 56F 8166 device is guaranteed to 40MHz and specified to meet Industrial requirements only CAN is NOT available on the 56F 8166 device Table 10 1 Absolute Maximum Ratings Vss Vssa anc 0 Characteristic Symbol Notes Min Max Unit Supply voltage Vop_lo 0 3 4 0 V ADC Supply Voltage VDDA ADC VREFH VREFH must be less than or 0 3 4 0 vV equal to VDDA_ADC Oscillator PLL Supply Voltage VDDA_OsC PLL 0 3 4 0 V Internal Logic Core Supply Voltage VDD_CORE OCR_DIS is High 0 3 3 0 V Input Voltage digital Vin Pin Groups 1 2 5 6 9 10 0 3 6 0 V Input Voltage analog VINA Pin Groups 11 12 13 0 3 4 0 V Output Voltage VouT Pin Groups 1 2 3 4 5 6 7 8 0 3 4 0 V 6 01 Output Voltage open drain Vop Pin Group 4 0 3 6 0 V Ambient Temperature Automotive Ta 40 125 C Ambient Temperature Industrial Ta 40 105 C Junction Temperature Automotive Ty 40 150 C Junction Temperature Industrial Ty 40 125 C Storage Temperature Automotive TsTG 55 150 C Storage Temperature Industrial TsTG 55 150 C 1 If corresponding GPIO pin is configured as open drain Note Pins in italics are NOT available in the 56F8166 device Pin Group 1 TXDO 1 RXDO 1 SSO MISOO MOSIO Pin Group 2 PHASEAO PHASEA1 PHASEBO PHASEB1 INDEXO INDEX1 HOMEO HOME1 ISB
131. evice uses to latch the data To activate the SPI function set the PHSB_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOC1 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output In the 56F8366 the default state after reset is PHASEB1 In the 56F8166 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit 1 in the GPIOC_PUR register 56F8366 Technical Data Rev 7 Freescale Semiconductor 31 Preliminary Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset INDEX1 8 Schmitt Input Index1 Quadrature Decoder 1 INDEX input Input pull up enabled TB2 Schmitt TB2 Timer B Channel 2 Input Output MISO1 Schmitt SPI 1 Master In Slave Out This serial data pin is an input to a Input master device and an output from a slave device The MISO line of Output a slave device is placed in the high impedance state if the slave device is not selected The slave device places data on the MISO line a half cycle before the clock edge the master device uses to latch the data To activate the SPI function set the INDEX_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOC2 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input an input or output pin Output After re
132. ference Manual The interrupt controller recognizes fast interrupts before the core does A fast interrupt is defined to the ITCN by 1 Setting the priority of the interrupt as level 2 with the appropriate field in the IPR registers 2 Setting the FIMn register to the appropriate vector number 3 Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs its vector number is compared with the FIMO and FIM register values If a match occurs and it is a level 2 interrupt the ITCN handles it as a fast interrupt The ITCN takes the vector address from the appropriate FIVALn and FIVAHnh registers instead of generating an address that is an offset from the VBA The core then fetches the instruction from the indicated vector adddress and if it is not a JSR the core starts its fast interrupt handling 56F8366 Technical Data Rev 7 84 Freescale Semiconductor Preliminary Block Diagram 5 4 Block Diagram 5 5 any0 Priority gt Levelo y Level Z d 82 gt 7 7 Priority INT1 __ 2 gt 4 gt Encoder A Decode l e p m INT toe m VAB CONTROL m IPIC any3 gt Level3 Priority aa Level i Sa a 7 7 IACK riority Encoder SRI9 8 PIC_EN INT82__ 2 gt 4 Z Decode p Figure 5 1 Interrupt Controller Block Diagram
133. ffer 1 Control Status Register FCMSB1_ID_HIGH 49 Message Buffer 1 ID High Register FCMSB1_ID_LOW 4A Message Buffer 1 ID Low Register FCMB1_DATA 4B Message Buffer 1 Data Register FCMB1_DATA 4C Message Buffer 1 Data Register FCMB1_DATA 4D Message Buffer 1 Data Register FCMB1_DATA 4E Message Buffer 1 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 73 Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description Reserved FCMB2_CONTROL 50 Message Buffer 2 Control Status Register FCMB2_ID_HIGH 51 Message Buffer 2 ID High Register FCMB2_ID_LOW 52 Message Buffer 2 ID Low Register FCMB2_DATA 53 Message Buffer 2 Data Register FCMB2_DATA 54 Message Buffer 2 Data Register FCMB2_DATA 55 Message Buffer 2 Data Register FCMB2_DATA 56 Message Buffer 2 Data Register Reserved FCMB3_CONTROL 58 Message Buffer 3 Control Status Register FCMB3_ID_HIGH 59 Message Buffer 3 ID High Register FCMB3_ID_LOW 5A Message Buffer 3 ID Low Register FCMB3_DATA 5B Message Buffer 3 Data Register FCMB3_DATA 5C Message Buffer 3 Data Register FCMB3_DATA 5D Message Buffer 3 Data Register FCMB3_DATA 5E Message Buffer 3 Data Register Reserved FCMB4_ CONTROL 60 Message Buffer 4 Control Status Register FCMB4_ID_HIGH 61 M
134. for a total of 12 PWM outputs to enhance motor control functionality Complementary operation permits programmable dead time insertion distortion correction via current sensing by software and separate top and bottom output polarity control The up counter value is programmable to support a continuously variable PWM frequency Edge aligned and center aligned synchronous pulse width control 0 to 100 modulation is supported The device is capable of controlling most motor types ACIM AC Induction Motors both BDC and BLDC Brush and Brushless DC motors SRM and VRM Switched and Variable Reluctance Motors and stepper motors The PWMs incorporate fault protection and cycle by cycle current limiting with sufficient output drive capability to directly drive standard optoisolators A smoke inhibit write once protection feature for key parameters is also included A patented PWM waveform distortion correction circuit is also provided Each PWM is double buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16 The PWM modules provide reference outputs to synchronize the Analog to Digital Converters through two channels of Quad Timer C The 56F8366 incorporates two Quadrature Decoders capable of capturing all four transitions on the two phase inputs permitting generation of a number proportional to actual position Speed computation capabilities accommodate both fast and slow moving shafts An integ
135. form production flash programming of the on board flash memories as well as other potential methods Like all the flash memory blocks the Boot Flash can be erased and programmed by the user The Serial Bootloader application is programmed as an aid to the end user but is not required to be used or maintained in the Boot Flash memory 56F8366 Technical Data Rev 7 82 Freescale Semiconductor Preliminary Introduction Part 5 Interrupt Controller ITCN 5 1 Introduction The Interrupt Controller ITCN module is used to arbitrate between various interrupt requests IRQs to signal to the 56800E core when an interrupt of sufficient priority exists and to what address to jump in order to service this interrupt 5 2 Features The ITCN module design includes these distinctive features e Programmable priority levels for each IRQ Two programmable Fast Interrupts e Notification to SIM module to restart clocks out of Wait and Stop modes e Drives initial address on the address bus after reset For further information see Table 4 5 Interrupt Vector Table Contents 5 3 Functional Description The Interrupt Controller is a slave on the IPBus It contains registers allowing each of the 86 interrupt sources to be set to one of four priority levels excluding certain interrupts of fixed priority Next all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests f
136. fset Register 7 ADCA_POWER 29 Power Control Register ADCA_CAL 2A ADC Calibration Register Table 4 21 Analog to Digital Converter Registers Address Map ADCB_BASE 00 F240 Register Acronym Address Offset Register Description ADCB_CR 1 0 Control Register 1 ADCB_CR 2 1 Control Register 2 ADCB_ZCC 2 Zero Crossing Control Register ADCB_LST 1 3 Channel List Register 1 ADCB_LST 2 4 Channel List Register 2 ADCB_SDIS 5 Sample Disable Register ADCB_STAT 6 Status Register ADCB_LSTAT 7 Limit Status Register ADCB_ZCSTAT 8 Zero Crossing Status Register ADCB_RSLT O 9 Result Register 0 ADCB_RSLT 1 A Result Register 1 ADCB_RSLT 2 B Result Register 2 ADCB_RSLT 3 C Result Register 3 ADCB_RSLT 4 D Result Register 4 ADCB_RSLT 5 E Result Register 5 ADCB_RSLT 6 F Result Register 6 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Table 4 21 Analog to Digital Converter Registers Address Map Peripheral Memory Mapped Registers ADCB_BASE 00 F240 Continued Register Acronym Address Offset Register Description ADCB_RSLT 7 10 Result Register 7 ADCB_LLMT 0 11 Low Limit Register 0 ADCB_LLMT 1 12 Low Limit Register 1 ADCB_LLMT 2 13 Low Limit Register 2 ADCB_LLMT 3 14 Low Limit Register 3 ADCB_LLMT 4 15 Low Limit Register 4 ADCB_LLMT 5 16 Low Limit Register 5
137. gister ey 14 E le GPIOA8 set bit 8 in the GPIOA_PUR regist GPIOA11 xample set bit 8 in the a register A4 13 GPIOA12 A5 14 GPIOA13 56F8366 Technical Data Rev 7 20 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset A6 17 Output In reset Address Bus A6 A7 specify two of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR A6 A7 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOE2 Schmitt Port E GPIO These two GPIO pins can be individually Input programmed as input or output pins A7 18 Output After reset the default state is Address Bus GPIOE3 To deactivate the internal pull up resistor set the appropriate GPIO bit in the GPIOE_PUR register Example GPIOE2 set bit 2 in the GPIOE_PUR register A8 19 Output In reset Address Bus A8 A15 specify eight of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR A8 A15 and EMI contro
138. gisters Address Map SCI1_BASE 00 F290 Register Acronym Address Offset Register Description SCI1_SCIBR 0 Baud Rate Register SCI1_SCICR SCI1_SCISR 1 3 Control Register Reserved Status Register SCI1_SCIDR 4 Data Register Table 4 25 Serial Peripheral Interface 0 Registers Address Map SPIO_BASE 00 F2A0 Register Acronym Address Offset Register Description SPIO_SPSCR 0 Status and Control Register SPIO_SPDSR 1 Data Size Register SPIO_SPDRR 2 Data Receive Register SPIO_SPDTR 3 Data Transmitter Register 56F8366 Technical Data Rev 7 66 Freescale Semiconductor Peripheral Memory Mapped Registers Table 4 26 Serial Peripheral Interface 1 Registers Address Map SPI1_BASE 00 F2B0 Register Acronym Address Offset Register Description SPI1_SPSCR 0 Status and Control Register SPI1_SPDSR 1 Data Size Register SPI1_SPDRR 2 Data Receive Register SPI1_SPDTR 3 Data Transmitter Register Table 4 27 Computer Operating Properly Registers Address Map COP_BASE 00 F2C0 Register Acronym Address Offset Register Description Table 4 28 Clock Generation Module Registers Address Map Register Acronym COPCTL 0 Control Register COPTO 1 Time Out Register COPCTR 2 Counter Register CLKGEN_BASE 00 F2D0 Address Offset Register Descrip
139. idually programmed as Input pull up an input or output pin Output enabled CS3 Output Chip Select CS3 may be programmed within the EMI module to act as achip select for specific areas of the external memory map Depending upon the state of the DRV bit in the EMI Bus Control Register BCR CS3 is tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting CAN2_RX Schmitt FlexCAN2 Receive Data This is the CAN input This pin has an Input internal pull up resistor At reset this pin is configured as GPIO This configuration can be changed by setting bit 1 in the GPIO_D_PER register Then change bit 5 in the SIM_GPS register to select the desired peripheral function To deactivate the internal pull up resistor clear bit 1 in the GPIOD_PUR register TXDO 4 Output In reset Transmit Data SCIO transmit data output output is GPIOE0 Input disabled Port E GPIO This GPIO pin can be individually programmed as Output pull up is an input or output pin enabled After reset the default state is SCI output To deactivate the internal pull up resistor clear bit O in the GPIOE_PUR register RXDO 5 Input Input Receive Data SCIO receive data input pull up GPIOE1 Input enabled Port E GPIO This GPIO pin can be individually programmed as Output an input or output pin After reset the default state is SCI output To
140. ient for C C Compilers to enable rapid development of optimized control applications The 56F8366 and 56F8166 support program execution from either internal or external memories Two data operands can be accessed from the on chip data RAM per instruction cycle These devices also provides two external dedicated interrupt lines and up to 62 General Purpose Input Output GPIO lines depending on peripheral configuration 56F8366 Technical Data Rev 7 Freescale Semiconductor 7 Preliminary 1 2 1 56F8366 Features The 56F8366 hybrid controller includes 512KB of Program Flash and 32KB of Data Flash each programmable through the JTAG port with 4KB of Program RAM and 32KB of Data RAM It also supports program execution from external memory A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field programmable software routines that can be used to program the main Program and Data Flash memory areas Both Program and Data Flash memories can be independently bulk erased or erased in pages Program Flash page erase size is IKB Boot and Data Flash page erase size is 512 bytes The Boot Flash memory can also be either bulk or page erased A key application specific feature of the 56F8366 is the inclusion of two Pulse Width Modulator PWM modules These modules each incorporate three complementary individually programmable PWM signal output pairs each module is also capable of supporting six independent PWM functions
141. ill want to change the DRV state to DRV 1 instead of using the default setting To deactivate the internal pull up resistor set the CTRL bit in the SIM_PUDR register PS 46 Output In reset Program Memory Select This signal is actually CSO in the E output is EMI which is programmed at reset for compatibility with the CSO disabled 56F80x PS signal PS is asserted low for external program pull up is memory access enabled Depending upon the state of the DRV bit in the EMI bus control register BCR PS is tri stated when the external bus is inactive CSO resets to provide the PS function as defined on the 56F80x devices GPIOD8 Input Port D GPIO This GPIO pin can be individually programmed as Output an input or output pin To deactivate the Internal pull up resistor clear bit 8 in the GPIOD_PUR register 56F8366 Technical Data Rev 7 24 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset DS 47 Output In reset Data Memory Select This signal is actually CS1 in the EMI __ output is which is programmed at reset for compatibility with the 56F80x DS CS1 disabled signal DS is asserted low for external data memory access pull up is enabled Depending upon the state of the DRV bit in the EMI bus control register BCR DS is tri stated
142. ing edge of the system clock 56F8366 Technical Data Rev 7 Freescale Semiconductor 133 Preliminary Part 7 Security Features The 56F8366 56F8166 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory FM array The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array However part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program as this code would defeat the purpose of security At the same time the user may also wish to put a backdoor in his program As an example the user downloads a security key through the SCI allowing access to a programming routine that updates parameters stored in another section of the Flash 7 1 Operation with Security Enabled Once the user has programmed the Flash with his application code the device can be secured by programming the security bytes located in the FM configuration field which occupies a portion of the FM array These non volatile bytes will keep the part secured through reset and through power down of the device Only two bytes within this field are used to enable or disable security Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security When Flash security mode i
143. iority Register 4 IPR 5 5 Interrupt Priority Register 5 IPR6 6 Interrupt Priority Register 6 IPR 7 7 Interrupt Priority Register 7 IPR 8 8 Interrupt Priority Register 8 IPR 9 9 Interrupt Priority Register 9 VBA A Vector Base Address Register FIMO B Fast Interrupt Match Register 0 FIVALO C Fast Interrupt Vector Address Low 0 Register FIVAHO D Fast Interrupt Vector Address High O Register FIM1 E Fast Interrupt Match Register 1 FIVAL1 F Fast Interrupt Vector Address Low 1 Register FIVAH1 10 Fast Interrupt Vector Address High 1 Register IRQP 0 11 IRQ Pending Register 0 IRQP 1 12 IRQ Pending Register 1 IRQP 2 13 IRQ Pending Register 2 IRQP 3 14 IRQ Pending Register 3 IRQP 4 15 IRQ Pending Register 4 IRQP 5 16 IRQ Pending Register 5 ICTL 1D Interrupt Control Register IPR10 1F Interrupt Priority Register 10 56F8366 Technical Data Rev 7 62 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 20 Analog to Digital Converter Registers Address Map ADCA_BASE 00 F200 Register Acronym Address Offset Register Description ADCA_CR 1 0 Control Register 1 ADCA_CR 2 1 Control Register 2 ADCA_ZCC 2 Zero Crossing Control Register ADCA_LST 1 3 Channel List Register 1 ADCA_LST 2 4 Channel List Register 2 ADCA_SDIS 5 Sample Disable Register ADCA_STAT 6 Status Register ADCA_LSTAT 7
144. is disabled 6 5 10 I O Short Address Location Register SIM_ISALH and SIM_ISALL The I O Short Address Location registers are used to specify the memory referenced via the I O short address mode The I O short address mode allows the instruction to specify the lower six bits of address the upper address bits are not directly controllable This register set allows limited control of the full address as shown in Figure 6 14 Note If this register is set to something other than the top of memory EOnCE register space and the EX bit in the OMR is set to 1 the JTAG port cannot access the on chip EOnCE registers and debug functions will be affected Hard Coded Address Portion Instruction Portion N a s 6 Bits from I O Short Address Mode Instruction 16 Bits from SIM_ISALL Register y Figure 6 14 I O Short Address Determination 2 bits from SIM_ISALH Register Full 24 Bit for Short I O Address 56F8366 Technical Data Rev 7 130 Freescale Semiconductor Preliminary Register Descriptions With this register set an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I O Short addressing mode to reference them The ISR should restore this register to its previous contents prior to returning from interrupt Note The default value of this register set points to the EOnCE registers Note The pipeline delay between s
145. is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 7 Timer C Channel 2 Interrupt Priority Level TMRC2 IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 8 Timer C Channel 1 Interrupt Priority Level TMRC1 IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 Interrupt Priority Register 8 IPR8 Base 8 15 14 is 12 11 10 9 8 7 6 5 4 3 2 1 0 Read dde pod ae TMRA3 IPL TMRA2 IPL TMRA1 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 11 Interrupt Priority Register 8 IPR8 5 6 9 1 SCIO Receiver Full Interrupt Priority Level SCIO_RCV IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freesca
146. isabled by default e 00 IRQ disabled default e 01 IRQis priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 8 Reserved Bits 1 0 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 5 Interrupt Priority Register 4 IPR4 Base 4 15 14 13 12 11 5 4 3 2 1 0 Read ay ie a MT el GPIOAIPL GPIOBIPL GPIOC IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5 7 Interrupt Priority Register 4 IPR4 56F8366 Technical Data Rev 7 Freescale Semiconductor 93 Preliminary 5 6 5 1 SPIO Receiver Full Interrupt Priority Level SPIO_RCV IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 2 SPI1 Transmit Empty Interrupt Priority Level SPI1_XMIT IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 3 SPI1 Receiver Full Interrupt Priority Level SPI1_RCV IPL Bits 11 10 This field is used to set the interrupt priority
147. kage Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset RD 45 Output In reset Read Enable RD is asserted during external memory read output is cycles When RD is asserted low pins DO D15 become inputs disabled and an external device is enabled onto the data bus When RD is pull up is deasserted high the external data is latched inside the device enabled When RD is asserted it qualifies the AO A16 PS DS and CSn pins RD can be connected directly to the OE pin of a static RAM or ROM Depending upon the state of the DRV bit in the EMI bus control register BCR RD is tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting To deactivate the internal pull up resistor set the CTRL bit in the SIM_PUDR register WR 44 Output In reset Write Enable WR is asserted during external memory write output is cycles When WR is asserted low pins DO D15 become outputs disabled and the device puts data on the bus When WR is deasserted high pull up is the external data is latched inside the external device When WR is enabled asserted it qualifies the AO A16 PS DS and CSn pins WR can be connected directly to the WE pin of a static RAM Depending upon the state of the DRV bit in the EMI bus control register BCR WR is tri stated when the external bus is inactive Most designs w
148. l function of GPIO B 7 4 to be programmed as A 23 20 This can be changed by altering A 23 20 as shown in Figure 6 9 Base A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 CLK A23 A22 A21 A20 DIS CLKOSEL Write RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Figure 6 9 CLKO Select Register SIM_CLKOSR 6 5 7 1 Reserved Bits 15 10 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 7 2 Alternate GPIOB Peripheral Function for A23 A23 Bit 9 e 0 Peripheral output function of GPIO B7 is defined to be A23 e Peripheral output function of GPIO B7 is defined to be the oscillator clock MSTR_OSC see Figure 3 4 6 5 7 3 Alternate GPIOB Peripheral Function for A22 A22 Bit 8 e 0 Peripheral output function of GPIOB6 is defined to be A22 e 1 Peripheral output function of GPIOB6 is defined to be SYS_CLK2 6 5 7 4 Alternate GPIOB Peripheral Function for A21 A21 Bit 7 e 0 Peripheral output function of GPIOBS is defined to be A21 e 1 Peripheral output function of GPIOBS is defined to be SYS_CLK 6 5 7 5 Alternate GPIOB Peripheral Function for A20 A20 Bit 6 e 0 Peripheral output function of GPIOB4 is defined to be A20 e 1 Peripheral output function of GPIOB4 is defined to be the prescaler clock FREF see Figure 3 4 56F8366 Technical Data Rev 7 Freescale Semiconductor 123 Preliminary 6
149. l signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOAO Schmitt Port A GPIO These eight GPIO pins can be individually Input programmed as input or output pins A9 20 Output GPIOA1 After reset the default state is Address Bus A10 21 To deactivate the internal pull up resistor set the appropriate GPIOA2 GPIO bit in the GPIOA_PUR register edi 2 E le GPIOAO set bit 0 in the GPIOA_PUR regist GPIOA3 xample set bit O in the YA register A12 23 GPIOA4 A13 24 GPIOA5 A14 25 GPIOA6 A15 26 GPIOA7 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 21 Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset GPIOBO 33 Schmitt Input Port B GPIO This GPIO pin can be programmed as an input or Input pull up output pin Output enabled A16 Output Address Bus A16 specifies one of the address lines for external program or data memory accesses Depending upon the state of the DRV bit in the EMI bus control register BCR A16 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting After reset the startup state of GPIOBO GPIO or address is determined as a function of E
150. le Semiconductor 101 Preliminary 5 6 9 2 SCIO Receiver Error Interrupt Priority Level SCIO_RERR IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 3 Reserved Bits 11 10 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 9 4 SCIO Transmitter Idle Interrupt Priority Level SCIO_TIDL IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 5 SCI0 Transmitter Empty Interrupt Priority Level SCIO_XMIT IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 6 Timer A Channel 3 Interrupt Priority Level TMRA3 IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e
151. led by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 4 FlexCAN Message Buffer Interrupt Priority Level FCMSGBUF IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 92 Freescale Semiconductor Preliminary Register Descriptions 5 6 4 5 FlexCAN Wake Up Interrupt Priority Level FCWKUP IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 6 FlexCAN Error Interrupt Priority Level FCERR IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQis priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 7 FlexCAN Bus Off Interrupt Priority Level FCBOFF IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are d
152. lest or most negative Table 10 16 External Memory Interface Timing Characteristic Symbol Pd D M bd rte aay Unit Address Valid to WR Asserted a WWS 0 ne a wwss n WWS gt 0 1 795 0 75 DCAOE WR Width Asserted to WR fie WWS 0 0 094 0 25 DCAOE WWS r Deasserted WWS gt 0 0 012 0 Data Out Valid to WR Asserted WWS 0 9 321 0 25 DCAEO WWS 0 1 160 0 00 towr WWSS ns WWS gt 0 8 631 0 50 WWS gt 0 0 879 0 25 DCAOE Valid Data Out Hold Time after WR tooy 2 086 0 25 DCAEO WWSH s Deasserted 56F8366 Technical Data Rev 7 Freescale Semiconductor 155 Preliminary Table 10 16 External Memory Interface Timing Continued Characteristic Symbol Welt slate D M Walt Staras Unit Configuration Controls Valid Data Out Set Up Time to WR to ee Pee OEE A il ie Deasserted 8 315 0 50 WR t Valid Address after WR WAG 3 432 0 25 DCAEO WWSH ns Deasserted RD Deasserted to Address Invalid tRDA 1 780 0 00 RWSH ns Address Valid to RD Deasserted taRDD 2 120 1 00 RWSS RWS ns Valid Input Data Hold after RD 0 00 N A is Deasserted RD Assertion Width tRD 0 279 1 00 RWS ns Address Valid to Input Data Valid tap 15 723 1 00 ess W as 20 642 1 25 DCAOE Address Valid to RD Asserted taRDA 2 603 0 00 RWSS ns PD 13 120 1 00 RD Asserted to Input Data Valid t RDD ns 18 039 1 25 DCAOE RWSS RWS WR Deasserted to RD Asserted tWRRD
153. level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 4 Reserved Bits 9 6 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 5 5 GPIOA Interrupt Priority Level GPIOA IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 94 Freescale Semiconductor Preliminary Register Descriptions 5 6 5 6 GPIOB Interrupt Priority Level GPIOB IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 7 GPIOC Interrupt Priority Level GPIOC IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 Interrupt Priority Regis
154. liminary Architecture Block Diagram 5 JTAG EONCE Ser te as pdb_m 15 0 e Program pab 20 0 p Flash _ _ Program cdbw 31 0 b RAM 56800E ca e 17 CHIP H Address TAP gt EMI 16 Controller X 3 Data ae ae Control TAP Linking o gt p Module xab1 23 0 b gt Data RAM xab2 23 0 p e gt r yt External Data Flash Port cdbr_m 31 0 xdb2_m 15 0 lt To Flash IPBus Con trol Logic p Bridge A NOT available on the 56F8166 device Flash gt Memory Module IPBus Figure 1 1 System Bus Interfaces Note Flash memories are encapsulated within the Flash Memory FM Module Flash control is accomplished by the I O to the FM over the peripheral bus while reads and writes are completed between the core and the Flash memories Note The primary data RAM port is 32 bits wide Other data ports are 16 bits 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 11 To From IPBus Bridge Interrupt lt p CLKGEN OSC PLL Controller A Low Voltage Interrupt me
155. minary 3 2 3 External Clock Source The recommended method of connecting an external clock is given in Figure 3 4 The external clock source is connected to XTAL and the EXTAL pin is grounded Set OCCS_COHL bit high when using an external clock source as well Note When using an external clocking source with this configuration the input CLKMODE should be high and the COHL bit in the OSCTL External Vss register should be set to 1 Clock Figure 3 4 Connecting an External Clock Register 3 3 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual use the register definitions without the internal Relaxation Oscillator since the 56F8366 56F8166 devices do NOT contain this oscillator Part 4 Memory Map 4 1 Introduction The 56F8366 and 56F8166 devices are 16 bit motor control chip based on the 56800E core These parts use a Harvard style architecture with two independent memory spaces for Data and Program On chip RAM and Flash memories are used in both spaces This section provides memory maps for e Program Address Space including the Interrupt Vector Table e Data Address Space including the EOnCE Memory and Peripheral Memory Maps On chip memory sizes for each device are summarized in Table 4 1 Flash memories restrictions are identified in the Use Restrictions column of Table 4 1 56F8366 Technical Data Rev 7 40 Freescale Semiconductor Preliminary Prog
156. n ori Von min Pin Groups 5 6 7 8 Pin Group 8 12 Output Low Sink Current loL Pin Groups 1 2 3 4 4 mA VoL 0 4V V oL VoL max Pin Groups 5 6 7 8 Pin Group 8 12 Ambient Operating Temperature Ta 40 125 C Automotive Ambient Operating Temperature Ta 40 105 C Industrial Flash Endurance Automotive Ne Ta 40 C to 125 C 10 000 Cycle Program Erase Cycles s Flash Endurance Industrial Ne Ta 40 C to 105 C 10 000 Cycle Program Erase Cycles s Flash Data Retention TR Ty lt 85 C avg 15 Years Note Total chip source or sink current cannot exceed 200 mA See Pin Groups in Table 10 1 56F8366 Technical Data Rev 7 146 Freescale Semiconductor Preliminary 10 2 DC Electrical Characteristics DC Electrical Characteristics Note The 56F 8166 device is specified to meet Industrial requirements only CAN is NOT available on the 56F 8166 device Table 10 5 DC Electrical Characteristics At Recommended Operating Conditions see Table 10 4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VoH 2 4 a V loH lOHmax Output Low Voltage VoL 0 4 V loL loLmax Digital Input Current High hh Pin Groups 1 2 5 6 9 0 2 5 LA Vin 3 0V to 5 5V pull up enabled or disabled Digital Input Current High ll Pin Group 10 40 80 160 uA Vin 3 0V to 5 5V with pull dow
157. n Analog Input Current High liHA Pin Group 13 0 2 5 uA Vin Vppa ADC Input Current High liHADC Pin Group 12 0 3 5 uA Vin Vppa Digital Input Current Low liL Pin Groups 1 2 5 6 9 200 100 50 LA Vin OV pull up enabled Digital Input Current Low liL Pin Groups 1 2 5 6 9 0 2 5 uA Vin OV pull up disabled Digital Input Current Low liL Pin Group 10 0 2 5 uA Vin OV with pull down Analog Input Current Low liLa Pin Group 13 0 2 5 uA Vin OV ADC Input Current Low liLADC Pin Group 12 0 3 5 uA Vin OV EXTAL Input Current Low lexraj 0 2 5 uA Vin Vppa or OV clock input XTAL Input Current Low IXTAL CLKMODE High _ 0 2 5 uA Vin Vppa or OV clock input CLKMODE Low 200 pA Vin Vppa or OV Output Current loz Pin Groups 0 2 5 LA Vout 3 0V to 5 5V High Impedance State 1 2 3 4 5 6 7 8 or OV Schmitt Trigger Input Vuys Pin Groups 2 6 9 10 0 3 V Hysteresis Input Capacitance Cinc os 45 pF EXTAL XTAL Output Capacitance Coutc 55 pF EXTAL XTAL Input Capacitance Cin 6 pF Output Capacitance Cout 6 pF See Pin Groups in Table 10 1 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 147 E gt Cepal ea ras i IES A TS als SALE Sh 0 E 10 30 50 70
158. nal is used to initialize address bits 19 16 either as GPIO or as address These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset In addition this pin can be used as a general purpose input pin after reset 0 External address bits 19 16 are initially programmed as GPIO 1 When booted with EXTBOOT 1 A 19 16 are initially programmed as address If EXTBOOT is 0 they are initialized as GPIO 6 5 1 3 OnCE Enable OnCE EBL Bit 5 e 0 OnCE clock to 56800E core enabled when core TAP is enabled 1 OnCE clock to 56800E core is always enabled 6 5 1 4 Software Reset SW RST Bit 4 This bit is always read as 0 Writing a 1 to this bit will cause the part to reset 6 5 1 5 Stop Disable STOP_DISABLE Bits 3 2 00 Stop mode will be entered when the 56800E core executes a STOP instruction e 01 The 56800E STOP instruction will not cause entry into Stop mode STOP_DISABLE can be reprogrammed in the future 10 The 56800E STOP instruction will not cause entry into Stop mode STOP_DISABLE can then only be changed by resetting the device 11 Same operation as 10 6 5 1 6 Wait Disable WAIT_DISABLE Bits 1 0 e 00 Wait mode will be entered when the 56800E core executes a WAIT instruction 01 The 56800E WAIT instruction will not cause entry into Wait mode WAIT_DISABLE can be reprogrammed in the future e 10 The 56800E WAIT instruction will not cau
159. nductor Preliminary 153 Table 10 15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Bias Current low drive mode IBIASL 80 110 HA Quiescent Current power down mode Ipp NN 0 1 HA 10 8 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices Figure 10 5 shows sample timing and parameters that are detailed in Table 10 16 The timing of each parameter consists of both a fixed delay portion and a clock related portion as well as user controlled wait states The equation t D P M W should be used to determine the actual time of each parameter The terms in this equation are defined as t D P Parameter delay time Fixed portion of the delay due to on chip path delays Period of the system clock which determines the execution rate of the part 1 e when the device is operating at 60MHz P 16 67 ns Fixed portion of a clock period inherent in the design this number is adjusted to account for possible derating of clock duty cycle Sum of the applicable wait state controls The Wait State Controls column of Table 10 16 shows the applicable controls for each parameter and the EMI chapter of the 56F8300 Peripheral User Manual details what each wait state field controls When using the XTAL clock input directly as the chip clock without prescaling ZSRC selects prescaler clock and presc
160. ns 10 8 Access Out Valid caused by first instruction execution in the interrupt service routine tiDM FAST 14T IRQA IRQB Assertion to General Purpose Output tic 18T ns 10 8 Valid caused by first instruction execution in the interrupt service routine tig FAST 14T Delay from IRQA Assertion exiting Wait to External tii 22T ns 10 9 Data Memory Access tiRI FAST 18T Delay from IRQA Assertion to External Data Memory tr 22T ns 10 10 Access exiting Stop tir FAST 18T IRQA Width Assertion to Recover from Stop State tiw 1 5T ns 10 10 1 In the formulas T clock cycle For an operating frequency of 6OMHz T 16 67ns At 8MHz used during Reset and Stop modes T 125ns 2 Parameters listed are guaranteed by design 3 During Power On Reset it is possible to use the device s internal reset stretching circuitry to extend this period to 2217 4 The minimum is specified for the duration of an edge sensitive IRQA interrupt required to recover from the Stop state This is not the minimum required so that the IRQA interrupt is accepted 5 The interrupt instruction fetch is visible on the pins only in Mode 3 RESET tra a tRaz tRDA A0 A15 DO_D15 First Fetch Figure 10 6 Asynchronous Reset Timing IRQA IRQB trw Figure 10 7 External Interrupt Timing Negative Edge Sensitive 56F8366 Technical Data Rev 7 Freescale Semiconductor 157 Preliminary A0 A1
161. nt Timer A r POR amp LVI ail py Quadrature Decoder 0 y System POR SIM RESET a Timer D A COP Reset e Timer B lt _ _ gt COP q 4 p gt Quadrature Decoder 1 g gt FlexCAN FlexCAN2 SPI a PWMA w GPIOA GPIOB PWMB 13 GPIOC li GPIOD ch3i chai Timer C Puan GPIOE ones fey GPIOF ll 8 lt gt SPIO ADCB e gt Y lt P sco ADCA Be lt gt sen TEMP_SENSE ae NOT available on the 56F8166 device IPBus Note ADCA and ADCB use the same voltage Figure 1 2 Peripheral Subsystem 56F8366 Technical Data Rev 7 reference circuit with VrerH Vrerp VREFMID Vrern and VrerLO Pins Freescale Semiconductor Preliminary Architecture Block Diagram Table 1 2 Bus Signal Names Name Function Program Memory Interface pdb_m 15 0 Program data bus for instruction word fetches or read operations cdbw 15 0 Primary core data bus used for program memory writes Only these 16 bits of the cdbw 31 0 bus are used for writes to program memory pab 20 0 Program memory address bus Data is returned on pdb_m bus Primary Data Memory Interface Bus cdbr_m 31 0 Primary core data bus for memory reads Addressed via xab1 bus cdbw 31 0 Primary core data bus for memory writes Addressed via xab1 bus xab1 23 0 Primary data address bus Capable of addressing bytes words and long data types Data is written on cdbw and returned on cd
162. nt the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 21 IRQ Pending 3 Register IRQP3 Base 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 64 49 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 23 IRQ Pending 3 Register IRQP3 5 6 21 1 IRQ Pending PENDING Bits 64 49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 56F8366 Technical Data Rev 7 Freescale Semiconductor 109 Preliminary 5 6 22 IRQ Pending 4 Register IRQP4 Base 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 80 65 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 24 IRQ Pending 4 Register IRQP4 5 6 22 1 IRQ Pending PENDING Bits 80 65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 23 IRQ Pending 5 Register IRQP5 Base 16 3 2 1 0 PENDING 81 85 Figure 5 25 IRQ Pending Register 5 IRQP5 5 6 23 1 Reserved Bits 96 86 This bit field is
163. ntrol Register 0 Register FCCTL1 4 Control Register 1 Register FCTMR 5 Free Running Timer Register 56F8366 Technical Data Rev 7 72 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMAXMB 6 Maximum Message Buffer Configuration Register FCRXGMASK_H 8 Receive Global Mask High Register FCRXGMASK_L 9 Receive Global Mask Low Register FCRX14MASK_H A Receive Buffer 14 Mask High Register FCRX14MASK_L B Receive Buffer 14 Mask Low Register FCRX15MASK_H C Receive Buffer 15 Mask High Register FCRX15MASK_L D Receive Buffer 15 Mask Low Register FCSTATUS 10 Error and Status Register FCIMASK1 11 Interrupt Masks 1 Register FCIFLAG1 12 Interrupt Flags 1 Register FCR T_ERROR_CNTRS 13 Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMBO_CONTROL 40 Message Buffer O Control Status Register FCMBO_ID_HIGH 41 Message Buffer 0 ID High Register FCMBO_ID_LOW 42 Message Buffer 0 ID Low Register FCMBO_DATA 43 Message Buffer 0 Data Register FCMBO_DATA 44 Message Buffer 0 Data Register FCMBO_DATA 45 Message Buffer 0 Data Register FCMBO_DATA 46 Message Buffer 0 Data Register FCMSB1_CONTROL 48 Message Bu
164. ntry in the vector table This does not allow the full address range to be referenced from the vector table providing only 19 bits of address 2 If the VBA is set to 0200 or VBA 0000 for Mode 1 EMI_MODE 0 the first two locations of the vector table are the chip reset addresses therefore these locations are not interrupt vectors 56F8366 Technical Data Rev 7 46 Freescale Semiconductor Preliminary 4 4 Data Map Note Data Flash is NOT available on the 56F8166 device Table 4 6 Data Memory Map Data Map Begin End _ a2 Address EX 0 EA X FF FFFF EOnCE EOnCE X FF FFOO 256 locations allocated 256 locations allocated X FF FEFF External Memory External Memory X 01 0000 X 00 FFFF On Chip Peripherals On Chip Peripherals X 00 F000 4096 locations allocated 4096 locations allocated X 00 EFFF External Memory External Memory X 00 8000 X 00 7FFF On Chip Data Flash X 00 4000 32KB X 00 3FFF On Chip Data RAM X 00 0000 32KB3 1 All addresses are 16 bit Word addresses not byte addresses 2 In the Operation Mode Register OMR 3 The Data RAM is organized as an 8K x 32 bit memory to allow single cycle long word operations 4 5 Flash Memory Map Figure 4 1 illustrates the Flash Memory FM map on the system bus The Flash Memory is divided into three functional blocks The Program and boot memories reside on the Program Memory buses They are controlled by one set of banked
165. ocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 11 Serial Communications Interface 1 Enable SCI1 Bit 5 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 12 Serial Communications Interface 0 Enable SCI0 Bit 4 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 13 Serial Peripheral Interface 1 Enable SPI1 Bit 3 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 56F8366 Technical Data Rev 7 Freescale Semiconductor 129 Preliminary 6 5 9 14 Serial Peripheral Interface 0 Enable SPI0 Bit 2 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 15 Pulse Width Modulator B Enable PWMB 1 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 16 Pulse Width Modulator A Enable PWMA 0 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral
166. of the ADC inputs to monitor the on chip temperature e Quad Timer Inthe 56F8366 four dedicated general purpose Quad Timers totaling three dedicated pins Timer C with one pin and Timer D with two pins Inthe 56F8166 two Quad Timers Timer A and Timer C both work in conjunction with GPIO e Optional On Chip Regulator e Upto two FlexCAN CAN Version 2 0 B compliant modules with 2 pin port for transmit and receive 56F8366 Technical Data Rev 7 6 Freescale Semiconductor Preliminary Device Description e Two Serial Communication Interfaces SCIs each with two pins or four additional GPIO lines e Up to two Serial Peripheral Interfaces SPIs both with configurable 4 pin port or eight additional GPIO lines In the 56F8366 SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B In the 56F8166 SPI1 can alternately be used only as GPIO e Computer Operating Properly COP Watchdog timer e Two dedicated external interrupt pins e 62 General Purpose I O GPIO pins e External reset input pin for hardware reset External reset output pin for system reset Integrated Low Voltage Interrupt module e JTAG Enhanced On Chip Emulation OnCE for unobtrusive processor speed independent real time debugging e Software programmable Phase Lock Loop PLL based frequency synthesizer for the core clock 1 1 5 Energy Information e Fabricated in high density CMOS with 5V tolerant TTL compatible digital inpu
167. only by the Power On Reset POR It has no part specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources RESET pin software reset and COP reset 6 5 4 Most Significant Half of JTAG ID SIM_MSH_ID This read only register displays the most significant half of the JTAG ID for the chip This register reads 01D6 Base 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Read 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 RESET 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 Figure 6 6 Most Significant Half of JTAG ID SIM_MSH_ID 6 5 5 Least Significant Half of JTAG ID SIM_LSH_ID This read only register displays the least significant half of the JTAG ID for the chip This register reads DOID Base 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 RESET 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 Figure 6 7 Least Significant Half of JTAG ID SIM_LSH_ID 6 5 6 SIM Pull up Disable Register SIM_PUDR Most of the pins on the chip have on chip pull up resistors Pins which can operate as GPIO can have these resistors disabled via the GPIO function Non GPIO pins can have their pull ups disabled by setting the appropriate bit in this register Disabling pull ups is done on a peripheral by peripheral basis for pins not muxed with GPIO Each bit in the
168. ontents Continued Peripheral eae See oe Interrupt Function PLL 21 0 2 P 2A PLL FM 22 0 2 P 2C FM Access Error Interrupt FM 23 0 2 P 2E FM Command Complete FM 24 0 2 P 30 FM Command data and address Buffers Empty Reserved FLEXCAN 26 0 2 P 34 FLEXCAN Bus Off FLEXCAN 27 0 2 P 36 FLEXCAN Error FLEXCAN 28 0 2 P 38 FLEXCAN Wake Up FLEXCAN 29 0 2 P 3A FLEXCAN Message Buffer Interrupt GPIOF 30 0 2 P 3C GPIO F GPIOE 31 0 2 P 3E GPIO E GPIOD 32 0 2 P 40 GPIO D GPIOC 33 0 2 P 42 GPIO C GPIOB 34 0 2 P 44 GPIO B GPIOA 35 0 2 P 46 GPIO A Reserved SPI1 38 0 2 P 4C SPI 1 Receiver Full SPI 39 0 2 P 4E SPI 1 Transmitter Empty SPIO 40 0 2 P 50 SPI 0 Receiver Full SPIO 41 0 2 P 52 SPI 0 Transmitter Empty SCl1 42 0 2 P 54 SCI 1 Transmitter Empty SCI1 43 0 2 P 56 SCI 1 Transmitter Idle Reserved SCl1 45 0 2 P 5A SCI 1 Receiver Error SCI1 46 0 2 P 5C SCI 1 Receiver Full DEC1 47 0 2 P 5E Quadrature Decoder 1 Home Switch or Watchdog DEC1 48 0 2 P 60 Quadrature Decoder 1 INDEX Pulse DECO 49 0 2 P 62 Quadrature Decoder 0 Home Switch or Watchdog DECO 50 0 2 P 64 Quadrature Decoder 0 INDEX Pulse Reserved TMRD 52 0 2 P 68 Timer D Channel 0 TMRD 53 0 2 P 6A Timer D Channel 1 TMRD 54 0 2 P 6C Timer D Channel 2 TMRD 55 0 2 P 6E Timer D Channel 3 56F
169. or that level Within a given priority level zero is the highest priority while number 85 is the lowest 5 3 1 Normal Interrupt Handling Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority an interrupt vector address is generated Normal interrupt handling concatenates the VBA and the vector number to determine the vector address In this way an offset is generated into the vector table for each interrupt 5 3 2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced The following tables define the nesting requirements for each priority level Table 5 1 Interrupt Mask Bit Definition sR 9 sR 8 Permitted Exceptions Masked Exceptions 0 0 Priorities 0 1 2 3 None 0 1 Priorities 1 2 3 Priority O 1 0 Priorities 2 3 Priorities 0 1 1 1 Priority 3 Priorities 0 1 2 1 Core status register bits indicating current interrupt mask within the core 56F8366 Technical Data Rev 7 Freescale Semiconductor 83 Preliminary Table 5 2 Interrupt Priority Encoding 00 No Interrupt or SWILP Priorities 0 1 2 3 01 Priority O Priorities 1 2 3 10 Priority 1 Priorities 2 3 11 Priorities 2 or 3 Priority 3 1 See IPIC field definition in Part 5 6 30 2 5 3 3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Re
170. ould create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part La so freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 2009 All rights reserved MC56F8366 Rev 7 11 2009
171. ow profile Quad Flat Pack LQFP Figure 11 1 shows the package outline for the LQFP Figure 11 3 shows the mechanical parameters for this package and Table 11 1 lists the pin out for the 144 pin LQFP a oo 00 Qoo 3 oe Sw xX 222 N o WWQQQOQ FELE PETRER ETETEA AEE lvirzaaz2niiiina oaos zs RERE oooi Y O Orientation Mark DD_IO ANB4 Vpp2 ae E ANB3 CLKO Pin 4 109 ANB2 TXDO In ANBI RXDO ANBO de Vssa_ADC H yv MISO1 I Neo aa ae VREFP A2 VREFMID A3 VREFN VREFLO AS ANA7 Voap4 ANA6 Vop_lo ANA5 A6 E ANA4 pe ANA3 ANA2 A9 E ANA1 A10 C ANAO A11 CLKMODE A12 LH RESET Ata RSTO A14 Vpp_10 a Vcap3 ss TO EXTAL a E
172. p Select Option Register 2 CSOR 3 B Chip Select Option Register 3 CSOR 4 C Chip Select Option Register 4 CSOR 5 D Chip Select Option Register 5 CSOR 6 E Chip Select Option Register 6 CSOR 7 F Chip Select Option Register 7 CSTC 0 10 Chip Select Timing Control Register 0 CSTC 1 11 Chip Select Timing Control Register 1 CSTC 2 12 Chip Select Timing Control Register 2 CSTC 3 13 Chip Select Timing Control Register 3 CSTC 4 14 Chip Select Timing Control Register 4 CSTC 5 15 Chip Select Timing Control Register 5 CSTC 6 16 Chip Select Timing Control Register 6 CSTC 7 17 Chip Select Timing Control Register 7 BCR 18 Bus Control Register 0x016B sets the default number of wait states to 11 for both read and write accesses Table 4 11 Quad Timer A Registers Address Map TMRA_BASE 00 F040 Register Acronym Address Offset Register Description TMRAO_CMP1 0 Compare Register 1 TMRAO_CMP2 1 Compare Register 2 TMRAO_CAP 2 Capture Register TMRAO_LOAD 3 Load Register TMRAO_HOLD 4 Hold Register TMRAO_CNTR 5 Counter Register TMRAO_CTRL 6 Control Register TMRAO_SCR 7 Status and Control Register 56F8366 Technical Data Rev 7 52 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 11 Quad Timer A Registers Address Map Continued TMRA_BASE 00 F040
173. p pull up resistor To deactivate the internal pull up resistor set the JTAG bit in the SIM_PUDR register Note Always tie the TMS pin to Vpp through a 2 2K resistor TDI 123 Schmitt Input Test Data Input This input pin provides a serial input data Input pulled high stream to the JTAG EOnCE port It is sampled on the rising edge internally of TCK and has an on chip pull up resistor To deactivate the internal pull up resistor set the JTAG bit in the SIM_PUDR register TDO 124 Output In reset Test Data Output This tri stateable output pin provides a serial output is output data stream from the JTAG EOnCE port It is driven in the disabled shift IR and shift DR controller states and changes on the falling pull up is edge of TCK enabled 56F8366 Technical Data Rev 7 Freescale Semiconductor 27 Preliminary Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset TRST 120 Schmitt Input Test Reset As an input a low signal on this pin provides a reset Input pulled high signal to the JTAG TAP controller To ensure complete hardware internally reset TRST should be asserted whenever RESET is asserted The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG EOnCE module must not be reset In this case assert RESET but do not assert TRST To
174. parator Status and Control Register Table 4 15 Pulse Width Modulator A Registers Address Map PWMA_BASE 00 F140 PWMA is NOT available in the 56F8166 device Register Acronym Address Offset Register Description PWMA_PMCTL 0 Control Register PWMA_PMFCTL 1 Fault Control Register PWMA_PMFSA 2 Fault Status Acknowledge Register PWMA_PMOUT 3 Output Control Register PWMA_PMCNT 4 Counter Register PWMA_PWMCM 5 Counter Modulo Register PWMA_PWMVALO 6 Value Register 0 PWMA_PWMVAL1 7 Value Register 1 PWMA_PWMVAL2 8 Value Register 2 PWMA_PWMVAL3 9 Value Register 3 PWMA_PWMVAL4 A Value Register 4 PWMA_PWMVAL5 B Value Register 5 PWMA_PMDEADTM C Dead Time Register PWMA_PMDISMAP1 D Disable Mapping Register 1 PWMA_PMDISMAP2 E Disable Mapping Register 2 PWMA_PMCFG F Configure Register PWMA_PMCCR 10 Channel Control Register PWMA_PMPORT 11 Port Register PWMA_PMICCR 12 PWM Internal Correction Control Register 56F8366 Technical Data Rev 7 Freescale Semiconductor 59 Preliminary Table 4 16 Pulse Width Modulator B Registers Address Map PWMB_BASE 00 F160 Register Acronym Address Offset Register Description PWMB_PMCTL 0 Control Register PWMB_PMFCTL 1 Fault Control Register PWMB_PMFSA 2 Fault Status Acknowledge Register PWMB_PMOUT 3 Output Control Register PWMB_PMCNT 4 Counter
175. priorities e Illegal Instruction e SW Interrupt 3 HW Stack Overflow e Misaligned Long Word Access e SW Interrupt 2 e SW Interrupt 1 e SW Interrupt 0 e SW Interrupt LP These interrupts are enabled at their fixed priority levels Part 6 System Integration Module SIM 6 1 Overview The SIM module is a system catchall for the glue logic that ties together the system on chip It controls distribution of resets and clocks and provides a number of control features The system integration module is responsible for the following functions e Reset sequencing e Clock generation amp distribution e Stop Wait control e Pull up enables for selected peripherals e System status registers e Registers for software access to the JTAG ID of the chip e Enforcing Flash security There are discussed in more detail in the sections that follow 56F8366 Technical Data Rev 7 114 Freescale Semiconductor Preliminary 6 2 Features Features The SIM has the following features 6 3 Flash security feature prevents unauthorized access to code data contained in on chip Flash memory Power saving clock gating for peripheral Three power modes Run Wait Stop to control power utilization Stop mode shuts down the 56800E core system clock peripheral clock and PLL operation Stop mode entry can optionally disable PLL and Oscillator low power vs fast restart must be explicitly done Wait mode shuts down the 56800E core an
176. put as input or output pins GPIOD11 At reset these pins default to ISB functionality ISB2 53 To deactivate the internal pull up resistor clear the appropriate bit GPIOD12 of the GPIOD_PUR register For details see Part 6 5 8 FAULTBO 56 Schmitt Input FAULTBO 3 These four fault input pins are used for disabling Input pull up selected PWMB outputs in cases where fault conditions originate FAULTB1 57 enabled off chip FAULTB2 58 To deactivate the internal pull up resistor set the PWMB bit in the SIM_PUDR register For details see Part 6 5 8 FAULTB3 61 ANAO 88 Input Analog ANAO 3 Analog inputs to ADC A channel 0 Input ANA1 89 ANA2 90 ANA3 91 ANA4 92 Input Analog ANA4 7 Analog inputs to ADC A channel 1 Input ANA5 93 ANA6 94 ANA7 95 VREFH 101 Input Analog VreFH Analog Reference Voltage High VreFH must be less Input than or equal to Vppa_apc VREFP 100 Input Analog Vrerp Vrermip Vrern Internal pins for voltage reference Output Input which are brought off chip so they can be bypassed Connect to a VREFMID 99 Output 0 1uF or low ESR capacitor VREFN 98 VREFLO 97 Input Analog VreFLo Analog Reference Voltage Low This should normally Input be connected to a low noise Vssa 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP
177. r Input 1 0 0 See the Switch Matrix for Inputs to the Timer Quad Decoder table in the 56F8300 Peripheral User Manual Input 2 for the definition of timer inputs based on the Quad Decoder mode configuration Quad Timer Output 1 0 1 Quad Decoder Input 3 SPI input 1 1 See SPI controls for determining the direction qx _ SYS Of each of the SPI pins SPI output 1 1 car ia 1 This applies to the four pins that serve as Quad Decoder Quad Timer SPI GPIOC functions A separate set of control bits is used for each pin 2 Reset configuration 3 Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins 56F8366 Technical Data Rev 7 Freescale Semiconductor 125 Preliminary Two Input Output pins associated with GPIOD can function as GPIO EMI default peripheral or CAN2 NOT available in the 56F8166 device signals GPIO is the default and is enabled disabled via the GPIOD_PER as shown in Figure 6 11 and Table 6 3 When GPIOD 1 0 are programmed to operate as peripheral input output then the choice between EMI and CAN2 inputs outputs is made here in the GPS GPIOD_PER Register GPIO Controlled 0 1 0 Pad Control 1 SIM_ GPS Register EMI Controlled 0 CAN2 Controlled 1 Figure 6 11 Overall Control of GPIOD Pads Using SIM_GPS Control Note CAN2 is NOT available in the 56F8166 device Table 6 3 Control of GPIOD Pads Using SIM_GPS Control
178. r calibration VDCin 2 70V 100 T T T T T Nt Aa me cfi 0 002289 2 E A y Leet before calibration cf 25 591943 4 50 Wh ge Ef A Pam Me H i pa A A e 4 N 7 o Pi a i K _ pe el a NV uo o Z v 0 i 2 3 3 CN Q after calibration k 50 O percent reduction of range of error 0 4 mean before cal 31 8 mean after cal 0 3 Figure 10 23 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC 0 60V and 2 70V Note The absolute error data shown in the graphs above reflects the effects of both gain error and offset error The data was taken on 25 parts five each from four processing corner lots as well as five from one nominally processed lot each at three temperatures 40 C 27 C and 150 C giving the 75 data points shown above for two input DC voltages 0 60V and 2 70V The data indicates that for the given population of parts calibration significantly reduced by as much as 24 the collective variation spread of the absolute error of the population It also significantly reduced by as much as 38 the mean average of the absolute error and thereby brought it significantly closer to the ideal value of zero Although not guaranteed it is believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes 10 17 Equivalent Circuit for ADC Inp
179. r components on the board and board thermal resistance 6 See Part 12 1 for more details on thermal design considerations 7 TJ Junction temperature TA Ambient temperature 56F8366 Technical Data Rev 7 Freescale Semiconductor 145 Preliminary Note The 56F8166 device is guaranteed to 40MHz and specified to meed Industrial requirements only CAN is NOT available on the 56F 8166 device Table 10 4 Recommended Operating Conditions VREFLO OV Vss Vssa apc OV Vopa Vopa anc VppA_osc_ PLL Characteristic Symbol Notes Min Typ Max Unit Supply voltage Vpp_Io 3 3 3 3 6 V ADC Supply Voltage Vopa apc VREFH Must be less than or 3 3 3 3 6 V VREFH equal to VDDa_ADC Oscillator PLL Supply Voltage VpDA osc 3 3 3 3 6 V _ PLL Internal Logic Core Supply Voltage Von core OCR_DIS is High 2 25 2 5 2 75 V Device Clock Frequency FSYSCLK 0 60 MHz Input High Voltage digital VIN Pin Groups 1 2 5 6 9 10 2 5 5 Input High Voltage analog VIHA Pin Group 13 2 Vppato 3 Input High Voltage XTAL EXTAL ViHc Pin Group 11 Vopa 0 8 Vppa 0 3 XTAL is not driven by an external clock Input high voltage XTAL EXTAL ViHc Pin Group 11 2 Vopa 0 3 V XTAL is driven by an external clock Input Low Voltage Vi Pin Groups 1 2 5 6 9 10 0 3 0 8 V 11 13 Output High Source Current loH Pin Groups 1 2 3 4 mA Von 2 4V V i
180. ram Map Note Data Flash and Program RAM are NOT available on the 56F8166 device Table 4 1 Chip Memory Configurations On Chip Memory 56F8366 56F8166 Use Restrictions Program Flash 512KB 512KB Erase Program via Flash interface unit and word writes to CDBW Data Flash 32KB Erase Program via Flash interface unit and word writes to CDBW Data Flash can be read via either CDBR or XDB2 but not by both simultaneously Program RAM 4KB None Data RAM 32KB 32KB None Program Boot Flash 32KB 32KB Erase Program via Flash Interface unit and word to CDBW 4 2 Program Map The operating mode control bits MA and MB in the Operating Mode Register OMR control the Program memory map At reset these bits are set as indicated in Table 4 2 Table 4 4 shows the memory map configurations that are possible at reset After reset the OMR MA bit can be changed and will have an effect on the P space memory map as shown in Table 4 3 Changing the OMR MB bit will have no effect Table 4 2 OMR MB MA Value at Reset OMR MB OMR MA Flash Secured i i ie EXTBOOT Pin Chip Operating Mode State 0 0 Mode 0 Internal Boot EMI is configured to use 16 address lines Flash Memory is secured external P space is not allowed the EOnCE is disabled 0 1 Not valid cannot boot externally if the Flash is secured and will actually configure to 00 state 1 0 Mode 0 Internal Boot EMI is configured to use 16 ad
181. rated watchdog timer in the Quadrature Decoder can be programmed with a time out value to alert when no shaft motion is detected Each input is filtered to ensure only true transitions are recorded This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces SCIs two Serial Peripheral Interfaces SPIs and four Quad Timers Any of these interfaces can be used as General Purpose Input Outputs GPIOs if that function is not required Two Flex Controller Area Network FlexCAN interfaces CAN Version 2 0 B compliant and an internal interrupt controller are included on the 56F8366 1 2 2 56F8166 Features The 56F8166 hybrid controller includes 512KB of Program Flash programmable through the JTAG port with 32KB of Data RAM It also supports program execution from external memory A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field programmable software routines that can be used to program the main Program Flash memory area which can be independently 56F8366 Technical Data Rev 7 8 Freescale Semiconductor Preliminary Award Winning Development Environment bulk erased or erased in pages Program Flash page erase size is 1KB Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased A key application specific feature of the 56F8166 is the inclusion of one Pulse Width Modulator PWM module
182. register see Figure 6 8 corresponds to a functional group of pins See Table 2 2 to identify which pins can deactivate the internal pull up resistor Base 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nead 0 wma can EML RESET ira xBoor Pwme pwmao Ll errar a ras O y El Write ada EE PA RESET o 0 0 0 0 0 0 0 0 0 o lo o 0 0 0 Figure 6 8 SIM Pull up Disable Register SIM_PUDR 56F8366 Technical Data Rev 7 Freescale Semiconductor 121 Preliminary 6 5 6 1 Reserved Bit 15 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 6 2 PWMA1 Bit 14 This bit controls the pull up resistors on the FAULTA3 pin 6 5 6 3 CAN Bit 13 This bit controls the pull up resistors on the CAN_RX pin 6 5 6 4 EMI_MODE Bit 12 This bit controls the pull up resistors on the EMI MODE pin 6 5 6 5 RESET Bit 11 This bit controls the pull up resistors on the RESET pin 6 5 6 6 IRQ Bit 10 This bit controls the pull up resistors on the IRQA and IRQB pins 6 5 6 7 XBOOT Bit 9 This bit controls the pull up resistors on the EXTBOOT pin Note In this package this input pin is double bonded with the adjacent Vgg pin and this bit should be changed to a in order to reduce power consumption 6 5 6 8 PWMB Bit 8 This bit controls the pull up resistors on the FAULTBO FAULTB1 FAULTB2 and FAULTB3 pins 6 5 6 9 PW
183. reserved or not implemented The bits are read as 1 and cannot be modified by writing 5 6 23 2 IRQ Pending PENDING Bits 81 85 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 85 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 24 Reserved Base 17 5 6 25 Reserved Base 18 5 6 26 Reserved Base 19 5 6 27 Reserved Base 1A 56F8366 Technical Data Rev 7 110 Freescale Semiconductor Preliminary Register Descriptions 5 6 28 Reserved Base 1B 5 6 29 Reserved Base 1C 5 6 30 ITCN Control Register ICTL Base 1D 15 14 te ZA a4 OR 9 8 G 5 4 3 2 1 0 Read INT IPIC VAB ane IRQB STATE IRQA STATE ROB ROA Write EDG EDG RESET 0 0 0 1pojojpofojojo 0 1 1 1 0 0 Figure 5 26 ITCN Control Register ICTL 5 6 30 1 Interrupt INT Bit 15 This read only bit reflects the state of the interrupt to the 56800E core e 0 No interrupt is being sent to the 56800E core 1 Ahn interrupt is being sent to the 56800E core 5 6 30 2 Interrupt Priority Level IPIC Bits 14 13 These read only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken This field is only updated when the 56800E core jumps to a new interrupt service routine
184. riority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 3 Timer B Channel 2 Interrupt Priority Level TMRB2 IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 4 Timer B Channel 1 Interrupt Priority Level TMRB1 IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 5 Timer B Channel 0 Interrupt Priority Level TMRBO IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 100 Freescale Semiconductor Preliminary Register Descriptions 5 6 8 6 Timer C Channel 3 Interrupt Priority Level TMRC3 IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ
185. riority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 Interrupt Priority Register 6 IPR6 Base 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRCO IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRDO IPL Es pa en Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 9 Interrupt Priority Register 6 IPR6 5 6 7 1 Timer C Channel 0 Interrupt Priority Level TMRCO IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freescale Semiconductor 97 Preliminary 5 6 7 2 Timer D Channel 3 Interrupt Priority Level TMRD3 IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 3 Timer D Channel 2 Interrupt Priority Level TMRD2 IPL Bits 11 10 This field is used to set the interrupt priority le
186. s enabled in accordance with the method described in the Flash Memory module specification the device will disable external P space accesses restricting code execution to internal memory disable EXTBOOT 1 mode and disable the core EOnCE debug capabilities Normal program execution is otherwise unaffected 7 2 Flash Access Blocking Mechanisms The 56F8366 56F8166 have several operating functional and test modes Effective Flash security must address operating mode selection and anticipate modes in which the on chip Flash can be compromised and read without explicit user permission Methods to block these are outlined in the next subsections 7 2 1 Forced Operating Mode Selection At boot time the SIM determines in which functional modes the device will operate These are e Internal Boot Mode e External Boot Mode e Secure Mode When Flash security is enabled as described in the Flash Memory module specification the device will boot in internal boot mode disable all access to external P space and start executing code from the Boot Flash at address 0x02 0000 This security affords protection only to applications in which the device operates in internal Flash security mode Therefore the security feature cannot be used unless all executing code resides on chip When security is enabled any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored 56F8366 Technical D
187. se entry into Wait mode WAIT DISABLE can then only be changed by resetting the device 11 Same operation as 10 6 5 2 SIM Reset Status Register SIM_RSTSTS Bits in this register are set upon any system reset and are initialized only by a Power On Reset POR A reset other than POR will only set bits in the register bits are not cleared Only software should clear this register Base 1 15 14 13 12 11 10 9 8 7 6 5 4 3 Read COPR EXTR Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 6 4 SIM Reset Status Register SIM_RSTSTS 56F8366 Technical Data Rev 7 Freescale Semiconductor 119 Preliminary 6 5 2 1 Reserved Bits 15 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 2 2 Software Reset SWR Bit 5 When 1 this bit indicates that the previous reset occurred as a result of a software reset write to SW RST bit in the SIM_CONTROL register This bit will be cleared by any hardware reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit will clear it 6 5 2 3 COP Reset COPR Bit 4 When 1 the COPR bit indicates the Computer Operating Properly COP timer generated reset has occurred This bit will be cleared by a Power On Reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit will clear it 6 5 2 4 External Reset EXTR Bit 3 If 1 the EXT
188. set the default state is INDEX1 To deactivate the internal pull up resistor clear bit 2 in the GPIOC_PUR register HOME1 9 Schmitt Input Home Quadrature Decoder 1 HOME input Input pull up enabled TB3 Schmitt TB3 Timer B Channel 3 Input Output SS1 Schmitt SPI 1 Slave Select In the master mode this pin is used to Input arbitrate multiple masters In slave mode this pin is used to select the slave To activate the SPI function set the HOME_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOC3 Schmitt Port C GPIO This GPIO pin can be individually programmed as Input input or an output pin Output In the 56F8366 the default state after reset is HOME1 In the 56F8166 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit 3 in the GPIOC_PUR register 56F8366 Technical Data Rev 7 32 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset PWMAO 62 Output In reset PWMAO 5 These are six PWMA outputs output is PWMA1 64 disabled PWMA2 65 PWMA3 67 PWMA4 68 PWMA5 70 ISAO 113 Schmitt Input ISAO 2 These three input current status pins are used for Input pull up top bottom pulse width correc
189. sitics associated with pure input pins is ignored as it is assumed to be negligible 56F8366 Technical Data Rev 7 170 Freescale Semiconductor Preliminary 56F8366 Package and Pin Out Information Part 11 Packaging 11 1 56F8366 Package and Pin Out Information This section contains package and pin out information for the 56F8366 This device comes in a 144 pin Low profile Quad Flat Pack LQFP Figure 11 1 shows the package outline for the LQFP Figure 11 3 shows the mechanical parameters for this package and Table 11 1 lists the pin out for the 144 pin LQFP ul oo E Segui 252 wk E 2 Jawad 29o 22510_0xl0 Jor oy 2roma 23509 2Y 22 020l8 5 28
190. ssert Register 0 x 0000 GPIOB_IENR 5 Interrupt Enable Register 0 x 0000 GPIOB_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOB_IPR 7 Interrupt Pending Register 0 x 0000 GPIOB_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOB_PPMODE 9 Push Pull Mode Register 0 x OOFF GPIOB_RAWDATA A Raw Data Input Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 31 GPIOC Registers Address Map GPIOC_BASE 00 F310 Register Acronym Address Offset Register Description Reset Value GPIOC_PUR 0 Pull up Enable Register O x O7FF GPIOC_DR 1 Data Register 0 x 0000 GPIOC_DDR 2 Data Direction Register 0 x 0000 GPIOC_PER 3 Peripheral Enable Register O x O7FF GPIOC_IAR 4 Interrupt Assert Register 0 x 0000 GPIOC_IENR 5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR 7 Interrupt Pending Register 0 x 0000 GPIOC_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOC_PPMODE 9 Push Pull Mode Register 0 x O7FF GPIOC_RAWDATA A Raw Data Input Register Table 4 32 GPIOD Registers Address Map GPIOD_BASE 00 F320 Register Acronym Address Offset Register Description Reset Value GPIOD_PUR 0 Pull up Enable Register O x 1FFF GPIOD_DR 1 Data Register 0 x 0000 GPIOD_DDR 2 Data Direction Register 0 x 0000 GPIOD_PER 3
191. st the package case to avoid measurement errors caused by cooling effects of the thermocouple wire When heat sink is used the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material A clearance slot or hole is normally required in the heat sink Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink Because of the experimental difficulties with this technique many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface From this case temperature the junction temperature is determined from the junction to case thermal resistance 12 2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level Use the following list of considerations to assure correct device operation e Provide a low impedance path from the board power supply to each Vpp pin on the device and from the board ground to each Vgg GND pin
192. sted Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan Ofreescale com Asia Pacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 86 10 5879 8000 support asia O freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com RoHS compliant and or Pb free versions of Freescale products have the unctionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp nformation in this document is provided solely to
193. t e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 11 IRQ is priority level 2 5 6 3 4 PLL Loss of Lock Interrupt Priority Level LOCK IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 90 Freescale Semiconductor Preliminary Register Descriptions 5 6 3 5 Low Voltage Detector Interrupt Priority Level LVI IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 6 Reserved Bits 5 4 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 3 7 External IRQ B Interrupt Priority Level IRQB IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 8 External IRQ A Interrupt Priority Level IRQA IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This
194. t Tolerance Trsc 30 minutes output shorted to ground Table 10 10 PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start up time Tps 0 3 0 5 10 ms Resonator Start up time Trs 0 1 0 18 1 ms Min Max Period Variation Try 120 200 ps Peak to Peak Jitter Tpy 175 ps Bias Current IBIAS 1 5 2 mA Quiescent Current power down mode lpp 100 150 uA 10 2 1 Temperature Sensor Note Temperature Sensor is NOT available in the 56F8166 device Table 10 11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit Slope Gain m 7 762 mvV C Room Trim Temp 2 TRT 24 26 28 C Hot Trim Temp Industrial 1 Tyr Res Verena Reri X 25 128 C 12 Hot Trim Temp Automotive Tut 147 150 153 C 56F8366 Technical Data Rev 7 150 Freescale Semiconductor Preliminary AC Electrical Characteristics Table 10 11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit Output Voltage Vtso 1 370 V Vppa_apc 3 3V Ty 0 C Supply Voltage VDDA_ADC 3 0 3 3 3 6 V Supply Current OFF IDD OFF 10 pA Supply Current ON IDD ON 250 pA Accuracy from 40 C to 150 C Tacc 6 7 0 6 7 C Using Vis mT Viso Resolution 51 Res 0 104 C bit T Includes the ADC conversion of the analog Temperature Sens
195. ter FCMB10_ID_LOW 92 Message Buffer 10 ID Low Register FCMB10_DATA 93 Message Buffer 10 Data Register FCMB10_DATA 94 Message Buffer 10 Data Register FCMB10_DATA 95 Message Buffer 10 Data Register FCMB10_ DATA 96 Message Buffer 10 Data Register FCMB11_CONTROL 98 Message Buffer 11 Control Status Register FCMB11_ID_HIGH 99 Message Buffer 11 ID High Register FCMB11_ID_LOW 9A Message Buffer 11 ID Low Register FCMB11_DATA 9B Message Buffer 11 Data Register FCMB11_DATA 9C Message Buffer 11 Data Register FCMB11_DATA 9D Message Buffer 11 Data Register FCMB11_DATA 9E Message Buffer 11 Data Register FCMB12_CONTROL A0 Message Buffer 12 Control Status Register FCMB12_ID_HIGH A1 Message Buffer 12 ID High Register FCMB12_ID_LOW A2 Message Buffer 12 ID Low Register FCMB12_DATA A3 Message Buffer 12 Data Register FCMB12_DATA A4 Message Buffer 12 Data Register FCMB12_DATA A5 Message Buffer 12 Data Register FCMB12_DATA A6 Message Buffer 12 Data Register FCMB13_CONTROL A8 Message Buffer 13 Control Status Register FCMB13_ID_HIGH A9 Message Buffer 13 ID High Register FCMB13_ID_LOW SAA Message Buffer 13 ID Low Register FCMB13_DATA SAB Message Buffer 13 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym
196. ter 5 IPR5 Base 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DEC1_XIRQ DEC1_HIRQ SCI1_RCV SCI1_RERR SCI_TIDL SCI1_XMIT SPIO_XMIT IPL IPL IPL IPL IPL IPL IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 8 Interrupt Priority Register 5 IPR5 5 6 6 1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level DEC1_XIRQ IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8366 Technical Data Rev 7 Freescale Semiconductor 95 Preliminary 5 6 6 2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level DEC1_HIRQ IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 3 SCI 1 Receiver Full Interrupt Priority Level SCI1_RCV IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IR
197. ter Register TMRA3_CTRL 36 Control Register TMRA3_SCR 37 Status and Control Register TMRA3_CMPLD1 38 Comparator Load Register 1 TMRA3_CMPLD2 39 Comparator Load Register 2 TMRA3_COMSC 3A Comparator Status and Control Register Table 4 12 Quad Timer B Registers Address Map TMRB_BASE 00 F080 Quad Timer B is NOT available in the 56F8166 device Register Acronym Address Offset Register Description TMRBO_CMP1 0 Compare Register 1 TMRBO_CMP2 1 Compare Register 2 TMRBO_CAP 2 Capture Register TMRBO_LOAD 3 Load Register TMRBO_HOLD 4 Hold Register TMRBO_CNTR 5 Counter Register TMRBO_CTRL 6 Control Register TMRBO_SCR 7 Status and Control Register TMRBO_CMPLD1 8 Comparator Load Register 1 TMRBO_CMPLD2 9 Comparator Load Register 2 TMRBO_COMSCR A Comparator Status and Control Register TMRB1_CMP1 10 Compare Register 1 TMRB1_CMP2 11 Compare Register 2 TMRB1_CAP 12 Capture Register TMRB1_LOAD 13 Load Register TMRB1_HOLD 14 Hold Register TMRB1_CNTR 15 Counter Register TMRB1_CTRL 16 Control Register TMRB1_SCR 17 Status and Control Register TMRB1_CMPLD1 18 Comparator Load Register 1 56F8366 Technical Data Rev 7 54 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 12 Quad Timer B Registers Address Map Continued TMRB_BASE 00 F080 Quad Timer B is NOT available in the 56F8166 device R
198. tion SHUTDOWN 4 PLLCR 0 Control Register PLLDB 1 Divide By Register PLLSR 2 Status Register Reserved Shutdown Register OSCTL 5 Oscillator Control Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 67 Table 4 29 GPIOA Registers Address Map GPIOA_BASE 00 F2E0 Register Acronym Address Offset Register Description Reset Value GPIOA_PUR 0 Pull up Enable Register 0 x 3FFF GPIOA_DR 1 Data Register 0 x 0000 GPIOA_DDR 2 Data Direction Register 0 x 0000 GPIOA_PER 3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR 4 Interrupt Assert Register 0 x 0000 GPIOA_IENR 5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOA_IPR 7 Interrupt Pending Register 0 x 0000 GPIOA_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOA_PPMODE 9 Push Pull Mode Register 0 x 3FFF GPIOA_RAWDATA A Raw Data Input Register Table 4 30 GPIOB Registers Address Map GPIOB_BASE 00 F300 Register Acronym Address Offset Register Description Reset Value GPIOB_PUR 0 Pull up Enable Register O x OOFF GPIOB_DR 1 Data Register 0 x 0000 GPIOB_DDR 2 Data Direction Register 0 x 0000 GPIOB_PER 3 Peripheral Enable Register 0 x OOOF for 20 bit EMI address at reset 0 x 0000 for all other cases See Table 4 4 for details GPIOB_IAR 4 Interrupt A
199. tion in complementary channel enabled operation for PWMA GPIOC8 Schmitt Port C GPIO These three GPIO pins can be individually Input programmed as input or output pins GPIOC9 In the 56F8366 these pins default to ISA functionality after reset ISA2 115 In the 56F8166 the default state is not one of the functions offered GPIOC10 and must be reconfigured To deactivate the internal pull up resistor clear the appropriate bit of the GPIOC_PUR register For details see Part 6 5 8 FAULTAO 71 Schmitt Input FAULTAO 2 These three fault input pins are used for disabling Input pull up selected PWMA outputs in cases where fault conditions originate FAULTA1 73 enabled off chip FAULTA2 74 To deactivate the internal pull up resistor set the PVWMAO bit in the SIM_PUDR register For details see Part 6 5 8 PWMBO 34 Output In reset PWMBO 5 Six PWMB output pins output is PWMB1 35 disabled PWMB2 36 PWMB3 39 PWMB4 40 PWMB5 41 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 33 Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset ISBO 50 Schmitt Input ISBO 2 These three input current status pins are used for Input pull up top bottom pulse width correction in complementary channel enabled operation for PWMB GPIOD10 Schmitt Port D GPIO These GPIO pins can be individually programmed In
200. tional to actual position Speed computation capabilities accommodate both fast and slow moving shafts An integrated watchdog timer in the Quadrature Decoder can be programmed with a time out value to alert when no shaft motion is detected Each input is filtered to ensure only true transitions are recorded This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces SCIs two Serial Peripheral Interfaces SPIs and two Quad Timers Any of these interfaces can be used as General Purpose Input Outputs GPIOs if that function is not required An internal interrupt controller is also a part of the 56F8166 1 3 Award Winning Development Environment Processor Expert PE provides a Rapid Application Design RAD tool that combines easy to use component based software application creation with an expert knowledge system The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation compiling and debugging A complete set of evaluation modules EVMs and development system cards will support concurrent engineering Together PE CodeWarrior and EVMs create a complete scalable tools solution for easy fast and efficient development 56F8366 Technical Data Rev 7 Freescale Semiconductor 9 Preliminary 1 4 Architecture Block Diagram Note Features in italics are NOT available in the 56F8166 device and are shaded in the following figures
201. to provide the clock directly to the core This input clock can also be selected as the input clock for the on chip PLL 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary 19 Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset CLKO 3 Output In reset Clock Output This pin outputs a buffered clock signal Using output is the SIM CLKO Select Register SIM_CLKOSR this pin can be disabled programmed as any of the following disabled CLK_MSTR system clock IPBus clock oscillator output prescaler clock and postscaler clock Other signals are also available for test purposes See Part 6 5 7 for details AO 138 Output In reset Address Bus AO A5 specify six of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR AO A5 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOA8 Input Port A GPIO These six GPIO pins can be individually Output programmed as input or output pins A1 10 GPIOA9 After reset the default state is Address Bus A2 11 To deactivate the internal pull up resistor set the appropriate GPIOA10 GPIO bit in the GPIOA_PUR re
202. trol the clock divider circuit within the FM module This divider FM_CLKDIV 6 0 is used to control the period of the clock used for timed events in the FM erase algorithm This register must be set with appropriate values before the lockout sequence can begin Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value The value of the JTAG FM_CLKDIV 6 0 will replace the value of the FM register FMCLKOD that divides down the system clock for timed events as illustrated in Figure 7 1 FM_CLKDIV 6 will map to the PRDIVS8 bit and FM CLKDIV 5 0 will map to the DIV 5 0 bits The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz 200kHz The Writing the FMCLKD Register section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values 56F8366 Technical Data Rev 7 Freescale Semiconductor 135 Preliminary Flash Memory SYS_CLK input DIVIDER 2 clock 7 FMCLKD gt 7 FM_CLKDIV T TA AAS FM_ERASE A Figure 7 1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow EXAMPLE 1 If the system clock is the 8MHz crystal frequency because the PLL has not been set up the input clock will be below 12 8MHz so PRDIV8 FM_CLKDIV 6 0 Using the following equation yields a
203. ts e On board 3 3V down to 2 6V voltage regulator for powering internal logic and memories can be disabled e On chip regulators for digital and analog circuitry to lower cost and reduce noise e Wait and Stop modes available e ADC smart power management Each peripheral can be individually disabled to save power 1 2 Device Description The 56F8366 and 56F8166 are members of the 56800E core based family of controllers Each combines on a single chip the processing power of a Digital Signal Processor DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost effective solution Because of its low cost configuration flexibility and compact program code the 56F8366 and 56F8166 are well suited for many applications The devices include many peripherals that are especially useful for motion control smart appliances steppers encoders tachometers limit switches power supply and control automotive control 56F8366 only engine management noise suppression remote utility metering industrial control for power lighting and automation applications The 56800E core is based on a Harvard style architecture consisting of three execution units operating in parallel allowing as many as six operations per instruction cycle The MCU style programming model and optimized instruction set allow straightforward generation of efficient compact DSP and control code The instruction set is also highly effic
204. uffer 7 ID High Register FCMB7_ID_LOW 7A Message Buffer 7 ID Low Register FCMB7_DATA 7B Message Buffer 7 Data Register FCMB7_DATA 7C Message Buffer 7 Data Register FCMB7_DATA 7D Message Buffer 7 Data Register FCMB7_DATA 7E Message Buffer 7 Data Register Reserved FCMB8_CONTROL 80 Message Buffer 8 Control Status Register FCMB8_ID_HIGH 81 Message Buffer 8 ID High Register FCMB8_ID_LOW 82 Message Buffer 8 ID Low Register FCMB8_DATA 83 Message Buffer 8 Data Register FCMB8_DATA 84 Message Buffer 8 Data Register FCMB8_DATA 85 Message Buffer 8 Data Register FCMB8_DATA 86 Message Buffer 8 Data Register Reserved FCMB9 CONTROL 88 Message Buffer 9 Control Status Register FCMB9_ID_HIGH 89 Message Buffer 9 ID High Register FCMB9_ID_LOW 8A Message Buffer 9 ID Low Register FCMB9_DATA 8B Message Buffer 9 Data Register FCMB9_DATA 8C Message Buffer 9 Data Register 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8166 device Register Acronym Address Offset Register Description FCMB9_DATA 8D Message Buffer 9 Data Register FCMB9_DATA 8E Message Buffer 9 Data Register FCMB10_CONTROL 90 Message Buffer 10 Control Status Register FCMB10_ID_HIGH 91 Message Buffer 10 ID High Regis
205. ull up When RESET is asserted low the device is initialized and placed enabled in the reset state A Schmitt trigger input is used for noise immunity When the RESET pin is deasserted the initial chip operating mode is latched from the EXTBOOT pin The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks To ensure complete hardware reset RESET and TRST should be asserted together The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG EOnCE module must not be reset In this case assert RESET but do not assert TRST Note The internal Power On Reset will assert on initial power up To deactivate the internal pull up resistor set the RESET bit in the SIM_PUDR register See Part 6 5 6 for details RSTO 85 Output Output Reset Output This output reflects the internal reset state of the chip 56F8366 Technical Data Rev 7 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 144 Pin LQFP State Signal Name Pin No Type During Signal Description Reset EXTBOOT 112 Schmitt Input External Boot This input is tied to Vpp to force the device to Input pull up boot from off chip memory assuming that the on chip Flash enabled memory is not in a secure state Otherwise it is tied to ground For details see Table 4 4 Not
206. umber of each IRQ refer to Table 4 5 5 6 16 Fast Interrupt 1 Vector Address Low Register FIVAL1 Base F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read FAST INTERRUPT 1 Write VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 18 Fast Interrupt 1 Vector Address Low Register FIVAL1 5 6 16 1 Fast Interrupt 1 Vector Address Low FIVAL1 Bits 15 0 The lower 16 bits of vector address are used for Fast Interrupt 1 This register is combined with FIVAH1 to form the 21 bit vector address for Fast Interrupt 1 defined in the FIM register 56F8366 Technical Data Rev 7 Freescale Semiconductor 107 Preliminary 5 6 17 Fast Interrupt 1 Vector Address High Register FIVAH1 Base 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 19 Fast Interrupt 1 Vector Address High Register FIVAH1 5 6 17 1 Reserved Bits 15 5 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 17 2 Fast Interrupt 1 Vector Address High FIVAH1 Bits 4 0 The upper five bits of the vector address are used for Fast Interrupt 1 This register is combined with FIVALI to form the 21 bit vector address for Fast Interrupt 1 defined in the FIM1 register 5 6 18 IRQ Pending 0 Register IRQPO0 Base 11 15 1
207. upts must be set to priority level 2 Unexpected results will occur if a fast interrupt vector is set to any other priority Fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt Fast Interrupt 0 has priority over Fast Interrupt 1 To determine the vector number of each IRQ refer to Table 4 5 5 6 13 Fast Interrupt 0 Vector Address Low Register FIVALO Base C 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read Write FAST INTERRUPT 0 VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 15 Fast Interrupt 0 Vector Address Low Register FIVALO 5 6 13 1 Fast Interrupt 0 Vector Address Low FIVALO Bits 15 0 The lower 16 bits of the vector address used for Fast Interrupt 0 This register is combined with FIVAHO to form the 21 bit vector address for Fast Interrupt 0 defined in the FIMO register 5 6 14 Fast Interrupt 0 Vector Address High Register FIVAHO Base D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 o o o 0 0 o 0 o 0 0 FAST INTERRUPT 0 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 16 Fast Interrupt 0 Vector Address High Register FIVAHO 56F8366 Technical Data Rev 7 106 Freescale Semiconductor Preliminary Register Descriptions 5 6
208. uts Figure 10 24 illustrates the ADC input circuit during sample and hold S1 and S2 are always open closed at the same time that S3 is closed open When S1 S2 are closed amp S3 is open one input of the sample and hold circuit moves to VerrH Very 2 While the other charges to the analog input voltage When the 56F8366 Technical Data Rev 7 168 Freescale Semiconductor Preliminary Power Consumption switches are flipped the charge on C1 and C2 are averaged via S3 with the result that a single ended analog input is switched to a differential voltage centered about Verry VreFH 2 The switches switch on every cycle of the ADC clock open one half ADC clock closed one half ADC clock Note that there are additional capacitances associated with the analog input pad routing etc but these do not filter into the S H output voltage as S1 provides isolation during the charge sharing phase One aspect of this circuit is that there is an on going input current which is a function of the analog input voltage Vppp and the ADC clock frequency Analog Input 6 Si 4 ME 1 S3 S H VREFH VREFLO 2 C1 C2 1pF Parasitic capacitance due to package pin to pin and pin to package base coupling 1 8pf Parasitic capacitance due to the chip bond pad ESD protection devices and signal routing 2 04pf Equivalent resistance for the ESD isolation resistor and the channel select mux 500 ohms
209. ve P 0F FFFF The higher bit address GPIO and or chip se lects pins must be reconfigured before this external memory is accessible 7 Booting from this external address allows prototyping of the internal Boot Flash 8 Two independent program flash blocks allow one to be programmed erased while executing from another Each block must have its own mass erase 56F8366 Technical Data Rev 7 If Flash Security Mode is enabled EXTBOOT Mode 1 cannot be used See Security Features Part 7 This mode provides maximum compatibility with 56F80x parts while operating externally EMI_MODE 0 when EMI_MODE pin is tied to ground at boot up EMI_MODE 1 when EMI_MODE pin is tied to Vpp at boot up Not accessible in reset configuration since the address is above P 00 FFFF The higher bit address GPIO and or chip se Freescale Semiconductor Preliminary 43 4 3 Interrupt Vector Table Table 4 5 provides the reset and interrupt priority structure including on chip peripherals The table is organized with higher priority vectors at the top and lower priority interrupts lower in the table The priority of an interrupt can be assigned to different levels as indicated allowing some control over interrupt priorities All level 3 interrupts will be serviced before level 2 and so on For a selected priority level the lowest vector number has the highest priority The location of the vector table is determined by the Vector
210. vector address as provided in Table 4 4 Additional pins must be configured as address or chip select signals to access addresses at P 10 and above 56F8366 Technical Data Rev 7 42 Freescale Semiconductor Preliminary Program Map Note Program RAM is NOT available on the 56F8166 device Table 4 4 Program Memory Map at Reset Mode 0 MA 0 Mode 11 MA 1 Begin End Internal Boot External Boot Address Internal Boot EMI_MODE 02 EMI_MODE 14 16 Bit External Address Bus 16 Bit External Address Bus 20 Bit External Address Bus P 1F FFFF External Program Memory External Program Memory External Program Memory P 10 0000 P 0F FFFF P 05 0000 P 04 FFFF On Chip Program RAM P 04 F800 4KB P 04 F7FF Reserved P 04 4000 92KB P 04 3FFF Boot Flash Boot Flash P 04 0000 32KB 32KB External Program Memory COP Reset Address 04 0002 Not Used for Boot in this Mode COP Reset Address 04 00027 Boot Location 04 0000 Boot Location 04 00007 P 03 FFFF Internal Program Flash Internal Program Flash P 02 0000 256KB 256KB P 01 FFFF Internal Program Flash P 01 0000 128KB Internal Program Flash P 00 FFFF 256KB External Program Memory P 00 0000 COP Reset Address 00 0002 Boot Location 00 0000 aR WN lects pins must be reconfigured before this external memory is accessible 6 Not accessible in reset configuration since the address is abo
211. vel for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 4 Timer D Channel 1 Interrupt Priority Level TMRD1 IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 5 Timer D Channel 0 Interrupt Priority Level TMRDO IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 6 Reserved Bits 5 4 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 56F8366 Technical Data Rev 7 98 Freescale Semiconductor Preliminary Register Descriptions 5 6 7 7 Quadrature Decoder 0 INDEX Pulse Interrupt Priority Level DECO_XIRQ IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11

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