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uPSD34x Turbo Plus Series Fast Turbo 8032 MCU with

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1. 105 I2C Data Shift Register 51 107 Address Register 61 107 2 START Sample Setting 515 108 Operating 111 SPI SYNCHRONOUS PERIPHERAL 115 SPI Bus Features and Communication Flow 116 Full Duplex 116 Bus Level Activity a dec 116 SPISFR Registers t ee e RIA 118 SPI Configuration GG 119 Dynamic Control 119 USB INTERFACE is 2 2 AE 123 Basic USB Concepts ouo ex Rex IRE A MEM ee ee ee 124 Types of Transfers Phe Rei aera 127 Endpoint FIEOS vau etuer UNE rures xs eae iesu 129 USB Registers cuu IE rule Ran REA Ene Rt 132 Typical Connection to USB 150
2. Flash Secondary Mode on Port A Flash Main Flash Main Flash not used not used Note 1 Default value of Bits 1 2 3 and 4 is loaded from Non Volatile setting as specified from PSDsoft Express upon any reset or power up condition The default value of these bits can be overridden by 8032 at run time 2 Default value of Bit 7 is zero upon any reset condition Figure 70 VM Register Control of Memories CS 8032 Address CSBOOTO CSBOOT3 Main Flash Memory Flash 53 Other PLD Inputs Memory WR OE VM REG BIT 4 VM REG BIT 3 VM REG BIT 2 VM REG BIT 1 Secondary 110455 174 264 1572 Figure 71 VM Register Example Correspondin 8032 Address 53 Other PLD Inputs VM Register CSBOOTO CSBOOT3 Main Flash Secondary uPSD34xx PSD MODULE g to Memory Map Example CS Memory Flash cs Memory WR OE WR OE O A110456 PSD Module Data Bus Width The PSD Module functions as an 8 bit device to the MCU Module except when the PFQ is fetching instructions from the Flash memory When PSEN is active the PSD Module always drives 16 bit data out onto the bus The Flash memories are 16 bit wide when it is in Program Memory space and are 8 bit wide when it Table 105 Data Width in Different Bus Cycles is in the Data Space When the Flash memory is configured in both Program Space
3. 909 x2 2 gt 5X SS5q0qg 0 0 OOOX KEE lt 8r amp gt gt Eo Oo mole lt A wn 5 tc x 109696 Note 1 For 5V applications Vpp must be connected to 5 0V source For 3 3V applications must be connected to 3 3V source 2 These signals can be used on one of two different ports Port 1 or Port 4 for flexibility Default is Port1 3 AVngr and 3 3V AVcc are shared in the 52 pin package only ADC channels must use 3 3V as AVper for the 52 pin package 9 264 uPSD34xx PIN DESCRIPTIONS Figure 4 TQFP80 Connections 79 P3 2 EXINTO TGO 77 P3 1 TXDO 1 1 75 P3 0 RXDO 64 P1 7 SPISEL ADC7 63 PSEN 61 P1 6 SPITXD ADC6 68 RESET IN pt 72 AVcc H 70 Vier PD2 CSI 1 P1 5 SPIRXD 9 ADC5 P3 3 TG1 EXINT1 2 P1 4 SPICLK 3 ADC4 PD1 CLKIN 3 P1 3 TXD1 IrDA ADC3 ALE 4 NC PC7 5 P1 2 RXD1 IrDA ADC2 JTAG TDO 6 NC JTAG TDI 7 P1 1 T2X 9 ADC1 DEBUG 8 NC PC4 TERR 9 P1 0 T2 9 ADCO 3 3V Voc 10 NC USB4 11 12 XTAL2 GND 13 XTAL1 USB 14 MCU AD7 PC3 TSTAT 15 P3 7 SCL 2 16 MCU AD6 JTAG TCK 17 P3 6 SDA SPISEL 2 PCACLK1 P4 7 18 MCU AD5 SPITXD 2 TCM5 P4 6 19 P3 5 C1 JTAG TMS 20 MCU AD4 SPIRXD TCM4 P4 5 23 CL SPICLKO TCM3 P4 4 25 CL TXD1 IrDA 2 PCACLKO P4 3
4. Note 1 For each bit 1 pin drive type is selected 0 pin drive type is default mode CMOS push pull 2 Default state for register is OOh after reset or power up Table 139 Port D Pin Drive Select Register address csiop offset 17h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 2 3 PD1 N A N A N A N A N A Slew Bate Slew Rate N A Note 1 For each bit 1 pin drive type is selected 0 pin drive type is default mode CMOS push pull 2 Default state for register is OOh after reset or power up 3 Pin is not available on 52 pin uPSD34xx devices Table 140 Port A Enable Out Register address csiop offset OCh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PA7 OE PA6 OE PA5 OE PA4 OE PA3 OE PA2 OE PA1 OE PAO OE Note 1 Port A not available on 52 pin uPSD34xx devices 2 For each bit 1 pin drive is enabled as an output 0 pin drive is off high impedance pin used as input Table 141 Port B Enable Out Register address csiop offset ODh PB7 OE PB6 OE PB5 OE PB4 OE PB3 OE PB2 OE PB1 OE PBO OE Note For each bit 1 pin drive is enabled as an output 0 pin drive is off high impedance pin used as input Table 142 Port C Enable Out Register address csiop offset 1Ah Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7OE N A JTAG N A JTAG 4 PC3 OE PC2OE N A JTAG N A JTAG Note 1 For e
5. QFP A Al a KL Note Drawing is not to scale 3 257 264 uPSD34xx PACKAGE MECHANICAL INFORMATION Table 183 TQFP52 52 lead Plastic Thin Quad Flat Package Mechanical Data CP 0 10 0 004 258 264 uPSD34xx PACKAGE MECHANICAL INFORMATION Figure 115 TQFP80 80 lead Plastic Thin Quad Flat Package Outline QFP A Al a LL Note Drawing is not to scale ky 259 264 uPSD34xx PACKAGE MECHANICAL INFORMATION Table 184 TQFP80 80 lead Plastic Thin Quad Flat Package Mechanical Data Symb X 0 45 zi o n 80 Nd 20 Ne 20 CP 0 08 0 003 260 264 uPSD34xx PART NUMBERING PART NUMBERING Table 185 Ordering Information Scheme Example UPSD 34 3 4 E 40 U 6 T Device Type uPSD Microcontroller PSD Family 34 Turbo Plus core SRAM Size 2 4Kbytes 3 8Kbytes 5 32Kbytes Main Flash Memory Size 2 64Kbytes 3 128Kbytes 4 256Kbytes IP Mix IP Mix USB 2 SPI UART 2 IIDA ADC Supervisor PCA Operating Voltage blank Vcc 4 5 to 5 5V V Vcc 3 0 to 3 6V Speed 40 40MHz Package T 52 pin TQFP U 80 pin TQFP Temperature Range 6 40 to 85 C Shipping Option Tape amp Reel Packing T
6. 96 264 BR3 BR2 BRI BRO 0 0 0 0 115 2 0 0 1 1 19 2 0 1 0 0 14 4 0 1 0 1 12 8 0 1 1 0 9 6 0 1 1 1 72 1 0 0 0 4 8 1 0 0 1 3 6 1 0 1 0 24 1 0 1 1 1 8 uPSD34xx IrDA INTERFACE Pulse Width Selection The IrDA interface has two ways to modulate the standard UART1 serial stream 1 An IrDA data pulse will have a constant pulse width for any bit time regardless of the selected baud rate 2 An IrDA data pulse will have a pulse width that is proportional to the the bit time of the selected baud rate In this case an IrDA data pulse width is 3 16 of its bit time as shown in Figure 40 page 94 The PULSE bit in the SFR named IRDACON de termines which method above will be used According to the IrDA physical layer specification for all baud rates at 115 2k bps and below the minimum data pulse width is 1 41us For a baud rate of 115 2k bps the maximum pulse width 2 23us If a constant pulse width is to be used for all baud rates PULSE bit 0 the ideal general pulse width is 1 63us derived from the bit time of the fastest baud rate 8 68us bit time for 115 2k bps rate multiplied by the proportion 3 16 To produce this fixed data pulse width when the PULSE bit 0 a prescaler is needed to generate an internal reference clock SIRCIk shown in Fig ure 39 page 94 SIRCIk is derived by dividing the oscillator clock frequency fosc using the five bits CDIV 4 0 in the SFR named IRDACO
7. Y A CTRL and Data SETUP Command Buffer 8 bytes CTRL and Data Basic USB Concepts The Universal Serial Bus USB is more complex than the standard serial port and requires familiar ity with the specification to fully understand how to use the USB peripheral in the uPSD34xx The USB specification is available on the Internet at http www usb org Some basic concepts will be presented in this section but knowledge of the USB specification is required In a USB system there is only one master and the master is the host computer The host controls all activity on the bus and devices respond to re quests from the host The only exception is when a device has been put into a low power suspend mode by the host In this case the device can sig nal a remote wakeup Outside of that exception all activity is controlled and initiated by the host The host centric model versus a peer to peer model provides the best way to develop low cost periph erals by keeping the complex control logic on the 124 264 110488 host side uPSD34xx is a peripheral non host device Communication Flow The USB provides a means for communication between host client software and a function on a USB device Func tions can have different requirements for the com munication flow depending on the client software to the USB function interaction With USB the var ious communication
8. RCLK 0 TCLK 0 the baud rates in Modes 1 Rates See Baud Rate Generator and 3 are determined by the Timer 1 overflow rate Mode page 79 and the value of SMOD as follows Mode 1 3 Baud Rate 25MOD 32 x Timer 1 overflow rate Table 49 Commonly Used Baud Rates Generated from Timer 1 Timer 1 UART Mode bitin m value hex Mode 2 Max X X Mode 2 Max X X Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 0 2 Modes 1 or 3 12 0 0 2 Modes 1 or 3 11 0592 0 2 Modes 1 or 3 11 0592 0 2 Modes 1 or 3 0 2 Modes 1 or 3 11 0592 0 0 2 Modes 1 or 3 3 6864 0 0 2 Modes 1 or 3 3 6864 0 0 2 Modes 1 or 3 1 8432 9600 0 0 2 FF Modes 1 or 3 1 8432 4800 0 0 2 FE 86 264 More About UART Mode 0 Refer to the block diagram in Figure 31 page 88 and timing diagram in Figure 32 page 88 Transmission is initiated by any instruction which writes to the SFR named SBUF At the end of a write operation to SBUF a 1 is loaded into the 9th position of the transmit shift register and tells the TX Control unit to begin a transmission Transmis sion begins on the following MCU machine cycle when the SEND signal is active in Figure 32 SEND enables the output of the shift register to the alternate function on the port containing pin RxD and also enables the SHIFT CLOCK signal to the alternate functio
9. 165 Memory 169 PSD Module Data Bus Width 175 Runtime Control Register Definitions 176 PSD Module Detailed 178 PSD Module Reset 224 AC DC PARAMETERS i 34 sian NEXU E 233 MAXIMUM RATING Re oti Aiea et EEG aie tan de ewe dde 235 DC AND AC PARAMETERS 3 220 te aee dx 235 PACKAGE MECHANICAL 257 PART NUMBERING peel Rr rl 261 IMPORTANT NOTES 2 2 Ave RR rade sa e ae meee 262 USB Interrupts with Idle 262 USB Reset Interrupt 262 USB Reset o ruo IIIA lieve kl a ud ex AE Ra te 262 eee 262 Pata Toggle sec c Lm 262 USB FIFO Accessibility 22225 ee A ra RR e P 262 Erroneous Resend of Data 262 IN FIFO Pairing 263
10. Global Enable AI07844 3 43 264 uPSD34xx INTERRUPT SYSTEM Individual Interrupt Sources External Interrupts IntO and Int External in terrupt inputs on pins EXTINTO and EXTINT1 pins 3 2 and 3 3 are either edge triggered or lev el triggered depending on bits ITO and IT1 in the SFR named TCON When an external interrupt is generated from an edge triggered falling edge source the appropri ate flag bit IEO or IE1 is automatically cleared by hardware upon entering the ISR When an external interrupt is generated from a level triggered low level source the appropriate flag bit IEO or IE1 is NOT automatically cleared by hardware Timer 0 and 1 Overflow Interrupt Timer 0 and Timer 1 interrupts are generated by the flag bits TFO and TF1 when there is an overflow condition in the respective Timer Counter register except for Timer 0 in Mode 3 Timer 2 Overflow Interrupt This interrupt is generated to the MCU by a logical OR of flag bits TF2 and EXE2 The ISR must read the flag bits to determine the cause of the interrupt TF2 is set by an overflow of Timer 2 EXE2 is generated by the falling edge of a signal on the external pin T2X pin P1 1 UARTO and UART1 Interrupt Each of the UARTS have identical interrupt structure For each UART a single interrupt is generated to the MCU by the logical OR of the flag bits RI byte received and TI byte transmitted The ISR must rea
11. NOP Note 1 All mnemonics copyrighted lntel Corporation 1980 No Operation 1 byte 1 cycle Table 12 Notes on Instruction Set and Addressing Modes Rn Register RO R7 of the currently selected register bank 8 bit address for internal 8032 DATA SRAM locations 00h 7Fh or SFR registers locations 80h FFh direct Ri 8 bit internal 8032 SRAM locations 00h FFh addressed indirectly through contents of RO or R1 data 8 bit constant included within the instruction 16 16 bit constant included within the instruction addri6 16 bit destination address used by LCALL and LJMP rel Signed two s compliment 8 bit offset byte Direct addressed bit in internal 8032 DATA SRAM locations 20h to 2Fh or in SFR registers 88h 90h 98h A8h BO B8h COh C8h DOh D8h EOh FOh bit 37 264 uPSD34xx DUAL DATA POINTERS DUAL DATA POINTERS XDATA is accessed by the External Direct ad dressing mode which uses a 16 bit address stored in the DPTR Register Traditional 8032 ar chitecture has only one DPTR Register This is a burden when transferring data between two XDA TA locations because it requires heavy use of the working registers to manipulate the source and destination pointers However the uPSD34xx has two data pointers one for storing a source address and the other for storing a destination address These pointers can be configured to automatically incremen
12. SLAdNI 69 sna 1 106602 192 264 Output Macrocell The GPLD has 16 OMCs Ar chitecture of one individual OMC is shown in Fig ure 77 OMCs can be used for internal node feedback buried registers to build shift registers etc or their outputs may be routed to external port pins The user can choose any mixture of OMCs used for buried functions and OMCs used to drive port pins Referring to Figure 77 for each there are na tive product terms available from the AND OR Ar ray to form logic and also borrowed product terms are available if unused from other OMCs The polarity of the final product term output is con trolled by the XOR gate Each OMC can imple ment sequential logic using the flip flop element or combinatorial logic when bypassing the flip flop as selected by the output multiplexer An OMC output can drive a port pin through the OMC Allo cator it can also drive the 8032 data bus and also it can drive a feedback path to the AND OR Array inputs all at the same time Figure 77 Detail of a Single OMC PRODUCT TERMS FROMOTHER OMCs uPSD34xx PSD MODULE The flip flop in each OMC can be synthesized as a D T JK or SR type in PSDsoft Express OMC flip flops are specified using PSDsoft Express in the User Defined Nodes section of the Design Assis tant Each flip flop s clock preset and clear inputs may be driven individually from a product ter
13. Tate 83 UART Operation Modes 83 Serial Port Control 84 UART Baud Rates teaser ee qs Shee 86 More About UART 0 87 More About UART Mode 1 89 More About UART Modes 2 3 91 IrDA INTERFACE ern RR a atte he ae ene 94 Baud Rate Selection ete ie eed Fae fae ae 95 Pulse Width 2 2 2 424 22 0 ERE 97 IC INTERFACE toilet ilo Gots 98 I2C Interface Main Features 98 Communication Flow 99 Operating Modes li ere eue Ee a eee Eek TIER oak 101 Bus Arbitration 2l etek dee eee Siete 101 Clock Synchronization ull EL a ee bie hee ee ae IR REED E ee Es 101 General Call Address ee owed Gates MR RR eee 101 Serial 1 0 Engine SIOE 2 kee 102 Interface Control Register 1 103 Interface Status Register 515
14. CAPCOMH1 7 0 00 B2 CAPCOML2 7 0 00 Table 93 page 155 B3 i de 2 7 0 00 B4 PWMFO PWMFOQ 7 0 00 B5 RESERVED B6 RESERVED Table B7 PADC PSPI PPCA pst E Pizc 20 page 46 Table PT2 pso PTI PX1 PTO PXO 1 Ba lt BDh gt lt BCh gt lt BBh gt BAR lt B9h gt lt Bah gt 00 B9 RESERVED BA PCACL1 PCACL1 7 0 00 Table 93 page BB 1 1 7 0 00 155 Table BC 1 EN PCA EOVF1 PCA IDL CLK_SEL 1 0 00 97 page 161 27 264 uPSD34xx SPECIAL FUNCTION REGISTERS SFR SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Value Descr hex 7 6 5 4 3 2 1 0 hex with Link BD EINTF E COMP PE MATCH PWM 1 0 00 TCMMODE Table BE d EINTF E COMP PE MATCH TOGGLE PWM 1 0 00 99 page 163 BF PE EINTF E COMP PE MATCH TOGGLE PWN 1 0 00 a p P4 7 P46 P4 5 P4 4 P42 P40 co lt C7h gt lt C6h gt lt C5h gt lt C4h gt C3h C2h lt gt COh 2 c1 a CAPCOML3 7 0 00 c2 7 0 00 C3 wisi a CAPCOMLA 7 0 00 Table CAPCOMH4I 7 0 oo 99 page 4 155 C5 RE CAPCOMLS 7 0 00 C6 17 0 00
15. Stop Condition Repeated ACK Start Condition 3 8 9 Repeated if more A cH data bytes are transferred 109625 Operating Modes The 2 interface supports four operating modes m Master Transmitter m M Master Receiver m Slave Transmitter m The interface may operate as either a Master or a Slave within a given application controlled by firm ware writing to SFRs By default after a reset the 2 interface is in Mas ter Receiver mode and the SDA P3 6 and SCL P3 7 pins default to GPIO input mode high imped ance so there is no 2 bus interference Before using the 2 interface it must be initialized by firmware and the pins must be configured This is discussed in IC Operating Sequences page 111 Bus Arbitration A Master device always samples the bus to ensure a bus line is high whenever that Master is asserting a logic 1 If the line is low at that time the Master recognizes another device is overriding its own transmission A Master may start a transfer only if the 2 bus is not busy However it is possible that two or more Masters may generate a START condition simulta neously In this case arbitration takes place on the SDA line each time SCL is high The Master that first senses that its bus sample does not corre spond to what it is driving SDA line is low while it is asserting a high will immediately change from
16. 2kHz ACLK 8MHz Vcc 3 3V 2 AVrer Vcc in 52 pin package 243 264 uPSD34xx DC AND AC PARAMETERS Table 164 USB Transceiver Specification Symbol Parameter Test Conditions Min UVoH High Output Voltage Vpp 3 3V lout 2 2mA 3 UVoL Low Output Voltage Vpp 3 3V lout 2 2 0 25 V UViH High Input Voltage Vpp 3 6V 2 V UVIL Low Input Voltage Vpp 3 6V 0 8 V Output Impedance high state Note 2 28 43 Q RDL Output Impedance low state Note 2 28 IL Input Leakage Current Vpp 3 6V Vie Vor Vcr Crossover Point 1 3 tRISE Rise Time 4 tFALL Fall Time 4 Note 1 Temperature range 45 C to 85 C 2 This value includes an external resistor of 240 1 244 264 uPSD34xx DC AND AC PARAMETERS Figure 101 Input to Output Disable Enable INPUT X X tER tEA 4 INPUT TO OUTPUT ENABLE DISABLE 102863 Table 165 CPLD Combinatorial Timing 5 PSD Module Symbol Parameter Conditions Min Max ton 2 CPLD Input Pin Feedback to RD CPLD Combinatorial Output t CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay t CPLD Register Clear or Preset ARPW Pulse Width Note 1 Fast Slew Rate output available on PA3 PAO PB3 PBO and PD2 PD1 Decrement times by given amount 2 tpp for MCU address and contro
17. Figure 65 PSDsoft Express Memory Mapping gt Design Assistant Page Register Definition Chip Select Equations 1 0 Logic Equations User defined Node Equations For each chip select select a page number if memory paging is used the active address range and any additional signal qualifiers Ensure PSD page register bits have been defined if used here Signal qualifiers are listed in box on right Logically AND qualifiers within same line using amp symbol Create logic by using next line below Use symbol for logical Main PSD flash memory will reside in this space at power up Program Space Only Secondary PSD flash memory will reside in this space at power up Data Space Only List of chip selects Enter system memory information E Page Hex Start Hex End Logical AND of Signal Qualifiers Number Address Address more than one Ss 6000 x x Logical OR with next statement ll Logical OR with next statement a Ir Resultant equation Internal PSD chip select for one 16K byte segment of main flash 3FFF hex locations fs4 1 amp address gt h8000 amp address lt hBFFF J ll _ xi Double click any of the signal names below to append the signal name to the Logical AND of Signal Qualifiers box where the cursor is located Eligible signals a8 lt lt
18. P12 inira ANALOG 1 P13 L__ ADC3 MUX Pi4 ADGA Pi5 Piel ABER P1 7 SELECT ACON REG Register The ADC operates within a range of 2 to 16MHz with typical ADCCLK frequency at 8MHz The conversion time is 4us typical at 8 2 The processing of conversion starts when the Start Bit ADST is set to 1 After one cycle it is cleared by hardware The ADC is monotonic with no missing codes Measurement is by continuous conversion of the analog input The ADAT Regis ter contains the results of the A D conversion When conversion is complete the result is loaded into the ADAT The A D Conversion Status Bit ADSF is set to 1 The block diagram of the A D module is shown in Figure 57 The A D status bit ADSF is set automatically when A D conversion is completed and cleared when A D conversion is in process In addition the ADC unit sets the interrupt flag in the ACON Register after a conversion is complete if AINTEN is set to 1 The ADC interrupts the CPU when the enable bit AINTEN is set Port 1 ADC Channel Selects The P1SFSO and P1SFS1 Registers control the selection of the Port 1 pin functions When the P1SFSO Bit is 0 the pin functions as GPIO When bits are set to 1 the pins are configured as alternate functions A new P1SFS1 Register se lects which of the alternate functions is enabled The ADC channel is enabled when the bit in 1 51 is set to 1 Note In the
19. Data Packet Handshake Packet 110491 127 264 uPSD34xx USB INTERFACE m Control Transfers see Figure 53 Control transfers are used to configure and send commands to a device Control transfers consist of two or three stages SETUP This stage always consists of a data packet with eight bytes of USB CONTROL data DATA stage optional Ifthe CONTROL data is such that the host is requesting information from the device the SETUP stage is followed by a DATA stage In this case the host sends an IN token and the device responds with the requested data in the data packet STATUS stage This stage is essentially a handshake informing the device of a successfully completed control operation Enumeration Enumeration is the process that takes place when a device is first connected to the USB During enumeration the host requests infor mation from the device about what it is how many endpoints it has the power requirements bus bandwidth requirements and what driver to load Figure 53 Control Transfer Once the enumeration process is complete the device is available for use The enumeration process consists of a series of six steps as follows 1 When a device is first connected to the USB its address is zero Upon detecting a new device connected to the USB the host sends a Get Descriptor request to address zero endpointo 2 The device upon receiving a Get_Descriptor reques
20. On 2mA 4 5V 24 3 9 V Output High Voltage On 1uA Vstpy 0 8 V VsrBv SRAM Stand by Voltage 2 0 Vpp V SRAM Stand by Current Vpp OV 0 5 1 uA liDLE Idle Current Vstpy input Vpp gt VsTBY 0 1 0 1 uA VDF SRAM Data Retention Voltage Only on 2 Vpp 0 2 V Stand by Supply Current CSI gt Vpp 0 3V Ise for Power down Mode Notes 1 2 25 lu Input Leakage Current Vss lt lt 1 uA ILo Output Leakage Current 0 45 lt Vout lt 10 uA PLD_TURBO Off PLD Only PED TURBO On 400 700 uA PT loc DC Operating f OMHz Note 4 8 During Flash memory 15 30 ink Flash memory WRITE Erase Only SRAM f OMHz 0 0 mA PLD AC Adder Note 3 mA Icc AC Flash memory AC Adder 1 5 2 5 MHz Note 4 SRAM AC Adder 1 5 3 0 fru MHz Note 1 Internal Power down mode is active 2 PLD is in non Turbo mode and none of the inputs are switching 3 Please see Figure 96 page 233 for the PLD current calculation 4 lout 239 264 uPSD34xx DC AND AC PARAMETERS Table 158 PSD Module DC Characteristics with 3 3V Vpp Note 1 Internal PD is active 2 PLD is in non Turbo mode and none of the inputs are switching 3 Please see Figure 97 page 233 for the PLD current calculation 4 lout Test Condition Symbol Parameter in addition to those in Min Typ Max Unit
21. Any Main Flash memory sector select may not be mapped in the same address range as another Main Flash sector select cannot overlap segments of Main Flash on top of each other Secondary Flash memory sector select may not be mapped in the same address range as another Secondary Flash sector select cannot overlap segments of Secondary Flash on top of each other A Secondary Flash memory sector may overlap a Main Flash memory sector In the case of overlap priority is given to the Secondary Flash memory sector SRAM CSIOP or PSELx may overlap any Flash memory sector In the case of overlap priority is given to SRAM CSIOP or PSELx Note PSELx is for optional Peripheral I O Mode on Port A The address range for sector selects for SRAM PSELx and CSIOP must not overlap each other as they have the same priority causing contention if overlapped Figure 69 illustrates the priority scheme of the memory elements of the PSD Module Priority re fers to which memory will ultimately produce a byte of data or code to the 8032 MCU for a given bus cycle Any memory on a higher level can over lap and has priority over any memory on a lower level Memories on the same level must not over lap Example FSO is valid when the 8032 produces an address in the range of 8000h to BFFFh CSBOOTO is valid 8000h to 9FFFh RSO is valid from 8000h to 87FFh Any address from the 8032 in the range of RSO always
22. The AND OR Array is used to form product terms These product terms are configured from the logic definitions entered in PSDsoft Express A PLD In put Bus consisting of 69 signals is connected to both PLDs Input signals are shown in Table 111 both the true and compliment versions of each of these signals are available at inputs to each PLD Note The 8032 data bus DO D7 does not route directly to PLD inputs Instead the 8032 data bus has indirect access to the GPLD not the DPLD when the 8032 reads and writes the OMC and IMC registers within csiop address space 3 uPSD34xx PSD MODULE Turbo Bit and PLDs The PLDs can minimize power consumption by going to standby after ALL the PLD inputs remain unchanged for an extended time about 70ns When the Turbo Bit is set to log ic one Bit 3 of the csiop PMMRO Register Turbo mode is turned off and then this automatic standby mode is achieved Turning off Turbo mode in creases propagation delays while reducing power consumption The default state of the Turbo Bit is logic zero meaning Turbo mode is on Additional ly four bits are available in the csiop PMMRO and PMMR2 Registers to block the 8032 bus control signals RD WR PSEN ALE from entering the PLDs This reduces power consumption and can be used only when these 8032 control signals are not used in PLD logic equations See Power Management page 218 Table 111 DPLD and GPLD Inputs Input Source Input N
23. The Error Flag Bit DQ5 is set if either an internal time out occurred while the embedded algorithm attempted to program the byte or if the 8032 at tempted to program bit to logic 1 when that bit was already programmed to logic 0 must erase to achieve logic 1 It is suggested as with all Flash memories to read the location again after the embedded program ming algorithm has completed to compare the byte that was written to Flash memory with the byte that was intended to be written When using the Data Toggle method during an erase operation Figure 73 still applies the Toggle Flag Bit DQ6 toggles until the erase operation is complete A 1 on the Error Flag Bit DQ5 indi cates a time out condition on the Erase cycle a 0 indicates no error The 8032 can read any location within the sector being erased to get the Toggle Flag Bit DQ6 and the Error Flag Bit DQ5 uPSD34xx PSD MODULE PSDsoft Express generates ANSI C code func tions the user may use to implement these Data Toggling algorithms Figure 73 Data Toggle Flowchart READ DQ5 amp DQ6 YES YES READ DQ6 PASS 101370 183 264 uPSD34xx PSD MODULE Ready Busy PC3 This signal can be used to output the Ready Busy status of a program or erase operation on either Flash memory The out put on the Ready Busy pin is a 0 Busy when ei ther Flash memory array is being written or when
24. Native product terms come from the AND OR Ar ray Each OMC may borrow product terms only from certain other OMCs if they are not in use Figure 78 OMC Allocator PORT A PINS 80 pin pkg only 716 5 4 3 2 1 0 Bank MCELLABO 7 Bank BC MCELLBCO 7 PORT PINS 7 6 5 4 3 2 1 Product term allocation does not add any propaga tion delay to the logic The fitter report generated by PSDsoft Express will show any PT allocation that has occurred If an equation requires more product terms than are available to it through PT allocation then ex ternal product terms are required which con sumes other OMCs This is called product term expansion and also happens automatically in PS Dsoft Express as needed PT expansion causes additional propagation delay because an addition al OMC is consumed by the expansion process and its output is rerouted or fed back into the AND OR array The user can examine the fitter re port generated by PSDsoft Express to see result ing PT allocation and PT expansion expansion will have signal names such as fb 0 or fb 1 PSDsoft Express will always try to fit the logic de sign first by using PT allocation and if that is not sufficient then PSDsoft Express will use PT expan sion Product term expansion may occur in the DPLD for complex chip select equations for Flash mem ory sectors and for SRAM but this is a rare oc curence If PSDsof
25. Note AC inputs during testing are driven at 0 5 for a logic 1 0 45V for a logic 0 Timing measurements are made at for a logic 1 and Vii max for a logic 0 Figure 110 PSD Module AC Float I O Waveform VLOAD 0 1V 0 1V Test Reference Points VLOAD 0 1 VoL 0 1V 0 2 0 1V 106651 Note For timing purposes a Port pin is considered to be no longer floating when a 100 change from load voltage occurs and begins to float when a 100mV change from the loaded Vou or VoL level occurs lot and gt 20mA 255 264 uPSD34xx DC AND AC PARAMETERS Figure 111 External Clock Cycle 0 2 0 1 0 45 tener Figure 112 PSD Module AC Measurement I O Figure 113 PSD Module AC Measurement Waveform Load Circuit 2 01 V 3 0V 195 Q ai Device ov Under Test 30 pF Including Scope and Jig Capacitance AI03103b AI03104b Table 182 I O Pin Capacitance Vout OV output pins 9 Cour Note 1 Sampled only not 100 tested 2 Typical values are for TA 25 C and nominal supply voltages 3 Maximum for MCU Address and Data lines is 20pF each 256 264 uPSD34xx PACKAGE MECHANICAL INFORMATION PACKAGE MECHANICAL INFORMATION Figure 114 TQFP52 52 lead Plastic Thin Quad Flat Package Outline D ra gt D1
26. p SINANI Nid STISDOYOVIN 1 jojo s s s s s a s s SIMO 1 1 91 E 55 HOlV2 OTY 00000000 5199198 1 PLD INPUT BUS ze dn 2608 NVHS 8032 MCU Module uoje LOL Sa gy ze S1N3IND3S 01 dn o1008s5 50100980 AHOW3IN HSV 14 V101 Se1 gy 962 dn S1N3IND3S 8 01 dn 0 Sd AYOWAW HSV14 NIVIN 3901 5508 ALINDAS viva daav NOW 2608 SNA TOHINOO XXxy asdn einpoi asd 164 264 PSD Module Functional Description Major functional blocks are shown in Figure 62 page 164 The next sections describe each major block 8032 Address Data Control Interface These signals attach directly to the MCU Module to im plement a 16 bit multiplexed 8051 style bus be tween the two stacked die The MCU instruction prefetch and branch cache logic resides on the MCU Module leaving a modified 8051 style mem ory interface on the PSD Module The active low reset signal originating from the MCU Module goes to the PSD Module reset input RST This reset signal can then be routed as an external output from the 5034 to the system PC board if needed through any one of the PLD output pins
27. written the second packet of 64 bytes to the the data transfer rate Figure 55 FIFO Pairing Example 1 2 IN Paired and 3 4 OUT Paired Endpoint4 Endpoint4 Endpoint4 IN FIFO Endpoint3 Endpoint3 Endpoint3 IN FIFO Endpoin2 Endpoint not available Endpoint IN FIFO not available 1 IN Endpoint Endpoint1 Endpoint1 IN FIFO 1 EndpointO EndpointO EndpointO IN FIFO Serial FIFO Interface Interface Engine EndpointO EndpointO Logic EndpointO OUT FIFO CTRL Endpoint1 Endpoint USB SFRs Endpoint1 OUT FIFO Endpoint2 Endpoint2 Endpoint2 OUT FIFO IGT T Endpoint3 Endpoint3 OUT FIFO Endpoint3 Endpoint4 i Endpoint4 not available Endpoint4 OUT FIFO not available H 1 1 EE LLL EE 110494 ky 131 264 uPSD34xx USB INTERFACE Reading and Writing FIFOs There are a total of ten 64 byte FIFOs Each of the five Endpoints has two FIFOs one IN FIFO for IN transactions and one OUT FIFO for OUT transactions The FIFOs are accessible by the CPU through a 64 byte seg ment in the XDATA space when the VISIBLE Bit is set see Table 80 page 143 If the VISIBLE Bit is not set the FIFOs are not accessible by the CPU but are still accessible by the SIE The base ad dress of the 64 byte segment is specified by the USB Base Address High Register see Table 85 page 148 and the USB Base Address Low Register see Table 86 page 148 When the VISIBLE Bit is
28. 20 Input Macrocells IMC OMC Allocator Product Term Allocator inside each OMC AND OR Array capable of generating up to 137 product terms Three I O Ports A B and C 191 264 uPSD34xx PSD MODULE l pin Port A B or C ica One One and One Port typ Figure 76 GPLD 1 OWI T13290H2VW 1 31901 1HOd O I YAHLO OL HOIVOOTIV TI300HOVMW r7 777 NOH 31907 IVNSIS OW DOIN AINI voii 31V9 10 4390 19 VIVO 2608 593151999 40152 mox NOILO3HIQ 11HOd MOV LNO Viva 2508 LAdLNO OWO a318vN3 1091302 NOILO3HIG qu 2508 Ino viva NI 1 519 viva 90152 119 SGOW Lid HQQV 2608 JOHLNOD NOLLO3HIG LNO viva 593151099 HM 2508 SLId Viva sna 1OH1NOO V1va Ssauaav 2608 lt lt lt lt CS VIVO 2608 LNO OWO avad c 08 593151999 HM 2508 319071 4014 9113 2971320 aVT1S9IN 90159 IVNSIS 31V9 10 420 19 MOVSO33H Nid Movg8aaad HV31O dO 14 d 1H 3509 dO 14 dl 1H 32019 1V8O 19 931 LOndOHd HO1VOOTIV WHal lonaosd lt SONO H3HIO NOY SWHAL 1 1 1
29. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 Details Bit Symbol R W Definition 0 No division 2 Diviee iu 1 Divide fosc clock by 128 0 No division DINGS EY 1 Divide fosc clock by 64 0 No division ay 1 Divide fosc clock by 32 0 No division 4 pve FM 1 Divide fosc clock by 16 0 No division 3 BINS RW 1 Divide fosc clock by 8 0 No division 2 oe md 1 Divide fosc clock by 4 1 0 Not Used ky 121 264 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE Table 66 SPISTAT SPI Interface Status Register SFR D3h Reset Value 02h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BUSY TEISF RORISF TISF RISF Details Bit Symbol R W Definition 7 5 Reserved SPI Busy BUSY H 0 Transmit or Receive is completed 1 Transmit or Receive is in process Transmission End Interrupt Source flag 3 TEISE i 0 Automatically resets to 0 when firmware reads this register 1 Automatically sets to 1 when transmission end occurs Receive Overrun Interrupt Source flag 2 PARISE i 0 Automatically resets to 0 when firmware reads this register 1 Automatically sets to 1 when receive overrun occurs Transfer Interrupt Source flag 0 Automatically resets to 0 when SPITDR is full just after the SPITDR 1 TISF R uat is written 1 Automatically sets 1 when SPITDR is empty just after byte loads from SPITDR into SPI shift register Receive Inte
30. INPUT SIGNAL amp 8032 DATA BIT FROM PIN ON PORT A B or C a PIN INPUT E e Q D lt LD S 4 TO PLD INPUT BUS lt lt PSDsoft D LE G FROM AND OR ARRAY Y PT CLOCK OR GATE LD OR LE INPUT MACROCELL IMC a a 2ll 22 2l 4 gt gt THIS SIGAL IS GANGED TO 3 OTHER IMCs GROUPING IMC 0 3 or IMC 4 7 Al06603A Table 117 Input Macrocell Port A address csiop offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit IMC PA7 IMC PA6 IMC 5 IMC PA4 IMC IMC PA2 IMC PA1 IMC PAO Note 1 Port A not available on 52 pin uPSD34xx devices 2 1 current state of IMC is logic 1 0 current state is logic 0 Table 118 Input Macrocell Port B address csiop offset OBh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PB7 IMC PB6 IMC PB5 IMC PB4 IMC PB3 IMC PB2 IMC PB1 IMC PBO Note 1 current state of IMC is logic 1 0 current state is logic 0 Table 119 Input Macrocell Port C address csiop offset 18h Bit 7 Bit 4 Bit 3 Bit 2 Bit 1 IMC PC7 IMC PC4 IMC PC3 IMC PC2 X Note 1 X Not guaranteed value can be read either 1 or 0 These are JTAG pins 2 1 current state of IMC is logic 1 0 current state is logic 0 198 264 Ports There are four programmable I O p
31. Note 1 For 5V uPSD34xx devices pull up resistors and Vcc pin on the JTAG connector should be connected to 5V system Vpp 2 For 3 3V uPSD34xx devices pull up resistors and Vcc pin on the JTAG connector should be connected to 3 3V system Vcc 3 This signal is driven by an Open Drain output in the JTAG equipment allowing more than one source to activate RESET_IN 229 264 uPSD34xx PSD MODULE Recommended JTAG Connector There is no industry standard JTAG connector STMicroelec tronics recommends a specific JTAG connector and pinout for UPSD3xxx so programming and de bug equipment will easily connect to the circuit board The user does not have to use this connec tor if there is a different connection scheme The recommended connector scheme can accept a standard 14 pin ribbon cable connector 2 rows of 7 pins on 0 1 centers 0 025 square posts standard keying as shown in Figure 94 See the STMicroelectronics FlashLINK FL 101 User Manual for more information Figure 94 Recommended JTAG Connector VIEW Looking into face of shrouded male connector with 0 025 14 13 posts on 0 1 centers TERR TDO 128 will GND TCK 108 m9 GND TMS K7 KEY RST WAY Connector reference Molex 70247 1401 This connector accepts a 14 pin ribbon cable such as Samtec HCSD 07 D 06 00 01 S N Digikey M3CCK 14065 ND KS TSTAT TDI 4 CNTL GND 2 HM 1 TRST JEN 1
32. Select Alternate Func gt _ gt Vcc Voc 5 DELAY WEAK STONGER 1 MCU CLK PULL UP B PULL UP A lt P3 X Pin Digital_Alt_Func_Data_Out P3 X SFR Read Latch gt for R M W instructions MCU Reset gt 8032 Data Bus lt gt GPIO P3 X SFR gt _ gt Write Latch P3 X SFR Read Pin gt Digital Pin Data In lt lt lt 109601 3 57 264 uPSD34xx I O PORTS of MCU MODULE Figure 19 MCU I O Cell Block Diagram for Port 4 For PCA Alternate Function Enable Push Pull 5 Select Alternate Func gt _ gt Vcc Voc Voc WEAK STONGER PULL UP B PULL UP A Digital_Alt_Func_Data_Out gt gt P4 X SFR Read Latch gt _ gt HIGH q for R M W instructions SIDE P4 X Pin Reset gt _ gt 8032 Data Bus Bit lt gt GPIO P4 X SFR gt _ gt Write Latch P4 X SFR Read Pin gt _ gt Digital_Pin_Data_In lt _ lt 109602 Table 27 P1 I O Port 1 Register SFR 90h reset value FFh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Details Bit Symbol R W Function 7 P1 7 RW Port pin 1 7 6 P1 6 R W Port pin 1 6 5 P1 5 R W Port pin 1 5 4 P1 4 Port 1 4 3 P1 3 R W Port pin 1 3 2 P1 2 RW Port pin 1 2 1 P1 1 RW Port pin 1 1 0 P1 0 R W Port pin 1 0 Note 1 Write 1 or 0 for pin output Read for pin input but prior to READ this bit must have been se
33. icon preventing the PSD Module memories from waking up from stand by mode even if noise or other devices are driving the address lines The PLDs will also stay in standby mode if the PLDs are in non Turbo mode and if all other PLD inputs non address signals are static However if the ALE signal has a transition before the APD counter reaches max count the APD counter is cleared to zero and the PDN signal will not go active preventing power down mode To prevent unwanted APD time outs during normal 8032 operation not sleeping it is important to choose a clock frequency for CLKIN that will NOT produce 15 or more pulses within the longest peri od between ALE transitions A 32768 Hz clock sig nal is quite often an ideal frequency for CLKIN and APD and this frequency is often available on ex ternal supervisor or real time clock devices The PDN power down indicator signal is avail able to the PLD input bus to use in any PLD equa tions if desired The user may want to send this signal as a PLD output to an external device to in dicate the PSD Module is in power down mode PSDsoft Express automatically includes the 220 264 PDN signal in the DPLD chip select equations for FSx CSBOOTx RSO and CSIOP The following should be kept in mind when the PSD Module is in power down mode 8032 address and data bus signals are blocked from all memories and both PLDs The PSD Module comes out of power down mode when
34. uPSD34xx SPECIAL FUNCTION REGISTERS SFR SPECIAL FUNCTION REGISTERS SFR A group of registers designated as Special Func tion Register SFR is shown in Table 5 page 25 SFRs control the operating modes of the MCU core and also control the peripheral interfaces and pins on the MCU Module The SFRs can be ac cessed only by using the Direct Addressing meth od within the address range from 80h to FFh of internal 8032 SRAM Sixteen addresses in SFR address space are both byte and bit addressable The bit addressable SFRs are noted in Table 5 106 of a possible 128 SFR addresses are occu pied The remaining unoccupied SFR addresses designated as RESERVED in Table 5 should not be written Reading unoccupied locations will return an undefined value Note There is a separate set of control registers for the PSD Module designated as csiop and they are described in the PSD MODULE page 164 The I O pins PLD and other functions on the PSD Module are NOT controlled by SFRs SFRs are categorized as follows m registers IP A B PSW SP DPTL DPTH DPTC DPTM MCU Module I O Port registers P1 P4 15 50 P1SFS1 P3SFS 45 50 P4SFS1 m Standard 8032 Timer registers TCON TMOD T2CON THO TH1 TH2 TLO TL1 TL2 RCAP2L RCAP2H m Standard Serial Interfaces UART SCONO SBUFO SCON1 SBUF1 m Power clock and bus timing registers 24 264 PCON CCONO CCON1 BUSCON
35. 0 when ownership of the FIFO changes from the SIE to the CPU generates a USB inter rupt with the corresponding flag set For an inter rupt on an IN FIFO the CPU must fill the FIFO with the next set of data to be sent and then update the USIZE register with the number of bytes to send For an interrupt on an OUT FIFO the CPU reads the USIZE register to determine the number of bytes received and then reads that number of data bytes out of the FIFO Max packet size Supported directions FIFO size 0 64 Bytes 0 Control 64 Bytes 1 Bulk Interrupt OUT 64 Bytes 1 Bulk Interrupt IN 64 Bytes 2 Bulk Interrupt OUT 64 Bytes 2 Bulk Interrupt IN 64 Bytes 3 Bulk Interrupt OUT 64 Bytes 3 Bulk Interrupt IN 64 Bytes 4 Bulk Interrupt OUT 64 Bytes 4 Bulk Interrupt In 64 Bytes 129 264 uPSD34xx USB INTERFACE FIFO Pairing The FIFOs on endpoints 1 through 4 may be used independently as shown in Figure 54 as FIFOs with no Pairing or they may be selec tively paired to provide double buffering see Fig ure 55 page 131 Double buffering provides an efficient way to optimize data transfer rates with bulk transfers Double buffering allows the CPU to process a data packet for an Endpoint while the SIE is receiving or transmitting another packet of data on the same Endpoint and direction FIFO pairing is controlled by the USB Pairing Control Register see UPAIR Table 71 page 135 FIFO pairing options are l
36. 4 73 48 General I O port pin PLD inputs or i Latched PB5 71 46 General I O port Address Out PB6 67 43 General I O port pin A0 A7 PB7 42 General I O port pin JTAGTMS TMS ZEE JTAG pin TMS JTAGTCK TCK 17 JTAG 12 264 ky uPSD34xx PIN DESCRIPTIONS Port Pin Signal 80 Pin m Function Name No No Alternate 1 Alternate 2 SRAM Standby PLD Macrocell PC2 VsTBY 16 11 voltage input output or PLD input Optional JTAG PLD Macrocell ROS TSIAI 19 Status TSTAT output or PLD input Optional JTAG PLD Macrocell TERR 3 Status TERR output or PLD input JTAGTDI TDI 7 4 JTAG pin TDI JTAGTDO TDO 6 3 JTAG 3 PLD Macrocell PC7 5 2 General I O port pin output or PLD input PLD I O PD1 CLKIN 3 1 General I O port Clock input to PLD and APD PLD I O PD2 CSI 1 N A General I O port pin Chip select ot PSD Module USB D pin 1 5kQ USB 11 7 pull up resistor is required USB 14 10 USB D pin 3 3V Vcc 10 6 Vcc MCU Module 72 47 Analog Vcc Input Vbb Vpp PSD Module 12 8 Vpp 3 3V for 3V 3 3V or 5V 5V for 5V Vpp PSD Module 50 33 Vo 3 3V for 3V 3 3V or 5V Vpp 5V for 5V GND 13 9 GND 29 19 GND 69 45 NC 51 N A NC 53 N A NC 55 N A NC 57 N A Note 1 N A Signal Not Available on 52 pin packag
37. C7 PWMF1 PWMF1 7 0 00 TA CP Table EXF2 TCLK EXEN2 TR 1 8 T2CON cerns lt CEh gt lt CDh gt CCh lt CBh gt CAh Con PL2 00 43 page C8h TY C9 RESERVED CA RCAP2L 2 7 0 00 Standard cB RCAP2H RCAP2H 7 0 00 Timer ce TL2 TL2 7 0 00 ie e CD TH2 TH2 7 0 00 Table IRDACON IRDA ENBBIT PULS CDIV4 CDIV3 CDIV2 CDIV1 CDIVO 50 page 95 Program pot FO RS 1 0 ov lt D5h gt lt D4h D3h gt lt D2h gt DO PSW pa ge 23 D1 RESERVED Table D2 SPICLKD SPICLKD 5 0 04 65 121 Table 03 SPISTAT BUSY TEISF RORISF TISF RISF 02 66 page 122 28 264 uPSD34xx SPECIAL FUNCTION REGISTERS SFR SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Value Descr hex 7 6 5 4 3 2 1 0 hex with Link D4 SPITDR SPITDR 7 0 O0 Table 64 page D5 SPIRDR SPIRDR 7 0 00 121 Table D6 SPICONO TE RE SPIEN SSEL FLSB SPO 00 63 page 120 Table 1 z TEIE RORIE TIE RIE 00 64 page 121 0 SMO SM SM2 REN TB8 RB8 TI MN 41 D8 DF DE lt DD gt DC DB DA D9 lt 08 gt r t Figure D9 SBUF1 SBUF1 7 0 00 28 page 81 DA RESERVED Table SiSETUP SS EN S
38. For other options or for more information on any aspect of this device please contact the ST Sales Office nearest you 261 264 uPSD34xx IMPORTANT NOTES IMPORTANT NOTES The following sections describe the limitations that apply to the uPSD34xx devices USB Interrupts with Idle Mode Description An interrupt generated by a USB related event does not bring the MCU out of idle mode for pro cessing Impact On Application Idle mode cannot be used with USB Workaround None identified at this time USB Reset Interrupt Description When the MCU clock prescaler is set to a value other than fcu fosc no division a reset signal on the USB does not cause a USB interrupt to be generated Impact On Application An MCU clock other than that equal to the frequen cy of the oscillator cannot be used Workaround The CPUPS field in the CCONO register must be set to 000b default after reset The 3400 USB firmware examples set CCONO register to 000b USB Reset Description A USB reset does not reset the USB SIE s regis ters Impact On Application A USB reset does not reset the USB SIE s regis ters as does a power on or hardware reset Workaround When a USB reset is detected the USB SIE s reg isters must be initialized appropriately by the fir ware The 3400 USB firmware examples clear USB SIE s if USB reset is detected 262 264 Data Toggle Description The data toggle bit is read only Impac
39. NIB Input Low Time Note 1 12 ns tino NIB Input to Combinatorial Delay Note 1 43 4 15 ns Note 1 Inputs from Port A B and C relative to register latch clock from the PLD ALE latch timings refer to and tLxax 250 264 uPSD34xx DC AND AC PARAMETERS Table 173 Program WRITE and Erase Times 5V 3V PSD Modules Note 1 Programmed to all zero before erase 2 Typical after 100K Write Erase cycles is 5 seconds 3 The polling status DQ7 is valid 7 time units before the data byte DQ0 DQ7 is valid for reading 3 Symbol Parameter Flash Program Flash Bulk Erase pre programmed Flash Bulk Erase not pre programmed 5 S twHQv3 Sector Erase pre programmed twHave Sector Erase not pre programmed 2 2 S twHav1 Byte Program 14 150 us Program Erase Cycles per Sector PLD Program Erase Cycles twHWLO Sector Erase Time Out tazvav DQ7 Valid to Output 007 000 Valid Data Polling 9 251 264 uPSD34xx DC AND AC PARAMETERS Figure 106 Peripheral I O READ Timing A D BUS ADDRESS tavav PA PA QUAL tRLav gt csi DATA ON PORTA tRHOZ PA tpvav PA 106610 Table 174 Port Peripheral Data Mode READ Timing 5 PSD Module Symbol Parameter Conditions Min Max ur Unit CURE Valid to Data Note 1 37 10 hs tstav pa
40. Port A also supports Open Drain Slew Rate output drive type options using csiop Drive Select regis ters Pins PAO PA3 can be configured to fast slew rate pins PA4 PA7 can be configured to Open Drain Mode See Figure 85 for details we PORTA WR PSEL RD PIO EN PSELx LOGIC PERIPHERAL MODE SETS DIRECTION DRIVE TYPE SELECT lt CMOS BUFFER PIN INPUT NO hm 71 TYPICAL iiti PIN PORT A HYSTERESIS IMCAO IMCA7 109179 Note 1 Port pins capable of Fast Slew Rate output drive option Port pins PA4 PA7 capable of Open Drain output option 212 264 Port B Structure Port B supports the following operating modes m MCU I O Mode m GPLD Output Mode from Output Macrocells MCELLABx or MCELLBCx OMC allocator routes these signals m GPLD Input Mode to Input Macrocells IMCBx m Latched Address Output Mode Figure 86 Port B Structure PORT FROM AND 3 OUTPUT ENABLE diciiur OR ARRAY FROM PLD 9D MODULE RESET INPUTBUS DIRECTION DRIVE TYPE RD gt 1 OPEN 11 FAST DRAIN i SLEW RATE BE OUTPUT PB4 PB7j PB3 SELECT i 1 1 Q2 Yoo B MCUI O X 5 DATA OUT 1 OUTPUT d U T ENABLE A i TYPICAL E P PIN PIN PORT B lt U OUTPUT i i LATCHED ADDR BIT i ON Z a OUTPUT A E
41. Prev Next gt gt Reset All View Cancel Show 170 264 1572 EEPROM Emulation EEPROM emulation is needed if it is desired to repeatedly change only a small number of bytes of data in Flash memory In this case EEPROM emulation is needed because although Flash memory can be written byte by byte it must be erased sector by sector it is not erasable byte by byte unlike EEPROM which is written AND erased byte by byte So changing one or two bytes in Flash memory typically re quires erasing an entire sector each time only one byte is changed within that sector However two of the 8K byte sectors of Secondary Flash memory may be used to emulate EEPROM by using a linked list software technique to create a small data set that is maintained by alternating between the two flash sectors For example a data set of 128 bytes is written and maintained by software in a distributed fashion across one 8K byte sector of Secondary Flash memory until it be comes full Then the writing continues on the other 8K byte sector while erasing the first 8K byte sec tor This process repeats continuously bouncing back and forth between the two 8K byte sectors This creates a wear leveling effect which increas es the effective number of erase cycles for a data set of 128 bytes to many times more than the base 100K erase cycles of the Flash memory EEPROM emulation in Flash memory is typically faster than writing to actua
42. TI Start Tx Clock Send Serial Port Interrupt Load SBUF Shift RI 1100 Rx Control Transition Start Input Shift Register Rx Clock RxD Load S7 Pin SBUF Shift SBUF Read SBUF v Internal Bus 106826 Figure 34 UART Mode 1 Timing Diagram Tx Clock Write to SBUF Send Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Transmit cl G I n n n n n Start Bit D XD XD D3 X D4 X Ds X D6 D7 Stop Bit EA er ry eee 5 n nm n n n n n n m mnm n m Start Bit D X Di X 52 X D3 X D4 X Ds X D6 X 57 Stop Bit M mui mm omm mm mp mm mmu pymes SL Sc Receive 106843 90 264 1572 More About UART Modes 2 and 3 For Mode 2 refer to the block diagram in Figure 35 page 92 and timing diagram in Figure 36 page 92 For Mode 3 refer to the block dia gram in Figure 37 page 93 and timing diagram in Figure 38 page 93 Keep in mind that the baud rate is programmable to either 1 32 or 1 64 of fosc in Mode 2 but Mode 3 uses a variable baud rate generated from Timer 1 or Timer 2 rollovers The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction which writes to SBUF At the end of a writ
43. TXD1 UART or IrDA ADC Channel 3 PIS apes General VO port Pin Transmit TxD1 input ADC3 SPICLK SPI Clock Out ADC Channel 4 P1 4 ADC4 General I O port pin SPICLK input 4 SPIRxD SPI Receive ADC Channel 5 P1 5 ADCS vo General I O port pin SPIRxD input ADCS SPITXD SPI Transmit ADC Channel 6 P1 6 ADC6 General I O port pin SPITxD input ADC6 SPISEL SPI Slave Select ADC Channel 7 P1 7 ADC7 General I O port pin SPISEL input ADC7 UARTO Receive P3 0 RxDO General I O port pin RxDO UARTO Transmit P3 1 TXDO 77 24 General I O port TxDO EXINTO Interrupt O input P3 2 TGO 79 25 General I O port pin EXTINTO Timer 0 gate control TGO Interrupt 1 input P3 3 INT1 2 26 General I O port pin EXTINT1 Timer 1 gate control TG1 P3 4 CO 40 27 General I O port pin Counter 0 input CO P3 5 C1 42 28 General I O port pin Counter 1 input C1 2 H P3 6 SDA 44 29 WO General VO port pin C Bus serial data IFCSDA 2 P3 7 SCL 46 30 General VO port pin 0 Bus clock IFCSCL T2 Program Counter Timer 2 Count input P4 0 TCMO 33 22 General I O port pin ArrayO PCAO TCMO T2 11 264 uPSD34xx PIN DESCRIPTIONS 2 Signal 80 Pin 52 Function Port P No Alternate 1 Alternate 2 T2X 5
44. Table 156 page 238 ViH High Level Input Voltage 3 0V Vpp 3 6V V Low Level Input Voltage 3 0V Vpp 3 6V Vpp min for Flash Erase and VLKO Program y loL 200 Vpp 3 0V V VoL Output Low Voltage lo 4mA Vpp 3 0V E V Output High Voltage Except loH 20 Vpp 3 0V 2 9 2 99 V On loH 1mA Vpp 3 0V 2 7 2 8 V Output High Voltage On 1uA Vstpy 0 8 V VsrBv SRAM Stand by Voltage 2 0 Vpp V SRAM Stand by Current Vpp OV 0 5 1 uA Idle Current input Vpp gt VsTBY 0 1 uA VDF SRAM Data Retention Voltage Only on 2 V Stand by Supply Current CSI gt Vpp 0 3V 3B for Power down Mode Notes 1 2 Input Leakage Current Vss lt VIN lt VDD 1 uA ILo Output Leakage Current 0 45 lt Vin lt 10 PLD TURBO Off f OMHz Note 2 PLD Only FED TUE 200 400 uA PT loc DC Operating f OMHz Note 4 AA During Flash memory 10 25 m Flash memory WRITE Erase Only Read only f OMHz 0 0 mA SRAM f OMHz 0 0 mA PLD AC Adder Note 3 mA Icc AC Flash memory AC Adder 1 0 1 5 MHz Note 4 SRAM AC Adder 0 8 XM EU 2 240 264 o uPSD34xx DC AND AC PARAMETERS Figure 99 External READ Cycle 80 pin Device Only tLHLL tLLRL ALE tAVLL L MCU ADO AD7 tRX LATCHED A8 A15 Al10471 Table 159 External READ
45. The four basic JTAG signals on Port C TMS TCK TDI and TDO form the IEEE 1149 1 interface The PSD Module does not implement 168 264 the IEEE 1149 1 Boundary Scan functions but uses the JTAG interface for ISP an 8032 debug The PSD Module can reside in a standard JTAG chain with other JTAG devices and it will remain in BYPASS mode when other devices perform JTAG functions ISP programming time can be reduced as much as 30 by using two optional JTAG signals on Port C TSTAT and TERR in addition to TMS TCK TDI and TDO and this is referred to as 6 pin JTAG The FlashLINK JTAG programming cable is available from STMicroelectronics and PSDsoft Express software is available at no charge from www st com psm More JTAG ISP information maybe found in the section titled JTAG ISP and Debug on page 137 The MCU module is also included in the JTAG chain within the uPSD34xx device for 8032 debug ging and emulation While debugging the PSD Module is in BYPASS mode Conversely during ISP the MCU Module is in BYPASS mode Power Management The PSD Module has bits in csiop registers that are configured at run time by the 8032 to reduce power consumption of the GPLD The Turbo Bit in the PMMRO Register can be set to logic 1 and both PLDs will go to Non Turbo mode meaning it will latch its outputs and go to sleep until the next transition on its inputs There is a slight penalty in PLD performance longer propagation delay but
46. and the operating voltage A 5V uPSD34xx device operates with four memory wait states but a 3 3V device operates with five memory wait states yielding 8 MIPS peak com pared to 10 MIPs peak for 5V device The same number of wait states will apply to both program fetches and to data READ WRITEs unless other wise specified in the SFR named BUSCON In general a 3X aggregate performance increase is expected over any standard 8032 application running at the same clock frequency uPSD34xx 8032 MCU CORE PERFORMANCE ENHANCEMENTS Figure 9 PFQ Operation on Multi cycle Instructions PFQ Execution zT gt o N 5 g o N 5 E o 5 m X E o 5 5 T A Q Three 2 byte 2 cycle Instructions on uPSD34xx Pre Fetch Inst A Pre Fetch Inst B and C Pre Fetch next Inst i i i 1 1 1 4 clock Macine Cycle i i Phase 1 Phase 2 Phase 3 Phase 4 Phase 5 Phase 6 1 Instruction A Instruction B Instruction C 110432 Figure 10 uPSD34xx Multi cycle Instructions Compared to Standard 8032 Three 2 byte 2 cycle Instructions uPSD34xx vs Standard 8032 24 Clocks Total 4 clocks per cycle gt 1 Cycle 72 Clocks 12 clocks per cycle Std 8032 1 Byte 2 Process Inst Byte 1 2 Process Inst B Byte 1 Byte2 Process Inst C 1 Cycle Al10412 21 264 u
47. as de fined with PSDsoft Express The user only has to specify an address range for each segment and specify if Secondary Flash memory will reside in 8032 data or program address space and then PSEN RD or WR are automatically activated for the specified range 8032 firmware is easily pro grammed into Secondary Flash memory using PS Dsoft Express and others See Table 101 page 166 for Secondary Flash sector sizes SRAM The SRAM is selected by a single signal named RSO from the Decode PLD SRAM may be located at any address within 8032 XDATA space accessed with RD or WR These choices are specified using PSDSoft Express where the user specifies an SRAM address range See Table 101 page 166 for SRAM sizes The SRAM may optionally be backed up by an ex ternal battery or other DC source to make its con tents non volatile see SRAM Standby Mode battery backup page 224 165 264 uPSD34xx PSD MODULE Table 101 uPSD34xx Memory Configuration Main Flash Memory Secondary Flash Memory SRAM Device Total Individual Number of Total Individual Number of Flash Size Sector Size Sectors Sector Flash Size Sector Size Sectors Sector bytes bytes Select Signal bytes bytes Select Signal uPSD3422 16K 4 FS0 3 4 CSBOOTO 3 uPSD3433 128K 16K 8 50 7 4 CSBOOTO 3 uPSD3434 256K 32K 8 50 7 4 CSBOOTO 3 uPSD3454 256K 32K 8 50 7 4 CSBOOTO 3 Runtime Control Regi
48. configured as Open Drain and the resistor should be sized not to exceed the current sink capability of the pin see DC specifications Open Drain out puts are diode clamped thus the maximum volt age on an pin configured as Open Drain 1 0 7V A pin can be configured as Open Drain if its corre sponding bit in the Drive Select Register is set to logic 1 Note The slew rate is a measurement of the rise and fall times of an output A higher slew rate means a faster output response and may create more electrical noise A pin operates in a high slew rate when the corresponding bit in the Drive Reg ister is set to 1 The default rate is standard slew rate see AC specifications Table 136 through Table 139 page 211 show the csiop Drive Registers for Ports A B C and D The tables summarize which pins can be configured as Open Drain outputs and which pins the slew rate can be changed The default output type is CMOS push pull output with normal slew rate Enable Out Registers The state of the output enable signal for the output driver at each pin on Ports A B C and D can be read at any time by the 8032 when it reads the csiop Enable Output regis ters Logic 1 means the driver is in output mode logic 0 means the output driver is in high imped ance mode making the pin suitable for input mode read by the input buffer shown in Figure 80 page 200 Figure 80 shows the three sources that can control the p
49. halt The Watchdog Timer should be disabled while debugging with JTAG else a reset will be generated upon a watchdog time out INTERRUPT SYSTEM The uPSD34xx has an 12 source two priority level interrupt structure summarized in Table 16 Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named IP and IPA shown in Table 16 An inter rupt will be serviced as long as an interrupt of equal or higher priority is not already being ser viced If an interrupt of equal or higher priority is being serviced the new interrupt will wait until it is finished before being serviced If a lower priority interrupt is being serviced it will be stopped and the new interrupt is serviced When the new inter rupt is finished the lower priority interrupt that was stopped will be completed If new interrupt re quests are of the same priority level and are re ceived simultaneously internal polling sequence determines which request is selected for service Thus within each of the two priority levels there is a second priority structure deter mined by the polling sequence Firmware may individually enable or disable inter rupt sources by writing to bits in the SFRs named IE and IEA shown in Table 16 page 42 The SFR named IE contains a global disable bit EA which can be cleared to disable all 12 interrupts at once as shown in Table 17 page45 Figure 13 page 43 illustrates the
50. in the POR bit of the SFR named PCON Table 26 page 52 Software can read this bit to determine whether the last MCU reset was the result of a power up cold reset or a reset from some other condition warm reset This bit must be cleared with soft ware JTAG Debug Reset The JTAG Debug Unit can generate a reset for de bugging purposes This reset source is also avail able when the MCU is in Idle Mode and Power Down Mode the user can use the JTAG debugger to exit these modes Watchdog Timer WDT When enabled the WDT will generate a reset whenever it overflows Firmware that is behaving correctly will periodically clear the WDT before it overflows Run away firmware will not be able to clear the WDT and a reset will be generated Figure 24 Watchdog Counter By default the WDT is disabled after each reset Note The WDT is not active during Idle mode or Power down Mode There are two SFRs that control the WDT they are WDKEY Table 39 page 70 and WDRST Table 40 page 70 If WDKEY contains 55h the WDT is disabled Any value other than 55h in WDKEY will enable the WDT By default after any reset condition WD KEY is automatically loaded with 55h disabling the WDT It is the responsibility of initialization firmware to write some value other than 55h to WDKEY after each reset if the WDT is to be used The WDT consists of a 24 bit up counter Figure 24 whose initial count is 000000h by default after ever
51. range limit is 256 bytes of internal 8032 SRAM For example MOV A 40h Move contents of DATA SRAM at location 40h into the accumulator Register Indirect Addressing This mode uses an 8 bit address contained in ei ther Register RO or R1 to indirectly address an op erand which resides in 8032 IDATA SRAM internal address range 80h FFh Although 8032 SFR registers also occupy the same physical ad dress range as IDATA SFRs will not be accessed by Register Indirect mode SFRs may only be ac cesses using Direct address mode For example MOV A RO Move into the accumulator the contents of IDATA SRAM that is pointed to by the address contained in RO 3 uPSD34xx 8032 ADDRESSING MODES Immediate Addressing This mode uses 8 bits of data a constant con tained in the second byte of the instruction and stores it into the memory location or register indi cated by the first byte of the instruction Thus the data is immediately available within the instruction This mode is commonly used to initialize registers and SFRs or to perform mask operations There is also a 16 bit version of this mode for load ing the DPTR Register In this case the two bytes following the instruction byte contain the 16 bit val ue For example MOV A 40 Move the constant 40h into the accumulator MOV DPTR 1234 Move the constant 1234h into DPTR External Direct Addressing This mode will access external me
52. rial logic example which is implemented on pins of Port B To give a general idea of how PLD logic is imple mented using PSDsoft Express Figure 82 page 206 illustrates the pin declaration win dow of PSDsoft Express showing the PLD output at pin PBO declared as Combinatorial in the PLD Output section and a signal name pld out is specified The other three signals on pins PB1 PB2 and PB3 would be declared as Logic or Ad dress in the PLD Input section and given signal names In the Design Assistant window of PSDsoft Ex press shown in Figure 83 page 207 the user simply enters the logic equation for the signal pld out as shown The user can either type in the logic statements or enter them using a point and click method selecting various signal names and logic operators available in the window After PSDsoft Express has accepted and realized the logic from the equations it synthesizes the log ic statement pld out pld in 1 pld in 2 amp pld in 3 to be programmed into the GPLD See the PSD soft User s Manual for all the steps Note If a particular OMC output is specified as an internal node and not specified as a port pin output in PSDsoft Express then the port pin that is asso ciated with that OMC can be used for other I O functions Figure 81 Simple PLD Logic Example Al09178 BYR uPSD34xx PSD MODULE Figure 82 Pin Declarations in PSDsoft Express
53. shown in Table 108 page 181 The status bits can be read as many times as needed until an operation is complete The 8032 performs a READ operation to obtain these status bits while an erase or program oper ation is being executed by the state machine in side each Flash memory array Data Polling Flag DQ7 While programming ei ther Flash memory the 8032 may read the Data Polling Flag Bit DQ7 which outputs the comple ment of the D7 Bit of the byte being programmed into Flash memory Once the program operation is complete DQ7 is equal to D7 of the byte just pro grammed into Flash memory indicating the pro gram cycle has completed successfully The correct select signal FSx or CSBOOTx must be active during the entire polling procedure Polling may also be used to indicate when an erase operation has completed During an erase operation DQ7 is 0 After the erase is complete 180 264 Directing this command to any individual sector within a Flash memory array will invoke the bulk erase of all Flash memory sectors 007 is 1 The correct select signal FSx or CS BOOTx must be active during the entire polling procedure DQ7 is valid after the fourth instruction byte WRITE operation for program instruction se quence or after the sixth instruction byte WRITE operation for erase instruction sequence If all Flash memory sectors to be erased are pro tected DQ7 is reset to 0 for about 100 5 and then D
54. up counting 16 bit Ca MAX pture TH2 TL2 and store to fosc 12 Capture RCAP2H RCAP2L at falling edge on fosc 24 pin T2X Baud Rate x No overflow interrupt request TF2 Generator Extra Interrupt on pin T2X sets TF2 Off Note 1 falling edge Timer 2 stops 78 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Baud Rate Generator Mode The RCLK and or TCLK Bits in the SFR T2CON allow the transmit and receive baud rates on serial port UARTO to be derived from either Timer 1 or Timer 2 Figure 30 page 82 illustrates Baud Rate Generator Mode When TCLK 0 Timer 1 is used as UARTO s transmit baud generator When TCLK 1 Timer 2 will be the transmit baud generator RCLK has the same effect for UARTO s receive baud rate With these two bits UARTO can have different receive and transmit baud rates one generated by Timer 1 the other by Timer 2 Note Bits RCLK1 and TCLK1 in the SFR named PCON see PCON Power Control Register SFR 87h reset value OOh page 52 have identical functions as RCLK and TCLK but they apply to UART1 instead For simplicity in the following dis cussions about baud rate generation no suffix will be used when referring to SFR registers and bits related to UARTO or UART1 since each UART in terface has identical operation Example TCLK or TCLK1 will be referred to as just TCLK The Baud Rate Generator Mode is similar to the Auto reload Mode in that a roll over in TH2
55. when logic 0 is written to a bit in any of these port SFRs while in GPIO mode the corresponding port pin will enable a low side driver which pulls the pin to ground and at the same time releases the high side driver and pull ups resulting in a logic 0 output When a logic 1 is written to the SFR the low side driver is released the high side driver is enabled for just one MCU_CLK period to rapidly make the 0 to1 transition on the pin while weak active pull ups total 150KQ to Vcc are enabled This structure is consistent with standard 8051 architecture The high side driver is momentarily enabled only for 0 to 1 transitions which is implemented with the de lay function at the latch output as pictured in Fig ure 17 page 57 Figure 18 page 57 and Figure 19 page 58 After the high side driver is disabled the two weak pull ups remain enabled resulting in a logic 1 output at the pin sourcing uA to an external device Optionally an external pull up re sistor can be added if additional source current is needed while outputting a logic 1 GPIO Input To use a GPIO port pin as an input the low side driver to ground must be disabled or else the true logic level being driven on the pin by an external device will be masked always reads logic 0 So to make a port pin input ready the corresponding bit in the SFR must have been set to a logic 1 prior to reading that SFR bit as an in put A reset
56. 0 1 0 1 or2 3 4 or5 0 0 0 0 0 RESET WRITE to CAPCOMHn 1 0 WRITE to CAPCOMLn A107858 157 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM Figure 60 PWM Mode X8 Fixed Frequency CAPCOMHn CAPCOMLn 1 ENABLE _ 8 bit gt CEXn OVERFLOW PCACLm TCMMODEn EINTF MATCH TOGGLE PWM PWMO 0 0 0 0 0 107859 Note 0 m 15 0 1 or2 3 4 or5 158 264 3 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM PWM Mode X8 Programmable Frequency In this mode the PWM frequency is not deter mined by the overflow of the low byte of the Counter Instead the frequency is determined by the PWMFm Register The user can load a value in the PWMFm Register which is then compared to the low byte of the Counter If there is a match the Counter is cleared and the Load registers PWMFm CAPCOMHn are re loaded for the next PWM pulse There is only one PWMFm Register which serves all 3 TCM in a PCA block If one of the TCM modules is operating in this mode the other modules in the PCA must be con figured to the same mode or left not to be used The duty cycle of the PWM can be specified in the CAPCOMHn Register as in the PWM with fixed frequency mode Different TCM modules can have their own duty cycle
57. 1 Only name Choose Peripheral I O mode function and specify address range in DPLD for PSELx No action required in PSDsoft to get 4 pin JTAG By default TDO 4 PIN JTAG ISP TDI TCK TMS are N A dedicated JTAG functions Choose JTAG TSTAT ido ISP function for PC3 and N A rogramming JTAG TERR function for prog 9 pin PC4 PIO_EN Bit Logic 1 default is 0 Peripheral I O 202 264 MCU I O Mode In MCU mode the 8032 on the MCU Module expands its own by using the Ports on the PSD Module The 8032 can read PSD Module I O pins set the direction of the I O pins and change the output state of I O pins by ac cessing the Data In Direction and Data Out csiop registers respectively at run time To implement MCU mode each desired pin is specified in PSDsoft Express as MCU I O function and given a pin name Then 8032 firmware is writ ten to set the Direction bit for each corresponding pin during initialization routines 0 In 1 Out of the chip then the 8032 firmware simply reads the uPSD34xx PSD MODULE corresponding Data In register to determine the state of an pin or writes to a Data Out register to set the state of a pin The Direction of each pin may be changed dynamically by the 8032 if de sired A mixture of input and output pins within a single port is allowed Figure 80 page 200 shows the Data In Data Out and Direction signal paths The
58. 1572 15 20 25 103100 233 264 uPSD34xx AC DC PARAMETERS Table 149 PSD Module Example Typ Power Calculation at Vcc 5 0V Turbo Mode Off Conditions MCU Clock Frequency 12MHz Highest Composite PLD input frequency Fea AD MCU ALE frequency Freq ALE Flash memory Access SRAM access access 5 no additional power above base Operational Modes Normal 40 Power down Mode 60 Number of product terms used from fitter report 45 PT of total product terms 45 182 24 7 Turbo Mode Off Calculation using typical values Icc total Icc MCUactive x MCUactive Icc PSDactive PSDactive Ipp pwrdown x pwrdown Icc MCUactive Ipp pwrdown Icc PSDactive lcc dc flash x 2 5mA MHz x Freq ALE SRAM x 1 5mA MHz x Freq ALE PLD x from graph using Freq PLD 0 8 x 2 5mA MHz x 2MHz 0 15 x 1 5mA MHz x 2MHz 24mA 4 0 45 24 mA 28 45 20mA x 40 28 45 x 40 250 x 60 Icc total 8mA 11 38mA 1500 19 53 This is the operating power with no Flash memory Erase or Program cycles in progress Calculation is based on all pins being disconnected and lout OMA 234 264 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per manent damage to the devi
59. 16 8000h System 2100h csiop 256 bytes Common to All Pages 2000h 50 8KB Common Memory to All Pages 0000h 8000h 8 4000h 8KB 2000h 8 0000h 8KB 109176 It is also possible to reclassify the Flash memo ries during runtime moving the memories be tween XDATA memory space and program memory space on the fly This essentially means that the user can override the initial setting during run time by writing to a csiop register the VM Reg ister This is useful for IAP because standard 8051 architecture does not allow writing to pro gram space For example if the user wants to up date firmware in Main Flash memory that is residing in program space the user can temporari 172 264 ly reclassify the Main Flash memory into XDATA space to erase and rewrite it while executing IAP code from the Secondary Flash memory in pro gram space After the writing is complete the Main Flash can be reclassified back to program space then execution can continue from the new code in Main Flash memory The mapping example of Fig ure 68 will accommodate this operation Memory Sector Select Rules When defining sector select signals FSx CSBOOTx RSO CSIOP PSELx in PSDsoft Express the user must keep these rules in mind Main Flash and Secondary Flash memory sector select signals may not be larger than their physical sector size as defined in Table 101 page 166
60. 167 and also the Automatic Power Down APD page 220 PD2 can be used as a common chip select signal CSI for the Flash and SRAM memories on the PSD Module see Chip Se lect Input CSI page 222 If driven to logic 1 by an external source CSI will force all memories into standby mode regardless of what other internal memory select signals are doing on the PSD Module This is specified in PSDsoft as PSD Chip Select Input CSI Port D also supports the Fast Slew Rate output drive type option using the csiop Drive Select reg isters uPSD34xx PSD MODULE Figure 88 Port D Structure U CMOS BUFFER PIN INPUT ONE of 5 NO CSIOP HYSTERESIS REGISTERS PORT D FROM OUTPUT ENABLE OE OR ARRAY FROM PLD MODULE INPUT BUS i DIRECTION DRIVE DRIVE TYPE SELECT 1 FAST gt SLEW RATE B m o i a Voo B MCUI O a DATA OUT 10 OUTPUT 1 U 1 T ENABLE c LR TYPICAL amp PIN PORT D 4 OUTPUT B E TG KY Oo OUTPUT HN M ENABLE 55 A DIRECTION U x lt ec 1 FROM DPLD 2 TO POWER MANAGEMENT AND PLD INPUT BUS lt lt a TO POWER MANAGEMENT e PD1 PIN PD2 PIN DIRECTLY PLD INPUT BUS NO IMC lt lt 109182 Note 1 Optional function specific Port D pin 217 264 uPSD34xx PSD MO
61. 2 has two SFRs that form the 16 bit counter and perform other functions m TH2 is the high byte address CDh m TL2 is the low byte address Timer 2 has two SFRs for capture and reload m RCAP2H is the high byte address CBh m RCAP2L is the low byte address CAh Clock Sources When enabled in the Timer function the Regis ters THx and TLx are incremented every 1 12 of the oscillator frequency fosc This timer clock source is not effected by MCU clock dividers in the CCONO stalls from PFQ BC or bus transfer cy cles Timers are always clocked at 1 12 of fosc When enabled in the Counter function the Reg isters THx and TLx are incremented in response to a 1 to 0 transition sampled at their corresponding external input pin pin CO for Timer 0 pin C1 for Timer 1 or pin T2 for Timer 2 In this function the external clock input pin is sampled by the counter at a rate of 1 12 of fosc When a logic 1 is deter mined one sample and a logic 0 in the next sample period the count is incremented at the very next sample period periodi sample 1 period2 sample 0 period3 increment count while continuing to sample This means the max imum count rate is 1 24 of the fosc There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be active for at least one full sample period 12 fosc sec onds However
62. 4 Bytes of Instruction Wait Instruction Pre Fetch Queue PFQ 110431 1572 19 264 uPSD34xx 8032 MCU CORE PERFORMANCE ENHANCEMENTS Pre Fetch Queue PFQ and Branch Cache BC The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture to eliminate wasted memory fetches and to maxi mize memory bandwidth to the MCU The PFQ does this by running asynchronously in relation to the MCU looking ahead to pre fetch two bytes word of code from program memory during any idle bus periods Only necessary word will be fetched no dummy fetches like standard 8032 The PFQ will queue up to four code bytes in ad vance of execution which significantly optimizes sequential program performance However when program execution becomes non sequential pro gram branch a typical pre fetch queue will empty itself and reload new code causing the MCU to stall The Turbo uPSD34xx diminishes this prob lem by using a Branch Cache with the PFQ The BC is a four way fully associative cache meaning that when a program branch occurs its branch destination address is compared simultaneously with four recent previous branch destinations stored in the BC Each of the four cache entries contain up to four bytes of code related to a branch If there is a hit a match then all four code bytes of the matching program branch are trans ferred immediately and simultaneously from the BC to the PFQ and execution
63. 52 pin package there is no individual Vngr pin because Vref is combined with AVcc pin 10 BIT SAR ADC CONTROL ADC OUT 10 BITS 0 Lm 107856 151 264 uPSD34xx ANALOG TO DIGITAL CONVERTOR ADC Table 89 ACON Register SFR 97h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AINTF AINTEN ADEN ADS2 ADS1 ADSO ADST ADSF Details Bit Symbol AINTF AINTEN Function ADC Interrupt flag This bit must be cleared with software 0 No interrupt request 1 The AINTF flag is set when ADSF goes from 0 to 1 Interrupts CPU when both AINTF and AINTEN are set to 1 ADC Interrupt Enable 0 ADC interrupt is disabled 1 ADC interrupt is enabled ADEN ADC Enable Bit 0 ADC shut off and consumes no operating current 1 Enable ADC After ADC is enabled 16ms of calibration is needed before ADST Bit is set ADS2 0 ADST Analog channel Select 000 Select channel 0 P1 0 001 Select channel 0 P1 1 010 Select channel 0 P1 2 011 Select channel 0 P1 3 101 Select channel 0 P1 5 110 Select channel 0 P1 6 111 Select channel 0 P1 7 ADC Start Bit 0 Force to zero 1 Start ADC then after one cycle the bit is cleared to 0 ADSF ADC Status Bit 0 ADC conversion is not completed 1 ADC conversion is completed The bit can also be cleared with software 152 264
64. ALE starts pulsing again or the CSI input on PD2 transitions from logic 1 to logic 0 or the PSD Module reset signal RST transitions from logic 0 to logic 1 Various signals can be blocked prior to power down mode from entering the PLDs by using blocking bits in csiop PMMR registers All memories enter standby mode and the state of the PLDs and I O Ports are unchanged if no PLD inputs change Table 148 page 225 shows the effects of power down mode on I O pins while in various operating modes The 8032 Ports 1 3 and 4 on the MCU Module are not affected at all by power down mode in the PSD Module Power down standby current given in the AC specifications for PSD Module assume there are no transitions on any unblocked PLD input and there are no output pins driving any loads The APD counter will count whenever Bit 1 of csiop PMMRO register is set to logic 1 and when the ALE signal is steady at either logic 1 or logic 0 not transitioning Figure 90 page 222 shows the flow leading up to power down mode The only action required in PSDsoft Express to enable APD mode is to select the pin function Common Clock Input CLKIN before programming with JTAG 3 uPSD34xx PSD MODULE Forced Power Down FDP An alternative to The MCU Module must put itself into Power Down APD is FPD The resulting power savings is the mode after it puts the PSD Module into Power same but the PD
65. Bit 0 EN ALL EN PCA EOVFI PCAIDLE CLK SEL 1 0 Details Bit Symbol Function 0 No impact on TCM modules 7 EN ALL 1 Enable both PCA counters simultaneously override the EN_PCA Bits This bit is to start the two 16 bit counters in the PCA For customers who want 5 PWM for example this bit can start all of the PWM outputs 0 PCA counter is disabled 1 counter is enabled 6 EN_PCA EN_PCA Counter Run Control Bit Set with software to turn the PCA counter on Must be cleared with software to turn the PCA counter off 5 EOVFI 1 Enable Counter Overflow Interrupt if overflow flag OVF is set 0 PCA operates when CPU is in Idle Mode 4 REA 1 PCA stops running when CPU is in Idle Mode 3 Reserved 0 Select 16 bit PWM 2 TOE EM 1 Select 10 bit PWM 00 Select Prescaler clock as Counter clock 1 0 Ec 01 Select Timer 0 Overflow 10 Select External Clock pin P4 3 for MAX clock rate fosc 4 160 264 ky uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM Table 97 PCA1 Control Register PCACON1 SFR OBCh Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PCAIDLE CLK SEL 1 0 Details Bit Symbol Function 0 PCA counter is disabled 1 PCA counter is enabled 6 EN PCA EN PCA Counter Run Control Bit Set with software to turn the PCA counter on Must be cleared with software to turn the PCA counter off 5 EOVFI 1 Enable Counter Overflow In
66. CLEAR TO PLD INPUT BUS lt amp NODE FEEDBACK CFB OUTPUT MACROCELL Al06617A ky 193 264 uPSD34xx PSD MODULE OMC Allocator Outputs of the 16 OMCs can be routed to a combination of pins on Port A 80 pin devices only Port B or Port C as shown in Figure 78 OMCs are routed to port pins automatically af ter specifying pin numbers in PSDsoft Express Routing can occur on a bit by bit basis spitting OMC assignment between the ports However one OMC can be routed to one only port pin not both ports Product Term Allocator Each OMC has a Prod uct Term Allocator as shown in Figure 77 page 193 PSDsoft Express uses PT Alloca tors to give and take product terms to and from other OMCs to fit a logic design into the available silicon resources This happens automatically in PSDsoft Express but understanding how PT allo cation works will help if the logic design does not fit in which case the user may try selecting a dif ferent pin or different OMC for the logic where more product terms may be available The follow ing list summarizes how product terms are allocat ed to each as shown in Table 112 page 195 MCELLABO MCELLAB7 each have three native product terms and may borrow up to six more MCELLBCO MCELLBC3 each have four native product terms and may borrow up to five more MCELLBC4 MCELLBC7 each have four native product terms and may borrow up to six more
67. CONTENTS uPSD34xx INSTRUCTION SET SUMMARY 33 DUAL DAT A POINTERS Aere et eed HU Prem ERE cR RUE e 38 Data Pointer Control Register DPTC 85 38 Data Pointer Mode Register DPTM 86 39 DEBUG SU NUM e 40 INTERRUPT SYSTEM DIE ee eee aed lie ae eee SR OR e ade 41 Individual Interrupt 44 MCU CLOCK GENERATION 47 MCU 4e a ee 47 PERIPH CE ic Se 47 POWER SAVING MODES ee Ee ee ee 50 Idle Mode cic erre Se Ga ee M 50 Power down Mode cssc 622 lla Rb Ar E 50 Reduced Frequency 50 OSCILLATOR AND EXTERNAL COMPONENTS 53 VO PORTS of MCU MODULE wie aici be eas 54 MCU Port Operating Modes 54 MCU BUS nee eee ae ee ae ue 63 PSEN Bus Cycles 25 Weg ae es
68. DPTR1 No Change 3 2 MD 1 1 10 RW 01 Reserved 10 Auto Increment 11 Auto Decrement DPTRO Mode Bits 1 0 MD 01 00 RW 00 DPTRO No Change 01 Reserved 10 Auto Increment 11 Auto Decrement Table 15 8051 Assembly Code Example MOV R7 COUNT initialize size of data block to transfer MOV DPTR 4SOURCE ADDR load XDATA source address base into DPTRO MOV 85h 01h load DPTC to access DPTR1 pointer MOV DPTR 4DEST ADDR load XDATA destination address base into DPTR1 MOV 85h 40h load DPTC to access DPTRO pointer and auto toggle MOV 86h 0Ah load DPTM to auto increment both pointers LOOP MOovx A DPTR load XDATA byte from source into ACC after load completes DPTRO increments and DPTR switches DPTR1 MOovx QDPTR A store XDATA byte from ACC to destination after store completes DPTR1 increments and DPTR switches to DPTRO DJNZ R7 LOOP continue until done MOV 86h 400 disable auto increment MOV 85h 00 disable auto toggle now back to single DPTR mode Note 1 The code loop where the data transfer takes place is only 3 lines of code ky 39 264 uPSD34xx DEBUG UNIT DEBUG UNIT The 8032 MCU Module supports run time debug ging through the JTAG interface This same JTAG interface is also used for In System Programming ISP and the physical connections are described in the PSD Module section JTAG ISP and JTAG Debug page 226 Debugging with a serial interface s
69. Enable Endpoint 2 OUT FIFO interrupt 1 OUT1IE R W Enable Endpoint 1 OUT FIFO interrupt 0 OUTOIE R W Enable Endpoint 0 OUT FIFO interrupt 174 137 264 uPSD34xx USB INTERFACE USB IN FIFO Interrupt Enable Register UIE3 When an endpoint s IN FIFO is empty and an IN transaction to that endpoint has been received the SIE sends a NAK handshake token since there is no data ready for it to send Table 75 USB IN FIFO NAK Interrupt Enable Register UIE3 OE7h Reset Value 00h The register see Table 75 is used to enable each endpoint s IN FIFO NAK Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NAK4IE NAKSIE NAK2IE NAK1IE NAKOIE Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 NAK4IE R W Enable Endpoint 4 IN FIFO NAK interrupt 3 NAKSIE R W Enable Endpoint 3 IN FIFO NAK interrupt 2 NAK2IE R W Enable Endpoint 2 IN FIFO NAK interrupt 1 NAK1IE R W Enable Endpoint 1 IN FIFO NAK interrupt 0 NAKOIE R W Enable Endpoint 0 IN FIFO NAK interrupt 138 264 TTA USB Global Interrupt Flag Register UIFO There are many different events that generate a USB interrupt requiring a number of registers to indicate the cause of the interrupt To more efficiently identify the cause of the uPSD34xx USB INTERFACE Register see Table 76 indicates the type of interrupt that occurred Once the type of interrupt
70. FIFO that was empty numbered FIFO Interrupt flags are active Table 78 USB OUT FIFO Interrupt Flag UIF2 OEAh Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OUT4F OUT3F OUT2F OUT1F OUTOF Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved Endpoint 4 OUT FIFO Interrupt flag OUT4F iid This bit is set when the FIFO status changes from empty to full Endpoint 3 OUT FIFO Interrupt flag 3 OUT3F i This bit is set when the FIFO status changes from empty to full Endpoint 2 OUT FIFO Interrupt flag 2 OUT2F This bit is set when the FIFO status changes from empty to full Endpoint 1 OUT FIFO Interrupt flag 1 OUTIF This bit is set when the FIFO status changes from empty to full Endpoint 0 OUT FIFO Interrupt flag QUIE EM This bit is set when the FIFO status changes from empty to full 3 141 264 uPSD34xx USB INTERFACE USB IN FIFO Interrupt Flag UIF3 The USB IN FIFO NAK Interrupt Flag register see Table 79 contains flags that indicate when an IN Endpoint FIFO is not ready The Endpoint FIFO is not ready when data has not been loaded into its FIFO and the USIZE register has not been written to writing to the USIZE register puts the FIFO in a ready to send data state Until the FIFO is ready the SIE will continue to NAK all IN requests to the respective Endpoint Once set firmware must clear the flag by
71. Flag AC This flag is set when the last arithmetic operation that was executed re sults in a carry into addition or borrow from sub traction the high order nibble It is cleared by all other arithmetic operations Figure 12 Program Status Word PSW Register uPSD34xx 8032 MCU REGISTERS General Purpose Flag F0 This is a bit addres sable general purpose flag for use under software control Register Bank Select Flags RS1 RSO These bits select which bank of eight registers is used during RO R7 register accesses see Table 4 Overflow Flag OV The OV flag is set when an ADD ADDC or SUBB instruction causes a sign change a MUL instruction results in an overflow result greater than 255 a DIV instruction causes a divide by zero condition The OV flag is cleared by the ADD ADDC SUBB MUL and DIV instruc tions in all other cases The CLRV instruction will clear the OV flag at any time Parity Flag P The P flag is set if the sum of the eight bits in the Accumulator is odd and P is cleared if the sum is even Table 4 Register Bank Select Addresses 9 0 00h 07h 1 08h OFh 1 2 10h 17h 1 3 18h 1Fh MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag LSB LCY AC FO RST RSO OV Reset Value oon Parity Flag Bit not assigned Overflow Flag Register Bank Select Flags to select Bank0 3 106639 23 264
72. MIPS rate as close as possible to the peak MIPS rate at all times This is accomplished with an instruction Pre Fetch Queue PFQ a Branch Cache BC and a 16 bit program memory bus as shown in Figure 8 page 19 3 uPSD34xx 8032 MCU CORE PERFORMANCE ENHANCEMENTS Figure 7 Comparison of uPSD34xx with Standard 8032 Performance 1 or 2 byte 1 cycle Instructions Instruction 1 Instruction B 1 Instruction C Execute Instruction and Execute Instruction and Execute Instruction and Turbo uPSD34xx Pre Fetch Next Instruction Pre Fetch Next Instruction Pre Fetch Next Instruction 1 1 1 1 1 1 1 1 1 i i i 4 clocks one machine cycle machine cycle one machine cycle 1 1 1 1 1 1 1 1 1 12 clocks one machine cycle Instruction A Standard 8032 Dummy Byte is Ignored wasted bus access Turbo uPSD34xx executes instructions A B and C in the same amount of time that a standard 8032 executes only Instruction A Al10411 Figure 8 Instruction Pre Fetch Queue and Branch Cache Branch 4 Branch 4 Code Code ear fax gt Code Code Branch 2 Branch Cache Branch 2 BC Code Code Branch 1 Branch 1 Code Code Load on Branch Address Match Current Branch Address Instruction Byte 16 bit Instruction Byte Program Memory Instruction Byte on PSD Module d Address Address
73. Master Transmitter to Slave Receiver mode The arbitration process can carry on for many bit times if both Masters are addressing the same Slave de vice and will continue into the data bits if both Masters are trying to be Master Transmitter It is also possible for arbitration to carry on into the ac knowledge bits if both Masters are trying to be Master Receiver Because address and data in formation on the bus is determined by the winning Master no information is lost during the arbitration process Clock Synchronization Clock synchronization is used to synchronize arbi trating Masters or used as a handshake by a de vices to slow down the data transfer Clock Sync During Arbitration During bus ar bitration between competing Masters Master X uPSD34xx INTERFACE with the longest low period on SCL will force Master_Y to wait until Master_X finishes its low period before Master_Y proceeds to assert its high period on SCL At this point both Masters begin asserting their high period on SCL simultaneously and the Master with the shortest high period will be the first to drive SCL for the next low period In this scheme the Master with the longest low SCL pe riod paces low times and the Master with the shortest high SCL period paces the high times making synchronized arbitration possible Clock Sync During Handshaking This allows receivers in different devices to handle various transfer rates either at
74. Note The value in the Frequency Register PWM Fm must be larger than the duty cycle register CAPCOM Figure 61 PWM Mode X8 Programmable Frequency PWM FREQ COMPARE 8 CAPCOMHn PWMFm PCACLm 1 T ENABLE gt 8 bit COMPARATORm ENABLE T MALER gt CEXn TCMMODEn e cow ve cur waren Pwi Note m 0 n 0 1 or2 m 1 n 3 4 or5 ky 107860 159 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM PWM Mode Fixed Frequency 16 bit The operation of the 16 bit PWM is the same as the 8 bit PWM with fixed frequency In this mode one or all the TCM can be configured to have a fixed frequency PWM output on the port pins The PWM frequency is depending on the clock input frequency to the 16 bit Counter The duty cycle of each TCM module can be specified in the CAP COMHn and CAPCOMLn Registers When the 16 bit PCA Counter is equal or greater than the val ues in registers CAPCOMHn and CAPCOMLn the PWM output is switched to a high state When the PCA Counter overflows CEXn is asserted low PWM Mode Fixed Frequency 10 bit The 10 bit PWM logic requires that all 3 TCMs in or PCA1 operate in the same 10 bit PWM mode The 10 bit PWM operates in a similar man ner as the 16 bit PWM except the PCACHm and PCACLm counters are reconfigured as 10 bit counters The CAPCOMHn and CAP
75. PORT 1 Not 5 volt IO Tolerant 263 REVISION HISTORY eee eee ee pee dy ee 264 6 264 TA SUMMARY DESCRIPTION The Turbo Plus uPSD34xx Series combines a powerful 8051 based microcontroller with a flexi ble memory structure programmable logic and a rich peripheral mix to form an ideal embedded controller At its core is a fast 4 cycle 8032 MCU with a 4 byte instruction prefetch queue PFQ and a 4 entry fully associative branching cache BC The MCU is connected to a 16 bit internal instruc tion path to maximize performance enabling loops of code in smaller localities to execute extremely fast The 16 bit wide instruction path in the Turbo Plus Series allows double byte instructions to be fetched from memory in a single memory cycle This keeps the average performance near its peak performance peak performance for 5V 40MHz Turbo Plus uPSD34xx is 10 MIPS for single byte instructions and average performance will be ap proximately 9 MIPS for mix of single and multi byte instructions USB 2 0 full speed 12Mbps is included provid ing 10 endpoints each with its own 64 byte FIFO to maintain high data throughput Endpoint 0 Con trol Endpoint uses two of the 10 endpoints for In and Out directions the remaining eight endpoints may be allocated in any mix to either type of trans fers Bulk or Interrupt Code development is easily managed without a hardware In C
76. Preliminary MCU Module DC Characteristics Note 1 Power supply Vcc is always 3 0 to 3 6V for the MCU Module Vpp for the PSD Module may be or 5V 2 Port 1 is not 5V tolerant maximum Vcc 0 5 3 Ipp Power down Mode is measured with XTAL1 Vss XTAL2 NC RESET Vcc Port 0 Vcc all other pins are disconnected 4 Icc cPu Active Mode is measured with XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Voc 0 5V XTAL2 NC RESET Vss Port 0 Vcc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used approximately 1mA 5 Idle Mode is measured with XTAL1 driven with tci cu tcHcL 5ns Vss 0 5V Voc 0 5V XTAL2 NC RESET Vcc Port 0 Vcc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used approximately 1 All IP clocks are disabled and the MCU clock is set to fosc 2048 6 current OmA all I O pins are disconnected 238 264 Symbol Parameter Test Conditions Min Vcc Supply Voltage 3 0 High Level Input Voltage ViH Ports 0 1 3 4 XTAL1 RESET 3 0V Vcc 3 6V 0 7Vcc 5V Tolerant max voltage 5 5V Low Level Input Voltage VIL Ports 0 1 3 4 XTAL1 RESET lt SB x lo 10mA V Output Low Voltage Port 4 Ol2 Other
77. RW low 8 bits of PCA 16 bit counter A3 BB PCACHO PCACH1 RW The high 8 bits of PCA 16 bit counter Control Register Enable PCA Timer Overflow flag m Be FACON Penta RW PCA Idle Mode and Select clock source Status Register Interrupt Status flags PCASTA NA Bw Ihe Common for both PCA Block 0 and 1 9 TCMMODEO TCMMODE3 bare Compare dnd Toddl AA BE TCMMODE1 TCMMODE4 RW ee des S gge AB BF TCMMODE2 TCMMODE5 PWM Mode Select AC C1 CAPCOMLO CAPCOML3 AD C2 CAPCOMHO CAPCOMH3 RW Capture Compare registers of TCMO AF C3 CAPCOML1 CAPCOML4 3 B1 C4 CAPCOMH1 CAPCOMH4 RW Capture Compare registers of TCM1 B2 C5 CAPCOML2 CAPCOMLS5 B3 C6 2 CAPCOMHS RW Capture Compare registers of TCM2 The 8 bit register to program the PWM B4 C7 PWMFO PWMF1 RW frequency This register is used for programmable 8 bit PWM Mode only Specify the pre scaler value of PCAO or FB FC CCON2 CCON3 RW 1 clock input 155 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM PCA Clock Selection The clock input to the 16 bit up counter in the PCA block is user programmable The three clock sources are PCA Prescaler Clock PCAOCLK PCA1CLK Timer 0 Overflow External Clock Pin P4 3 or P4 7 The clock source is selected in the configuration register PCACON The Prescaler output clock PCACLK is the fosc divided by the divisor which is specified the CCON2 or CCONS
78. Timer 2 Trigger input P4 1 1 31 21 General I O port pin PCAO TCM1 T2X RXD1 5 UART1 or IrDA P4 2 TCM2 General I O port pin 2 Receive RxD1 TXD1 UART1 or IrDA P4 3 PCACLKO General I O port pin PCACLKO Transmit TxD1 SPICLK Program Counter SPI Clock Out TCM3 General VO port pin 1 1 SPICLK SPIRXD SPI Receive P4 5 TCM4 General I O port pin PCA1 TCM4 SPIRxD SPI Transmit P4 6 SPITXD General I O port pin PCA1 TCM5 SPITxD SPISEL SPI Slave Select P4 7 PCACLK1 General I O port pin PCACLK1 SPISEL Reference Voltage VREF EI input for ADC READ Signal WB WRITE Signal external bus PSEN Signal PSEN external bus ALE Address Latch signal external bus RESET IN Active low reset input XTAL1 Oscillator input pin for system clock XTAL2 Oscillator output pin for system clock to the MCU DEBUG Debug Unit PAO General I O port pin All Port A pins PA1 General I O port pin support PA2 i General I O port pin PLD Macro cell outputs or ara VO General I O port pin PLD inputs or PA4 General I O port pin Latched Address Out PA5 General I O port pin A0 A7 or PA6 0 General I O port Peripheral PA7 General I O port pin Mode PBO General I O port pin PB1 General I O port pin All Port B pins i support PB2 76 50 General I O port pin PLD Macro cell PB3 74 49 General I O port pin outputs ae gt
79. Upon a be enabled by the CPU for communication with the host over the USB Table 80 USB Control Register UCTL OECh Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USBEN VISIBLE WAKEUP Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved USB Enable 2 USBEN R W When this bit is set the USB function is enabled and the SIE responds to tokens from the host USB FIFO VISIBLE 1 VISIBLE R W When this bit is set the selected USB FIFO is accessible visible in the XDATA space Remote Wakeup Enable This bit forces a resume or K state on the USB data lines to initiate a 0 WAKEUP R W remote wake up The CPU is responsible for controlling the timing of the forced resume that must be between 10ms and 15ms Setting this bit will not cause the RESUMF Bit to be set 3 143 264 uPSD34xx USB INTERFACE USB EndpointO Status USTA The USB 0 Status register see Table 81 provides the status for events that occur on the USB that are directed to endpointO Table 81 USB Endpoint0 Status USTA OEDh Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SETUP IN OUT Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 Reserved Received Data Toggle Bit This bit indicates the toggle bit of the r
80. an interrupt occurs 1 Contents of CPUPS 2 0 automatically become 000b whenever any interrupt occurs MCUCLK Pre Scaler 000b fcu fosc Default after reset 001b ficu fosc 2 2 0 CPUPS Baws MoUs iosa 011b fucu fosc 8 100b fucu fosc 16 101b fucu fosc 32 110b fiucu fosc 1024 111b fiucu fosc 2048 Table 23 CCON1 PLL Control Register SFR FAh reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLM 3 0 PLLD 3 0 Details Bit Symbol R W Definition Lower 4 bits of the 5 bit PLLM 4 0 Multiplier Default after reset 7 4 PLLM 3 0 RW PLLM 00h PLLM 4 is in the CCONO Register 3 0 PLLD 3 0 4 bit PLL Divider Default after reset PLLD Oh 3 49 264 uPSD34xx POWER SAVING MODES POWER SAVING MODES The uPSD34xx is a combination of two die or modules each module having its own current con sumption characteristics This section describes reduced power modes for the MCU Module See the section Power Management page 168 for re duced power modes of the PSD Module Total cur rent consumption for the combined modules is determined in the DC specifications at the end of this document The MCU Module has three software selectable modes of reduced power operation m Idle Mode m Power down Mode m Reduced Frequency Mode Idle Mode Idle Mode will halt the 8032 MCU core while leav ing the MCU peripherals active Idle Mode bloc
81. and Data Space the Flash will drive 16 bit in a PSEN cycle and operates as an 8 bit memory in READ or WRITE cycle The SRAM csiop and external device are always in 8 bit data space Type of Bus Cycle Main Flash Secondary SRAM Flash PSEN Cycle Program Memory 16 bit 16 bit x Read or Write Cycle Data Memory 8 bit 8 bit 8 bit Flash Programming Cycle Flash hi di Write or Reading Status P eon n s Note x 3 175 264 uPSD34xx PSD MODULE Runtime Control Register Definitions csiop The 39 csiop registers are defined in Table 106 press Do not write to unused locations within the The 8032 can access each register by the address csiop block of 256 registers they should remain offset specified in Table 106 added to the csiop logic zero base address that was specified in PSDsoft Ex Table 106 CSIOP Registers and their Offsets in hexadecimal Register Port A Name 80 pin Port B PortC PortD Other Description Link MCU I O input mode Read to obtain Table Data In 00h 01h 10h 11h current logic level of pins on Ports A B 122 page C or D No WRITEs 203 Selects MCUI O or Latched Address Out mode Logic 0 MCU I O 1 8032 Addr Out Write to select mode Read for status Control 02h MCU I O output mode Write to set logic level on pins of Ports A B C or D Read Data Out 04h to check status This register has no effect if a port pin is driven by an OM
82. as active high or active low logic by specifying logic equations in PSDsoft Express The 8032 address and data busses are routed throughout the PSD Module as shown in Figure 62 connecting many elements on the PSD Module to the 8032 MCU The 8032 bus is not only connect ed to the memories but also to the General PLD making it possible for the 8032 to directly read and write individual logic macrocells inside the General PLD Dual Flash Memories and IAP 5034 de vices contain two independent Flash memory ar rays This means that the 8032 can read instructions from one Flash memory array while erasing or writing the other Flash memory array Concurrent operation like this enables robust re mote updates of firmware also known as In Appli cation Programming IAP IAP can occur using any uPSD34xx interface e g UART I2C SPI Concurrent memory operation also enables the designer to emulate EEPROM memory within ei ther of the two Flash memory arrays for small data sets that have frequent updates The 8032 can erase Flash memories by individual sectors or it can erase an entire Flash memory ar ray at one time Each sector in either Flash mem ory may be individually write protected blocking any WRITEs from the 8032 good for boot and start up code protection The Flash memories au tomatically go to standby between 8032 READ or WRITE accesses to conserve power Minimum erase cycles is 100K and minimum data retention is 1
83. be cleared with software TCM2 Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software INTF1 TCM1 Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software 162 264 INTFO TCMO Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM TCM Interrupts There are 8 TCM interrupts 6 match or capture in By the nature of PCA application it is unlikely that terrupts and two counter overflow interrupts The 8 many of the interrupts occur simultaneously If interrupts are ORed as one PCA interrupt to the they do the CPU has to read the interrupt flags CPU and determine which one to serve The software has to clear the interrupt flag in the Status Register after serving the interrupt Table 99 TCHMODEO TCMMODES 6 Registers Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINTF E COMP CAP PE CAP NE MATCH TOGGLE PWN 1 0 Details Bit Symbol Function 7 EINTF 1 Enable the interrupt flags INTF in the Status Register to generate an interrupt 6 E COMP 1 Enable the comparator when set 5 CAP PE 1 Enable Capture Mode a positive edge on the CEXn 4 CAP NE 1 Enable Capture Mode a negative edge on the CEXn pin 3 MATCH 1 A match from the comparator sets the INTF bi
84. by default 7 0 WDKEY W Any value other than 55h written to this SFR will enable the WDT and counting begins Table 40 WDRST Watchdog Timer Reset Counter Register SFR A6h reset value 00h WDRST 7 0 Details Definition 7 0 WDRST This SFR is the upper byte of the 24 bit WDT up counter Writing this SFR sets the upper byte of the counter to the written value and clears the lower two bytes of the counter to 0000h Counting begins when WDKEY does not contain 55h 70 264 uPSD34xx STANDARD 8032 TIMER COUNTERS STANDARD 8032 TIMER COUNTERS There are three 8032 style 16 bit Timer Counter registers Timer 0 Timer 1 Timer 2 that can be configured to operate as timers or event counters There are two additional 16 bit Timer Counters in the Programmable Counter Array PCA seePCA Block page 154 for details Standard Timer SFRs Timer 0 and Timer 1 have very similar functions and they share two SFRs for control m TCON Table 41 page 72 m TMOD Table 42 page 74 Timer 0 has two SFRs that form the 16 bit counter or that can hold reload values or that can scale the clock depending on the timer counter mode m THO is the high byte address 8Ch m TLO isthe low byte address 8Ah Timer 1 has two similar SFRs m TH1 is the high byte address 8Dh m TL1 is the low byte address 8 Timer 2 has one control SFR m T2CON Table 43 page 77 Timer
85. causes the Timer 2 registers TH2 and TL2 to be reloaded with the 16 bit value in Registers RCAP2H and RCAP2L which are preset with firmware The baud rates in UART Modes 1 and 3 are deter mined by Timer 2 s overflow rate as follows UART Mode 1 3 Baud Rate Timer 2 Overflow Rate 16 3 The timer can be configured for either timer or counter operation In the most typical applica tions it is configured for timer operation C T2 0 Timer operation is a little different for Timer 2 when it s being used as a baud rate generator In this case the baud rate is given by the formula UART Mode 1 3 Baud Rate fosc 32 x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of the SFRs RCAP2H and RCAP2L taken as a 16 bit un signed integer A roll over in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer Inter rupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode If 2 is set a 1 to 0 transition on pin T2X will set the Timer 2 interrupt flag EXF2 but will not cause a reload from RCAP2H and RCAP2L to TH2 and TL2 Thus when Timer 2 is in use as a baud rate generator the pin T2X can be used as an extra external interrupt if desired When Timer 2 is running TR2 1 in a timer function in the Baud Rate Generator Mode firm ware should not read or write TH2 or TL2 Under these conditions the results of a read or write may not be accu
86. channel is active and JTAG channel is active and JTAG channel is active and available available available Register Power Up Reset Warm Reset APD Power down Mode and PMMR2 Cleared to 00 Unchanged Unchanged Output of OMC Flip flops Cleared to 0 Depends on re and pr Depends on re and pr equations equations Initialized with value that Initialized with value that 1 VM Register was specified in PSDsoft was specified in PSDsoft Unchanged All other csiop registers Cleared to 00h Cleared to 00h Unchanged Note 1 VM register Bit 7 PIO_EN and Bit 0 SRAM in 8032 program space are cleared to zero at power up and warm reset conditions 225 264 uPSD34xx PSD MODULE JTAG ISP and JTAG Debug An IEEE 1149 1 serial JTAG interface is used on uPSD34xx devic es for ISP In System Programming of the PSD module and also for debugging firmware on the MCU Module IEEE 1149 1 Boundary Scan oper ations are not supported in the uPSD34xx The main advantage of JTAG ISP is that a blank uPSD34xx device may be soldered to a circuit board and programmed with no involvement of the 8032 meaning that no 8032 firmware needs to be present for ISP This is good for manufacturing for field updates and for easy code development in the lab JTAG based programmers and debug gers for uPSD34xx are available from STMicro electronics and 3rd party vendors ISP is different than IAP In App
87. comparator and three internal DACs The unit has 8 input channels with 10 bit resolution The A D converter has its own Vref input 80 pin package only which specifies the voltage reference for the A D operations The analog to digital converter A D allows conversion of an analog input to a corre sponding 10 bit digital value The A D module has eight analog inputs P1 0 through P1 7 to an 8x1 multiplexor One ADC channel is selected by the bits in the configuration register The converter generates a 10 bits result via successive approxi mation The analog supply voltage is connected to the Vref input which powers the resistance lad der in the A D module The A D module has 3 registers the control regis ter ACON the A D result register ADATO and the second A D result register ADAT1 The ADATO Register stores Bits 0 7 of the converter output Bits 8 9 are stored in Bits 0 1 of the ADAT1 Reg ister The ACON Register controls the operation of the A D converter module Three of the bits in the ACON Register select the analog channel inputs and the remaining bits control the converter oper ation ADC channel pin input is enabled by setting the corresponding bit in the P1SFSO and P1SFS1 Registers to 1 and the channel select bits in the ACON Register The ADC reference clock ADCCLK is generated from fosc divided by the divider in the ADCPS Figure 57 10 Bit ADC Pii
88. data xmit buff er set count xmit buf pointer to data buf length number of bytes to xmit Set global variables to indicate Mas ter Xmitter I2C xmitter 1 I2C master 0 Enable SIOE SFR S1CON INI1 1 Prepare to Xmit first data byte SFR S1DAT 7 0 xmit_buf 0 Enable All Interrupts and go do some thing else SFR IE EA 1 Slave Receiver Disable all interrupts SFR IE EA 0 Set pointer to global data recv buff er set count recv_buf pointer to data buf length number of bytes to recv Set global variables to indicate Mas ter Xmitter I2C xmitter 0 I2C master 0 Enable SIOE SFR 51 1 1 Enable All Interrupts and go do some thing else SFR IE EA 1 112 264 Interrupt Service Routine ISR typical interrupt service routine would handle a interrupt for any of the four combinations of Master Slave and Transmitter Receiver In the example routines above the firmware sets global variables I2C master and 2 xmitter before enabling in terrupts These flags tell the ISR which one of the four cases to process Following is pseudo code for high level steps in the 2 ISR Begin C ISR lt interrupt just occurred Clear I2C interrupt flag S1STA INTR 0 Read status of SIOE put in to vari able status status SISTA Read global v
89. devices Table 126 MCU I O Mode Port A Data Out Register address csiop offset 04h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO Note 1 Port A not available on 52 pin uPSD34xx devices 2 For each bit 1 drive port pin to logic 1 0 drive port pin to logic 0 3 Default state of register is 00 after reset or power up Table 127 MCU I O Mode Port B Data Out Register address csiop offset 05h Note 1 For each bit 1 drive port pin to logic 1 0 drive port pin to logic 0 2 Default state of register is 00 after reset or power up y 203 264 uPSD34xx PSD MODULE Table 128 MCU I O Mode Port C Data Out Register address csiop offset 12h Note 1 For each bit 1 drive port pin to logic 1 0 drive port pin to logic 0 2 Default state of register is 00 after reset or power up Table 129 MCU I O Mode Port D Data Out Register address csiop offset 13h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N A N A N A N A N A 2 3 PD1 N A Note 1 For each bit 1 drive port pin to logic 1 0 drive port pin to logic 0 2 Default state for register is OOh after reset or power up 3 Not available on 52 pin uPSD34xx devices Table 130 MCU I O Mode Port A Direction Register address csiop offset 06h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PA7 PA6 PA5
90. ee 63 READ or WRITE Bus 63 Connecting External Devices to the MCU 63 Programmable Bus 64 Controlling the PFQ and 64 SUPERVISORY 5 67 External Reset Input Pin 67 Low Vcc Voltage Detect 68 Power up Heset 5 12 9 x LIRE Gg xe meae RR ween S 68 2 22 2 ere ee eee rh Rx 68 Watchdog Timer 68 STANDARD 8032 TIMER COUNTERS 71 Standard Timer SFRS 2226 23205 shee 4e RELIER AT ERE REED Re ERE 71 COCK SOUICOS ERR 71 SER ICON er et re ere ee ARE oe ee aaa er RR NERA AR RES 73 SER TMOD cto oti tat ene he ied 73 Timer 0 and Timer 1 Operating Modes 73 Timer2 lei 76 4 264 ky uPSD34xx TABLE OF CONTENTS SERIAL UART INTERFACES 2 22
91. flows are separated to pro vide better bus utilization For example one communication flow is used for managing the de vice while another is for transferring data related to the operation of the device Some bus access is used for each communication flow with each flow terminated at an endpoint on a device Each end point has various aspects associated with the communication flow A USB device looks like a collection of endpoints to the USB system Endpoints Each USB device contains a collec tion of independent endpoints with an endpoint being the destination of a communication flow be tween client software and the device By design each USB device s endpoints are given specific unique identifiers called endpoint numbers In ad dition each endpoint has an associated direction for the data flow either in from device to host or out from host to device At the time a device is connected to the USB it is assigned a unique ad dress The combination of the device address endpoint number and direction allows each end point to be uniquely referenced Each endpoint has some associated characteris tics for the communication flow with the client soft ware running on the host Those characteristics include m Endpoint number m Frequency and latency requirements m Bandwidth requirements 3 uPSD34xx USB INTERFACE Maximum packet size capability Error handling requirements Data transfer direction and Transfe
92. for Simple PLD Example Definitions Bf xl Define each pin by repeating the following steps Step 2 Pin Function standard pins already defined Define the pin function then click the Step 1 Select a pin on the chip diagram below Add Update button Return to step 1 repeat for next pin Pin Function CPLD Input p34 Logie or address p33 Latched address p32 C 1 PT clocked register pict PT clocked latch nl CPLD Output Combinatorial 21 5 el C D type register C T type register Ss SR type register JK type register 1 Extemal chip select Active Hi nez C Extemal chip select Active Lo debug pin Other eec c Ress 45272 ReseLIn C _Resetin GPI O mode with pin enable Latched address out 206 264 uPSD34xx PSD MODULE Figure 83 Using the Design Assistant in PSDsoft Express for Simple PLD Example Design Assistant 19 out out Output enable pld in 1 pld in 2 amp lpld in 3 207 264 uPSD34xx PSD MODULE Latched Address Output Mode In the MCU Module the data bus Bits DO D15 are multiplexed with the address Bits AO A15 and the ALE signal is used to separate them with respect to time Sometimes it is necessary to send de multiplexed address signals to external peripherals or memory devices Latched Add
93. has identical operation Example SBUFO and SBUF1 will be referred to as just SBUF Each UART serial port can be full duplex meaning it can transmit and receive simultaneously Each UART is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the SBUF Register However if the first byte still has not been read by the time reception of the second byte is complete one of the bytes will be lost UART Operation Modes Each UART can operate in one of four modes one mode is synchronous and the others are asyn chronous as shown in Table 46 Table 46 UART Operating Modes uPSD34xx SERIAL UART INTERFACES Mode 0 Mode 0 provides asynchronous half du plex operation Serial data is both transmitted and received on the RxD pin The TxD pin outputs a shift clock for both transmit and receive directions thus the MCU must be the master Eight bits are transmitted received LSB first The baud rate is fixed at 1 12 of fosc Mode 1 Mode 1 provides standard asynchro nous full duplex communication using a total of 10 bits per data byte Data is transmitted through TxD and received through RxD with a Start Bit logic 0 eight data bits LSB first and a Stop Bit logic 19 Upon receive the eight data bits go into the SFR SBUF and the Stop Bit goes into bit RB8 of the SFR SCON The baud rate is variable and de rived from overflows of Timer 1 or Timer 2 Mod
94. if MCU_CLK is divided by the SFR CCONO then the sample period must be cal culated based on the resultant longer frequency In this case an external clock signal on pins CO C1 or T2 should have a duration longer than one MCU machine cycle tuAcH The section Watchdog Timer WDT page 68 explains how to estimate tuACH CYC 71 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Table 41 TCON Timer Control Register SFR 88h reset value 00h IE1 IT1 IEO ITO TF1 TR1 TFO TRO Details Bit Symbol R W Definition Timer 1 overflow interrupt flag Set by hardware upon overflow 7 TF1 R Automatically cleared by hardware after firmware services the interrupt for Timer 1 6 TR1 RW Timer 1 run control 1 Timer Counter 1 is on 0 Timer Counter 1 is off Timer 0 overflow interrupt flag Set by hardware upon overflow 5 TFO R Automatically cleared by hardware after firmware services the interrupt for Timer 0 4 TRO RW Timer 0 run control 1 Timer Counter 0 is on 0 Timer Counter 0 is off Interrupt flag for external interrupt pin EXTINT1 Set by hardware when 3 IE1 R edge is detected on pin Automatically cleared by hardware after firmware services interrupt Trigger type for external interrupt pin 1 falling edge 0 low 2 IT1 RW level Interrupt flag for external interrupt pin EXTINTO Set by hardware when 1 IEO R edge is detected on pin Automatically cleared by ha
95. if desired 101 264 uPSD34xx INTERFACE Serial l O Engine SIOE At the heart of the interface is the hardware m SISTA Interface Status Table SIOE shown in Figure 43 The SIOE automatically 56 page 106 handles low level bus protocol data shifting S1DAT Data Shift Register Table handshaking arbitration clock generation and 57 page 107 synchronization and it is controlled and monitored m 1 Device Address Table by five SFRs 58 page 107 The five SFRs shown in Figure 43 are m SISETUP Sampling Rate Table m S1CON Interface Control Table 59 page 108 54 page 103 Figure 43 Interface SIOE Block Diagram INTR to 8032 8 S1STA Interface Status S1CON Interface Control S1SETUP Sample Rate 8 SCL P3 7 5 Control START Condition E Open Drain Input gt 2 Output Syne Periph Timing and Clock Control fosc Clock Generation SDA P3 6 Mi 8032 MCU Bus Open n Serial DATA IN Drain Input 8 Output BR Shift Direction n 3 ET Serial DATA OUT ACK b7 S1DAT Shift Register 7 8 S1ADR Device Address 109626 1572 102 264 uPSD34xx INTERFACE Interface Control Register 51 Table 54 Serial Control Register S1CON SFR DCh Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit
96. is the Industrial range 40 C to 85 C 2 264 uPSD34xx TABLE OF CONTENTS TABLE OF CONTENTS FEATURES SUMMARY Ry canine Re ed cee ee 1 TABLE OF CONTENTS Site ae hie Share ee eae See Eu 3 SUMMARY DESCRIPTION EET I ee Pies 7 2 2 lt Tad eed ie ae eta cams 9 HARDWARE DESCRIPTION 14 MEMORY ORGANIZATION 16 Internal Memory MCU Module Standard 8032 Memory DATA IDATA SFR 17 External Memory PSD Module Program memory Data 17 8032 MCU CORE PERFORMANCE ENHANCEMENTS 18 Pre Fetch Queue PFQ and Branch Cache 20 PFQ Example Multi cycle 20 Aggregate 20 MCU MODULE DISCRIPTION 22 8032 MCU REGISTERS sited pene Sec ean ee he A ee ee ae 22 Sta k Pointer SP a es See 22 Data Pointer DPTR elc ate ere LEA ee a eee 22 Program Counter PC curie sack eae to
97. may be generated from uPSD34xx GPIO outputs one for each Slave or from the PLD outputs of the PSD Module Figure 44 illus trates three examples of SPI device connections using the uPSD34xx m Single Master Single Slave with SPISEL m Single Master Single Slave without SPISEL m Single Master Multiple Slave without SPISEL SPI Bus SPIRxD SPITxD SPICLK SPISEL uPSD34xx SPI Slave SPI Master Device Single Master Single Slave with SPISEL SPI Bus SPIRxD SPITxD SPICLK GPIO or PLD uPSD34xx SPI Master GPIO or PLD Single Master Multiple Slave without SPISEL SPI Bus SPIRxD SPITxD SPICLK SPI Slave Device uPSD34xx SPI Master Single Master Single Slave without SPISEL SPI Slave Device SPI Slave Device AI07853b 115 264 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE SPI Bus Features and Communication Flow The SPICLK signal is a gated clock generated from the uPSD34xx Master and regulates the flow of data bits The Master may transmit at a va riety of baud rates and the SPICLK signal will clock one period for each bit of transmitted data Data is shifted on one edge of SPICLK and sam pled on the opposite edge The SPITXD signal is generated by the Master and received by the Slave device The SPIRxD signal is generated by the Slave device and received by the Master There may be no more than one Slave device transmitting data on SPIRxD at any given ti
98. of individual Secondary Flash memory segments the SRAM or the group of csiop registers when the 8032 presents an ad dress to DPLD inputs see Figure 75 page 190 The DPLD can also optionally drive external chip select signals on Port D pins The DPLD also op tionally produces two select signals PSELO and PSEL1 used to enable a special data bus repeat er function on Port A referred to as Peripheral I O Mode There are 69 DPLD input signals which in clude 8032 address and control signals Page Register outputs PSD Module Port pin inputs and GPLD logic feedback PLD 2 General PLD GPLD This program mable logic is used to create both combinatorial and sequential general purpose logic see Figure 76 page 192 The GPLD contains 16 Output Macrocells OMCs and 20 Input Macrocells IMCs Output Macrocell registers are unique in that they have direct connection to the 8032 data bus allowing them to be loaded and read directly by the 8032 at runtime through OMC registers in csiop This direct access is good for making small peripheral devices shifters counters state ma chines etc that are accessed directly by the 8032 with little overhead There are 69 GPLD inputs which include 8032 address and control signals Page Register outputs PSD Module Port pin in puts and GPLD feedback OMCs There are two banks of eight OMCs inside the GPLD MCELLAB and MCELLBC totalling 16 OMCs all together Each individual OMC is a bas
99. offset 03h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 addr or addr 5 addr A4 or A14 A13 A12 addr A7 or A15 addr A3 or PB3 PB2 PB1 PBO Addr A2 or addr A1 or addr AO or A11 A10 A9 A8 Note 1 For each bit 1 drive demuxed 8032 address signal on pin 0 pin is default mode MCU I O 2 Default state for register is OOh after reset or power up 208 264 Peripheral I O Mode This mode will provide a data bus repeater function for the 8032 to interface with external parallel peripherals The mode is only available on Port A 80 pin devices only and the data bus signals DO D7 are de multiplexed no address 0 7 When active this mode be haves like a bidirectional buffer with the direction automatically controlled by the 8032 RD and WR signals for a specified address range The DPLD signals PSELO and PSEL1 determine this address range Figure 80 page 200 shows the action of Peripheral I O mode on the Output Enable logic of the tri state output driver for a single port pin Fig ure 84 page 209 illustrates data repeater the op eration To activate this mode choose the pin function Peripheral I O Mode in PSDsoft Express on any Port A pin all eight pins of Port A will auto matically change to this mode Next in PSDsoft specify an address range for the PSELx signals in the Chip Select section of the Design Assistant The user can s
100. operation containing the Bypass Un lock command 20h as shown Table 107 page 179 The Flash memory array that re ceived that sequence then enters the Bypass Un lock mode After this a two bus cycle program operation is all that is required to program a byte in this mode The first bus cycle in this shortened program instruction sequence contains the By passed Unlocked Program command AOh to any valid address within the unlocked Flash array The second bus cycle contains the address and data of the byte to be programmed Programming status 184 264 is checked using toggle polling or Ready Busy just as before Additional data bytes are pro grammed the same way until this Bypass Unlock mode is exited To exit Bypass Unlock mode the system must is sue the Reset Bypass Unlock instruction se quence The first bus cycle of this instruction must write 90h to any valid address within the unlocked Flash Array the second bus cycle must write to any valid address within the unlocked Flash Ar ray After this sequence the Flash returns to Read Array mode During Bypass Unlock Mode only the Bypassed Unlock Program instruction or the Reset Bypass Unlock instruction is valid other instruction will be ignored Erasing Flash Memory Flash memory may be erased sector by sector or an entire Flash memo ry array may be erased with one command bulk Flash Bulk Erase The Flash Bulk Erase instruc tion sequenc
101. overflow pulses for its transmit clock in Modes 1 and 3 TCLK 0 Timer 1 overflow is used for transmit clock EXEN2 TR2 R W R W Timer 2 External Enable When EXEN2 1 capture or reload results when negative edge on pin T2X occurs EXEN2 0 causes Timer 2 to ignore events at pin T2X Timer 2 run control 1 Timer Counter 2 is on 0 Timer Counter 2 is off C T2 CP RL2 RW RW Counter or Timer function select When C T2 0 function is timer clocked by internal clock When C T2 1 function is counter clocked by signal sampled on external pin T2 Capture Reload When CP RL2 1 capture occurs on negative transition at pin T2X if EXEN2 1 When CP RL2 0 auto reload occurs when Timer 2 overflows or on negative transition at pin T2X when EXEN2 1 When RCLK 1 or TCLK 1 CP RL2 is ignored and Timer 2 is forced to auto reload upon Timer 2 overflow Note 1 The RCLK1 and TCLK1 3 Bits in the SFR named PCON control UART1 and have the exact same function and TCLK 77 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Table 44 Timer Counter 2 Operating Modes Bits in SFR Input Clock Counter Mode Remarks Timer External Internal Pin T2 P1 0 reload RCAP2H RCAP2L to TH2 16 bit TL2 upon overflow up counting MAX Auto reload reload RCAP2H RCAP2L to TH2 fosc 24 TL2 at falling edge on pin T2X 16 bit Timer Counter
102. part of a read modify write instruction and the write destination is a bit or bits in a port SFR These instructions are ANL ORL XRL JBC CPL INC DEC DJNZ MOV CLR and SETB All other types of reads to port SFRs will read the ac tual pin logic level and not the port latch This is consistent with 8051 architecture 55 264 uPSD34xx I O PORTS of MCU MODULE Figure 16 MCU Module Port Pin Function Routing MCU Module Ports ADC 8 O geht SO P GPIO 8 Q SFR NO P3 UARTO 2 TIMERO 1 4 2 2 C SFR 8 1 TIMER 2 UART1 2 SPI 4 P4 8032 MCU Low Addr amp Data 7 0 8 CORE gt 8 Hi Address 15 8 Available on PSD Module Pins RD WR PSEN ALE E 56 264 On 80 pin Devices Only AI09199b uPSD34xx I O PORTS of MCU MODULE Figure 17 MCU I O Cell Block Diagram for Port 1 Select_Alternate_Func gt _ gt DELAY gt 1MCU CLK WEAK STONGER PULL UP B PULL UP A Digital Alt Func Data gt P1 X SFR Read Latch gt _ gt for R M W instructions HIGH SIDE P1 X Pin LN LOW SIDE 2 MCU_Reset gt gt 8032 Data Bus Bit lt GPIO P1 X SFR Write Latch P1 X SFR Read Pin gt gt Digital Pin Data In lt _ lt Analog Pin In lt _ lt 109600 Figure 18 MCU I O Cell Block Diagram for Port 3 Disables High Side Driver Enable_I C gt gt D
103. pin input changes state The user can configure the counter value to be loaded by positive edge negative edge or any transition of the input signal At loading the TCM can generate an interrupt if it is enabled Timer Mode The TCM modules can be configured as software timers by enable the comparator The user writes a value to the CAPCOM registers which is then compared with the 16 bit counter If there is a match an interrupt can be generated to CPU Figure 59 Timer Mode CAPCOMHn CAPCOMLn ENABLE 16 bit COMPARATOR res 16 bit up Timer Counter PCASTA INTR MATCH Toggle Mode In this mode the user writes a value to the TCM s CAPCOM registers and enables the comparator When there is a match with the Counter output the output of the TCM pin toggles This mode is a sim ple extension of the Timer Mode PWM Mode X8 Fixed Frequency In this mode one or all the TCM s can be config ured to have a fixed frequency PWM output on the port pins The PWM frequency depends on when the low byte of the Counter overflows modulo 256 The duty cycle of each TCM module can be specified in the CAPCOMHn Register When the PCA_Counter_L value is equal to or greater than the value in CAPCOMHn the PWM output is switched to a high state When the PCA_Counter_L Register overflows the content in CAPCOMHn is loaded to CAPCOMLn and a new PWM pulse starts TCMMODEn D EN_FLAG 4 Note
104. regardless if it needs them or not dummy fetch This means for one byte one cycle instruc tions the second byte is ignored These one byte one cycle instructions account for half of the 8032 s instructions 126 out of 255 opcodes There are inefficiencies due to wasted bus cycles and idle bus times that can be eliminated The uPSD34xx 8032 MCU core offers increased performance in a number of ways while keeping the exact same instruction set as the standard 8032 all opcodes the number of bytes per in 18 264 struction and the native number a machine cycles per instruction are identical to the original 8032 The first way performance is boosted is by reduc ing the machine cycle period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032 This shortened machine cycle improves the instruction rate for one or two byte one cycle in structions by a factor of three Figure 7 page 19 compared to standard 8051 architectures and sig nificantly improves performance of multiple cycle instruction types The example in Figure 7 shows a continuous exe cution stream of one or two byte one cycle in structions The 5V uPSD34xx will yield 10 MIPS peak performance in this case while operating at 40MHz clock rate In a typical application however the effective performance will be lower since pro grams do not use only one cycle instructions but special techniques are implemented in the uPSD34xx to keep the effective
105. set the FIFO that is accessible in the 64 byte XDATA space segment is the FIFO selected by the USEL register The USEL register contains two fields used for selecting the accessi ble FIFO The EP field determines the Endpoint selected and the DIR Bit selects the IN or OUT FIFO associated with the Endpoint Accessing FIFO Control Registers UCON and USIZE Each of the 10 Endpoint FIFOs has an as sociated USB Endpoint Control Register UCON OF1H and a USB FIFO Valid Size Register USIZE OF2H The USB Endpoint Select Regis ter USEL is not only used to select the Endpoint FIFO that is accessible in the XDATA space but also selects the associated Endpoint s UCON and USIZE registers that are accessible at SFR ad dresses OF1H and OF2H 132 264 Accessing the Setup Command Buffer Setup Packets are sent from the host to a device s EndpointO and consist of 8 bytes of command da ta When the SIE receives a Setup packet from the host it stores the 8 bytes of data in the Command Buffer The command buffer is accessed via the indexed USB Setup Command Value register US CV The USB Setup Command Index register USCI is used to select the byte from the com mand buffer that is read when accessing the USCV register USB Registers The USB module is controlled via registers mapped into the SFR space The USB SFRs con sist of the following UADDR USB device address UPAIR USB FIFO pairing control UIEO 3 USB in
106. significant power savings are realized Going to Non Turbo mode may require an additional wait state in the 8032 SFR BUSCON because memory decode signals are also delayed The default state of the Turbo Bit is logic 0 meaning by default the GPLD is in fast Turbo mode until the user turns off Turbo mode Additionally bits in csiop registers PMMRO and 2 can be set by the 8032 to selectively block signals from entering both PLDs which fur ther reduces power consumption There is also an Automatic Power Down counter that detects lack of 8032 activity and reduces power consumption on the PSD Module to its lowest level see Power Management page 168 3 Security and NVM Sector Protection A pro grammable security bit in the PSD Module pro tects its contents from unauthorized viewing and copying The security bit is specified in PSDsoft Express and programmed into the uPSD34xx with JTAG Once set the security bit will block access of JTAG programming equipment to the PSD Mod ule Flash memory and PLD configuration and also blocks JTAG debugging access to the MCU Mod ule The only way to defeat the security bit is to erase the entire PSD Module using JTAG the erase command is the only JTAG command al lowed after the security bit has been set after which the device is blank and may be used again Additionally and independently the contents of each individual Flash memory sector can be write protected sector protectio
107. summarizes the status of pins and peripherals during Idle and Power down Modes on the MCU Module Table 25 page 51 shows the state of 8032 MCU address data and control signals during these modes Reduced Frequency Mode The 8032 MCU consumes less current when oper ating at a lower clock frequency The MCU can re duce its own clock frequency at run time by writing to three bits CPUPS 2 0 in the SFR named CCONO described in Table 22 page 49 These bits effectively divide the clock frequency fosc coming in from the external crystal or oscillator de vice The clock division range is from 1 2 to 1 2048 and the resulting frequency is ficu This MCU clock division does not affect any of the peripherals except for the WTD The clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 14 page 48 1572 MCU firmware may reduce the MCU clock fre quency at run time to consume less current when performing tasks that are not time critical and then restore full clock frequency as required to perform urgent tasks Returning to full clock frequency is done automat ically upon an MCU interrupt if the CPUAR Bit in the SFR named CCONO is set the interrupt will force CPUPS 2 0 000 This is an excellent way to conserve power using a low frequency clock un uPSD34xx POWER SAVING MODES til an event occurs that requires full performance See Table 22 page 49 for details on CPUAR See the DC
108. two different configurations of the JTAG inter face m 4 pin TDI TMS m 6 pin Signals above plus TSTAT TERR At power up the four basic JTAG signals are all in puts waiting for a command to appear on the JTAG bus from programming or test equipment When the enabling command is received be comes an output and the JTAG channel is fully functional The same command that enables the JTAG channel may optionally enable the two addi tional signals TSTAT and TERR uPSD34xx PSD MODULE 4 pin JTAG ISP default The four basic JTAG pins on Port C are enabled for JTAG operation at all times These pins may not be used for other O functions There is no action needed in PSDsoft Express to configure a device to use 4 pin JTAG as this is the default condition No 8032 firmware is needed to use 4 pin ISP because all ISP func tions are controlled from the external JTAG pro gram test equipment Figure 92 shows recommended connections on a circuit board to a JTAG program test tool using 4 pin JTAG It is re quired to connect the RST output signal from the JTAG program test equipment to the RESET IN input on the uPSD34xx The RST signal is driven by the equipment with an Open Drain driver allow ing other sources like a push button to drive RESET IN without conflict Note The recommended pull up resistors and de coupling capacitor are illustrated in Figure 92 Figure 92 Recommended 4 pi
109. uPSD34xx ANALOG TO DIGITAL CONVERTOR ADC Table 90 ADCPS Register Details SFR 94h Reset Value 00h Bit Symbol Function 7 4 Reserved ADC Conversion Reference Clock Enable 3 ADCCE o ADC reference clock is disabled default 1 ADC reference clock is enabled ADC Reference Clock PreScaler Only three Prescaler values are allowed 20 ADCPSI2 0 nly e Prescaler values are allowe ADCPS 2 0 0 for fosc frequency 16 2 or less Resulting ADC clock is fosc ADCPS 2 0 1 for fosc frequency 32MHz or less Resulting ADC clock is fosc 2 ADCPS 2 0 2 for fosc frequency 32MHz gt 40MHz Resulting ADC clock is fosc 4 Table 91 ADATO Register SFR 95h Reset Value 00h Bit Symbol Function 7 0 Store ADC output Bit 7 0 Table 92 ADAT1 Register SFR 96h Reset Value 00h Bit Symbol Function 7 2 Reserved 1 0 Store ADC output Bit 9 8 3 153 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM PROGRAMMABLE COUNTER ARRAY PCA WITH PWM There are two Programmable Counter Array blocks PCAO and PCA1 in the uPSD34xx A PCA block consists of a 16 bit up counter which is shared by three TCM Timer Counter Module A TCM can be programmed to perform one of the following four functions 1 Capture Mode capture counter values by external input signals 2 Timer Mode 3 Toggle Output Mode 4 PWM Mode fixed frequency 8 bit or 16 bit programmable frequency 8 bit on
110. will not automatically be generated by the SIOE The STOP condition must be generated with S1CON STO 1 SLV Slave Mode flag SLV 1 when the SIOE is in Slave mode SLV 0 when the SIOE is in Master mode default 106 264 Data Shift Register S1DAT The S1ADR register Table 57 holds a byte of se rial data to be transmitted or it holds a serial byte that has just been received The MCU may access S1DAT while the SIOE is not in the process of shifting a byte the INTR flag indicates shifting is complete While transmitting bytes are shifted out MSB first and when receiving bytes are shifted in MSB first through the Acknowledge Bit register as shown in Figure 43 page 102 Bus Wait Condition After the SIOE finishes re ceiving a byte in Receive mode or transmitting a byte in Transmit mode the INTR flag in S1STA uPSD34xx INTERFACE is set and automatically a wait condition is im posed on the IC bus SCL held low SIOE In Transmit mode this wait condition is released as soon as the MCU writes any byte to S1DAT In Re ceive mode the wait condition is released as soon as the MCU reads the S1DAT register This method allows the user to handle transmit and receive operations within an interrupt service routine The SIOE will automatically stall the 2 bus at the appropriate time giving the MCU time to get the next byte ready to transmit or time to read the byte that
111. with 12C Interface Device with 12C Interface Interface 109623 Note 1 For 3 3V system connect Rp to 3 3V Vcc For 5 0V system connect Rp to 5 0V Vpp 98 264 Communication Flow 2 data flow control is based on the fact that all 2 compatible devices will drive the bus lines with open drain or open collector line drivers pulled up with external resistors creating a wired AND situation This means that either bus line SDA or SCL will be at a logic 1 level only when no 2 de vice is actively driving the line to logic 0 The logic for handshaking arbitration synchronization and collision detection is implemented by each 2 de vice having 1 The ability to hold a line low against the will of the other devices who are trying to assert the line high 2 The ability of a device to detect that another device is driving the line low against its will Assert high means the driver releases the line and external pull ups passively raise the signal to logic 1 Holding low means the open drain driver is actively pulling the signal to ground for a logic 0 For example if a Slave device cannot transmit or receive a byte because it is distracted by and inter rupt or it has to wait for some process to complete it can hold the SCL clock line low Even though the Master device is generating the SCL clock the Master will sense that the Slave is holding the SCL line low against the will of the
112. writing a 0 to the appropriate bit When FIFOs are paired only the odd numbered FIFO Interrupt Flags are active Table 79 USB IN FIFO NAK Interrupt Flag UIF3 OEBh Reset Value 00h 4 NAK4F R W 3 NAKSF R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NAK4F 2 NAK1F NAKOF Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved Endpoint 4 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready Endpoint 3 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready 2 NAK2F R W 1 NAK1F R W 0 NAKOF R W Endpoint 2 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready Endpoint 1 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready Endpoint 0 IN FIFO NAK Interrupt flag This bit is set when the SIE responded to an IN request with a NAK since the FIFO was not ready 142 264 USB Control Register The USB Control Register see Table 80 is reset the USB module is disabled and must used to enable the SIE make the Endpoint FIFOs visible in the XDATA space and for uPSD34xx USB INTERFACE generating a remote wakeup signal
113. 0 F2 USIZE SIZE 6 0 00 F3 UBASEH BASEADDR 15 8 00 F4 UBASEL BASEADDR T7 6 0 0 0 0 00 F5 USCI USCI 2 0 00 F6 USCV USCV 7 0 00 F7 RESERVED F8 RESERVED CPU Table F9 PLLM 4 DBGCE iR CPUPS 2 0 50 22 page FA PLLM 3 0 PLLD 3 0 00 Table FB PCAOPS 3 0 10 94 page 156 Table FC CCON3 PCA1CE PCA1PS 3 0 10 95 page 156 FD RESERVED FE RESERVED FF RESERVED FE RESERVED FF RESERVED Note 1 This SFR can be addressed by individual bits Bit Address mode or addressed by the entire byte Direct Address mode 30 264 8032 ADDRESSING MODES The 8032 MCU uses 11 different addressing modes listed below m Register Direct Register Indirect Immediate External Direct External Indirect Indexed Relative Absolute Long Bit Register Addressing This mode uses the contents of one of the regis ters RO R7 selected by the last three bits in the instruction opcode as the operand source or des tination This mode is very efficient since an addi tional instruction byte is not needed to identify the operand For example MOV A R7 Move contents of R7 to accumulator Direct Addressing This mode uses an 8 bit address which is con tained in the second byte of the instruction to di rectly address an operand which resides in either 8032 DATA SRAM internal address range 00 07Fh or resides 8032 SFR internal address range 80h FFh This mode is quite fast since the
114. 09187 230 264 Chaining uPSD34xx Devices It is possible to chain uPSD34xx device with other uPSD34xx devices on a circuit board and also chain with IEEE 1149 1 compliant devices from other manu facturers Figure 95 page 231 shows a chaining example The TDO of one device connects to the TDI of the next device and so on Only one device is performing JTAG operations at any given time while the other two devices are in BYPASS mode Configuration for JTAG chaining can be made in PSDsoft Express by choosing More than one de vice when prompted about chaining devices No tice in Figure 95 page 231 that the uPSD34xx devices are chained externally but also be aware that the two die within each uUPSD34xx device are chained internally This internal chaining of die is transparent to the user and is taken care of by PS Dsoft Express and 3rd party JTAG tool software The example in Figure 95 page 231 also shows how to use 6 pin JTAG when chaining devices The signals TSTAT and TERR are configured as open drain type signals from PSDsoft Express This facilitates a wired OR connection of TSTAT signals from multiple uPSD34xx devices and also a wired OR connection of TERR signals from those same multiple devices PSDsoft Express puts TSTAT and TERR signals into open drain mode by default requiring external pull up resis tors Click on Properties in the JTAG ISP window of PSDsoft Express to change to standard CMOS push pull output
115. 1 Bit CR2 Details ENI1 STA STO ADDR AA CR 1 0 Bit Symbol CR2 R W RW Function This bit along with bits CR1 and CRO determine the SCL clock frequency when SIOE is in Master mode These bits create a clock divisor for fosc See Table 55 ENI1 RW 12 Interface Enable 0 SIOE disabled 1 SIOE enabled When disabled both SDA and SCL signals are in high impedance state STA RW START flag When set Master mode is entered and SIOE generates a START condition only if the bus is not busy When a START condition is detected on the bus the STA flag is cleared by hardware When the STA bit is set during an interrupt service the START condition will be generated after the interrupt service STO RW STOP flag When STO is set in Master mode the SIOE generates a STOP condition When a STOP condition is detected the STO flag is cleared by hardware When the STO bit is set during an interrupt service the STOP condition will be generated after the interrupt service 1 0 ADDR AA CR1 CRO RW RW RW This bit is set when an address byte received in Slave mode matches the device address programmed into the S1ADR register The ADDR bit must be cleared with firmware Assert Acknowledge enable If AA 1 an acknowledge signal low on SDA is automatically returned during the acknowledge bit time on the SCL line when any of the f
116. 27 RXD1 IrDA Q TCM2 P4 2 30 CL T2x 2 TCM1 P4 1 31 T 2 2 4 0 33 CL MCU ADO 36 MCU AD1 37 MCU AD2 38 CL MCU 39 CL P3 4 CO 40 CL 109697 Note NC Not Connected Note 1 The USB pin needs a 1 5kQ pull up resistor 2 For 5V applications Vpp must be connected to a 5 0V source For 3 3V applications Vpp must be connected to a 3 3V source 3 These signals can be used on one of two different ports Port 1 or Port 4 for flexibility Default is Port1 10 264 Table 2 Pin Definitions uPSD34xx PIN DESCRIPTIONS in Signal 80 Pin 52 Pin 2 Function 20 Port P t uh Name wou Basic Alternate 1 Alternate 2 External Bus MCUADO ADO lO Multiplexed Address Data bus A0 DO Multiplexed Address CECE Data bus A1 D1 Multiplexed Address MENADE Data bus A2 D2 Multiplexed Address ABS Data bus A3 D3 Multiplexed Address MCUAD4 ADA Data bus A4 D4 Multiplexed Address ADS Data bus A5 D5 Multiplexed Address ADG Data bus A6 D6 Multiplexed Address MOUAD AD Data bus A7 D7 T2 Timer 2 Count input ADC Channel 0 P1 0 ADCO General I O port pin T2 input ADCO T2X Timer 2 Trigger input ADC Channel 1 P1 1 General I O port T2X input ADC1 RxD1 j UART1 or IrDA ADC Channel 2 Ele ADC2 General VO port pin Receive RxD1 input ADC2
117. 34xx PSD MODULE Loading and Reading OMCs Each of the two OMC groups eight OMCs each occupies a byte in csiop space named MCELLAB and MCELLBC see Table 113 and Table 114 When the 8032 writes or reads these two OMC registers in csiop it is accessing each of the OMCs through its 8 bit data bus with the bit assignment shown in Table 112 page 195 Sometimes it is important to know the bit assignment when the user builds GPLD log ic that is accessed by the 8032 For example the user may create a 4 bit counter that must be load ed and read by the 8032 so the user must know which nibble in the corresponding csiop OMC reg ister the firmware must access The fitter report generated by PSDsoft Express will indicate how it assigned the OMCs and data bus bits to the logic The user can optionally force PSDsoft Express to assign logic to specific OMCs and data bus bits if desired by using the PROPERTY statement in PSDsoft Express Please see the PSDsoft Ex press User s Manual for more information on OMC assignments Loading the OMC flip flops with data from the 8032 takes priority over the PLD logic functions As such the preset clear and clock inputs to the flip flop can be asynchronously overridden when the 8032 writes to the csiop registers to load the in dividual OMCs Table 113 Output Macrocell MCELLAB address csiop offset 20h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCELLAB7 MCELLAB6 M
118. 3M ENABLE O DIRECTION O a Q 8032 4 2 x lt DATA E i lt lt EU M ak i 5 mn X IN MCUI O CMOS BUFFER PIN INPUT gt 8032 of 6 NO CSIOP HYSTERESIS EA FROM OMC OUTPUT FROM gt MCELLABx or MCELLBCx TO IMCs x 1 0 IMCB7 uPSD34xx PSD MODULE Port B also supports Open Drain Slew Rate output drive type options using the csiop Drive Select reg isters Pins PBO PB3 can be configured to fast slew rate pins PB4 PB7 can be configured to Open Drain Mode See Figure 86 for detail Note 1 Port pins PBO PBS are capable of Fast Slew Rate output drive option Port pins PB4 PB7 are capable of Open Drain output option 213 264 uPSD34xx PSD MODULE Port C Structure Port C supports the following operating modes on pins PC2 PC3 PC4 PC7 m MCU I O Mode m GPLD Output Mode from Output Macrocells MCELLBC2 MCELLBC3 MCELLBC4 MCELLBC7 m GPLD Input Mode to Input Macrocells IMCC2 IMCC4 IMCC7 See Figure 87 page 215 for detail Port C pins can also be configured in PSDsoft for other dedicated functions and PC4 support TSTAT and TERR status indicators to reduce the amount of time required for JTAG ISP programming These two pins must be used together for this function adding to the four standard JTAG signals When TSTAT and T
119. 4xx s SIE detects 3ms of no activity on the bus it generates the SUSPEND interrupt request It also causes the clock to the SIE to shut down to conserve power The clock to the SIE is turned back on when a USB Resume signal or Reset is detected USB EOP End of Packet Interrupt Every packet sent on the USB includes a signal called EOP to indicate the end of the packet When an EOP is detected the SIE generates an EOP interrupt USB Resume Interrupt When USB activity is detected and the SIE is in the suspend state a RESUME interrupt is generated and the USB clock to the SIE is turned back on USB Global Interrupt Enable Register UIEO There are four USB events that are considered to be global in nature meaning they are not specific to an endpoint but apply to the USB bus in general The four global USB events include Reset Suspend EOP and Resume Each event can be enabled to generate an interrupt using the UIEO register shown in Table 72 Table 72 USB Global Interrupt Enable Register UIEO OE4h Reset Value 00h 136 264 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSTIE SUSPENDIE EOPIE RESUMIE Details Bit Symbol R W Definition 7 E Reserved 6 Reserved 5 Reserved 4 Reserved 3 RSTIE R W Enable the USB Reset interrupt 2 SUSPENDIE R W Enable the USB Suspend interrupt 1 EOPIE R W Enable the USB EOP interrupt 0 RESUMIE R W Enab
120. 5 MCELLAB4 MCELLAB3 MCELLAB2 MCELLAB1 MCELLABO Note 1 Default is after any reset condition 2 1 block writing to individual macrocell 0 allow writing to individual macrocell Table 116 Output Macrocell MCELLBC Mask Register address csiop offset 23h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mask Mask Mask Mask Mask Mask Mask Mask MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBCO Note 1 Default is after any reset condition 2 1 block writing to individual macrocell 0 allow writing to individual macrocell Input Macrocells The GPLD has 20 IMCs one for each pin on Port A 80 pin device only one for each pin on Port B and for the four pins on Port C that are not JTAG pins The architecture of one in dividual IMC is shown in Figure 79 page 198 IMCs are individually configurable and they can strobe a signal coming in from a port pin as a latch gated or as a register clocked or the IMC can pass the signal without strobing all prior to driving the signal onto the PLD input bus Strobing is use ful for sampling and debouncing inputs keypad in puts etc before entering the PLD AND OR arrays The outputs of IMCs can be read by the 8032 asynchronously when the 8032 reads the csiop registers shown in Table 117 Table 118 and Table 119 page 198 It is possible to read a PSD Module port pin using one of two different method
121. 5 PSD 3 0 to 3 6 MCU 3 0 to 3 6 PSD and MCU Operating Temperature MCU Frequency Operating Current Typical 20 of PLD used 25 C operation Bus control signals are blocked from the PLD in Non Turbo mode Idle Current Typical 20 of PLD used 25 C operation Standby Current Typical SRAM Backup Current Typical 8MHz min for 40MHz Crystal Turbo 40 to 85 40 to 85 3 Min 40 Max 3 Min 40 Max 40MHz Crystal Non Turbo 71 58 mA 8MHz Crystal Turbo 32 24 mA 8MHz Crystal Non Turbo 17 7 14 mA 40MHz Crystal divided by 2048 internally 19 18 mA All interfaces are disabled Power down Mode needs reset to exit If external battery is attached Sink Source Current Ports A B C and D Sink Source Current Port 4 PLD Macrocells VoL 0 45V max 2 4V VoL 0 6V max VoH 2 4V min For registered or combinatorial logic lo 8 max loH 2 min lor 10 max 10 min lo 4 max 1 min lo 10 max 10 min PLD Inputs Inputs from pins feedback or MCU addresses PLD Outputs Output to pins or internal feedback PLD Propagation Delay Typical Turbo Mode PLD input to output Note 1 Operating current is measured while the uPSD34xx is executing a typical program at 40MHz 237 264 uPSD34xx DC AND AC PARAMETERS Table 156
122. 5 years Flash memory as well as the entire PSD Module may be programmed with the JTAG In System Programming ISP interface with no 3 uPSD34xx PSD MODULE 8032 involvement good for manufacturing and lab development Main Flash Memory The Main Flash memory is divided into equal sized sectors that are individual ly selectable by the Decode PLD output signals named FSx one signal for each Main Flash mem ory sector Each Flash sector can be located at any address within 8032 program address space accessed with PSEN or data address space also known as 8032 XDATA space accessed with RD or WR as defined with the software develop ment tool PSDsoft Express The user only has to specify an address range for each segment and specify if Main Flash memory will reside in 8032 data or program address space and then PSEN RD or WR are automatically activated for the specified range 8032 firmware is easily pro grammed into Main Flash memory using PSDsoft Express or other software tools See Table 101 page 166 for Main Flash sector sizes on the various uPSD34xx devices Secondary Flash Memory The smaller Second ary Flash memory is also divided into equal sized sectors that are individually selectable by the De code PLD signals named CSBOOTx one signal for each Secondary Flash memory sector Each sector can be located at any address within 8032 program address space accessed with PSEN or XDATA space accessed with RD or WR
123. 7 Timer 2 has three operating modes selected by bits in T2CON according to Table 44 page 78 The three modes are m Capture mode m Auto re load mode m Baud rate generator mode Capture Mode In Capture Mode there are two options which are selected by the bit EXEN2 in T2CON Figure 28 page 81 illustrates Capture mode If EXEN2 0 then Timer 2 is a 16 bit timer if C T2 0 or it is a 16 bit counter if C T2 1 either of which sets the interrupt flag bit TF2 upon overflow If EXEN2 1 then Timer 2 still does the above but with the added feature that a 1 to O transition at external input pin T2X causes the current value in the Timer 2 registers TL2 and TH2 to be cap tured into Registers RCAP2L and RCAP2H re spectively In addition the transition at T2X causes interrupt flag bit EXF2 in T2CON to be set Either flag TF2 or EXF2 will generate an interrupt and the MCU must read both flags to determine the cause Flags TF2 and EXF2 are not automati cally cleared by hardware so the firmware servic ing the interrupt must clear the flag s upon exit of the interrupt service routine Auto reload Mode the Auto reload Mode there are again two options which are selected by the bit EXEN2 in T2CON Figure 29 page 81 shows Auto reload mode If EXEN2 0 then when Timer 2 counts up and rolls over from FFFFh it not only sets the interrupt flag TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit
124. 8 These registers contain not only the mode selec tion bits but also the 9th data bit for transmit and receive bits TB8 and RB8 and the UART Inter rupt flags Tl and RI Table 47 SCONO Serial Port UARTO Control Register SFR 98h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMO SM1 SM2 REN TB8 RB8 TI RI Details Bit Symbol R W Definition 7 SMO R W Serial Mode Select See Table 46 page 83 Important notice bit order of SMO and SM1 SMO SM1 00b Mode 0 6 SM1 RW SMO SM1 01b Mode 1 SM0 SM1 10b Mode 2 SM0 SM1 11b Mode 3 Serial Multiprocessor Communication Enable Mode 0 SM2 has no effect but should remain 0 5 SM2 Mode 1 If SM2 0 then stop bit ignored SM2 1 then RI active if stop bit 1 Mode 2 and 3 Multiprocessor Comm Enable If SM2 0 9th bit is ignored If SM2 1 RI active when 9th bit 1 Receive Enable 4 REN RW If RENZO UART reception disabled If REN 1 reception is enabled TB8 is assigned to the 9th transmission bit in Mode 2 and 3 Not used in 3 TBS RW Mode 0 and 1 Mode 0 RB8 is not used 2 RB8 RW Mode 1 If SM2 0 the RB8 is the level of the received stop bit Mode 2 and 3 RB8 is the 9th data bit that was received in Mode 2 and 3 Transmit Interrupt flag 1 TI RW Causes interrupt at end of 8th bit time when transmitting in Mode 0 or at beginning of stop bit transmission in other modes Must clear flag with firmware Receive I
125. 8032 signals RD and WR XDATA can be present at any address in data space between 0x0000 and OxFFFF Note the uPSD34xx has dual data pointers source and destination making XDATA transfers much more efficient Memory Placement PSD Module architecture allows the placement of its external memories into different combinations of program memory and data memory spaces This means the main Flash the secondary Flash and the SRAM can be viewed by the 8032 MCU in various combinations of program memory or data memory as defined by PSDsoft Express As an example of this flexibility for applications that require a great deal of Flash memory in data space large lookup tables or extended data re cording the larger main Flash memory can be placed in data space and the smaller secondary Flash memory can be placed in program space The opposite can be realized for a different appli cation if more Flash memory is needed for code and less Flash memory for data 17 264 uPSD34xx 8032 MCU CORE PERFORMANCE ENHANCEMENTS By default the SRAM and csiop memories on the PSD Module must always reside in data memory space and they are treated by the 8032 as XDA TA The main Flash and secondary Flash memories may reside in program space data space or both These memory placement choices specified by PSDsoft Express are programmed into non vola tile sections of the uPSD34xx and are active at power up and after reset It is possible to overri
126. 89h 88h 00 SEM E 89 TMOD GATE C T M1 Mo GATE C T M1 MO 00 42 page 74 8A TLO TLO 7 0 00 Standard 8B TL1 TL1 7 0 00 Timer 8C THO THO 7 0 00 M e 8D TH1 TH1 7 0 00 Table 8E 15 50 P1SFSO 7 0 00 31 page 61 Table 8F P1SFS1 P1SFS1 7 0 00 32 page 61 Table P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 1 90 97h 96h 95h 94h 93h 92h 91h 90h FF PENES Table 91 P3SFS P3SFS 7 0 00 30 page 61 Table 92 P4SFSO P4SFSO 7 0 00 34 page 62 Table 93 P4SFS1 PASFS1 7 0 00 35 page 62 ky 25 264 uPSD34xx SPECIAL FUNCTION REGISTERS SFR SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Name Value Descr hex 7 6 5 4 3 1 0 hex with Link Table 94 ADCPS ADCCE ADCPS 2 0 00 90 page 153 Table 95 ADATO ADATA 7 0 O0 91 page 153 Table 96 ADAT 1 ADATA 9 8 00 92 page 153 Table 97 ACON AINTF AINTEN ADEN ADS 2 0 ADSF 00 89 page 152 Table SMO SM1 SM2 REN TB8 Tl RI 1 980 SCONO lt 9Eh gt lt 9Dh gt lt 9Ch gt lt 9Bh gt lt 9 gt 99h 9h8 00 Figure 99 SBUFO SBUFO 7 0 00 28 page 81 9A RESERVED 9B RESERVED 9 RESERVED Table 9D BUSCON EPFQ EBC WRW1 WRWO RDW1 RDWO CW1 EB 37 page 65 9E RESERVED 9F RESERVED A
127. A WR to Data Propagation Delay tpvov PA Data to Port A Data Propagation Delay Note 1 twHaz PA WR Invalid to Port A Tri state Symbol Parameter Conditions Min tRST LO IN Reset Input Duration 10 tRST_ACTV Generated Reset Duration fosc 40 2 1002 tRST_FIL Reset Input Spike Filter VRST_HYS Reset Input Hysteresis Voc 3 3V VRST_THRESH LVD Trip Threshold Voc 3 3V 2 4 Note 1 25 minimum to abort a Flash memory program or erase cycle in progress 2 As fosc decreases tnsr increases Example tast_actv 50ms when fosc 8MHz 253 264 uPSD34xx DC AND AC PARAMETERS Table 179 VsrByow Definitions Timing BV PSD Modules Parameter Conditions Vstpy Detection to Output High Note 1 V Off Detection to V Output Note 1 VsrByoN timing is measured at Vcc ramp rate of 2ms Figure 108 ISC Timing tisccH TCK tisccL gt tiscpsu tiscPH lt TDITMS tiscPzv tiscpco lt gt ISC OUTPUTS TDO tiscpvz lt gt ISC OUTPUTS TDO Al02865 Table 180 ISC Timing 5V PSD Module Symbol Parameter Conditions Min Max Unit tisccr Clock PC1 Frequency except for PLD Note 1 20 MHz tisccH Clock PC1 High Time except for PLD Note 1 tisccL Clock PC1 Low Time except for PLD Note 1 tisccrp Clock PC1 Frequency PLD only Note 2 t
128. ANALOG TO DIGITAL CONVERTOR ADC 151 Port 1 ADC Channel 151 5 264 uPSD34xx TABLE OF CONTENTS PROGRAMMABLE COUNTER ARRAY PCA WITH 154 ERE eti 154 PCA Clock Selection leno el nee aed ve 156 Operation of TCM Modes 157 Capture Mode i iR eee eee 157 TimerMode 22 2 2 See x edic I IRR EE ES EN 157 Toggle Mode ete RENE ate OSEE S PR exa 157 PWM Mode X8 Fixed 157 PWM Mode X8 Programmable 159 PWM Mode Fixed Frequency 16 160 PWM Mode Fixed Frequency 10 160 Writing to Capture Compare 160 Control Register Bit 160 TOM Interr pts 2 Ie de Paine ia EINE Ja 163 PSD MODULE 224220 ELI a tied iad ete eee ie 164 PSD Module Functional
129. AT 7 7 Fast Turbo 8032 MCU with USB and Programmable Logic FEATURES SUMMARY FAST 8 BIT TURBO 8032 MCU 40MHz Advanced core 4 clocks per instruction 10 peak performance at 40MHz 5V Debug and In System Programming 16 bit internal instruction path fetches double byte instruction in a single memory cycle Branch Cache amp 4 instruction Prefetch Queue Dual XDATA pointers with automatic increment and decrement Compatible with 3rd party 8051 tools DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT Place either memory into 8032 program address space or data address space READ while WRITE operation for In Application Programming and EEPROM emulation Single voltage program and erase 100K guaranteed erase cycles 15 year retention CLOCK RESET AND POWER SUPPLY MANAGEMENT SRAM is Battery Backup capable Flexible 8 level CPU clock divider register Normal Idle and Power Down Modes Power on and Low Voltage reset supervisor Programmable Watchdog Timer PROGRAMMABLE LOGIC GENERAL PURPOSE 16 macrocells for logic applications e g shifters state machines chip selects glue logic to keypads and LCDs A D CONVERTER Eight Channels 10 bit resolution 6us October 2005 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice uPSD34xx Tu
130. ATA BIT 1 1 6 INPUT 1 1 BUFFER 1 1 1 1 8032 RD ONE of 6 gt gt CSIOP REGISTERS 1 1 FROM 1 FROM OUTPUT ALLOCATOR 1 107873 3 200 264 uPSD34xx PSD MODULE Table 120 Port Operating Modes Note 1 MCELLBC outputs available only on pins PC2 PC3 PC4 and PC7 Port Operating Mode Port A 80 pin only Find it MCU I O MCU I O Yes Mode p age 203 PLD OMC MCELLAB Outputs Yes PLD I O OMC MCELLBC Outputs No Mode p External Chip Select Outputs No age 205 PLD Inputs Yes Latched Address Latched Address Output Yes Output Mode pa ge 208 Peripher al I O Peripheral I O Mode Yes Mode pa ge 209 JTAG ISP No 2 JTAG pins PCO TMS PC1 TCK PC5 TDI PC6 TDO are dedicated to JTAG pin functions cannot be used for general I O 201 264 uPSD34xx PSD MODULE Table 121 Port Configuration Setting Requirements NEMESIS SR Control Register at Direction Register PIO EN of csiop VM 9 run time at run time Register at run time Choose the MCU I O Logic 1 Out of MCU I O function and declare the Logic 0 default uPSD pin name Logic 0 Into uPSD Choose the PLD function Direction register PLD 1 0 type declare pin name N A has no effect ona and specify logic pin if pin is driven equation s from OMC output Choose Latched Address A ai a Out function declare pin Logic
131. C output from PLD MCU I O mode Configures port pin as input or output Write to set direction of Direction 06h port pins Logic 1 out Logic 0 in Read to check status Write to configure port pins as either CMOS push pull or Open Drain on some Drive Select 08h pins while selecting high slew rate on other pins Read to check status Default output type is CMOS push pull Input Read to obtain logic state of IMCs No Macrocells WRITEs Read state of output enable logic on each I O port driver 1 driver output is Enable och enabled 0 driver is off and it is in high impedance state No WRITEs Output Read logic state of MCELLAB outputs Macrocells AB bank of eight OMCs MCELLAB Write to load MCELLAB flip flops Output Read logic state of MCELLBC outputs Macrocells BC bank of eight OMCs MCELLBC Write to load MCELLBC flip flops Write to set mask for MCELLAB Logic Mask 1 blocks READs WRITEs of Macrocells AB Logic 0 will pass value Read to check status Write to set mask for MCELLBC Logic Mask boh 1 blocks READs WRITEs of OMC us Macrocells BC Logic 0 will pass value Read to p check status 176 264 uPSD34xx PSD MODULE Register Port A 80 pin Port D Other Description Read to determine Main Flash Sector e eet Protection Setting non volatile that was Protection specified in P
132. CELLAB5 MCELLAB4 MCELLABS MCELLAB2 MCELLAB1 MCELLABO Note All bits clear to logic 0 at power on reset but do not clear after warm reset conditions non power on reset Table 114 Output Macrocell MCELLBC address csiop offset 21h MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBCO Note All bits clear to logic 0 at power on reset but do not clear after warm reset conditions non power on reset 196 264 y OMC Mask Registers There is one OMC Mask Register for each of the two groups of eight OMCs shown in Table 115 and Table 116 The OMC mask registers are used to block loading of data to individual OMCs The default value for the mask registers is 00h which allows loading of all OMCs When a given bit in a mask register is set to a 1 the 8032 is blocked from writing to the associated uPSD34xx PSD MODULE OMC flip flop For example suppose that only four of eight OMCs MCELLABO 3 are being used for a state machine The user may not want the 8032 to write to all the OMCs in MCELLAB because it would overwrite the state machine registers Therefore the user would want to load the mask register for MCELLAB with the value OFh before writing OMCs Table 115 Output Macrocell MCELLAB Mask Register address csiop offset 22h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mask Mask Mask Mask Mask Mask Mask Mask MCELLAB7 MCELLAB6 MCELLAB
133. COMLn Reg isters become 10 bit registers PWM duty cycle of each TCM module can be specified in the 10 bit CAPCOMHn and CAP COMLn Registers When the 10 bit PCA counter is equal or greater than the values in the 10 bit registers CAPCOMHn and CAPCOML n the PWM output switches to a high state When the 10 bit PCA counter overflows the PWM pin is switched to a logic low and starts the next PWM pulse The most significant 6 bits in the PCACHm counter and CAPCOMH Register are Don t cares and have no effect on the PWM generation Writing to Capture Compare Registers When writing a 16 bit value to the PCA Capture Compare registers the low byte should always be written first Writing to CAPCOMLn clears the E COMP Bit to 0 writing to CAPCOMHn sets E COMP to 1 the largest duty cycle is 100 CAPCOMHn CAPCOMLn 0x0000 and the smallest duty cycle is 0 0015 CAPCOMHn CAPCOMLn OxFFFF A 0 duty cycle may be generated by clearing the E COMP Bit to 0 Control Register Bit Definition Each PCA has its own PCA CONFIGn and each module within the PCA block has its own TCM Mode Register which defines the operation of that module see Table 96 page 160 through Table 97 page 161 There is one PCA STATUS Register that covers both PCAO and PCA1 see Table 98 page 162 Table 96 Control Register PCACONO SFR 0A4h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
134. CU Module The serial path is completed when TDO of the MCU Module exits the uPSD34xx package through the TDO pin on Port C The 226 264 JTAG signals TCK and TMS are common to both modules as specified in IEEE 1149 1 When JTAG devices are chained typically one devices is in BYPASS mode while another device is executing a JTAG operation For the uPSD34xx the PSD Module is in BYPASS mode while debugging the MCU Module and the MCU Module is in BYPASS mode while performing ISP on the PSD Module The RESET_IN input pin on the 5034 pack age goes to the MCU Module and this module will generate the RST reset signal for the PSD Mod ule These reset signals are totally independent of the JTAG TAP controllers meaning that the JTAG channel is operational when the modules are held in reset It is required to assert RESET IN during ISP STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal during ISP However the user must connect this reset signal to RESET IN as shown in examples in Fig ure Figure 92 227 and Figure 93 page 229 Figure 91 JTAG Chain in uPSD34xx Package MCU MODULE OPTIONAL K 3 DEBUG RESET INK 3 JTAG TAP CONTROLLER JTAG TDO K JTAG TCK Do IEEE 1149 1 JTAG TMS i TSTAT K 3 OPTIONAL PC4A TERRK MAIN 2ND FLASH FLASH PLD MEMORY MEMORY PSD MODULE 110460 In System Programming The ISP function can use
135. CU_CLK Periods Required to Optimize Bus Transfer Rate RDW 1 0 Clk WRW 1 0 Clk MCU Clock Frequency CWI 1 0 Periods Periods Periods fmcu 3 3V 5y 3 31 5 1 3 30 40MHz Turbo mode PSD 5 40MHz Non Turbo mode PSD 36MHz Turbo mode PSD 36MHz Non Turbo mode PSD 32MHz Turbo mode PSD 32MHz Non Turbo mode PSD 28MHz Turbo mode PSD 28MHz Non Turbo mode PSD 24MHz Turbo mode PSD 24MHz Non Turbo mode PSD 20MHz and below Turbo mode PSD 20MHz and below Non Turbo mode PSD Note 1 Vpp of the PSD Module 2 Turbo mode PSD means that the PSD Module is in the faster Turbo mode default condition A PSD Module in Non Turbo mode is slower but consumes less current See PSD Module section titled PLD Non Turbo Mode for details A A A BR A A AR BR A a 5 AJAJAJ AJo AI oO oa oOo AY BR BR BR RY BR AJA A AJ AJAJAJA w A AR ay aJ ajl aJ a A gt 66 264 SUPERVISORY FUNCTIONS Supervisory circuitry on the MCU Module will issue an internal reset signal to the MCU Module and si multaneously to the PSD Module as a result of any of the following four events external RESET IN pin is asserted The Low Voltage Detect LVD circuitry has detected a voltage on Vcc below a specific threshold power on or voltage sags The JTAG Debug interface has issued a
136. Cycle AC Characteristics 3V or 5V Device Variable Oscillator 40MHz Oscillator Symbol Parameter 1 to 40 2 Unit Min Max Min Max ALE pulse width 17 8 ns Address setup to ALE 13 12 ns Address hold after ALE 7 5 0 5 ns Address float to RD a 4 way Address valid to latched address out 35 5 3V Ports 28 5V 9 5 ns Note 1 BUSCON Register is configured for 4 PFQCLK 2 Refer to Table 160 for n and values Table 160 n m and x y Values of PFQCLK in READ Cycle WRITE Cycle BUSCON Reg n m x y 4 2 3 2 1 5 3 4 3 2 6 4 5 4 3 7 5 6 5 4 241 264 uPSD34xx DC AND AC PARAMETERS Figure 100 External WRITE Cycle 80 pin Device Only MCU ADO AD7 ALE tLHLL tAVQV 4 LATCHED MCU A8 A15 tLLWL tWLWH gt tWHLH DATA IN A8 A15 110472 Table 161 External WRITE Cycle AC Characteristics 3V or 5V Device Variable Oscillator Symbol Parameter sii dail Unit Min Min tLHLL ALE pulse width 17 8 ns Address Setup to ALE 13 12 ns Address hold after ALE 7 5 5 ns WR pulse width 40 10 ns tLLWL ALE to WR 7 5 O 5
137. DPLD equations because they are routed in silicon directly to the memory arrays of the PSD Module bypassing the PLDs For example it is NOT necessary to qualify a memory chip select signal with an MCU write strobe such as fsO address range amp WR_ Only fsO address range is needed Each of the 8032 bus control signals may be blocked individually by writing to Bits 2 3 4 and 5 of the PMMR2 register shown Table 145 page 219 Blocking any of these four bus control signals only prevents them from reaching the PLDs but they will always go to the memories directly However sometimes it is necessary to use these 8032 bus control signals in the GPLD when creat ing interface signals to external I O peripherals But it is still possible to save power by dynamically unblocking the bus signals before reading writing the external device then blocking the signals after the communication is complete The user can also block an input signal coming from pin PC7 to the PLD input bus if desired by writing to Bit 6 of PMMR2 Blocking Common Clock CLKIN The input CLKIN from pin PD1 can be blocked to reduce current consumption CLKIN is used as a common clock input to all OMC flip flips it is a general input to the PLD input bus and it is used to clock the APD counter In PSDsoft Express the function of pin PD1 must be specified as Common Clock In put CLKIN before programming the device with JTAG to get the CLKI
138. DULE Power Management The PSD Module offers configurable power saving options and also a way to manage power to the SRAM battery backup These options may be used individually or in com binations A top level description for these func tions is given here then detailed descriptions will follow Zero Power Memory All memory arrays Flash and SRAM in the PSD Module are built with zero power technology which puts the memories into standby mode zero DC current when 8032 address signals are not changing As soon as a transition occurs on any address input the affected memory wakes up changes and latches its outputs then goes back to standby The designer does not have to do anything special to achieve this memory standby mode when no inputs are changing it happens automatically Thus the slower the 8032 clock the lower the current consumption Both PLDs DPLD and GPLD are also zero power but this is not the default condition The 8032 must set a bit in one of the csiop PMMR registers at run time to achieve zero power Automatic Power Down APD The APD feature allows the PSD Module to reach its lowest current consumption levels If enabled the APD counter will time out when there is a lack of 8032 bus activity for an extended amount of time 8032 asleep After time out occurs all 8032 address and data buffers on the PSD Module are shut down preventing the PSD Module memories and potentially the PL
139. Data In registers are defined in Table 122 to Table 125 The Data Out registers are defined in Table 126 to Table 129 page 204 The Direction registers are defined in Table 130 to Table 133 page 204 Table 122 MCU I O Mode Port A Data In Register address csiop offset 00h Bit 7 Bit 6 Bit 5 Bit 4 PA7 PA6 PA5 PA4 Bit 3 Bit 2 Bit 1 Bit 0 PA3 PA2 PA1 PAO Note 1 Port A not available on 52 pin uPSD34xx devices 2 For each bit 1 current state of input pin is logic 1 0 current state is logic 0 Table 123 MCU I O Mode Port B Data In Register address csiop offset 01h Note For each bit 1 current state of input pin is logic 1 0 current state is logic 0 Table 124 MCU I O Mode Port C Data In Register address csiop offset 10h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 X X PC4 Note 1 X Not guaranteed value can be read either 1 or 0 2 X X 2 For each bit 1 current state of input pin is logic 1 0 current state is logic 0 Table 125 MCU I O Mode Port D Data In Register address csiop offset 11h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X 2 3 PD1 X Note 1 X Not guaranteed value can be read either 1 or 0 2 For each bit 1 current state of input pin is logic 1 0 current state is logic 0 3 Not available on 52 pin uPSD34xx
140. Ds from waking up from standby even if address inputs are changing state because of noise or any external components driving the address lines Since the actual address and data buffers are turned off current consumption is even further reduced Note Non address signals are still available to PLD inputs and will wake up the PLDs if these signals are changing state but will not wake up the memories The APD counter requires a relatively slow external clock input on pin PD1 that does stop when the 8032 goes to sleep mode Forced Power Down FPD The MCU can put the PSD Module into Power Down mode with the same results as using APD described above but FPD does not rely on the APD counter Instead FPD will force the PSD Module into Power Down mode when the MCU firmware sets a bit in one of the csiop PMMR registers This is a good alternative to APD because no external clock is needed for the APD counter 218 264 PSD Module Chip Select Input CSI This input on pin PD2 80 pin devices only can be used to disable the internal memories placing them in standby mode even if address inputs are changing This feature does not block any internal signals the address and data buffers are still on but signals are ignored and CSI does not disable the PLDs This is a good alternative to using the APD counter which requires an external clock on pin PD1 Non Turbo Mode The PLDs can operate in Turbo or non Turbo modes Turbo mode has
141. ERR are used it is referred to as 6 pin JTAG PC3 and PC4 cannot be used for other functions if they are used for 6 pin JTAG See JTAG ISP and JTAG Debug page 226 for details 2 be used as a voltage input from battery or other DC source to backup the contents of SRAM when Vpp is lost This 214 264 function is specified in PSDsoft Express as SRAM Standby Mode battery backup page 224 be used as an output to indicate when a Flash memory program or erase operation has completed This is specified in PSDsoft Express as Ready Busy PC3 page 184 PC4can be used as an output to indicate when the SRAM has switched to backup voltage when Vpp is less than the battery input voltage on PC2 This is specified in PSDsoft Express as Standby On Indicator see SRAM Standby Mode battery backup page 224 The remaining four pins TDI TDO TCK TMS on Port C are dedicated to the JTAG function and cannot be used for any other function See JTAG ISP and JTAG Debug page 226 Port C also supports the Open Drain output drive type options on pins PC2 PC4 PC7 us ing the csiop Drive Select registers 3 uPSD34xx PSD MODULE Figure 87 Port C Structure PT OUTPUT ENABLE JTAG STATE MACHINE PORT C FROM AND Y AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS LOGIC ORARRAY FROM PLD MODULE RESET 1 1 INPUT BUS DIRECTION Vpp Vgar PU
142. F After this RE CEIVE is cleared and the receive interrupt flag RI is set 87 264 uPSD34xx SERIAL UART INTERFACES Figure 31 UART Mode 0 Block Diagram Write to SBUF fosc 12 Internal Bus RxD SBUF Pin Zero Detector Start Tx Control Tx Clock T Interrupt Shift 20 Clock TxD Rx Clock R Receive Pin REN Start Rx Control Shift R1 76543210 RxD Input Shift Register ga Alt put Function Internal Bus Al06824 Figure 32 UART Mode 0 Timing Diagram Write to SBUF Send OOOO Salt Transmit RxD Data Out Di X 52 X D3 X X Ds X D6 X 57 TxD ShiftClock LN LT LT LT LT LTLUTLU T A ceu mm Write to SCON A Clear RI RTL Receive L Receive Shift MNM NM Tn Tnm n Tm RxD Data In 2 pps pps ppe Ie E 7 Al06825 88 264 1572 More About UART Mode 1 Refer to the block diagram in Figure 33 page 90 and timing diagram in Figure 34 page 90 Transmission is initiated by any instruction which writes to SBUF At the end of a write operation to SBUF a 1 is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission ac tually starts at the end of the MCU the machine cy cle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide
143. Flag Bit DQ5 indicates a time out condition on the Erase cycle a 0 indicates no error The 8032 can read any location within the sector being erased to get the Data Polling Flag Bit DQ7 and the Error Flag Bit DQ5 182 264 PSDsoft Express generates ANSI C code func tions the user may use to implement these Data Polling algorithms Figure 72 Data Polling Flowchart READ DQ5 amp DQ7 at VALID ADDRESS PASS 101369 Data Toggle Checking the Toggle Flag Bit DQ6 is another method of determining whether a program or erase operation is in progress or has completed Figure 73 shows the Data Toggle algo rithm When the 8032 issues a program instruction se quence the embedded algorithm within the Flash memory array begins The 8032 then reads the lo cation of the byte to be programmed in Flash memory to check status The Toggle Flag Bit DQ6 of this location toggles each time the 8032 reads this location until the embedded algorithm is complete The 8032 continues to read this loca tion checking the Toggle Flag Bit DQ6 and mon itoring the Error Flag Bit DQ5 When the Toggle Flag Bit DQ6 stops toggling two consecutive reads yield the same value then the embedded algorithm is complete If the Error Flag Bit DQ5 is 1 the 8032 should test the Toggle Flag Bit DQ6 again since the Toggle Flag Bit DQ6 may have changed simultaneously with the Error Flag Bit DQ5 see Figure 73
144. H1 and TL1 are cascaded No pre scaler 10b 8 bit auto reload T C TH1 holds a constant and loads into TL1 upon overflow 11b Timer Counter 1 is stopped Gate control 3 GATE RW When GATE 1 T C is enabled only while pin EXTINTO is 1 and the flag TRO is 1 When GATE 0 is enabled whenever the TRO is 1 Counter or Timer function select 2 C T When C T 0 function is timer clocked by internal clock C T 1 function is counter clocked by signal sampled on external pin CO Timer 0 Mode Select 00b 13 bit T C 8 bits in THO with TLO as 5 bit pre scaler 01b 16 bit T C THO and TLO are cascaded No pre 1 0 M 1 0 RW scaler 10b 8 bit auto reload T C THO holds a constant and loads into TLO upon overflow 11b TLO is 8 bit T C controlled by standard Timer 0 control bits THO is a separate 8 bit timer that uses Timer 1 control bits 74 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Figure 25 Timer Counter Mode 0 13 bit Counter Interrupt Control Gate pin 106622 Interrupt Al06623 Control Gate EXTINTO pin Interrupt Control TRI 106624 y 75 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Timer 2 Timer 2 can operate as either an event timer or as an event counter This is selected by the bit C T2 in the SFR named T2CON Table 43 page 7
145. Hardware watchdog timer registers WDKEY WDRST Interrupt system registers IP IPA IE IEA Prog Counter Array PCA control registers PCACLO PCACHO PCACONO PCASTA PCACL1 PCACH1 1 CCON2 CCONS PCA capture compare and PWM registers CAPCOMLO CAPCOMHO TCMMODEO CAPCOML1 CAPCOMH1 TCMMODE2 CAPCOML2 CAPCOMH2 TCMMODE2 CAPCOML3 CAPCOMHS TCMMODES CAPCOMLA CAPCOMH4 TCMMODEA CAPCOML5 CAPCOMHS5 5 PWMFO PMWF1 SPI interface registers SPICLKD SPISTAT SPITDR SPIRDR SPICONO SPICON1 interface registers S1SETUP S1CON S1STA S1DAT S1ADR Analog to Digital Converter registers ACON ADCPS ADATO ADAT1 IrDA interface register IRDACON USB interface registers UADDR UPAIR WEO 8 UIFO 3 UCTL USTA USEL UCON USIZE UBASEH UBASEL USCI USCV uPSD34xx SPECIAL FUNCTION REGISTERS SFR Table 5 SFR Memory Map with Direct Address and Reset Value SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Name Value Descr hex 7 6 5 4 3 2 1 0 hex with Link 80 RESERVED Stack Pointer 81 SP SP 7 0 07 SP page 22 82 DPL DPL 7 0 00 Data Pointer 83 DPH 7 0 DPTR 22 84 RESERVED Table 85 DPTC AT DPSEL 2 0 00 13 page 38 Table MD1 1 0 MDO 1 0 00 14 page 39 Table RCLK1 TCLK1 PD IDLE 00 26 page 52 Table IE1 IT1 IEO ITO lt 8Bh gt lt gt
146. Interrupt handler SPIRDR Full Transmit End interrupt requested read data in SPIRDR interrupt requested interrupt requested 107855 Figure 47 SPI Transmit Operation Example 1 frame 1 1 SPICLK SPO 0 SPICLK SPO 1 1 1 1 TISF TEISF BUSY SPISEL SPIINTR SPITDR Empty Interrupt handler SPITDR Empty Transmit End interrupt requested write data in TDR interrupt requested interrupt requested 107854 117 264 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE SPI SFR Registers Six SFR registers control the SPI interface m SPICONO Table 63 page 120 for interface control m SPICON1 Table 64 page 121 for interrupt control m SPITDR SFR Write only holds byte to transmit m SPIRDR SFR D5h Read only holds byte received m SPICLKD Table 65 page 121 for clock divider m SPISTAT Table 66 page 122 holds interface status Figure 48 SPI Interface Master Mode Only The SPI interface functional block diagram Figure 48 shows these six SFRs Both the transmit and receive data paths are double buffered meaning that continuous transmitting or receiving back to back transfer is possible by reading from SPIRDR or writing data to SPITDR while shifting is taking place There are a number of flags in the SPISTAT register that indicate when it is full or empty to as sist the 8032 MCU in data flow management When enabled these s
147. Is set only by a power on reset generated by Supervisory circuit see Power up Reset page 68 for details Received Clock Flag UART1 See Table 43 page 77 for flag description Transmit Clock Flag UART1 See Table 43 page 77 for flag description Activate Power down Mode 0 Not in Power down Mode 1 Enter Power down Mode IDL Activate Idle Mode 0 Not in Idle Mode 1 Enter Idle Mode 52 264 3 uPSD34xx OSCILLATOR AND EXTERNAL COMPONENTS OSCILLATOR AND EXTERNAL COMPONENTS The oscillator circuit of UPSD34xx devices is a sin gle stage inverting amplifier in a Pierce oscillator configuration The internal circuitry between pins XTAL1 and XTAL2 is basically an inverter biased to the transfer point Either an external quartz crys tal or ceramic resonator can be used as the feed back element to complete the oscillator circuit Both are operated in parallel resonance Ceramic resonators are lower cost but typically have a wid er frequency tolerance than quartz crystals Alter natively an external clock source from an oscillator or other active device may drive the uPSD34xx oscillator circuit input directly instead of using a crystal or resonator The minimum frequency of the quartz crystal ce ramic resonator or external clock source is 3MHz if the USB is used The minimum is 8MHz if is used The maximum is 40MHz in all cases This frequency is fosc which can be divided interna
148. L Bit is set the SPISEL pin will drive to logic 0 active to select a connected slave de vice at the appropriate time before the first data bit of a byte is transmitted and SPISEL will automat ically return to logic 1 inactive after transmitting the eight bit of data as shown in Figure 47 page 117 SPISEL will continue to automati cally toggle this way for each byte data transmis sion while the SSEL bit is set by firmware When the SSEL Bit is cleared the SPISEL pin will drive to constant logic 1 and stay that way after a transmission in progress completes The Interrupt Enable Bits TEIE RORIE TIE and RIE when set will allow an SPI interrupt to be generated to the MCU upon the occurrence of the condition enabled by these bits Firmware must read the four corresponding flags in the SPISTAT register to determine the specific cause of inter rupt These flags are automatically cleared when firmware reads the SPISTAT register 119 264 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE Table 63 SPICONO Control Register 0 SFR D6h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIEN SSEL FLSB SBO Details Bit Symbol R W Definition 7 Reserved Transmitter Enable 5 RW 0 Transmitter is disabled 1 Transmitter is enabled Receiver Enable BE RW 0 Receiver is disabled 1 Receiver is enabled SPI Enable 4 SEIEN RW 0 E
149. LD configu ration The security bit also blocks JTAG access to the MCU Module for debugging The only way to defeat the security bit is to erase the entire PSD Module using JTAG erase is the only JTAG oper ation allowed while security bit is set after which the device is blank and may be used again The 8032 MCU will always have access to Flash mem ory contents through its 8 bit data bus even while the security bit is set The 8032 can read the status of the security bit at run time but it cannot change it by reading the csiop register defined in Table 110 Table 109 Main Flash Memory Protection Register Definition address csiop offset COh Sec7 Prot Sec6 Prot 5 Prot Sec4 Prot Sec3 Prot Sec2 Prot Prot 0 Prot Note Bit Definitions Sec i Prot 1 Flash memory sector i is write protected 0 Flash memory sector lt i gt is not write protected Table 110 Secondary Flash Memory Protection Security Register Definition csiop offset C2h Security Bit not used not used not used Sec3 Prot Sec2 Prot Prot 0 Prot Note Security Bit 1 device is secured 0 not secured Note lt gt Prot 1 Flash memory sector lt gt is write protected 0 Flash memory sector i is not write protected 186 264 y PLDs The PSD Module contains two PLDs the Decode PLD DPLD and the General PLD GPLD as shown in Figure 74 page 188 Both PLDs are fed by a commo
150. LL UP 50k ONLY ON 2 JTAG TDI D DRIVE RIVE TYPE SELECT TMS TCK SIGNALS 1 Vpp Vop Vgar MCUI O DATA OUT OUTPUT TYPICAL ENABLE er PIN PORTC OUTPUT KY 8032 2 DATA D DATA OUT BIT B MCUI O 4 ENABLE OUT M U PIN X 5 DATA IN MCUI O CMOS NPUT 8032 ADDRESS DATA CONTROL BUS BUFFER ONE of 6 NO CSIOP HYSTERESIS REGISTERS FROM OMC ALLOCATOR icap elles aeaea a e e d dd beet eel ieee FROM SRAM STANDBY ON TO SRAM BACK UP CIRCUIT 22 A BATTERY FROM FLASH MEMORIES 35 D BSY OES TSTAT TERR IMCC2 IMCC3 IMCC4 IMCC7 STATE MACHINE lt TMS TO IMCs lt lt 109181 Note 1 Pull up switches to Vgat when SRAM goes to battery back up mode 2 Optional function on a specific Port C pin ky 215 264 uPSD34xx PSD MODULE Port D Structure Port D has two pins PD1 PD2 on 80 pin uPSD34xx devices and just one pin PD1 on 52 pin devices supporting the follow ing operating modes MCU Mode DPLD Output Mode for External Chip Selects ECS1 ECS2 This does not consume OMCs in the GPLD PLD Input Mode direct input to the PLD Input Bus available to DPLD and GPLD Does not use IMCs See Figure 88 page 217 for detail 216 264 Port D pins can also be configured in PSDsoft as pins for other dedicated functions PD1 can be used as a common clock input to all 16 OMC Flip flops see OMCs page
151. MPL 5 6 0 00 59 page 108 Table DC 1 CR2 EN1 STA STO ADDR AA CR1 CRO 54 page 103 Table DD S1STA GC STOP INTR TX MD BUSY B LOST s v 00 56 page 106 Table DE S1DAT S1DAT 7 0 00 57 page 107 Table DF S1ADR S1ADR 7 0 00 58 page 107 Accumulat A 7 0 or 1 Eo bit addresses E7h E6h E5h E4h E3h E2h Eth EOh gt 00 ACC pa ge 22 E1 RESERVED E2 UADDR USBADDR 6 0 00 E3 UPAIR PR1OUT PR3IN PR1IN 00 SUSPND RES E4 RSTIE EOPIE jue 00 E5 INSIE IN2IE IN1IE INOIE E6 OUTAIE OUTSIE OUT2IE OUT1IE x 00 E7 UIE3 NAKAIE 2 NAK1IE kin 00 E8 UIFO GLF INF OUTF NAKF RSTF SINE EOPF jou 00 29 264 uPSD34xx SPECIAL FUNCTION REGISTERS SFR SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Name Value Descr hex 7 6 5 4 3 2 1 0 hex with Link E9 UIF1 INAF INSF IN2F IN1F INOF 00 EA UIF2 OUT4F OUT2F OUT1F OUTOF 00 UIF3 NAK2F NAK1F 00 be USBEN VISIBLE wig 00 ED USTA RCVT SETUP IN OUT 00 EE RESERVED EF USEL DIR EP 2 0 00 B Register B lt bit addresses F7h Poh Fh F3h F2h F1h gt E page F1 UCON STALL TOGGLE BSY 0
152. Master indicating that the Master must wait until the Slave releases SCL before proceeding with the transfer Another example is when two Master devices try to put information on the bus simultaneously the first one to release the SDA data line looses arbi tration while the winner continues to hold SDA low Two types of data transfers are possible with I C depending on the R W bit see Figure 42 page 100 1 Data transfer from Master Transmitter to Slave Receiver R W 0 In this case the Master generates a START condition on the bus and it generates a clock signal on the SCL line Then the Master transmits the first byte on the SDA line containing the 7 bit Slave address plus the R W bit The Slave who owns that address will respond with an acknowledge bit on SDA and all other Slave devices will not respond Next the Master will transmit a data byte or bytes that the addressed Slave must receive The Slave will return an acknowledge bit after each data byte it successfully receives After the final byte is transmitted by the Master the Master will generate a STOP condition on the bus or it will generate a RE 3 uPSD34xx INTERFACE START and begin the next transfer There is no limit to the number of bytes that can be transmitted during a transfer session 2 Data transfer from Slave Transmitter to Master Receiver R W 1 In this case the Master generates a START condition on the bus and i
153. Master device and a Slave device on two wires More than one bus Master is allowed but only one Master may control the bus at any given time Data is not lost when another Master requests the use of a busy bus because supports collision de tection and arbitration The bus Master initiates all data movement and generates the clock that per mits the transfer Once a transfer is initiated by the Master any device addressed is considered a Slave Automatic clock synchronization allows devices with different bit rates to communicate on the same physical bus A single device can play Figure 41 Typical I C Bus Configuration the role of Master or Slave or a single device can be a Slave only Each Slave device on the bus has a unique address and a general broadcast ad dress is also available A Master or Slave device has the ability to suspend data transfers if the de vice needs more time to transmit or receive data This 12 interface has the following features Serial Engine SIOE serial parallel conversion bus arbitration clock generation and synchronization and handshaking are all performed in hardware nterrupt or Polled operation Multi master capability T bit Addressing Supports standard speed SCL up to 100kHz fast mode 2 101KHz to 400kHz and high speed mode 2 401KHz to 833kHz Vcc or Vpp SDA P8 6 5 7 uPSD33XX V Device with I2C Device
154. N A divisor must be chosen to produce a frequency for SIRCIk that lies between 1 34 MHz and 2 13 MHz but it is best to choose a divisor value that produces SIR Clk frequency as close to 1 83MHz as possible because SIRCIk at 1 83MHz will produce an fixed IrDA data pulse width of 1 63 Table 53 provides recommended values for CDIV 4 0 based on sev eral different values of fosc For reference SIRCIk of 2 13MHz will generate a fixed IrDA data pulse width of 1 4115 and SIRCIk of 1 34MHz will generate a fixed data pulse width of 2 23us Table 53 Recommended CDIV 4 0 Values to Generate SIRCIk default CDIV 4 0 OFh 15 decimal 11 059 or 12 00 7 3728 fosc MHz Value in CDIV 4 0 Resulting fsincLk MHz 36 864 or 36 00 14h 20 decimal 1 84 or 1 80 24 00 ODh 13 decimal 1 84 O6h 6 decimal 1 84 or 2 00 04h 4 decimal 1 84 Note 1 When PULSE bit 0 fixed data pulse width this is minimum recommended fosc because CDIV 4 0 must be 4 or greater 3 97 264 uPSD34xx INTERFACE 12 INTERFACE uPSD34xx devices support one serial inter face This is a two wire communication channel having a bi directional data signal SDA pin P3 6 and a clock signal SCL pin P3 7 based on open drain line drivers requiring external pull up resis tors Rp each with a typical value of 4 7kO see Figure 41 Interface Main Features Byte wide data is transferred MSB first between a
155. N function Bit 4 of PMMRO can be set to logic 71 to block CLKIN from reaching the PLD input bus but CLKIN will still reach the APD counter Bit 5 of PMMRO can be set to logic 71 to block CLKIN from reaching the OMC flip flops only but 224 264 CLKIN is still available to the PLD input bus and the APD counter See Table 144 page 219 for details SRAM Standby Mode battery backup The SRAM on the PSD Module may optionally be backed up by an external battery or other DC source to make its contents non volatile This is achieved by connecting a battery to pin PC2 on Port C and selecting the SRAM Standby function for pin PC2 within PSDsoft Express Automatic voltage supply cross over circuitry is built into the PSD Module to switch SRAM supply to battery as Soon as Vpp drops below the voltage level of the battery SRAM contents are protected while bat tery voltage is greater than 2 0V Pin PC4 on Port C can be used as an output to indicate that a bat tery switch over has occurred This is configured in PSDsoft Express by selecting the Standby On Indicator option for pin PC4 PSD Module Reset Conditions The PSD Module receives a reset signal from the MCU Module This reset signal is referred to as the RST input in PSD Module documentation and it is active low when asserted The character of the RST signal generated from the MCU Module is de scribed in SUPERVISORY FUNCTIONS page 67 Upon power up and w
156. N signal in Figure 89 page 222 Down Mode How can it do this if code memory is set and Power Down mode is entered immedi goes off line The answer is the Pre Fetch Queue ately when firmware sets the FORCE_PD Bit to PFQ in the MCU Module By using the instruction logic 1 in the csiop Register PMMR3 Bit 1 FPD scheme shown in the 8051 assembly code exam will override APD counter activity when ple in Table 147 the PFQ will be loaded with the FORCE_PD is set No external clock source for final instructions to command the MCU Module to the APD counter is needed The FORCE PD Bit is Power Down mode after the PDS Module goes to cleared only by a reset condition Power Down mode In this case even though the Caution must be used when implementing FPD code memory goes off line in the PSD Module the PSD Module Power Down mode is entered leav PFQ ing the MCU with no instruction stream to execute Table 147 Forced Power Down Example PDOWN ANL A8h 7Fh disable all interrupts ORL 9Dh COh ensure PFQ and BC are enabled MOV DPTR xxC7 load XDATA pointer to select PMMR3 register xx base address of csiop registers CLR A clear A JMP LOOP first loop fill PFQ BQ with Power Down instructions NOP second loop fetch code from PFQ BC and set Power Down bits for PSD Module and then MCU Module LOOP MOVX QDPTR A set FORCE PD Bit in PSD Module in second loop MOV 87h A set PD Bit in PCON Register in MCU Mod
157. O RESERVED A1 RESERVED Table A2 PCACLO PCACLO 7 0 00 93 page 155 Table A3 PCACHO PCACHO 7 0 00 93 page 155 Table A4 PCACONO EN EN EOVF1 PCA_IDL CLK SEL 1 0 00 96 page 160 Table A5 PCASTA OVF1 INTF5 INTF4 INTF3 OVFO INTF2 INTF1 INTFO 00 98 page 162 Table A6 WDRST WDRST 7 0 00 40 page 70 Table A7 IEA EADC ESPI EPCA ES1 EI2C 00 18 page 45 26 264 ky uPSD34xx SPECIAL FUNCTION REGISTERS SFR SFR SFR Bit Name and lt Bit Address gt Reset Reg Addr Name Value Descr hex 7 6 5 4 3 2 1 0 hex with Link Table EA ET2 Eso EX1 ETO EXO 1 Ag lt AFh gt lt ADh gt lt ACh gt lt ABh gt lt gt A9h A8h 00 di A9 PE MATCH TOGGLE PWN 1 0 00 TCMMODE Table AA EINTF PE _ MATCH TOGGLE PWM 1 0 00 99 page 163 AB EINTF MATCH TOGGLE PWM 1 0 00 CAPCOMLO 7 0 00 Table 93 page AD CAPCOMHO 7 0 00 155 Table AE WDKEY WDKEY 7 0 55 39 page 70 Table AF MdL CAPCOML1 7 0 00 93 page 155 P3 7 P36 p35 p34 p33 p32 P31 P30 i 1 Bo lt B7h gt B6h B5h lt B4h gt B3h B2h lt Bih gt lt Bon gt FF FE B1
158. PA4 PA3 PA2 PA1 PAO Note 1 Port A not available on 52 pin uPSD34xx devices 2 For each bit 1 out from uPSD34xx port pin1 0 in to PSD34xx port pin 3 Default state for register is OOh after reset or power up Table 131 MCU I O Mode Port B Direction In Register address csiop offset 07h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO Note 1 For each bit 1 out from uPSD34xx port pin1 0 in to PSD34xx port pin 2 Default state for register is OOh after reset or power up Table 132 MCU I O Mode Port C Direction Register address csiop offset 14h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit PC7 N A N A PC4 PC3 PC2 N A N A Note 1 For each bit 1 out from uPSD34xx port 1 0 in to PSD34xx port pin 2 Default state for register is OOh after reset or power up Table 133 MCU I O Mode Port D Direction Register address csiop offset 15h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit N A N A N A N A N A PD2 9 PD1 N A Note 1 For each bit 1 out from uPSD34xx port pin1 0 in to PSD34xx port pin 2 Default state for register is OOh after reset or power up 3 Not available on 52 pin uPSD34xx devices 204 264 uPSD34xx PSD MODULE PLD I O Mode Pins on Ports A B C and D can serve as inputs to either the DPLD or the GPLD Inputs to these PLDs from Ports A B and C are r
159. PSD MODULE Turbo Mode Current Consumption To deter mine the AC current component of the specific PLD design with Turbo mode on the user will have to interpolate from the graph given the number of product terms specified in the fitter report and the estimated composite frequency of PLD input sig nal transitions For the DC component y axis crossing the user can calculate the number by multiplying the number of product terms used from fitter report times the DC current per prod uct term specified in the DC specifications for the PSD Module The total PLD current usage is the sum of its AC and DC components Non Turbo Mode Current Consumption No tice in Figure 96 page 233 Figure 97 page 233 that when Turbo mode is off the DC current consumption is zero just standby cur rent when the composite frequency of PLD input transitions is zero no input transitions Now mov ing up the frequency axis to consider the AC cur rent component current consumption remains considerably less than Turbo mode until PLD input transitions happen so rapidly that the PLDs do not have time to latch their outputs and go to standby between the transitions anymore This is where the lines converge on the graphs and current con sumption becomes the same for PLD input transi tions at this frequency and higher regardless if Turbo mode is on or off To determine the current consumption of the PLDs with Turbo mode off ex trapolate the AC
160. PSD34xx MCU MODULE DISCRIPTION MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and peripherals in cluding m 8032 MCU Registers Special Function Registers 8032 Addressing Modes uPSD34xx Instruction Set Summary Dual Data Pointers Debug Unit Interrupt System MCU Clock Generation Power Saving Modes Oscillator and External Components Ports 8032 MCU REGISTERS The uPSD34xx has the following 8032 MCU core registers also shown in Figure 11 Figure 11 8032 MCU Registers Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose RO R7 Register Bank0 3 DPTR DPH DPTR DPL Data Pointer Register 106636 Stack Pointer SP The SP is an 8 bit register which holds the current location of the top of the stack It is incremented before a value is pushed onto the stack and dec remented after a value is popped off the stack The SP is initialized to 07h after reset This causes the stack to begin at location 08h top of stack To avoid overlapping conflicts the user must initialize the top of the stack to 20h if all four banks of reg isters RO R7 are used as well as the top of stack to 30h if all of the 8032 bit memory locations are used Data Pointer DPTR DPTR is a 16 bit register consisting of two 8 bit registers DPL and DPH The DPTR Register is used as a base register to create an address for in dir
161. Page register outputs feed directly into both PLDs creating extended address signals used to page memory beyond the 64K byte limit pro gram space or XDATA Most 8051 compilers di rectly support memory paging also known as memory banking If memory paging is not needed or if not all eight page register bits are needed for memory paging the remaining bits may be used in the General PLD for general logic Page Register outputs are cleared to logic 0 at reset and power up 166 264 Programmable Logic PLDs The uPSD34xx contains two PLDs Figure 74 page 188 that may optionally run in Turbo or Non Turbo mode PLDs operate faster less propagation delay while in Turbo mode but consume more power than in Non Turbo mode Non Turbo mode allows the PLDs to go to standby automatically when no PLD inputs are changing to conserve power The logic configuration from equations of both PLDs is stored with non volatile Flash technology and the logic is active upon power up PLDs may NOT be programmed by the 8032 PLD program ming only occurs through the JTAG interface Figure 63 Memory Page Register Page Register Chip Selects 8032 and Data General Logic Load or Read via csiop offset EOh PSD Module Reset Al09172 PLD 1 Decode PLD DPLD This programma ble logic implements memory mapping and is used to select one of the individual Main Flash memory segments one
162. Ports V V Output High Voltage loH 10 2 4 V OH Ports 4 push pull V V Output High Voltage loH mA 2 4 V one Port 0 push pull V V Output High Voltage loH 20 2 4 V Other Ports Bi directional mode V XTAL Open Bias Voltage _ XTAL1 XTAL2 lot 3 2mA 1 0 2 0 V RESET Pin Pull up Current IRST RESET Vin Vss 10 55 uA XTAL Feedback Resistor Current 2 E IFR XTAL1 XTAL1 Vcc XTAL2 Vss 20 Input High Leakage Current D 0 Vss lt lt 5 5 10 Input High Leakage Current _ E liHL2 Port 1 3 4 2 3V 10 Input Low Leakage Current E 1 3 4 Vip lt 0 5 10 126 3 Power down Mode 3 6V 65 95 uA Active 12MHz 14 20 mA Vcc 3 6V Idle 12MHz 10 12 mA Icc CPU Active 24MHz 19 30 mA Notes Voc 3 6V 4 5 6 Idle 24MHz 13 17 mA Active 40MHz 26 40 mA Vcc 3 6V Idle 40MHz 17 22 mA uPSD34xx DC AND AC PARAMETERS Table 157 PSD Module DC Characteristics with 5V Vpp Test Condition Symbol Parameter in addition to those in Min Typ Max Unit Table 156 page 238 Input High Voltage 4 5V Vpp 5 5V V Input Low Voltage 4 5V lt Vpp lt 5 5V Vpp min for Flash Erase and VLko Program y lot 20uA Vpp 4 5V V VoL Output Low Voltage lo 8mA Vpp 4 5V i V Output High Voltage Except 20 Vpp 4 5V 4 4 4 49 V
163. Q7 returns to the value of D7 of the previ ously addressed byte No erasure is performed Toggle Flag DQ6 The Flash memories offer an alternate way to determine when a Flash memory program operation has completed During the pro gram operation and while the correct sector select FSx or CSBOOTx is active the Toggle Flag Bit DQ6 toggles from 0 to 1 and 1 to 0 on subse quent attempts to read any byte of the same Flash array When the internal program operation is complete the toggling stops and the data read on the data bus DO 7 is the actual value of the addressed memory byte The device is now accessible for a new READ or WRITE operation The operation is finished when two successive READs yield the same value for DQ6 DQ6 may also be used to indicate when an erase operation has completed During an erase opera tion DQ6 will toggle from 0 to 1 and 1 to 0 until the erase operation is complete then DQ6 stops toggling The erase is finished when two succes sive READs yield the same value of DQ6 The cor rect sector select signal FSx or CSBOOTx must be active during the entire procedure DQ6 is valid after the fourth instruction byte WRITE operation for program instruction se quence or after the sixth instruction byte WRITE operation for erase instruction sequence If all the Flash memory sectors selected for era sure are protected DQ6 toggles to 0 for about 100ys then returns value of D6 of
164. Register When External Clock is selected the maximum clock frequency should not exceed fosc 4 Table 94 CCON2 Register Bit Definition SFR OFBh Reset Value 10h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCAOPS3 PCAOPS2 PCAOPS1 PCAOPSO Details Bit Symbol R W Definition PCAO Clock Enable 3 R W 0 is disabled 1 PCAOCLK is enabled default Prescaler PCAOPS a 3 0 RW PCAoCLK fosc 2 5 3 0 Divisor range 1 2 4 8 16 16384 32768 Table 95 CCONS Register Bit Definition SFR OFCh Reset Value 10h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCA1CE PCA1PS3 PCA1PS2 PCA1PS1 PCA1PSO Details Bit Symbol R W Definition PCA1 Clock Enable 4 1 R W 0 PCAICLK is disabled 1 PCA1CLK is enabled default 1 Prescaler 1 5 50 3 0 PW tecaicik fosc 2 PCA1PS 3 0 Divisor range 1 2 4 8 16 16384 32768 156 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM Operation of TCM Modes Each of the TCM in a PCA block supports four modes of operation However an exception is when the TCM is configured in PWM Mode with programmable frequency In this mode all TCM in a PCA block must be configured in the same mode or left to be not used Capture Mode The CAPCOM registers in the TCM are loaded with the counter values when an external
165. Reserved al 2 0 EP R W Reserved Endpoint Selects Bits 0 EndpointO 1 Endpoint 2 Endpoint2 3 Endpoint3 4 Endpoint4 3 145 264 uPSD34xx USB INTERFACE USB Endpoint Control Register UCON Register see Table 83 The USB Endpoint The Endpoint selected by the USB Endpoint Control Register is used to control the Select Register see Table 82 page 145 selected Endpoint and provides some status determines the direction and FIFO IN or OUT about that Endpoint that is controlled by the USB Endpoint Control Table 83 USB Endpoint Control Register OF1h Reset Value 00h 146 264 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E STALL TOGGLE Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ENABLE R W Selected FIFO Enable Bit Stall Control Bit 2 STALL R W When this bit is set the Endpoint returns a STALL handshake whenever it receives an IN or OUT token Data Toggle Bit Endpoint IN Case The state of this bit determines the type of data packet 0 or 1 1 that will be sent during the next IN transaction The CPU is 1 TOGGLE R W responsible for toggling this bit for every IN transaction Endpoint OUT Case The state of this bit indicates the type of data packet PID that was received with the last OUT transaction OZDATAO 1 DATA1 The CPU is respon
166. S1 PUSB Details Bit Symbol R W Function 70 PADC RW ADC Interrupt priority level 61 PSPI RW SPI Interrupt priority level 50 PPCA RW PCA Interrupt level 40 PS1 RW UART1 Interrupt priority level 3 Reserved 2 Reserved 100 RW 2 Interrupt priority level 0 PUSB R W USB Interrupt priority level MCU CLOCK GENERATION Internal system clocks generated by the clock gen eration unit are derived from the signal XTAL1 shown in Figure 14 XTAL1 has a frequency fosc which comes directly from the external crystal or oscillator device The SFR named CCONO Table 22 page 49 controls the clock generation unit There are two clock signals produced by the clock generation unit m m MCU_CLK This clock drives the 8032 MCU core and the Watchdog Timer WDT The frequency of MCU_CLK is equal to fosc by default but it can be divided by as much as 2048 shown in Figure 14 The bits CPUPS 2 0 select one of eight different divisors ranging from 2 to 2048 The new frequen cy is available immediately after the CPUPS 2 0 bits are written The final frequency of is fucu MCU_CLK is blocked by either bit PD or IDL in the SFR named PCON during MCU Power down Mode or Idle Mode respectively MCU CLK clock can be further divided as re quired for use in the WDT See details of the WDT in SUPERVISORY FUNCTIONS page 67 PERIPH CLK This clock drives all the uPSD34xx pe
167. SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI Transmit T N MM Start Bit bo X Di X D2 X D3 X D4 X D5 X 06 X 07 X TB8 Stop Bit a 2 In n n m nm mm m nm Start Bit 50 X Di 52 X ps X 54 X ps X De X 57 Y Stop Bit MOMO mu gmL TTL N IL LLLI Receive 106847 93 264 uPSD34xx IrDA INTERFACE IrDA INTERFACE uPSD34xx devices provide an internal IrDA inter face that will allow the connection of the UART1 serial interface directly to an external infrared transceiver device The IrDA interface does this by automatically shortening the pulses transmitted on UART1 s TxD1 pin and stretching the incoming pulses received on the RxD1 pin Reference Fig ures 39 and 40 When the IrDA interface is enabled the output sig nal from UART t s transmitter logic TxD1 is Figure 39 IrDA Interface SIRCIk IrDA Interface uPSD34xx compliant with the IrDA Physical Layer Link Spec ification v1 4 www irda org operating from 1 2k bps up to 115 2k bps The pulses received on the RxD1 pin are stretched by the IrDA interface to be recognized by UART1 s receiver logic also adher ing to the IrDA specification up to 115 2k bps Note In Figure 40 a logic 0 in the serial data stream of a UART Fr
168. SD34xx PSD MODULE Figure 75 DPLD Logic Array NUMBER OF PRODUCT TERMS PLD INPUT BUS M En 3 FS1 SS 3 FS2 PSM MODULE RESET RST cmm 3 FS3 FLASH POWER DOWN INDICATOR PDN H St TET TE MEMORY E 3 gt FS4 SECTOR PIN INPUT PORTS A B C IMCs pi SELECTS 3 FS5 PIN INPUT PORT D 3 FS6 PAGE REGISTER PGRO PGR7 pi 3 FS7 OMC FEEDBACK MCELLAB FBO 7 3 gt CSBOOTO OMC FEEDBACK MCELLBC FBO 7 i T CSBOOT SECONDARY FLASH FLASH MEM PROG STATUS RDYBSY 1 9 1 MEMORY Bil iii 13 5 CSBOOT SECTOR SELECTS 3 CSBOOT3 ANAT 2 RSO SRAM E amp CONTROL 1 CSIOP REGISTERS HOC cn 1 ECSO EXTERNAL CHIP D PORT D 1 PSELO PERIPHERAL MODE 1 PSEL1 RANGE SELECTS AI06601A 190 264 ky General PLD GPLD The GPLD is used to cre ate general system logic Figure 74 page 188 shows the architecture of the entire GPLD and Figure 76 page 192 shows the relationship be tween one one IMC and one port pin which is representative of pins on Ports A B and C It is important to understand how these ele ments work together A more detailed description will follow for the three major blocks IMC O Port shown in Figure 76 Figure 76 also shows which csiop registers to access for various PLD and I O functions uPSD34xx PSD MODULE The GPLD contains m 16 Output Macrocells OMC
169. SDsoft Express No WRITEs Read to determine if PSD Module Security Bit device Security Bit is active non and Secondary volatile Logic 1 device secured Also Flash Sector read to determine Secondary Flash Protection Protection Setting non volatile that was specified in PSDsoft No WRITEs Power Management Register 0 WRITE PMMRO and READ Power Management Register 2 WRITE and READ Power Management Register 3 WRITE PMMR3 and READ However Bit 1 can be cleared only by a reset condition Memory Page Register WRITE and READ Places PSD Module memories into 8032 Program Address Space and or 8032 VM Virtual XDATA Address Space VM overrides Memory initial non volatile setting that was 3 specified PSDsoft Express Reset restores initial setting 177 264 uPSD34xx PSD MODULE PSD Module Detailed Operation Specific details are given here for the following key functional areas on the PSD Module m Flash Memories m PLDs DPLD and GPLD m Ports m Power Management m JTAG ISP and Debug Interface Flash Memory Operation The Flash memories are accessed through the 8032 Address Data and Control Bus interfaces Flash memories and SRAM cannot be accessed by any other bus master other than the 8032 MCU these are not dual port memories The 8032 cannot write to Flash memory as it would an SRAM supply address supply data supply WR strobe assume the data was corre
170. SR must read the USB Interrupt Flag Registers UIFO 3 to determine the source of the interrupt The USB interrupt can be activated by any of the following four group of interrupt sources Global the interrupt flag is set when any of the following events occurs USB Reset USB Suspend USB Resume and End of Packet In FIFO the interrupt flag is set when any of the End Point In FIFO becomes empty Out FIFO the interrupt flag is set when any of the End Point Out FIFO becomes full and In FIFO the interrupt is set when any of the End Point In FIFO is not ready for an IN in bound packet uPSD34xx INTERRUPT SYSTEM Table 17 IE Interrupt Enable Register SFR A8h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EA ET2 ESO ET1 EX1 ETO EXO Details Bit Symbol R W Function Global disable bit 0 All interrupts are disabled 1 Each interrupt 7 EA R W source can be individually enabled or disabled by setting or clearing its enable bit Do not modify this bit It is used by the JTAG debugger for instruction 6 R W tracing Always read the bit and write back the same bit value when writing this SFR 50 ET2 RW Enable Timer 2 Interrupt 40 ESO RW Enable UARTO Interrupt 30 RW Enable Timer 1 Interrupt 20 EX1 RW Enable External Interrupt INT1 10 ETO RW Enable Timer 0 Interrupt o RW Enable External Interrupt INTO Note 1 1 Enable Int
171. Specifications at the end of this docu ment to estimate current consumption based on the MCU clock frequency Note Some of the bits in the PCON SFR shown in Table 26 page 52 are not related to power con trol Table 24 MCU Module Port and Peripheral Status during Reduced Power Modes PCA SPI SUPER Mode Ports 1 3 4 UARTO 1 ber USB ADC EXT INTO 1 VISORY Idle Maintain Data Active Active Active Active Active Active Power down Maintain Data Disabled Disabled Disabled Disabled Disabled Disabled Note 1 The Watchdog Timer is not active during Idle Mode Other supervisor functions are active LVD external reset JTAG Debug reset Table 25 State of 8032 MCU Bus Signals during Power down and Idle Modes Mode ALE PSEN_ Idle 0 1 Power down 0 1 51 264 uPSD34xx POWER SAVING MODES Table 26 PCON Power Control Register Gi 87h reset value me es wr Bit 7 SMODO Bit 6 SMOD1 RCLK1 TCLK1 Details Bit SMODO SMOD1 R W Baud Rate Double Bit UARTO 0 No Doubling 1 Doubling See UART Baud Rates page 86 for details Baud Rate Double Bit for 2nd UART UART1 0 No Doubling 1 Doubling See UART Baud Rates page 86 for details Reserved POR RCLK1 TCLK1 PD R W R W R W Only a power on reset sets this bit cold reset Warm reset will not set this bit 0 Cleared to zero with firmware 1
172. TAG debug channel re set event 185 264 uPSD34xx PSD MODULE Flash Memory Sector Protection Each Flash memory sector can be separately protected against program and erase operations This mode can be activated or deactivated by selecting this feature in PSDsoft Express and then programming through the JTAG Port Sector protection can be selected for individual sectors and the 8032 can not override the protection during run time The 8032 can read but not change sector protection Any attempt to program or erase a protected Flash memory sector is ignored The 8032 may read the contents of a Flash sector even when a sector is protected Sector protection status is not read using Flash memory instruction sequences but instead this status is read by the 8032 reading two registers within csiop address space shown in Table 109 and Table 110 Flash Memory Protection During Power Up Flash memory WRITE operations are automatical ly prevented while Vpp is ramping up until it rises above voltage threshold at which time Flash memory WRITE operations are allowed PSD Module Security Bit A programmable se curity bit in the PSD Module protects its contents from unauthorized viewing and copying The secu rity bit is set using PSDsoft Express and pro grammed into the PSD Module with JTAG When set the security bit will block access of JTAG pro gramming equipment from reading or modifying the PSD Module Flash memory and P
173. USCON and the MCU clock divider selections in the SFR CCONO i e a ma chine cycle is typically set to 4 MCU clocks for a 5V uPSD34xx However an individual machine cycle may grow in duration when either of two things happen Table 6 Arithmetic Instruction Set Mnemonic and Use 1 astall is imposed while loading the 8032 Pre Fetch Queue PFQ or 2 the occurrence of a cache miss in the Branch Cache BC during a branch in program execution flow See 8032 MCU CORE PERFORMANCE ENHANCEMENTS page 18 or more details But generally speaking during typical program ex ecution the PFQ is not empty and the BC has no misses producing very good performance without extending the duration of any machine cycles The uPSD34xx Programmers Guide describes each instruction operation in detail Description Length Cycles ADD A Rn Add register to ACC 1 byte 1 cycle ADD A Direct ADD A Ri Add direct byte to ACC Add indirect SRAM to ACC 2 byte 1 cycle 1 byte 1 cycle ADD A data Add immediate data to ACC 2 byte 1 cycle ADDC A Rn Add register to ACC with carry 1 byte 1 cycle ADDC A Ri Add indirect SRAM to ACC with carry 1 byte 1 cycle ADDC A data Add immediate data to ACC with carry 2 byte 1 cycle SUBB Subtract register from ACC with borrow 1 byte 1 cycle SUBB A direct Subtract direct byte from ACC with borrow 2 byte 1 cycle SUBB A Ri Subtract indirect SRAM from ACC with borrow 1
174. W GPIO SPI Transmit SPITXD ADC Chn 6 Input ADC6 7 R W GPIO SPI Select SPISEL_ ADC Chn 7 Input ADC7 61 264 uPSD34xx I O PORTS of MCU MODULE Table 34 P4SFSO Port 4 Special Function Select 0 Register SFR 92h reset value 00h P4SF07 45 06 45 05 45 04 P4SF03 P4SF02 P4SFO1 P4SF00 Details Table 35 P4SFS1 Port 4 Special Function Select 1 Register SFR 93h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4SF17 P4SF16 PASF15 P4SF14 P4SF13 P4SF12 PASF11 PASF10 Table 36 PASFSO and P4SFS1 Details Default Port Function Alternate 1 Port Function Alternate 2 Port Function Port4Pin RAW PASSI x PASFSI I 0 PASFSI I 1 Port 4 Pin i 0 7 Port 4 Pin i 0 7 Port 4 Pin i 0 7 0 RW GPIO PCAO Module 0 TCMO Timer 2 Count Input T2 1 RW GPIO PCAO Module 1 TCM1 Timer 2 Trigger Input TX2 2 RW GPIO PCAO Module 2 TCM2 UART1 Receive RXD1 3 RW GPIO PCAO Ext Clock PCACLKO 4 RW GPIO PCA1 Module 3 TCM3 SPI Clock SPICLK 5 RW GPIO PCA1 Module 4 TCM4 6 RW GPIO PCA1 Module 5 5 7 RW GPIO PCA1 Ext Clock PCACLK1 SPI Select SPISEL 62 264 MCU BUS INTERFACE The MCU Module has a programmable bus inter face which is a modified 8032 bus with 16 multi plexed address and data lines The bus supports four types of data transfer 16 or 8 bit each transfer is to from a memory location external to the MCU Mo
175. XXXXXb OOh default 1 1 0000000b 80h 1 1 0000001b 81h 2 1 0000010b 82h 3 1 0001011b 8Bh 12 1 0010111b 97h 24 1 1111111b FFh 128 Table 61 Start Condition Hold Time PC Bus S d R t C Clock 6 46 Minimum START Condition Hold us Spee ange o ock Speed fsci Time tui psrA Standard Up to 100KHz 4000ns 101KHz to Fast 400KHz 600ns High 401KHz to 833KHz 160ns Note 1 833KHz is maximum for UPSD34xx devices 109 264 uPSD34xx INTERFACE Table 62 provides recommended settings for Important The SCL bit rate fsc must first be de S1SETUP based on various combinations of fosc termined by bits CR 2 0 in the SFR S1CON be and fsc Note that the Total Sample Period fore a value is chosen for SMPL SET 6 0 in the times in Table 61 page 109 are typically slightly SFR S1SETUP less than the minimum START condition hold time tHLpsTA for a given 2 bus speed Table 62 STSETUP Examples for Various 2 Bus Speeds and Oscillator Frequencies Bus Oscillator Frequency fosc Speed Parameter fscL Recommended S1SETUP Value Standard Number of Samples 20 Time Between Samples 166 6ns Total Sampled Period 3332ns 3332ns 3332ns 3333ns 3200ns Recommended S1SETUP Value Seh BER n Fast Number of Samples 3 6 12 17 Time Between Samples 30ns Total Sampled Period 500ns 500ns 510ns 500ns Recommended S1SETUP Value Note 1 30 Re id High Number of Samples 1 3 4 5 Time Between Samples 83 3
176. _ CSI Valid to Data Valid 27 3 68 na tRLav Pa RD to Data Valid Note 2 32 ns tDVQV PA Data In to Data Out Valid 22 ns tnHaz PA RD to Data High Z 23 ns Note 1 Any input used to select Port A Data Peripheral Mode 2 Data is already stable on Port A Table 175 Port A Peripheral Data Mode READ Timing 3V PSD Module Note 1 Any input used to select Port A Data Peripheral Mode 2 Data is already stable on Port A 252 264 Symbol Parameter Conditions tavav PA Address Valid to Data Valid Note 1 tsiav PA CSI Valid to Data Valid tmLov PA RD to Data Valid tpvav PA Data In to Data Out Valid 2 RD to Data High Z Figure 107 Peripheral I O WRITE Timing A D BUS ADDRESS uPSD34xx DC AND AC PARAMETERS lt gt tDVQV PA DATA OUT gt twHoz PA PORTA DATA OUT Al06611 Table 176 Port A Peripheral Data Mode WRITE Timing 5V PSD Module Symbol Parameter Conditions Min Max Unit twiov PA WR to Data Propagation Delay 25 ns tpvov PA Data to Port A Data Propagation Delay Note 1 22 ns twHoz PA WR Invalid to Port A Tri state 20 ns Note 1 Data stable on Port 0 pins to data on Port A Table 177 Port A Peripheral Data Mode WRITE Timing 3V PSD Module Note 1 Data stable on Port 0 pins to data on Port A Table 178 Supervisor Reset and LVD Symbol Parameter Conditions twiov P
177. a fixed priority see PSD Module Functional Description page 165 this is not the case with the USB FIFOs Unpredictable results as well as potential damage to the device may occur if there is an overlap of addresses Table 85 USB FIFO Base Address High Register UBASEH OF3h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASEADDR 15 8 Details Bit Symbol R W Definition 7 0 BASEADDR R W The upper 8 bits of the 16 bit base address for USB FIFOs to be mapped 15 8 in XDATA space Table 86 USB FIFO Base Address L ow Register UBASEL OF4h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASEADDR T7 6 0 0 0 0 0 0 Details Bit Symbol R W Definition 7 6 BASEADDR R W Bits 7 and 6 of the 16 bit base address for the USB FIFOs to be mapped 7 6 in XDATA space 5 0 ear R Hardwired 0 148 264 uPSD34xx USB INTERFACE USB Setup Command Index and Value Command Index Register see Table 87 Registers USCI and USCV determines which one of the eight bytes in the When a Setup Data packet is received over buffer is read using the USB Setup Command the USB the 8 bytes of data received are Value Register see Table 88 stored in a command buffer The USB Setup Table 87 USB Setup Command Index Register USCI OF5h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 De
178. accesses the SRAM Any address in the range of CSBOOTO greater than 87FFh and less than 9FFFh auto matically addresses Secondary Flash memory Any address greater than 9FFFh accesses Main Flash memory One half of the Main Flash memo ry segment and one fourth of the Secondary Flash memory segment cannot be accessed by the 8032 Figure 69 PSD Module Memory Priority Highest Priority Level 1 SRAM CSIOP and Peripheral I O Mode Level 2 Secondary Flash Memory Level 3 Main Flash Memory Lowest Priority AI02867E uPSD34xx PSD MODULE The VM Register One of the csiop registers the VM Register controls whether or not the 8032 bus control signals RD WR and PSEN are routed to the Main Flash memory or the Secondary Flash memory Routing of these signals to these PSM Module memories determines if memories reside in 8032 program address space 8032 XDATA space or both The initial setting of the VM Regis ter is determined by a choice in PSDsoft Express and programmed into the UPSD34xx in a non vol atile fashion using JTAG This initial setting is loaded into the VM Register upon power up and also loaded upon any reset event However the 8032 may override the initial VM Register setting at run time by writing to the VM Register which is useful for IAP Table 104 page 174 defines bit functions within the VM Register Note Bit 7 PIO_EN is not related to the memory manipulation fu
179. ach bit 1 pin drive is enabled as an output 0 pin drive is off high impedance pin used as input Table 143 Port D Enable Out Register address csiop offset 1Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit N A N A N A N A N A PD2 OE PD1 N A Note 1 For each bit 1 pin drive is enabled as an output 0 pin drive is off high impedance pin used as input 2 Pin is not available on 52 pin uPSD34xx devices 211 264 uPSD34xx PSD MODULE Individual Port Structures Ports A B C and D have some differences The structure of each indi vidual port is described in the next sections Port A Structure Port A supports the following operating modes MCU Mode GPLD Output Mode from Output Macrocells MCELLABx GPLD Input Mode to Input Macrocells IMCAx Latched Address Output Mode Peripheral I O Mode Figure 85 Port A Structure FROM OR ARRAY FROM PLD gt INPUT BUS FROM OMC ALLOCATOR PT OUTPUT ENABLE OE PSD MODULE RESET DIRECTION MCUI O DATA OUT LATCHED ADDR BIT D PERIPH MODE D 7 DIRECTION 8032 P2 DATA D4 B M 4 x 8032 ADDRESS DATA CONTROL BUS A MCUI O ENABLE OUT U5 c DATA IN MCUI O ONE of 6 CSIOP REGISTERS TO IMCs lt lt 1 OPENi 1 4 7 Nr Voo y j o OUTPUT PERIPH DATA BIT
180. al I O or Data memory devices The READ and WRITE data transfer is carried out on the AD 7 0 bus which is available in the 80 pin package The ad dress lines can be brought out to the external de vices in one of three ways 1 Configure Ports B and A of the PSD Module in Address Output mode as shown in Figure 20 2 Use Port B together with an external latch as shown in Figure 21 page 64 The external latch latches the low address byte from the AD 7 0 bus with the ALE signal This configuration is for design where Port A is needed for CPLD functions and 3 Configure the microcell in the CPLD to output any address line to any of the CPLD output pins This is the most flexible implementation but requires the use of CPLD resources Ports A and B in the PSD Module can be config ured in the PSDsoft to provide latched MCU ad dress A 7 0 and A 15 8 see PSD Module Detailed Operation page 178 for details on how to enable Address Output mode The latched ad dress outputs on the ports are pin configurable For example Port B pins PB 2 0 can be enabled to provide A 10 8 and the remaining pins can be configured for other functions such as generating chip selects to the external devices Figure 20 Connecting External Devices using Ports A and B for Address AD 15 0 uPSD34xx MCU PSD Module Module RD or WR External 8 bit RD or WR Device 110434 63 264
181. al during reset then these floating inputs should be pulled up externally to Vpp with a weak 100KQ minimum resistor In PLD I O mode pins of Ports A B C and D may also float during reset if no external device is driv uPSD34xx PSD MODULE ing them and if there is no equation specified for the DPLD or GPLD to make them an output In this case a weak external pull up resistor 100KQ min imum should be used on floating pins to avoid ex cessive current draw The pins on Ports 1 3 and 4 of the 8032 MCU module do have weak internal pull ups and the in puts will not float so no external pull ups are need ed Table 148 Function Status During Power Up Reset Warm Reset Power down Mode Port Configuration Power Up Reset APD Power down Mode Warm Reset Pin logic state is loaded Happens long before RST is de asserted MCU I O Pins are in input mode Pins are in input mode unchanged Pin logic is valid after Pin logic depends on inputs internal PSD Module Pin logic is valid and is to PLD 8032 addresses PLD I O configuration bits are determined by PLD logic are blocked from reaching equations PLD inputs during power down mode Latched Address Out Mode Pins are High Impedance Pins are High Impedance Pins logic state not defined since 8032 address signals are blocked Peripheral I O Mode Pins are High Impedance Pins are High Impedance Pins are High Impedance JTAG ISP and Debug JTAG
182. ally generated when any one of the following five events occur When the SIOE receives an address that matches the contents of the SFR S1ADR Requirements SIOE is in Slave Mode and bit 1 in the SFR S1CON When the SIOE receives General Call address Requirments SIOE is in Slave Mode bit AA 1 in the SFR S1CON uPSD34xx INTERFACE When a complete data byte has been received or transmitted by the SIOE while in Master mode The interrupt will occur even if the Master looses arbitration When a complete data byte has been received or transmitted by the SIOE while in selected Slave mode ASTOP condition on the bus has been recognized by the SIOE while in selected Slave mode Selected Slave mode means the device address sent by the Master device at the beginning of the current data transfer matched the address stored in the S1ADR register If the interrupt is not enabled the MCU may poll the INTR flag in S1STA 105 264 uPSD34xx INTERFACE Table 56 S1STA 12 Interface Status register SFR reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit GC Details Bit STOP Symbol INTR R W TX_MODE BBUSY BLOST ACK_RESP SLV Function GC General Call flag GC 1 if the General Call address of 00h was received when SIOE is in Slave mode and GC is cleared by a START or STOP condition on the bus If the SIOE is in Master
183. ame 8032 Address Bus 0 15 PSEN RD WR 8032 Bus Control Signals ALE Reset from MCU Module RESET Power Down from Auto PDN Power Down Counter PortA Input Macrocells 80 pin devices only PortB Input Macrocells PBO PB7 PC2 PC3 PC4 PortC Input Macrocells PC7 Port D Inputs 52 pin devices have only PD1 PD2 PD1 Page Register PGRO PGR7 Macrocell OMC bank MCELLAB 8 Feedback FBO 7 Macrocell OMC bank BC MCELLBC 8 Feedback FBO 7 Flash memory Status Bit Ready Busy 1 187 264 uPSD34xx PSD MODULE Figure 74 DPLD and GPLD snd ce08 a 1HOd 519v8Q33H Nid 3 g S1LYOd 5Iovgaaad Nid STTSDOYOVIN 02 8 V 1HOd sna v1va ce08 HOLVO Ino aid 8 110 01 8 SLNdNI 69 xs93 5 195 si ejes ejedued lt _ 4 _ 2 dOISO 199195 1HOd lt 69 0Su 9919S WWHS lt L XLOO8S2 sp j s use 4 402 X84 spajes Aiowey use 4 807 snd LNdNI S IVN9SIS YAHLO 92151999 ADVd IOHLNOO SNA 2608 SS3uaqv 2608 AI06600A 188 264 Decode PLD DPLD The DPLD Figure 75 page 190 generates the following memory decode signals m Eight Main Flash memory sector selec
184. ame corresponds to a logic high pulse in an IR Frame A logic 1 in a UART Frame corresponds to no pulse in an IR Frame TxD1 IrDA IrDA Transceiver RxD1 IrDA 110437 Figure 40 Pulse Shaping by the IrDA Interface Start Bit UART Frame 4 IR Frame gt lt Bit Time UART Frame lt ___________ Data Bits Stop 4 Bit IR Frame Stop Bit Pulse Width 3 16 Bit Time 110438 94 264 The UART1 serial channel can operate in one of four different modes as shown in Table 46 page 83 in the section SERIAL UART INTERFACES page 83 However when UART1 is used for IIDA communication UART1 must op erate in Mode 1 only to be compatible with IrDA protocol up to 115 2k bps The IrDA interface will support baud rates generated from Timer 1 or Tim er 2 just like standard UART serial communica tion but with one restriction The transmit baud rate and receive baud rate must be the same can not be different rates as is allowed by standard UART communications The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the SFR named IRDACON Table 50 page 95 When uPSD34xx IrDA INTERFACE IrDA is disabled the UART1 s RxD and TxD sig nals will bypass the internal IrDA logic and instead they are routed directly to the pins RxD1 and TxD1 respectively When IrDA is enabled the IrDA pulse shaping logic is a
185. and the ENDP field contains the endpoint within the addressed de vice The CRC5 is a Cyclic Redundancy Check for error checking The data packet contains a DATA1 or DATAO PID In a USB system the host or device that is sending data is responsible for toggling the data PID be tween DATAO DATAt1 The receiving device keeps track of the Toggle Bit and compares it with the data PID that is received This provides a means for the receiving host or device to detect a corrupted handshake packet The Payload Data is the data that the host is sending to the device and the CRC16 is used for error checking For an OUT transaction the host sends the token and data packets The receiving device sends a handshake packet to notify the host whether it was able to accept the packet or not There are three handshake PIDs as follows ACK this PID indicates that the device received the data successfully this handshake indicates that the device was not able to receive the data itis busy A NAK does not mean there was an error since errors are indicated by a no handshake packet When the host receives a NAK PID or does not receive a handshake packet at all the host retries sending the data at a later time STALL this handshake indicates that something is wrong For example the host has sent a device request that is not understood the host is trying to access a resource that is not available or something is wr
186. ariables that determine the mode mode lt I2C master I2C slave If mode is Master Transmitter Bus Arbitration lost sta tus BLOST 1 If Yes Arbitration was lost S1DAT dummy write to release bus Exit ISR SIOE will switch to Slave Recv mode If No Arbitration was not lost continue ACK recvd from tus ACK 5 0 If No an ACK was not received Slave sta 1CON STO 1 set STOP bus condi tion STOP occurs after ISR exit S1DAT dummy write to release bus Exit ISR If Yes ACK was received then continue S1DAT xmit buf buffer index transmit byte Was that the last byte of data to transmit If No it was not the last byte then Exit ISR transmit next byte on next interrupt If Yes it was the last byte then 1CON STO 1 set STOP bus condi ion STOP occurs after ISR exit gt NA tN 1DAT dummy write to release bus Exit ISR 1572 Else If mode is Master Receiver Bus Arbitration lost sta tus BLOST 1 If Yes Arbitration was lost S1DAT dummy write to release bus Exit ISR SIOE will switch to Slave Recv mode If No Aribitration was not lost continue Is this Interrupt from sending an ad dress to Slave or is it from receiv ing a data byte from Slave If its from sending Slave ad dress goto A If it
187. ated at address 4000h the resulting jump Will be made to 4500h Long Addressing This mode will use the 16 bits contained in the two bytes following the instruction byte as a jump des tination address for LCALL and LJMP instructions For example LJMP 0500h Unconditionally jump to address 0500h in program memory Bit Addressing This mode allows setting or clearing an individual bit without disturbing the other bits within an 8 bit value of internal SRAM Bit Addressing is only available for certain locations in 8082 DATA and SFR memory Valid locations are DATA address es 20h 2Fh and for SFR addresses whose base address ends with Oh or 8h Example The SFR IE has a base address of A8h so each of the eight bits in IE can be addressed individually at address A9h up to AFh For example SETB AFh Set the individual EA bit Enable All Interrupts inside the SFR Register IE uPSD34xx uPSD34xx INSTRUCTION SET SUMMARY uPSD34xx INSTRUCTION SET SUMMARY Tables 6 through 11 list all of the instructions sup ported by the uPSD34xx including the number of bytes and number of machine cycles required to implement each instruction This is the standard 8051 instruction set The meaning of machine cycles is how many 8032 MCU core machine cycles are required to execute the instruction The native duration of all machine cycles is set by the memory wait state settings in the SFR B
188. atements of the ABEL language for the DPLD such as those shown in Table 103 Specifying these equations using PSDsoft Ex press is very simple For example Figure 65 page 84 shows how to specify the chip select equation for the 16K byte Flash memory segment fs4 No tice fs4 is on memory page 1 This specification process is repeated for all other Flash memory segments the SRAM the csiop register block and any external chip select signals that may be need ed Table 103 HDL Statement Example Generated from PSDsoft Express for Memory Map 50 address gt 0000 address hlFFF csiop address gt h2000 6 address lt h20FF 0 address gt h0000 6 address lt h3FFF address gt h4000 6 address lt h7FFF fs2 page 0 amp address 2 h8000 amp address lt hBFFF fs3 page 0 amp address 2 hC000 amp address lt hFFFF fs4 page 1 amp address 2 h8000 amp address lt hBFFF fs5 1 amp address gt hC000 amp address lt hFFFF fs6 page 2 amp address gt h8000 6 address lt hBFFF fs7 page 2 amp address 2 hC000 amp address lt hFFFF csboot0 address 2 h8000 amp address h9FFF csboot1 address gt 000 6 address lt hBFFF csboot2 address 2 hC000 amp address lt hDFFF csboot3 address gt hE000 amp address lt hFFFF
189. ation furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 1572 264 264
190. ber of clock periods for RD or WR cycles see Figure Figure 22 page 65 64 264 External 8 bit RD or WR Device Controlling the PFQ and BC The BUSCON Register allows firmware to enable and disable the PFQ and BC at run time Some times it may be desired to disable the PFQ and BC to ensure deterministic execution The dynamic action of the PFQ and BC may cause varying pro gram execution times depending on the events that happen prior to a particular section of code of interest For this reason it is not recommended to implement timing loops in firmware but instead use one of the many hardware timers in the uPSD34xx By default the PFQ and BC are en abled after a reset condition Important Disabling the PFQ or BC will seriously reduce MCU performance uPSD34xx MCU BUS INTERFACE Figure 22 A RD or PSEN Bus Cycle Set to 5 MCU_CLK 1 MCU Clock ALI Ly Ly LI LI LJ ALE 222240 29001 022 0 0 0 s 2 3 4 5 5 Clock Bus Cycle gt 110436 Note 1 The PSEN cycle is 16 bit while the RD cycle is 8 bit only 2 A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch Cache BC determines the current code fetch cycle is not needed 3 Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN and RD cycles the bus cycle timing is typically identical for each of these types of bus cycles In this case the only time PSEN read cycl
191. by 16 counter not to the writing of SBUF Transmission begins with activation of SEND which puts the start bit at pin TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to pin TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeros are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX Control unit to do one last shift and then deac tivates SEND and sets the interrupt flag TI This occurs at the 10th divide by 16 rollover after a write to SBUF Reception is initiated by a detected 1 to 0 transi tion at the pin RxD For this purpose RxD is sam pled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFH is written into the input shift register Reset ting the divide by 16 counter aligns its rollovers uPSD34xx SERIAL UART INTERFACES with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples Thi
192. byte 1 cycle SUBB A data Subtract immediate data from ACC with borrow 2 byte 1 cycle 1 byte 1 cycle 1 byte 1 cycle INC Increment indirect SRAM A INC Rn Increment register INC direct Increment direct byte A 2 byte 1 cycle 1 byte 1 cycle DEC Decrement ACC 1 byte 1 cycle DEC Rn Decrement register 1 byte 1 cycle DEC direct Decrement direct byte 2 byte 1 cycle DEC lem Decrement indirect SRAM INC DPTR 1 byte 1 cycle 1 byte 2 cycle MUL AB DA A Decimal adjust ACC Increment Data Pointer Multiply ACC and B DIV Divide ACC by B 1 byte 4 cycle 1 byte 4 cycle 1 byte 1 cycle Note 1 All mnemonics copyrighted lntel Corporation 1980 1572 33 264 uPSD34xx uPSD34xx INSTRUCTION SET SUMMARY Table 7 Logical Instruction Set Note 1 All mnemonics copyrighted lntel Corporation 1980 34 264 Logical Instructions ANL A Rn AND register to ACC 1 byte 1 cycle ANL A direct AND direct byte to ACC 2 byte 1 cycle ANL A data AND immediate data to ACC 2 byte 1 cycle ANL direct A AND ACC to direct byte 2 byte 1 cycle ANL direct data AND immediate data to direct byte 3 byte 2 cycle ORL A Rn OR register to ACC 1 byte 1 cycle ORL A direct OR direct byte to ACC 2 byte 1 cycle ORL A Ri OR indirect SRAM to ACC 1 byte 1 cycle ORL A data OR immediate data to ACC 2 byte 1 cycle ORL direct A OR ACC to direct byte 2 byte 1 cycl
193. byte 2 cycle MOV Q Ri data Move immediate data to indirect SRAM 2 byte 1 cycle MOV DPTR data16 Load Data Pointer with 16 bit constant 3 byte 2 cycle MOVC A A PC Move code byte relative to PC to ACC 1 byte 2 cycle MOVX A Ri Move XDATA 8 bit addr to ACC 1 byte 2 cycle MOVX Move XDATA 16 bit addr to ACC 1 byte 2 cycle MOVX Ri A Move ACC to XDATA 8 bit addr 1 byte 2 cycle MOVX DPTR A Move ACC to XDATA 16 bit addr 1 byte 2 cycle PUSH direct Push direct byte onto stack 2 byte 2 cycle POP direct Pop direct byte from stack 2 byte 2 cycle XCH A direct Exchange direct byte with ACC 2 byte 1 cycle XCH A Ri Exchange indirect SRAM with ACC 1 byte 1 cycle XCHD A Ri Exchange low order digit indirect SRAM with ACC 1 byte 1 cycle Note 1 All mnemonics copyrighted lntel Corporation 1980 35 264 uPSD34xx uPSD34xx INSTRUCTION SET SUMMARY Table 9 Boolean Variable Manipulation Instruction Set Note 1 All mnemonics copyrighted lntel Corporation 1980 36 264 CLR bit Clear direct bit 2 byte 1 cycle SETB C Set carry 1 byte 1 cycle CPL C Compliment carry 1 byte 1 cycle CPL i Compliment direct bit 2 byte 1 cycle ANL AND direct bit to carry 2 byte 2 cycle ANL C bit AND compliment of direct bit to carry 2 byte 2 cycle ORL C bit OR direct bit to carry 2 byte 2 cycle ORL C bit OR compliment of direct bit to carry 2 byte 2 cycle MOV Mov
194. byte to Memor Flash unlock unlock command address pp pag Memory Bypass Write AAh to Write 55h Write 20h poe 1 555 to XAAAh to 555 unlock unlock commana p e 18 4 E Program a Byte to Flash Write AOh to Write data ginta Memory XXXXh byte to Senienna p with command address 3 e18 4 P Bypassed 9 Unlock Reset Write 90h to Write 00h m pasee Bypass XXXXh to XXXXh Me tee Unlock command command sid 4 P Flash Bulk Write AAh to Write 55h Write 80h Write Write 55h Write 10h to Flash Bulk E 3 X555h to XAAAh sto X555h to X555h to XAAAh 555 Erase page unlock unlock unlock unlock command 184 Flash Write AAh to Write 55h Write 80h Write Write 55h Write 30h to Write 30810 Flash Sector Sector X555h to XAAAh toX555h X555h toXAAAh Sector end Erase page Erase unlock unlock command unlock unlock command command 185 Write BOh to address that Suspend activates Sector or CSBOOTx Erase Erase where erase eid 9 is progress command Write 30h to address that activates FSx Resume or CSBOOTx Ps Sector where nace Erase desired to 1 ur g resume erase command 3 179 264 uPSD34xx PSD MODULE Instr Bus Bus Bus Bus Sequence Cycle 1 Cycle 2 Cycle 5 Cycle 6 Write FOh to address that Reset activates FSx Reset Flash or CSBOOTx Flas
195. cations Modes 2 and 3 have a special provision for multiprocessor com munications In these modes 9 data bits are re ceived The 9th one goes into bit RB8 then comes a stop bit The port can be programmed such that when the stop bit is received the UART interrupt will be activated only if bit RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multi processor systems is as fol lows When the master processor wants to trans mit a block of data to one of several slaves it first sends out an address byte which identifies the tar get slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 ina data byte With SM2 1 no slave will be interrupt ed by a data byte An address byte however will interrupt all slaves so that each slave can exam ine the received byte and see if it is being ad dressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that were not being addressed leave their SM2 bits set and go on about their busi ness ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 SM2 can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive inter rupt will not be activated unless a valid stop bit is received Serial Port Control Registers The SFR SCONO controls UARTO and SCON1 controls UART1 shown in Table 47 and Table 4
196. ce These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im Table 150 Absolute Maximum Ratings uPSD34xx MAXIMUM RATING plied Exposure to Absolute Maximum Rating con ditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality docu ments Symbol Parameter TsrG Storage Temperature TiEAD Lead Temperature during Soldering 20 seconds 0 Vio Input and Output Voltage Q Von or Hi Z V Vcc Supply Voltage 0 5 6 5 V Vpp Device Programmer Supply Voltage 0 5 14 0 V Vesp Electrostatic Discharge Voltage Human Body Model 2000 2000 V Note 1 IPC JEDEC J STD 020A 2 JEDEC Std JESD22 A114A C1 100pF R1 1500 R2 500 DC AND AC PARAMETERS This section summarizes the operating and mea surement conditions and the DC and AC charac teristics of the device The parameters in the DC and AC Characteristic tables that follow are de rived from tests performed under the Measure Table 151 Operating Conditions 5V Devices ment Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame ters Symbol Parameter Min Max Unit Voc Supply Volta
197. com mand In this case the 8032 must start a new sec tor erase instruction sequence unlock and command beginning again after the current sec tor erase operation has completed Programming Flash Memory When a byte of Flash memory is programmed individual bits are programmed to logic 0 cannot program a bit in Flash memory to a logic 1 once it has been pro grammed to a logic 0 A bit must be erased to log 1 and programmed to logic 0 That means Table 108 Flash Memory Status Bit Definition uPSD34xx PSD MODULE Flash memory must be erased prior to being pro grammed A byte of Flash memory is erased to all 1s FFh The 8032 may erase the entire Flash memory array all at once or erase individual sec tor by sector but not erase byte by byte Howev er even though the Flash memories cannot be erased byte by byte the 8032 may program Flash memory byte by byte This means the 8032 does not need to program group of bytes 64 128 etc at one time like some Flash memories Each Flash memory requires the 8032 to send an instruction sequence to program a byte or to erase sectors see Table 107 page 179 If the byte to be programmed is in a protected Flash memory sector the instruction sequence is ignored IMPORTANT It is mandatory that a chip select signal is active for the Flash sector where a pro gramming instruction sequence is targeted The user must make sure that the correct chip select equat
198. component from the graph based on number of product terms and input frequency The only DC component in non Turbo mode is the PSD Module standby current The key to reducing PLD current consumption is to reduce the composite frequency of transitions on the PLD input bus moving down the frequency scale on the graphs One way to do this is to care fully select which signals are entering PLD inputs not selecting high frequency signals if they are not used in PLD equations Another way is to use PLD Blocking Bits to block certain signals from enter ing the PLD input bus 223 264 uPSD34xx PSD MODULE PLD Blocking Bits Blocking specific signals from entering the PLDs using bits of the csiop PMMR registers can further reduce PLD AC cur rent consumption by lowering the effective com posite frequency of inputs to the PLDs Blocking 8032 Bus Control Signals When the 8032 is active on the MCU Module four bus con trol signals RD WR PSEN and ALE are con stantly transitioning to manage 8032 bus traffic Each time one of these signals has a transition from logic 1 to 0 or O to 1 it will wake up the PLDs if operating in non Turbo mode or when in Turbo mode it will cause the affected PLD gates to draw current If equations in the DPLD or GPLD do not use the signals RD WR PSEN or ALE then these signals can be blocked which will reduce the AC current component substantially These bus control signals are rarely used in
199. condition forces SFRs P1 P3 and P4 to FFh thus all three ports are input ready after re set When a pin is used as an input the stronger pull up A maintains a solid logic 1 until an external device drives the input pin low At this time pull up A is automatically disabled and only pull up will source the external device uA consistent with standard 8051 architecture GPIO Bi Directional It is possible to operate indi vidual port pins in bi directional mode For an out put firmware would simply write the corresponding SFR bit to logic 1 or 0 as needed But before using the pin as an input firmware must first ensure that a logic 1 was the last value writ ten to the corresponding SFR bit prior to reading that SFR bit as an input 3 uPSD34xx I O PORTS of MCU MODULE GPIO Current Capability A GPIO pin on Port 4 can sink twice as much current than a pin on either Port 1 or Port 3 when the low side driver is output ting a logic 0 See the DC specifications at the end of this document for full details Reading Port Pin vs Reading Port Latch When firmware reads the GPIO ports sometimes the ac tual port pin is sampled in hardware and some times the port SFR latch is read and not the actual pin depending on the type of MCU instruction used These two data paths are shown in Figure 17 page 57 through Figure 19 page 58 SFR latches are read and not the pins only when the read is
200. ctive and resides between UART1 and the pins RxD1 and TxD1 as shown Figure 39 page 94 Baud Rate Selection The IrDA standard only supports 2 4 9 6 19 2 and 115 2kbps Table Table 52 page 96 informs the IrDA Interface of the baud rate of UARTZ2 so that it can perform pulse modulation properly It may not be necessary to implement the BR 3 0 bits in the IRDACON Register if the IrDA Interface obtains the proper timing from UART 2 Table 50 IRDACON Register Bit Definition SFR CEh Reset Value OFh PULSE RW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRDAEN PULSE CDIV4 CDIV3 CDIV2 CDIV1 CDIVO Details Bit Symbol R W Definition 7 Reserved IrDA Enable 6 IRDAEN RW 0 IrDA Interface is disabled 1 IrDA is enabled UART1 outputs are disconnected from Port 1 or Port 4 IrDA Pulse Modulation Select 0 1 627us 1 3 16 bit time pulses 4 0 CDIV 4 0 RW Specify Clock Divider see Table 53 page 97 Table 51 Baud Rate Selection Register SFR xxh reset value xxh Bit Symbol R W Definition 7 4 BR 3 0 R W Specify Baud Rate see Table 52 IrDA Pulse Modulation Select 3 2 PULSE R W 0 3 16 bit time pulses not recommended 1 1 627us 0 IrDA Interface is disabled 1 0 IRDAEN RW 1 IrDA is enabled UART 2 outputs are disconnected from Port 1 or Port 4 95 264 uPSD34xx IrDA INTERFACE Table 52 Baud Rate of UART 2 for IrDA Interface
201. ctly written to memory Flash memory must first be unlocked with a special instruction sequence of byte WRITE operations to invoke an internal algo rithm inside either Flash memory array then a sin gle data byte is written programmed to the Flash memory array then programming status is checked by a byte READ operation or by checking the Ready Busy pin PC3 Table 107 page 179 lists all of the special instruction sequences to pro gram a byte to either of the Flash memory arrays erase the arrays and check for different types of status from the arrays This unlocking sequence is typical for many Flash memories to prevent accidental WRITEs by errant code However it is possible to bypass this un locking sequence to save time while intentionally programming Flash memory IMPORTANT The 8032 may not read and exe cute code from the same Flash memory array for which it is directing an instruction sequence Or more simply stated the 8032 may not read code from the same Flash array that is writing or eras ing Instead the 8032 must execute code from an alternate memory like SRAM or a different Flash array while sending instruction sequences to a given Flash array Since the two Flash memory ar rays inside the PSD Module device are completely independent the 8032 may read code from one array while sending instructions to the other It is possible however to suspend a sector erase op eration in one particular Flash array in o
202. d flag bits in the SFR named SCONO for UARTO or SCON1 for UART1 to de termine the cause of the interrupt SPI Interrupt The SPI interrupt has four interrupt sources which are logically ORed together when interrupting the MCU The ISR must read the flag bits to determine the cause of the interrupt A flag bit is set for end of data transmit TEISF data receive overrun RORISF transmit buffer empty TISF or receive buffer full RISF 44 264 Interrupt The flag bit INTR is set by a variety of conditions occurring on the interface re ceived own slave address ADDR flag received general call address GC flag received STOP condition STOP flag or successful transmission or reception of a data byte The ISR must read the flag bits to determine the cause of the interrupt ADC Interrupt The flag bit AINTF is set when an A to D conversion has completed PCA Interrupt The PCA has eight interrupt sources which are logically ORed together when interrupting the MCU The ISR must read the flag bits to determine the cause of the interrupt Each of the six TCMs can generate a match or capture interrupt on flag bits OFV5 0 respectively Each of the two 16 bit counters can generate an overflow interrupt on flag bits INTF1 and INTFO respectively Tables 17 through Table 20 page 46 have de tailed bit definitions of the interrupt system SFRs USB Interrupt The USB interrupt has multiple sources The I
203. d for any other I O function There are two optional pins on Port C TSTAT and TERR that can be used to re duce programming time during ISP See JTAG ISP and JTAG Debug page 226 Other Port Capabilities It is possible to change the type of output drive on the ports at run time It is also possible to read the state of the output en able signal of the output driver at run time The fol lowing sections provide the details Port Pin Drive Options The csiop Drive Select registers allow reconfiguration of the output drive type for certain pins on Ports A B C and D The 8032 can change the default drive type setting at run time The is no action needed in PSDsoft Ex press to change or define these pin output drive types Figure 80 page 200 shows the csiop Drive Select register output controlling the pin output driver The default setting for drive type for all pins on Ports A B C and D is a standard CMOS push pull output driver Note When a pin on Port A B C D is not used as an output and has no external device driving it as an input floating pin excess power consumption can be avoided by placing a weak pull up resistor 100KO to Vpp which keeps the CMOS input pin from floating Drive Select Registers The csiop Drive Select Registers will configure a pin output driver as Open Drain or CMOS push pull for some port pins and controls the slew rate for other port pins An external pull up resistor should be used for pins
204. dback to the 8032 and allows only one source at a time to be read when the 8032 reads various csiop regis ters There is one PDB for each port pin enabling the 8032 to read the following on a pin by pin ba sis 1 MCU signal direction setting csiop Direction reg 2 Pin drive type setting csiop Drive Select reg 3 Latched Addr Out mode setting csiop Control reg 4 MCU I O pin output setting csiop Data Out reg 5 Output Enable of pin driver csiop Enable Out reg 6 MCU I O pin input csiop Data In reg uPSD34xx PSD MODULE A port pin s output enable signal is controlled by a two input OR gate whose inputs come from a product term of the AND OR array the output of the csiop Direction Register If an output enable from the AND OR Array is not defined and the port pin is not defined as an OMC output and if Peripheral I O mode is not used then the csiop Di rection Register has sole control of the OE signal As shown in Figure 80 page 200 a physical port pin is connected to the Port logic and is also separately routed to an IMC allowing the 8032 to read a port pin by two different methods MCU I O input mode or read the IMC Port Operating Modes Port logic has sever al modes of operation Table 115 page 197 sum marizes which modes are available on each port Each of the port operating modes are described in following sections Some operating modes can be defined using PSDsoft Exp
205. de these initial settings during runtime for In Applica tion Programming IAP Standard 8032 MCU architecture cannot write to its own program memory space to prevent acci dental corruption of firmware However this be comes an obstacle in typical 8032 systems when a remote update to firmware in Flash memory is required using IAP The PSD module provides a solution for remote updates by allowing 8032 firm ware to temporarily reclassify Flash memory to reside in data space during a remote update then returning Flash memory back to program space when finished See the VM Register Table 104 page 174 in the PSD Module section of this document for more details 8032 MCU CORE PERFORMANCE ENHANCEMENTS Before describing performance features of the uPSD34xx let us first look at standard 8032 archi tecture The clock source for the 8032 MCU cre ates a basic unit of timing called a machine cycle which is a period of 12 clocks for standard 8032 MCUs The instruction set for traditional 8032 MCUS consists of 1 2 and 3 byte instructions that execute in different combinations of 1 2 or 4 ma chine cycles For example there are one byte in structions that execute in one machine cycle 12 clocks one byte instructions that execute in four machine cycles 48 clocks two byte two cycle instructions 24 clocks and so on In addition standard 8032 architecture will fetch two bytes from program memory on almost every machine cycle
206. dule Code Fetch cycle using the PSEN signal fetch a 16 bit code word for filling the pre fetch queue The CPU fetches a code byte from the PFQ for execution Code Read cycle using PSEN read a 16 bit code word using the MOVC Move Constant instruction The code word is routed directly to the CPU and by pass the PFQ XDATA Read cycle using the RD signal read a data byte using the MOVX Move eXternal instruction and XDATA Write cycle using the WR signal write a data byte using the MOVX instruction PSEN Bus Cycles In a PSEN bus cycle the MCU module fetches the instruction from the 16 bit program memory in the PSD module The multiplexed address data bus AD 15 0 is connected to the PSD module for 16 bit data transfer The uPSD34xx does not support external PSEN cycles and cannot fetch instruction from other external program memory devices READ or WRITE Bus Cycles In an XDATA READ or WRITE bus cycle the MCU s multiplexed AD 15 0 bus is connected to the PSD module but only the lower bytes AD 7 0 are used for the 8 bit data transfer The AD 7 0 lines are also connected to pins in the 80 pin pack uPSD34xx MCU BUS INTERFACE age for accessing external devices If the high ad dress byte A 15 8 is needed for external devices Port B in the PSD Module can be configured to provide the latched A 15 8 address outputs Connecting External Devices to the MCU Bus The uPSD34xx supports 8 bit only extern
207. e 13 264 uPSD34xx HARDWARE DESCRIPTION HARDWARE DESCRIPTION The uPSD34xx has a modular architecture built from a stacked die process There are two die one is designated MCU Module in this document and the other is designated PSD Module see Figure 5 page 15 In all cases the MCU Module die op erates at 3 3V with 5V tolerant I O The PSD Mod ule is either a 3 3V die or a 5V die depending on the uPSD34xx device as described below The MCU Module consists of a fast 8032 core that operates with 4 clocks per instruction cycle and has many peripheral and system supervisor func tions The PSD Module provides the 8032 with multiple memories two Flash and one SRAM for program and data programmable logic for ad dress decoding and for general purpose logic and additional I O The MCU Module communicates with the PSD Module through internal address and data busses ADO AD15 and control signals RD WR PSEN ALE RESET There are slightly different I O characteristics for each module I Os for the MCU module are desig nated as Ports 1 and 4 I Os for the PSD Mod ule are designated as Ports A B C and D For all 5V uPSD34xx devices a 3 3V MCU Module is stacked with a 5V PSD Module In this case a 5V uPSD34xx device must be supplied with 3 3Vcc for the MCU Module and 5 0Vpp for the PSD Module Ports 3 and 4 of the MCU Module are 3 3V ports with tolerance to 5V devices they can be directly drive
208. e ORL direct data OR immediate data to direct byte 3 byte 2 cycle SWAP A Swap nibbles within the ACC 1 byte 1 cycle XRL A Rn Exclusive OR register to ACC 1 byte 1 cycle XRL A direct Exclusive OR direct byte to ACC 2 byte 1 cycle XRL A data Exclusive OR immediate data to ACC 2 byte 1 cycle XRL direct A Exclusive OR ACC to direct byte 2 byte 1 cycle CLR A Clear ACC 1 byte 1 cycle CPL A Compliment ACC 1 byte 1 cycle RLC A Rotate ACC left through the carry 1 byte 1 cycle HR A Rotate ACC right 1 byte 1 cycle RRC A Rotate ACC right through the carry 1 byte 1 cycle uPSD34xx uPSD34xx INSTRUCTION SET SUMMARY Table 8 Data Transfer Instruction Set MOV Move register to ACC 1 byte 1 cycle MOV A direct Move direct byte to ACC 2 byte 1 cycle MOV A Ri Move indirect SRAM to ACC 1 byte 1 cycle MOV Move immediate data to ACC 2 byte 1 cycle MOV Rn Move ACC to register 1 byte 1 cycle MOV Rn direct Move direct byte to register 2 byte 2 cycle MOV Rn data Move immediate data to register 2 byte 1 cycle MOV direct A Move ACC to direct byte 2 byte 1 cycle MOV direct Rn Move register to direct byte 2 byte 2 cycle MOV direct direct Move direct byte to direct 3 byte 2 cycle MOV direct Ri Move indirect SRAM to direct byte 2 byte 2 cycle MOV direct data Move immediate data to direct byte 3 byte 2 cycle MOV QRi A Move ACC to indirect SRAM 1 byte 1 cycle MOV Q Ri direct Move direct byte to indirect SRAM 2
209. e logic element consisting of a flip flop and some AND OR logic Figure 77 page 193 The gener al structure of the GPLD with OMCs is similar in nature to a 22V10 PLD device with the familiar sum of products AND OR construct True and compliment versions of 69 input signals are avail able to the inputs of a large AND OR array AND OR array outputs feed into an OR gate within each OMC creating up to 10 product terms for each OMC Logic output of the OR gate can be passed on as combinatorial logic or combined with a flip flop within in each OMC to realize sequential logic OMC outputs can be used as a buried nodes driv ing internal feedback to the AND OR array or OMC outputs can be routed to external pins on Ports A B or C through the OMC Allocator uPSD34xx PSD MODULE OMC Allocator The OMC allocator Figure 78 page 194 will route eight of the OMCs from MCELLAB to pins on either Port A or Port B and will route eight of the OMCs from MCELLBC to pins on either Port B or Port C based on what is specified in PSDsoft Express IMCs Inputs from pins on Ports A B and C are routed to IMCs for conditioning clocking or latch ing as they enter the chip which is good for sam pling and debouncing inputs Alternatively IMCs can pass port input signals directly to PLD inputs without clocking or latching Figure 79 page 198 The 8032 may read the IMCs asynchronously at any time through IMC registers in csiop Note Th
210. e 2 Mode 2 provides asynchronous full du plex communication using a total of 11 bits per data byte Data is transmitted through TxD and re ceived through RxD with a Start Bit logic 07 eight data bits LSB first a programmable 9th data bit and a Stop Bit logic 1 Upon Transmit the 9th data bit from bit TB8 in SCON can be as signed the value of 0 or 1 Or for example the Parity Bit P in the PSW could be moved into TB8 Upon receive the 9th data bit goes into RB8 in SCON while the Stop Bit is ignored The baud rate is programmable to either 1 32 or 1 64 of fosc Mode 3 Mode 3 is the same as Mode 2 in all re spects except the baud rate is variable like it is in Mode 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination regis ter Reception is initiated in Mode 0 by the condi tion RI 0 and REN 1 Reception is initiated in the other modes by the incoming Start Bit if REN 1 Bits of SFR Dat Mode Synchronization SCON Baud Clock Start Stop Bits See Figure SMO SM1 0 Synchronous 0 0 fosc 12 8 None 31 jene 88 1 Asynchronous 0 1 Timer 1 or Timer 2 Overflow 8 1 Start 1 Stop 33 page 90 Figure 2 Asynchronous fosc 32 or fosc 64 1 Start 1 Stop 35 92 Figure 3 Asynchronous Timer 1 or Timer 2 Overflow 1 Start 1 Stop 37 page 93 83 264 uPSD34xx SERIAL UART INTERFACES Multiprocessor Communi
211. e JTAG signals TDO TDI TCK and TMS on Port C do not route through IMCs but go direct ly to JTAG logic Ports For 80 pin uPSD34xx devices the PSD Module has 22 individually configurable pins distributed over four ports these I O are in addition to on MCU Module For 52 pin uPSD34xx devices the PSD Module has 13 indi vidually configurable pins distributed over three ports See Figure 85 page 212 for I O port pin availability on these two packages port pins on the PSD Module Ports A C and D are completely separate from the port pins on the MCU Module Ports 1 3 and 4 They even have different electrical characteristics port pins on the PSD Module are accessed by csiop registers or they are controlled by PLD equations Conversely I O Port pins on the MCU Module controlled by the 8032 SFR registers Table 102 General I O pins on PSD Module rona Pons ponc rono ur Note Four pins on Port C are dedicated to JTAG leaving four pins for general 167 264 uPSD34xx PSD MODULE Each I O pin on the PSD Module can be individu ally configured for different functions on a pin by pin basis Figure 80 page 200 Following are the available functions on PSD Module pins MCU I O 8032 controls the output state of each port pin or it reads input state of each port pin by accessing csiop registers at run time The direction in or out of each pin
212. e direct bit to carry 2 byte 1 cycle MOV Move carry to direct bit 2 byte 2 cycle JC Jump if carry is set 2 byte 2 cycle JNC rel Jump if carry is not set 2 byte 2 cycle JB rel Jump if direct bit is set 3 byte 2 cycle JNB rel Jump if direct bit is not set 3 byte 2 cycle uPSD34xx uPSD34xx INSTRUCTION SET SUMMARY Table 10 Program Branching Instruction Set Program Branching Instructions ACALL addr11 Absolute subroutine call 2 byte 2 cycle LCALL addr16 Long subroutine call 3 byte 2 cycle RETI Return from interrupt 1 byte 2 cycle AJMP addr1 1 Absolute jump 2 byte 2 cycle LJMP addr16 Long jump 3 byte 2 cycle SJMP rel Short jump relative addr 2 byte 2 cycle JMP A DPTR Jump indirect relative to the DPTR 1 byte 2 cycle JZ rel Jump if ACC is zero 2 byte 2 cycle JNZ rel Jump if ACC is not zero 2 byte 2 cycle CJNE A direct rel Compare direct byte to ACC jump if not equal 3 byte 2 cycle CJNE A data rel Compare immediate to ACC jump if not equal 3 byte 2 cycle CJNE Rn data rel Compare immediate to register jump if not equal 3 byte 2 cycle CJNE data rel Compare immediate to indirect jump if not equal 3 byte 2 cycle DJNZ Rn rel Decrement register and jump if not zero 2 byte 2 cycle DJNZ direct rel 3 byte 2 cycle Note 1 All mnemonics copyrighted lntel Corporation 1980 Table 11 Miscellaneous Instruction Set Mnemonic and Use Description Length Cycles Miscellaneous
213. e operation to SBUF the TB8 Bit is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmis sion actually starts at the end of the MCU the ma chine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchro nized to the divide by 16 counter not to the writing of SBUF Transmission begins with activation of SEND which puts the start bit at pin TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to pin TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register There after only zeros are clocked in Thus as data bits shift out to the right zeros are clocked in from the left When bit TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all po sitions to the left of that contain zeros This condi tion flags the TX Control unit to do one last shift and then deactivate SEND and set the interrupt uPSD34xx SERIAL UART INTERFACES flag This occurs at the 11th divide by 16 roll over after writing to SBUF Reception is initiated by a detected 1 to 0 transi tion at pin RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the di vide by 16 counter i
214. e uses six WRITE operations fol lowed by a READ operation of the status register as described in Table 107 page 179 If any byte of the Bulk Erase instruction sequence is wrong the Bulk Erase instruction sequence aborts and the device is reset to the Read Array mode The address provided by the 8032 during the Flash Bulk Erase command sequence may select any one of the eight Flash memory sector select sig nals FSx or one of the four signals CSBOOTx An erase of the entire Flash memory array will occur in a particular array even though a command was sent to just one of the individual Flash memory sectors within that array During a Bulk Erase the memory status may be checked by reading the Error Flag Bit DQ5 the Toggle Flag Bit DQ6 and the Data Polling Flag Bit DQ7 The Error Flag Bit DQ5 returns 1 if there has been an erase failure Details of acquir ing the status of the Bulk Erase operation are de tailed in the section entitled Programming Flash Memory page 181 During a Bulk Erase operation the Flash memory does not accept any other Flash instruction se quences Flash Sector Erase The Sector Erase instruc tion sequence uses six WRITE operations as de scribed in Table 107 page 179 Additional Flash Sector Erase commands to other sectors within the same Flash array may be issued by the 8032 if the additional commands are sent within a limit ed amount of time The Erase Time out Flag Bit DQ3 ref
215. eceived data packet 3 R 0 Data0 and 1 Data1 SETUP Token Detect Bit 2 SETUP R W This bit is set when EndpointO receives a SETUP token This bit is not cleared when EndpointO receives an IN or OUT token following the SETUP token that set this bit This bit is cleared by software or a reset IN Token Detect Bit 1 IN R This bit is set when EndpointO receives an IN token This bit is cleared when EndpointO receives a SETUP or OUT token OUT Token Detect Bit 0 OUT R This bit is set when EndpointO receives an OUT token This bit is cleared when EndpointO receives a SETUP or IN token 3 144 264 USB Endpoint Select Register USEL Endpoints share the same XDATA space for FIFOs as well as the same SFR addresses for Control and FIFO Valid Size registers The USB Endpoint Select Register see Table 82 is used to select the desired direction and uPSD34xx USB INTERFACE endpoint that is accessed when reading or writing to the FIFO XDATA address space This register is also used to select the direction and Endpoint when accessing the USB Endpoint Control Register Table 82 USB Endpoint Select Register USEL OEFh Reset Value 00h Bit 7 Bit 6 Bit 5 DIR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EP 2 EP 1 EP 0 Details Bit Symbol DIR R W R W FIFO s Direction Select Bit 0 IN FIFO select 1 OUT FIFO select Definition Reserved Reserved
216. ect jumps table look up operations and for ex ternal data transfers XDATA When not used for 22 264 MCU Bus Interface Supervisory Functions Standard 8032 Timer Counters Serial UART Interfaces IrDA Interface Interface SPI Interface Analog to Digital Converter Programmable Counter Array PCA USB Interface Note A full description of the 8032 instruction set may be found in the uPSD34xx Programmers Guide addressing the DPTR Register can be used as a general purpose 16 bit data register Very frequently the DPTR Register is used to ac cess XDATA using the External Direct addressing mode The uPSD34xx has a special set of SFR registers DPTC DPTM to control a secondary DPTR Register to speed memory to memory XDATA transfers Having dual DPTR Registers al lows rapid switching between source and destina tion addresses see details in DUAL DATA POINTERS page 38 Program Counter PC The PC is a 16 bit register consisting of two 8 bit registers PCL and PCH This counter indicates the address of the next instruction in program memory to be fetched and executed A reset forc es the PC to location 0000h which is where the re set jump vector is stored Accumulator ACC This is an 8 bit general purpose register which holds a source operand and receives the result of arithmetic operations The ACC Register can also be the source or destination of logic and data movement operations For MUL and DIV instr
217. ed algorithm within the Flash memory array begins The 8032 then reads the lo cation of the byte to be programmed in Flash memory to check status The Data Polling Flag Bit DQ7 of this location becomes the compliment of Bit D7 of the original data byte to be programmed The 8032 continues to poll this location compar ing the Data Polling Flag Bit DQ7 and monitoring the Error Flag Bit DQ5 When the Data Polling Flag Bit DQ7 matches Bit D7 of the original data then the embedded algorithm is complete If the Error Flag Bit DQ5 is 1 the 8032 should test the Data Polling Flag Bit DQ7 again since the Data Polling Flag Bit DQ7 may have changed simulta neously with the Error Flag Bit DQ5 see Figure 72 The Error Flag Bit DQ5 is set if either an internal time out occurred while the embedded algorithm attempted to program the byte indicating a bad Flash cell or if the 8032 attempted to program bit to logic 1 when that bit was already programmed to logic 0 must erase to achieve logic 1 It is suggested as with all Flash memories to read the location again after the embedded program ming algorithm has completed to compare the byte that was written to the Flash memory with the byte that was intended to be written When using the Data Polling method during an erase operation Figure 72 still applies However the Data Polling Flag Bit DQ7 is 0 until the erase operation is complete 1 on the Error
218. ed within the time out period must be addressed to other de sired segments within the same Flash memory ar ray Suspend Sector Erase When a Sector Erase operation is in progress the Suspend Sector Erase instruction sequence can be used to sus pend the operation by writing BOh to any valid ad dress within the Flash array that currently is undergoing an erase operation This allows read ing of data from a different Flash memory sector within the same array after the Erase operation has been suspended Suspend Sector Erase is accepted only during an Erase operation uPSD34xx PSD MODULE There is up to 15 delay after the Suspend Sector Erase command is accepted and the array goes to Read Array mode The 8032 will monitor the Tog gle Flag Bit DQ6 to determine when the erase operation has halted and Read Array mode is ac tive If a Suspend Sector Erase instruction sequence was executed the following rules apply Attempting to read from a Flash memory sector that was being erased outputs invalid data Reading from a Flash memory sector that was not being erased is valid The Flash memory cannot be programmed and only responds to Resume Sector Erase and Reset Flash instruction sequences Ifa Reset Flash instruction sequence is received data in the Flash memory sector that was being erased is invalid Resume Sector Erase If a Suspend Sector Erase instruction sequence was previously exe cuted
219. either Flash memory array is being erased The output is a 1 Ready when no program or erase operation is in progress To activate this function on this pin the user must select the Ready Busy selection in PSDsoft Express when configuring pin PC3 This pin may be polled by the 8032 or used as a 8032 interrupt to indicate when an erase or program operation is complete requires routing the signal on PC board from PC3 back into a pin on the MCU Module This signal is also available internally on the PSD Module as an input to both PLDs without routing a signal externally on PC board and its signal name is bsy The Ready Busy output can be probed during lab develop ment to check the timing of Flash memory pro gramming in the system at run time Bypassed Unlock Sequence The Bypass Un lock mode allows the 8032 to program bytes in the Flash memories faster than using the standard Flash program instruction sequences because the typical AAh 55h unlock bus cycles are bypassed for each byte that is programmed Bypassing the unlock sequence is typically used when the 8032 is intentionally programming a large number of bytes such as during IAP After intentional pro gramming is complete typically the Bypass mode would be disabled and full protection is back in place to prevent unwanted WRITEs to Flash mem ory The Bypass Unlock mode is entered by first initiat ing two Unlock bus cycles This is followed by a third WRITE
220. errupt 0 Disable Interrupt Table 18 IEA Interrupt Enable Addition Register SFR A7h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EADC ESPI EPCA ES1 EIC EUSB Details Bit Symbol R W Function 74 EADC RW Enable ADC Interrupt 60 ESPI RW Enable SPI Interrupt 5 EPCA RW Enable Programmable Counter Array Interrupt 40 ES1 RW Enable UART1 Interrupt 3 Reserved do not set to logic 1 2 Reserved do not set to logic 1 10 EIC RW Enable I C Interrupt 0 EUSB RW Enable USB Interrupt Note 1 1 Enable Interrupt 0 Disable Interrupt 45 264 uPSD34xx INTERRUPT SYSTEM Table 19 IP Interrupt Priority Register SFR B8h reset value 00h Note 1 1 Assigns high priority level 0 Assigns low priority level Table 20 IPA Interrupt Priority Addition register SFR B7h reset value 00h PT2 PSO PT1 PX1 PTO PXO Details Bit Symbol R W Function 7 Reserved 6 Reserved 5 1 PT2 R W Timer 2 Interrupt priority level 40 PSO RW UARTO Interrupt priority level 301 PT1 RW Timer 1 Interrupt priority level 20 PX1 RW External Interrupt INT1 priority level 10 PTO RW Timer 0 Interrupt priority level 00 RW External Interrupt INTO priority level Note 1 1 Assigns high priority level 0 Assigns low priority level 46 264 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PADC PSPI PPCA P
221. es are longer than RD read cycles is when the PFQ issues a stall while reloading PFQ stalls do not affect RD read cycles By comparison in many traditional 8051 architectures RD bus cycles are always longer than PSEN bus cycles Table 37 BUSCON Bus Control Register SFR 9Dh reset value EBh Bit 7 EPFQ Bit 6 EBC Bit 5 WRW 1 0 RDW 1 0 CW 1 0 Details Bit Symbol EPFQ EBC R W R W R W Definition Enable Pre Fetch Queue 0 PFQ is disabled 1 PFQ is enabled default Enable Branch Cache 0 BC is disabled 1 is enabled default 5 4 3 2 1 0 WRWT 1 0 RDW 1 0 CW 1 0 RW RW RW WR Wait number of MCU_CLK periods for WR write bus cycle during any instruction 00b 4 clock periods 01b 5 clock periods 10b 6 clock periods default 11b 7 clock periods RD Wait number of MCU CLK periods for RD read bus cycle during any MOVX instruction 00b 4 clock periods 01b 5 clock periods 10b 6 clock periods default 11b 7 clock periods Code Wait number of MCU_CLK periods for PSEN read bus cycle during any code byte fetch or during any MOVC code byte read instruction Periods will increase with PFQ stall 00b 3 clock periods exception for MOVC instructions this setting results 4 clock periods 01b 4 clock periods 10b 5 clock periods 11b 6 clock periods default 65 264 uPSD34xx MCU BUS INTERFACE Table 38 Number of M
222. f data are shifted out on one pin while a different 8 bits of data are simultaneously shifted in on a second pin Another way to view this transfer is that an 8 bit shift register in the Master and another 8 bit shift register in the Slave are connected as a circular 16 bit shift register When a transfer occurs this distributed shift register is shifted 8 bit positions thus the data in the Master and Slave devices are effectively exchanged see Figure 45 Bus Level Activity Figure 46 details an SPI receive operation with respect to bus Master and Figure 47 details an SPI transmit operation Also shown are internal flags available to firmware to manage data flow These flags are accessed through a number of SFRs Note uPSD34xx SPI interface SFRs allow the choice of transmitting the most significant bit MSB of a byte first or the least significant bit LSB first The same bit order applies to data re ception Figures 46 and 47 illustrate shifting the LSB first Master Device SPIRxD 8 Bit Shift Register SPITxD SPICLK Baud Rate Generator SPI Bus 8 Bit Shift Register Slave Device MISO 4 110485 116 264 3 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE Figure 46 SPI Receive Operation Example H4 1 frame _ gt SPICLK SPO 0 SPICLK SPO 1 SPIRXD RORIS pM BUSY SPIINTR SPIRDR Full
223. fa e Cnt e dete 22 Accumulator ACC 2 2 oe ners 22 B Register B 5 ellus cen Nee cu RR tier REN etx IAN MEM eei ejes 22 General Purpose Registers 7 23 Program Status Word PSW 23 SPECIAL FUNCTION REGISTERS 5 24 8032 ADDRESSING MODES ik llmgzx EI e ETE eects Joie 31 Register Addressing eeu eee ww t ame ATE ERR NHAU 31 Direct Addressing xen n m n eie m 31 Register Indirect 0 31 Immediate Addressing 31 External Direct Addressing 31 External Indirect 0 31 Indexed Addressing 32 Relative Addressing 2c ce eee ed ru ee eee ele eae 32 Absolute Addressing 32 Long Addr ssirig 5 eR Slee Ne 32 BitAddressing Rex ee ee RE ERA ME 32 3 264 uPSD34xx TABLE OF
224. following Power up Subsequent Reset RST pulses do not clear the registers 1 Blocking bits should be set to logic 1 only if the signal is not needed in a DPLD or GPLD logic equation Table 146 Power Management Mode Register PMMR3 address csiop offset C7h Bit 0 X 0 Not used and should be set to zero Bit 1 FORCE PD 0 off APD counter will cause Power Down Mode if APD is enabled 1 Power Down mode will be entered immediately regardless of APD activity Bit 3 7 X 0 Not used and should be set to zero Note The bits of this register are cleared to zero following Power up Subsequent Reset RST pulses do not clear the registers 219 264 uPSD34xx PSD MODULE Automatic Power Down APD The APD unit shown in Figure 74 page 188 puts the PSD Mod ule into power down mode by monitoring the activ ity of the 8032 Address Latch Enable ALE signal If the APD unit is enabled by writing a logic 1 to Bit 1 of the csiop PMMRO register and if ALE sig nal activity has stopped 8032 in sleep mode then the four bit APD counter starts counting up If the ALE signal remains inactive for 15 clock peri ods of the CLKIN signal pin PD1 then the APD counter will reach maximum count and the power down indicator signal PDN goes to logic 1 forc ing the PSD Module into power down mode Dur ing this time all buffers on the PSD Module for 8032 address and data signals are disabled in sil
225. fs7 16KB 16KB 16KB 16KB C000h 150 152 154 156 16 16KB 16KB 16KB System I O 8000h 8 600 8KB 4000h System 2100h csiop 256B 2000h 50 8KB 0000h Al09174 8000h Nothing Mapped 4000h csboot1 8KB 2000h Common Memory to All Pages csboot0 8KB 0000h Common Memory to All Pages Figure 67 Mapping All Flash in Code Space 8032 PROGRAM 8032 XDATA SPACE SPACE PSEN RD and WR Page Page Page Page FFFFh 0 1 2 3 Page FFFFh fs1 fs3 fs5 fs7 16KB 16KB 16KB 16KB 150 152 154 156 16KB 16KB 16KB 16KB 8000h csboot3 8KB 6000h Common Memory to All Pages csboot2 8KB 4000h Common Memory to All Pages csboot1 8KB 2000h Common Memory to All Pages csboot0 8KB 0000h Common Memory to All Pages Coo0h System 2100h 256B 2000h 50 8KB 0000h Al09175 171 264 uPSD34xx PSD MODULE Figure 68 Place the larger Main Flash Memory into XDATA space and the smaller Secondary Flash into program space for systems that need a large amount of Flash for data recording or large look up tables and not so much Flash for 8032 firmware Figure 68 Mapping Small Code Big Data 8032 PROGRAM 8032 XDATA SPACE SPACE PSEN RD and WR Page Page Page Page 3 1 2 FFFFh Nothing Mapped fs1 fs3 fs5 fs7 16KB 16KB 16KB 16KB Cco00h 150 152 154 156 16 16 16
226. g at 0x0000 without interference because the 8032 core does not assert the RD or WR signals when accessing internal SRAM External Memory on PSD Module External memories may be placed at virtually any address using software tool PSDsoft Express The SRAM and Flash memories may be placed in 8032 Program Space or Data Space using PSDsoft Express Any memory in 8032 Data Space is XDATA Secondary Flash SRAM 1104106 Internal Memory MCU Module Standard 8032 Memory DATA IDATA SFR DATA Memory The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called DATA which can be accessed using 8032 direct or indirect addressing schemes and are typically used to store variables and stack Four register banks each with 8 registers RO R7 occupy addresses 0x0000 to 0x001F Only one of these four banks may be enabled at a time The next 16 locations at 0 0020 to OxOO2F contain 128 directly addressable bit locations that can be used as software flags SRAM locations 0x0030 and above may be used for variables and stack IDATA Memory The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to OxOOFF IDATA can be accessed only through 8032 indirect addressing and is typically used to hold the MCU stack as well as data vari ables The stack can reside in both DATA and IDATA memories and reach a size limited only by the available space in the combined 256 bytes
227. ge 4 5 5 5 V Ambient Operating Temperature industrial 40 85 C A Ambient Operating Temperature commercial 0 70 C Table 152 Operating Conditions 3 3V Devices Symbol Parameter Min Max Unit Vcc Supply Voltage 3 0 3 6 V Ambient Operating Temperature industrial Ambient Operating Temperature commercial 235 264 uPSD34xx DC AND AC PARAMETERS Table 153 AC Signal Letters for Timing Table 154 AC Signal Behavior Symbols for A Address Timing Clock Tine L Logic Level ALE D Input Data ogic Level Low or H Logic Level High Instruction L ALE V Valid X NoL Valid Logic Level N RESET Input or Output a Z Float P PSEN signal PW Pulse Width Q Output Data ulse wig Note Example tav_x Time from Address Valid to ALE Invalid R RD signal WR signal B Vstpy Output M Output Macrocell Note Example tavi x Time from Address Valid to ALE Invalid Figure 98 Switching Waveforms Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM WILL BE CHANGING HI TO LO FROMHI TO LO MAY CHANGE FROM WILL BE CHANGING LO TO HI LO TO HI X X X X X X DON T CARE CHANGING STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI STATE 103102 236 264 Table 155 Major Parameters Parameter uPSD34xx DC AND AC PARAMETERS Test Conditions Comments 5 0V Value 3 3V Value Operating Voltage 4 5 to 5
228. h page 1 in desired 85 array command Note 1 All values are in hexadecimal X Don t care 2 8032 addresses A12 through A15 are Don t care during the instruction sequence decoding Only address bits AO A11 are used during decoding of Flash memory instruction sequences The individual sector select signal FSO FS7 or CSBOOT0 CSBOOT3 which is active during the instruction sequence determines the complete address within that array Reading Flash Memory Under typical condi tions the 8032 may read the Flash memory using READ operations READ bus cycles just as it would a ROM or RAM device Alternately the 8032 may use READ operations to obtain status information about a Program or Erase operation that is currently in progress The following sections describe the kinds of READ operations Read Memory Contents Flash memory is placed in the Read Array mode after Power up af ter a PSD Module reset event or after receiving a Reset Flash memory instruction sequence from the 8032 The 8032 can read Flash memory con tents using standard READ bus cycles anytime the Flash array is in Read Array mode Flash memo ries will always be in Read Array mode when the array is not actively engaged in a program or erase operation Reading the Erase Program Status Bits The Flash arrays provide several status bits to be used by the 8032 to confirm the completion of an erase or program operation on Flash memory
229. he SFR WDRST cvc is the average duration of one MCU machine cycle By default an MCU machine cycle is always 4 MCU_CLK periods for uPSD34xx but the following factors can sometimes add more MCU_CLK periods per machine cycle The number of MCU CLK periods assigned to MCU memory bus cycles as determined in the SFR BUSCON If this setting is greater than 4 then machine cycles have additional MCU CLK periods during memory transfers Whether or not the PFQ BC circuitry issues a stall during a particular MCU machine cycle A stall adds more MCU CLK periods to a machine cycle until the stall is removed tMACH is also affected by the absolute time of a single MCU_CLK period This number is fixed by the following factors Frequency of the external crystal resonator or oscillator fosc Bit settings in the SFR CCONO which can divide fosc and change MCU CLK As an example assume the following 1 fosc is 40 2 thus its period is 25ns 2 1 10h meaning no clock division so the period of MCU CLK is also 25ns 3 BUSCON is C1h meaning the PFQ and BC are enabled and each MCU memory bus cycle is 4 MCU_CLK periods adding no additional periods to MCU machine cycles during memory transfers uPSD34xx SUPERVISORY FUNCTIONS 4 Assume there are no stalls from the PFQ BC In reality there are occational stalls but their occurance has minimal impact on WDT timeou
230. hile RST is asserted the PSD Module immediately loads its configuration from non volatile bits to configure the PLDs and other items PLD logic is operational and ready for use well before RST is de asserted The state of PLD outputs are determined by equations speci fied in PSDsoft Express The Flash memories are reset to Read Array mode after any assertion of RST even if a pro gram or erase operation is occurring Flash memory WRITE operations are automatical ly prevented while Vpp is ramping up until it rises above the Vi voltage threshold at which time Flash memory WRITE operations are allowed Once the uPSD34xx is up and running any subse quent reset operation is referred to as a warm re set until power is turned off again Some PSD Module functions are reset in different ways de pending if the reset condition was caused from a power up reset or a warm reset Table 148 page 225 summarizes how PSD Module functions are affected by power up and warm re sets as well as the affect of PSD Module power down mode from APD The I O pins of PSD Module Ports A B C and D do not have weak internal pull ups In MCU I O mode Latched Address Out mode and Peripheral I O mode the pins of Ports A B C and D become standard CMOS inputs during a re set condition If no external devices are driving these pins during reset then these inputs may float and draw excessive current If low power con sumption is critic
231. ied interrupt will not be serviced This means that active interrupts are not remembered Every poling cycle is new Assuming all of the listed conditions are satisfied the MCU executes the hardware generated LCALL to the appropriate ISR This LCALL pushes the contents of the PC onto the stack but it does not save the PSW and loads the PC with the ap propriate interrupt vector address Program exe cution then jumps to the ISR at the vector address Execution precedes in the ISR It may be neces sary for the ISR firmware to clear the pending in terrupt flag for some interrupt sources because not all interrupt flags are automatically cleared by hardware when the ISR is called as shown in Ta ble 16 page 42 If an interrupt flag is not cleared after servicing the interrupt an unwanted interrupt will occur upon exiting the ISR After the interrupt is serviced the last instruction executed by the ISR is RETI The RETI informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes from the stack and loads them into the PC Execution of the inter rupted program continues where it left off Note An ISR must end with a RETI instruction not a RET An RET will not inform the interrupt control system that the ISR is complete leaving the MCU to think the ISR is still in progress mak ing future interrupts impossible 41 264 uPSD34xx INTERRUPT SYSTEM Table 16 Interrupt Summary Flag Bit Name Inter
232. igh order address signals are required on external pins MCU addresses A 15 8 then these address signals can be brought out as need ed to PLD output pins or to the Address Out mode pins on PSD Module ports See PSD Module sec tion Latched Address Output Mode page 208 for details Figure 16 page 56 represents the flexibility of pin function routing controlled by the SFRs Each of the 24 pins on three ports P1 P3 and P4 may be individually routed on a pin by pin basis to a de sired function 54 264 MCU Port Operating Modes MCU port pins can operate as GPIO or as alter nate functions see Figure 17 page 57 through Figure 19 page 58 Depending on the selected pin function a particu lar pin operating mode will automatically be used m Quasi bidirectional mode UARTO UART1 Quasi bidirectional mode SPI Quasi bidirectional mode 12 Open drain mode ADC Analog input mode PCA output Push Pull mode PCA input Input only Quasi bidirectional m Timer 0 1 2 Input only Quasi bidirectional GPIO Function Ports in GPIO mode operate as quasi bidirectional pins consistent with standard 8051 architecture GPIO pins are individually con trolled by three SFRs m SFR P1 Table 27 page 58 m SFR Table 28 page 59 m SFR P4 Table 29 page 59 These SFRs can be accessed using the Bit Ad dressing mode an efficient way to control individ ual port pins GPIO Output Simply stated
233. igure 35 UART Mode 2 Block Diagram fosc 32 Internal Bus TB8 Write SBUF SBUF y v V Y S Zero Detector Shift Tx Control TI Start Data Tx Clock Send Serial Port Interrupt Load SBUF Shift RI 121020 Rx Control Transition Start MEM Input Shift Register Rx Clock Load RxD Pin SBUF M Shift SBUF Read SBUF v Internal Bus Figure 36 UART Mode 2 Timing Diagram Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI 92 264 Start Bit 50 X pi X 52 X os X 54 X Ds X DS X 57 TBS Y Stop Bit TE IL IL IL IL Start Bit Do XDi X D2 X D3 X X D5 X D6 X D7 X RB8 Stop Bit 106844 Transmit Receive 106845 uPSD34xx SERIAL UART INTERFACES Figure 37 UART Mode 3 Block Diagram Timer1 Overflow Timer2 Overflow Internal Bus TB8 TxD SBUF y v V Y S Zero Detector Shift Data Tx Control TI Start Tx Clock Send Serial Port Interrupt Load SBUF Shift RI 11020 Rx Control Transition Start Input Shift Register Rx Clock Load RxD Pin SBUF M Shift SBUF Read SBUF v Internal Bus AI06846 Figure 38 UART Mode 3 Timing Diagram Tx Clock Write to
234. in output enable signal a product term from AND OR array the csiop Direc tion register or the Peripheral I O Mode logic Port A only The csiop Enable Out registers represent the state of the final output enable signal for each port pin driver and are defined in Table 140 page 211 through Table 143 page 211 Table 136 Port A Pin Drive Select Register address csiop offset 08h 7 6 Bits 5 4 2 Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Note 1 Port A not available on 52 pin uPSD34xx devices 2 For each bit 1 pin drive type is selected 0 pin drive type is default mode CMOS push pull 3 Default state for register is after reset or power up Table 137 Port B Pin Drive Select Register address csiop offset 09h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Note 1 For each bit 1 pin drive type is selected 0 pin drive type is default mode CMOS push pull 2 Default state for register is OOh after reset or power up 210 264 uPSD34xx PSD MODULE Table 138 Port C Pin Drive Select Register address csiop offset 16h 7 6 Bits 5 4 3 Bit2 2 1
235. interrupt priority poll ing and enabling process Each interrupt source has at least one interrupt flag that indicates whether or not an interrupt is pending These flags reside in bits of various SFRs shown in Table 16 page 42 All of the interrupt flags are latched into the inter rupt control system at the beginning of each MCU machine cycle and they are polled at the begin ning of the following machine cycle If polling de termines one of the flags was set the interrupt control system automatically generates an LCALL to the user s Interrupt Service Routine ISR firm ware stored in program memory at the appropriate vector address uPSD34xx INTERRUPT SYSTEM The specific vector address for each of the inter rupt sources are listed in Table 16 page 42 How ever this LCALL jump may be blocked by any of the following conditions interrupt of equal or higher priority is already in progress Thecurrent machine cycle is not the final cycle in the execution of the instruction in progress The current instruction involves a write to any of the SFRs IE IEA IP or IPA The current instruction is an RETI Note Interrupt flags are polled based on a sample taken in the previous MCU machine cycle If an in terrupt flag is active in one cycle but is denied ser viced due to the conditions above and then later it is not active when the conditions above are finally satisfied the previously den
236. ion FSx or CSBOOTx specified in PSDsoft Express matches the address range that the 8032 firmware is accessing otherwise the instruction sequence will not be recognized by the Flash ar ray If memory paging is used be sure that the 8032 firmware sets the page register to the correct page number before issuing an instruction se quence to the Flash memory segment on a partic ular memory page otherwise the correct sector select signal will not become active Once the 8032 issues a Flash memory program or erase instruction sequence it must check the sta tus bits for completion The embedded algorithms that are invoked inside a Flash memory array pro vide several ways to give status to the 8032 Sta tus may be checked using any of three methods Data Polling Data Toggle or Ready Busy pin Functional Block FSx or CSBOOTx DQ7 DQ6 DQ5 004 DQ2 DQ1 DQO Active the desired Data Flash Memory segment is selected Polling Erase Toggle Error X Time X X X Flag Flag cut Note 1 X Not guaranteed value can be read either 1 or 0 2 007 000 represent the 8032 Data Bus Bits 07 00 181 264 uPSD34xx PSD MODULE Data Polling Polling on the Data Polling Flag Bit DQ7 is a method of checking whether a program or erase operation is in progress or has complet ed Figure 72 shows the Data Polling algorithm When the 8032 issues a program instruction se quence the embedd
237. ion RETI the next instruction to be executed will be the one which follows the instruction that set the IDL bit in the PCON SFR After a reset from the supervisor the IDL bit is cleared Idle Mode is terminated and the MCU restarts after three MCU machine cycles Power down Mode Power down Mode will halt the 8032 core and all MCU peripherals Power down Mode blocks MCU CLK USB CLK and PERIPH This is the lowest power state for the MCU Module When the PSD Module is also placed in Power down mode the lowest total current consumption for the combined die is achieved for the uPSD34xx See Power Management page 168 in the PSD Module section for details on how to also place the PSD Module in Power down mode The sequence of 8032 instructions is important when placing both modules into Power down Mode The instruction that sets the PD Bit in the SFR named PCON Table 26 page 52 is the last in struction executed prior to the MCU Module going into Power down Mode Once in Power down Mode the on chip oscillator circuitry and all clocks are stopped The SFRs DATA and XDATA are preserved Power down Mode is terminated only by a reset from the supervisor originating from the RESET IN pin the Low Voltage Detect circuit LVD or a JTAG Debug reset command Since the clock to the WTD is not active during Power down mode it is not possible for the supervisor to generate a WDT reset Table 24 page 51
238. ion when starting another data transfer immediately following the previous data transfer Figure 42 page 100 When transferring data the logic level on the SDA line must remain stable while SCL is high and SDA can change only while SCL is low However when not transferring data SDA may change state while SCL is high which creates the START and STOP bus conditions 99 264 uPSD34xx INTERFACE An Acknowlegde bit is generated from a Master or a Slave by driving SDA low during the ninth bit time just following each 8 bit byte that is transfered on the bus Figure 42 page 100 A Non Acknowledge occurs when SDA is asserted high during the ninth bit time All byte transfers on the 2 bus include a 9th bit time reserved for an Acknowlege ACK or Non Acknowledge NACK Figure 42 Data Transfer an 2 Bus Condition READ WRITE Indicator 7 bit Slave Address to stall transfer 100 264 Clock can be held low N Acknowledge An additional Master device that desires to control the bus should wait until the bus is not busy before generating a START condition so that a possible Slave operation is not interrupted If two Master devices both try to generate a START condition simultaneously the Master who looses arbitration will switch immediately to Slave mode so it can recoginize its own Slave address should it appear on the bus bits from
239. ircuit Emulator by using the serial 3 uPSD34xx SUMMARY DESCRIPTION JTAG debug interface JTAG is also used for In System Programming ISP in as little as 10 sec onds perfect for manufacturing and lab develop ment The 8032 core is coupled to Programmable System Device PSD architecture to optimize the 8032 memory structure offering two independent banks of Flash memory that can be placed at vir tually any address within 8032 program or data ad dress space and easily paged beyond 64K bytes using on chip programmable decode logic Dual Flash memory banks provide a robust solu tion for remote product updates in the field through In Application Programming IAP Dual Flash banks also support EEPROM emulation eliminat ing the need for external EEPROM chips General purpose programmable logic PLD is in cluded to build an endless variety of glue logic saving external logic devices The PLD is config ured using the software development tool PSD soft Express available from the at www st com psm at no charge The uPSD34xx also includes supervisor functions such as a programmable watchdog timer and low voltage reset Note For a list of known limitations of the uPSD34xx devices please refer to IMPORTANT NOTES page 262 7 264 uPSD34xx SUMMARY DESCRIPTION Figure 2 Block Diagram 3 16 bit Timer Counters 2 External Interrupts Programmable Page Logic 8 GPIO Port 3 General Pur
240. is also controlled by csiop registers at run time PLD I O PSDsoft Express logic equations and pin configuration selections determine if pins are connected to OMC outputs or IMC inputs This is a static and non volatile configuration Port pins connected to PLD outputs can no longer be driven by the 8032 using MCU output mode Latched MCU Address Output Port A or Port B can output de multiplexed 8032 address signals AO A7 on a pin by pin basis as specified in csiop registers at run time In addition Port B can also be configured to output de multiplexed A8 A15 in PSDsoft Express Data Bus Repeater Port A can bi directionally buffer the 8032 data bus de multiplexed for a specified address range in PSDsoft Express This is referred to as Peripheral I O Mode in this document Open Drain Outputs Some port pins can function as open drain as specified in csiop registers at run time Pins on Port D can be used for external chip select outputs originating from the DPLD without consuming OMC resources within the GPLD JTAG Port In System Programming ISP can be performed through the JTAG signals on Port C This serial interface allows programming of the en tire PSD Module device or subsections of the PSD Module for example only Flash memory but not the PLDs without the participation of the 8032 A blank uPSD34xx device soldered to a circuit board can be completely programmed in 10 to 25 sec onds
241. is higher that a particular value Please re fer to Table 38 page 66 in the MCU Module section The default state of the Turbo Bit is logic 0 mean ing Turbo mode is on by default after power up and reset conditions until it is turned off by the 8032 writing to PMMRO PLD Current Consumption Figure 96 page 233 and Figure 97 page 233 5V and 3 3V devices respectively show the relationship between PLD current consumption and the com posite frequency of all the transitions on PLD in puts indicating that a higher input frequency results in higher current consumption Current consumption of the PLDs have a DC com ponent and an AC component Both need to be considered when calculating current consumption for a specific PLD design When Turbo mode is on there is a linear relationship between current and frequency and there is a substantial DC current component consumed by the PSD Module when there are no transitions on PLD inputs composite frequency is zero The magnitude of this DC cur rent component is directly proportional to how many product terms are used in the equations of both PLDs PSDsoft Express generates a fitter report that specifies how many product terms were used in a design out of a total of 186 available product terms Figure 96 page 233 and Figure 97 page 233 both give two examples one with 100 of the 186 product terms used and another with 2596 of the 186 product terms used 3 uPSD34xx
242. is identified the associated Interrupt Flag Register may be read to determine the exact cause of the interrupt interrupt the USB Global Interrupt Flag Table 76 USB Global Interrupt Flag Register UIFO OE8h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GLF INF OUTF NAKF RSTF SUSPENDF EOPF RESUMF Details Bit Symbol R W Definition 7 GLE R Global Interrupt flag Logical OR of the RSTF SUSPENDF EOPF and RESUMF interrupt flags 6 INE R IN FIFO Interrupt flag Logical OR of the IN4F INSF IN2F IN1F and INOF interrupt flags OUT FIFO Interrupt flag 5 OUTF R Logical OR of the OUT4F OUT3F OUT2F OUT1F and OUTOF interrupt flags NAK FIFO Interrupt flag 4 NAKF R Logical OR of the NAK4F NAK3F NAK2F NAK1F and NAKOF interrupt flags USB Reset flag 3 RSTF R W This bit is set when a USB Reset is detected on the D and D lines When a USB Reset is detected the USB module is reset Note The CPU is not reset with a USB reset USB suspend mode flag 2 SUSPENDF R W This bit is set when the SIE detects 3ms of no activity on the bus and the clock to the SIE is also shut down to conserve power End of Packet flag 1 EOPF R W This bit is set when a valid End of Packet sequence is detected on the D and D line Resume flag 0 RESUMEF R W This bit is set when USB bus activity is detected while the SUSPNDF Bit is set 139 264 uPSD34xx USB INTERFACE USB IN FIFO Interr
243. isccHP Clock PC1 High Time PLD only Note 2 5 Clock PC1 Low Time PLD only Note 2 tiscpsu ISC Port Set Up Time tiscPH ISC Port Hold Up Time tiscPco ISC Port Clock to Output tiscpzv ISC Port High Impedance to Valid Output tiscPvz ISC Port Valid Output to High Impedance Note 1 For non PLD Programming Erase or in ISC By pass Mode 2 For Program or Erase PLD only 254 264 Table 181 ISC Timing 3V PSD Module uPSD34xx DC AND AC PARAMETERS Note 1 For non PLD Programming Erase or in ISC By pass Mode 2 For Program or Erase PLD only Figure 109 MCU Module AC Measurement I O Waveform Symbol Parameter Conditions Min Max Unit tisccr Clock PC1 Frequency except for PLD Note 1 16 MHz tisccH Clock TCK PC1 High Time except for PLD Note 1 tisccL Clock PC1 Low Time except for PLD Note 1 tisccrp Clock PC1 Frequency PLD only Note 2 4 MHz tisccHP Clock PC1 High Time PLD only Note 2 90 ns 45 Clock PC1 Low Time PLD only Note 2 90 ns tiscpsu 15 Port Set Up Time 12 ns tiscPH ISC Port Hold Up Time 5 ns tiscPco ISC Port Clock to Output 30 ns tiscPzv ISC Port High Impedance to Valid Output 30 ns tiscpvz_ ISC Port Valid Output to High Impedance Voc 0 5V 0 2 Voc 0 9V Test Points 0 2 Voc 0 1V 0 45V 106650
244. isted below m 1 and2 m OUTFIFO 1 and2 m IN FIFO 4 m OUT FIFO3 and 4 Note When the FIFOs are paired the CPU must access the odd numbered FIFO while the even numbered FIFOs are no longer available for use Also when they are paired the active FIFO is au tomatically toggled by the update of USIZE Figure 54 FIFOs with no Pairing Non pairing FIFOs Example Consider a case where the device needs to send 1024 bytes of data to the host Without FIFO pairing see Figure 54 the CPU loads the IN EndpointO FIFO with 64 bytes of data and waits until the host sends an IN token to EndpointO and the SIE transfers the data to the host Once all 64 bytes have been transferred by the SIE the FIFO becomes empty and the CPU starts writing the next 64 bytes of data to the FIFO While the CPU is writing the data to the FIFO the host is sending IN tokens to EndpointO requesting the next 64 bytes of data but only gets NAKs while the FIFO is being loaded Once the FIFO has been loaded by the CPU the SIE starts sending the data to the host with the next IN EndpointO token Again the CPU waits until the SIE transfers the 64 bytes of data to the host This is repeated until all 1024 bytes have been transferred Endpoint4 Endpoint4 FIFO Endpoint3 Endpoint3 IN FIFO Endpoint2 Endpoint2 IN FIFO Endpoint1 Endpoint IN FIFO EndpointO EndpointO IN FIFO Serial Interface Engine E
245. ix phases to reference in this dis cussion Each instruction is pre fetched into the PFQ in advance of execution by the MCU Prior to Phase 1 the PFQ has pre fetched the two instruc tion bytes A1 and A2 of Instruction A During Phase one both bytes are loaded into the MCU execution unit Also in Phase 1 the PFQ is pre fetching Instruction B bytes B1 and B2 from pro gram memory In Phase 2 the MCU is processing Instruction A internally while the PFQ is pre fetch ing Instruction C In Phase 3 both bytes of instruc tion B are loaded into the MCU execution unit and the PFQ begins to pre fetch bytes for the next in struction In Phase 4 Instruction B is processed The uPSD34xx MCU instructions are an exact 1 3 scale of all standard 8032 instructions with regard to number of cycles per instruction Figure 10 page 21 shows the equivalent instruction se quence from the example above on a standard 8032 for comparison Aggregate Performance The stream of two byte two cycle instructions in Figure 9 page 21 running on a 40MHz 5V uPSD34xx will yield 5 MIPs And we saw the stream of one or two byte one cycle instructions in Figure 7 page 19 on the same MCU yield 10 MIPs Effective performance will depend on a number of things the MCU clock frequency the mixture of instructions types bytes and cycles in the application the amount of time an empty PFQ stalls the MCU mix of instruction types and miss es on Branch Cache
246. k data transfers With double buffer ing enabled the MCU can operate on one data packet while another is being transferred over USB When two FIFOs are paired the active FIFO is au tomatically toggled by the update of USIZE The MCU must only use the odd numbered endpoint FIFO when paired in order to access the active FIFO For example if endpoints 3 and 4 OUT FIFOs are paired the active FIFO is accessed via endpoint 3 s OUT FIFO see Table 71 Table 70 USB Device Address Register UADDR OE2h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USBADDR 6 0 Details Bit Symbol R W Definition 7 Reserved USB Address of the device 5 0 USBADDA RW These bits are cleared with a Hardware RESET or a USB RESET Table 71 Pairing Control Register UPAIR OE3h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PR3OUT PR1OUT PR1IN Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 Reserved Setting this bit enables double buffering of the OUT FIFOs for Endpoints 3 R W 3 and 4 Access to the double buffered FIFOs is through Endpoint3 s OUT FIFO Setting this bit enables double buffering of the OUT FIFOs for Endpoints 2 PR1OUT R W 1 and 2 Access to the double buffered FIFOs is through Endpoint1 s OUT FIFO Setting this bit enables double buffering of the IN FIFOs for Endpoi
247. ks MCU_CLK only For lowest current consumption in this mode it is recommended to disable all un used peripherals before entering Idle mode such as the ADC and the Debug Unit breakpoint com parators The following functions remain fully ac tive during Idle Mode except if disabled by SFR settings m External Interrupts INTO and INT1 m Timer 0 Timer 1 and Timer 2 m Supervisor reset from LVD JTAG Debug External RESET but not the WTD ADC Interface UARTO and UART1 Interfaces SPI Interface Programmable Counter Array m USB Interface An interrupt generated by any of these peripher als or a reset generated from the supervisor will cause Idle Mode to exit and the 8032 MCU will re sume normal operation The output state on I O pins of MCU ports 1 3 and 4 remain unchanged during Idle Mode To enter Idle Mode the 8032 MCU executes an in struction to set the IDL bit in the SFR named PCON shown in Table 26 page 52 This is the last instruction executed in normal operating mode before Idle Mode is activated Once in Idle Mode the MCU status is entirely preserved and there are no changes to SP PSW PC ACC SFRs DATA IDATA or XDATA The following are factors related to Idle Mode exit Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware terminating Idle Mode The interrupt is 50 264 serviced and following the Return from Interrupt instruct
248. l EEPROM memory and more reli able because the last known value in a data set is maintained even if a WRITE cycle is corrupted by a power outage The EEPROM emulation function can be called by the user s firmware making it ap pear that the user is writing a single byte or data record thus hiding all of the data management that occurs within the two 8K byte flash sectors EEPROM emulation firmware for the uPSD34xx is available from www st com psm Alternative Mapping Schemes Here are more possible memory maps for the uPSD3433 Note Mapping examples would be slightly differ ent for uPSD3433 and uPSD3434 because of the different sizes of individual Flash memory sectors Figure 66 Place the larger Main Flash Memory into program space but split the Secondary Flash in half placing two of its sectors into XDATA space and remaining two sectors into program space This method allows the designer to put IAP code or boot code into two sectors of Secondary Flash in program space and use the other two Secondary Flash sectors for data storage such as EEPROM emulation in XDATA space uPSD34xx PSD MODULE Figure 67 Place both the Main and Secondary Flash memories into program space for maximum code storage with no Flash memory in XDATA space Figure 66 Mapping Split Second Flash in Half 8032 PROGRAM 8032 XDATA SPACE SPACE PSEN RD and WR Page Page Page Page FFFFh 0 1 2 3 Page Xx FFFFh fs1 fs3 fs5
249. l signals refers to delay from pins on Port 0 Port 2 RD WR PSEN and ALE to CPLD combinatorial output 80 pin package only Table 166 CPLD Combinatorial Timing 3V PSD Module Symbol Parameter Conditions Min Max io Tom e Unit EET 2 eem EA E Ped to CPLD Output 38 15 6 ns to CPLD Output 38 15 6 ie 5 sas 6 perc 5 s tarno CPLD Array Delay i LA 20 4 ns Note 1 Fast Slew Rate output available on PA3 PAO PB3 PBO and PD2 PD1 Decrement times by given amount 2 tpp for MCU address and control signals refers to delay from pins on Port 0 Port 2 RD WR PSEN and ALE to CPLD combinatorial output 80 pin package only 245 264 uPSD34xx DC AND AC PARAMETERS Figure 102 Synchronous Clock Mode Timing PLD CLKIN INPUT REGISTERED OUTPUT tCH tcL lt Symbol Parameter Conditions Min Unit Maximum Frequency External Feedback Maximum Frequency fmax Internal Feedback 1 ts tco 1 tg tco 10 MHz Maximum Frequency Pipelined Data ts Input Setup Time 1 tcH tcL tH Input Hold Time Clock Input Clock Low Time Clock Input tco Clock to Output Delay tARD CPLD Array Delay Clock Input Any macrocell Minimum Clock Period No
250. l will last only as long as the RESET signal is active it is not stretched Refer to the Supervisor AC specifi cations in Table 178 page 253 at the end of this document for these parameter values MCU RESET gt _ gt to MCU and Peripherals RESET to PSD Module 109603 67 264 uPSD34xx SUPERVISORY FUNCTIONS Low Vcc Voltage Detect LVD An internal reset is generated by the LVD circuit when Vcc drops below the reset threshold THRESH After Vcc returns to the reset thresh old the RESET signal will remain asserted for tast_actv before it is released The LVD circuit is always enabled cannot be disabled by SFR even in Idle Mode and Power down Mode The LVD input has a voltage hysteresis of Vast_Hys and will reject voltage spikes less than a duration of tasT_FIL Important The LVD voltage threshold is Viv THRESH Suitable for monitoring both the 3 3V Vcc supply on the MCU Module and the 3 3V Vpp supply on the PSD Module for 3 3V uPSD34xxV devices since these supplies are one in the same on the circuit board However for 5V uPSD34xx devices Vi y THRESH is not suitable for monitoring the 5V Vpp voltage supply VLv_THRESH is too low but good for mon itoring the 3 3V Vcc supply In the case of 5V uPSD34xx devices an external means is required to monitor the separate 5V Vpp supply if desired Power up Reset At power up the internal reset generated by the LVD circuit is latched as a logic 1
251. ld be unconditionally cleared The 3400 USB firmware implements this workaround IN FIFO Pairing Operation Description FIFO pairing is not available on IN endpoints Sin gle FIFO buffering should be used instead Impact On Application Use Single FIFO Buffering uPSD34xx IMPORTANT NOTES Workaround Only use the single FIFO mode The 3400 USB firmware implements this workaround PORT 1 Not 5 volt IO Tolerant Description The port P1 is shared with the ADC module and as a result Port P1 is not 5V tolerant Impact On Application 5V devices should not be connected to port P1 Workaround Peripherals or GPIO that require 5 Volt IO toler ance should be mapped to Port 3 or Port 4 263 264 uPSD34xx REVISION HISTORY REVISION HISTORY Table 186 Document Revision History Date Version Revision Details 04 Feb 2005 30 Mar 2005 1 First Edition Added one note in SUMMARY DESCRIPTION page 7 Added two notes in USB INTERFACE page 123 Changed values in Table 175 page 252 Turbo Off column Added IMPORTANT NOTES page 262 25 Oct 2005 Changed Table 1 page 2 to add sales types with 32K SRAM Changed Figure 2 page 8 Changed Figure 6 page 16 Corrected Port Pin P1 5 from ADC6 to ADC5 in Table 2 page 11 Removed duplicate entry for 80 pin no 11 in Table 2 page 11 Changed Figure 62 page 164 Updated Table 101 page 166 Updated Table 185 page 261 Inform
252. le the USB Resume interrupt 3 uPSD34xx USB INTERFACE USBIN FIFO Interrupt Enable Register UIE1 USB OUT FIFO Interrupt Enable Register When an endpoint s IN FIFO has been UIE1 successfully sent to the host with an IN transaction the FIFO becomes empty The UIE1 register is used to enable each endpoint s IN FIFO interrupt Table 73 Table 73 USB IN FIFO Interrupt Enable Register UIE1 OE5h Reset Value 00h Table 74 When an endpoint s OUT FIFO has been filled by an OUT transaction from the host the FIFO becomes full The UIE2 register is used to enable each endpoint s OUT FIFO interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 IN2IE INOIE Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 INAIE R W Enable Endpoint 4 IN FIFO interrupt 3 INSIE R W Enable Endpoint 3 IN FIFO interrupt 2 IN2IE R W Enable Endpoint 2 IN FIFO interrupt 1 IN1IE R W Enable Endpoint 1 IN FIFO interrupt 0 INOIE R W Enable Endpoint 0 IN FIFO interrupt Table 74 USB OUT FIFO Interrupt Enable Register UIE2 OE6h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 OUT4IE OUTSIE OUT2IE OUTOIE Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved 4 OUT4IE R W Enable Endpoint 4 OUT FIFO interrupt 3 OUTSIE R W Enable Endpoint 3 OUT FIFO interrupt 2 OUT2IE R W
253. lects the time out period allowed between two consecutive sector erase instruction sequence bytes If multi ple sector erase commands are desired the addi tional sector erase commands 30h must be sent by the 8032 to another sector within 80us after the previous sector erase command is 0 before this time period has expired indicating it is OK to issue additional sector erase commands will go to logic 1 if the time has been longer than 80 since the previous sector erase command time has expired indicating that is not OK to send an other sector erase command In this case the 8032 must start a new sector erase instruction se quence unlock and command beginning again after the current sector erase operation has com pleted During a Sector Erase operation the memory sta tus may be checked by reading the Error Flag Bit DQ5 the Toggle Flag Bit DQ6 and the Data Polling Flag Bit DQ7 as detailed in Reading the Erase Program Status Bits page 180 During a Sector Erase operation a Flash memory accepts only Reset Flash and Suspend Sector Erase instruction sequences Erasure of one Flash memory sector may be suspended in order to read data from another Flash memory sector and then resumed The address provided with the initial Flash Sector Erase command sequence Table 107 page 179 must select the first desired sec tor FSx or CSBOOTx to erase Subsequent sec tor erase commands that are append
254. lication Program ming IAP involves the 8032 to program Flash memory over any interface supported by the 8032 e g UART SPI I2C which is good for remote updates over a communication channel uPSD34xx devices support both ISP and IAP The entire PSD Module Flash memory and PLD may be programmed with JTAG ISP but only the Flash memories may be programmed using IAP JTAG Chaining Inside the Package JTAG pro tocol allows serial chaining of more than one de vice in a JTAG chain The uPSD34xx is assembled with a stacked die process combining the PSD Module one die and the MCU Module the other die These two die are chained together within the uPSD34xx package The standard JTAG interface has four basic signals m TDI Serial data into device m TDO Serial data out of device m TCK Common clock m TMS Mode Selection Every device that supports IEEE 1149 1 JTAG communication contains a Test Access Port TAP controller which is a small state machine to man age JTAG protocol and serial streams of com mands and data Both the PSD Module and the MCU Module each contain a TAP controller Figure 91 illustrates how these die are chained within a package JTAG programming test equip ment will connect externally to the four IEEE 1149 1 JTAG pins on Port C The TDI pin on the uPSD34xx package goes directly to the PSD Mod ule first then exits the PSD Module through TDO TDO of the PSD Module is connected to TDI of the M
255. lly as described in MCU CLOCK GENERATION page 47 Figure 15 Oscillator and Clock Connections The pin XTAL1 is the high gain amplifier input and XTAL2 is the output To drive the uPSD34xx de vice externally from an oscillator or other active device XTAL1 is driven and XTAL2 is left open circuit This external source should drive a logic low at the voltage level of 0 3 Vcc or below and logic high at 0 7V Vcc or above up to 5 5V Vcc The XTAL1 input is 5V tolerant Most of the quartz crystals in the range of 25MHz to 40MHz operate in the third overtone frequency mode An external LC tank circuit at the XTAL2 output of the oscillator circuit is needed to achieve the third overtone frequency as shown in Figure 15 page 53 Without this LC circuit the crystal will oscillate at a fundamental frequency mode that is about 1 3 of the desired overtone frequency Note In Figure 15 page 53 crystals which are specified to operate in fundamental mode not overtone mode do not need the LC circuit compo nents Since quartz crystals and ceramic resona tors have their own characteristics based on their manufacturer it is wise to also consult the manu facturer s recommended values for external com ponents C1 XTAL fosc XTAL fosc Crystal or Resonator Usage C3 L1 Ceramic Resonator Crystal fundamental mode 3 40MHz Crystal overtone mode 25 40MHz XTAL1 XTAL2 Direct Drive in out External Oc
256. lock the Flash array followed by writing a command byte The bus operations consist of writing the data AAh to address X555h during the first bus cycle and data 55h to address XAAAh during the second bus cy cle 8032 address signals A12 A15 are Don t care during the instruction sequence during WRITE cycles However the appropriate sector select signal FSx or CSBOOTx from the DPLD must be active during the entire instruction se quence to complete the entire 8032 address this includes the page number when memory paging is used Ignoring A12 A15 means the user has more flexibility in memory mapping For example in many traditional Flash memories instruction se quences must be written to addresses AAAAh and 5555h not XAAAh and X555h like supported on the PSD Module When the user has to write to AAAAh and 5555h the memory mapping options are limited The Main Flash and Secondary Flash memories each have the same instruction set shown in Table 107 page 179 but the sector select signals de termine which memory array will receive and exe cute the instructions uPSD34xx PSD MODULE Table 107 Flash Memory Instruction Sequences Instr Bus Bus Bus Bus Sequence Cycle 1 Cycle 2 Cycle 5 Cycle 6 Read Memory Read byte Contents from any iint dea Read valid Flash eet p Array memory addr g mode Program write a Write AAh to Write 55h Write AOh Writedata jui ero Byte to X555h to XAAAh X555h
257. ly PCA Block The 16 bit Up Counter in the PCA block is a free running counter except in PWM Mode with pro grammable frequency The Counter has a choice Figure 58 PCAO Block Diagram of clock input from an external pin Timer 0 Over flow or PCA Clock A PCA block has 3 Timer Counter Modules TCM which share the 16 bit Counter output The TCM can be configured to capture or compare counter value generate a toggling output or PWM func tions Except for the PWM function the other TCM functions can generate an interrupt when an event occurs Every TCM is connected to a port pin in Port 4 the TCM pin can be configured as an event input a PWMs a Toggle Output or as External Clock In put The pins are general I O pins when not as signed to the TCM The TCM operation is configured by Control regis ters and Capture Compare registers Table 93 page 155 lists the SFR registers in the PCA blocks TIMERO OVERFLOW 4 3 IDLE MODE From CPU 154 264 16 bit up Timer Counter 1 PCACLO 8 bit CLEAR COUNTER INT 8 bit gt P4 0 CEXO 4 5 P4 1 CEX1 lt gt lt P4J2 CEX2 PWM FREQ COMPARE 107857 1572 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM Table 93 PCAO and PCA1 Registers 3 SFR Address Register Name RW Register Function PCAO PCA1 PCAO PCA1 A2 BA PCACLO PCACL1
258. m of the AND OR Array defined by equations in PSD soft Express for signals c pr and re respec tively The preset and clear inputs on the flip flops are level activated active high logic signals The clock inputs on the flip flops are rising edge logic signals Optionally the signal CLKIN pin PD1 can be used for a common clock source to all OMC flip flops Each flip flop is clocked on the rising edge A common clock is specified in PSDsoft Express by assigning the function Common Clock Input for pin PD1 in the Pin Definition section and then choosing the signal CLKIN when specifying the clock input c for individual flip flops in the User Defined Nodes section DATA BIT FROM 8032 o a 1 zx o i a E BORROWED LENDED INDICATES MCU WRITE PTs PTs PARTICULAR CSIO REGISTER _ i PT ALLOCATOR MCU READ OF amp DRAWS FROM LOCAL PARTICULAR CSIOP AND GLOBAL UNUSED REGISTER _ 2 i PRODUCT TERMS MCU OVERRIDES lt lt PSDsoft DICTATES PT PRESET AND DATA BIT TO 8032 CLR DURING 2 1 MCU WRITE i FROM AND OR ARRAY gt gt ELEBESETCERI ES 9 ALLOCATED PTs F N FROM AND OR ARRAY J gt MAUVE PIS 2 a OMC POLARITY Du OUTPUT SELECT PRE OMC D Q gt gt PSDsoft ALLO FROM PLD INPUT BUS 27 s OB AL CLOCK CLKIN PSDsoft FROM AND OR ARRAY 3 CLOCK CC CLR FROM AND OR ARRAY J gt
259. me in a multi Slave configuration Slave selection is accomplished when a Slave s Slave Select SS input is permanently grounded or asserted active low by a Master device Slave devices that are not selected do not interfere with SPI activities Slave devices ignore SPICLK and keep their MISO output pins in high impedance state when not selected The SPI specification allows a selection of clock polarity and clock phase with respect to data The uPSD34xx supports the choice of clock polarity but it does not support the choice of clock phase phase is fixed at what is typically known as CPHA 1 See Figure 46 and Figure 47 page 117 for SPI data and clock relationships Referring to these figures 46 and 47 when the phase mode is defined as such fixed at CPHA 1 in a new SPI data frame the Master device begins driving the first data bit on SPITxD at the very first edge of the first clock period of SPI CLK Figure 45 SPI Full Duplex Data Exchange The Slave device will use this first clock edge as a transmission start indicator and therefore the Slave s Slave Select input signal may remain grounded in a single Master single Slave configu ration which means the user does not have to use the SPISEL signal from uPSD34xx in this case The SPI specification does not specify high level protocol for data exchange only low level bit seri al transfers are defined Full Duplex Operation When an SPI transfer occurs 8 bits o
260. mmon clock input on OMCs Bit 6 Not used and should be set to zero Bit 7 x o Not used and should be set to zero Note All the bits of this register are cleared to zero following Power up Subsequent Reset RST pulses do not clear the registers 1 Blocking bits should be set to logic 1 only if the signal is not needed in a DPLD or GPLD logic equation Table 145 Power Management Mode Register PMMR2 address csiop offset B4h Bit 0 X 0 Not used and should be set to zero Bit 1 X 0 Not used and should be set to zero Blocking Bit 8032 WR input to the PLD Input Bus is not blocked WR to PLDs 8032 WR input to PLD Input Bus is blocked saving power i it 0 8032 RD input to the PLD Input Bus is not blocked Bit 3 Blocking Bit 0 on p p Bit 2 RD to PLDs 4 8032 RD input to PLD Input Bus is blocked saving power Blocking Bit 8032 input the PLD Input Bus is not blocked Bit 4 PSEN to PLDs 8032 PSEN input to PLD Input Bus is blocked saving power Blocking Bit 8032 ALE input to the PLD Input Bus is not blocked Bit 5 ALE to PLDs 8032 ALE input to PLD Input Bus is blocked saving power Blocking Bit Pin PC7 input to the PLD Input Bus is not blocked Bit 5 PC7 to PLDs 1 Pin PC7 input to PLD Input Bus is blocked saving power Bit 7 Not used and should be set to zero Note The bits of this register are cleared to zero
261. mode when GC 1 the Bus Lost condition exists and BLOST 1 STOP STOP flag STOP 1 while SIOE detects a STOP condition on the bus when in Master or Slave mode INTR TX_MODE R W Interrupt flag INTR is set to 1 by any of the five 2 interrupt conditions listed above INTR must be cleared by firmware Transmission Mode flag TX MODE 1 whenever the SIOE is in Master Transmitter or Slave Transmitter mode TX MODE 0 when SIOE is in any receiver mode BBUSY Bus Busy flag BBUSY 1 when the 2 bus is in use BBUSY is set by the SIOE when a START condition exists on the bus and BBUSY is cleared by a STOP condition BLOST Bus Lost flag BLOST is set when the SIOE is in Master mode and it looses the arbitration process to another Master device on the bus ACK RESP Not Acknowledge Response flag While SIOE is in Transmitter mode After SIOE sends a byte ACK RESP 1 whenever the external IC device receives the byte but that device does NOT assert an ackowledge signal external device asserted a high on SDA during the acknowledge bit time After SIOE sends a byte ACK RESP 0 whenever the external IC device receives the byte and that device DOES assert an ackowledge signal external device drove a low on SDA during the acknowledge bit time Note If SIOE is in Master Transmitter mode and ACK RESP 1 due to a Slave Transmitter not sending an Acknowledge a STOP condition
262. mory XDATA by using the 16 bit address stored in the DPTR Register There are only two instructions using this mode and both use the accumulator to either re ceive a byte from external memory addressed by DPTR or to send a byte from the accumulator to the address in DPTR The uPSD34xx has a spe cial feature to alternate the contents source and destination of DPTR rapidly to implement very ef ficient memory to memory transfers For example MOVX A Move contents of accumulator to XDATA at address contained in DPTR MOVX Move XDATA to accumulator Note See details in DUAL DATA POINTERS page 38 External Indirect Addressing This mode will access external memory XDATA by using the 8 bit address stored in either Register RO or R1 This is the fastest way to access XDATA least bus cycles but because only 8 bits are available for address this mode limits XDATA to a size of only 256 bytes the traditional Port 2 of the 8032 MCU is not available in the uPSD34xx so it is not possible to write the upper address byte This mode is not supported by uPSD34xx For example MOVX QRO0 A Move into the accumulator the XDATA that is pointed to by the address contained in RO 31 264 uPSD34xx 8032 ADDRESSING MODES Indexed Addressing This mode is used for the MOVC instruction which allows the 8032 to read a constant from program memory not data memory MOVC is often used to read lo
263. n by configuration with PSDsoft Express This is typically used to protect 8032 boot code from being corrupted by inadvert ent WRITEs to Flash memory from the 8032 Status of sector protection bits may be read but not written using two registers in csiop space Memory Mapping There many different ways to place or map the address range of PSD Module memory and depending on system requirements The DPLD provides complete mapping flexibility Figure 64 shows one possible system memory map In this example 128K bytes of Main Flash memory for a uPSD3433 device is in 8032 program address space and 32K bytes of Secondary Flash memo ry the SRAM and csiop registers are all in 8032 XDATA space In Figure 64 the nomenclature fsO fs7 are desig nators for the individual sectors of Main Flash memory 16K bytes each CSBOOTO CSBOOTS3 are designators for the individual Secondary Flash memory segments 8K bytes each rsO is the des ignator for SRAM and csiop designates the PSD Module control register set The designer may easily specify memory mapping in a point and click software environment using PSDsoft Express creating a non volatile configu ration when the DPLD is programmed using JTAG uPSD34xx PSD MODULE 8032 Program Address Space In the example of Figure 64 six sectors of Main Flash memory fs2 167 are paged across three memory pages in the upper half of program address space and the remaining two sec
264. n Figure 27 page 75 TLO uses the Timer 0 control Bits C T GATE TRO and TFO as well as the pin EXTINTO THO is locked into a timer function counting at a rate of 1 12 fosc and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt flag Mode 3 is provided for applications requiring an extra 8 bit timer on the counter see Figure 27 75 With Timer 0 in Mode 3 uPSD34xx device can look like it has three Timer Counters not including the PCA When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate gen erator or in fact any application not requiring an interrupt 73 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Table 42 TMOD Timer Mode Register SFR 89h reset value 00h GATE C T M 1 0 GATE C T M 1 0 Details Bit Symbol R W Timer Definition T C is abbreviation for Timer Counter Gate control 7 GATE RW When GATE 1 T C is enabled only while pin EXTINT1 is 1 and the flag TR1 is 1 When GATE 0 T C is enabled whenever the flag TR1 is 1 Counter or Timer function select 6 C T R W When C T 0 function is timer clocked by internal clock C T 1 function is counter clocked by signal sampled on Timer 1 external pin C1 Mode Select 00b 13 bit T C 8 bits in TH1 with TL1 as 5 bit pre scaler 5 4 M 1 0 RW 01b 16 bit T
265. n JTAG Connections CIRCUIT BOARD uPSD34xx TMS TCK SRAM STBY or I O GENERAL I O GENERAL I O TDI GENERAL I O GENERAL 100k typical JTAG Programming or Test Equipment Connects Here SIGNALS PUSH BUTTON or ANY OTHER RESET SOURCE OPTIONAL TEST POINT 110457 Note 1 For 5V uPSD34xx devices pull up resistors and Vcc pin on the JTAG connector should be connected to 5V system Vpp 2 For 3 3V uPSD34xx devices pull up resistors and Vcc pin on the JTAG connector should be connected to 3 3V system Vcc 3 This signal is driven by an Open Drain output in the JTAG equipment allowing more than one source to activate RESETIN ky 227 264 uPSD34xx PSD MODULE 6 pin JTAG ISP optional The optional signals TSTAT and TERR are programming status flags that can reduce programming time by as much as 30 compared to 4 pin JTAG because this status information does not have to be scanned out of the device serially TSTAT and TERR must be used as a pair for 6 pin JTAG operation TSTAT indicates when programming of a single Flash location is complete Logic 1 Ready Logic 0 busy TERR pin PC4 indicates if there was a Flash programming error Logic 1 no error Logic O error The pin functions for PC3 and PC4 must be select ed as Dedicated JTAG TSTAT and Dedicated JTAG TERR in PSDsoft Express to enable 6 pin JTAG ISP No 8032 firmware i
266. n PLD input signal bus and additionally the GPLD is connected to the 8032 data bus PLD logic is specified using PSDsoft Express and programmed into the PSD Module using the JTAG ISP channel PLD logic is non volatile and avail able at power up PLDs may not be programmed by the 8032 The PLDs have selectable levels of performance and power consumption The DPLD performs address decoding and gen erates select signals for internal and external com ponents such as memory registers and I O ports The DPLD can generate External Chip Select ECS1 ECS2 signals on Port D The GPLD can be used for logic functions such as loadable counters and shift registers state ma chines encoding and decoding logic These logic functions can be constructed from a combination of 16 Output Macrocells OMC 20 Input Macro cells IMC and the AND OR Array Routing of the 16 OMCs outputs can be divided between pins on three Ports A B or C by the OMC Allocator as shown in Figure 78 page 194 Eight of the 16 OMCs that can be routed to pins on Port A or Port B and are named MCELLABO The other eight OMCs to be routed to pins on Port B or Port C and are named MCELLBCO MCELLBC7 This routing depends on the pin number assignments that are specified in PSDsoft Express for PLD Outputs in the Pin Def inition section OMC outputs can also be routed in ternally not to pins used as buried nodes to create shifters counters etc
267. n be configured as an input so an external device can initiate an internal debug event e g break execution The Debug pin func tion is configured by the 8032 IDE debug software tool See DEBUG UNIT page 40 for more details The Debug signal should always be pulled up ex ternally with a weak pull up 100K minimum to Vcc even if nothing is connected to it as shown in Figure 92 page 227 and Figure 93 page 229 232 264 JTAG Security Setting A programmable securi ty bit in the PSD Module protects its contents from unauthorized viewing and copying The security bit is set by clicking on the Additional PSD Set tings box in the main flow diagram of PSDsoft Ex press then choosing to set the security bit Once a file with this setting is programmed into a uPSD34xx using JTAG ISP any further attempts to communicate with the uPSD34xx using JTAG will be limited Once secured the only JTAG oper ation allowed is a full chip erase No reading or modifying Flash memory or PLD logic is allowed Debugging operations to the MCU Module are also not allowed The only way to defeat the secu rity bit is to perform a JTAG ISP full chip erase op eration after which the device is blank and may be used again The 8032 on the MCU Module will al ways have access to PSM Module memory con tents through the 8 bit 8032 data bus connecting the two die even while the security bit is set Initial Delivery State When delivered from ST Microelectr
268. n by external 5V devices and they can directly drive external 5V devices while producing a of 2 4V and Vcc max Ports A B C and D of the PSD Module are true 5V ports For all 3 3V uPSD34xxV devices 3 3V MCU Module is stacked with a 3 3V PSD Module In this case a 3 3V uPSD34xx device needs to be sup plied with a single 3 3V voltage source at both Vcc and Vpp I O pins on Ports 3 and 4 are 5V tolerant and can be connected to external 5V peripherals devices if desired Ports A B C and D of the PSD Module are 3 3V ports which are not tolerant to external 5V devices Refer to Table 3 for port type and voltage source requirements 80 uPSD34xx devices provide access to 8032 address data and control signals on external pins to connect external peripheral and memory devic es 52 pin uPSD34xx devices do not provide ac cess to the 8032 system bus All non volatile memory and configuration portions of the uPSD34xx device are programmed through the JTAG interface and no special programming voltage is needed This same JTAG port is also used for debugging of the 8032 core at runtime providing breakpoint single step display and trace features A non volatile security bit may be programmed to block all access via JTAG inter face for security The security bit is defeated only by erasing the entire device leaving the device blank and ready to use again Table 3 Port Type and Voltage Source Combination
269. n on the port containing the pin TxD At the end of each SHIFT CLOCK in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX 3 uPSD34xx SERIAL UART INTERFACES Control unit to do one last shift then deactivate SEND and then set the interrupt flag TI Both of these actions occur at S1P1 Reception is initiated by the condition REN 1 and RI 0 At the end of the next MCU machine cycle the RX Control unit writes the bits 11111110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables the SHIFT CLOCK signal to the alternate function on the port containing the pin TxD Each pulse of SHIFT CLOCK moves the contents of the receive shift register one position to the left while RECEIVE is active The value that comes in from the right is the value that was sampled at the RxD pin As data bits come in from the right 1s shift out to the left When the 0 that was initially loaded into the right most position arrives at the left most position in the shift register it flags the RX Control unit to do one last shift and then it loads SBU
270. n the CSI function is specified in PSDsoft Ex press the CSI signal is automatically included in DPLD chip select equations for FSx CSBOOTx RSO and CSIOP When the CSI pin is driven to logic 0 from an external device all of these mem ories will be available for READ and WRITE oper ations When CSI is driven to logic 1 none of these memories are available for selection re gardless of the address activity from the 8032 re ducing power consumption The state of the PLD and port I O pins are not changed when CSI goes to logic 1 disabled PLD Non Turbo Mode The power consumption and speed of the PLDs are controlled by the Turbo Bit Bit 3 in the csiop PMMRO register By setting this bit to logic 1 the Turbo mode is turned off and both PLDs consume only stand by current when ALL PLD inputs have no transitions for an extend ed time 65ns for 5V devices 100ns for 3 3 V de vices significantly reducing current consumption The PLDs will latch their outputs and go to stand by drawing very little current When Turbo mode is off PLD propagation delay time is increased as shown in the AC specifications for the PSD Mod ule Since this additional propagation delay also effects the DPLD the response time of the memo ries on the PSD Module is also lengthened by that same amount of time If Turbo mode is off the user should add an additional wait state to the 8032 BUSCON SFR register if the 8032 clock fre quency
271. nctions of Bits 1 2 3 and 4 SRAM and csiop registers are always in XDATA space and cannot reside in program space Figure 70 page 174 illustrates how the VM Reg ister affects the routing of RD WR and PSEN to the memories on the PSD Module As an example if we apply the value OCh to the VM Register to im plement the memory map example shown in Fig ure 64 page 169 then the routing of RD WR and PSEN would look like that shown in Figure 71 page 175 In this example the configuration is specified in PSDsoft Express and programmed into the uPSD34xx using JTAG Upon power on or any re set condition the non volatile value OCh is loaded into the VM Register At runtime the value OCh in the VM Register may be changed overridden by the 8032 if desired to implement IAP or other func tions 173 264 uPSD34xx PSD MODULE Table 104 VM Register address csiop offset E2h Peripheral I O Mode on Port A 1 enable Peripheral I O not used not used not used not used cannot access Main Flash 1 RDorWR can access access Secondary Flash 1 RDorWR can access cannot access Main Flash 1 Bit 4 Bit 3 Bit 2 Bit 7 Bit 6 Main Flash Secondary Main Flash Flash y PIO_EN XDATA Flash XDATA Program Program Space Space Space Space 0 RDorWR Seen 0 PSEN 0 disable pesi cannot cannot access Secondary Flash 1 PSEN
272. nd ACK to Slave S1CON AA is already 1 Exit ISR ready to recv more bytes from Slave Else If mode is Slave Transmitter Is this Intr from SIOE detecting a STOP on bus If Yes a STOP was detected S1DAT dummy write to release bus Exit ISR Master needs no more data bytes If No a STOP was not detected continue ACK recvd from tus ACK RESP 0 If No an ACK was not received Master sta S1DAT dummy write to release bus Exit ISR Master needs no more data bytes If Yes ACK was received then continue S1DAT xmit buf buffer index transmit byte Exit ISR transmit next byte on next interrupt 113 264 uPSD34xx INTERFACE Else If mode is Slave Receiver Is this Intr from SIOE detecting a STOP on bus If Yes a STOP was detected buf buffer index S1DAT get last byte Exit ISR Master has sent last byte If co Determin No a STOP was not detected ntinue e if this Interrupt is from receiving an address or a data byte from a Master Is S1CON ADDR 1 and S1CON AA 1 If No intr is from receiving data goto C If Yes intr is from an address continue Sglave is adressed 1 local vari able set true indicates Master selected this slave 114 264 S1CON ADDR 0 clear address match flag Determine if R W bit indicates tran
273. ndpointO EndpointO OUT FIFO Endpoint1 Endpoint1 OUT FIFO Endpoint2 Endpoint2 OUT FIFO Endpoint3 napon Endpoint3 OUT FIFO Endpoint4 Endpoint4 OUT FIFO 130 264 8032 MCU XDATA FIFO Interface Logic umo 110493 1572 Pairing FIFOs Example Now assume that IN Endpoint1 and Endpoint2 FIFOs are paired for double buffering and the same 1024 bytes of data are to be transferred to the host As in the non pairing example the CPU loads the IN EndpointO FIFO with 64 bytes of data Instead of having to wait for the SIE to transfer the 64 bytes of data to the host the CPU can write another 64 bytes of data to IN EndpointO FIFO While the CPU is writing the second packet of 64 bytes of data into the FIFO the SIE is sending the first packet of 64 bytes of data to the host After the CPU has uPSD34xx USB INTERFACE FIFO it waits a shorter amount of time for the SIE to complete sending the first packet of data since they were working concurrently As soon as the first packet is sent by the SIE the second packet is immediately available to be sent by the SIE since the FIFO was already loaded by the MCU Also after the first packet is sent by the SIE the alternate FIFO is available for the MCU to load the third packet of 64 bytes of data With double buffering the MCU is able to always have a FIFO loaded and ready with data to be sent by the SIE when the host sends an IN token maximizing
274. ng on Ports A B C and D by pulling them up to Vpp with a weak external resistor 100KQ or by setting the csiop Direction register to output at run time for all unused inputs This will prevent the CMOS input buffers of unused input pins from drawing excessive current The csiop PMMR register definitions are shown in 144 through Table 146 page 219 uPSD34xx PSD MODULE Table 144 Power Management Mode Register PMMRO address csiop offset BOh Bit 0 Not used and should be set to zero APD Erabi EM Automatic Power Down APD counter is disabled nable APD counter is enabled Bit 2 x 0 Not used and should be set to zero PLD Turbo PLD Turbo mode is on Bit 1 Bit 3 Disable 1 off PLD Turbo mode is off saving power Blocking Bit CLKIN pin PD1 to the PLD Input Bus is not blocked Every transition of CLKIN ocKing Dit owers up the PLDs Bit4 PLDs CLKIN input to PLD Input Bus is blocked saving power But CLKIN still goes to APD X counter Blocking Bit on CLKIN input is not blocked from reaching all OMCs common clock inputs input is not blocked from CLKIN input is not blocked from reaching all OMCs common clock inputs all OMCs common clock inputs Bit 5 CLKIN to aA CLKIN input to common clock of all OMCs is blocked saving power But CLKIN still OMCs Only 1 Goes to APD counter and PLD logic besides the co
275. ns 41 6ns 30ns 25ns Note 1 Not compatible with High Speed 110 264 Operating Sequences The following pseudo code explains hardware control for these 2 functions on the uPSD34xx Initialize the Interface Function as Master Transmitter Function as Master Receiver Function as Slave Transmitter Function as Slave Receiver Interrupt Service Routine uPSD34xx INTERFACE Disable Master from returning an ACK SFR S1CON AA 0 Enable I2C SIOE SFR S1CON INI1 1 Transmit Address and R W bit 0 to Slave Is bus not busy 0 SFR S1STA BBUSY Full C code drivers for the uPSD34xx inter face and other interfaces are available from the web at www st com psm Initialization after a uPSD34xx reset Ensure pins P3 6 and P3 7 are GPIO in puts SFR P3 7 1 and SFR P3 6 1 Configure pins P3 6 and P3 7 as SFR P3SFS 6 1 and P3SFS 7 1 Set clock prescaler to determine SFR S1CON CR 2 0 desired SCL freq Set bus START condition sampling SFR 915 7 0 number of sam ples Enable individual I C interrupt and set priority SFR IEA I2C 1 SFR 2 1 if high priority is desired Set the Device address for Slave mode SFR S1ADR XXh desired address Enable SIOE ACK signal SFR 51 1 Master Transmitter Di
276. nship be tween the contents of S1SETUP and the resulting number of I C bus samples that SIOE will take af ter detecting the 1 0 0 transition on SDA of START condition Important Keep in mind that the time between samples is always 1 fosc The minimum START condition hold time ps is different for the three common speed categories per Table 61 page 109 Table 59 STSETUP START Condition Sample Setup register SFR DBh reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O EN SS SMPL_SET 6 0 Details Bit Symbol R W Function Enable Sample Setup EN SS 1 will force the SIOE to sample a START condition on the bus d 88 RAW the number of times specified in SMPL_SET 6 0 SS 0 means the SIOE will sample a START condition only one time regardless of the contents of SMPL SET 6 0 Sample Setting an SMPL_SET _ 6 0 Specifies the number of bus samples taken during START condition See Table 60 for values Note 1 Sampling SCL and SDA lines begins after 1 to 0 transition on SDA occurred while SCL is high Time between samples is 1 fosc 108 264 uPSD34xx INTERFACE Table 60 Number of 12 Bus Samples Taken after 1 to 0 Transition on SDA START Condition Contents of STSETUP Resulting value for STSETUP ot Eus SS EN bit SMPL SET 6 0 After 1 10 on ine 0 XX
277. nterrupt flag 0 RI RW Causes interrupt at end of 8th bit time when receiving in Mode 0 or halfway through stop bit reception in other modes see SM2 for exception Must clear this flag with firmware 84 264 uPSD34xx SERIAL UART INTERFACES Table 48 SCON1 Serial Port UART1 Control Register SFR D8h reset value 00h SMO SM1 SM2 REN TB8 RB8 Tl RI Details Bit Symbol R W Definition 7 SMO RW Serial Mode Select See Table 46 page 83 Important notice bit order of SMO and SM1 SMO SM1 00b Mode 0 6 SM1 0 1 01b Mode 1 SMO SM1 10b Mode 2 SMO SM1 11b Mode 3 Serial Multiprocessor Communication Enable Mode 0 SM2 has no effect but should remain 0 5 SM2 RW Mode 1 If SM2 0 then stop bit ignored SM2 1 then RI active if stop bit 1 Mode 2 and 3 Multiprocessor Comm Enable If SM2 0 9th bit is ignored If SM2 1 RI active when 9th bit 1 Receive Enable 4 REN RW If RENZO UART reception disabled If REN 1 reception is enabled TB8 is assigned to the 9th transmission bit in Mode 2 and 3 Not used in 3 TBS FUN Mode 0 and 1 Mode 0 RB8 is not used 2 RB8 RW Mode 1 If SM2 0 the is the level of the received stop bit Mode 2 and 3 RB8 is the 9th data bit that was received in Mode 2 and 3 Transmit Interrupt flag 1 TI RW Causes interrupt at end of 8th bit time when transmitting in Mode 0 or at beginning of stop bit transmission in other m
278. ntire SPI Interface is disabled 1 Entire SPI Interface is enabled Slave Selection 3 SSEL RW 0 SPISEL output pin is constant logic 1 slave device not selected 1 SPISEL output pin is logic 0 slave device is selected during data transfers First LSB FESB RW 0 Transfer the most significant bit MSB first 1 Transfer the least significant bit LSB first Sampling Polarity 0 Sample transfer data at the falling edge of clock SPICLK is 0 when 1 SPO idle 1 Sample transfer data at the rising edge of clock SPICLK is 1 when idle 0 Reserved 120 264 ky uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE Table 64 SPICON1 SPI Interface Control Register 1 SFR D7h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEIE RORIE TIE RIE Details Bit Symbol R W Definition 7 4 Reserved Transmission End Interrupt Enable 5 TES ayy 0 Disable Interrupt for Transmission End 1 Enable Interrupt for Transmission End Receive Overrun Interrupt Enable HORIE RW 0 Disable Interrupt for Receive Overrun 1 Enable Interrupt for Receive Overrun Transmission Interrupt Enable 1 RW 0 Disable Interrupt for SPITDR empty 1 Enable Interrupt for SPITDR empty Reception Interrupt Enable 2 RIE RW 0 Disable Interrupt for SPIRDR full 1 Enable Interrupt for SPIRDR full Table 65 SPICLKD SPI Prescaler Clock Divider Register SFR D2h Reset Value 04h
279. nts 3 1 PRSIN R W and 4 Access to the double buffered FIFOs is through Endpoint3 s IN FIFO Setting this bit enables double buffering of the IN FIFOs for Endpoints 1 0 PR1IN R W and 2 Access to the double buffered FIFOs is through Endpoint1 s IN FIFO 135 264 uPSD34xx USB INTERFACE USB Interrupts There are many USB related events that generate an interrupt The events that generate an interrupt are selectively enabled through the use of the USB Interrupt Enable Reg isters All USB interrupts are serviced through a single interrupt vector see INTERRUPT SYSTEM page 41 for the address of the interrupt vector When a USB interrupt occurs firmware must check the USB Interrupt Flag Registers to determine the source of the interrupt clear that in terrupt flag and process the interrupt before return ing to the interrupted code The USB interrupt priority can be set to low or high For the best USB response time and to max imize data transfer times the USB interrupt should be set to the highest priority see the INTERRUPT SYSTEM for the details on setting the interrupt pri ority USB Reset Interrupt The host signals a bus reset by driving both D and D low for at least 10ms When the uPSD34xx s SIE detects a reset on the USB it generates the RST interrupt request When a USB reset is detected the USB SIE is reset A USB reset does not reset the CPU USB Suspend Interrupt If the uPSD3
280. odes Must clear flag with firmware Receive Interrupt flag 0 RI RW Causes interrupt at end of 8th bit time when receiving in Mode 0 or halfway through stop bit reception in other modes see SM2 for exception Must clear this flag with firmware 85 264 uPSD34xx SERIAL UART INTERFACES UART Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate fosc 12 The baud rate in Mode 2 depends on the value of the bit SMOD in the SFR named PCON If SMOD 0 default value the baud rate is 1 64 the oscil lator frequency fosc If SMOD 1 the baud rate is 1 32 the oscillator frequency Mode 2 Baud Rate 25 64 x fosc Baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator bits The Timer 1 Interrupt should be disabled in this application The Timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applica tions it is configured for timer operation in the Auto reload Mode high nibble of the SFR TMOD 0010B In that case the baud rate is given by the formula Mode 1 3 Baud Rate 25 39 x fosc 12 x 256 TH1 Table 49 lists various commonly used baud rates and how they can be obtained from Timer 1 Using Timer Counter 2 to Generate Baud
281. of these two memories since stack accesses are al ways done using indirect addressing the bound ary between DATA and IDATA does not exist with regard to the stack SFR Memory Special Function Registers Table 5 page 25 occupy a separate physical memory but they logically overlap the same 128 bytes as IDATA ranging from address 0x0080 to OxOOFF SFRs are accessed only using direct addressing There 86 active registers used for many functions changing the operating mode of the 8032 MCU core controlling 8032 peripherals controlling and managing interrupt functions The remaining unused SFRs are reserved and should not be ac cessed 16 of the SFRs are both byte and bit addressable Bit addressable SFRs are those whose address ends in O or 8 hex External Memory PSD Module Program memory Data memory The PSD Module has four memories main Flash secondary Flash SRAM and csiop See the PSD MODULE section for more detailed information on these memories Memory mapping in the PSD Module is imple mented with the Decode PLD DPLD and option ally the Page Register The user specifies decode equations for individual segments of each of the memories using the software tool PSDsoft Ex press This is a very easy point and click process allowing total flexibility in mapping memories Ad ditionally each of the memories may be placed in various combinations of 8032 program address space or 8032 data addres
282. og phase locked loop PLL that can be config ured to generate the 48MHz USB clock on a wide range of fosc frequencies The USB CLK must be at 48MHz for the USB to function proper ly The PLL is enabled after power up The power on lock time for the PLL clock is about 200us and the firmware should wait that much time before en abling the USB by setting the USBCE Bit in the CCONO Register to 1 The PLL is disabled in Power down mode it can also be disabled or en abled by writing to the PLLEN Bit in the CCONO Register The PLL output clock frequency can be determined by using the following formula PLLD 2 x 2 where PLLM and PLLD are the multiplier and divi sor that are specified in the CCON1 Register The fosc the PLLM and PLLD range must meet the following conditions to generate a stable USB CLK a 1 lt x30 binary 11111 lt PLLM 4 0 lt 11110 b 1 lt PLLD lt 14 binary 1111 lt PLLD 3 0 1110 and C fosc PLLD 2 must be equal to or greater than 3MHz The USB requires a 48MHz clock to operate cor rectly The PLLM 4 0 and PLLD 3 0 values must be selected so as to generate a USB CLK that is as close to 48MHz as possible at different oscilla tor frequencies fosc Table 21 page 48 lists some of the PLLM and PLLD values that can be used on common fosc frequencies 47 264 uPSD34xx MCU CLOCK GENERATION Table 21 PLLM and PLLD Values f
283. ok up tables that are embedded in pro gram memory The final address produced by this mode is the result of adding either the 16 bit PC or DPTR value to the contents of the accumulator The value in the accumulator is referred to as an index The data fetched from the final location in program memory is stored into the accumulator overwriting the index value that was previously stored there For example MOVC A A DPTR Move code byte relative to DPTR into accumulator MOVC A A PC Move code byte relative to PC into accumulator Relative Addressing This mode will add the two s compliment number stored in the second byte of the instruction to the program counter for short jumps within 128 or 127 addresses relative to the program counter This is commonly used for looping and is very effi cient since no additional bus cycle is needed to fetch the jump destination address For example SJMP 34h Jump 34h bytes ahead in program memory of the address at which the SJMP instruction is stored If SJMP is at 1000h program execution jumps to 1034h 32 264 Absolute Addressing This mode will append the 5 high order bits of the address of the next instruction to the 11 low order bits of an ACALL or AJUMP instruction to produce a 16 bit jump address The jump will be within the same 2K byte page of program memory as the first byte of the following instruction For example AJMP 0500h If next instruction is loc
284. ol USB Status 00 EF F1 USEL UCON DIR ENABLE EP 2 0 STALL TOGGLE BSY USB 00 Endpoint Select USB 00 Endpoint Control 133 264 uPSD34xx USB INTERFACE F4 F5 UBASEL USCI BASEADDR 7 6 SFR SFR Bit Name and Bit Address Addr Name Value Comment hex 7 6 5 4 3 2 1 hex USB FIFO F2 USIZE SIZE 6 0 00 Valid Size USB Base UBASEH BASEADDR 15 8 00 Address USCI 2 0 High USB Base Address Low Setup 00 Command Setup F6 USCV USCV 7 0 00 Command Value Note Note Bits marked with a are Reserved 134 264 ky USB Device Address Register Initially when a device is connected to the USB it responds to the host on address 0 Using the Set_Address re quest the host assigns a unique address to the device The firmware writes this address to the USB Device Address register see Table 70 and subsequently the SIE only responds to transac tions on that assigned address This assigned ad dress is in effect until the device or an upstream hub is disconnected from the USB the host issues a USB Reset or the host shuts down The address register is cleared with a Hardware RESET or a USB RESET uPSD34xx USB INTERFACE Endpoint FIFO Pairing Endpoint FIFOs can be paired for double buffering to provide an efficient method for bul
285. olerant If the alternate function is the related pins will be in open drain mode which is just like quasi bi directional mode but the high side driver is not en abled for one cycle when outputting O to 1 transition Only the low side driver and the internal weak pull ups are used Only Port 3 supports open drain mode Figure 18 page 57 1 re quires the use of an external pull up resistor on each bus signal typically 4 7KQ to Vcc If the alternate function is PCA output then the re lated pins are in push pull mode meaning the pins are actively driven and held to logic 1 by the high side driver or actively driven and held to logic 0 by the low side driver Only Port 4 supports push pull mode Figure 19 page 58 Port 4 push pull pins can source current when driving logic 1 and sink current when driving logic 0 This current is significantly more than the capability of pins on Port 1 or Port 3 see Table 156 page 238 For example to assign these port functions m Port 1 UART1 ADC 1 0 P1 7 4 are GPIO m Port 3 UARTO 12 P3 5 2 are GPIO m Port 4 TCMO SPI P4 3 1 are GPIO The following values need to be written to the SFRs 15 50 00001111b or OFh P1SFS1 0000001 1b or 03h P3SFS 1100001 1b or C3h PASFSO 11110001b or Fih P4SFS1 11110000b or FOh uPSD34xx I O PORTS of MCU MODULE Table 30 P3SFS Port 3 Special Function Select Register SFR 91h re
286. ollowing three events occur 1 SIOE in Slave mode receives an address that matches contents of S1ADR register 2 data byte has been received while SIOE is in Master Receiver mode 3 A data byte has been received while SIOE is a selected Slave Receiver When AA 0 no acknowledge is returned high on SDA during acknowl edge bit time These bits along with bit CR2 determine the SCL clock frequency fsc when SIOE is in Master mode These bits create a clock divisor for fosc See Table 55 for values 3 103 264 uPSD34xx INTERFACE Table 55 Selection of the SCL Frequency in Master Mode based on fosc Examples Bit Rate kHz fosc Note 1 These values are beyond the bit rate supported by uPSD34xx 104 264 CR2 CR1 CRO _ fosc Divided by 12MHz fosc 24MHz fosc 36MHz fosc 40MHz fosc 0 0 0 32 375 0 0 1 48 250 0 1 0 60 200 400 66 0 1 1 120 100 200 300 333 1 0 0 240 50 100 150 166 1 1 0 960 12 5 25 37 5 41 1 1 1 1920 6 25 12 5 18 75 20 Interface Status Register S1STA The S1STA register provides status regarding im mediate activity and the current state of operation on the bus All bits in this register are read only except bit 5 INTR which is the interrupt flag Interrupt Conditions If the 12 interrupt is en abled 1 in SFR named IEA and EA 1 SFR named IE and the SIOE is initialized then an interrupt is automatic
287. on that branch con tinues with minimal delay This greatly reduces the chance that the MCU will stall from an empty PFQ and improves performance in embedded control systems where it is quite common to branch and loop in relatively small code localities By default the PFQ and BC are enabled after power up or reset The 8032 can disable the PFQ and BC at runtime if desired by writing to a specific SFR BUSCON The memory in the PSD module operates with variable wait states depending on the value spec ified in the SFR named BUSCON For example a uPSD34xx device operating at a 40MHz crystal frequency requires four memory wait states equal to four MCU clocks In this example once the PFQ has one word of code the wait states be come transparent and a full 10 MIPS is achieved when the program stream consists of sequential one or two byte one machine cycle instructions as shown in Figure 7 page 19 transparent be cause a machine cycle is four MCU clocks which equals the memory pre fetch wait time that is also four MCU clocks But it is also important to under stand PFQ operation on multi cycle instructions 20 264 PFQ Example Multi cycle Instructions Let us look at a string of two byte two cycle in structions in Figure 9 page 21 There are three instructions executed sequentially in this example instructions A B and C Each of the time divisions in the figure is one machine cycle of four clocks and there are s
288. ong with the device Figure 50 USB Packets in a USB Transfer Example our ADDR ENDP CRC5 Token Packet OUT ADDR ENDP CRC5 Payload CRC16 Data ACK Data Packet Handshake Packet Payload Data Token Packet 126 264 Data Packet Al10489 Data Transfers with the Host The host issues OUT tokens followed by Data Tokens to send data to a device The device responds with an appropri ate handshake packet indicating whether it was able to receive the data If the de vice does not receive the data packet OK be cause there is some error it does not respond with a handshake packet In the case of a NAK or no response the host retries sending the data ata later time USB devices are not able to send data to a host whenever they have it ready When a device has data ready it loads data into its endpoint buffer making it ready for a transfer The data will remain in the buffer until the host issues an IN token to that device s endpoint at which time the data will be sent If the host receives the data OK it follows with an ACK handshake a host never NAKs If the host did not receive the data OK there is no handshake packet In this case the device should reload its endpoint buffer as appropriate and the host will retry again later to retrieve the data Types of Transfers The USB specification defines four types of trans fers Bulk Interrupt Isochronous and Con
289. onics uPSDS34xx devices are erased meaning all Flash memory and PLD configuration bits are logic 1 Firmware and PLD logic configu ration must be programmed at least the first time using JTAG ISP Subsequent programming of Flash memory may be performed using JTAG ISP JTAG debugging or the 8032 may run firmware to program Flash memory IAP AC DC PARAMETERS These tables describe the AD and DC parameters of the uPSD34xx Devices DC Electrical Specification AC Timing Specification PLD Timing Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input Macrocell Timing MCU Module Timing READ Timing WRITE Timing Power down and RESET Timing uPSD34xx AC DC PARAMETERS The following are issues concerning the parame ters presented In the DC specification the supply current is given for different modes of operation The AC power component gives the PLD Flash memory and SRAM mA MHz specification Figure 96 and Figure 97 show the PLD mA MHz as a function of the number of Product Terms PT used In the PLD timing parameters add the required delay when Turbo Bit is 0 Figure 96 PLD Icc Frequency Consumption 5V range mA HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS MHz 15 20 25 102894 60 50 40 mA 30 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS MHz
290. or Different fosc Frequencies fosc PLLM 4 0 PLLD 3 0 fusB CLK MHz decimal binary decimal MHz 40 0 22 10110 48 0 33 0 30 9 30 0 14 3 24 0 18 3 16 0 3 12 0 2 8 0 0 6 0 30 11110 0 0000 48 0 3 0 30 11110 1 1111 48 0 Figure 14 Clock Generation Logic PCON 1 PD PCON 2 0 CPUPS 2 0 PCON O IDL Power Down Mode Clock Pre Scaler Select XTAL1 default XTAL1 2 Clock Divider gt PCON 1 CCONO 6 to TIMERO 1 2 UARTO 1 1 SPI 2 ADC Idle Mode MCU CLK fMCU to 8032 WDT CLK fosc USB CLK 110433 48 264 uPSD34xx MCU CLOCK GENERATION Table 22 CCONO Clock Control Register SFR F9h reset value 50h PLLM 4 PLLEN UPLLCE DBGCE CPUAR CPUPS 2 0 Details Bit Symbol R W Definition 7 PLLM 4 R W Upper bit of the 5 bit PLLM 4 0 Multiplier Default 0 for 001 PLL Enable 6 PLLEN R W 0 Disable PLL operation 1 Enable PLL operation Default condition after reset USB Clock Enable 5 UPLLCE RW 0 USB clock is disabled Default condition after reset 1 USB clock is enabled Debug Unit Breakpoint Comparator Enable 4 DBGCE RW 0 JTAG Debug Unit comparators are disabled 1 JTAG Debug Unit comparators are enabled Default condition after reset Automatic MCU Clock Recovery 3 CPUAR RW 0 There is no change of CPUPS 2 0 when
291. orts on the PSD Module Port A 80 pin device only Port B Port C and Port D Ports A and B are eight bits each Port C is four bits and Port D is two bits for 80 pin devices or 1 bit for 52 pin devices Each port pin is individually configurable thus allowing multiple functions per port The ports are config ured using PSDsoft Express then programming with JTAG and also by the 8032 writing to csiop registers at run time Topics discussed in this section are m General Port architecture m Port Operating Modes m Individual Port Structure General Port Architecture The general archi tecture for a single I O Port pin is shown in Figure 80 page 200 Port structures for Ports A B C and D differ slightly and are shown in Figure 85 page 212 though Figure 88 page 217 Figure 80 page 200 shows four csiop registers whose outputs are determined by the value that the 8032 writes to csiop Direction Drive Control and Data Out The I O Port logic contains an out put mux whose mux select signal is determined by PSDsoft Express and the csiop Control register bits at run time Inputs to this output mux include the following 1 Data from the csiop Data Out register for MCU output mode All ports 2 Latched de multiplexed 8032 Address for Address Output mode Ports A and B only 3 Peripheral I O mode data bit Port A only 4 GPLD ONC output Ports A B and C The Port Data Buffer PDB provides fee
292. ossible only when the 8032 MCU is operating below approximately one MIPS of performance Above one MIPS the program will not run real time while tracing One MIPS performance is determined by the combination of choice for MCU clock frequency and the bit settings in SFR registers BUSCON and CCONO Breakpoints can optionally halt the MCU and or assert the external Debug Event pin Breakpoint definitions may be qualified with read or write operations and may also be qualified with an address of code SFR DATA IDATA or XDATA memories Three breakpoints will compare an address but the fourth breakpoint can compare an address and also data content Additionally the fouth breakpoint can be logically combined AND OR with any of the other three breakpoints The Debug Event pin can be configured by the PC host to generate an output pulse for external triggering when a break condition is met The pin can also be configured as an event input to the breakpoint logic causing a break on the falling edge of an external event signal If not used the Debug Event pin should be pulled up to Vcc as described in the section Debugging the 8032 MCU Module page 232 The duration of a pulse generated when the Event pin configured as an output is one MCU clock cycle This is an active low signal so the first edge when an event occurs is high to low The clock to the Watchdog Timer ADC and interface are not stopped by a breakpoint
293. outed through IMCs before reaching the PLD in put bus Inputs to the PLDs from Port D do not pass through IMCs but route directly to the PLD input bus Pins on Ports A B and C can serve as outputs from GPLD OMCs and Port D pins can be outputs from the DPLD external chip selects which do not consume OMCs Whenever a pin is specified to be a PLD output it cannot be used for MCU I O mode or other pin modes If a pin is specified to be a PLD input it is still possible to read the pin using MCU input mode with the csiop register Data In Also the csiop Direction register can still affect a pin which is used for a PLD input The csiop Data Out regis ter has no effect on a PLD output pin Each pin on Ports A B C and D have a tri state buffer at the final output stage The Output Enable signal for this buffer is driven by the logical OR of two signals One signal is an Output Enable signal generated by the AND OR array from an oe equation specified in PSDsoft and the other sig nal is the output of the csiop Direction register This logic is shown in Figure 80 page 200 At power on all port pins default to high impedance input Direction registers default to 00h However if an equation is written for the Output Enable that is active at power on then the pin will behave as an output PLD equations are specified in PSDsoft Ex press and programmed into the uPSD using JTAG Figure 81 shows a very simple combinato
294. pecify an address range for either Figure 84 Peripheral I O Mode 8032 RD VM REGISTER BIT 7 PIO EN 8032 WR 3 BUS DO D7 DE MUXED uPSD34xx PSD MODULE PSELO or PSEL1 Always qualify the PSELx equa tion with PSEN is logic 1 to ensure Peripheral 1 O mode is only active during 8032 data cycles not code cycles Only one equation is needed since PSELx signals are OR ed together Figure 84 Then in the 8032 initialization firmware a logic 1 is written to the csiop VM register Bit 7 PIO EN as shown in Table 99 page 163 After this Port A will automatically perform this repeater function whenever the 8032 presents an address and memory page number if paging is used that is within the range specified by PSELx Once Port A is designated as Peripheral I O mode in PSDsoft Express it cannot be used for other functions Note The user can alternatively connect an exter nal parallel peripheral to the standard 8032 ADO AD7 pins on an 80 pin uPSD device not Port A but these pins have multiplexed address and data signals with a weaker fanout drive capability PAO PA7 8032 DATA Al02886A 209 264 uPSD34xx PSD MODULE JTAG ISP Mode Four of the pins on Port C are based on the IEEE 1149 1 JTAG specification and are used for In System Programming ISP of the PSD Module and debugging of the 8032 MCU Module These pins TDI TDO TMS TCK are dedicated to JTAG and cannot be use
295. pose Programmable Logic 16 Macrocells 8 10 bit ADC 8 GPIO Port 1 qup tn in i 4 gt 4 Optional IrDA Encoder Decoder MARTE m SPI 16 bit PCA 6 PWM CAPCOM TIMER 8 GPIO Port 4 qu E USB v2 0 10 M E ES 8 264 1st Flash Memory 64K 128K or 256K Bytes 2nd Flash Memory 32K Bytes SRAM 4K 8K or 32K Bytes 8 GPIO Port A 80 pin only 8 GPIO Port B 2 GPIO Port D 4 GPIO Port C Supervisor Watchdog and Low Voltage Reset Dedicated Pins Al09695b uPSD34xx PIN DESCRIPTIONS PIN DESCRIPTIONS Figure 3 TQFP52 Connections 40 P1 6 SPITXD ADC6 1 42 PB7 T 41 P1 7 SPISEL ADC7 47 150 2 49 PB3 1 48 PB4 46 45 GND 44 RESET IN 43 PB6 o tn N E L 51 PB1 PD1 CLKIN 1 39 P1 5 SPIRXD ADC5 PC7 2 38 P1 4 SPICLK 2 ADC4 JTAG 3 37 P1 3 TXD1 IrDA 2 ADC3 TDI 4 36 P1 2 RXD1 IrDA 2 ADC2 DEBUG 5 35 P1 1 T2X 2 ADC1 3 3V Vec 6 34 P1 0 T2 2 ADCO USB 7 33 vyg Vpop 8 32 XTAL2 GND 9 31 XTAL1 USB 10 30 P3 7 SCL 2 11 29 P3 6 SDA JTAG TCK 12 28 P3 5 C1 JTAG TMS 13 27 P3 4 CO Uru L LILILI LI LI LI LI LE UUU UU O O O s AOAO rrr QN QN QN QN 4 4 4 20 nnn
296. r type All USB devices are required to implement a de fault control method that uses both the input and output endpoints with Endpoint zero The USB System Software uses this default control method to initialize and generically manipulate the logical device as the Default Control Pipe Endpoint zero is always accessible and provides access to the device s configuration and status information as well as some basic control access Additional non zero endpoints provide the com munication flow required for the functionality of the device The non zero endpoints are available for use only after the device is configured per the nor mal device configuration process see Chapter 9 of the USB specification http www usb org 125 264 uPSD34xx USB INTERFACE Packets USB transactions consist of data pack ets that contain special codes called Packet IDs PIDs A PID signifies the kind of packet that is being transmitted While there are more types of PIDs in a USB system the 5034 responds to the three types shown in Table 67 Table 67 Types of Packet IDs PID Type PID Name Token IN OUT SETUP Data DATAO DATA1 Handshake ACK NAK STALL Figure 50 shows an example of packets sent dur ing a USB transfer The first packet is a Token Packet with an OUT PID The OUT PID indicates that the host is going to send data to the ad dressed device s endpoint The ADDR field con tains the address of the device
297. r types main Flash 64K 128K or 256K bytes a smaller secondary Flash 32K SRAM 4K 8K or 32Kbytes and a block of PSD Module control registers called csiop 256 bytes These external memories reside at programmable address rang es specified using the software tool PSDsoft Ex press See the PSD Module section of this document for more details on these memories External memory is accessed by the 8032 in two separate 64K byte address spaces One address space is for program memory and the other ad Figure 6 uPSD34xx Memories Internal SRAM on MCU Module Fixed Addresses 384 Bytes SRAM Indirect 128 Bytes Addressing IDATA SFR Direct go 128 Bytes Addressing 128 Bytes DATA Direct or Indirect Addressing 16 264 dress space is for data memory Program memory is accessed using the 8032 signal PSEN Data memory is accessed using the 8032 signals RD and WR If the 8032 needs to access more than 64K bytes of external program or data memory it must use paging or banking techniques provided by the Page Register in the PSD Module Note When referencing program and data mem ory spaces it has nothing to do with 8032 internal SRAM areas of DATA IDATA and SFR on the MCU Module Program and data memory spaces only relate to the external memories on the PSD Module External memory on the PSD Module can overlap the internal SRAM memory on the MCU Module in the same physical address range startin
298. rate However SFRS RCAP2H and RCAP2L may be read but should not be written because a write might overlap a reload and cause write and or reload errors Timer 2 should be turned off clear TR2 before accessing Timer 2 or Registers RCAP2H and RCAP2L in this case Table 45 page 80 shows commonly used baud rates and how they can be obtained from Timer 2 with T2CON 34h 79 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Table 45 Commonly Used Baud Rates Generated from Timer2 T2CON 34h Timer 2 SFRs fosc MHz Desired Resulting Baud Rate Baud Rate RCAP2H hex RCAP2L hex Baud Rate Deviation 40 0 115200 FF F5 113636 1 36 40 0 FF EA 56818 1 36 40 0 40 0 40 0 36 864 115200 115200 36 864 57600 57600 36 864 28800 28800 36 864 36 864 36 0 36 0 9600 24 0 19200 12 0 9600 9615 11 0592 115200 115200 11 0592 0 11 0592 0 11 0592 0 3 6864 115200 115200 0 3 6864 57600 57600 0 3 6864 28800 28800 0 3 6864 0 3 6864 0 1 8432 0 80 264 ky uPSD34xx STANDARD 8032 TIMER COUNTERS Figure 28 Timer 2 in Capture Mode T2 pin Timer 2 Interrupt Transition Detector T2X pin Control EXEN2 106625 Figure 29 Timer 2 Auto Reload Mode T2 pin Timer 2 Interrupt Transition Detector T2X pin Control EXEN2 106626 81 264 uPSD34xx STANDARD 8032 TIMER COUNTERS Figure 30 Timer 2 in Baud Ra
299. rbo Plus Series PRELIMINARY DATA Figure 1 Packages TQFP80 U 80 lead Thin Quad Flat COMMUNICATION INTERFACES USB v2 0 Full Speed 12Mbps 10 endpoint pairs In Out each endpoint with 64 byte FIFO supports Control Intr and Bulk transfer types C Master Slave controller 833kHz SPI Master controller 1MHz Two UARTs with independent baud rate IrDA Potocol up to 115 kbaud Upto 46 I O 5V tolerant uPSD34xxV TIMERS AND INTERRUPTS Three 8032 standard 16 bit timers Programmable Counter Array PCA six 16 bit modules for PWM CAPCOM and timers 8 10 16 bit PWM operation 12 Interrupt sources with two external interrupt pins OPERATING VOLTAGE SOURCE 10 5V Devices 5 0V and 3 3V sources 3 38V Devices 3 3V source Rev 3 0 1 264 uPSD34xx FEATURES SUMMARY Table 1 Device Summary Part Number Max MHz En Pkg bytes uPSD3422E 40T6 40 64K TQFP52 uPSD3422EV 40T6 32K 3 3V uPSD3422E 40U6 32K TQFP80 uPSD3422EV 40U6 32K TQFP80 uPSD3433E 40T6 32K TQFP52 uPSD3433EV 40T6 32K TQFP52 uPSD3433E 40U6 32K TQFP80 uPSD3433EV 40U6 32K TQFP80 uPSD3434E 40T6 32K TQFP52 uPSD3434EV 40T6 32K TQFP52 uPSD3434E 40U6 32K TQFP80 uPSD3434EV 40U6 32K TQFP80 uPSD3454E 40T6 32K TQFP52 uPSD3454EV 40T6 32K TQFP52 uPSD3454E 40U6 32K 5 0V uPSD3454EV 40U6 40 256K 32K 32K 46 Yes 3 3v 3 3v TQFP80 Note Operating temperature
300. rder to ac cess a different sector within that same Flash array then resume the erase later After a Flash memory array is programmed or erased it will go to Read Array mode then the 8032 can read from Flash memory just as it would read from any ROM or SRAM device 178 264 Flash Memory Instruction Sequences An struction sequence consists of a sequence of spe cific byte WRITE and byte READ operations Each byte written to either Flash memory array on the PSD Module is received by a state machine inside the Flash array and sequentially decoded to exe cute an embedded algorithm The algorithm is ex ecuted when the correct number of bytes are properly received and the time between two con secutive bytes is shorter than the time out period of 80us Some instruction sequences are struc tured to include READ operations after the initial WRITE operations An instruction sequence must be followed exactly Any invalid combination of instruction bytes or time out between two consecutive bytes while ad dressing Flash memory resets the PSD Module Flash logic into Read Array mode where Flash memory is read like a ROM device The Flash memories support instruction sequences summa rized in Table 107 page 179 Program a Byte Unlock Sequence Bypass Erase memory by array or by sector Suspend or resume a sector erase m Reset to Read Array mode The first two bytes of an instruction sequence are 8032 bus WRITE operations to un
301. rdware after firmware services EXTINTO interrupt Trigger type for external interrupt pin EXTINTO 1 falling edge 0 low 0 ITO RW level 72 264 uPSD34xx STANDARD 8032 TIMER COUNTERS SFR TCON Timer 0 and Timer 1 share the SFR TCON that controls these timers and provides information about them See Table 41 page 72 Bits IEO and IE1 are not related to Timer Counter functions but they are set by hardware when a signal is active on one of the two external interrupt pins EXTINTO and EXTINT1 For system informa tion on all of these interrupts see Table 16 page 42 Interrupt Summary Bits ITO and IT1 are not related to Timer Counter functions but they control whether or not the two external interrupt input pins EXTINTO and are edge or level triggered SFR TMOD Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD Table 42 Timer 0 and Timer 1 Operating Modes The Timer or Counter function is selected by the C T control bits in TMOD The four operating modes are selected by bit pairs M 1 0 in TMOD Modes 0 1 and 2 are the same for both Timer Counters Mode 3 is different Mode 0 Putting either Timer Counter into Mode 0 makes it an 8 bit Counter with a divide by 32 pre scaler Figure 25 shows Mode 0 operation as it ap plies to Timer 1 same applies to Timer O In this mode the Timer Register is configured as a 13 bit regi
302. reset command The Watch Dog Timer WDT has timed out The resulting internal reset signal RESET will force the 8032 into a known reset state while asserted and then 8032 program execution will jump to the reset vector at program address 0000h just after MCU RESET is deasserted The MCU Module will also assert an active low internal reset signal RESET to the PSD Module If needed the signal RESET can be driven out to external sys tem components through any PLD output pin on the PSD Module When driving this Figure 23 Supervisor Reset Generation PULL UP RESET_IN JTAG Debug DELAY R tRST_ACTV uPSD34xx SUPERVISORY FUNCTIONS RESET_OUT signal from a PLD output the user can choose to make it either active high or active low logic depending on the PLD equation External Reset Input Pin RESET_IN The RESET_IN pin can be connected directly to a mechanical reset switch or other device which pulls the signal to ground to invoke a reset RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage hystere sis of Vast_Hys for immunity to the effects of slow signal rise and fall times as shown in Figure 23 RESET IN is also filtered to reject a voltage spike less than a duration of rii The RESET IN signal must be maintained at a logic O for at least a duration of tasr 10 iN while the oscillator is run ning The resulting MCU RESET signa
303. ress and some by the 8032 writing to the csiop registers at run time and some require both For example PLD I O Latched Address Out and Peripheral I O modes must be defined in PSDsoft Express and programmed into the device using JTAG but an additional step must happen at run time to activate Latched Ad dress Out mode and Peripheral I O mode but not needed for PLD I O In another example MCU I O mode is controlled completely by the 8032 at run time and only a simple pin name declaration is needed in PSDsoft Express for documentation Table 116 page 197 summarizes what actions are needed in PSDsoft Express and what actions are required by the 8032 at run time to achieve the various port functions 199 264 uPSD34xx PSD MODULE Figure 80 Detail of a Single I O Port typical of Ports A B C 1 1 FROM ARRAY yy PT OUTPUT ENABLE GE DEED uo POE 1 1 FROM PLD INPUT BUS ee i DIRECTION PERIPHERAL i MODE SETS DIRECTION i y PORT A ONLY i 1 1 8032 DRIVE DRIVE TYPE DATA BITS E Wy 1 1 1 e 8032 CONTROL m WA i 22 OUTPUT ENABLE MCUI O 2 OUT B 1 P 1 LR OUTPUT 1 qj S LATCHED ADDR PORT A or B DRIVER KA o gt gt E D BIT PERIPH I O MODE Port A TYPICAL 1 8 7 DIRECTION PORT 8032 m 8 pata P BIT PERIPH lt lt 4 D
304. ress Output mode will drive individual demuxed address signals on pins of Ports A or B Port pins can be designated for this function on a pin by pin basis meaning that an en tire port will not be sacrificed if only a few address signals are needed To activate this mode the desired pins on Port A or Port B are designated as Latched Address Out in PSDsoft Then in the 8032 initialization firm ware a logic 1 is written to the csiop Control reg ister for Port A or Port B in each bit position that corresponds to the pin of the port driving an ad dress signal Table 134 and Table 135 define the csiop Control register locations and bit assign ments The latched low address byte A4 A7 is available on both Port A and Port B The high address byte A8 A15 is available on Port B only Selection of high or low address byte is specified in PSDsoft Express Table 134 Latched Address Output Port A Control Register address csiop offset 02h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO addr A7 addr addrA5 addr 4 Note 1 Port A not available on 52 pin uPSD34xx devices addr AddrA2 1 addr AO 2 For each bit 1 drive demuxed 8032 address signal on pin 0 pin is default mode MCU 3 Default state for register is after reset or power up Table 135 Latched Address Output Port B Control Register address csiop
305. ripherals ex cept the WDT The Frequency of PERIPH_CLK is always fosc Each of the peripherals can indepen dently divide PERIPH CLK to scale it appropriate ly for use PERIPH CLK runs at all times except when blocked by the PD bit in the SFR named PCON during MCU Power down Mode JTAG Interface Clock The JTAG interface for ISP and for Debugging uses the externally sup plied JTAG clock coming in on pin TCK This means the JTAG ISP interface is always available and the JTAG Debug interface is available when enabled even during MCU Idle mode and Power down Mode However since the MCU participates in the JTAG debug process and MCU CLK is halted during Idle and Power down Modes the majority of de bug functions are not available during these low power modes But the JTAG debug interface is ca pable of executing a reset command while in these low power modes which will exit back to normal 3 uPSD34xx MCU CLOCK GENERATION operating mode where all debug commands are available again The CCONO SFR contains a bit DBGCE which enables the breakpoint comparators inside the JTAG Debug Unit when set DBGCE is set by de fault after reset and firmware may clear this bit at run time Disabling these comparators will reduce current consumption on the MCU Module and it is recommended to do so if the Debug Unit will not be used such as in the production version of an end product USB_CLK The uPSD34xx has a dedicated ana l
306. rrupt Source flag 0 RISF R 0 Automatically resets to 0 when SPIRDR is empty after the SPIRDR is read 1 Automatically sets to 1 when SPIRDR is full 122 264 ky USB INTERFACE uPSD34xx devices provide a full speed USB Uni versal Serial Bus device interface The serial in terface engine SIE provides the interface between the CPU and the USB see Figure 49 Notes 1 For a list of known limitations of USB interface for UPSD34xx devices please refer to IMPOR TANT NOTES page 262 2 Please make sure you have the latest 3400 USB firmware The USB module supports the following features m USB 2 0 compliant to full speed mode 12 Mbps m 3 3V USB transceiver m Five endpoints including Control endpoint 0 Each endpoint includes two 64 byte FIFOs one for IN and one for OUT transactions Endpoints 1 through 4 support Interrupt and Bulk transfers m USB Bus Suspend detection and Resume generation m PLL Multiplier to generate the 48 MHz as required for USB support m Interrupts for various USB bus conditions m Performs NRZI encoding and decoding bit stuffing CRC generation and checking and serial parallel data conversion 3 uPSD34xx USB INTERFACE m Double buffering using FIFO pairing for efficient data transfer in Bulk transfer m Busy bit based FIFO status monitoring m FIFOs accessible via XDATA space The analog front end of the USB module is an on chip USB transceiver It is designed
307. rupt Polling Vector SFR bit position Source Priority Addr 1 Intr Pending 0 No Interrupt Flag Bit Auto Cleared by Hardware Enable Bit Name SFR bit position Intr Enabled Intr Disabled Priority Bit Name SFR bit position 1 High Priority 0 Low Priority External Edge Interrupt INTO 0003h IEO TCON 1 Levels 0 PXO 0 Timer 0 Overflow 000Bh TCON 5 ETO IE 1 IP 1 External Edge e Interrupt INT1 0013h IE1 TCON 3 Levels EX4 IE 2 PX1 IP 2 Timer 1 Overflow 001Bh TF1 TCON 7 Yes ET1 IE 3 PT1 IP 3 SCONO 0 UARTO ES 0023h ESO IE 4 PSO IP 4 Timer 2 TF2 T2CON 7 Overflow 6 002Bh No ET2 IE 5 PT2 IP 5 or TX2 Pin EXF2 T2CON TEISF RORISF SPI 7 0053h TISF RISF Yes ESPI IEA 6 PSPI IPA 6 SPISTAT 3 0 USB 8 0033h _ 1 No EUSB 0 PUSB 0 9 0043h INTR S1STA 5 Yes IEA 1 IPA 1 ADC 10 003Bh AINTF ACON 7 No EADC IEA 7 PADC IPA 7 OF Vx INTFx PCA 11 005Bh PCASTA 0 7 No EPCA IEA 5 PPCA IPA 5 RI SCON1 0 UART1 12 low 004Bh TI SCON1 1 No ES1 IEA 4 51 4 Note 1 See USB interrupt flag registers UIFO 3 42 264 uPSD34xx INTERRUPT SYSTEM Figure 13 Enabling and Polling Interrupts Interrupt Priority Sources IE IEA IP IPA Reserved Ext INTO Timer 0 Ext INT1 Timer 1 UARTO Timer 2 eouenbeg Buipjog
308. s F Vcc for MCU Vpp for PSD Device Module Module 5V uPSD34xx oo 3 3V uPSD34xxV iid dd 14 264 Ports 1 3 and 4 on MCU Module Ports A B C and D on PSD Module 3 3V Ports 3 and 4 are 5V tolerant 3 3V Ports 3 and 4 are 5V tolerant 5V 3 3V NOT 5V tolerant 3 Figure 5 Functional Modules Port 3 UARTO Intr Timers Port 3 Turbo 8032 Core 3 Timer Counters 256 Bye SRAM XTAL Clock Unit Dual UARTs Interrupt Dedicated Memory Interface Prefetch Branch Cache 8 Bit 16 Bit Die to Die Bus Decode PLD JTAG ISP uPSD34xx Port 4 PCA Port 1 Timer ADC SPI E PWM UART1 PCA PWM Counters 8032 Internal Bus Internal Reset Secondary Main Flash Flash PSD Internal Bus CPLD 16 MACROCELLS HARDWARE DESCRIPTION USB pins MCU Module USB and Trans ceiver PSD Module Vpp Pins 3 3V or 5V uPSD34xx s pue Port AB C PLD GPIO and GPIO 110409 y 15 264 uPSD34xx MEMORY ORGANIZATION MEMORY ORGANIZATION The 8032 MCU core views memory on the MCU module as internal memory and it views memory on the PSD module as external memory see Figure 6 Internal memory on the MCU Module consists of DATA IDATA and SFRs These standard 8032 memories reside in 384 bytes of SRAM located at a fixed address space starting at address 0x0000 External memory on the PSD Module consists of fou
309. s mit or receive Does status TX MODE 1 If Yes Master wants transmit mode Exit ISR indicate Master wants Slv Xmit mode If No Master wants Slave Recv mode dummy S1DAT read to release bus Exit ISR ready to data on next interrupt C Interrupt is from Slv receiving data from Mastr buf buffer index S1DAT read byte Exit ISR recv next byte on next interrupt uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE SPI SYNCHRONOUS PERIPHERAL INTERFACE uPSD34xx devices support one serial SPI inter face in Master Mode only This is a three or four wire synchronous communication channel capa ble of full duplex operation on 8 bit serial data transfers The four SPI bus signals are m SPIRxD Pin P1 5 or P4 5 receives data from the Slave SPI device the uPSD34xx m SPITxD Pin P1 6 or P4 6 transmits data from the uPSD34xx to the Slave SPI device m Pin P1 4 or P4 4 clock is generated from the uPSD34xx to the SPI Slave device m SPISEL Pin P1 7 or P4 7 selects the signal from the uPSD34xx to an individual Slave SPI device Figure 44 SPI Device Connection Examples This SPI interface supports single Master multi ple Slave connections Multiple Master connec tions are not directly supported by the uPSD34xx no internal logic for collision detection If more than one Slave device is required the SPISEL signal
310. s one method is by reading IMCs as de scribed here the other method is using MCU mode described in a later section 3 The optional IMC clocking or gating signal used to strobe pin inputs is driven by a product term from the AND OR array There is one clocking or gating product term available for each group of four IMCs Port inputs 0 3 are controlled by one prod uct term and 4 7 by another To specify in PSDsoft Express the method in which a signal will be strobed as it enters an IMC for a given input pin on Port A B or C just specify PT Clocked Register to use a rising edge to clock the incoming signal or specify PT Clock Latch to use an active high gate signal to latch the incoming signal Then de fine an equation for the IMC clock 10 or the IMC gate le signal in the I O Equations section If the user would like to latch an incoming signal using the gate signal ALE from the 8032 then in PSDsoft Express for a given input pin on Port A B or C specify Latched Address as the pin func tion If it is desired to pass an incoming signal through an IMC directly to the AND OR array inputs with out clocking or gating this is most common in PSDsoft Express simply specify Logic or Ad dress for the input pin function on Port A B or C 197 264 uPSD34xx PSD MODULE Figure 79 Detail of a Single IMC y FROM PORT o LOGIC m 8032 READ OF PARTICULAR CSIOP IMC REGISTER
311. s from receiving Slave da ta goto B A Interrupt is from Master sending addr to Slave ACK recvd from tus ACK_RESP 0 If No an ACK was not received 1CON STO 1 set STOP condition STOP occurs after ISR exit Slave sta dummy S1DAT read to release bus Exit ISR If Yes ACK was received then continue dummy S1DAT read to release bus Does Master want to receive just one data byte If Yes do not allow Master to ACK on next interrupt S1CON AA is already 0 Exit ISR now ready to one byte from Slv If No Master can ACK next byte from Slv S1CON AA 1 allow Master to send ACK Exit ISR now ready to data from Slave B Interrupt is from Master recving data from Slv buf buffer index S1DAT read byte uPSD34xx INTERFACE Is this the last data byte to receive from Slave If Yes tell Slave to stop transmitting S 1CON STO 1 set STOP bus condi tion lt STOP occurs after ISR exit gt Exit ISR finished receiving data from Slave If No continue Is this the next to last byte to re ceive from Slave If this is the next to last byte do not allow Master to ACK on next interrupt S1CON AA 0 don t let Master re turn ACK Exit ISR now ready to last byte from Slv If this is not next to last byte let Master se
312. s if desired but wired OR logic is not possible in CMOS output mode uPSD34xx PSD MODULE Figure 95 Example of Chaining uPSD34xx Devices JTAG CIRCUIT BOARD Device 1 JTAG Programming Optional OF Tes TERR Equipment Connects Here pHPSD34xx Device 2 IEEE 1149 1 Compliant Device Device N System Reset Circuitry uPSD34xx A110459 231 264 uPSD34xx PSD MODULE Debugging the 8032 MCU Module The 8032 on the MCU module may be debugged in circuit using the same four basic JTAG signals as used for JTAG ISP TDI TDO TCK TMS The signals TSTAT and TERR are not needed for debugging and they will not create a problem if they exist on the circuit board while debugging The same con nector specified in Figure 94 page 230 can be used for ISP or for 8032 debugging There are 3rd party suppliers of uPSD34xx JTAG debugging equipment check www st com psm These are small pods which connect to a PC or notebook computer using a USB interface and they are driven by an 8032 Integrated Development Envi ronment IDE running on the PC Standard debugging features provided through this JTAG interface such as single step breakpoints trace memory dump and fill and oth ers There is also a dedicated Debug pin shown in Figure 91 page 226 which can be configured as an output to trigger external devices upon a programmable internal event e g breakpoint match or the pin ca
313. s immediately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit de tector samples the value of RxD The value ac cepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the left most position in the shift register which in Modes 2 and 3 is a 9 bit regis ter it flags the RX Control unit to do one last shift load SBUF and RBS and set the interrupt flag RI The signal to load SBUF RB8 and to set RI will be generated if and only if the following con ditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for 1 to 0 transition on RxD 91 264 uPSD34xx SERIAL UART INTERFACES F
314. s is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the re Set of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the left most position in the shift register which in mode 1 is a 9 bit reg ister it flags the RX Control unit to do one last shift load SBUF and RB8 and set the receive in terrupt flag RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two conditions are not met the re ceived frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition on pin RxD 89 264 uPSD34xx SERIAL UART INTERFACES Figure 33 UART Mode 1 Block Diagram Timer1 Overflow Timer2 Overflow Internal Bus TB8 TxD SBUF 2 Pin EREZA Zero Detector Shift Data Tx Control
315. s needed to use 6 pin ISP be cause all ISP functions are controlled from the ex ternal JTAG program test equipment 228 264 TSTAT and TERR are functional only when JTAG ISP operations are occurring which means they are non functional during JTAG debugging of the 8032 on the MCU Module Programming times vary depending on the num ber of locations to be programmed and the JTAG programming equipment but typical JTAG ISP programming times are 10 to 25 seconds using 6 pin JTAG The signals TSTAT and TERR are not included in the IEEE 1149 1 specification Figure 93 page 229 shows recommended con nections on a circuit board to a JTAG program test tool using 6 pin JTAG It is required to connect the RST output signal from the JTAG program test equipment to the RESET IN input on the uPSD34xx The RST signal is driven by the equip ment with an Open Drain driver allowing other sources like a push button to drive RESET without conflict Note The recommended pull up resistors and de coupling capacitor are illustrated in Figure 93 uPSD34xx PSD MODULE Figure 93 Recommended 6 pin JTAG Connections 100k typical CIRCUIT BOARD uPSD34xx TMS PCO TCK PC1 SRAM STBY or I O PC2 TSTAT PC3 TERR PC4 TDI PCS is Programming or Test GENERAL I O PC7 Equipment Connects Here GENERAL SIGNALS RESETIN PUSH BUTTON or ANY OTHER RESET SOURCE OPTIONAL TEST POINT A110458
316. s space by using the software tool PSDsoft Express ky uPSD34xx MEMORY ORGANIZATION Program Memory External program memory is addressed by the 8032 using its 16 bit Program Counter PC and is accessed with the 8032 sig nal PSEN Program memory can be present at any address in program space between 0x0000 and OxFFFF After a power up or reset the 8032 begins pro gram execution from location 0 0000 where the reset vector is stored causing a jump to an initial ization routine in firmware At address 0x0003 just following the reset vector are the interrupt service locations Each interrupt is assigned a fixed inter rupt service location in program memory An inter rupt causes the 8032 to jump to that service location where it commences execution of the service routine External Interrupt O EXINTO for example is assigned to service location 0x0003 If EXINTO is going to be used its service routine must begin at location Ox0003 Interrupt service lo cations are spaced at 8 byte intervals 0x0003 for EXINTO 0x000B for Timer 0 0x0013 for EXINT1 and so forth If an interrupt service routine is short enough it can reside entirely within the 8 byte in terval Longer service routines can use a jump in struction to somewhere else in program memory Data Memory External data is referred to as XDATA and is addressed by the 8032 using Indi rect Addressing via its 16 bit Data Pointer Register DPTR and is accessed by the
317. sable all interrupts SFR IE EA 0 Set pointer to global data xmit buff er set count as Slave to return an xmit_buf pointer to data buf length number of bytes to xmit Set global variables to indicate Mas ter Xmitter I2C master 1 I2C xmitter 1 lt If busy then test until not busy gt SFR 51 7 0 Load Slave Ad dress amp FEh SFR 51 5 1 send START on bus lt bus transmission begins gt Enable All thing else SFR IE EA 1 Master Receiver Disable all interrupts SFR IE EA 0 Set pointer to global data recv buff er set count Interrupts and go do some recv_buf pointer to data buf length number of bytes to recv Set global variables to indicate Mas ter Xmitter I2C xmitter 0 Disable Master from returning an ACK SFR S1CON AA 0 Enable I2C SIOE SFR S1CON INI1 1 Transmit Address and R W bit 1 to Slave I2C master 1 Is bus not busy SFR S1STA BBUSY 0 lt If busy then test until not busy gt SFR S1DAT 7 0 Load Slave Ad dress 01 SFR S1CON STA 1 send START on bus bus transmission begins Enable All thing else SFR IE EA 1 Interrupts and go do some 111 264 uPSD34xx IC INTERFACE Slave Transmitter Disable all interrupts SFR IE EA 0 Set pointer to global
318. se the minimum duration of an START con dition varies with 2 bus speed and also because the uPSD34xx may be operated with a wide variety of frequencies fosc it is necessary to scale the number of samples per START condi tion based on fosc and fsc In Slave mode the SIOE recognizes the beginning of a START condition when it detects a 1 to 0 transition on the SDA bus line while the SCL line is high see Figure 42 page 100 The SIOE must then validate the START condition by sampling the bus lines to ensure SDA remains low and SCL re mains high for a minimum amount of hold time tui psrA Once validated the SIOE begins receiv ing the address byte that follows the START con dition If the SS Bit in the S1SETUP Register is not set then the SIOE will sample only once after de tecting the 1 to 0 transition on SDA This single sample is taken 1 fosc seconds after the initial 1 to 0 transition was detected However more sam ples should be taken to ensure there is a valid START condition To take more samples the SIOE should be initial ized such that the SS Bit is set and a value is written to the SMPL SET 6 0 field of the S1SETUP Register to specify how many samples to take The goal is to take a good number of sam ples during the minimum START condition hold time tui psrA but no so many samples that the bus will be sampled after tuj psrA expires Table 60 page 109 describes the relatio
319. ses SFRs P1SFSO Table 31 page 61 and P1SFS1 Table 32 page 61 m Port 4 uses SFRs PASFSO Table 34 page 62 and P4SFS1 Table 35 page 62 Since these SFRs are cleared by a reset then by default all port pins function as GPIO not the alter nate function until firmware initializes these SFRs Each pin on each of the three ports can be inde pendently assigned a different function on a pin by pin basis The peripheral functions Timer 2 UART1 and be split independently between Port 1 and Port 4 for additional flexibility by giving a wider choice of peripheral usage on a limited number of device pins When the selected alternate function is UARTO UART1 or SPI then the related pins are in quasi bidirectional mode including the use of the high side driver for rapid O to 1 output transitions The high side driver is enabled for just one MCU_CLK period on 0 to 1 transitions by the delay function at the digital alt func data out signal pictured in Figure 17 page 57 through Figure 19 page 58 If the alternate function is Timer 0 Timer 1 Timer 2 or PCA input then the related pins are in quasi bidirectional mode but input only If the alternate function is ADC then for each pin the pull ups the high side driver and the low side 60 264 driver are disabled The analog input is routed di rectly to the ADC unit Only Port 1 supports analog functions Figure 17 page 57 Port 1 is not 5V t
320. set value 00h Details P3SFS7 P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFSO Details Default Port Function Port 3 Pin R W P3SFS i 0 Port 3 Pin i 0 7 P3SFS i 1 Port Pin i 0 7 0 R W GPIO UARTO Receive RXDO 1 R W GPIO UARTO Transmit TXDO 2 R W GPIO Ext Intr O Timer 0 Gate EXTOINT TGO 3 RW GPIO Ext Intr 1 Timer 1 Gate EXT1INT TG1 4 RW GPIO Counter 0 Input CO 5 R W GPIO Counter 0 Input C1 6 RW GPIO 2 Data I2CSDA 7 RW GPIO 2 Clock 2 Table 31 P1SFSO Port 1 Special Function Select 0 Register SFR 8Eh reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF07 15 06 15 05 P1SF04 15 P1SF02 P1SF01 15 00 Table 32 15 51 Port 1 Special Function Select 1 Register SFR 8Fh reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF17 P1SF16 P1SF15 P1SF14 P1SF13 P1SF12 P1SF11 P1SF10 3 Table 33 P1SFSO and P1SFS1 Details Default Port Function Alternate 1 Port Function Port 1 Pin RW 5 x PIsFSilil 0 1 Port 1 Pin i 0 7 Port 1 Pin i 0 7 Port 1 Pin i 0 7 0 RW GPIO Timer 2 Count Input T2 ADC Chn 0 Input ADCO 1 RW GPIO Timer 2 Trigger Input TX2 2 RW GPIO UART1 Receive RXD1 ADC Chn 2 Input ADC2 3 RW GPIO UART1 Transmit TXD1 ADC Chn 3 Input ADC3 4 RW GPIO SPI Clock SPICLK 5 RW GPIO SPI Receive SPIRXD ADC Chn 5 Input ADC5 6 R
321. sible for comparing this bit with what is expected for error detection and processing FIFO Busy Status Endpoint IN Case Once the FIFO has been loaded and armed USIZE written with the number of bytes to send the BSY Bit is set and remains set until the SIE has transmitted the data in the FIFO The CPU should only access the FIFO when BSY 0 0 BSY R W Endpoint OUT Case While the SIE is receiving data and storing it in the FIFO BSY 1 it should not be accessed by the CPU Once the OUT transaction is complete BSY 0 the CPU may read the contents of the FIFO The BSY Bit will remain cleared until another OUT transaction is received USB FIFO Valid Size USIZE The Endpoint selected by the USB Endpoint Select Register see Table 82 page 145 determines the direction and FIFO that is controlled by the USB FIFO Valid Size see uPSD34xx USB INTERFACE indicates the number of bytes loaded into the IN FIFO that the SIE is to send in a Data packet for an Endpoint IN case and indicates the number of bytes received for an Endpoint OUT case Table 84 The USB FIFO Valid Size Register Table 84 USB FIFO Valid Size USIZE OF2h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIZE 6 0 Details Bit Symbol R W Definition 7 Reserved Endpoint IN Case The CPU writes the USIZE register with the number of bytes it loaded into the IN endpoint FIFO for
322. sillator or No Connect Active Clock Source A109198 53 264 uPSD34xx I O PORTS of MCU MODULE PORTS OF MCU MODULE The MCU Module has three 8 bit I O ports Port 1 Port 3 and Port 4 The PSD Module has four other ports Port A C and D This section de scribes only the I O ports on the MCU Module ports will function as bi directional General Purpose I O GPIO but the port pins can have al ternate functions assigned at run time by writing to specific SFRs The default operating mode during and after reset for all three ports is GPIO input mode Port pins that have no external connection will not float because each pin has an internal weak pull up 150K ohms to Vcc ports 3 and 4 are tolerant meaning they can be driven pulled externally up to 5 5V without damage The pins on Port 4 have a higher current capability than the pins on Ports 1 and 3 Three additional MCU ports only on 80 pin uPSD34xx devices are dedicated to bring out the 8032 MCU address data and control signals to external pins port named MCUAD 7 0 has eight multiplexed address data bidirectional sig nals The third port has MCU bus control outputs read write program fetch and address latch These ports are typically used to connect external parallel peripherals and memory devices but they may NOT be used as GPIO Notice that the eight upper address signals do not come out to pins on the port If h
323. ster As the count rolls over from all 1s to all Os it sets the Timer Interrupt flag TF1 The counted input is enabled to the Timer when 1 and either GATE 0 or EXTINT1 1 Setting GATE 1 allows the Timer to be con trolled by external input EXTINT1 to facilitate pulse width measurements TR1 is a control bit in the SFR TCON GATE is a bit in the SFR TMOD The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored Setting the run flag TR1 does not clear the registers Mode 0 operation is the same for the Timer 0 as for Timer 1 Substitute TRO TFO CO TLO THO and EXTINTO for the corresponding Timer 1 sig nals in Figure 25 There are two different GATE Bits one for Timer 1 and one for Timer 0 Mode 1 Mode 1 is the same as Mode 0 except that the Timer Register is being run with all 16 bits Mode 2 Mode 2 configures the Timer Register as an 8 bit Counter TL1 with automatic reload as shown in Figure 26 page 75 Overflow from TL1 not only sets TF1 but also reloads TL1 with the contents of TH1 which is preset with firmware The reload leaves TH1 unchanged Mode 2 oper ation is the same for Timer Counter 0 Mode 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer 0 is shown i
324. sters csiop A block of 256 bytes is decoded inside the PSD Module for module control status see Table 106 page 176 The base address of these 256 locations is referred to in this data sheet as csiop Chip Select I O Port and is selected by the De code PLD output signal CSIOP The csiop regis ters are always viewed by the 8032 as XDATA and are accessed with RD and WR signals The address range of csiop is specified using PSDsoft Express where the user only has to specify an ad dress range of 256 bytes and then the RD or WR signals are automatically activated for the speci fied range Individual registers within this block are accessed with an offset from the specified csiop base address 39 registers are used out of the 256 locations to control the output state of I O pins to read I O pins to set the memory page to control 8032 program and data address space to control power management to READ WRITE macrocells inside the General PLD and other functions during runtime Unused locations within csiop are re served and should not be accessed Memory Page Register 8032 MCU architecture has an inherent size limit of 64K bytes in either program address space or XDATA space Some uPSD34xx devices have much more memory that 64K so special logic such as this page register is needed to access the extra memory This 8 bit page register Figure 63 can be loaded and read by the 8032 at runtime as one of the csiop regis ters
325. t sends data back to the host identifying what it is 3 The host resets the device and then sends a Set_Address request This is a unique address that identifies it from all other devices connected to the USB This address remains in effect until the device is disconnected from the USB 4 host sends more Get Descriptor requests to the device to gather more detailed information about it and then loads the specified driver 5 The host will setup and enable the endpoints defined by the device 6 The device is now configured and ready for use with the host communicating to the device using the assigned address and endpoints Payload ADDR CRC16 TEUER ADDR aai iiaa Data 8 bytes SETUP Stage Token Packet Data Packet Handshake Packet ADDR ENDP CRC5 Payload ACK DATA Data Stage Token Packet Data Packet Handshake Packet Optional OUT ADDR ENDP CRC5 CRC16 ACK our ADDR enor crcs Datan cnc STATUS Handshake Stage Token Packet Data Packet 110492 128 264 1572 Endpoint FIFOs The uPSD34xx s USB module includes 5 end points and 10 FIFOs Each endpoint has two FIFOs with one for IN and the other for OUT trans actions Each FIFO is 64 bytes long and is selec tively made visible in a 64 byte XDATA segment for CPU access For efficient data transfers the FIFOs may be paired for double buffering With double buffering the CPU may operate on the contents in one buffer
326. t to LSB last When FLSB Bit is set to 1 the data is transferred in order from LSB first to MSB last The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal PERIPH_CLK always operates at the frequency fosc and runs constantly except when stopped in MCU Power Down mode SPICLK is a result of di viding PERIPH_CLK by a sum of different divisors selected by the value contained in the SPICLKD register The default value in SPICLKD after a re set divides PERIPH_CLK by a factor of 4 The bits in SPICLKD can be set to provide resulting divisor values in of sums of multiples of 4 such as 4 8 12 16 20 all the way up to 252 For example if SPICLKD contains Ox24 SPICLK has the fre quency of PERIH CLK divided by 36 decimal 3 SPICLK frequency must be set low enough to allow the MCU time to read received data bytes without loosing data This is dependent upon many things including the crystal frequency of the MCU and the efficiency of the SPI firmware Dynamic Control At runtime bits in registers SPICONO SPICON1 and SPISTAT are managed by firmware for dy namic control over the SPI interface The bits Transmitter Enable TE and Receiver Enable RE when set will allow transmitting and receiving respectively If TE is disabled both transmitting and receiving are disabled because SPICLK is driven to constant output logic 0 when SPO 0 or logic 1 when SPO 1 When the SSE
327. t Express does use PT expansion in the DPLD it results in an approxi mate 15ns additional propagation delay for that chip select signal which gives 15ns less time for the memory to respond Be aware of this and con sider adding a wait state to the 8032 bus access using the SFR named BUSCON or lower the 8032 clock frequency to avoid problems with memory access time PORT C PINS 715174131211 Used for JTAG Pin Not Available to GPLD A109177 194 264 Table 112 OMC Port and Data Bit Assignments uPSD34xx PSD MODULE Data Bit on 8032 Data omc Port Native Product Terms Maximum Borrowed Bus for Loading or Assignment from AND OR Array Product Terms Reading OMC MCELLABO Port AO or BO 3 6 DO MCELLAB1 Port A1 or B1 3 6 MCELLAB2 Port A2 or B2 3 6 D2 MCELLABS3 Port A3 or B3 3 6 D3 MCELLAB4 Port A4 or B4 3 6 D4 MCELLAB5 Port A5 or B5 3 6 D5 MCELLABG Port A6 or B6 3 6 D6 MCELLAB7 Port A7 or B7 3 6 D7 MCELLBCO Port BO 4 5 DO MCELLBC1 Port B1 4 5 D1 MCELLBC2 Port B or C2 4 5 D2 MCELLBC3 Port B3 or C3 4 5 D3 MCELLBC4 Port B4 or C4 4 6 D4 MCELLBC5 Port B5 4 6 D5 MCELLBC6 Port B6 4 6 06 MCELLBC7 Port B7 orC7 4 6 D7 Note 1 MCELLABO MCELLAB7 can be output to Port A pins only on 80 pin devices Port A is not available on 52 pin devices 2 Port pins PCO PC1 PC5 and PC6 are dedicated JTAG pins and are not available as outputs for MCELLBC 0 1 5 or 6 3 uPSD
328. t On Application The IN FIFO data toggle bit is controlled exclusive ly by the USB SIE therefore it is not possible to change the state of the data toggle bit by firmware Workaround For cases where the data toggle bit must be reset such as after a Clear Feature Stall request send ing the subsequent data on that endpoint twice re sults in getting the data toggle bit back to the state that it should be USB FIFO Accessibility Description The USB FIFO is only accessible by firmware and not by a JTAG debugger Impact On Application Using a JTAG debugger it is not possible to view the USB FIFO s contents in a memory dump win dow Workaround None identified at this time Erroneous Resend of Data Packet Description When a data packet is sent the respective IN FIFO busy bit is not automatically cleared by the USB SIE This can cause a data packet to be errone ously resent to the host in response to an IN PID immediately after the first correct transmission of this data packet Impact On Application Since the Data Toggle in the retransmitted data packet is toggled from when the data was first sent the host will treat this packet as valid If the identified workaround is not implemented then this extra and unexpected data packet would result in a communication breakdown 1572 Workaround In the USB ISR when an INx x the endpoint number of the IN FIFO is detected the IN FIFOs respective busy bit shou
329. t generates a clock signal on the SCL line Then the Master transmits the first byte on the SDA line containing the 7 bit Slave address plus the R W bit The Slave who owns that address will respond with an acknowledge bit on SDA and all other Slave devices will not respond Next the addressed Slave will transmit a data byte or bytes to the Master The Master will return an acknowledge bit after each data byte it successfully receives unless it is the last byte the Master desires If so the Master will not acknowledge the last byte and from this the Slave knows to stop transmitting data bytes to the Master The Master will then generate a STOP condition on the bus or it will generate a RE START conditon and begin the next transfer There is no limit to the number of bytes that can be transmitted during a transfer session A few things to know related to these transfers Either the Master or Slave device can hold the SCL clock line low to indicate it needs more time to handle a byte transfer An indefinite holding period is possible A START condition is generated by a Master and recognized by a Slave when SDA has a 1 to 0 transition while SCL is high Figure 42 page 100 ASTOP condition is generated by a Master and recognized by a Slave when SDA has a 0 to1 transition while SCL is high Figure 42 page 100 ARE START repeated START condition generated by a Master can have the same function as a STOP condit
330. t or decre ment after each data transfer further reducing the burden on the 8032 and making this kind of data movement very efficient Data Pointer Control Register DPTC 85h By default the DPTR Register of the uPSD34xx will behave no different than in a standard 8032 MCU The DPSELO Bit of SFR register DPTC shown in Table 13 selects which one of the two background data pointer registers DPTRO or 1 will function as the traditional DPTR Reg ister at any given time After reset the DPSELO Bit is cleared enabling DPTRO to function as the DP TR and firmware may access DPTRO by reading or writing the traditional DPTR Register at SFR ad dresses 82h and 83h When the DPSELO bit is set then the DPTR1 Register functions as DPTR and firmware may now access DPTR1 through SFR registers at 82h and 83h The pointer which is not selected by the DPSELO bit remains in the back ground and is not accessible by the 8032 If the DPSELO bit is never set then the uPSD34xx will behave like a traditional 8032 having only one DPTR Register To further speed XDATA to XDATA transfers the SFR bit AT may be set to automatically toggle the two data pointers DPTRO and DPTR1 each time the standard DPTR Register is accessed by a MOVX instruction This eliminates the need for firmware to manually manipulate the DPSELO bit between each data transfer Detailed description for the SFR register DPTC is shown in Table 13 Table 13 DPTC Da
331. t period 5 WDRST contains 00h meaning a full 224 up counts are required to reach FFFFFh and generate a reset In this example 1 _ 100ns 4 periods x 25ns NovERrLow 224 16777216 up counts 100ns X 16777216 1 67 seconds The actual value will be slightly longer due to PFQ BC Firmware Example The following 8051 assem bly code illustrates how to operate the WDT A simple statement in the reset initialization firmware enables the WDT and then a periodic write to clear the WDT in the main firmware is required to keep the WDT from overflowing This firmware is based on the example above 40MHz fosc CCONO 10h BUSCON Cth For example in the reset initialization firmware the function that executes after a jump to the reset vector MOV AE AA enable WDT by writing value to WDKEY other than 55h Somewhere in the flow of the main program this statement will execute periodically to reset the WDT before its time out period of 1 67 seconds For example MOV A6 00 reset WDT loading 000000h Counting will automatically resume as long as 55h in not in WDKEY 69 264 uPSD34xx SUPERVISORY FUNCTIONS Table 39 WDKEY Watchdog Timer Key Register SFR AEh reset value 55h WDKEY T7 0 Details Bit Symbol R W Definition 55h disables the WDT from counting 55h is automatically loaded in this SFR after any reset condition leaving the WDT disabled
332. t signals FSO FS7 with three product terms each m Four Secondary Flash memory sector select signals CSBOOT0O CSBOOTS with three product terms each m One SRAM select signal RSO with two product terms m One select signal for the base address of 256 PSD Module device control and status registers csiop with one product term m Two external chip select output signals for Port D pins each with one product term 52 pin devices only have one pin on Port D m Twochip select signals PSELO PSEL1 used to enable the 8032 data bus repeater function Peripheral I O mode for Port on 80 pin devices Each has one product term uPSD34xx PSD MODULE A product term indicates the logical OR of two or more inputs For example three product terms in a DPLD output means the final output signal is ca pable of representing the logical OR of three differ ent input signals each input signal representing the logical AND of a combination of the 69 PLD in puts Using the signal FSO for example the user may create a 3 product term chip select signal that is logic true when any one of three different address ranges are true FSO address range 1 OR ad dress range 2 OR address range 3 The phrase one product term is a bit misleading but commonly used in this context One product term is the logical AND of two or more inputs with no OR logic involved at all such as the CSIOP sig nal in Figure 75 page 190 189 264 uP
333. t to 1 by firmware or by a reset event 58 264 uPSD34xx I O PORTS of MCU MODULE Table 28 P3 I O Port 3 Register SFR BOh reset value FFh P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Details Bit Symbol R W Function 7 P3 7 R W Port pin 3 7 6 P3 6 RW Port pin 3 6 5 P3 5 RW Port pin 3 5 4 P3 4 RW Port pin 3 4 3 P3 3 RW Port pin 3 3 2 P3 2 RW Port pin 3 2 1 P3 1 RW Port pin 3 1 0 P3 0 RW Port pin 3 0 Note 1 Write 1 or 0 for pin output Read for pin input but prior to READ this bit must have been set to 1 by firmware or by a reset event Table 29 P4 I O Port 4 Register SFR COh reset value FFh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Details Bit Symbol R W Function 7 P4 7 RW Port pin 4 7 6 P4 6 RW Port pin 4 6 5 P4 5 RW Port pin 4 5 4 P4 4 RW Port pin 4 4 3 P4 3 RW Port pin 4 3 2 P4 2 RW Port pin 4 2 1 P4 1 R W Port pin 4 1 0 P4 0 RW Port pin 4 0 Note 1 Write 1 or 0 for pin output Read for pin input but prior to READ this bit must have been set to 1 by firmware or by a reset event 59 264 uPSD34xx I O PORTS of MCU MODULE Alternate Functions There are five SFRs used to control the mapping of alternate functions onto MCU port pins and these SFRs are depicted as switches in Figure 16 page 56 m Port 3 uses the SFR P3SFS Table 30 page 61 m Port 1 u
334. ta Pointer Control Register SFR 85h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DPSELO Details Bit Symbol R W Definition 7 Reserved 0 Manually Select Data Pointer AT FUN 1 Auto Toggle between DPTRO and DPTR1 5 1 Reserved 0 DPSEO RW 0 DPTRO Selected for use as DPTR 1 DPTR1 Selected for use as DPTR 38 264 Data Pointer Mode Register DPTM 86h The two background data pointers DPTRO and DPTR1 can be configured to automatically incre ment decrement or stay the same after a MOVX instruction accesses the DPTR Register Only the currently selected pointer will be affected by the in uPSD34xx DUAL DATA POINTERS Firmware Example The 8051 assembly code il lustrated in Table 15 shows how to transfer a block of data bytes from one XDATA address region to another XDATA address region Auto address in crementing and auto pointer toggling will be used crement or decrement This feature is controlled by the DPTM Register defined in Table 14 The automatic increment or decrement function is effective only for the MOVX instruction and not MOVC or any other instruction that uses the DTPR Register Table 14 DPTM Data Pointer Mode Register SFR 86h reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD11 MD10 MDO1 Details Bit Symbol R W Definition 7 4 Reserved DPTR1 Mode Bits 00
335. tails Bit Symbol R W Definition 7 3 Reserved OIL E Table 88 USB Setup Command Value Register USCV OF6h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 USCV 7 0 Details Bit Definition The nth byte of the 8 bytes of USB Setup Command Data received with 7 0 the last Setup transaction The nth byte that is read from this register is specified by the index value in the USCI register 149 264 3 uPSD34xx USB INTERFACE Typical Connection to USB Connecting the uPSD34xx to the USB is simple and straightforward Figure 56 shows a typical self powered example requiring only three resis tors and a USB power detection circuit The USB power detection circuit detects when the device has been connected to the USB When Vpus is de tected it switches 3 3V to the pull up resistor on Figure 56 Typical Self Powered Example the D line Per the USB specification the pull up resistor on D is required to signal to the upstream USB port when a full speed device has been con nected to the bus The resistors in series in the D and D lines are recommended per the USB spec ification to reduce transients on the data lines USB Power Detection Block VDD uPSD34xx 150 264 110495 1572 uPSD34xx ANALOG TO DIGITAL CONVERTOR ADC ANALOG TO DIGITAL CONVERTOR ADC The ADC unit in the UPSD34xx is a SAR type ADC with an SAR register an auto zero
336. tatus flags will cause an in terrupt to the MCU SPICONO SPICON1 CONTROL REGISTERS TIMING AND CONTROL SPISTAT STATUS REGISTER PERIPH_CLK SPICLKD DIVIDE SELECT 8032 MCU DATA BUS 8 SPITDR TRANSMIT REGISTER 8 FEET TT Ty SPIRxD P1 5 or P4 5 SPIRDR RECEIVE REGISTER 8 SPITxD P1 6 or P4 6 SPISEL P1 7 or P4 7 SPICLK P1 4 or P4 4 Al10486 118 264 uPSD34xx SPI SYNCHRONOUS PERIPHERAL INTERFACE SPI Configuration The SPI interface is reset by the MCU reset and firmware needs to initialize the SFRs SPICONO SPICON1 and SPICLKD to define several opera tion parameters The SPO Bit in SPICONO determines the clock po larity When SPO is set to 0 a data bit is transmit ted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be valid during the falling edge of SPICLK When SPO is set to 1 a data bit is transmitted on SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the rising edge of SPICLK The uPSD34xx will sample received data on the appro priate edge of SPICLK as determined by SPO The effect of the SPO Bit can be seen in Figure 46 and Figure 47 page 117 The FLSB Bit in SPICONO determines the bit order while transmitting and receiving the 8 bit data When FLSB is 0 the 8 bit data is transferred in or der from MSB firs
337. tci cL 5 ns tavWL Address A0 A7 valid to WR 32 5 Saas WR High to ALE High 9 5 0 5 3 0 5tcLoL 2 tavwH Data setup before WR 20 ytcLcL 5 ns twHox Data hold after WR 9 5 14 5 0 5 3 0 5 2 ns tavay Address valid to Latched Address out 35 5 3V 1 2 ns on Ports A and B 28 5V 9 5 ns Note 1 BUSCON Register is configured for 4 PFQCLK 2 Refer to Table 162 page 243 for n and m val 3 Latched address out on Ports A and B to WR is 2ns minimum 242 264 ues uPSD34xx DC AND AC PARAMETERS Table 162 External Clock Drive 40MHz Oscillator Symbol Parameter 1 to 40MHz tcLcL Oscillator period High time tcLcx tci cH Rise time 10 ns Table 163 A D Analog Specification Symbol Parameter Test Conditions Min Typ Max Unit Normal Input IDD Power down AVIN Analog Input Voltage GND Analog Reference Voltage Accuracy Resolution INL Integral Nonlinearity v DNL Differential Nonlinearity v SNR Signal to Noise Ratio fsAMPLE 500ksps 50 SNDR Signal to Noise Distortion Ratio 48 ADC Clock 2 tc Conversion Time 8MHz 1 4 8 us tCAL Power up Time Calibration Time 16 ms fin Analog Input Frequency 60 kHz THD Total Harmonic Distortion 50 54 dB Note 1
338. te 1 Fast Slew Rate output available on PA3 PAO PB3 PBO and PD2 PD1 Decrement times by given amount 2 CLKIN PD1 tci teL 105 246 264 Table 168 CPLD Macrocell Synchronous Clock Mode Timing 3V PSD Module uPSD34xx DC AND AC PARAMETERS Sle Symbol Parameter Conditions bs 9 Maximum Frequency External Feedback 1 ts tco 23 2 Maximum Frequency UM fmax Internal Feedback W ts tco 10 oe Maximum Frequency Pipelined Data 1 tcH tcL 40 0 MHz ts Input Setup Time 20 4 ns Clock High Time Clock Input 15 ns Clock Low Time Clock Input ns tco Clock to Output Delay Clock Input 23 6 ns CPLD Array Delay Any macrocell 20 4 ns twin Minimum Clock Period 25 ns Note 1 Fast Slew Rate output available on PA3 PAO PB3 PBO and PD2 PD1 Decrement times by given amount 2 CLKIN PD1 tci 247 264 uPSD34xx DC AND AC PARAMETERS Figure 103 Asynchronous RESET Preset RESET PRESET INPUT REGISTER OUTPUT tARPW tARP Al02864 Figure 104 Asynchronous Clock Mode Timing Product Term Clock CLOCK INPUT REGISTERED OUTPUT tSA tHA tCOA Symbol Parameter Conditions EN Max p 2 Maximum Frequency Maximum Frequency E Maximum Frequency tsa Input Setup Time 7 2 10 ns tHA Input Hold Time 8 ns tcHA Clock Inp
339. te Generator Mode Timer 1 Overflow Note Oscillator frequency is divided by 2 not 12 like in other timer modes TH2 8bits N TL2 8 bits 1 1 Control 16 RX CLK 16 TX CLK Transition Detector Timer 2 Interrupt Control EXEN2 P al Note Availability of additional external interrupt 109605 82 264 SERIAL UART INTERFACES uPSD34xx devices provide two standard 8032 UART serial ports The first port UARTO is connected to pins RxDO P3 0 and TxDO P3 1 second port UART1 is connected to pins RxD1 P1 2 and TxD1 P1 3 UART1 can optionally be routed to pins P4 2 and P4 3 as described in Alternate Functions page 60 The operation of the two serial ports are the same and are controlled by two SFRs m SCONO Table 47 page 84 for UARTO m SCON1 Table 48 page 85 for UART1 Each UART has its own data buffer accessed through an SFR listed below m SBUFO for UARTO address 99h m SBUF1 for UART1 address D9h When writing SBUO or SBUF1 the data automati cally loads into the associated UART transmit data register When reading this SFR data comes from a different physical register which is the receive register of the associated UART Note For simplicity in the remaining UART dis cussions the suffix 0 or 1 will be dropped when referring to SFR registers and bits related to UARTO or UART1 since each UART interface
340. terrupt enable UIFO 3 USB interrupt flags UCTL USB Control USTA USB Status USEL USB Endpoint and direction select USB Selected FIFO control register USIZE USB Selected FIFO size register UBASE USB Base Address register USCI USB Setup Command index USCV USB Setup Command value The memory map for the USB SFRs the individual bit names and the reset values are shown in Ta ble 69 page 133 3 uPSD34xx USB INTERFACE Table 69 uPSD34xx USB SFR Register Map SFR Addr hex SFR Name 4 3 Bit Name and Bit Address 2 1 Reset Value Comment hex E2 UADDR USBADDR 6 0 USB 00 Address E3 E4 UPAIR UIEO PRSOUT PR1OUT SUSPNDIE PRSIN PR1IN RESUMIE USB 00 Pairing Control USB Global Interrupt Enable E5 UIE1 USB IN FIFO Interrupt Enable E6 E7 UIE2 OUT4IE OUTSIE NAKAIE NAKSIE OUT2IE OUTIIE 2 NAK1IE OUTOIE NAKOIE USB OUT FIFO Interrupt Enable USB IN FIFO NAK Int Enable E8 UIFO GLF INF SUSPNDF RESUMF USB Global Interrupt Flag E9 EA UIF1 UIF2 OUT4F OUTSF USB IN FIFO Interrupt Flag USB OUT FIFO Interrupt Flag EB EC ED EE UIF3 UCTL USTA NAK4F NAK3F USBEN RESERVED VISIBLE WAKEUP USB IN 00 FIFONAK Int Flag USB Contr
341. terrupt if overflow flag OVF is set 0 PCA operates when CPU is in Idle Mode 4 1 stops running when CPU is in Idle Mode 3 Reserved 0 Select 16 bit PWM 10B PWM 4 _ Select 10 bit PWM 00 Select Prescaler clock as Counter clock 1 0 Nr 01 Select Timer 0 Overflow 10 Select External Clock pin P4 7 for PCA1 MAX clock rate fosc 4 3 161 264 uPSD34xx PROGRAMMABLE COUNTER ARRAY PCA WITH PWM Table 98 PCA Status Register PCASTA SFR 0A5h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit OVF1 INTF5 INTF4 INTF3 OVFO INTF2 INTF1 INTFO Details Bit Symbol OFV1 INTF5 Function PCA1 Counter OverFlow flag Set by hardware when the counter rolls over OVF1 flags an interrupt if Bit EOVFI in PCACON1 is set OVF1 may be set with either hardware or software but can only be cleared with software TCMB Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software INTF4 TCMA Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software INTF3 OVFO INTF2 Interrupt flag Set by hardware when a match or capture event occurs Must be clear with software PCAO Counter OverFlow flag Set by hardware when the counter rolls over OVFO flags an interrupt if Bit EOVFI in PCACONO is set OVF1 may be set with either hardware or software but can only
342. the byte level or bit level At the byte level a device may pause the transfer between bytes by holding SCL low to have time to store the latest received byte or fetch the next byte to transmit At the bit level a Slave device may extend the low period of SCL by holding it low Thus the speed of any Master device will adapt to the internal opera tion of the Slave General Call Address A General Call GC occurs when a Master Trans mitter initiates a transfer containing a Slave ad dress of 0000000b and the R W bit is logic 0 All Slave devices capable of responding to this broad cast message will acknowledge the GC simulta neously and then behave as a Slave Receiver The next byte transmitted by the Master will be ac cepted and acknowledged by all Slaves capable of handling the special data bytes A Slave that can not handle one of these data bytes must ignore it by not acknowledging it The specification lists the possible meanings of the special bytes that fol low the first GC address byte and the actions to be taken by the Slave device s upon receiving them A common use of the GC by a Master is to dynamically assign device addresses to Slave de vices on the bus capable of a programmable de vice address The uPSD34xx can generate a GC as a Master Transmitter and it can receive a GC as a Slave When receiving a GC address 00h an interrupt will be generated so firmware may respond to the special GC data bytes
343. the erase cycle may be resumed with this instruction sequence The Resume Sector Erase instruction sequence consists of writing the com mand 30h to any valid address within the Flash ar ray that was suspended as shown in Table 107 page 179 Reset Flash The Reset Flash instruction se quence resets the embedded algorithm running on the state machine in the targeted Flash memory Main or Secondary and the memory goes into Read Array mode The Reset Flash instruction consists of one bus WRITE cycle as shown in Ta ble 107 page 179 and it must be executed after any error condition that has occurred during a Flash memory Program or Erase operation It may take the Flash memory up to 25us to com plete the Reset cycle The Reset Flash instruction sequence is ignored when it is issued during a Program or Bulk Erase operation The Reset Flash instruction sequence aborts any on going Sector Erase operation and returns the Flash memory to Read Array mode within 25us Reset Signal Applied to Flash Memory When ever the PSD Module receives a reset signal from the MCU Module any operation that is occurring in either Flash memory array will be aborted and the array s will go to Read Array mode It may take up to 25us to abort an operation and achieve Read Array mode A reset from the MCU Module will result from any of these events an active signal on the uPSD34xx RESET IN input pin a watchdog timer time out detection of low Vcc or a J
344. the previously addressed byte 1572 Error Flag DQ5 During a normal program or erase operation the Error Flag Bit DQ5 is to 0 This bit is set to 1 when there is a failure during Flash memory byte program sector erase or bulk erase operations In the case of Flash memory programming DQ5 Bit indicates an attempt to program a Flash mem ory bit from the programmed state of 0 to the erased state of 1 which is not valid DQ5 may also indicate a particular Flash cell is damaged and cannot be programmed In case of an error in a Flash memory sector erase or byte program operation the Flash memory sec tor in which the error occurred or to which the pro grammed byte belongs must no longer be used Other Flash memory sectors may still be used DQb is reset after a Reset Flash instruction se quence Erase Time out Flag DQ3 The Erase Time out Flag Bit DQ3 reflects the time out period al lowed between two consecutive sector erase in struction sequence bytes If multiple sector erase commands are desired the additional sector erase commands 30h must be sent by the 8032 within 80us after the previous sector erase com mand DQ3 is 0 before this time period has ex pired indicating it is OK to issue additional sector erase commands will go to logic 1 if the time has been longer than 80us since the previous sec tor erase command time has expired indication that is not OK to send another sector erase
345. the shortest signal propagation delay but consumes more current than non Turbo mode A csiop register can be written by the 8032 to select modes the default mode is with Turbo mode enabled In non Turbo mode the PLDs can achieve very low standby current zero DC current while no PLD inputs are changing and the PLDs will even use less AC current when inputs do change compared to Turbo mode When the Turbo mode is enabled there is a significant DC current component AND the AC current component is higher than non Turbo mode as shown in Figure 96 page 233 5V and Figure 97 page 233 3 3V Blocking Bits Significant power savings can be achieved by blocking 8032 bus control signals RD WR PSEN ALE from reaching PLD inputs if these signals are not used in any PLD equations Blocking is achieved by the 8032 writing to the blocking bits in csiop PMMR registers Current consumption of the PLDs is directly related to the composite frequency of all transitions on PLD inputs so blocking certain PLD inputs can significantly lower PLD operating frequency and power consumption resulting in a lower frequency on the graphs of Figure 96 page 233 and Figure 97 page 233 SRAM Backup Voltage Pin PC2 can be configured in PSDsoft to accept an alternate DC voltage source battery to automatically retain the contents of SRAM when Vpp drops below this alternate voltage Note It is recommended to prevent unused inputs from floati
346. to allow volt age levels equal to Vpp from the standard logic to interface with the physical layer of the USB It is capable of receiving and transmitting serial data at full speed 12 Mb s The SIE is the digital front end of the USB block This module recovers the 12MHz clock detects the USB sync word and handles all low level USB protocols and error checking The bit clock recov ery circuit recovers the clock from the incoming USB data stream and is able to track jitter and fre quency drift according to the USB specifications The SIE also translates the electrical USB signals into bytes or signals When there is a USB device address match the USB data is directed to an endpoints FIFO for OUT transactions and read from an endpoint s FIFO for IN transactions Con trol transfers are supported on EndpointO and in terrupt and bulk data transfers are supported on Endpoints1 through 4 The device s USB address and the enabling of the endpoints are programma ble using the SIE s SFRs Important Note The USB SIE requires a 48MHz clock to operate properly A PLL is included in the uPSD34xx that must be programmed appropriate ly based on the input clock to provide a 48MHz clock to the SIE see USB page 47 to set up the PLL 123 264 uPSD34xx USB INTERFACE Figure 49 USB Module Block Diagram 3 40MHz Serial USB Interface Transceiver Engine Endpoint4 XDATA CTRL
347. tors of Main Flash memory 150 fs1 reside in the lower half of program ad dress space and these two sectors are indepen dent of paging they reside in common program address space This paged memory example is quite common and supported by many 8051 soft ware compilers 8032 Data Address Space XDATA Four sec tors of Secondary Flash memory reside in the up per half of 8032 XDATA space in the example of Figure 64 SRAM and csiop registers are in the lower half of XDATA space The 8032 SFR regis ters and local SRAM inside the 8032 MCU Module do not reside in XDATA space so it is OK to place PSD Module SRAM or csiop registers at an ad dress that overlaps the address of internal 8032 MCU Module SRAM and registers Figure 64 Typical System Memory Map 8032 PROGRAM SPACE 8032 XDATA PSEN _ SPACE RD and WR FFFFh Page 0 1 Page2 Page X FFFFh 8KB E000h 8KB 8KB csboot0 fs3 fs5 fs7 16KB 16KB 16KB Co00h fs2 fs4 fs6 16KB 16KB 16KB 8000h fs1 16KB Common Memory to All Pages System 1 0 256B 2000h rs0 8KB 0000h 109173 4000h 150 16KB Common Memory to All Pages 0000h 169 264 uPSD34xx PSD MODULE Specifying the Memory Map with PSDsoft Ex press The memory map example shown in Fig ure 64 page 169 is implemented using PSDsoft Express in a point and click environment PSDsoft Express will automatically generate Hardware Definition Language HDL st
348. transmission with the next IN transaction Once the USIZE register has been written the FIFO becomes ready for transmission 6 0 SIZE R W Endpoint OUT Case The CPU reads the USIZE register to determine how many bytes were received in the data packet during the last OUT transaction This tells the CPU how many valid bytes to read from the FIFO Note Since the FIFOs are 64 bytes in length the maximum value for SIZE is 64 40h 3 147 264 uPSD34xx USB INTERFACE USB FIFO Base Address High and Low Registers UBASEH and UBASEL All 10 Endpoint FIFOs share the same 64 byte address range The 16 bit base address for the FIFOs is specified using the USB Base Address registers see Table 85 and Table 86 The USB Endpoint Select Register see Table 82 page 145 selects the direction and the Endpoint for the FIFO that is accessed when addressing the 64 bytes of XDATA space starting with the base address specified in the Base Address Registers The Base Address is a 64 byte segment where the lower 6 bits of the base register are hardwired to O Important Note The USB FIFO Base Address must be set to an open 64 byte segment in the XDATA space Care should be taken to ensure that there is no overlap of addresses between the USB FIFOs and the flash memory SRAM csiop registers and anything else accessed in the XDATA space While the logic in the PSD module handles overlap of flash memory SRAM and the csiop registers with
349. trol Figure 51 IN and OUT Bulk Transfers uPSD34xx USB INTERFACE Note The uPSD34xx supports all types of trans fers except Isochronous m Bulk Transfers see Figure 51 Bulk data is transferred in both directions and is used with both IN and OUT endpoints Packets may be 8 16 32 or 64 bytes in length Bulk transfers occur in bursts and are scheduled by the host when there is available time on the bus While there is no guaranteed delivery time for bulk transfers the accuracy of the data is guaranteed due to automatic retries for erroneous data Bulk transfers are typically used for mass storage printer and scanner data m Interrupt Transfers see Figure 52 Interrupt data is a lot like bulk data but travels only in one direction from the device to the host so only IN endpoints are used Interrupt data holds packet sizes ranging from 1 to 64 bytes Interrupt endpoints have an associated polling interval meaning that the host sends IN tokens at a periodic interval to the host on a regular basis Interrupt transfers are typically used for human interface devices such as keyboards mice and joysticks ADDR ENDP CRC5 Payload Data Token Packet our ADDR ENDP CRC5 Token Packet Payload CRC16 Data Data Packet Handshake Packet ACK Data Packet Handshake Packet 110490 Figure 52 Interrupt Transfer ADDR ENDP CRC5 Payload Data ACK Token Packet
350. ts in the Status Register 2 TOGGLE 1 match on the comparator results in a toggling output on CEXn pin 01 Enable PWM Mode x8 fixed frequency Enable the CEXn pin as a PWM output 10 Enable PWM Mode x8 with programmable frequency Enable the CEXn pin as a 1 0 PWM 1 0 PWM output 11 Enable PWM Mode x10 or x16 fixed frequency Enable the CEXn pin as a PWM output Table 100 TCMMODE Register Configurations EINTF E_COMP CAP PE CAP NE MATCH TOGGLE TCM FUNCTION 0 0 0 0 0 ee No operation reset value 0 1 0 0 0 8 bit PWM fixed frequency 0 1 0 0 0 2 programmable 5 3 2 bit PMW fixed X 1 0 0 1 16 bit toggle X 1 0 0 1 16 bit Software Timer X X 0 1 0 16 bit capture negative trigger X X 1 0 0 16 bit capture positive trigger X X 1 1 0 0 0 0 16 bit capture transition trigger Note 1 10 bit PWM mode requires the 10B_PWM Bit in the PCACON Register set to 1 3 163 264 modules interface with each other at the 8032 Ad dress Data and Control interface blocks in Figure 62 see HARDWARE the uPSD34xx DESCRIPTION page 14 Details of the PSD Mod form The PSD Module is stacked with the MCU Module ule are shown in Figure 62 The two separate uPSD34xx PSD MODULE Figure 62 PSD Module Block Diagram PSD MODULE to NO Svir OL Al10454b 31naow asd JO svauv MOoVv8daad AGON mu mmm
351. uPSD34xx MCU BUS INTERFACE Figure 21 Connecting External Devices using Port A and an External Latch for Address AD 15 0 uPSD34xx MCU Module AD 15 8 PSD Module PSEN ALE RD or WR 110435 Programmable Bus Timing The length of the bus cycles are user programma ble at run time The number of MCU_CLK periods in a bus cycle can be specified in the SFR register named BUSCON see Table 37 page 65 By de fault the BUSCON Register is loaded with long bus cycle times 6 periods after a re set condition It is important that the post reset ini tialization firmware sets the bus cycle times appropriately to get the most performance ac cording to Table 38 page 66 Keep in mind that the PSD Module has a faster Turbo Mode default and a slower but less power consuming Non Tur bo Mode The bus cycle times must be pro grammed in BUSCON to optimize for each mode as shown in Table 38 See PSD Module Detailed Operation page 178 for more details It is not possible to specify in the BUSCON Regis ter a different number of MCU CLK periods for various address ranges For example the user cannot specify 4 MCU CLK periods for RD read cycles to one address range on the PSD Module and 5 MCU CLK periods for RD read cycles to a different address range on an external device However the user can specify one number of clock periods for PSEN read cycles and a different num
352. uc tions ACC is combined with the B Register to hold 16 bit operands The ACC is referred to as A in the MCU instruction set B Register B The B Register is a general purpose 8 bit register for temporary data storage and also used as a 16 bit register when concatenated with the ACC Reg ister for use with MUL and DIV instructions 1572 General Purpose Registers RO R7 There are four banks of eight general purpose 8 bit registers RO R7 but only one bank of eight registers is active at any given time depending on the setting in the PSW word described next RO R7 are generally used to assist in manipulating values and moving data from one memory location to another These register banks physically reside in the first 32 locations of 8032 internal DATA SRAM starting at address OOh At reset only the first bank of eight registers is active addresses OOh to 07h and the stack begins at address O8h Program Status Word PSW The PSW is an 8 bit register which stores several important bits or flags that are set and cleared by many 8032 instructions reflecting the current state of the MCU core Figure 12 page 23 shows the individual flags Carry Flag CY This flag is set when the last arithmetic operation that was executed results in a carry addition or borrow subtraction It is cleared by all other arithmetic operations The CY flag is also affected by Shift and Rotate Instruc tions Auxiliary Carry
353. uch as JTAG is a non intrusive way to gain access to the internal state of the 8032 MCU core and various memo ries A traditional external hardware emulator can not be completely effective on the uPSD34xx because of the Pre Fetch Queue and Branch Cache The nature of the PFQ and BC hide the visibility of actual program flow through traditional external bus connections thus requiring on chip serial debugging instead Debugging is supported by Windows PC based software tools used for 8051 code development from 3rd party vendors listed at www st com psm Debug capabilities include m Halt or Start MCU execution Reset the MCU Single Step 3 Match Breakpoints 1 Range Breakpoint inside or outside range Program Tracing Read or Modify MCU core registers DATA IDATA SFR XDATA and Code m External Debug Event Pin Input or Output Some key points regarding use of the JTAG De bugger The JTAG Debugger can access MCU registers data memory and code memory while the MCU is executing at full speed by cycle stealing This means watch windows may be displayed and periodically updated on the PC during full speed operation Registers and data content may also be modified during full speed operation 40 264 There is no on chip storage for Program Trace data but instead this data is scanned from the uPSD34xx through the JTAG channel at run time to the PC host for proccessing As such full speed program tracing is p
354. ule in second loop MOV A 02h set power down bit in the A Register but not in or PCON yet in first loop JMP LOOP uPSD enters into Power Down mode in second loop 3 221 264 uPSD34xx PSD MODULE Figure 89 Automatic Power Down APD Unit 8032 ADDR FROM MCU MODULE c3 8032 DATA FROM MCU MODULE BIT 1 FORCE PD 1 APD EN v 1 FOUND 1 ENABLE TRANSITION ENABLE 8032 ALE FULL v is PDN 1 1 8032 ADDR SS 8082 ADDR 8032 DATA gt lt gt EK gt gt 2 CLKIN pin PD1 gt pi Oo o D gt D A o m o 5 zi o 2 2 T o 2 m x 4 UJ x 2 2 e 5 o Q U Figure 90 Power Down Mode Flow Chart 222 264 Enable APD Set PMMRO Bit 1 2 1 ALE idle for 15 CLKIN clocks YES PDN 1 PSD Module in Power Down Mode 1PLDs by setting PMMRO bits 4 and 5 2 bits 2 through 6 i E 109183 CLEAR COUNT DOWN MODE 4 BIT APD FSx gt UP COUNTER CSBOOTx DPLD CHIP gt gt SELECT RSO EQUATIONS 22 CSIOP gt PDN OMCOUTPUTS AI06608B Chip Select Input CSI Pin PD2 of Port D can optionally be configured in PSDsoft Express as the PSD Module Chip Select Input CSI which is an active low logic input By default pin PD2 does not have the CSI function Whe
355. upt Flag UIF1 empty Once set firmware must clear the flag The USB IN FIFO Interrupt Flag register see by writing a 0 to the appropriate bit When Table 77 contains flags that indicate when an FIFOs are paired only the odd numbered IN Endpoint FIFO that was full becomes FIFO Interrupt flags are active Table 77 USB IN FIFO Interrupt Flag UIF1 OE9h Reset Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IN4F IN3F IN2F IN1F INOF Details Bit Symbol R W Definition 7 Reserved 6 Reserved 5 Reserved Endpoint 4 IN FIFO Interrupt flag 4 EAM This bit is set when the FIFO status changes from full to empty Endpoint 3 IN FIFO Interrupt flag INSE ii This bit is set when the FIFO status changes from full to empty Endpoint 2 IN FIFO Interrupt flag FAN This bit is set when the FIFO status changes from full to empty 1 IN1F R W Endpoint 1 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty 0 INOF R W Endpoint 0 IN FIFO Interrupt flag This bit is set when the FIFO status changes from full to empty 140 264 USB OUT FIFO Interrupt Flag UIF2 The USB OUT FIFO Interrupt Flag register see Table 78 contains flags that indicate uPSD34xx USB INTERFACE becomes full Once set firmware must clear the flag by writing a 0 to the appropriate bit When FIFOs are paired only the odd when an OUT Endpoint
356. ut High Time 9 10 ns Clock Input Low Time 10 ns tcoa Clock to Output Delay 21 10 2 ns tarmoa CPLD Array Delay Any macrocell 11 2 1 Minimum Clock Period 1 16 ns 248 264 uPSD34xx DC AND AC PARAMETERS Table 170 CPLD Macrocell Asynchronous Clock Mode Timing 3V PSD Module Symbol Parameter Conditions ESE ae eee ra Maximum Frequency Maximum Frequency E Maximum Frequency tHA Input Hold Time 12 ns Clock High Time 17 15 ns tcoa Clock to Output Delay 31 15 6 ns tARD CPLD Array Delay Any macrocell 20 4 ns Minimum Clock Period 1 36 ns ki 249 264 uPSD34xx DC AND AC PARAMETERS Figure 105 Input Macrocell Timing Product Term Clock tine PT CLOCK tis ty INPUT OUTPUT tino AI03101 Table 171 Input Macrocell Timing 5V PSD Module Symbol Parameter tis Input Setup Time NIE Input Hold Time NIB Input High Time tINL NIB Input Low Time tino NIB Input to Combinatorial Delay Note 1 34 2 10 ns Note 1 Inputs from Port A B and C relative to register latch clock from the PLD ALE AS latch timings refer to x and xax Table 172 Input Macrocell Timing 3V PSD Module Symbol Parameter Conditions Min Max rus px Unit tis Input Setup Time Note 1 0 ns Input Hold Time Note 1 25 15 ns tiNH NIB Input High Time Note 1 12 ns
357. value contained in Registers RCAP2L and RCAP2H which are pre set with firmware If EXEN2 1 then Timer 2 still does the above but with the added feature that a 1 to O transition at external input T2X will also trigger the 16 bit re load and set the interrupt flag EXF2 Again firm ware servicing the interrupt must read both TF2 and EXF2 to determine the cause and clear the flag s upon exit Note The uPSD34xx does not support selectable up down counting in Auto reload mode this fea ture was an extension to the original 8032 archi tecture 76 264 _ uPSD34xx STANDARD 8032 TIMER COUNTERS Table 43 T2CON Timer 2 Control Register SFR C8h reset value 2n Bit 7 TF2 Bit 6 EXF2 Bit 5 RCLK TCLK EXEN2 CP RL2 Details Bit Symbol TF2 R W R W Definition Timer 2 flag causes interrupt if enabled TF2 is set by hardware upon overflow Must be cleared by firmware TF2 will not be set when either RCLK or TCLK 1 EXF2 R W Timer 2 flag causes interrupt if enabled EXF2 is set when a capture or reload is caused by a negative transition on T2X pin and EXEN2 1 EXF2 must be cleared by firmware RCLK RW UARTO Receive Clock control When RCLK 1 UARTO uses Timer 2 overflow pulses for its receive clock in Modes 1 and 3 RCLK 0 Timer 1 overflow is used for its receive clock TCLK R W UARTO Transmit Clock control When TCLK 1 UARTO uses Timer 2
358. was just received Table 57 S1DAT Data Shift register SFR DEh reset value 00h Address Register S1ADR The S1ADR register Table 58 holds the 7 bit de vice address used when the SIOE is operating as a Slave When the SIOE receives an address from a Master it will compare this address to the con Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S1DAT 7 0 Details Bit Symbol R W Function Holds the data byte to be transmitted in Transmit mode or it holds the 59 S1DAT 7 0 RAW data byte received in Receiver mode If the 7 bits match the INTR Interrupt flag in S1STA is set and the ADDR Bit in S1CON is set The SIOE cannot modify the contents S1ADR and S1ADR is not used during Master mode tents of S1ADR as shown in Figure 43 page 102 Table 58 S1ADR Address register SFR DFh reset value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLAO Details Bit Symbol R W Function 7 1 SLA 6 0 R W Stores desired 7 bit device address used when SIOE is in Slave mode Not used 107 264 uPSD34xx IC INTERFACE START Sample Setting S1SETUP The S1SETUP register Table 59 determines how many times an bus START condition will be sampled before the SIOE validates the START condition giving the SIOE the ability to reject noise or illegal transmissions Becau
359. while the SIE is transmitting or receiving data in the paired buffer uPSD34xx supported endpoints and FIFOs are shown in Ta ble 68 Busy Bit BSY Operation Each FIFO has a busy bit BSY that indicates when the USB SIE has ownership of the FIFO When the SIE has ownership of the FIFO it is either writing data to or reading data from the FIFO The SIE writes data to the FIFO when it is receiving an OUT packet and reads data from the FIFO when it is sending data in response to an IN packet The CPU is only per mitted to access the FIFO when it is not busy and accesses to it while busy are ignored Once the IN FIFO has been written with data by the CPU the CPU updates the USIZE register with the number Table 68 uPSD34xx Supported Endpoints Endpoint Function uPSD34xx USB INTERFACE of bytes written to the FIFO The value written to the USIZE register tells the SIE the number of bytes to send to the host in response to an IN packet Once the USIZE register is written the FIFOs busy bit is set and remains set until the data has been transmitted in response to an IN packet The busy bit for an OUT FIFO is set as soon as the SIE starts receiving an OUT packet from the host Once all the data has been received and written to the FIFO the SIE clears the busy bit and writes the number of bytes received to the USIZE register Busy Bit and Interrupts When the FIFO s inter rupt is enabled a transition of the busy bit from a 1 to a
360. y reset The most significant byte of this counter is controlled by the SFR WDRST After being enabled by WDKEY the 24 bit count is in creased by 1 for each MCU machine cycle When the count overflows beyond FFFFFh 224 MCU machine cycles a reset is issued and the WDT is automatically disabled WDKEY 55h again To prevent the WDT from timing out and generat ing a reset firmware must repeatedly write some value to WDRST before the count reaches FFFFFh Whenever WDRST is written the upper 8 bits of the 24 bit counter are loaded with the writ ten value and the lower 16 bits of the counter are cleared to 0000h The WDT time out period can be adjusted by writ ing a value other that 00h to WDRST For exam ple if WDRST is written with 04h then the WDT will start counting 040000h 040001h 040002h and so on for each MCU machine cycle In this ex ample the WDT time out period is shorter than if WDRST was written with 00h because the WDT is an up counter A value for WDRST should never be written that results in a WDT time out period shorter than the time required to complete the longest code task in the application else unwant ed WDT overflows will occur 23 15 7 0 SFR WORST 109604 68 264 The formula to determine WDT time out period is WDTpERIOD _ X NovERFLOW NoverRFLow is the number of WDT up counts re quired to reach FFFFFFh This is determined by the value written to t

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