NIM 3001
Contents
1. trioga cs only inust be inhibit 1s measure ento amum pulse woth 10 Anta ge of iF eof 7 esec 3 gate pulse for Threshold Operating Mode Trigger Mode Continuous Stop at Overflow Intensify Display LIN LOG Start Stop Clear Memory Select Full 4 34 4 Vertical Gain FRONT PANEL INPUTS Q Input V input Gate Input Output Inhibit Stop FRONT PANEL OUTPUTS Threshold Test Point Internal Gate Vens internal Gate Test Point SEAR PANEL OUTPUTS amory C ow 22 External crete 4 External Memory Adaress Laich A Memory En able 21 External Load N Front panel screwdriver adjustable potentiometer determines threshold setting in internal trigger INT mode Range 1 mV to 15 mV in O mode 1 mV to 15 mV in V mode Front panel monitor point gives output voltage equal to 1000X actual threshold setting Threshold stability lt 0 2 C over 20 C to 60 C operating range One of the three analysis modes Q V or T is selected by a 3 position switch A 3 position switch selects internal trigger operation INT External Trigger operation EXT TRIG or operation via an externally applied gate pulse EXT GATE A 2 position switch either permits continuous data collection and display or limits each channel to a full scale capacity Either every 10th or every 50th channel is intensified on the display determined by a front panel 2 position switch Sel2. umoer 1 01 4 Q n F 4 ied States of Ainsrica Al ris uw electronic or mechanical Plon storage PHY SICS 111 LAB 286 Le Conte Hall U C BERKELEY COPY MBE y NIM MODEL 3001 QVT MULTICHANNEL ANALYZER UOA PHYSICS 111 LAB 286 Le Conte Hall U C BERKELEY COPY JON E as a rights reserved Contents of not ve reproduced in any form or gt y any means including photocopying reo a e end retrieval systems without the writt GENERAL PRODUCT WARRANTY LeCroy Research Systems warrants operation of its products within published specifications for a period of one year from the date of shipment This warranty is provisional on the correct and proper use of the equipment as expressed in the operation manual accom panying that product If during this period a product is found to be defective it should be returned to the factory or for European customers to the nearest authorized European service location for repair or replacement at the discretion of LeCroy The customer must pay shipping charges for the return of any equipment to the factory or authorized sege location LeCroy will pay the return shipping charges for in warranty repairs OEM PRODUCTS The above general one year warranty applies only to equipment desrgned and manufactured by LeCroy Research Systems All non LeCroy products which accompany or are provided with a System are covered by the Original Equipment Manufacturers
3. 2 each time the Model 3001 gate generator is fired The INHIBIT IN connector allows the output of the internal discriminator to be inhibited The INHIBIT pulse a NIM fast pulse should overlap the gate for proper operation The GATE INHIBIT inputs are ignored after conversion is begun EXT Trigger Mode Operation in the EXT TRIG Mode is intended for ap plications in which a somewhat more extensive trigger is required In this mode a NIM fast pulse applied to the GATE INPUT is used to trigger the internal gate generator The INHIBIT IN input accepts NIM fast pulses which may be used to veto the trigger The internal discrim inator is therefore defeated in this mode The leading edge of the gate trigger pulse shouid be coincident in time with the leading edge of the analog input at the V INPUT connector A fast NIM inhibit pulse of minimum 10 nsec duration should be applied simultaneous with the leading edge of the GATE TRIGGER pulse in order to inhibit conversion The GATE and INHIBIT inputs are ignored after conversion is begun 5 EXT GATE Mode In the EXT GATE Mode the 3001 accepts an external gate pulse rather than employing the internal gate generator In fact the WIDTH setting has no effect on performance in this mode The peak search time in this mode is equal to the width of the gate pulse Gat as short as 100 nsec may be used Because of internal delays the leading edge of a
4. Busy out Operating Modes q Mode q Mode Gating The Gate Generator INT Trigger Mode EXT Trigger Mode EXT Gate Mode q Mode Input Signals q Mode Pedestal and Slope V Mode Mode Gating The Gate Generator INT Trigger Mode EXT Trigger Mode EXT Gate Mode V Mode Input Signals V Mode Slope and Pedestal t Mode So SCO COO OH OD DD oes eR 0 00 WG DD DS DO Functional Desciption 9 as alog Front End 9 Digital Section 10 Display Section 10 Con t TABLE OF CONTENTS Continued Appendix 1 QVT System Interface Connections 111 Page 12 14 wiar eama rn E h y r MYX 710 577 2832 PET TERRE A Ge tee NIM Model 3001 Multichannel Analyzer The Model 3001 is a research grade multichannel analyzer which provides excep tional versatility at relatively low cost The Model 3001 features 3 Mode Analysis Charge Q area and voltage V peak analog to digital con version and time to dioital conversion T start stop modes mean direct com patibility with photomultiplier anodes and elimination of charge sensitive preamps and time to amplitude converters TAC s High Sensitivity Cl 0 25 pC sensitivity in charge mode V 1 mV resolution in peak mode 0 to 1 or 0 to 10 volt inputs and T 100 psec resolution in time mode mean direct compatibility with low level signals from a variety of sources and the ability to precisely measure short tim
5. Cee ONE For direct digitizing of photo For use aS a conventional For Start Stop timing meas multiplier anode current Puise Height Analyzer Ac urements Not multisclaing pulses No charge sensitive cepts positive volage signals No TAC necessary i vired m or de levels SPECIFICATIONS NIM Model 3001 at MULTICHANNEL ANALYZER GENERAL OPERATIONAL CHARACTERISTICS Analysts Modes Number of Channels Memory Size Digitizing Time Temperature Stability Long Term Stability Integral Non linearity Display Channel Intensification PHYSICAL CHARACTERISTICS Packaging onag zs Used Current Requirements Finn Co nectors INPUT CHARACTERISTICS talog inca O and V des External Gate External Trigger Start Internal Gate View wat Ep CARTE VEL CON SOLS p oe O Rance 120 to 1120 nsec Q Current Integrating charge sensitive integration interval 20 nsec to 1 Sec full scale 256 pC 10 sensitivity 0 25 pC channel V Peak voltage input signal risetime gt 50 nsec full scale 1 volt or 10 volt 10 resolution mV or 10 mV channel external gate width 100 nsec minimum to 1 sec or switch selectable 5 sec maximum T Time interval Start Stop full scale internally swatch selectable 102 or 1024 nsec 10 resolu tion 100 psec and 1 nsec respectively 1024 lo bits 256 8 bits in quadrants overflow counts are stored rn the last address of the selected memory
6. Stat the memory output and prev it from being written into TIL high enables memory in or output Low level permits loading external data into the In crementing Register Input data must be quiescent and should be low until external load EXT LD is returned high state EXT LD must be high during write interval External Load X X EXT LD N External data ED00 to ED1 is loaded into the Increment ing Register by trailing ec of a low going TTL compatible pulse 200 nsec minimum dura tion Data must be quiescent during load interval See Note Increment Register X INCR REG P The contents of MCA s Incrc menting Register is increment by 1 by the positive going transition of the INCR REG pulse a TTL compatible 200 nsec minimum width pulse When unused must be a TTL high during EXT ENB See Note June 1977 15 ENGINEERING DEPARTMENT LeCroy Research Systems Cc 2301 3157 Signal Designation External eS Read Write X R W External Memory Address Latch X Xx MAL External Data Input Data Output X ED00 NOTE The signals EXT LD INC REG interval that EXT ENB is low June 1977 technical information manual J2 Connector Contact Usage Pin No b P S Characteristic The contents of the Increment ing Register are written into the memory of minimum duration 600 nsec The R W must be high f
7. a conversion with the V INPUT open Although S is fixed No is not Increasing the gate width will effect the pedestal in the V Mode only slightly t Mode In the t MODE tie GATE switch must be in the EXT TRIG position In this mode the GATE TRIG input is the T START input and the INHIBIT input is the T STOP input The time between the T START and T STOP pulses is digi tized without the use of a time to amplitude converter TAC A side panel switch is used to select the full scale time Two ranges are available 100 nsec full scale 0 to 100 nsec and 1 usec full scale 100 nsec to 1100 nsec Two spare switch positions are supplied to allow selection or alternate conversion gains Full scale time may range OPERATION from 100 nsec minimum to 7 usec maximum Selection of resistance values for alternate gains is based on the following relationships GAIN S 10 sec channel 9 where 10 ne sec chan lt GAIN 6 x 10 sec chan and where R is expressed in Dhns A pedestal of approximately 14 of full scale must be provided externally because of the inherent negative pedestal of the system Therefore a selected gain of 6 x 1079 sec count will range from 2 84 usec to 6 84 usec full scale Pedestal external 2 140 x GAIN At any time of operation only one time range should be selected Th following diagram illustrates positions for alternate conversion gain components Access
8. analog front end of the q MODE section of the 3001 is shown in Fig 2 A gate pulse inter nally or externally generated activates the linear gate and allows the current at the Q INPUT to be integrated on the capacitor C Thus the analog pulse height is stored for ADC Since the input to the amplifier is a virtual ground the input impedance of the Q INPUT is 50 Q This mode exhibits best stability when driven from source impedances gt 1 KR such as a photomultiplier SIG NT il TINN GNC 2 6 5ND OUT A ee vat E AN i A Maag Hoo o S LIN I a AMP gt o oe 2 Te J S sate na SME s e S CONST g CURA SOURCE eno ee e lt lt AA AE POL Aa EDO TESTO ANC BAMP CAN OPERATION q Mode Gating An internal gate generator may be used to generate gates an by An as The Gate Generator potentiometer width of approxima gt 1 psec The act gate pulse at the In the INT mode put of the gate pulse wi test point and GATE gate generator INT Trigger Mode inator on the analog ual ga test point adjacent to the GATE WIDTH potentiometer INPUT GATE VIEW connector serves as an out h an amplitude of approximately 100 mV The he GAT in the q MODE internal discriminator o an externally applied NI externally applied NIM the gate pulse P EXT GATE This generator may be triggered either by perating on the analog input sign
9. edge decrements Incrementing _Reg ister Internal pull up is provided A TTL low of 500 nsec duration indicates the data in the Incrementing Register is zero A TTL output indicating the state of the qgVt Low for stopped high for started ENGINEERING DEPARTMENT LeCroy Research Systems Corp Spriny Valley New York technic SEA A Digital Input Output The digital connector J2 on the 3001 is a 44 contact edge connector which mates with AMP connector number 582358 2 The contacts are named A thru Z excluding G I 0 and Q and 1 through 22 The extreme contacts A Z 1 and 22 are labeled on the board All signals are TTL standard Read out writing in and histogramming may be performed through this connector The details and definitions of each of the 44 input or output requirements are described in the next section A block diagram of the memory and register section of the 3001 is shown in figure 3 32 CONNECT OF RW ME MA LINES 10 MAL ED LINES 16 EXT LD NCR Reg Eiga US Data may be read from or written into any channel of the 3001 by latching an address into the Memory Address Latch and supplying the appropriate strobes Latching Into The Memory Address Latch In order to read out or write into the memory of the 3001 it is necessary to latch an address into the Memory Address Latch Tne procedure is shown in figure 4 The memory address lines should be driven from either an open
10. segment 16 bits 1 per channel 65 535 counts 12 psec 0 05 secichannel t 03 of full scale 0 2 of full scale week maximum 0 25 of reading 2 channels 100 sweeps second Every 10th or 50th channel front panel selectable 2 width RF shielded NIM standard module conforming to specifications outlined in AEC Report TID 20893 24 volts 12 volts Note a rear panel switch permits operation from volts to available instead of 12 volts 24 Vat24 mA 24 V at 125mA 12 V at 06 mA 12 Vat 127 mA 6 V at 1 35 A 6 Vat 510 mA Mote 1 8 Vrequrcne v s addio 112 Vreg remens when 26 Vepios s unused BNC OF got mugied z Qin Vanse Dalis oa OT ine fort psec linear range Cto 4 Cin V mide One Common tront panel commecior fura ira arm iis sanch requires 600 mV signal into 50 9 Q and V Modes In External Gate EXT CATE mode the is Qual to ihe duration of the gate pulse applied to this connector in External Trigger moda EXT TRIG the nizina gate s 2 cing atge ofa test NIM signal epphed ie ihis connector min any E mal INT rodea the imermaeistce ested cz coat us connector tude 100 mV Q Mode Usabie cate duration 20 nsec to asec V Mode Minimum duration 100 nsec Maximum curation sec Pas 7 si encilese peak of input signal to be measured T Mode The leading edge of Stan input begins the sian stop 1 measurement minimum pulse widih 10 nsec Extema
11. to the PC board illustrated below is gained by sliding back the right hand side cover having the cutout that exposes the t mode range select switch For best results use a 1 resistor value A second resistor position is provided in each of the two alternate gain locations for a fine trim of the gain if desired A A TSAN A aT e p Area RTE SOT AES SE Ea OE A A Al O a ee EP le na el gt FUNCTIONAL DESCRIPTION alog Front End DH mh O H O RK HO t oO to e operation of the 3001 is shown by the block diagram in Fig 1 The DC employed is a run down type consisting of three separate front ends e of which is selected to gate clock pulses to a scaler The three ront ends are the hybrid circuits QTIOOC VT100 and QT1OOT used for e q V and t modes respectively See page 2 of the schematic diagram e QT1OOC and QT1OOT are charge to time converters consisting of virtual ground inputs Pin 16 capable of current amplifying the input lse received during the time that a gate gt 12 V is applied to Pin 15 11 scale charge is about 300 pC and 1500 pC for the QT1OOC and QT1OOT spectively When a gate pulse is received by either of these hybrids internal capacitor is charged and a run down is begun For the dura ion of the run down a TTL clamp to ground is present at Pin 9 This output width is proportional to the amount of charge transferred the ca
12. used to veto the trigger The internal discriminator is therefore defeated in this 3 nsec after the leading edge of the analog input E VIEW connector serves as gate view n should be applied simultaneous with nput pulse at the Q INPUT to inhibit the EXT TRIG Mode is intended for appli extensive trigger is required In this E pulse applied to the GATE INPUT is used to trigger the generator HIBIT IN input accepts NIM fast pulses The leading edge of the gate trigger at the Q INPUT connector eat LTS REN a o do a orc ae ieee a a PA ici a E LR Semmes e te OPERATION A fast NIM inhibit pulse of minimum 10 nsec duration should be applied simultaneous with the leading edge of the GATE TRIGGER pulse in order to inhibit conversion The GATE and INHIBIT inputs are ignored after conversion is begun EXT GATE Mode In the EXT GATE Mode the 3001 accepts an external gate pulse rather than employing the internal gate generator In fact the WIDTH setting has no effect on performance in this mode The integration time in this mode is equal to the width of the gate pulse Gates as short as 10 nsec may be used Because of internal delays the leading edge of a NIM fast pulsemust be applied to the GATE INPUT 3 nsec after the leading edge of the Q INPUT analog pulse Note that THIS REQUIRES 5 NSEC OF ADDITIONAL SIGNAL DELAY as compared with LRS Model 2249A operation The I
13. warranty which is typically 90 days from the date of shipment In some cir cumstances and for out of warranty repair It may be more ex peditious to contact the OEM set vice facility directly OEM product warranties and service locations are listed below Model 39314 Printer Plotter Hi G Co Inc Printer Products Service Center 580 Spring Street Windsor Locks Connecticut 06096 Telephone 203 623 3363 Warranty Period 1 Year Model 3500 35 Quad Serial Interface Central Data Corporation 1592 Newton Drive Champaign IL 67821 1098 217 382 5010 Warranty Period 1 Year tt adel 3500 57 Time and Date Unit Model spag Ploter Printer Ents 23 G S Interface e 10 Court mo DA 32401 caranty Feriod 1 Year Waranty penod 1 Year Model 3500 39 Bubble Memory Intel Products Service 2402 West Beardsley Road Phoenix Arizona 65027 800 528 0595 Warranty Period 90 Days Model 3955 Streaming Tape Drive Model Rimfire 38A Hard Disk Warranty Period 1 Year Controller Computer Products Corporation 3405 Annapolis Lane P lymouth MN 55441 2 2034 remy Penoc 0 Days Model DPP 7 Printer Cate Intersil el 2821 Dual Fioppy Disk Drive Sys ems inc waranty Period 1 Year SOFTWARE LeCroy warrants only software and firmware which has been written and developed by LeCroy LeCroy assumes no responsibility for user written software When a customer encounters a problem with L
14. 0 nsec to 1 sec A front panel adjustable internal gate is generated by either an internal or an external trigger or an external gate pulse may be directly applied to the MCA Operating in the Internal mode the Model 3001 is a stand alone device possessing an internal discriminator of 1 mV minimum threshold The Q input is terminated in 50 Q and all analog circuitry is dc coupled thus eliminating the need for dc restoration instrumentation The 10 bit TDC used for the T time mode of the Model 3001 digitizes time intervals by the start stop technique and stores their spectra Full scale time intervals are 102 nsec and 1024 nsec offering respective resolutions of 100 psec channel and 1 nsec channel The start and stop inputs are ieading edge triggered responding to NIM negative signals Uses of the T mode include time of flight counter timing and delay measurement time correlation spectra and drift chamber calibration nthe V CERON mode the output of any voltage source e g acharge sensitive pregi piter may 32 29a TS J SEU E ak woliage of signals gt 50 nsec rissti ime apptied to the input a te gae pla ls Ed tnu naking external sireiching circuits unnscessary The full scale input i the y node siai n ae Vis ares selectable overing a resolution of 1 mV 19 mV consistent with that of a SL cetecior The in nal gate may be extended to 5 sec in this mode DUDIK ODE VOLTAGE MODE LAA PEAK NIM BIN c
15. INPUT is 93 R the gate timing is less the GATE the GATE INPUT GATE an amplit triggered tor is a triggerable front panel GATE WIDTH ise this control sets a gate ully clockwise width for V MODE operation is 100 nsec n be determined by viewing the NIM gate WIDTH potentiometer VIEW connector serves as an Out ude of approximately 100 mY Because An internal gate generator may be used to generate gates j This generator may by an internal discriminator on the analog input signal externally applied NIM fast logic pulse on the GATE INPUT NIM pulse derived from estemal logic may be applied EXT GATE be triggered either INT or by an EXT TRIG An monostable it sets a width The VIEW outputs supply gate pulses whenever A OPERATION INT Trigger Mode In the INT GATE trigger mode an internal discrim inator on the analog signal is used to trigger the gate generator The discriminator level is set by the 22 turn THRESH potentiometer Set fully counter clockwise a threshold of approximately 1 mV is ob tained Fully clockwise the threshold is approximately 20 mV The test point adjacent to the input THRESH potentiometer gives a voltage approximately 1000 X the threshold No connection should be made to the Q INPUT In this mode the GATE INPUT GATE VIEW connector serves as a gate view output giving a 100 mV amplitude gate output into 50
16. NHIBIT INPUT requires a NIM fast pulse of 10 nsec minimum duration in order to inhibit the gate pulse The leading edge of the Inhibit pulse should be coincident with the leading edge of the gate pulse After conversion has begun the GATE and INHIBIT inputs are ignored a MODE Input Signals The Q INPUT is terminated in 50 Q Because of the high speed nature of this mode attention should be paid to proper impedance matching throughout the system The reflec tions caused by impedance mismatches will cause a loss of resolution The Q INPUT accepts negative analog signals Signals as large as 20 mA 1 V into 50 Q are handled linearly Larger signals cause a gradual deviation from linearity Two volt input signals for example register approximately 10 lower than 1 V signals of twice the duration The input is protected against de 100 V transients of duration lt l usec Although such transients will not cause circuit damage they may however Cause the data in the analyzer to become disturbed q Mode Slope and Pedestal The action of the charge sensitive ADC in the Model 3002 is to produce a digital output related to the input charge q by the relationship q S N No N gt Nq Here S is the slope approximately 0 25 pC count ox 1 pC count in the full a or quadrant modes respectively obtained for a conversion with no Q signal the output impedance of the signal source
17. NIM fast pulse applied to the GATE INPUT should be coincident with the leading edge of the V INPUT analog pulse The INHIBIT INPUT pulse will veto a gate pulse if a NIM fast level is pr sent coincident with the leading edge of a gate pulse and persists for at least 10 nsec o and as ce cie e Borra bl Aura OPERATION V Mode Input Signals The V INPUT is terminated in 93 Q and accepts input signals of 50 nsec risetime or greater Generally gaussian shaped pulses are used as analog inputs but the 3001 allows other shapes also For example a ramp input may be used If no peak is obtained during the gating interval the maximum voltage will be analyzed The V INPUT accepts positive analog signals The range of the ADC for this mode allows signals to 1 V into 93 Q Larger signals give an off scale result and are treated as a full scale ch 1024 signal The input is protected against 100 V transients of lt 1 usec duration Al though such transients will not cause circuit damage they may however cause the data in the analyzer to become disturbed V Mode Slope and Pedestal The action of the peak sensing ADC in the Model 3001 is to produce a digital output N related to largest voltage in the gate interval by V S N No N gt No Here S is the slope approximately 1 mV count or 4 mV count in the full or quadrant modes respectively NO is the pedestal or the channel num ber obtained for
18. NO is the pedestal or the channel Pedestal also depends Although S is fixed NO is OPERATION number upon not Increasing the gate width will cause an increase in the pedestal s nclosed specifications tal board adjacent to the QT100C hybrid affords pedestal adjustment a range of approximately 50 counts is advantageous in that it allows th origin of his histogram In general xperimenter to be aware of the This is of particular significance for A trimmer capacitor mounted on the digi over a pedestal gt 0 counts the Model 3001 in that it maintains linearity even in the first few channels above pedestal v Mode The V Mode is intended for analysis of the output of voltage sources such as spectroscopic amplifiers or Mossbauer velocity drives Analog to digital conversion is performed upon the maximum voltage within the gating interval the V INPUT is intended for slower signals critical V Mode Gating in externally applied as the gate pulse The Gate Generator the V MODE The gate genera whose output may be adjusted by a 22 turn potentiometer width of approximately 20 nsec and f The minimum gate gt 1 psec The actual gate width ca pulse at the test point in the INT mode put of the gate pulse with test point and GATE the gate generator is Fully counter clockw adjacent to The input impedance of the V
19. al INT or fast logic pulse on the GATE INPUT EXI TRIG ulse derived from external logic may be applied The gate generator is a triggerable monostable whose output may be adjusted by a 22 turn front panel GATE WIDTH Fully counter clockwise this control sets a gate tely 20 nsec and fully clockwise it sets a width te width can be determined by viewing the NIM e h ri EW outputs supply gate pulses whenever th gered the TNT GATE trigger mode an internal discrim Signal is used to trigger the gate generator The discriminator level is set by the 22 turn THRESH potentiometer Set fully counter cl Fully clockwise adjacent to the 1000 x the threshold In this node output giving a the 3001 gate the output of th lockwise threshold i t THRI No hold of approximately 1 mV is obtained s approximately 20 mV The test point ESH potentiometer gives a voltage approximately tion should Se made to the V INPUT INPUT GAT mV amplitude gate output into 50 Q each time is fired The INHIBIT IN ccnnsctor allows e internal discriminator to be inhibited A NIM fast pulse of 10 nsec minimum the leading edge of the analog i The GATE INHIBIT EXT Trigger Mode pulse should inputs are ignored after conversion is begun Operation in cations in which a somewhat more ode a NIM fast internal gate which may be
20. but 210 bit X ED11 16 As above but 211 bit X ED12 18 As above but 21 pit e X ED13 17 As above but 213 pit X ED14 19 As above but 21 bit X ED15 20 As above but 215 bit Memory Overflow X MO F 22 A high level output indicate an overflow in the 16th bit of the memory Clock Inhibit X CK INH 1 A high TTL inhibits internal clock halting operation use to generate an intensified display marker provided in hibit is synchronous with dis play sweep June 1977 Slys ENGINEERING DEPARTMENT LeCroy Research Systems C gt D Signal A a Designation ADC Data SEL Clear qvt X CLR Start qVvt X START stop qvt X STOP Display Clock X DCLK Display Reset X DR Decrement Register X DREG Zero Register X ZREG qvt Status X STATUS Common Xx Xx GND June 1977 eE 18 technical information manual J2 Connector Contact Usage Characteristic Active Low TTL signal of 200 nsec duration indicates ADC data is present on pins A to L TTL low level of 100 msec minimum duration clears the qvt EXT EN not required TTL low of 2 usec minimum dur ation starts the qVt EXT EN not required TTL low of 2 psec minimum dur ation stops the qgVt EXT EN not required TTL level display 50 kHz 400 nsec wide clock pulses available when clock inhibit is low TTL low of 500 nsec duration indicates that the display sweep has begun Positive going TTL
21. ch sold to be determined by LeCroy LeCroy shall not be responsible for failure to provide replacement parts due to causes beyond its control Including strikes of labor stoppages or acts of God or be required to adjust or repair any equipment or part if it would be impractical to do so because of the alterations in the equipment or its connection by electrical or mechanical means to another machine or device This warranty shall become void if customer fails to operate equip mentin accordance with LeCroy written instructions or in case of disc drive read write reads if customer uses other than approved magnetic recording meda Approved media shall be only diskettes manufactured to quality standardsequal to or exceeding those of diskettes manufactured by International Business Machines IBM and Dysan This warranty is in and all other warranties expressed by implied regarding the equipment supplied hereunder including any regarding merchantability or fitness for a particular purpose This warranty apples only to end user customers of LeCroy LeCroy reserves the right to make changes without prior notice and without incurring obligations LeCALY RISTARCH SYSTEMS CORPORATION 790 SOUTH MAN STAEET SPRING VALLEY N Y 10977 314 426 2000 EI EA A PHYSICS HAB 286 Le Conte Hal U C BERKELEY In general LeCroy provides factory service only from its Spring Valley New York facility Service for customers in New Mexico Sout
22. collector or tri state source activated by a low level on the external line June 1977 19 ENGINEERING DEPARTMENT Read Out See Figure 4 Data Ef E latc 400 the ED lines for the duration of the he state of the R W line is high hed into the Memory Address Latch will settle on the nsec of the trailing edge of the MAL pulse technical information manual the data contained in the address EXT cat 1 00 aa gt 200 NSEC gt EXT MAL FIGURE June 1977 20 ED lines within Data levels persist on ENB level o CA 7 7 7 7 WEES TRI STATE ey aw NM A dd Z ENB ENGINEERING DEPARTMENT LeCroy Research Systems Corp Spring Valley New York technica information ee Writing Into the Model 3001 See Figure 5 In order to write into the Model 3001 data must also be latched into the Incrementing Register by an EXT LD pulse Data levels may be set on the ED lines only after the memory is disabled ME low hs SLT 3 FITITITIT TT ED AND 7 ee V E LEVEL SET ese VA ERA 0 MA LINES LLL LDL S LLALL Do E ATA LS AL ME lt gt 200 nsec gt EXT LD c enan AOS T R W 2400 NSEC k 2100 NSEC FIGURE 5 June 1977 aes
23. d from the users of our equipment the Engineering Department at LeCroy is continually seeking to refineandimprove the performance of our products While the actual physical modifications or changes necessary to improve a model s operation can be implemented quite rap idly the corrected documentation associated with the unit usually requires more time to produce Consequently this manual may not agree in every detail with the accompanying unit There may be small discrepancies that were brought about by customer prompted engineering changes or by changes determined during calibration in our Test Department These differences usually are changes in the values of components for the purposes of pulse shape timing offset etc and only rarely include minor logic changes Where any such in consistencies exist please be assured that the unit is cor rect and incorporates the most up to date circuitry When ever original discrepancies exist fully updated documenta tion should be available upon your request within a month after your receipt of the unit e or operation from our En E ing Valley NY telephone 214 425 2000 or from your local distritutor in countries other than the U S A LECROY RESEARCH SYSTEM PHYSICS 111 LAB 286 Le Conte Hall U C BERKELEY COPY TABLE OF CONTENTS Page Introduction 1 Operation Fower Display Accumulation and Memory Clear Memory Control
24. e high speed pulse in a NIM system The entire analyzer is packaged in a double NIM module and is otherwise self contained requiring only an addition of a standard X Y display oscilloscope to form a complete analysis system The MCA offers three operational modes permitting measurement of total charge positive peak voltage and time intervals Capability for generating internal qating for the first two modes is provided by inclusion of a low threshold discriminator set to detect levels down to 1 mV The width of the in ternally generated gate may be adjusted by means of a multi turn front panel control The analog to digital converter of the MCA provides a resolution of 1024 channels with an integral linearity of 0 25 The converted data is stored in a 1024 x 16 bit semiconductor memory which may be used either in its full or quadrant configuration This feature provides capability for storage and subsequent retrieval of up to four 256 channel spectra All overflow events are stored in the 1024th channel A high speed flickerless display with a repetition rate of approximately 100 sweeps per second presents the memory contents in real tim whil the measure ment is in progress providing a constant monitoring facility The digitally generated analog output can be displayed in linear format or in a log compressed format The log format allows channels with only 1 count to be diff
25. e intervals Segmentable Memory 4 x 256 quadrants or 1 x 1024 full scale gives the flexibility to accumulate display and compare up to four different spectra or to display quadrants of a full 1024 channel spectrum lt High Count Capacity 2116 1 65 535 counts capacity permits enough data accumulation to satisfy applications including cosmic ray and high energy experiments and many nuclear spectroscopy ane Mossbauer applications Nanosecond Logic Functions Internal trigger ing mode permits the 3001 to be used as a stand alone device while the external modes permit either internal gate generation upon application of an external trigger or direct application of an exter nal gate signal e Choice of 1 0 imiedaces inmough accessor 7sdulgs ic an X Y plotter line printer or the CAMAC une Compact Packaging Complete 1024 channel analyzer compactly packaged in a 2 NIM standard module gives greater portabilityt lower cost and enhanced reliability Drives Any X Y Scope The use of the 3001 w 2 any external X Y scope in your ab means sma er basic analyzer size gre2 e mobility and saves you the synense of 2b in scope which you may have available February 1983 DRED ANY 700 SOUTH MAIN STREET SPRING VALLEY N Y 10977 CABLE LERESCO TELEPHONE 314 425 2000 GENERAL DESCRIPTION The Model 3001 is a new low cost 1024 channel multichannel analyzer offering three analysis
26. eCroy developed software a System 3500 Software Firmware Problem Report provided in the Operator s Manual should be sub mitted to LeCroy in which the customer identifies the Program and Version Number and defines the problem LeCroy will respond to the Problem Report within two weeks of receipt and if the problem is in the software will resolve the problem by issuing a new software release In some cases a solution may be provided to the customer by lelephone LeCroy s responsibility in the event of software defects is limited to resolution of the problem by correction and or replacement of the defective software INSTALLATION Installation of equipment purchased from LeCroy will be the respon sibility of the customer unless installation arrangements and terms are defined at the time of purchase WARRANTY EXCLUSIONS The foregoing warranties will not apply to replacement or repairs of parts whose failure is caused by accident transportation neglect misuse intentional damage alterations which shall include but not be limited to any change in circuit or structural equipment design as provided by LeCroy installation or removal of LeCroy features or any other modification or maintenance related activities Whenever any of the foregoing are performed by other than LeCroy representatives any machine or device other than those sold by LeCroy or the use of the equipment for other than data acquisition and or processing purposes for whi
27. ects linear or logarithmic display Front panel two position spring return toggle switch Start position initiates new measurement cycle after a Stop or Clear Stop position stops measurement cycle Front panel spring return toggle clears all memory and register simultaneously placed in stop position In the Full position all 1024 channels accept and display input data In the 1 position the first quadrant 256 channels accepts and displays input data Full scale range settings remain the same i e 256 pC 1 volt and 102 or 1024 nsec srmiiar for Y Ya In LIN linear mode an e position switch selects a maximum number of counts to be displayed per channel between 512 and 65 k Star Stop switch must be Analog input 50 Q impedance dc coupled Accepts input charge of O to 256 pC Protected to 100 volts Analog input 50 2 impedance 93 optional Accepts inpu voltage of 0 to 1 V with switch selection O to 10 V range Protected to 100 volts Multifunctional connector Acts as trigger or gate input output in Qor V mode Acts as Start input in T mode Input impedance 50 Accepts NIM fast signals See detailed specifications Accepts fast NIM signals Ads as inhibit in Qor V mode and slop input in T mode Impedance 50 2 Reads 1300X preset threshold value in internal mode operation internally generated gate is available for oscilloscope monitoring on the Gate Connector when Inter nal Trigger is selected Am
28. el 3001 supply 0 to 5 0 V Intensification of every 10th or 50th channel is selected by the INTENSIFICATION Switch Channel intensification is accomplished by pausing Any oscilloscope capable of X Y operation may be used The oscilloscope should be used with unterminated high impedance inputs to use the 0 to 5 0 V calibration of the 3001 s outputs he DISPLAY SCALE switch selects the mode of display In the LIN position T the display is linear with a full scale 5 0 V as set by the COUNTS FULL SCALE switch In the LOG position the display is logarithmic the 5 0 V corresponding to LOG 65 5 K counts In the LOG display mode the COUNTS FULL SCALE switch is inactive Accumulation and Memory Clear After the START STOP switch is placed in the STARI position the Model 3001 will accept Jata It will remain live until it receives a STOP command When the MEASURE_ switch is in the STOP AT OVERFLOW position the analyzer generates a STOP when the contents of any channel exceeds the capacity of the memory 1 1 A STOP command is also generated when th START STOP switch is placed in the STOP position if the MEASURE switch is in CONTINUE the analyzer memory will oveflow but will continue acquisition The memory display of the 3001 remains active at all times A slight flicker is discernable only at very high input rates The portion of memory in use full
29. erentiated from zero while also displaying a full scale channel e e o cr e indino 8 WINOZTYOH LAdino WOPLYAA 2490 907 N1 1 O gt H9J1Uu71 wa y UNY XNA YUH We AS A Be QUINI I 301 i 390 os 7 Se 4345 YO LYHIN 4 Pl a TT SOLSZ 1 frre QTOHSAIYUHL Tignan SVT WEHISIO YOJUNINIO YUIUYHINAID Pee AE TO NA USSI INUN Deus earn 19013 AGA 401 UAW 7HNDO 1 Y IV 4 j thetunt NS 21yon A 4109 lt A do mn 90 1 Nf 1 1301 S544004 i AVISEN p ANT OL ratas autasia_ PT JOUYHO 130711 Mg Aupa a HOLE sng H Se O a ball P rro T NERO 1 E UV IIS i Y JLYIANOD 1 ssayany aa 30 91XbzZ0 EEN dl Se de ABONA Y Ss rf A eo 8315 9334 ONTININIYINI 3NTL Ol zg ty Ae CEN td ee r ALISNJINT G 1y j ass agro UIC beware tk A eee pe 944 LATHS amp o E xn 5 HIS MALYAANOD gt UALYAANDI ANT QL JOUY a ee 300 l t V 1907 NI 190R UIU So dues AUOWAN A A IPE ACE LAN WYHIYIA A90 70 eo mos OPERATION Power The Model 3001 utilized 6 V 12 V and 224 V Because some NIM bins do not supply 6 V 6 V supplies operating off of the 12 V supplies have been incorporated in the qt A rear panel switch selects this feature Note that the current required for the 6 V sections is then drawn from the 12 V supplies Display The HORIZ OUT and VERT OUT connectors of the Mod
30. hern Nevada Arizona Colorado and EIl Paso County Texas is provided at this Branch Office LeCROY RESEARCH SYSTEMS CORPORATION New Mexico Service Facility 14800 Central Avenue SE Albuquerque New Mexico 87123 For European customers service is also provided at the following LeCroy Branch Offices LeCROY RESEARCH SYSTEMS SA European Products Division Rue Cardinal Journet 27 1217 Meyrin 1 Geneva Switzerland Telephone 022 82 33 55 Telex 28230 LeCROY RESEARCH SYSTEMS LTD Elms Court Botley Oxford CX2 9LP U K Telephone 0865 72 72 75 Telex 837539 Telephone of 907 38 97 Teiex 652 838 OY ii a cnke S 2200 Heidelberg Y Germany Felephone 96221 28192 Telex 04 6168680 2 a Fr du 0 3 gnttorecalrorizpiace detective com REPLACEMENT ORDERING PROCEDURE Replacement parts subassemblies or modules are dis patched to the customer from the factory or branch office for replacement in the defective equipment by the customer Should this not prove successful in solving the problem the equipment must be returned to the factory or nearest office for repairs In some circumstances a user may request replacement of a defective plug in subassembly or module prior to returning the defective item In these instances a replacement will be supplied if the user issues a purchase order for the replace ment item If the defective assembly or module is in war ranty and is not returned to the factory wi
31. ining the full scale time Two spare switch positions are available Pads are available for both fixed and trim resistors The gate applied to the QTIOOT is based upon the T START and T STOP input pulses The T START clocks the Start Flip Flop The clock for the Start Flip Flop is kept high by the busy level derived from the Busy Generator See sheet 1 of the schematic Similarly the Stop Flip Flop is clocked by a signal derived from the T STOP input Its circuitry is activated by the Start Flip Flop The transistors Q11 and Q12 are used to form the gate pulse applied to the OT100T Digital Section The master clock employed in the 3001 is based upon a 20 MHz LC oscil lator see page 3 of the schematic The circuit was designed to allow rapid start up and shut down gating When conversion is initiated the clock is stopped and remains off until the 7 psec Wait Monostable completes its cycle The clock may also be inhibited by the user through the pad labeled CI located between TP and TQ a TTL high inhibits When a conversion is in process Channel A of the dual 11 bit 20 MHz scaler Model SC100 is used The output of the hybrid front end is used to gate the master clock Thus after a conversion is completed the binary data address is available at the SC100 outputs See sheet 4 of the schematic The scaler address is latched into the Memory Address Latch See sheet 4 In the quadrant mode the word is shifted righ
32. modes charge area voltage peak and time start stop Packaged as a double width NIM module it is significantly more compact than even the smallest analyzers previously avaiiable Each of the 3001 s 1024 channels has a count capacity of 16 bits 65 535 The contents may be displayed in log linear fashion on any X Y oscilloscope The display is active on a time available basis thus affording display during data accumulation A front panel switch selects intensification of every tenth or fiftieth channel Data may be accumulated and displayed in selected 256 channel quadrants or in the full 1024 channel memory In addition to both an internal and external trigger capability with variable gate width the 3001 provides external gate and inhibit inputs which are also used as start and stop inputs in the time mode Rear panel digital outputs are supplied to allow for data transfer to interface options including a readout device e g printer or a CAMAC Dataway The output connector may also be used to load or increment any one of the 16 bit words in memory This feature allows the 3001 to be used as an additional 1024 words of memory and to act as a histogram display module The 10 bit ADC used for the Q charge mode has a sensitivity of 0 25 pC channel directly compatible with photomultiplier anodes pulses thus obviating the need for a charge sensitive preamplifier In the Q mode the in put current is integrated for a duration ranging from 1
33. or quadrant will be cleared set to zero by moving the CLEAR_ switch to the right CLEAR position and simultaneously moving the START STOP switch to the left STOP position This is a protection feature to guard against inadvertant clearing of the memory OPERATIONS Memory Control The MEMORY switch allows the user to select the part of the memory he wishes to Usen In the FULL position the entire 1024 channels are used for both histogramming and display In the 2 4 position only channels 256 to 511 Quadrant 2 are used etc When the analyzer is operated in the quadrant mode the CLEAR operation effects only the quadrant in use Busy out The BUSY OUT supplies a TTL low during conversion and a TTL high at all other times This signal is intended to allow determination of live time and to count the number of accepted events Operating Modes The OPERATING MODE switch selects the q V or tmode It allows the operating controls inputs and outputs to have varying functions Thos described above however are independent of the OPERATING MODE operat Y of the 3001 in each of the 3 modes will be discussed below q Mode The q MODE is intended for analysis of photcmultiplier anode signals without amplifying or shaping Analog to digital conver sion is performed on the quantity of charge received at the Q INPUT within a well defined time interval A block diagram of the
34. or reading Read or write operations require ME high level See Note The data applied to the ten MA lines A L are latched on the trailing edge of a TTL compatible positive 200 nsec minimum duration pulse Address data must be quiescent at least 200 nsec prior to the latching dge S Note The least significant bit 20 of external data Coding is TTL high true Data source must be from either an open collector or Tri State source Input of external data is per mitted when ME is in Low State No internal pull up resistors are supplied Data are loaded into the Incrementing Register y an EXT LD pulse The 16 ED lines serve as memory data out ut when ME is in the High tate Outputs will drive one standard TTL load Length of i Ss nterconnecting data cables hould be limited to 6 feet R W and MAL can be applied only during the ENGINEERING DEPARTMENT LeCroy Research Systems Corp Spring Valley New York techn informa J2 Connector Contact Usage gf Signal N Designation Pin No Characteristic External Data Input Data Output X EDg1 5 As above but 2 bit n m X EDo2 7 As above but 2 bit x EDO3 8 As above but 23 bit X EDO4 10 As above but 2 bit xX EDO5 9 As above but 2 bit x EDO6 11 As above but 2 bit e X EDO7 12 As above but 2 bit X ED08 14 As above but 28 bit n X ED09 13 As above but 2 bit X ED10 15 As above
35. pacitor The VT100 has an identical pin configuration to that of the QT100 described above The input is also a virtual ground but it is non integrating An amount of charge proportional to the maximum input cur rent applied during the gating interval is stored on the internal capacitor Run down is identical to that of the QT100 s Full scale is 10 mA In the g MODE the QT100C is biased on by applying 50 mV to Pin 8 In the V and t modes it is biased off by applying 200 mV to Pin 8 In the q MODE a gate may be generated either internally or applied from an ex ternal source The Internal Gate Generator is shown on Sheet 1 of the schematic The Q INPUT is connected directly to the Internal Discriminator an LD604LG hybrid and then via a 25 5 nsec 50 Q delay cable to a 50 2 termination at the QTI1OOC Since the input impedance of the LD604LG is very high the Q INPUT performs as a low reflection transmission line Well terminated at the QTI1OOC In the INT gate mode the LD604LG is used to generate a gate trigger for the internal gate generator circuit The purpose of the delay line is to account for the propagation delay through the LD604LG and gate circuitry In the t MODE an amount of charge proportional to the gate width is de posited in the QT1OOT A constant current source based upon the 24 V NIX supply is used A side panel switch selects a series resistance F UNCTIONAL DESCRIPTION thus determ
36. plitude 100 mV Internally generated gate is available for oscilloscope mode is selected Amplitude 200 mV TTL low level output during conversion time monitoring when Internal or External Trigger Horizontal deflection voltage for CRT proportional to channel number 0 5 volts for full or qudrant display Minimum load impedance 1 K9 Vertical deflection voltage for CRT propotional to number of counts Linearity 2 0 2 of full scale Full scale output of 5 volts corresponds to 200 db volt in the log mode Minimum load impedance 1 k tf conmtact card edge ceontsrer A high TTL level Low TTL level nabi The trating edge of a the address applied t 2 respectively TTL Compatible high level causes the contents of the memory address latched in lines A L to Se back into the internal incrementing register A low eva permits loading of the 16 External Data In put levels into the incrementing Register Pin 6 20 Pin 10 24 Pin 14 28 Pin 18 212 5 21 9 25 B 29 17 23 7 22 11 26 B 210 19 214 a 23 12 27 16 11 20 2 5 Alow level latches the internal Incrementing Register Data must be quiescent during load interval Minimum duration 200 nsec e nbnveg Bel sist or written in iensor A TSO Te Cases data to be iga Som the Intercai inc re nenting regisier to teon INTRODUCTION The Model 3001 Multichannel Analyzer is a versatile height and time interval analyzer designed to operat
37. rogrammed read Only memory The analog mantissa is generated by the 8 bit LIN Mantissa DAC and the analog characteristic is generated by the 8 bit characteristic APPENDIX 1 A simplified method for calibrating Q mode pedestal and gain using standard lab equipment General The inherent 51 R termination of the Model 3001 Q input allows one to obtain a well defined amount of charge from the area of a well defined pulse given by the relation Q V 51 t Block Diagram of 3001 Q Mode Full Scale Calibration yA DISCRIMINATOR TRIGGER l SETTING of PULSE Y PULSE ON SCOPE OSCILLOSCOPE List of Test Equipment which can be used 1 Attenuator LeCroy Yodels Al01 A101L or A102 2 Discriminator LeCroy Models 621BL 621BLP or 623 etc 3 Trigger Oscillator Fan In Out 1923 or Instapulser IP 1 4 Oscilloscope Textronix 475 or 485 June lks Procedure Set the Model 3001 gate width to 150 nsec using a NIM input pulse and with the gate switch in EXT TRIG position Terminate the scope input 50 Q and with the calibration set up as shown in the block diagram select and set the Q input pulse For a pedestal of 30 a charge of 243 pc is required to obtain a peak in channel 1000 based on 0 25 pc channel sensitivity One therefore obtains the relation t 12 368 V nsec from it t can be determined if V is selected Note V must be between 0 2 and 0 5 volts Furthermore meas
38. t two bits and the two most significant bits are determined by the MEMORY switch The word in the Memory Address Latch addresses the memory which is normally in a READ state The resulting data work is latched into the Incrementing Register incremented by 1 and replaced in the Memory in the same address as given by the Memory Address Latch Display Section The display is activ xcept when an analog signal is being received or the results of a conversion are being entered in the Memory The clock continuously cycles Channel B of the SC100 through 1024 counts The re sulting addresses latched into the Memory Address Latch are supplied to amd Mr ii at o AAA oneness ea a YAA E the Horizontal Sweep DAC and to FUNCTIONAL DESCRIPTION the Memory In the quadrant mode the memory address is shifted right as in the digital section discussed above The data read from Memory and latched into the Data Scalar are processed either by an 8 bit linear or 16 bit logarithmic vertical DAC See Sheet 6 Display mode is selected by the DISPLAY SCALE switch In the is shifted right in accordance with the setting of the switch and presented to the LIN Mantissa DAC In the linear mode data COUNTS FULL SCALE T logarithmic mode the characteristic is generated by counting the number of shifts left required to obtain a left justified logic 1 The re maining data are used to generate a mantissa using a p
39. thin 30 days from the date o shipment of the replacement the user will be in voiced for the replacement POST WARRANTY REPAIRS For all LeCroy products in need of repair after the warranty period the customer must provide a Purchase Order Num ber before any inoperative equipment can be repaired or replaced The customer will be billed for the parts and labor for the repair as well as for shipping RETURN PROC ZDURE For all products returned to the factory for repair include the product model number serial number ECN number an ac curate description of the defect or failure and the name and phone number of the user Before reiurning a product for repair whether in_or out of warranty the user should contact the Engineering Services Department at the factory Phone No 914 425 2000 for aReturn Authorization Number This number is used to identify the product for repair and to reference any correspondence concerning that repair Return shipping costs are a the customer s expense LeCroy will not accept C O D or Collect Return Shipments Products should be returned in their original shipping car tons where possible LL ROY HESS RCH SYSTEMS CORPORATION ea er rra n NOTE TO THE USER LeCroy Research Systems is committed to providing unique re liable state of the art instrumentation in the field of high speed data acquisition and processing Because of this commitment and in response to information receive
40. tion manual Signal Memory Address emory Address emory Address emory Address emory Address emory Address emory Address emory Address emory Address emory Address June 1977 x 23 21 x 3157 Designation MA 0 14 J2 Connector Contact Usage Pin No A Characteristic Least significant bit of memory address a positive true TTL level When used as input address data must be supplied by an open col lector or Tri state driver Internal 2 K pull up resis tors are provided in the MCA The transmission of address must be enabled only when the EXT EN is low Address is read into the Address Register on negative going transition of MAL pin R The line serves as a memory address output when EXT EN is high Logic is positive true The line will drive one low power TTL load As above but 21 bit As above but 22 bit As above but 23 bit As above but 2 bit As above but 2 bit As above but 26 bit As above but 27 bit As above but 28 bit As above but 29 bit ENGINEERING DEPARTMENT LeCroy Research Systems Corp Spring Valley New York tech inform J2 Connector Contact Usage 2301 3157 Signal Designation Pin No Characteristic gt lt EXTERNAL ENABLE X EXT EN 4 Low TTL compatible level disables internal control thus enabling external mem ory control functions Memory Enable X ME 21 TTL low disables Tri
41. urements showed that the above value of t must be connected by increasing its value by about 8 105 Example Let V 0 30 volts which gives t 41 nsec and the increased t is 45 nsec This value of t is used for the calibration pulse Terminate the q INPUT with 50 Q and switch the channel intensifi cation i e INTENSIFY to 10th Note The NIM input pulse is still connected to the GATE INPUT On the scope select the XY mode and adjust the Q mode pedestal to channel 30 via the 6 20 pF trim capacitor on pin 16 of QT 100M Remove the terminator from the q INPUT and connect the output of the attenuator to it Set gate switch to INT INTENSIFY to 50th and adjust Q mode gain for counts in channel 1000 Repeat steps 4 and 5 until pedestal and pulse occur in channels 30 and 1000 respectively The Q mode gain is set with the 200 Q pot at pin 12 of QTIOOM NOTE Gain by extension cable should be checked with unit in NIM bin since gain setting may be affected Location Q Mode ga A Sb 1977 13 technical information manual QVT SYSTEM INTERFACE CONNECTIONS The following is a list of signals provided at the QVT rear panel connector Usage in the LeCroy Model 2301 CAMAC interface and the Model 3157 printer interface is indicated A a ENGINEERING DEPARTMENT LeCroy Research Systems Corp Spring Valley New York technical informa
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