TPMC812 - TEWS TECHNOLOGIES
Contents
1. e Address 0x00 to OxOE PCI9050 PCI Configuration Register Values e Address 0x10 to 0x62 PCI9050 Local Configuration Register Values e Address 0x64 to 0x7C Not used e Address 0x7E TPMC variant See the PCI9050 Manual for more information Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C Ox0E 0x00 0x9050 0x10B5 0x1180 Ox0000 Ox029E 0x1498 Ox0000 0x0100 0x10 OxOFFF OxFFO1 OxOFFF OxF800 Ox0000 Ox0000 Ox0000 0x0000 0x20 0x0000 0x000 0x0000 0x0001 0x0000 0x1001 0x0000 0x0000 0x30 0x0000 0x000 0x0000 Ox0000 0x5542 0x2100 0x5542 0x2140 0x40 0x0000 0x000 0x0000 Ox0000 Ox0000 Ox0000 Ox0000 0x0041 0x50 0x0000 0x1401 0x0000 0x0085 Ox0000 Ox0000 Ox0000 0x005B 0x60 0x0078 0x0040 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0x70 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF s b Figure 5 3 Configuration EEPROM TPMC812 xx Subsystem ID Value Offset 0x7E TPMC812 10 Ox000A TPMC812 11 0x000B For more information please refer to the PCI9050 1 data sheet which is part of the TPMC812 ED Engineering Documentation TPMC812 User Manual Issue 1 6 Page 17 of 23 TEWS S TECHNOLOGIES 5 4 Local Software Reset The PCI9050 Local Reset Output LRESETo is used to reset the on board local logic The PCI9050 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9050 local con2. indicates Little Endian For further information please refer to the PCI9050 manual which is also part of the TPMC812 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Name 0x28 0x2C 0x30 0x34 0x38 Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Local Address Space 0 Bus Region Description Register Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC812 User Manual Issue 1 6 Page 19 of 23 5 5 1 PCI Interrupt Control Status Register TEWS amp TECHNOLOGIES The INTO output of the SERCON816 Controller is connected to the LINT1 input of the PCI9050 PCI Target Chip The INT1 output of the SERCON816 Controller is connected to the LINT2 input of the PCI9050 PCI Target Chip The PCI9050 PCI Target Chip can generate an interrupt at pin INTA of the PCI bus The interrupt status can be read at the Interrupt Status Register INTCSR of the PCI Controller PCI9050 1 For disabling enabling PCI interrupts only set bit 6 of the PCI9050 Interrupt Control Status Register INTCSR 0x4C to 0 1 Do not change any other bits of this register Bit Description Access Reset
3. TEWS S TECHNOLOGIES 1 Product Description The TPMC812 is a standard single width 32 bit PMC module with a complete SERCOS bus interface using the SERCON816 SERCOS Controller in the SERCON410B compatible mode The physical interface supports RS485 on board as well as optical fiber ring In addition the TPMC812 offers two encoder interface ports to provide hand wheel functionality The encoder interface supports RS422 and TTL signal levels SERCOS Controller SERCON816 Figure 1 1 Block Diagram TPMC812 TPMC812 User Manual Issue 1 6 Page 6 of 23 TEWS amp TECHNOLOGIES 2 Technical Specification LOGIC INTERFACE Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 1 compliant 33 MHz 32 bit PCI 5V PCI Signaling Voltage PCI Target Chip PCI9050 1 PLX Technology FUNCTIONALITY SERCOS Controller SERCON816 SERCON410B Compatible Mode Encoder Interface 2 Ports X4 quadrature 8 bit Up Down Counter with Overflow Underflow Flags for incremental Encoders Physical SERCOS Interface I O RS485 DB15 Female Connector Optical fiber HFBR 1505A HFBR 2505A Physical Encoder Interface I O RS422 or TTL DB15 Female Connector PHYSICAL DATA Operating Temperature Range Operating 40 C to 85 C Storage 40 C to 85 C MTBF 196153 h Weight len Figure 2 1 Technical Specification TPMC812 User Manual Issue 1 6 Page 7 of 23 3 Local Space Addressi
4. Value 31 8 unused R 0 7 Software Interrupt R W 0 6 PCI Interrupt Enable R W 1 5 Local Interrupt 2 Status R 0 4 Local Interrupt 2 Polarity R W 1 3 Local Interrupt 2 Enable R W 1 2 Local Interrupt 1Status R 0 1 Local Interrupt 1 Polarity R W 1 0 Local Interrupt 1 Enable R W 1 Figure 5 5 Interrupt Control Status Register INTCSR 0x4C TPMC812 User Manual Issue 1 6 Page 20 of 23 TEWS S TECHNOLOGIES 6 Programming Hints For more information on programming the SERCON816 Controller please refer to the SERCON816 Reference Manual which is part of the TPMC812 ED Engineering Documentation TPMC812 User Manual Issue 1 6 Page 21 of 23 TEWS amp TECHNOLOGIES 7 Installation 7 1 Jumper Installation 7 1 1 Jumper Configuration J3 SERCOS I O INTERFACE TYPE 1 3 CLOSED 2 4 CLOSED 5 7 OPEN 6 8 OPEN 1 3 OPEN Optical Fiber 2 4 OPEN 5 7 CLOSED 6 8 CLOSED Default SERCOS RS485 INTERFACE 1 2 CLOSED Termination ON SYNC LINE TERMINATION Default 120R 1 2 OPEN Termination OFF SERCOS RS485 INTERFACE 1 2 CLOSED Termination ON DATA LINE TERMINATION Default 120R 1 2 OPEN Termination OFF Figure 7 1 Jumper Configuration 7 1 2 Jumper Location Figure 7 2 Jumper Location TPMC812 User Manual Issue 1 6 Page 22 of 23 TEWS amp TECHNOLOGIES 8 Pin Assignment I O Connector 8 1 1 DB15 Female Connector Pin Signal Function e soam
5. Local Address Space 1 cccssecsseeeeeeeeeeceeseeeeeenseeeeneeeesaaeegseeeenseeeesaesesaaesaseeeeeeeeeeseaesaseeeensneeeeeeeneas 12 3 3 1 SERCON816 Controller DPDRAM 12 4 FUNCTIONAL DESCRIPTION WEE 13 5 PCI9050 TARGET CHIP gege 14 5 1 PCI Configuration CFG Registers sssssesnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnna 14 5 1 1 PCI Header of the TDMCDI annn nn nannten nnne ennnen 14 5 1 2 PCI Base Address Initialization ccceccceceesseceeeeeeeeeeeeeeeeeeseneeeeeseeeeeesseneaeenseessaeenssneaeens 15 5 2 Local Configuration Register LCR ss sssusssunsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn annann nannaa 16 5 3 Configuration EEPROM siisii anai iaaa aaea EENEG 17 5 4 Local Software Heset uisa aaan iaaa a aaaea aeaa daaa ea anaa aaia a daadaa anaa iat 18 5 5 Big Little Ende 18 5 5 1 PCI Interrupt Control Status Heglsier 20 6 PROGRAMMING HINTS c csscssssessssssssssesssssesessesstssessssessessesesscssesessesaesenseeacess 21 7 Jung Eu de ME 22 7 1 Jumper installation ce ceeee ce eeeeee ee eee ee eee eeee eee neee sees neee eee neee eee gees see neee eee anes seen neee nnmnnn nnmnnn nnna 22 Ait JUMPS eet e Le e E 22 Fila Jumper LOCATON serasa araea a ge Eeer 22 8 PIN ASSIGNMENT UO CONNECTOR ccccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 23 8 1 1 DB15 Female Connector cccccccescececsecececeeeeeeecseeeeeeceneeeeeseeee
6. SERCOS RS405 DATALNE e eng _ SERCOS RS4 5 SYNCLINEs p ENGzAr_ ENCODER2 PHASER ps pes ENCODER PHASEB GND SIGNAL GROUND 7 Encrar ENCODER TPHASEA pe pes ENCODER TPHASEB o sem SERCOS RS4as DATALNE Figure 8 1 DB15 Female Connector H For TTL level encoder interface inputs the pins for these signals must be left unconnected DB15 Female OPT RX OPT TX Figure 8 2 Connector Location TPMC812 User Manual Issue 1 6 Page 23 of 23
7. service channel information over several communication cycles is executed automatically The TPMC812 PMC also implements two 8 bit X4 Quadrature Mode Counter for incremental encoder signals Since this is a X4 Quadrature Counter the signal change of any Encoder Signal Phase A or B will be counted In case of a leading Phase A signal the counting direction is up otherwise down Overflow and underflow conditions are signed by flags TPMC812 User Manual Issue 1 6 Page 13 of 23 5 PCI9050 Target Chip 5 1 PCI Configuration CFG Registers 5 1 1 PCI Header of the TPMC812 TEWS amp TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Read after Register write initialization ARIES able write access 31 24 23 16 15 8 7 0 Hex Value 0x00 Device ID Vendor ID N 9050 10B5 Target Chip PCI9050 1 PLX Technology 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 028000 XX 0x0C BIST Header Type PCI Latency Cache line Y 7 0 000000 00 Timer Size 0x10 PCI Base Address 0 for Memory Mapped Configuration Y FFFFFF80 Registers 0x14 PCI Base Address 1 for I O Mapped Configuration Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFO1 0x1C PCI Base Address 3 for Local Address Space 1 Y FFFFF800 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 f
8. 812 User Manual Issue 1 6 Page 8 of 23 TEWS S TECHNOLOGIES Offset Name Function Size bit to PCI Base Address 0x0C REGO6 16 Ox0E REGO7 16 0x10 REGO8 16 0x12 REG09 16 0x14 REGOA 16 0x16 REGOB 16 0x18 REGOC 16 Ox1A REGOD 16 0x1C REGOE 16 Ox1E TSCYCO 16 0x20 TSCYC1 See SERCON816 Reference Manual 16 0x22 TCYCDEL 16 0x24 TCNTLT 16 0x26 TCNTST 16 0x28 TCYCSTART 16 Ox2A JTSCYC1 16 0x2C JTSCYC2 16 Ox2E PROGERR_FL 16 0x30 JTRDEL1 16 0x32 JTRDEL2 16 0x34 TINTO 16 0x36 TINTI 16 0x38 TINT2 16 0x3A TINT3 16 0x3C TDIVCLK 16 Ox3E DTDIVCLK 16 0x40 REG20 16 0x42 THTPT 16 0x44 THT 16 0x46 THWPT 16 0x48 THW 16 0x4A REG25 16 0x4C THR 16 Ox4E FIFO 16 Figure 3 2 SERCON816 Controller Registers For a detailed description of the functionality of these registers please refer to the SERCON816 Reference Manual which is part of the TPMC812 ED Engineering Documentation TPMC812 User Manual Issue 1 6 Page 9 of 23 TEWS S TECHNOLOGIES 3 2 2 Additional Local Register The Additional Local Registers are mapped into PCI I O Space and are accessible in the Local Address Space 0 of the PCI9050 PCI Target Chip The PCI Base Address for the Additional Local Registers is the PCI Base Address for Local Address Space 0 of the PCI9050 PCI Target Chip PCI9050 PCI Configuration Register Space Offset 0x18 Offse
9. IEN SZ The Embedded I O Company TECHNOLOGIES TPMC812 SERCOS PMC with 2 Encoder Interfaces Version 1 0 User Manual Issue 1 6 September 2006 D76812801 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com TPMC812 10 SERCOS PMC with 2 encoder interfaces TPMC812 11 SERCOS PMC with 2 encoder interfaces optical isolated encoder interface TPMC812 User Manual Issue 1 6 TEWS amp TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET 1999 2006 by TEWS TECHNOLOGIES GmbH P
10. age 2 of 23 TEINS S TECHNOLOGIES Issue Description Date 1 0 First Issue March 1999 1 1 Additions to User Manual Board Revision changed to B May 1999 1 2 Add MTBF and weight value to Technical Specification March 2001 1 3 Jumper Configuration Description modified July 2002 PCI Interface Data added to Technical Specification 1 4 General Revision May 2003 1 5 SERCON816 SERCOS Controller September 2004 1 6 New address TEWS LLC September 2006 TPMC812 User Manual Issue 1 6 Page 3 of 23 TEWS S TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION ssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnana 6 2 TECHNICAL SPECIFICATION uuuunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nna 7 3 LOCAL SPACE ADDRESSIN e sis arasa kisasi darias aiai 8 3 1 PCI9050 Local Space Configuration cccsccseeeesteeeeeeeeeeeeeeseaeeeeseeeeeeeseseaeseseeeeneeeeseeesseseneneeees 8 3 2 Local Address Space Q sssnssennsennsennnnnnnnnnnnnnn unnn nnnn unnn nnnn nnne nnnnnnnnnnnnnnnn nunne nnne nnnn ennnen mnnn nn nnmnnn nnmnnn 8 3 2 1 SERCON816 Controller Register 0 ccccccceesceceeeeeeeeeeeeeeseneeeeeeaeeseaeeseneeeseaeeesaeseeeeseneeee 8 3 2 2 Additional Local Heotsier nnt 10 3 2 2 1 MSYNC Register Oxvp0 10 3 2 2 2 ENCx Register 0x82 0X84 oo ceceeeeeeeeceeeeeeaeeeeeee seas eeseaeeeeaeesecaeeetaeeeeaeeteaes 11 3 3
11. cal Configuration Registers Offset from Register Value PCI Base Address 0x00 Local Address Space 0 Range OxOFFF_FFO1 0x04 Local Address Space 1 Range OxOFFF_F800 0x08 Local Address Space 2 Range 0x0000_0000 0x0C Local Address Space 3 Range 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_1001 0x1C Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x5542_ 2100 0x2C Local Address Space 1 Descriptor 0x5542 2140 0x30 Local Address Space 2 Descriptor 0x0000_0000 0x34 Local Address Space 3 Descriptor 0x0000_0000 0x38 Local Exp ROM Descriptor 0x0000_0000 0x3C Chip Select 0 Base Address 0x0000_0041 0x40 Chip Select 1 Base Address 0x0000_ 1401 0x44 Chip Select 2 Base Address 0x0000_0085 0x48 Chip Select 3 Base Address 0x0000_0000 0x4C Interrupt Control Status 0x0000_005B 0x50 Miscellaneous Control Register 0x0078_0040 Figure 5 2 PCI9050 Local Configuration Register TPMC812 User Manual Issue 1 6 Page 16 of 23 TEWS amp TECHNOLOGIES 5 3 Configuration EEPROM After power on or PCI reset the PCI9050 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data
12. eeeeseneaesesseeeeeessnaeeseseeaeess 23 TPMC812 User Manual Issue 1 6 Page 4 of 23 TEWS S TECHNOLOGIES Table of Figures FIGURE 1 1 BLOCK DIAGRAM IPDM 6 FIGURE 2 1 TECHNICAL SPECIFICATION iiucsrreissine tavoita aeta anaa ENEE RENEA 7 FIGURE 3 1 PCI9050 LOCAL SPACE CONFIGURATION ssssssssiesisrrsrrsrrreirsirerisrinsinrinsrnrrnsrnstenrrneensrner 8 FIGURE 3 2 SERCON816 CONTROLLER REGISTERS oe eeceeceeeeeeeeeeneeenee eee eaecaeenaeseeeesaeseaeeeeeeaeee 9 FIGURE 3 3 ADDITIONAL LOCAL RE GIGSTER AA 10 FIGURE 3 4 MSYNG REGISTER WEE 10 FIGURE 3 5 ENCX REGISTER E 11 FIGURE 3 6 SERCON816 CONTROLLER DPRAM cece eecseeeeeeeene ener seer eeeeeseeeseaeesaeesaeeeeeeesaeeeeeenaeeaaes 12 FIGURE 5 1 PC CONFIGURATION REGISTER MARD 14 FIGURE 5 2 PCI9050 LOCAL CONFIGURATION REGISTER eee eeceeeeeseeeeeeeneeeeeseesnaessaessaeeeeeeaaes 16 FIGURE 5 3 CONFIGURATION EEPROM TPMC812 XX 0 0 eececeeeeeeee seer eeeeeeeeeseaeesaeesaeesaeesaeeseeeaeeaaes 17 FIGURE 5 4 LOCAL BUS LITTLE BIG ENDIAN AAA 18 FIGURE 5 5 INTERRUPT CONTROL STATUS REGISTER INTCSR DRAN 20 FIGURE 7 1 JUMPER CONFIGURATION AA 22 FIGURE 7 2 JUMPER LOCATION eitesecevtisace steve ten tennadenn aeie Eana AAR aa iNe 22 FIGURE 8 1 DB15 FEMALE CONNECTOR wistitescnses cttcesenveuntnas exsuedde clave shdveetyaacseeevduenss Deele paata ak 23 FIGURE 8 2 CONNECTOR LOCA TION cece cece terre cree eee teas cae seae seas a aiia 23 TPMC812 User Manual Issue 1 6 Page 5 of 23
13. figuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9050 and issues a reset to the Local Bus LRESETo asserted The PCI9050 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9050 PCI and Local Configuration Registers are not reset The PCI9050 PCI Interface is not reset 5 5 Big Little Endian e PCI Bus Little Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 e Every Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit pe Sp Byte 1 Sen Byte 2 0123 16 Byte 8 SES 16 Bit upper lane 16 Bit Byte 0 Sp Byte 1 Sen 16 Bit lower lane Ps 8 Bit upper lane 8 Bit Byte 0 SE 8 Bit lower lane PF Byte 0 D 7 0 Figure 5 4 Local Bus Little Big Endian TPMC812 User Manual Issue 1 6 Page 18 of 23 Standard use of the TPMC812 Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space TEWS amp TECHNOLOGIES 16 bit bus in Big Endian Mode Lower Lane 16 bit bus in Big Endian Mode Lower Lane not used not used not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0
14. ng 3 1 PCI9050 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9050 local TEWS amp TECHNOLOGIES spaces PCI9050 PCI9050 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0 0 0x10 MEM 128 32 LITTLE Local Configuration Registers 1 1 0x14 UO 128 32 LITTLE Local Configuration Registers 2 2 0x18 UO 256 16 BIG Local Address Space 0 lower Controller Additional lane Registers 3 3 0x1C MEM 2048 16 BIG Local Address Space 1 lower Controller DPRAM lane 4 4 0x20 Local Address Space 2 5 5 0x24 Local Address Space 3 6 0x30 Local Expansion ROM Space 3 2 1 SERCON816 Controller Register Figure 3 1 PCI9050 Local Space Configuration 3 2 Local Address Space 0 The SERCON816 Controller Registers are mapped into PCI I O Space and are accessible in the Local Address Space 0 of the PCI9050 PCI Target Chip The PCI Base Address for the SERCON816 Controller Registers is the PCI Base Address for Local Address Space 0 of the PCI9050 PCI Target Chip PCI9050 PCI Configuration Register Space Offset 0x18 Offset Name Function Size bit to PCI Base Address 0x00 VERSION 16 0x02 REGO1 16 0x04 REGo2 See SERCON816 Reference Manual 16 0x06 REGO03 16 0x08 REG04 16 0x0A REGO5 16 TPMC
15. or Local Address Space 3 Y 00000000 0x28 Cardbus CIS Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 032C 1498 TPMC812 TEWS TECHOLOGIES GmbH 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved N 00000000 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 000001 00 Figure 5 1 PCI Configuration Register Map TPMC812 User Manual Issue 1 6 Page 14 of 23 TEWS amp TECHNOLOGIES 5 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9050 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9050 PCI Base Address Register 2 Read back the PCI9050 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size F
16. or example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9050 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9050 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9050 PCI Base Address Register After programming the PCI9050 PCI Base Address Registers the software must enable the PCI9050 for PCI I O and or PCI Memory Space access in the PCI9050 PCI Command Regisiter Offset 0x04 To enable PCI I O Space access to the PCI9050 set bit 0 to 1 To enable PCI Memory Space access to the PCI9050 set bit 1 to 1 For more information please refer to the PCI9050 1 data sheet which is part of the TMPC812 ED Engineering Documentation TPMC812 User Manual Issue 1 6 Page 15 of 23 TEWS S TECHNOLOGIES 5 2 Local Configuration Register LCR After reset the PCI9050 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9050 Local Configuration Registers is PCI9050 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9050 PCI Configuration Register Space or PCI9050 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9050 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9050 Lo
17. r In case of read access the Overflow and Underflow Flag are cleared automatically after read out while the encoder counter value remains unchanged Any write access to an ENCx Register clears the 8 bit encoder counter value and the Overflow and Underflow Flags TPMC812 User Manual Issue 1 6 Page 11 of 23 TEWS amp TECHNOLOGIES 3 3 Local Address Space 1 3 3 1 SERCON816 Controller DPRAM The SERCON816 Controller DPRAM is mapped into PCI Memory Space and is accessible through the Local Address Space 1 of the PCI9050 PCI Target Chip The PCI Base Address for the SERCON816 Controller DPRAM is the PCI Base Address for Local Address Space 1 of the PCI9050 PCI Target Chip PCI9050 PCI Configuration Space Offset 0x1C There are 1024 x 16 bit DPRAM words of storage Only the lower 1024 16 bit words of the SERCON816 are accessible SERCON410B compatible mode Offset Size bit to PCI Base Address 0x000 Figure 3 6 SERCON816 Controller DPRAM For more information on the SERCON816 Dual Ported RAM please refer to the SERCON816 Reference Manual which is part of the TPMC812 ED Engineering Documentation TPMC812 User Manual Issue 1 6 Page 12 of 23 TEWS S TECHNOLOGIES 4 Functional Description The TPMC812 SERCOS PMC implements a SERCOS communication interface by using the SERCON816 SERCOS controller in the SERCON410B compatible mode The SERCOS interface is a digital interface for communication between system
18. s which have to exchange information cyclically at short fixed intervals 65usec to 65msec It is appropriate for the synchronous operation of distributed control or test equipment e g connection between drives and numeric control A SERCOS interface communication system consists of one master and several slaves These units are connected by a optical fiber ring This ring starts and ends at the master The slaves regenerate and repeat their received data or send their own telegrams By this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves The optical fiber assures a reliable high speed data transmission with excellent noise immunity The TPMC812 SERCOS PMC contains all the hardware related functions of the SERCOS interface and considerably reduces the hardware costs and the computing time requirements of the host CPU It is the direct link between the electric optical receiver and transmitter and the host CPU that executes the control algorithms The TPMC812 20 SERCOS PMC can be used for both SERCOS interface masters and slaves The serial interface operates with data rates up to 4 Mbaud A Dual Ported RAM 1024 16 Bit is used for control and communication data exchange between the TPMC812 SERCOS PMC and the host CPU The organization of the memory is flexible The telegram processing of cyclic data is automatically controlled by the TPMC812 PMC The transmission of
19. t Size bit to PCI Base Address MSYNC Master Synchronization CLK Enable R W ENC1 Encoder 1 Counter amp Flags R C ENC2 Encoder 2 Counter amp Flags R C Figure 3 3 Additional Local Register 3 2 2 1 MSYNC Register 0x80 Bit Symbol Description Access Reset Value 15 1 Reserved Always read as 0 Write as 0 0 0 MSYNC Transmission of the SERCON Master Synchronization R W 0 CLK SERCON816 CON_CLK signal 1 enabled 0 disabled Reset State Figure 3 4 MSYNC Register TPMC812 User Manual Issue 1 6 Page 10 of 23 3 2 2 2 ENCx Register 0x82 0x84 TEWS amp TECHNOLOGIES Bit Symbol Description Access Reset Value 15 10 Reserved Always read as 0 9 UF Underflow Flag for the 8 bit Counter If an underflow occurs while the Overflow Flag is set the Overflow Flag will be cleared and the Underflow Flag will not be set R C OF Overflow Flag for the 8 bit Counter If an overflow occurs while the Underflow Flag is set the Underflow Flag will be cleared and the Overflow Flag will not be set R C 7 0 C7 C0 8 bit Encoder Counter Value of encoder x x 1 2 Since this is a X4 Quadrature Counter the signal change of any Encoder Signal Phase A or B will be counted In case of a leading Phase A Signal the counting direction is up otherwise down R C Figure 3 5 ENCx Registe
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