CPM1/CRM1 cPCI Pentium M Based Single Board
Contents
1. 32 bit PCI LPC Bus 64 bit PCI X 66 MHz 528 MB s cme pur Dual ENET 10 100 1000 PICMG 2 16 Compact PCI P1 and P2 P3 Dynatem CPM cPCI Pentium Processor Board User s Manual 5 Chapter 3 Hardware Description snnm aa E E E gt EEES EETTTTTTETTE T 3 2 Processor The CPMI supports a Pentium M processor at 1 4 GHz The Intel Pentium M processor with 2 MB of L2 cache is meet the current and future demands of high performance low power embedded computing making it ideal for communications mobile applications vehicles and industrial automation applications While incorporating advanced processor technology it remains software compatible with previous members of the Intel microprocessor family e 400 MHz front side bus e 4MB of L2 cache for fast large table look ups routing tables e Advanced branch prediction Micro op fusion Hardware stack manager for faster processing e Second generation Streaming SIMD Extensions Streaming SIMD Extensions 2 capability adds 144 new instructions including 128 bit SIMD integer arithmetic and 128 bit SIMD double precision floating point operation e Fully compatible with existing Intel amp Architecture based software For further information on the Pentium M processor available from Intel Corporation search at http www intel com design intarch pentiumm pentiumm htm The Intel amp Pentium M processor was designed from the ground2. 6300ESB ICH PCI IDE Interface E 6300ESB ICH SATA Interface 6300ESB ICH SMBus Interface 2 2 2 2 2 25A9 6300ESB ICH PCI USB 0 Interface 25AA 6300ESB ICH PCI USB 1 Interface 25AC 6300ESB ICH APIC 0 3 82541 Fast Ethernet Controller 9 PCI Configuration Dynatem CPM cPCI Pentium Processor Board User s Manual 33 Appendix B Address Maps Interrupts DMA Channels B 3 Interrupt Request Routing The ISA interrupt request routing is shown below Description Timer 0 ICH Keyboard SMSC s LPC47B272 Cascade Interrupt from slave PIC ICH COM2 COM4 LPC47B272 COM1 COM3 LPC47B272 LPT2 LPC47B272 Floppy Drive LPC47B272 LPT1 LPC47B272 Real Time Clock ICH No connection pulled up via 8 2K No connection pulled up via 8 2K No connection pulled up via 8 2K Mouse LPC47B272 s kybd mouse controller Math Coprocessor ICH Primary IDE Interface via P2 connector ICH Secondary IDE Interface CompactFlash ICH The LPC47B272 is found on the optional CPMIPTB rear I O expansion card it is not included with the CPMI The PCI interrupt request routing to the Intel 6300ESB I O Controller Hub ICH is shown below PIRQA USB 0 PIRQB 82546EB PIRQC GMCH integrated SVGA Controller PIRQD USB 1 PCI 6254LINTO For further details on interrupts refer to the documentation for the various peripherals that generate interrupts as well as Intel 6300ESB YO C
3. As shown in the block diagram the PCI bridge to the backplane shares its primary side with the 82546 Dual Gb Ethernet controller and PMC site 1 If the PMC card installed in site 1 is not PCI X compatible then neither the PCI bridge nor the 82546 can operate in the PCI X mode The same is true with the bridge chip Therefore the CPMI cannot support PCI X on site 1 PMC cards or on the 82546 on boards that use the PCI6254 The same is true with clock frequencies the PCI bus can only run as fast as the slowest device on the bus so a PMC module running at 33 MHz will force the 82546 and the PCI PCI bridge to operate at 33 MHz Both the 6254 and the 6540 are universal bridges meaning their mode of operation is determined by the SYSEN signal on the cPCI backplane In this application the CPMI can be used without jumpers for the system slot or peripheral slot in a CompactPCI system The bridge senses the type of slot system or peripheral and configures itself as Transparent or Non Transparent respectively In the system slot the CPU is expected to operate as a host and the bridge operates in Transparent mode In the peripheral slot the CPU is part of an intelligent subsystem and the bridge is configured in Non Transparent mode The figure below shows Transparent Non Trans PCI Bridge PCI Bridge This drawing shows how the CPMI operates differently depending on whether it s in the system slot on the backplane denoted by a triangle or
4. 64 bit transfers and there s no JN4 connector to route I O to the backplane The following table lists the reference designators used on the CPM1 s second PMC site 4 5 Front Panel Connectors and Reset Switch The CPMI offers front panel connections for two COM ports one PS 2 connector for a combined mouse keyboard interface and an RJ45 connector for a 1 Gb Ethernet port The CPMI is shipped with a splitter cable for the PS 2 mouse and keyboard ports Install all front panel cables by inserting them into the appropriate connector Thw COMI and COM2 ports use Micro D subminiature connectors that can be secured to the CPMI by tightening their thumbscrews into the connectors jackscrews Ethernet mating connectors should snap into place Mounting hardware for the front panel connectors are isolated from the CPM1 s digital ground They are continuous with the front panel itself that in turn is common with chassis ground The CPMI contains a recessed reset switch accessible from the front panel To reset the CPM press the reset switch using a small screwdriver blade or similar implement There is also a PICMG 2 1 R2 0 compliant hot swap LED that can be seen at the front panel This LED goes on when it is safe to extract the CPMI from its chassis The Ethernet connector has a pair of indicator LED s built in These two LED s offer stats on the 10 100BaseTX port provided by the 82541PI Ethernet controller on the CPMI Here is an explanation
5. BIOS settings SW1 8 should always be closed in the on position this switch is used for factory use 4 3 CompactFlash Drive Installation The CPMI supports a bootable CompactFlash Drive for single slot booting Connector J4 is a Type II CompactFlash connector and is used for this purpose J4 is located behind the front panel Ethernet connector on the CPM1 s printed circuit board 4 4 PCI Mezzanine Card PMC Installation The CPMI supports two add on module sites that let the user expand the CPM1 s local I O with PCI Mezzanine Card PMC or PMCX PMC modules capable of PCI X transfers cards Only one of the two sites located in the middle of the CPMI and labeled PMC1 on the front panel supports PMCX cards that in turn support PCI X transfers at a maximum of 66 MHz The PMCX site is backwards compatible and can support any module from 32 bit PMC cards at 33 MHz to 64 bit PMCX modules at 66 MHz however it shares a bus with the 82546EB dual Gb LAN controller used for PICMG 2 16 compliance and the PCI6540 PCI X to PCI X bridge to the cPCI backplane Putting a standard PMC card in this site will force the 82546EB and the PCI6540 to operate in standard PCI mode The CPM1 s PCI X bus interfaces to the 82546 dual Gb Ethernet controller and to the PMCX site PMCX site Available Data Rates with VIO z 5 V Available Data Rates with VIO z 3 3 V JP3 is shunted between pins 2 amp 3 JP3 is shunted between pins 1 amp 2 3
6. DYNATEM CPM1 CRM1 cPCI Pentium M Based Single Board Computer User s Manual CPM1 User s Manual Rev 1 01 May 2006 Dynatem 23263 Madero Suite C Mission Viejo CA 92691 Phone 949 855 3235 Fax 949 770 3481 www dynatem com Dynatem Table of Contents Features Related Documents Hardware Description Overview Processor Chipset DRAM PCI Mezzanine Card PMCX Expansion 0 Intel s FW82802A Firmware Hub Holds the System BIOS In Flash Memory Clock Drivers Installation Installing CPMI in a CompactPCI Chassis Jumper Selectable Options Lu CompactFlash Drive Installation aa PCI Mezzanine Card PMC Installation Front Panel Connectors and Reset Switch CPM cPCI Pentium Processor Board User s Manual B 3 D Connector Pin outs 19 COMI amp COM2 Front Panel Connector J8 1 Gb Ethernet Front Panel Connector J9 CompactFlash Interface Connector J6 PS 2 Mouse Keyboard Connector J10 JTAG Debug Port J13 cPCI Connectors J1 J2 J3 amp J5 PCI X Mezzanine Card PMC1 Connectors JN1 JN2 JN3 and JN4 PCI Mezzanine Card PMC2 Connectors JN1 amp JN2 Address Maps Interrupts DMA Channels 20 20 21 22 23 26 30 33 Memory Map PCI Configuration Space Map Interrupt Request Routing Power and Environmental Requirements 33 34 35 XPMIRIO Rear Plug in I O Expansion Module 37 CPM cPCI Pentium Processor Board User s Manual Dynate
7. Link and a green LED to indicate 1 Gb mode Signal Description TP0 TPO TP1 TP2 TP2 T A Receive Data RX TP1 7 TP3 TP3 1 Gb Ethernet Connector J9 Front Panel RJ 45 Connector The metal shell of the connector goes to chassis ground 20 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A3 A4 Dynatem CompactFlash Interface Connector J6 CMPFLASHDET sumi pe Bk 1 CompactFlash Type Il Interface Connector J6 ND 3 4 5 7 S14 A0 1 Pin Pin as j 39s i PS 2 Mouse Keyboard Connector J10 Signal Description Keyboard Data 5 VDC via 1 amp self resetting fuse F1 Keyboard Clock Mouse Clock Keyboard Mouse Connector J10 Front Panel Mini DIN Receptacle The metal shell of the connector goes to chassis ground per Cai CPM cPCI Pentium Processor Board User s Manual 21 Appendix A Connector Pin outs A 5 JTAG Debug Port J13 This JTAG connector permits in circuit emulation for system debugging and is not populated on production boards cPUEPMR 6 PRSE cPugewa 8 GND GND GND JTAG Connector J13 22 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A 6 cPCI Connectors J1 J2 J3 and J5 Connectors J1 and J2 bring a 64 bit 66 MHz capable PCI X bus to the CompactPCI backplane PU stands for pu
8. a DVI I connector The DVO port e Provides high speed 12 bit interfaces with 165 MHz dot clocks e Supports DVO devices TV Out Encoders TMDS amp LVDS transmitters etc with pixel resolutions up to 1600 x 1200 85 Hz and up to 1048 x 1536 72 Hz 6 CPM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description rr EEEE EEEcrr omIc a orl e Compliant with DVI Specification 1 0 e Front side system bus bandwidth of 3 2 GB s 400 MHz The 6300ESB I O Controller Hub ICH provides most of the CPM1 s on board I O and it s the CPM1 s PCI and PCI X expansion bridge The ICH is designed as a low power high performance I O hub that features e 64 bit 66 MHz PCI X expansion that is used on the CPMI for the on board PMC X slot the two Ethernet ports available in compliance with PICMG 2 16 and for the PLX PCI6254 PCI to PCI bridge to the backplane e 32 bit 33 MHz PCI bus that supports the second PMC site and the front panel s Gb Ethernet port e Four USB 2 0 compliant ports that are routed to the J5 connector to the backplane and to the optional XPMIRIO rear I O module where industry standard USB connectors are provided e Integrated IDE controller supports Ultra 100 DMA Mode Transfers for up to 100 MB sec read cycles and 88 88 MB sec write cycles for a CompactFlash drive on board and a primary IDE port that is routed through J5 to the XPMIRIO e Two Serial ATA ports providing 150 MB sec data ra
9. http www smbus org specs e Universal Serial Bus Specification http www usb org developers The following documents cover topics relevant to the cPCI and can be purchased through VITA e IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus cPCI The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 Dynatem CPMI cPCI Pentium Processor Board User s Manual 3 Chapter 2 Related Documents The following documents are the current draft standards for the PCI Mezzanine Card PMC e JEFE Draft Std P1386 2 0 Draft Standard for a Common Mezzanine Card Family CMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 e IEEE Draft Std P1386 1 2 0 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 4 CPMI cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description 3 Hardware Description 3 1 Overview The block diagram of the CPMI is shown below The sections that follow describe the major functional blocks of the CPMI Intel Pentium M or Celeron M 3 2 GB s System Bus Addressing at 200 MHz Data at 400MT s SDRAM DDR 266 512 MB or 1 GB 2 136 GB s O Controller Hul Primary IDE dual SATA quad USB 2 0
10. one of the remaining peripheral slots denoted by circles silkscreened on the backplane When in the system slot the six additional REQ GNT pairs and six additional clocks are routed to the backplane in compliance with the PICMG CompactPCI spec though boards using the PCI6540 route CLK3 to the pins assigned to CLK3 and CLK5 and CLK4 to CLK4 and CLK6 because the 6540 only has five CLK output lines 10 CPM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description wa 5852522525 available These additional CLK and REQ GNT lines are not used when the CPMI is installed in a peripheral slot They are in a tristate mode A transparent PCI bridge is meant to provide electrical isolation to the system It allows additional loads and devices to be attached to the bus and can also be used to operate dissimilar PCI Bus data widths and speeds on the same system For example a transparent bridge can allow several 32 bit 33 MHz PCI devices to attach to a 64 bit 66 MHz PCI X slot A non transparent PCI bridge offers address isolation in addition to electrical isolation Devices on both sides of the bridge retain their own independent Memory space and data from one side of the bridge is forwarded to the other side using an address translation mechanism A non transparent bridge is used when there is more than one intelligent entity such as multiple processors in the system It is a common mechanism used for creating intellige
11. up with a new microarchitecture that delivers high performance with low power consumption With its 90 nm processing technology and 2 MB of L2 advanced transfer cache the Pentium M offers more performance per Watt The Pentium M also offers a dedicated hardware stack manager that employs sophisticated hardware control for improved stack management advanced branch prediction capability and a 400 MHz front side bus to the memory controller hub 3 3 Chipset The Intel 855GME Graphics Memory Controller Hub GMCH and Intel 6300ESB I O Controller Hub ICH chipset create an optimized integrated graphics solution with a 400 MHz system bus and integrated 32 bit 3D core at 133 MHz The 855GME GMCH provides a 266 MHz interface to DDR RAM 72 bits wide with ECC The CPMI can be populated with one or two banks of DRAM for 512 MB or 1 GB of total memory respectively The GMCH system memory architecture is optimized to maintain open pages up to 16 kB page size across multiple rows As a result up to 16 pages across four rows is supported To complement this the GMCH will tend to keep pages open within rows or will only close a single bank on a page miss The 855GME also has an advanced integrated graphical display controller The CPMI routes the DVO B port through a PanelLink device and this along with the VGA port is brought out through the J5 connector to the system backplane The XPMIRIO rear plug in card combines the the DVO and VGA ports in
12. 232 when closed LIO MM 9 95797 59 5 9 TITI LANa J3 USB3 USB1 LANb J4 USB4 SATA J2 COM4 J6 COM3 J5 USB DVI I J1 Fan Connectors Ground 12 Volts Fan T Fan S Dynatem CPM cPCI Pentium Processor Board User s Manual 37
13. 3 MHz 33 MHz and 66 MHz The General Software BIOS will determine during startup what the status is on the installed PMC X card The BIOS monitors the following pins that are routed to the ICH PCIXCAP PCX X capable and it is pin 39 on Dynatem CPM cPCI Pentium Processor Board User s Manual 17 Chapter 4 Installation r r rr __ n11 2k21212kln __oD connector P11 and M66EN 66 MHz capable and pin 47 on connector P12 The user s manual on your PMC X modules will tell you how PCIXCAP JNI pin 39 and M66EN JN2 pin 47 are configured If either is grounded than the PMC X module does not have the corresponding capability these pins were assigned as ground on the original PMC specification before PCI X or 66 MHz modes of operation were supported Conventionally PMC connectors have four designators JN1 JN4 JN1 amp JN2 provide all the signals necessary for 32 bit PCI transactions JN3 has the 32 additional data lines required for 64 bit transfers and JN4 routes I O off the module for possible backplane access see Section A for JN4 to P2 backplane PMCX I O routing The following table lists the reference designators used on the CPMI s PMC X site The second PMC site labeled PMC2 on the front panel only supports 32 bit PCI transactions at 33 MHz There is no JN3 connector for
14. 300ESB I O Controller Hub ICH provide high speed memory control built in graphics integrated I O including Serial ATA USB 2 0 IDE supporting Ultra 100 DMA Mode for transfers up to 88 88 MB sec and 64 bit PCI X bus transfers at 66 MHz e Intel s 82541 10 100BaseTX interface accessible at the front panel e Intel s 82546 Ethernet Controller offers two 10 100 1000BaseTX support routed to J3 in compliance with PICMG 2 16 for backplane fabric switching e Upto 1 GB of DDR DRAM provided on board e PLX PCI6254 dual mode Universal asynchronous 64 bit 66 MHz PCI PCI bridge lets the CPMI act as a peripheral card or system slot module e Pigeon Point s IPM Sentry offers IPMI system management in compliance with PICMG 2 9 e Two PCI Mezzanine Card PMC expansion sites are supported one supports up 64 bits up to 66 MHz while the other supports 32 bit modules at 33 MHz e Secondary IDE port for CompactFlash on board for flash based mass storage for single slot booting e General Software s flash based system BIOS e PXE for diskless booting over Ethernet e Operating System OS and driver support including Windows NT Embedded NT XP QNX VxWorks Linux Solaris and pSOS 2 CPMI cPCI Pentium Processor Board User s Manual Dynatem Chapter 2 Related Documents a __rea _ tt 21k in a ich ici ade 4A 2 Related Documents Listed below are documents that describe the Pen
15. C modules The CPMI is shipped in an antistatic bag Be sure to observe proper handling procedures during the configuration and installation process to avoid damage due to electrostatic discharge ESD 4 1 Installing the CPM1 in a CompactPCI Chassis The CPMI features a Universal PCI X PCI X bridge to the backplane Without changing any jumpers the CPM 1 will operate as a system slot card coming up in transparent mode whereby it can initialize peripheral cards on the backplane when installed in the system slot or as a peripheral card in peripheral slots coming up in non transparent mode so that initialization will be done locally without interference from the system slot processor board 4 2 Jumper Selectable Options The CPMI contains three jumpers and a surface mount piano switch for system configuration The jumper switch PMC site and CompactFlash socket are indicated in the photo below PMCX Site inside hashed line PMC Site J7 SWI CompactFlash Socket Dynatem CPM cPCI Pentium Processor Board User s Manual 15 Chapter 4 Installation The CPMI offers a number of user configurable hardware options Grounds PRV DEV XB MEM when shunted Determines VIO for the PMCX site 1 1 2 for 3 8 VDC 2 3 for 5 0 VDC Determines VIO for the PMC site 2 1 2 for 3 3 VDC 2 3 for 5 0 VDC SW1 1 COMI is in RS 232 mode when closed RS 4xx when open SW1 2 COM2 is in RS 232 mode when closed RS 4xx when open SW1 3
16. H pi z RESVD NC in 60 24 CPMI cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs Kia DVI D2 SE DVI DZ SE DVI DT 009 Dos A DVD USB_OC0 USB_OC2 A22 _ A21 A20 Aie Ais At Ais SE DVI CLK4 DVI CLK VI HSYNC VI GREEN DVI RED DVI BLUE DVI VSYNC DVI DDCDAT D D ATO DVI DO A09 DVLDO 205 USE PON A07 USB POP 206 205 203 c A03 A02 Ao COM3 CTS WGATE HDSEL INDEX TRKO USB P1N USB P1P USB P2N USB P2P USB P3N USB P3P CompactPCI Backplane Connector J5 Row F is grounded Dynatem CPM cPCI Pentium Processor Board User s Manual 25 Appendix A Connector Pin outs A 7 PCI X Mezzanine Card PMCX Connectors JN1 JN2 JN3 and JN4 This section has the pin outs for all four PMC connectors On the CPMI connectors JN1 JN2 JN3 and JN4 are labeled P11 P12 P13 and P14 respectively This site is labeled PMCI on the front panel PX PIRO1 5 6K pull down 12 VDC Pin EA E 2 5 33 35 37 PR 44 9N Ap so sw so 13 15 17 19 21 23 25 27 9 3 4 4 4 4 4 PAR ND AD9 VI O 5 VDC REQ64 PCI X Mezzanine Card PMC1 Connector P11 Molex 71439 0164 9 1 3 5 7 9 51 53 55 57 59 61 63 VIO is jumper selectable through JP1 please see Section 4 1 26 CPMI cPCI Pentium Processor Board User s Manual Dynatem Dynatem Sign
17. al ND No connection No connection GND 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 ban 13 Et LE Li 49 21 23 25 27 29 st 33 35 37 39 RECTE BEC 45 HE INI EA 51 a 53 55 O CO mere GND 2 2 2 2 3 3 3 3 4 4 4 0 4 6 8 0 4 6 0 4 6 8 0 4 6 2 2 3 2 8 4 2 4 5 52 5 5 58 62 Appendix A Connector Pin outs TRST pulled down C BE2 80 Noconnection ACK64 62 3 3 VDC No connection PCI X Mezzanine Card PMC1 Connector P12 Molex 71439 0164 CPM cPCI Pentium Processor Board User s Manual 27 Appendix A Connector Pin outs 28 Pin Signal Pin Signal 3 GND 5 cms 6 CBE 7 cea 8 GND s vo 1 pars 5 Nocomecin 60 Noconnecion PCI X Mezzanine Card PMC1 Connector P13 Molex 71439 0164 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs PCI X Mezzanine Card PMC1 Site 1 Connector P14 Molex 71439 0164 These I O lines are optionally routed to the cPCI backplane on the listed J3 pins Dynatem CPM cPCI Pentium Processor Board User s Manual 29 Appendix A Connector Pin outs A 8 PCI Mezzanine Card PMC2 Connectors JN1 amp JN2 This section has the pin outs for both of the PMC connectors for the second PMC site label
18. button e When the CPMI is installed in a peripheral slot it can be reset by the system controller module through a conventional PCI Reset e A DS1233 monitors the on board 3 3 VDC regulated from the 5 0 VDC off the backplane and provides proper power sequencing for the CPU e A hot swap removal of the CPMI from the chassis When the ejector handles are released and the blue front panel LED is lit the board has been reset and it it safe to remove the CPM1 completely from the chassis For further information on the peripherals that play a part in the reset circuitry refer to ICH datasheet that s referenced in Section 2 There are four FRU LEDs that are routed from the IPMI controller and they are located near the front panel on the solder side of the CPM1 under PMC site 2 These LEDs cannot be seen when through the front panel Here is the signal LED correspondence Atmel ATmega 128L IPMI Controller Pin LED MOSI PB2 D11 Green MISO PB3 D11 Red OCO PB4 D12 Green OC1 PB5 D12 Red 14 CPMI cPCI Pentium Processor Board User s Manual Dynatem Chapter 4 Installation na 7a 4 Installation The following sections cover the steps necessary to configure the CPM1 and install it into a cPCI system for single slot operation This chapter should be read in its entirety before proceeding with the installation This section explains how to set up user configurable switches and jumpers and how to install CompactFlash drives and PM
19. ction 3 7 The CPMI also provides a 32 bit 33 MHz PMC site that shares its PCI bus with the 82541PI front panel Ethernet port I O is only accessible from the front panel it is not routed to the backplane as with the PMC site Both sites are compliant with ANSI VITA 20 2001 for conduction cooled systems Conduction cooled PMC modules are recommended for use with the CRPMI rugged version 3 9 Intel s FW82802AC Firmware Hub Holds the System BIOS In Flash Memory The Intel FW82802AC uses a 5 pin interface and provides 1 MByte of flash memory for the system BIOS This device can fill the 1 MB real mode memory map so only a portion its upper 256 MB is used The FW82802AC s 1 MB of memory space is segmented into sixteen parameter blocks of 64 KB each The CPM1 powers up into real mode and the BIOS is eventually shadowed into system DRAM after booting through the BIOS The 6300ESB Southbridge provides the 5 pin interface to the E82802AC The upper 256 KB of the E82802AC is located from 000C0000 000FFFFF and its full 1 MB of memory is aliased from FFF00000 FFFFFFFF where it can be fully accessed after booting up through the BIOS Here s a link to a datasheet for the 82802AC ftp download intel com design chipsets datashts 29065804 pdf Dynatem CPM cPCI Pentium Processor Board User s Manual 11 Chapter 3 Hardware Description 3 10 Clock Drivers The clock driver circuitry is shown below Cypress 28409 14 31818 MHz Pent
20. echanism is not relevant Also if XB MEM I the PCI 6540 autoloads serial EEPROM data up to Group 5 instead of Group 4 PRV DEV XB MEM JP1 Grounded Logic 0 PMCX Site 1 Signaling Voltage Selection Jumpers JP2 amp JP3 select the VIO routed to the CPM1 s PMCX amp PMC modules respectively The VIO pins determine the signaling voltage on the PMC X modules PCI X interface Refer to the PMC module s reference manual to ascertain the recommended VIO Shunting pins 1 amp 2 of JP2 amp JP3 provides a VIO of 3 3 VDC Shunting between pins 2 amp 3 routes 5 VDC to the VIO pins on the PMC X module VIO Voltage Level JP2 3 3 VDC Necessary for PCI X Operation 1 2 5 VDC PMCX Site 1 Signaling Voltage Selection 16 CPM cPCI Pentium Processor Board User s Manual Dynatem Chapter 4 Installation VIO Voltage Level JP3 3 3 VDC 1 2 5 VDC PMC Site 2 Signaling Voltage Selection The SWI switches are closed when in the on position Switch SW 1 1 determines the communication mode under which the CPM1 s COMI port will operate RS 232 or RS 422 485 COM1 Mode Selection sw RS 4xx Mode RS 232 Mode COM Selection Switch SW 1 2 determines the communication mode under which the CPM1 s COMZ port will operate RS 232 or RS 422 485 COM2 Mode Selection SW1 2 RS 4xx Mode RS 232 Mode COM Selection Switch SW 7 should be closed momentarily for about 30 seconds to restore the default
21. ed PMC2 at the front panel Connectors JN1 amp JN2 are labeled as P21 and P22 resepctively 4 5 6 7 7 9 1 INT6 6 INTH Nocomecio 8 s5VDC PCIXCAP grounded 40 LOCK Noconnecion 42 Noconnection PAR 44 GND AD9 eno 52 OBEO ADE 54 AD5 AD4 GND AD3 AD2 60 ADI ADO PCI Mezzanine Card PMC2 Connector P21 Molex 71439 0164 VIO is jumper selectable through JP3 please see Section 4 1 30 CPM cPCI Pentium Processor Board User s Manual Dynatem Dynatem Signal ND No connection No connection GND 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 ban 13 Et LE Li 49 21 23 25 27 29 st 33 35 37 39 RECTE BEC 45 HE INI EA 51 a 53 55 O CO GND 2 2 2 2 3 3 3 3 4 4 4 0 4 6 8 0 4 6 0 4 6 8 0 4 6 2 2 3 2 8 4 2 4 5 52 5 5 58 62 Appendix A Connector Pin outs TRST pulled down C BE2 80 Noconneoton ACK64 62 3 3 VDC No connection PCI Mezzanine Card PMC2 Connector P22 Molex 71439 0164 CPM cPCI Pentium Processor Board User s Manual 31 Appendix A Connector Pin outs ee iu 1k11____ __T __u e 1 ym__ M t 32 CPMI cPCI Pentium Processor Board User s Manual Dynatem Appendix B Address Maps Interru
22. evice are brought out to the J3 backplane connector in compliance with the PICMG 2 16 specification PICMG 2 16 lets the user implement fabric switching on the backplane where 2 16 compliant SBC s can communicate with each other and with an external network through switch modules that are located at either end of the backplane Optionally these two 1 Gb Ethernet ports are brought to industry standard RJ 45 connectors on Dynatem s rear I O plug in module CPMIPTB The Intel 82546 contains several PCI configuration registers It also contains a number of device registers for controlling the Ethernet operation that can be mapped to the memory space or the I O space The PCI signals specific to the CPM1 s 82546 are shown below Intel 82546 Signal PCI Bus Connection Bus IDSEL AD18 Device 2 3 6 Intel 82541 Gb Ethernet Controller For A Front Panel LAN Port The Intel 82541PI offers the following features e 10 100 and 1000BaseTX support with auto negotiation e Independent 64 KB RX and TX FIFO where the apportionment is tunable to the application e Transmit TCP segmentation IP TCP and UDP checksum offloading e Built in Phyceiver e Serial EEPROM for nonvolatile Ethernet address storage The 10BaseT 100 1000BaseTX signals are brought out to J9 an RJ 45 connector with built in magnetics on the front panel The connector also features three functioning LEDs for Linkup Network Activity and 1 Gb Link The LEDs are controlled by the Etherne
23. ium M CPU Crystal 100 MHz differential clocks for GMCH To GMCH for SDRAM Clocks ICH ITP amp CPU ICH 32 768 KHz To ICH for clocks Crystal Real Time ITP Port Clock 48 MHz MH To Ethernet Routed to ICH for Jes cut _ gt Controllers USB and UART s and Oscillators 82546 amp 82541 to the GMCH for and Watchdog Graphics To ICH for USB amp Serial To GMCH for dot clocks Clock Driver Circuitry The clocks are generated by the Cypress 28409 which is driven by a 14 31818 MHz crystal DRAM clocks are synthesized by the GMCH and Hub Interface and PCI X clocks are produced by the ICH A 32 768 KHz Crystal drives the Real Time Clock RTC on the ICH The Fast Ethernet port provided to the front panel by the 82541 and the two 1 Gb Ethernet ports provided to the backplane by the 82546 require separate 25 0 MHz oscillators one of the two oscillators is also used for the watchdog timer clock A 64 0 MHz oscillator drives the PCI 6254cPCI circuitry 3 11 IPMI amp Reset Circuitry amp LEDs The CPM with Pigeon Point System s Data Sentry system implements the mandatory management interfaces defined by the PICMG 2 9 specification to be supported in connection with an IPM Controller Optional features are listed below Several of these signals are required to be supported in cPCI boards that comply with specific PICMG 2 x specifications such as PICMG 2 1 or PICMG 2 16 for the first four signals below but with no corres
24. lled up pa Pi ADO A23 ADS Ace azz A7 ADG ADS A21 ADS Gato A20 ADTO RE GND ADIS SE PAR CBETA At GND PERRA Ais LOOK SE TROVA Ara KEYT3 NG SE KEY14 NC BE KEV NC A GND Ben ATO 7019 A09 ces Bos GNDMIDSEL cos Apes pes eo 122 205 Das A07 GND Ae A06 meoo sos END cos ssvoct os omo Eos asi A05 GND SAT 203 NTS A03 TOS A02 TDI NG CompactPCI Backplane Connector J1 Row F is grounded Dynatem CPM cPCI Pentium Processor Board User s Manual 23 Appendix A Connector Pin outs GAO RESVD NC RESVD NC RESVD NC RESVD NC GNT6 RESVD NC GNT5 AD32 Am GM A21 GA4 RESVD NC R R R ESVD N NC NC G G G G G G G G G 3 D D D NC D NC D D D D D NC D D eis ow GND Cis FALE uted Up eno cos Dos eno cor Dos C BES VI O RESVD N REQ2 CompactPCI Backplane Connector J2 Row F is grounded REQ4 A N N N N N N N N N N CLK2 CLK1 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 RESVD NC LPa DC gi LPa DD a LPa_DC LPa_DA LPa_DD LPa_DB LPa_DA LPa_DB LPb_DC LPb_DA LPb_DA A i P DIO P P P Dog P P Dos LPb DC 3 3 VDC 3 3 VDC 3 3 VDC 5 VDC MCI O pin 5 MCI O pin 4 MCI O pin 3 MCI O pin 10 P P P P P P P P CompactPCI Backplane Connector J3 Row F is grounded P P PUG
25. m Chapter 1 Features 1 Features The Dynatem CPMI is a single slot 6U cPCI Single Board Computer SBC The CPMI offers full PC performance with a Pentium M low power processor The CPMI is available in two versions the lower cost CPM1 for standard industrial applications and the 1101 2 compliant conduction cooled CRPM1 with wedgelocks stiffener bar and a full board heatsink for rugged applications When referring to attributes of both versions we will use the name CPM1 The CPM1 employs Intel s embedded technology to assure long term availability Features of the CPMI include e Single slot cPCI operation with on board CompactFlash disk for bootable mass storage and front panel connectors for two RS232 485 COM ports a 1 Gb Ethernet port I O for two PMC sites and PS 2 Mouse Keyboard ports e Primary IDE DVI I graphics four USB 2 0 ports two Serial ATA ports and Super I O generated Floppy Disk drive interface and undriven COM3 amp 4 ports are routed out to the backplane via the J5 connector e Two Gb Ethernet ports in compliance with PICMG 2 16 and PMC I O for Slot B in compliance with PICMG 2 3 R1 0 are routed to J3 Dynatem CPM cPCI Pentium Processor Board User s Manual 1 Chapter 1 Features n e r 6 m 121t e The Intel 855GME Graphics Memory Controller Hub GMCH and Intel 6
26. nt I O cards and multi processor systems The bridge is CompactPCI Hot Swap Ready and complies with PICMG 2 1 R2 0 with High Availability Programming Interface level 1 PI 1 The CPMI reset circuitry is tied to the bridge since the CPMI can generate the cPCI SYSRESET signal as well as be reset by another cPCI board that asserts the SYSRESET signal The CPMI reset circuitry is discussed in detail in Section 3 12 This section supplements the PCI to PCI Bus Bridge documentation downloadable from PLX Technology s website at http www plxtech com products fastlane bridges default asp which contains comprehensive descriptions of the operation and programming of the PCI 6254 and PCI6540 devices 3 8 PCI X Mezzanine Card PMCX and PMC Expansion The CPMI has two PMC I O expansion slots one 64 bit PCI X compatible site and one 32 bit at 33 MHz site The CPMI supports a PCI X Mezzanine Card PMC site on board where the I O can be routed out through the J3 connector please see Appendix A or accessed from the front panel This first PMC site shares its PCI X bus with the PCI bridge to the backplane and with the 82546GB dual 1 Gb Ethernet controller that provides two PICMG 2 16 compliant LAN ports through J3 to the backplane This site supports 64 bit PCI X transfers at 66 MHz 33 MHz PMC cards or PMC cards not capable of PCI X transfers can be used in this site but they will limit the 82546GB and the PCI bridge to their capabilities see Se
27. of their functionality e Link Ethernet link is established when this LED flashes yellow e 1Gb mode Ethernet data is being transmitted at 1 Gbps when this LED flashes green 18 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A Connector Pin outs The locations of the CPM1 connectors are shown below The connectors that do not go to the front panel have their pin 1 location designated accordingly a Pero INA lose L men JN2 am o FE E IR 33 KA RAR J10 J10 Mouse Kybd Dynatem CPM cPCI Pentium Processor Board User s Manual 19 Appendix A Connector Pin outs AA COM1 amp COM Front Panel Connectors J8 Connector J8 provides two RS 232 interfaces at the front panel via a stacked pair of Micro D sub miniature MDSM DB 9 connectors Both connectors have the same pin out The connector for COM2 is lower and closer to the printed circuit board RS 232 Signals Data Carrier Detect DCD Input Received Data RxD Input Transmitted Data TxD Output Data Terminal Ready DTR Output Request To Send RTS Output Clear To Send CTS Input Ring Indicator RI Input COM1 amp COM2 Connector J8 Front Panel DB9M Connector The metal shell of the connectors go to chassis ground A 2 Gb Ethernet Front Panel Connector J9 The CPMI uses an RJ45 connector to provide an Ethernet port at the front panel J9 has a built in yellow LED for
28. ontroller Hub Datasheet Document 300641 002 34 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix C Power and Environmental Requirements ur__ ___rmr nung eGQzoii P TTmtT5T FIVIsiss erro rs xe arl C Power and Environmental Requirements The CPM1 power and environmental requirements are shown in the tables below 1 4 MHz Pentium M 5 VDC 2 0 A typ 3 3 VDC 2 0 A typ 3 0 VDC Lithium Coin Cell 3 4 uA Power Requirements The 3 Volt lithium coin cell is a CR2032 with 190 mAhours capacity and it is used to battery back the Real Time Clock the 2 MB of NV SRAM and the BIOS s NV RAM At 3 4 UA this battery should last for over six years with power off Operating Temperature 40 to 471 C Storage Temperature 50 to 105 Environmental Requirements Dynatem CPMI cPCI Pentium Processor Board User s Manual 35 Appendix C Power and Environmental Requirements ae SS C CV pio EC CP CC C CU RR ea ____o w 36 CPM cPCI Pentium Processor Board User s Manual Dynatem Appendix D CPM1PTB Rear Plug in I O Expansion Module for the CPM1 D XPM1RIO Rear Plug in I O Expansion Module for the CPM1 Much of the CPM1 s I O is driven directly through the J3 and J5 connectors so a rear plug in module is useful for interfacing to industry standard cables The XPMIRIO is available for this purpose Here is a photo of the XPMIRIO J3 J5 FDC J8 IDE J7 RS
29. ponding requirement that the IPM Controller on a board have any particular responsibility or control regarding them BD SEL signal Handle switch Hot swap LED HEALTHY signal Fan control and monitoring 12 CPM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description The reset circuitry is shown below 3 Volts PCI PCI Bridge to the CompactPCI Backplane cPCI Blue LED on front SYSRESET panel means eject is OK ENUM Atmel ATmega 128L IPMI Controller Front Panel 8 VCSR SET RES Reset Switch PB1 amp PRST on il backplane SYSRESET BD_SEL Payload Interface 6300ESB ICH LPC Interface SYSRESET Reset Control Register Pentium M soft reset Ejector Handle PCI Reset PCI peripherals PWRGD VR Vcore Monitor Pentium M hard reset 9 2 5 V Good PD Reset Circuitry Dynatem CPM cPCI Pentium Processor Board User s Manual 13 Chapter 3 Hardware Description r 5 z 5 There are multiple ways to perform a hard reset of the CPMI e A simple power cycle turn the chassis power off and on e There are two options for using a push button reset the momentary push button switch that s accessible at the CPM l s front panel near the lower ejector handle the PRST signal on the backplane connector J2 pin C17 that is generally connected to the chassis reset
30. pts DMA Channels B Address Maps Interrupts DMA Channels Tables of the CPM1 s address maps interrupt request assignments and DMA channel usage are given in the following sections All addresses are shown in hexadecimal notation B 1 Memory Map The CPM1 s memory map is shown below 00000000 000FFFFF DOS legacy address range 00100000 Top of On board DDR SDRAM Memory On board DDR DRAM 1GB Top of On board DRAM Memory FEBFFFFF PCI Device Allocation FEC00000 FEEFFFFF APIC Configuration Area unused on CPM1 FFE00000 FFFFFFFF High BIOS Area This is the memory map on the GMCH For further details on the CPM1 memory space map refer to Section 5 1 in Intel s 855GM 855GME Chipset Graphics and Memory Controller Hub GMCH Datasheet Document 252615 004 available from Intel Corporation B 2 PCI Configuration Space Map The PCI configuration space map will vary if the PMCX expansion slot is used to support a PMCX add on mezzanine card and if that PMCX module uses a expansion bridge designed for multiple targets on the secondary bus This is an extremely unlikely situation but the bus numbers in this condition will differ from those provided in the following table The Vendor ID and Device ID in hex for the PMCX slot are shown as xxxx since they depend on the type of device installed in the PMC slot ose Bus bev Fen ven bed Deseo 6300ESB ICH P2P Bridge 6300ESB ICH P2L Bridge 5A2
31. rals cannot operate in PCI X mode if they share their PCI bus interface with the PCI6254 The PCI cPCI interface based on the PLX PCI 6254 on PWB 010 6057 002 offers the following features e 64 bit 33MHz 66MHz Asynchronous operation e KB FIFO for efficient PCI PCI bridging and speed conversion e Transparent and non transparent bridge operation e Usable in the cPCI system slot or a peripheral slot e Supports hot swapping to eliminate the mid transaction extraction problems associated with cPCI The block diagram of the PCI PCI interface is shown below 6300ESB IPMI amp Reset Input Output Controller Hot Swap Control Hub E PCI X interface sensnm PCI6254 on boards PWB D010 6057 002 no PCI X SYSEN determines system slot or peripheral operation PCI6540 on boards Controller PWB D010 6057 003 AD32 AD63 and later PCI X cPCI P2 Connector I O from PMC X P14 cPCI P3 Connector PCI cPCI Backplane Interface Block Diagram Dynatem CPM cPCI Pentium Processor Board User s Manual 9 Chapter 3 Hardware Description eere Tri z5 0 The PCI X to cPCI X interface based on the PLX PCI 6540 offers the following features e 64 bit PCI X r1 0b compliant asynchronous operation limited to 66MHz by the 6300ESB south bridge e 10 KB FIFO for efficient PCI X to PCI X bridging and speed conversion e Transparent and non transparent bridge operation e Usable in the cPCI system slot or a peripheral slot
32. t circuitry The pin out for J9 is given in Appendix A The Intel 82541 contains several PCI configuration registers It also contains a number of device registers for controlling the Ethernet operation that can be mapped to the memory space or the I O space The 82541 is controlled by the PCI interface of the ICH The PCI signals specific to the Intel 82541 are shown below Intel 82541 Signal PCI Bus Connection Bus 3 IDSEL AD17 PCI Device 0 PREQ REQ1 PGNT GNT1 ia INTG 8 CPM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description For further information on the 82541 refer to 82541 Fast Ethernet Multifunction PCI Cardbus Controller available from Intel Corporation Please go to the link at http www intel com design network products lan controllers 82541ei htm 3 7 PLX PCI6254 amp PC6540PCI cPCI Interfaces Section Under Construction The CPMI uses two different PCI bridges to the backplane depending on the revision of the module The first revision of the board identified by PWB 010 6057 002 etched on the printed circuit board near the top card puller uses PLX s PCI6254 PCI PCI bridge On subsequent versions of the CPMI this chip was replaced by the PLX PCI6540 as it supports PCI X to PCI X transfers and the primary side of the bridge is shared with the PCI X compatible 82546 dual 1 Gb Ethernet controller chip and possibly PCI X compatible PMC modules in PMC site 1 These periphe
33. tes are routed through J5 e Standard PC functionality like a battery backed RTC and 256 bytes of CMOS RAM Power Management Logic Interrupt Controller Watchdog Timer AC 97 CODEC Integrated 16550 compatible UART s and multimedia timers based on the 82C54 For further information see the documents referenced in Section 2 3 4 DRAM The CPMI supports a 72 bit wide DDR 266 memory interface with memory bandwidth of 2 1 GB s with ECC The module can be populated to support 512 MB or 1 GB of DRAM 3 5 Intel 82546EB Dual Gigabit Ethernet Controller The CPMI supports two 10 100 1000BaseTX channels accessible from the backplane The Intel 82546EB Dual Port Gigabit Ethernet Controller incorporates two full Gigabit Ethernet MAC and PHY layer functions on a single compact component The CPM1 uses the PCI X interface of the ICH to control the 82546EB Therefore the front side data path to the dual Ethernet port controller is 64 bits at 66 MHz The Intel 82546EB offers the following features e 10 100 and 1000BaseTX support with auto negotiation e Dual 64KB configurable RX and TX packet FIFOs e 128 bit internal data path architecture for low latency data handling and superior DMA transfer rate performance e Built in Phyceiver e Serial EEPROM for non volatile Ethernet address storage Dynatem CPM cPCI Pentium Processor Board User s Manual 7 Chapter 3 Hardware Description r5 55553 Both 10 100 1000BaseTX ports of the 82546 d
34. through SW1 6 Unused SW1 7 Close momentarily to flush RTC and NV RAM and revert to BIOS defaults SW1 8 MUST STAY CLOSED on board BIOS is disabled when open Jumper JP1 determines the status of PRV_DEV XB_MEM PRV DEV when in the Transparent Mode When set to 1 the PCI 6540 can mask secondary devices using IDSEL connected to S_AD 23 16 as private devices Any Type 1 Configuration access to these IDSELs is routed to AD24 If there is no device on S AD24 the re routed Type 1 Configuration cycles are Master Aborted The PCI 6540 also reserves Private Memory space for the secondary port The Memory space can be programmed using the Private Memory Base and Limit registers Base PVTMBAR PCI 6Ch and VTMBARU32 PCI 70h Limit VTMLMT PCI 6Eh and PVTMLMTU32 PCI 74h If the limit is smaller than the base Private Memory space is disabled The primary port cannot access this Memory space through the bridge and the secondary port does not respond to Memory cycles addressing this Private Memory space XB MEM when in the Non Transparent Mode When set to 1 the PCI 6540 automatically claims 16 MB of Memory space This allows the boot up of the Low Priority Boot port to proceed without waiting for the Priority Boot port to program the corresponding Memory Base Address registers BARs Although the default claims 16 MB the BARS can be modified by serial EEPROM or software to change the window size If XB MEM I the P PORT READY or S PORT READY m
35. tium processor and chipset and the peripheral components used on the CPMI Either download from the Internet or contact your local distributor for copies of these documents The CPMI uses the Low Voltage Pentium M For information on this processor go to http www intel com design intarch pentiumm pentiumm htm For the ICH component in the 6300ESBchipset get the Intel e 6300ESB I O Controller Hub Datasheet It is document number 300641 003 http www intel com design intarch datashts 300641 htm For the GMCH component in the chipset get the Intel e 855GM 855GME Chipset Graphics and Memory Controller Hub GMCH Datasheet It is document number 252615 005 http www intel com design chipsets datashts 252615 htm For data sheets on I O controllers e 82546EB Fast Ethernet PCI Controller http developer intel com design network products lan controllers 82546 htm e 62541EI Ethernet PCI Controller http developer intel com design network products lan controllers 82541ei htm e CompactPCI Specification PICMG 2 0 R3 0 and other Compact PCI Specifications http www picmg org compactpci stm CompactPCISpecifications The following documents provide information on the PC architecture and I O e PCI Local Bus Specification Revision 2 2 http www pcisig com specifications e PCI X Specification Revision 1 0A http www pcisig com specifications e System Management Bus Specification SMBus Revision 1 1
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