Philips Semiconductors Application of the P8xC592 microcontroller
Contents
1. Terminal PC 12V Display CEOE O O Connector RS232 Power Interface Supply Wrap E Field P8xC592 lt O ne on chip CAN X lu i P8xC592 Evaluation Board A x Philips Components c 1990 N p m Tee C Physical Application Layer E ll g Interface OO S 2 CAN Bus Wires Fig 14 P8xC592 Evaluation Board Philips Semiconductors Application Note HKI AN 91 014 eee 5 1 1 P8xC592 Evaluation Board Hardware The P8xC592 evaluation board hardware single EURO format size is shown in figure 14 It consists of o P87C592 microcontroller with an external memory capacity of 32 KBytes for RAM and 32 KBytes for ROM storage Together with the on chip EPROM there are 48 KBytes of continuous program memory o 5V power supply with protection against car battery voltage fluctuations o off chip transceiver circuit designed to meet ISO TC 22 SC 3 N608E with two selectable op tions very low standby power consumption support of single wire communication to recover from wiring failures o RS232 interface o removable LED unit for demonstration purposes o wrap field for the user s specific circuitry 5 1 2 P8xC592 Evalu2. P8xC592 to other on chip CPU to CAN interface peripherals bu109053 Fig 6 Block diagram of the CPU to CAN interface Philips Semiconductors Application Note HKI AN 91 014 10 4 2 1 CAN Related Special Function Registers Table 1 shows the special function register arrangement Note that CANCON and CANSTA have different meanings for a read and write access MSB LSB SFR ADR ACS 7 6 5 4 3 2 1 0 CANADR D8H R W DMA reserved Autolnc CANA4 CANA3 CANA2 CANA1 CANAO CANDAT DAH R W CAND7 CAND6 CAND5 CAND4 CAND3 CAND2 CAND1 CANDO Wake up Overrun Error Transmit Receive CANCON D9H R reserved reserved reserved Int Int Int Int Int RXO RX1 Wake up Slee Clear Release Abort Transmit w active active Mode P Overrun Rx Buffer Transm Request Bus Error Transmit Receive TX compl Tx Buffer Data Rx Buffer CANSTA D8H R Status Status Status Status Status Access Overrun Status W RAMA7 RAMA6 RAMA5 RAM4 RAMA3 RAMA2 RAMA2 RAMA1 HA107221 Table 1 CAN Special Function Registers CANADR With the least significant bits CANA4 CANAO each of the CAN controller internal registers can be addressed by a write access to CANADR Reading or modification of the particular CAN register then is done by reading or writing to CANDAT CANADR is implemented as a read write register which also contai
3. CRXO IN CRX1 Table 7 Results of setting RXOA RX1A With the help of the described comparator switches three configurations can be selected o two wire communication differential signal o single wire communication using CAN_H o single wire communication using CAN_L Thereby a test of the bus wires can be implemented easily by software if single wire communication is possible in the network with each of the bus lines as well as differential communication then there is no wiring failure Otherwise the faulty wire is detected diagnosis and the network may continue to communicate on the other wire till the faulty wire is repaired For more details on CAN Bus failure management please refer to 8 Philips Semiconductors Application Note HKI AN 91 014 16 4 4 Control of CAN Communication Information about the reception of messages the completion of a transmission data overrun error status etc can be signalled to the CPU either with interrupt processing described in chapter 4 4 1 or with polling described in chapter 4 4 2 It can be of advantage to mix both polling and interrupt control Note that the wake up event can only be processed by interrupt 4 4 1 Interrupts The P8xC592 controls five different CAN related interrupt sources These are the Receive Transmit Overrun Error and the Wake up Interrupt All interrupts can be enabled disabled via the Control Register except of the Wake up In
4. tpitTmin tBI tsJwW LY ESC 21 25 us tpiTmax tBIT tsgw 23 tscL 28 75 us define bus driver characteristics write OUTPUT CONTROL REGISTER example contents of OUTPUT CONTROL REGISTER 10101010B results in output mode normal 1 bit sequence on TXO and TX1 pins TXO configuration bit state 0 1 gt output state low float TX1 configuration bit state 0 1 gt output state high float end initialization write to CONTROL REGISTER enable interrupt sources DIES Ae tata VA define mode of reference voltage bit 5 x define the resynchronization mode SYNCH bit 6 set RESET REQUEST absent bit 0 start of comment end of comment Table 4 Flow chart of an initialization procedure Philips Semiconductors Application Note HKI AN 91 014 14 4 3 3 Reception Whenever the status bit Receive Buffer Status is set a new message is available in the Rx Buffer Polling the Status Register enables the information of new message data in the Rx Buffer to be coordinated and controlled by the CPU When the Receive Interrupt is enabled the according bit in the interrupt register is set simultaneously with the Receive Buffer Status bit and the interrupt service can start with reading of message data from the Rx Buffer After Reading the buffer contents the CPU has to release t
5. and bit rate The term 7 receive interrupt execution time message length only depends on the data length code as it is shown in fig 11 Using this formula the CPU load can be calculated for any bit rate at any bus load for example a bus load of 10 at 400kbit s with only one byte messages copy all of them means 10 0 4 Mbit s 0 6 us bit 2 4 of CPU load For the example of 4 byte messages DLC 4 the CPU load has been calculated for different bit rates and different bus loads the result is shown in table 13 Philips Semiconductors Application Note HKT AN 91 014 25 T 0 7 ES N 0 6 X N Si 0 5 e gt xN Copy Sg SS SS 0 4 a m e LS an e PA oe 0 3 Reject ne e N o 0 2 O TT a TT nario T 9 2 3 4 5 6 7 8 receive interrupt execution time T message length Data Length Code pm Fig 11 Diagram for calculation of the CPU load while receiving messages bit rate 10 bus load 20 bus load 50 bus load 100 kbit s 0 4 0 8 2 1 250 kbit s 1 0 2 1 5 2 500 kbit s 2 1 4 2 10 1 Mbit s 4 2 8 4 21 Table 13 CPU load when 4 byte messages DLC 4 are used for worst case copy all of them 4 6 2 Spare Time But what happens when the CAN interruptis delayed or interrupted e g by other interrupt service routines with same or higher priority The first statement is that the CAN receive interrupt can be delayed for at least
6. controller and the P8xC592 s main RAM canbe done in extremely short time by using Direct Memory Access DMA More information about this feature is given in chapter 4 2 3 The P8xC592 has a 256 bytes on chip auxiliary RAM which is indirectly addressable in the same way as external data memory This doubling of internal RAM capacity satisfies the rising demand for parameter storage in distributed control applications Summarizing the P8xC592 is a single chip 8 bit microcontroller featuring o 80C51 CPU CAN controller with DMA 16K bytes ROM EPROM 2 256 bytes RAM 10 bit A D converter 8 channels 3 16 bit timer counters 4 capture registers 3 comparators controlling 8 outputs 6 8 bit I O ports 2 PWM outputs full duplex UART interrupt controller 15 sources watchdog timer Philips Semiconductors Application Note HKI AN 91 014 3 Hardware Aspects This section covers hardware considerations of a CAN based module in a network The first part describes the minimum circuitry required for the P83C592 P87C592 The second part gives suggestions for the connection of the controller to the CAN bus wires 3 1 Main Circuitry The P8xC592 is designed to work with a minimum of external components Fig 3 shows the circuitry of a CAN node using the ROM or EPROM version P83C592 or P87C592 The only additional components that are required are a crystal Q1 plus two small capacitors C1 C2 to drive th
7. fully transparent real time emulation o allows optimal emulation according to the exact specification of the target controller o emulation memory 64 KBytes with no wait states o interfaces to external equipment o full assembly level debugging o HLL debugging possible o single step and breakpoint setting o trace and triggering with hardware qualifiers o trace memory 2048 lines o new improved handbook o probes for optimal connection to the target system optimal emulation of the target uC For emulation of the P8xC592 the user needs the following parts o SDS80C51 stand alone debug system OM4120S o probe base OM4110 o emulation head 592 OM4112 Software for development support with the SDS assembler PL M compiler C compiler HLL debugger is offered and supported by Tasking B V Plotterweg 31 3821 BB Amersfoort Netherlands their products can also be ordered via Philips 5 2 2 ICE from Other Vendors Philips supports all major third party ICE suppliers with emulating chips for the P8xC592 Most of them already announced to support the P8xC592 5 3 Programming Support for P87C592 EPROM Philips offers a low cost programmer for microcontrollers inclusively the P87C592 o LCPX5X40 programmer OM4232 87C592 PLCC68 adaptor OM4235 Philips Semiconductors Application Note HKI AN 91 014 30 5 4 Debug Tools for CAN Communication In addition to the P8xC592 evaluation board three other so
8. load for CAN communication is very low as the analysis of the following communication example proves Simulations with NetSim a simulator for CAN communication see chapter 5 4 have been done with a real communication example of 7 nodes Ata data rate of 500kbit s 12 different messages M are transferred on the bus Fig 7 shows the structure of the network M3_2 means 2nd type of message that is transmitted by node number 3 for instance Node1 Node2 Node3 Node4 M1_1 M2_1 M3_1 M4_1 M2_2 M3_2 M4 2 omen JT Y E JT Node5 Node6 Node7 M5_1 M6_1 M7_1 M5_2 M6_2 HA107161 Fig 7 Network example The communication matrix and information about message length repetition time and node numbers are given in table 10 whereby the described communication of the example with the according messages results in a total bus load of about 23 The CPU load for CAN communication is defined as the percentage of time the CPU is serving the CAN communication its calculation is described in detail in chapter 4 6 The diagram of figure 8 shows the CPU load of nodes 1 7 split up in receive and transmit actions of the CPU Receive actions are executed for all messages that pass the acceptance filter These messages are copied into the CPU RAM except they are not of interest for the CPU the latter means they are rejected
9. load have been investigated by using a reference software fig 9 Appendix A 1 that uses the receive interrupt service routine It also checks the data overrun condition in order to evaluate the Spare Time The described software and the results are an example and transformation to user specific requirements is very easy Init P8xC592 Receive Interrupt Service Routine Main Loop LED Pet Indication Overrun Loop HA110163 Fig 9 Reference software with Receive Interrupt Service Routine Philips Semiconductors Application Note HKI AN 91 014 First of all the arrangement of the reference software is given in a short summary Identifier Interrupts Data Copy Remote Frames Overrun Reject 22 1D10 ID9 ID8 ID7 are fixed by acceptance filter e g ID 0101 XXXX XXX Receive Interrupt enabled data bytes according data length code and a part of the identifier as an indication for a new message are copied into the internal yC Main RAM in case of remote frame reception the data length code is deleted and only a part of the identifier is copied as an indication of its reception the overrun status bit is checked in the main loop Whenever an overrun condition would be detected indication would be done via LED The program remains in the overrun loop until reset Messages which pass the acceptance filter but are useless for the uC are rejected by the softwa
10. to the required communica tion parameters Before setting the registers in the Control Segment see fig 5 first the Reset Request bit in the Control Register has to be set to present high An initialization procedure should include definitions of the following items o Acceptance Filter o Bus Timing o Output Mode o Interrupts o Reference Voltage Mode A flow chart of the initialization procedure is shown in table 4 When the configuration of the P8xC592 is finished the Reset Request bit has to be set to absent to allow receive or transmit operations 4 3 2 Transmission The CPU may write a message into the transmit buffer whenever the transmit buffer access bit Status Register is set After writing the message to the transmit buffer and setting the transmission request bit high Command Register the CAN Controller begins with the transmission process If the CPU cannot access the transmit buffer because a previously requested message is still waiting for transmission it is possible to abort the current process A transmission already in progress is not stopped if status bit TRANSMIT BUFFER ACCESS released then ls write message into if lt high priority message to be transmitted gt TRANSMIT BUFFER then oe t else set command bit set command bit TRANSMISSION ABORT TRANSMISSION present REQUEST present gt the ne
11. use of single wire decoding is beneficial to continue communication when one of the two bus lines has a wiring failure open or short circuit please refer to 8 4 Software Aspects 4 1 CAN Registers The P8xC592 s on chip CAN controller is a full implementation of the CAN protocol It contains all necessary features required for a high performance communication protocol The CAN controller appears to the CPU as a memory mapped I O device which is arranged as Control Segment Transmit Tx Buffer and Receive Rx Buffer see fig 5 Exchange of status control and command signals between the CPU and the CAN controller is done by the control segment which contains 10 bytes It is programmed during initialization for configuration of the communication parameters Additionally the CPU controls the CAN communication via this segment Data to be transmitted are loaded into the Transmit Buffer by the CPU The buffer contains the descriptor Identifier RTR bit and DLC and up to eight data bytes After a successful reception messages are read from the Receive Buffer It consists of two 10 byte memories which are alternatively used to store messages The CPU can process one message while another is being received 4 2 On chip Interface Between CPU and CAN Controller To access the described CAN controller registers four special function registers CANADR CANDAT CANCON and CANSTA are implemented All CAN registers of the Control Segment whi
12. 4 34 Receive Interrupt Service Routin CAN_INTERRUPT CONTEXT_SWITCH 6 cycles PUSH ACC PUSH PSW USING 1 SETB RSO CLR RSL CLEAR_INTERRUPT 1 cycle CLR_INT OV A CANCON clear interrupt bits RX_INT_TARGET_ADDR 15 cycles BEGIN_RX OV CANADR AUTO_RX_BUFFER set auto incr and CANA 20dec OV A CANDAT fetch RX buffer ANL A 0FH upper 4 bits masked per acceptance filter OV R1 A OV A CANDAT fetch RX buffertl OV R5 A temp save of RX buffer 1 ANL A 0E0OH ID2 1D1 1D0 0 0 0 0 0 RR A gt 0 IDZ IDEID O70700 ORL A R1 0 1D2 1D1 ID0 1D6 1D5 1D4 1D3 ADD A TABLE TABLE_BASE MOVC A A PC accu contains the target address TABLE_BASE JZ RELEASE_BUF software reject no data copying RX_INT_COPY_DATA_LOOP_DMA 8 cycles OV CANSTA A target address for DMA OV A R5 get RX Buffer 1 JNB ACC 4 DMA_START test of RTR bit OV CANADR RX_BUFFER 1 in case of a Remote Frame ANL CANDAT O0FOH delete data length code only the descriptor byte is copied DMA_START OV CANADR DMA_RX_BUFFER 1 OP wait for data transfer OP RX_INT_ACKN 2 cycles RELEASE _BUF OV CANCON 4 release receive buffer RESTORE_CONTEXT 6 cycles END_RX POP PSW POP ACC RETI RX_INT_TARGET_
13. 820200 P8xC592 PHYSICAL INTERFACE PHYSICAL INTERFACE PHYSICAL INTERFACE CAN Bus Line bu108073 gem Fig 1 Example of a Controller Area Network The P8xC592 is a stand alone high performance microcontroller designed for use in automotive and general industrial applications In addition to the 80C51 standard features this device provides a number of dedicated hardware functions for these applications It basically combines the functions of the well known P8xC552 microcontroller 9 without re hardware and the PCA 82C200 Philips Stand alone CAN controller 3 with some enhanced features Philips Semiconductors Application Note HKI AN 91 014 The CAN part of the P8xC592 fulfills the complete CAN specification to provide the following important features o multi master operation in a serial communication network with an unlimited number of active network nodes o programmable data transmission rate up to 1 Mbit s o very low probability of undetected errors due to powerful error handling o 40 m maximum distance between two bus nodes at a data transmission rate of 1 Mbit s lower transmission rates allow even longer distances o guaranteed latency time supporting real time applications This Application Note covers the CAN related items of P8xC592 applications It describes a simple circuit example for a module in a CAN network To apply and understand t
14. ADDRESS_ TABLE TABLE copy data of message 01010101000 to ARRAY_LONG 8 1 bytes copy data of message 01010101010 to ARRAY_SHORT 0 1 byte DB 0 0 0 0 0 ARRAY_LONG 0 0 0 0 0 0 0 0 0 0 1D2 0 ID1 0 ID0 0 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID2 0 ID1 0 ID0 1 DB 0 0 0 0 0 ARRAY_SHORT 0 0 0 0 0 0 0 0 0 0 1D2 0 ID1 1 ID0 0 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID2 0 ID1 1 IDO 1 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1D2 1 1D1 0 1D0 0 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID2 1 1D1 0 IDO 1 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1D2 1 1D1 1 1D0 0 DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1D2 1 1D1 1 1D0 1 END Philips Semiconductors Application Note HKI AN 91 014 A 2 Transmitter part 35 Tx Procedur This module is a program including a transmit procedure using a loop that copies data from the internal MC RAM to the Tx buffer of the P8xC592 It runs on the P8xC592 Evaluation Board for instance When the contents of the buffer is transmitted on the CAN bus Therefore it generates ver the controller gets bus access Load The Identifier of the message has been chosen such that it will be received by the reference software see Appendix A 1 a very high bus CONTROL EQU OH COMMAND EQU 1H STATUS EQU 2H INTERRUPT EQU 3H ACCEPTANCE_CODE EQU 4H ACCEPTANCE_MASK EQU 5H BUS_TIMING_0O EQU 6H BUS_TIMING_1
15. Application Note Application of the P8xC592 microcontroller with CAN interface Peter Buehring Peter Hank Product Concept amp Application Laboratory Hamburg F R Germany Keywords P8xC592 microcontroller on chip CAN controller CPU load Report No HKI AN91 014 Date 92 07 02 Pages 36 Philips Export B V All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Philips Semiconductors Pan PHILIPS Summary The integrated circuit P8xC592 from Philips is a single chip high performance microcontroller designed for use in automotive and general industrial applications It is a high end derivative of the 80C51 family CMOS microcontrollers In addition to the 80C51 standard features the P8xC592 provides a number of dedicated hardware features for sophisticated control applications It includes timers A D converter PWM output UART and a CAN protocol controller CAN Controller Area Network for serial communication The P8xC592 covers the complete CAN specification offering important f
16. Board OM4239 for instance With only little modifications it can be adapted to other applications The receive interrupt execution time is less than 34us and every software reject is done within 28us The acceptance filter of the CAN part is set to 0101 XXXX XXX Upon reception of a message which passes the acceptance filter the data bytes plus the second byte of the Rx buffer for signalling the reception of new data to the main program are copied into the internal RAM of the P8xC592 according to a table In this table for each message the corresponding RAM address Can be found or a 0 telling that the message is not of interest and shall be rejected In case of an overrun condition indication is done via LED CONTROL EQU OH COMMAND EQU 1H STATUS EQU 2H INTERRUPT EQU 3H ACCEPTANCE_CODE EQU 4H ACCEPTANCE_MASK EQU 5H BUS_TIMING_O EQU 6H BUS_TIMING_1 EQU 7H OUTPUT_CONTROL EQU 8H CANADR EQU ODBH CANDAT EQU ODAH CANCON EQU OD9H CANSTA EQU OD8H AUTO_RX_BUFFER EQU 34H RX_BUFFER EQU 14H DMA_RX_BUFFER EQU 94H INT_MASK EQU 00000010B Rx Interrupt enabled ES1 BIT OADH DSEG AT 30H ARRAY_LONG DS 9 space for Rx of an 8 byte message ARRAY_SHORT DS 1 space for Rx of a O byte message BIT_VAR SEGMEN DATA BITADDRESSABLE RSEG BIT_VAR INT_SAVE DS 1 RX_INT BIT INT_SAVE 0 CSEG AT
17. EQU 7H OUTPUT_CONTROL EQU 8H CANADR EQU ODBH CANDAT EQU ODAH CANCON EQU OD9H CANSTA EQU OD8H DMA_TX_BUFFER EQU 8AH DSEG AT 30H ARRAY DS 10 CSEG AT RESET LUMP AAIN_PROG MAIN SEGMENT CODE RSEG MAIN MAIN_PROG OV SP 7FH CLR EA OV DPTR 4000H OV A 0FFH OVX DPTR A OV ARRAY 0 01010101B OV ARRAY 1 00001000B OV ARRAY 2 011H OV ARRAY 3 022H OV ARRAY 4 033H OV ARRAY 5 044H OV ARRAY 6 055H OV ARRAY 7 066H OV ARRAY 8 077H OV ARRAY 9 088H Initialization set stackpointer disable all interrupts ee Ul T E D NENE NE NE NE NE NENEN Se e EDs dark D10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 D2 1D1 IDO RTR DLC3 DLC2 LC1 DLCO lst data byte 2nd data byte last data byte Philips Semiconductors Application Note HKI AN 91 014 36 INIT_CAN OV CANADR CONTROL reset request OV CANDAT 00000001B OV A CANDAT JNB ACC 0 INIT_CAN repeat reset if reset request is absent OV CANADR ACCEPTANCE_MASK acceptance filter not used for Tx OV CANDAT FOFFH OV CANADR BUS_TIMING_O OV CANDAT 80H OV CANADR BUS_TIMING_1 OV CANDAT 23H OV CANADR OUTPUT_CONTROL OV CANDAT FOFAH OV CANADR CONTROL OV A CANDAT ANL A 11111110B reset request bit 0 OV CANDAT A Tx Loop BEGIN_TX OV CANSTA ARRAY target RAM address WAIT JNB CANSTA 2 WAIT wai
18. HKI AN 91 014 4 4 2 Polling 18 Analysing the contents of the Status Register as shown in table 9 is very similar to analysing the contents of the Interrupt Register With the following overview the concerning Status bits are described Receive Buffer Status Transmit Buffer Access Error Status Data Overrun the warning limit be stored this bit is set This bit is set when a new message is available The CPU may write a message to the Tx Buffer when this bit is set The Error Status bit is set when at least one of the Error Counters has reached When both Receive Buffers are full and the first byte of a new message should if TRANSMIT BUFFER ACCESS released z then ls a next message may be written into the TRANSMIT BUFFER if lt using the ABORT TRANSMISSION command gt then ls fy if TRANSMISSION COMPLETE STATUS complete last requested then ls transmission has last requested last requested been completed transmission has transmission has not Ei been completed been completed due to no ABORT TRANS an ABORT TRANSMISSION MISSION command command has been exec if RECEIVE BUFFER STATUS full then els read RECEIVE BUFFER into CPU memory set command bit RELEASE RECEIVE BUFFER released if DATA OVERRUN overrun then els an application may u
19. P8xC592 about the receive interrupt service execution time and CPU load when serving the CAN controller To get results as reliable as possible all figures are calculated for worst case As shown in fig 8 both reception of messages and transmission of messages result in CPU load but the partial CPU load for transmission obviously is almost negligible Therefore the considerations in the next sections have been focussed on the reception of messages Reception of messages is normally initiated by interrupt The according interrupt service routine copies the Rx buffer contents to an internal CPU RAM location Its execution time should be as short as possible in order to achieve a low CPU load The CPU load for CAN communication is defined as the percentage of time the CPU is serving the CAN communication measured in a time interval of interest In case the time interval is shorter than the duration of a message transfer on the bus the Spare Time should be considered instead of the CPU load The Spare Time is defined as the amount of coherent CPU time the CPU may reserve for non CAN activities between the reception of consecutive messages The next section presents the software which meets the requirements for a fast execution of the receive interrupt service Receive Interrupt Service Routine Base of all the following calculations is a simple receive interrupt service routine for the P8xC592 table 11 see also Appendix A 1 The calculations of CPU
20. Philips Components 1990 P8xC592 target device specification Version 2 2 Philips Export B V 1991 Data sheet PCA 82C200 Stand alone CAN controller Philips Export B V 1990 12NC 9397 285 30011 Application of the PCA 82C200 CAN Controller PSCC Philips Export B V 1990 12NC 9398 373 50011 Bit Timing Parameters for CAN Networks Application Note KIE07 91ME Philips Components PCALH 1991 Road vehicles Serial data communication for automotive application Part 1 Controller Area Network CAN ISO DIS 11519 part 1 International Organization for Standardization 1992 Road vehicles Interchange of digital information Controller Area Network CAN for high speed communication ISO DIS 11898 International Organization for Standardization 1992 CAN bus failure management using the P8xC592 microcontroller Application Note HKI AN 91 020 Philips Semiconductors PCALH 1991 Single chip 8 bit microcontrollers PCB83C552 User Manual Philips Export B V 1988 12NC 9398 637 90011 CAN Physical Layer Concepts for the P8xC592 Microcontroller Application Note HKI AN 91 027 Philips Semiconductors PCALH 1991 Philips Semiconductors Application Note HKI AN 91 014 Taj Appendix A Reference software for investigation of the CPU load A 1 Receiver part This module is a program including a very fast versatile receive interrupt service routine which is able to handle up to 128 identifiers It runs on the P8xC592 Evaluation
21. RESET LJMP AIN_PROG CSEG AT 2BH LJMP CAN_INTERRUPT Philips Semiconductors Application Note HKI AN 91 014 39 MAIN SEGMENT CODE RSEG MAIN MAIN_PROG Initialization MOV SP 7FH set stackpointer CLR EA disable all interrupts SETB ES1 CAN Controller interrupt enabled OV DPTR 4000H OV A 0FFH OVX DPTR A LEDs dark OV ARRAY_LONG 0 delete RAM position OV ARRAY LONG 1 0 OV INT_SAVE 0 delete interrupt save register INIT_CAN OV CANADR CONTROL reset request OV CANDAT 00000001B OV A CANDAT JNB ACC 0 INIT_CAN repeat reset if reset request is absent OV CANADR FACCEPTANCE_MASK OV CANDAT 0FH OV CANADR ACCEPTANCE_CODE ID 0101 XXXX XXX OV CANDAT 05FH OV CANADR BUS_TIMING_0O OV CANDAT 80H OV CANADR BUS_TIMING_1 OV CANDAT 23H OV CANADR OUTPUT_CONTROL OV CANDAT FOFAH OV CANADR CONTROL OV A CANDAT ORL A INT_MASK enable receive interrupt ANL A 11111110B reset request bit 0 OV CANDAT A SETB EA 7 enable all interrupts LOOP JB CANSTA 1 OVERRUN SJMP LOOP OVERRUN OV A ARRAY_LONG OV DPTR 4100H OVX DPTR A first byte of message to green LED OV A ARRAY_LONG 1 OV DPTR 4200H OVX ADPTR A second byte of message to red LED SJMP S Philips Semiconductors Application Note HKI AN 91 01
22. SMIT BUFFER if lt using the ABORT TRANSMISSION command gt then 4 ls if TRANSMISSION COMPLETE STATUS complete last requested then ls 4 transmission has last requested last requested been completed transmission has transmission has not been completed been completed no ABORT TRANSMISS the ABORT ION command has TRANSMISSION command been executed was successful if RECEIVE INTERRUPT set then t els read RECEIVE BUFFER into CPU memory set command bit RELEASE RECEIVE BUFFER released if OVERRUN INTERRUPT set then els an application may use this information to change its behaviour e g faster reaction on a RECEIVE INTERRUPT set command bit CLEAR OVERRUN clear if ERROR INTERRUPT set then els if BUS STATUS on bus then ls P8xC592 takes part in bus P8xC592 does not take part in activities bus activities if ERROR STATUS ok if lt restart CAN required gt then ls then ls the CAN Bus the CAN Bus set control bit is presently is presently RESET REQUEST CAN hardware not severely severely absent is left in disturbed disturbed now the P8xC592 off bus and waits for 128 11 reset state consecutive recessive bits perform appli before going cation specif on bus again default mode operation Table 8 Flow chart of Interrupt Register data evaluation Philips Semiconductors Application Note
23. The result of this simulation is that the CPU spends only 3 4 of the time for CAN related procedures In this example 96 6 of the time is free for other CPU activities Philips Semiconductors Application Note HKT AN 91 014 20 Transmitting Repetition receiving node node DLC ID Time message ms 1 2 3 4 5 6 7 1 M1_1 4 10 2 x x x x 2 M21 7 11 2 x x x x x x 2 M22 2 30 100 x 31 M3_1 5 15 20 x x x x 31 M32 3 31 100 x 4i M4 1 5 32 20 x x x 4 M42 3 33 100 xX 5 M5_1 8 20 100 xX xX x x x 51 M52 8 34 100 X 6 M61 8 21 100 xX xX xX x 6 M62 8 35 100 x 7 MII 8 36 100 x x Table 10 Communication Matrix of the network example ID Identifier DLC data length code CPU Load Ml y 96 6 96 Copy Reject Receive Transmit Other Fig 8 CPU load Average of nodes 1 7 Philips Semiconductors Application Note HKI AN 91 014 ooh tee 4 6 Calculation of the CPU Load for CAN Communication In chapter 4 5 a practical example was presented for which the CPU load for CAN communication had been investigated The figures were obtained for a real set up using 7 nodes In this chapter the details of such a CPU load calculation are presented The following calculations and diagrams give hints and ideas to the user of the
24. ation Board Software The software for the P8xC592 evaluation board is stored in the on board EPROM The software is designed to assist users with different experience in CAN based networks o A user with little experience is able to activate the demonstration software A menu driven software monitor allows the contents of the P87C592 s CAN registers to be altered and thereby enables the user to gain experience For the latter an RS232 terminal e g VT100 is required o A user with more experience will use the download facility this allows the user to load new software on to the P8xC592 evaluation board Download requires a PC with terminal emulating software The P8xC592 evaluation board is also ready to be used as a bus monitor receiving messages from the bus for display on a terminal 52 In Circuit Emulators For the software development on the P8xC592 several in circuit emulators ICE are available 5 2 1 Philips Stand alone Debug System SDS Philips well known and well accepted stand alone debug station SDS for the real time development of 8 bit uCs is already prepared for future probes gt 16MHz Three configurations are possible o stand alone operation together with a terminal o connected to a terminal plus a host computer download upload o connected to a PC AT IBM or compatible with terminal emulation software Philips Semiconductors Application Note HKI AN 91 014 29 Features of the SDS o
25. cation is controlled partly in the interrupt service routine and partly in the main program care has to be taken about the use of CANADR CANDAT indirect addressing of the CAN Registers or CANADR CANSTA use of DMA respectively If they are used as well in main program level as in interrupt level it might be necessary to save the address of CANADR push pop during interrupt processing or disable the CAN interrupt during DMA transfer at main level respectively For the latter if required the interrupt has to be disabled right before the RAM address is written into CANSTA and can be re enabled just after the start of the DMA transfer Philips Semiconductors Application Note HKT AN 91 014 oe li 2 read INTERRUPT REGISTER and store in the bitaddressable part of the CPU memory if WAKE UP INTERRUPT set then ls if lt CPU state gt just being awoken then ls the network was awoken by some the just issued GOTO SLEEP CAN Bus activity command was not successful Perform appropriate network Perform appropriate action wake up activities if TRANSMIT INTERRUPT set then ls the TRANSMIT BUFFER is released A next message may be written into the TRAN
26. ce eee eee eee ee 30 6 References o lake pied ss BAe ee a 31 Appendix A Example program for investigation of CPU load 0 0 cee eee ee 32 A l Receiver part s os vs atk ga el haat ea ie oie iaa eel oe 32 A 2 Lransmitter parteetan ea als A Sea hank Sues 35 Philips Semiconductors Application Note HKT AN 91 014 1 Introduction CAN Controller Area Network is an advanced serial communication protocol which efficiently supports distributed real time control with a very high safety level CAN allows the flexible configuration of networks with different types of microprocessors and microcontrollers Typical applications of CAN ba sed networks can be found in automotive and industrial environment o Automotive Systems multiplex wiring lt 125kbit s engine control ABS etc up to 1 Mbit s o Industrial Systems field bus applications robotics numeric machine control Fig 1 shows a schematic network using the P8xC592 for distributed control applications The kernel of each module is a Module Controller CPU that communicates via the Bus Controller i e CAN controller with the other modules CPU and CAN controller can also be implemented on the very same chip as it is in the P8xC592 Module 1 APPLICATION INTERFACE APPLICATION INTERFACE Module n APPLICATION INTERFACE MODULE CONTROLLER P8xC552 BUS CONTROLLER PCA
27. ch are used during communication now appear as being directly addressable as they are represented by these four special function registers The Status Register represented by CANSTA now is even bit addressable With the help of these registers and the DMA logic data transfer between Transmit Receive Buffers and internal main RAM is also done very effectively see fig 6 Philips Semiconductors Application Note HKT AN 91 014 CAN Registers Access Modes of the CPU address dec hex CONTROL SEGMENT 0 CONTROL l E 1 COMMAND write CANCON 2 STATUS read CANSTA Direct access 3 INTERRUPT read_ cancon With SFR 4 ACCEPTANCE CODE 5 ACCEPTANCE MASK 6 BUS TIMING 0 7 BUS TIMING 1 8 OUTPUT CONTROL l 9 TEST do not use read write Access with TRANSMIT BUFFER te AND ASADA 10 A identifier 10 3 ii B identif 2 0 rtr bit dic 12 data byte 1 write 19 13 data byte 8 RECEIVE BUFFER 0 1 Access 20 14 identifier 10 3 MIDA 2 15 identif 2 0 rtr bit dic 22 16 data byte 1 read E 29 1D data byte 8 3 Fig 5 CAN register mapping SFRs CAN control CANADR address R CAN Registers segment CAN DAT transmit buffer CAN CON receive CANSTA gt internal RAM CPU bus address DMA control Main RAM DMA Logic
28. e on chip oscillator a reset circuit to provide the power on RESET and a transceiver circuit see section 3 2 for the connection to the bus wires AV pp VDD IC1 REF 55 REF 54 A CAN_H RXI 56 53 RXO 57 52 CAN_L TRANSCEIVER TXT 57 51 TXO 23 50 49 21 1P1 5 48 T 20 E 47 digital I O AV ss 19 36 or 18 37 address data bus 17 38 16 39 40 digital 14 41 vO 13 42 12 43 11 10 44 9 45 8 46 5V 7 62 32 63 31 analogue SE a or igital digital 66 28 digital I O input 67 27 68 26 I 7 25 Reset Circuit 5V I 3 Prim 4 Loa sv 22 VDD SIMD PWM output C3 CAN Bus Line 18R 59 47uF C4 ais RsTL15 100nF 61 60 6 i D1 1N4148 1 5V a XTAL1 of E c XTAL2 Q1 33pF 100nF CI 830592 c2 PLCC 68 33pF BU108081 DWG Fig 3 P87C592 P83C592 circuitry for a CAN application Philips Semiconductors Application Note HKI AN 91 014 Power Supply The 5V power supply is split on the different power input pins of the uC The main supply for the digital part of the CPU is fed to the Vpp Vss pins buffered by capacitor CS It is recommended that the supply AVpp AVss for the analogue parts is derived from the main supply by the filter R2 C4 The AVpp AVss supply is used to drive the on chip A D converter and the receiver section of the CAN controller it shall also be used for optional biasing of the RXO RX1 pins in the off chip transceiver The pin CVss is the ground pin belonging to the CAN on chip transmitter
29. eatures such as multi master serial communication capability with a high number of participating network nodes programmable data transmission rate up to 1 Mbit s and powerful error handling This technical publication puts special emphasis on CAN applications of the P8xC592 The application note provides a simple circuit example for a CAN module built with a P8xC592 Furthermore flowcharts are discussed to let the reader become familiar with the software aspects of CAN communication A practical example shows that there is very little CPU load for the control of CAN communication Revision history 91 10 16 Ist release 92 07 02 2nd release pages 6 11 31 34 revised Philips Semiconductors Application Note HKI AN 91 014 Table of Contents 1 Introduction A A le atari sar due 2 Ze P8xC592 Features iio IA aa eee 3 3 Hardware Aspects cgi and oe Yeeeah ecient easier 5 3 1 Main Circuitry a cyan E eh Aoi seg ae 5 3 2 Transceiver Physical Interface to the Transmission Medium 6 3 2 1 On chip Transceiver Components 0 0 0 c cece cee eee 7 4 Software Aspects ni hee eae See aj 8 4 1 CAN Registers rinane e y ea EO A lie on neat ei ees 8 4 2 On chip Interface Between CPU and CAN Controller 00000 8 4 2 1 CAN Related Special Function Registers 0 00 00 e ee eee eee ee 10 4 2 2 Auto Address Increment 0 eee eee eee eee ences 11 4 23 High Speed DMA cc asee e
30. ed by relating the Receive Buffer Release time of table 12 39 cycles to the transmission time of a 0 byte message plus the first byte of a next message 58 bits time 16MHz CPU ps 250 200 150 100 50 00 02 04 06 08 10 p bit rate HA110171 Mbit s Fig 13 Worst case spare time Philips Semiconductors Application Note HKI AN 91 014 27 Se Development Tools For the P8xC592 several powerful support tools can be supplied to assist during the design and test phase These tools are o the P8xC592 Evaluation Board o P8xC592 In Circuit Emulators o P87C592 EPROM programmers o debug tools for CAN communication NetSim NetAna NetEmu 5 1 Philips P8xC592 Evaluation Board The P8xC592 evaluation board OM4239 is a most versatile aid consisting of a ready to use hardware and software module very similar to a real CAN bus node The P8xC592 evaluation board can be used in a car since it has its own 5V supply An RS232 interface allows the P8xC592 evaluation board to be connected to a terminal or to a PC with terminal emulating software
31. er can be realized with more or less effort the cheapest solution consists only of a couple of resistors more expensive ones need some more discrete components or an extra IC In principle the very same transceiver circuits can be used as for the stand alone CAN controller PCA 82C200 3 Three examples for cheap discrete transceivers have been described in the Application Note 4 for the PCA 82C200 for instance In order to get to an international standard for CAN communication including the transceiver the International Standardization Organization ISO has prepared two standards one for lower bit rates up to 125 kbit s 6 one for higher ones 7 They also define the electrical parameters for the transceiver Application hints for implementation of an ISO compatible transceiver circuit are given in 10 Philips Semiconductors Application Note HKT AN 91 014 3 2 1 On chip Transceiver Components The off chip transceiver circuit connects the bus wires to the on chip transceiver components The on chip transceiver provides the transmitter output stage and the receiver input comparator see fig 4 Transmitter The transmitter provides two output lines CTX0 CTX1 their characteristics can be programmed individually with the OUTPUT CONTROL register Each line can work as open drain or open source or push pull output with positive or negative polarity Thus the transmitter is well prepared to drive any kind of differential bus
32. he application examples given in this document the reader should be familiar with the Philips P8xC592 data sheet 2 2 P8xC592 Features Fig 2 shows the block diagram of the P83C592 ROM or the P87C592 EPROM versions There is also a ROM less version labeled P80C592 without on chip program memory Except the three blocks CAN controller DMA and 256 Bytes Aux RAM the blocks shown are not different from those which are present in other 80C51 derivatives like in the well known Philips P8xC552 The use of the CPU the memory access modes the timers A D converter and PWM outputs have already been described in detail in the User Manual for the P8xC552 9 which shall not be repeated in this application note again Please refer to that document for information about these topics Vpp Reset 8 Bit PWM PWM TX 2 CAN 10 Bit ADC Port 0 Controller RX CPU 80C51 Capt Comp 256 Bytes Timer Counter Aux RAM 256 Bytes Main RAM Watchdog Port 5 bu110151 Vss Fig 2 Block diagram of the P8xC592 Philips Semiconductors Application Note HKI AN 91 014 The CAN controller on the P8xC592 is mainly an on chip implementation of the Philips Stand alone CAN controller PCA 82C200 3 The access to the internal CAN registers now is given via 4 Special Function Registers SFR The transfer of the messages between the CAN
33. his buffer by setting the Release Receive Buffer command bit This may result in another message becoming immediately available read message from RECEIVE BUFFER set command bit RELEASE RECEIVE BUFFER released Table 5 Flow chart of a reception procedure 4 3 4 Sleep Mode If the Sleep Bit of the Command Register is set high the CAN controller enters the Sleep Mode requiring that there is no bus activity and no interrupt is pending A network enters the Sleep Mode when all its nodes enter the Sleep Mode The CAN Controller wakes up after setting the Sleep bit of the Command Register low or when there is any bus activity Upon wake up a wake up interrupt is generated It is not necessary to enable the wake up interrupt After the CAN Controller entered Sleep Mode the CPU may be set into the Power Down Mode oscillator stopped Upon wake up the oscillator is started again The wake up interrupt will wake up a CPU from Power Down Mode by generating a Reset pulse if the SIO1 CAN interrupt source was enabled A CAN Controller that wakes up because of bus activity is not able to receive this message until it detects a bus free signal Reading of the Sleep bit reflects the status of the CAN Controller ae Set command bit SLEEP sleep out pa ct a Table 6 Flow chart of a go to sleep procedure Philips Semiconductors Application No
34. lines The connections of the transmitter outputs to the bus wires have to be done in such a way that the resulting level on the bus is O recessive level when all nodes transmit a logical 1 or do not transmit o dominant level when one or more nodes transmit a logical 0 P8xC592 OUTPUT CONTROL REGISTE COMMAND REGISTER CONTROL REGISTER TXD COMP OUT y y AVDD 2 OUTPUT CONTROL LOGIC bu107302 gem nd 5V 5V to the CAN bus line Fig 4 Structure of the on chip CAN transceiver Philips Semiconductors Application Note HKI AN 91 014 Receiver The on chip receiver is a differential input comparator with the input lines CRXO and CRX1 It decodes o the recessive level to a logical 1 when the voltage at the CRX0 pin is higher than at the CRX1 pin o the dominant level to a logical O when the voltage at the CRX0 pin is lower than at the CRX 1 pin Instead of decoding the differential bus signal the comparator inputs can also be switched by software to decode the signal of only one of the two bus lines comparing it to the reference voltage at the REF pin The reference voltage can either be provided by the internal on chip voltage generator default or if desired it is fed to the REF pin by an external source with the internal source being switched off by software The
35. mA 5 mA Philips Semiconductors 1991 10 16 ij Philips Semiconductors Application Note HKI AN 91 014
36. ns control bits to select auto increment addressing and to start a DMA transfer CANDAT When reading or writing CANDAT access to the CAN registers addressed by CANADR is possible The way of accessing CAN registers via CANADR CANDAT normally is only necessary for the registers Acceptance Code Acceptance Mask Bus Timing O Bus Timing 1 Output Control which the CPU has to access during initialization only CANCON CANCON is a register with different meaning for write and read operation Writing to CANCON is a direct access to the command register and reading from it is a direct access to the interrupt register CANSTA The bit addressable register allows a direct read access to the Status Register of the CAN Controller Writing to CANSTA sets the address of the on chip main RAM for a subsequent DMA transfer Philips Semiconductors Application Note HKT AN 91 014 Ts 4 2 2 Auto Address Increment Fast reading and writing of consecutive CAN Controller internal registers is possible by setting the AutoInc bit of CANADR and the concerning register address simultaneously A first access to CANDAT refers to the register specified in CANADR After any read or write access to CANDAT the contents of CANADR are incremented automatically in this mode Incrementing CANADR beyond XX111111B resets the AutoInc bit automatically to XX000000B 4 2 3 High Speed DMA The DMA logic provides a very fast transfer of complete messages between
37. output stages cf chapter 3 2 1 which shall also be used for optional ground potential of the off chip transceiver Program Fetch The schematics of fig 3 present the circuitry for microcontrollers with on chip program memory ROM or EPROM Therefore the pin EA is connected to 5V for program being fetched from internal memory Note that the EA pin is only read by the CPU during RESET that means switching it during program execution is not possible This can give an additional protection against unauthorized copying of the on chip program Reset Circuit The schematics of fig 3 present a proposal for a discrete circuit that provides the necessary RESET signal to the CPU during power up The Reset Circuit can be replaced by a connection of the RST pin to the power on power fail reset output of the power supply if available Note that internal RESET conditions of the CPU e g watchdog or recover from power down may cause the output of a short pulse on the RST pin which the Reset Circuit has to tolerate 3 2 Transceiver Physical Interface to the Transmission Medium The transceiver circuit performs the following functions o it converts signals TXO TX1 into the voltage levels for the bus wires o it converts the voltage levels on the bus wires to be compatible with the CRX0 CRX1 inputs of the P8xC592 How this connection actually is implemented is application specific Depending on the requirements for the bus signals the transceiv
38. phisticated development and debug tools for CAN communication can be supplied These are offered and supported by Gesellschaft fiir Informatik und Mikro Elektronik Prof Dr Ing W Lawrenz mbH Ferdinandstr 15 A 3340 Wolfenbiittel Germany NetSim NetSim Network Simulator is a software simulator for use with a Personal Computer The CAN network is described using NetSim on the PC by o number of network nodes o data transmission rate o message identifiers message length message transmission repetition rate o noise The simulation is then started NetSim provides information for various parameters such as o message delays o bus load NetSim assists during the design phase to investigate these parameters NetAna NetAna Network Analyzer is a combined hardware software tool operating in conjunction with a PC NetAna has two basic functions o to monitor the bus traffic and store the data on the hard disk in the PC for subsequent analysis o an event is triggered identifier bus error etc and the messages around the trigger point are recorded NetAna assists to trace communication failures in an existing CAN network NetEmu NetEmu Network Emulator enables the user to transmit defined messages into an operational CAN network The resultant network response can then be analyzed by NetAna Philips Semiconductors Application Note HKI AN 91 014 31 References CAN Specification Version 1 2
39. pplication Note HKI AN 91 014 29 Macro Name Machine Copy Reject Rx Buff Cycles Release Max Interrupt 5 xX x x Response Time Long Jump to 2 x X X Interrupt Service Routine Context Switch 6 x x x Clear Int Bits 1 X X x Calculate Target Address 15 x x x Copy rx buffer 8 x x Acknowledge 2 X xX X Restore Context 6 x X Sum of cycles 45 37 39 Table 12 Summary of receive interrupt execution times machine cycles Fig 10 shows that due to the DMA function of the P8xC592 the receive interrupt execution time is always independent of the length of the received message It is very important that the receive interrupt execution time is much shorter than the time the message itself spends on the bus This clearly shows that a data overrun caused by a burst of messages can be excluded Message 250kbit s 250 P time we 7 e Message us 50 ye ee 500kbit s AO we ee Bee er 150 LE e A ar a oe ct Message 100 tree A eee 1Mbit s par E e a poe _ _ _ 50 A es J L oe 0 gt e e e COPY e oe e e e o REJECT 0 HA110152 0 1 2 3 4 5 6 Data Length Code Fig 10 Receive interrupt execution time copy and reject and message transfer time Message for 16MHz CPU as a function of Data Length Code Philips Semiconductors Application Note HKI AN 91 014 PAs 4 6 1 CPU Load Three parame
40. re automatically CAN_INTERRUPT context switch save Accu amp PSW select register bank clear interrupt bits read Interrupt Register calculate table address fetch target address from table if target address 0 then copy Rx Buffer to int uC RAM starting at target address release Receive Buffer Acknowledge restore context Table 11 Flowchart of the Receive Interrupt Service Routine Receive Interrupt Execution Time Table 12 shows the interrupt execution time for the used receive interrupt service routine The routine is split up into different macros for each of them the according processing time has been calculated The receive interrupt execution time is shorter when a message has to be rejected Therefore two columns are shown the particular processing time for the copy and the reject case Another column shows the time passing until the Receive Buffer is released for evaluation of the CPU Spare Time see chapter 4 6 2 Times are given in units of machine cycles and one cycle consists of 12 oscillator periods The used oscillator frequency of the P8xC592 is 16 MHz resulting in a cycle time of 0 75us Fig 10 shows the receive interrupt execution time copy and reject as a function of the message data length code DLC For purpose of comparison also the message transfer time on the bus is given for the data rates 250kbit s 500kbit s and 1Mbit s Philips Semiconductors A
41. receive transmit buffers and internal data memory Main RAM within 2 instruction cycles The transfer process operates in the background and therefore the CPU can continue with the next instruction However an access to the Main RAM or to the CAN special function registers is not allowed during this time A DMA transfer action is achieved by first writing the RAM address into CANSTA and then writing the Tx or Rx Buffer address and the DMA bit simultaneously into CANADR The DMA automatically recognizes the transfer direction see table 2 For the Rx Buffer DMA there is the option to copy a whole message or only a part of it CANADR subject to transfer transfer direction 8AH whole message RAM gt Tx Buffer 94H whole message Rx Buffer gt RAM 95H whole message without first byte 96H data bytes only 97H last data bytes 9DH only the last data byte data bytes are copied as far as they are available DLC Table 2 DMA Modes Setting the DMA bit causes an automatic evaluation of the data length and subsequent transfer For a Tx Buffer DMA transfer the data length is always expected at RAM address 1 After the DMA transfer has been finished the DMA bit and the Autolnc bit are reset Philips Semiconductors Application Note HKT AN 91 014 pie 4 3 Basic Functions for CAN Communication 4 3 1 Initialization During Initialization the P8xC592 s CAN Controller is configured according
42. s ohn eek ta does bie eat 11 4 3 Basic Functions for CAN Communication 0 0 00 0 eee ee eee 12 E initialization piss ale wae east ea tah eee Seah ee at ie eda Beta 12 43 20 TRANSMISSIONS 6 shear aba wae eae ana de eats A en eas eae 12 4 3 3 RECEptlOn st sates aco eae es a Siew yates an 14 EIA Sleep Mode tene iat one ee the ede ee bea ee eee ad 14 4 3 5 Comparator Switches 0 cee eee eens 15 4 4 Control of CAN Communication 0 0 cece eee eee 16 AR Interrupts tt a diets ahi eat 16 A A ine Ses dag eaten ois deli ee ea bee get eh 8 Bea aot Sa 18 4 5 CPU Load for CAN a Real Example 0 0 00 o 19 4 6 Calculation of the CPU Load for CAN Communication 21 40 1 CRU Sieads isis hugs A io a 24 4 60 22 Spare VimMer aes 2 8 etd te dt ae id ee ie eh ne A Meee ae ead 25 5 Development Tools on aE EE cence eee eae 27 5 1 Philips P8xC592 Evaluation Board 0 0 cee eee ee 27 5 1 1 P8xC592 Evaluation Board Hardware 0 0 eee eee ee 28 5 1 2 P8xC592 Evaluation Board Software 0 0 eee eee eee 28 5 2 In Circuit Emulators 2 0 0 0 eee ccc cece eee ae 28 5 2 1 Philips Stand alone Debug System SDS 0 0 000000000 eee 28 3 2 2 ICE from Other Vendors uri See ee a a ees 29 5 3 Programming Support for P87C592 EPROM 0 0 0 0 2 eee ee 29 5 4 Debug Tools for CAN communication 00 00 ce
43. se t his information to change its behaviour e g faster reaction on a RECEIVE INTERRUPT set command bit CLEAR OVERRUN clear if BUS STATUS on bus then ls P8xC592 takes part in bus P8xC592 does not take part in bus activities activities x if ERROR STATUS ok if lt restart CAN hardware required gt then ls then ls the CAN bus is the CAN bus is set control bit RESET perform presently presently REQUEST absent application not severely severely specific disturbed disturbed now the P8xC592 default mode xJ waits for 128 11 operation some application specific actions consecutive recessive bits before going may be necessary on bus again Table 9 Flow chart of Status Register data evaluation polling Philips Semiconductors Application Note HKI AN 91 014 19 4 5 CPU Load for CAN a Real Example In a CAN system data transfer can be done with a very high level of safety with the CAN controller part of the P8xC592 The CPU has only the task of post processing the received data and pre processing the data to be transmitted Communication between CPU and CAN controller is easily done via the Special Function Registers described in chapter 4 2 1 Using the DMA transfer facility data exchange between CPU and Rx Tx buffer is very effective That means that the resulting CPU
44. t until Transmit Buffer access OV CANADR DMA_TX_BUFFER Transmit Buffer 10H OP set DMA bit OP OV CANCON 00000001B transmission request SJMP BEGIN_TX END Philips Semiconductors Application Note HKI AN 91 014 Specification Differences for the P87C592 V1 Control Register REF pin The bit Reference Active bit 5 of the Control Register is not provided in the P87C592 V 1 This means it is not necessary to set the input function of pin REF see Initialization procedure chapter 4 3 1 In the case that the REF pin pin 55 shall be used in the application for tolerating physical bus errors opens and shorts of the bus wires a simple external circuit has to be connected to it Application example for a 2 5V reference voltage Components IC1 LM285Z 2 5 40 C LM385BZ 2 5 0 C LM385Z 2 5 0 C R1 High Speed Transceiver Low Speed Transceiver Cl High Speed Transceiver Low Speed Transceiver Characteristics Precise voltage regulation Low current consumption P87C592 V1 AV 5 REF AM MR z lt R1 IC1 lo Ie 85 C 1 5 70 C 1 5 70 C 3 1kQ IR 2 5 mA typ 16kQ IR 160 uA typ 0 InF 3 4 LM285Z over 2 6 LM385BZ temperature 2 5 mA resp 160 WA Supply voltage range 45Vto5 5V Load capacity lo High speed circuit Low speed circuit source 1 9 mA 70 uA sink 5
45. te HKT AN 91 014 15 4 3 5 Comparator Switches Data communication between the nodes of a network is disturbed or stopped when the bus wires are short circuited global failures or interrupted local failures With the P8xC592 precautions have been taken to continue data communication despite of a bus failure With the help of the comparator switches implemented in the CAN Controller it is possible to tolerate the following single wiring failures o one of the bus lines is short circuited with VBAT or GND o one bus line is short circuited against the other o interruption of one of the bus lines The structure of the on chip CAN Transceiver in fig 4 shows that in case of a short circuit it is possible to disconnect a blocked bus wire from the CAN receivers of all network nodes and replace this faulty bus line potential by a local reference level at one of the comparator inputs In some cases it might be necessary to disconnect the bias voltage of one bus wire from the power supply terminal additionally to continue with communication Bus line interruptions are solved similar to the short circuit failures by replacing the potential of one bus line with a local reference potential The positions of the switches are defined via the Command Register bits RXOA and RX1A see table 7 Reading of RXOA RX1A reflects the status of the switches RX0A RXIA Result 0 0 unchanged 0 1 IN REF IN CRXI 1 0 IN CRXO IN REF 1 1 IN
46. terrupt which is always enabled Setting of the interrupt sources is usually done during initialization see also table 4 Do not forget to enable the CPU s SIO1 interrupt by ES1 bit and the global interrupt by EA bit Upon the occurrence of one or more enabled interrupts the according bits are setin the Interrupt Register and a CAN interrupt SIO1 for the CPU is performed After reading this register that appears to the CPU as a read only memory all bits are reset by the CAN Controller Therefore the Interrupt Register should be stored in a bitaddressable part of the CPU memory for later interrupt evaluation Table 8 shows the procedure for an Interrupt Register data evaluation In this example it is assumed that all interrupt sources are enabled to present a complete description The following summary gives a short overview of the CAN related interrupts and their occurrences Receive Interrupt If a new message is available in the Receive Buffer the Receive Interrupt is given Transmit Interrupt A Transmit Interrupt is signalled when a transmission has been completed or aborted Error Interrupt If the Bus Status or the Error Status changes an Error Interrupt is given Overrun Interrupt When both Receive Buffers contain a message and the first byte of the next message should be stored the Overrun Interrupt is signalled Wake up Interrupt Whenever the Sleep Mode is left a Wake up Interrupt is signalled When CAN communi
47. ters are important for the calculation of the CPU load while receiving messages The used receive interrupt execution time see tables 11 12 the bit rate and the bus load The bus load is the percentage of time the bus is occupied active by transferring messages Therefore it has to be calculated how many messages are transferred in a time interval and how long a message transfer is on the bus The latter is the message length number of bits multiplied by the time of one bit The message length depends on the data length code For the following calculations a data length code estimation has to be made bus load bus active time number of messages message length bit time time interval time interval In order to get a direct relation between CPU Load bit rate and bus load from the formula for the bus load the formula for the number of messages is derived which can be inserted into the definition of the CPU load bus load time interval message length bit time number of messages number of messages receive interrupt execution time CPU load AE time interval bus load time interval receive interrupt execution time CPU Load er oes message length bit time time interval With the definition of bit rate 1 bit time we get receive interrupt execution time message length CPU load bus load bit rate bus load bit rate T The result is that the CPU load is proportional to the bus load
48. that amount of time that is the difference between message transfer time and the receive interrupt execution time The actual time that a CAN receive interrupt service may be delayed without risk of loosing a message data overrun is even longer In fig 12 the execution of the receive interrupt service routine has been delayed so that the routine is not yet finished when the next message comes in but the Release Receive Buffer command comes just in time before the first byte of the next message is to be stored in the Receive Buffer No message is lost but of course that long delay must be compensated by faster response for subsequent reception Philips Semiconductors Application Note HKT AN 91 014 a message n message n 1 message n 2 DLC DLC 0 DLC gt RX Buffer 0 gt RX Buffer 1 gt RX Buffer 0 its SOF bits 3 44 3 7 Identifier bits 3 gt delay receive interrupt execution time here receive interrupt latest possibility for the for messagen becomes active release receive buffer command for RX buffer 0 time for reception of message n 3 44 3 8 bit times 58 bit times no stuff bits HA110161 Fig 12 Delay of receive interrupt service The worst case is when a message is followed by a 0 byte message plus another message of any DLC The resulting allowed spare time worst case is shown in fig 13 for different bit rates Ithas been calculat
49. xt transmission is delayed until TRANSMIT BUFFER ACCESS released is signalled by a TRANSMIT INTERRUPT or by polling the STATUS REGISTER Table 3 Flow chart of a transmission procedure Philips Semiconductors Application Note HKI AN 91 014 s134 start initialization write CONTROL REGISTER set RESET_REQUEST present set TEST_MODE disabled write acceptance filter write ACCEPTANCE CODE REGISTER write ACCEPTANCE MASK REGISTER example contents of ACCEPTANCE CODE REGISTER 01110010B contents of ACCEPTANCE MASK REGISTER 00111000B allows for messages with following IDs 01xxx010xxxB define bus timing baud rate on the CAN Bus write BUS TIMING 0 REGISTER write BUS TIMING 1 REGISTER example contents of BUS TIMING 0 REGISTER 10001001B contents of BUS TIMING 1 REGISTER 11101011B results in ESCE 9 1 2 tosc with fosc 16 MHz 1 25 us tSJW 2 1 ESCL 3 75 us SAM 1 three samples bit taken ESYNC 1 x ESCL 1 25 us CTSEG2 6 1 ESCL 8 75 us CTSEG1 11 1 tscL 15 00 us CBIT tSyNCSEG tTSEG1 tTSEG2 20 tscL 25 00 us variation of bit time due to resynchronization
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