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MPC853T Hardware Specification

1. Name Pin Number Type PD5 R14 Bidirectional MII TXD3 5V tolerant PD4 P14 Bidirectional MII TXD2 5V tolerant PD3 M12 Bidirectional 1 5V tolerant TMS F15 nput 5V tolerant TDI G14 Input DSDI 5V tolerant TCK H13 Input DSCK 5V tolerant TRST F16 nput 5V tolerant TDO F14 Output DSDO 5V tolerant MI 9 B6 nput 016 Bidirectional 5V tolerant MI T14 Output 5V tolerant GOL F2 Input Vsssyn N4 PLL analog GND VsssYN1 P3 PLL analog GND VDDSYN P2 PLL analog VDD GND G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 Power J10 J11 K6 K7 K8 K9 K10 K11 VDDL A7 C1 D16 G15 L4 M2 R1 M15 T8 Power VDDH F5 F6 F7 F8 F9 F10 F11 F12 G5 G12 H5 H12 J5 J12 Power K5 K12 L5 L6 L7 L8 L9 L10 L11 L12 N C A1 A16 B16 C15 D14 E12 L13 M4 P15 R16 T1 T16 No connect 15 1 2 The Non JEDEC Pinout Figure 68 shows the non JEDEC pinout of the PBGA package as viewed from the top surface For additional information see the MPC866 PowerQUICC Family User s Manual MPC853T Hardware Specification Rev 1 74 Freescale Semiconductor Mechanical Data and Ordering Information NOTE This is the top vievv of the device 51 CS7 AZ VVE2 BS AO VDDL gt D gt a z
2. OO 020 4 T e OR 80 DO 02020 2 D gt o 5 gt i l gt a E E o E P pe a o gt o 2 o x g a E E a E 2 T o x N N s N o E E a N w E bo KO E N wo EDO OG TMS 2 o o N C o PD10 0 EO 8 FO 8 Q TOR 9 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 68 Pinout of the PBGA Package non JEDEC Table 32 contains a list of the MPC853T input and output signals and shows multiplexing and pin assignments Table 32 Pin Assignments Non JEDEC Name Pin Number Type A 0 31 C16 B16 B15 D15 E14 F12 C15 B14 D14 C14 E13 F11 D13 Bidirectional C13 B13 E12 F10 D12 B10 B12 E11 D11 C9 B11 E10 D10 Three state 3 3 V only D9 C12 B9 C11 C10 E9 TSIZO EO Bidirectional REG Three state 3 3 V only TSIZ1 F8 Bidirectional Three state 3 3 V only RD WR C2 Bidirectional Three state 3 3 V only MPC853T Hardware Specification Rev 1 Freescale Semiconductor 75 Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type BURST
3. CD3 Input CD3 SYNC Input Figure 51 SCC NMSI Receive Timing Diagram TCLK3 TxD3 Output RTS3 Output CTS3 Input CTS3 SYNC Input Figure 52 SCC NMSI Transmit Timing Diagram MPC853T Hardware Specification Rev 1 56 Freescale Semiconductor Echo Input TCLK3 RTS3 Output CTS3 Figure 53 HDLC Bus Timing Diagram 13 7 Ethernet Electrical Specifications Table 23 provides the Ethernet timings as shown in Figure 54 to Figure 58 Table 23 Ethernet Timing CPM Electrical Characteristics All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 ns 121 RCLK3 rise fall time 15 ns 122 RCLK3 width low 40 ns 123 RCLK3 clock period 1 80 120 ns 124 RXD3 setup time 20 ns 125 RXD3 hold time 5 ns 126 RENA active delay from RCLKS rising edge of the last data bit 10 ns 127 RENA vidth lovv 100 ns 128 TCLKS rise fall time 15 ns 129 TCLK3 width low 40 ns 130 TCLK3 clock period 99 101 ns 131 TXD3 active delay from TCLK3 rising edge 50 ns 132 TXD3 inactive delay from TCLK3 rising edge 6 5 50 ns 133 TENA active delay from TCLK3 rising edge 10 50 ns MPC853T Hardware Specification Rev 1 Freescale Semiconductor 57 CPM Electrical Characteristics Table 23 Ethernet Timing continu
4. MPC853T Hardware Specification Rev 1 78 Freescale Semiconductor Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type PA10 J16 Bidirectional TXD3 Optional open drain L1RXDB 5 V tolerant PA9 K17 Bidirectional RXD4 Optional open drain 5 V tolerant PA8 K16 Bidirectional TXD4 Optional open drain 5 V tolerant PA3 L17 Bidirectional CLK5 5 V tolerant BRGO3 TIN3 PA2 L15 Bidirectional CLK6 5 V tolerant TOUT3 L1RCLKB PA1 M16 Bidirectional CLK7 5 V tolerant BRGO4 TIN4 PAO N17 Bidirectional CLK8 5 V tolerant TOUT4 L1TCLKB PB31 F14 Bidirectional SPISEL Optional open drain 5 V tolerant PB30 G14 Bidirectional SPICLK Optional open drain 5 V tolerant PB29 E16 Bidirectional SPIMOSI Optional open drain 5 V tolerant PB28 H14 Bidirectional SPIMISO Optional open drain BRGO4 5 V tolerant PB25 J15 Bidirectional SMTXD1 Optional open drain 5 V tolerant MPC853T Hardware Specification Rev 1 Freescale Semiconductor 79 Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type PB24 J17 Bidirectional SMRXD1 Optional open drain 5 V tolerant PB15 M17 Bidirectional BRGO3 5 V tolerant PC15 D17 Bidirectional DRE
5. B20 D 0 31 DP 0 3 valid to CLKOUT falling 4 00 4 00 400 400 ns edge setup time 7 MIN 0 00 x B1 4 00 B21 CLKOUT falling edge to D 0 31 2 00 200 200 200 ns DP 0 3 valid hold Time 7 MIN 0 00 x B1 2 00 B22 CLKOUT rising edge to CS asserted 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns GPCM ACS 00 MAX 0 25 x B1 6 3 B22a CLKOUT falling edge to CS asserted 8 00 8 00 8 00 8 00 ns GPCM ACS 10 TRLX 0 MAX 0 00 x B1 8 00 B22b CLKOUT falling edge to CS asserted 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns GPCM ACS 11 0 0 MAX 0 25 x B1 6 3 B22c CLKOUT falling edge to CS asserted 10 90 18 00 10 90 16 00 7 00 14 10 5 20 12 30 ns GPCM ACS 11 TRLX 0 1 MAX 0 375 x B1 6 6 B23 CLKOUT rising edge to CS negated 2 00 8 00 2 00 8 00 2 00 8 00 2 00 8 00 ns GPCM read access GPCM write access ACS 00 TRLX 0 amp CSNT 0 MAX 0 00 x B1 8 00 B24 A 0 31 and BADDR 28 30 to CS 5 60 4 30 3 00 1 80 ns asserted GPCM ACS 10 TRLX 0 MIN 0 25 x B1 2 00 B24a A 0 31 and BADDR 28 30 to CS 13 20 110 501 8 00 5 60 ns asserted GPCM ACS 11 TRLX MIN 0 50 x B1 2 00 B25 CLKOUT rising edge to OE 9 00 9 00 9 00 9 00
6. SMTXD1 Optional Open drain 5V tolerant PB24 H16 Bidirectional SMRXD1 Optional Open drain 5V tolerant PB15 L16 Bidirectional BRGO3 5V tolerant PC15 C16 Bidirectional DREQO 5V tolerant PC13 E14 Bidirectional RTS3 5V tolerant LiRQB LISTO MPC853T Hardware Specification Rev 1 72 Freescale Semiconductor Table 31 Pin Assignments JEDEC Standard continued Name Pin Number Type 12 15 Bidirectional RTS4 5V tolerant L1ST4 PC7 J14 Bidirectional LITSYNCB 5V tolerant CTS3 PC6 K15 Bidirectional LIRSYNCB 5V tolerant CD3 PC5 J13 Bidirectional CTS4 5V tolerant SDACK1 PC4 L14 Bidirectional CD4 5V tolerant PD15 M14 Bidirectional MII RXD3 5V tolerant PD14 N16 Bidirectional MII RXD2 5V tolerant PD13 K13 Bidirectional MII RXD1 5V tolerant PD12 N15 Bidirectional MII MDC 5V tolerant PD11 P16 Bidirectional RXD3 5V tolerant MII TXERR PD10 R15 Bidirectional TXD3 5V tolerant MII RXDO PD9 N14 Bidirectional RXD4 5V tolerant MII TXDO PD8 M13 Bidirectional TXD4 5V tolerant MI EO GUK PD7 T15 Bidirectional RTS3 5V tolerant MIL RX ER PD6 N13 Bidirectional RTS4 5V tolerant MIL EO DV MPC853T Hardware Specification Rev 1 Mechanical Data and Ordering Information Freescale Semiconductor 73 Mechanical Data and Ordering Information Table 31 Pin Assignments JEDEC Standard continued
7. no direct relation with the total system interrupt latency that the MPC853T is able to support Figure 23 provides the interrupt detection timing for the external level sensitive lines CLKOUT Figure 23 Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge sensitive lines CLKOUT 2 ee E ET Figure 24 Interrupt Detection Timing for External Edge Sensitive Lines MPC853T Hardware Specification Rev 1 34 Freescale Semiconductor Table 11 shows the PCMCIA timing for the MPC853T Table 11 PCMCIA Timing Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max J82 A 0 31 REG valid to PCMCIA strobe 20 70 116 701 13 00 9 40 ns asserted MIN 0 75 x B1 2 00 J83 A 0 31 REG valid to ALE negation 28 30 123 00 1 18 00 13 20 ns MIN 1 00 x B1 2 00 J84 CLKOUT to REG valid 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns MAX 0 25 x B1 8 00 J85 CLKOUT to REG invalid 8 60 7 30 6 00 4 80 ns MIN 0 25 x B1 1 00 J86 CLKOUT to CE1 CE2 asserted 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns MAX 0 25 x B1 8 00 J87 CLKOUT to CE1 CE2 negated 7 60 15 60 6 30
8. 0 1 CSNT 1 EBDF 1 MAX 0 375 x B1 6 6 10 90 18 00 10 90 18 00 7 00 14 30 5 20 12 30 ns B28d CLKOUT falling edge to CS negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MAX 0 375 x B1 6 6 18 00 18 00 14 30 12 30 ns B29 WE 0 3 BS_B 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access CSNT 0 EBDF 0 MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns B29a WE 0 3 BS_B 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX CSNT 1 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 8 00 5 60 ns B29b CS negated to D 0 31 DP 0 3 High Z GPCM write access ACS 00 TRLX 0 1 amp CSNT 0 MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns MPC853T Hardware Specification Rev 1 Freescale Semiconductor 17 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max 29 CS negated to D 0 31 DP 0 3 High Z 13 20 10 50 8 00 5 60 ns GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 B29d WE 0 3 BS_B 0 3 negated to D 0 31 43 50 135 501 28 00 20 701 ns DP 0 3 High Z GPCM write access TRLX 1 CSN
9. 14 30 5 00 13 00 3 80 11 80 ns MAX 0 25 x B1 8 00 CLKOUT to PCOE IORD PCWE 111 001 111 01 11 00 11 00 ns J88 1OVVR assert time MAX 0 00 x B1 11 00 CLKOUT to PCOE IORD PCWE 2 00 11 00 1 2 00 11 00 1 2 00 11 00 2 00 11 00 ns J89 IOWR negate time MAX 0 00 x B1 11 00 J90 CLKOUT to ALE assert time 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns MAX 0 25 x B1 6 30 J91 CLKOUT to ALE negate time 15 60 14 30 13 00 11 80 ns MAX 0 25 x B1 8 00 J92 PCWE IOWR negated to D 0 31 5 60 4 30 3 00 1 80 ns invalid MIN 0 25 x B1 2 00 J93 WAITA and WAITB valid to CLKOUT 8 00 8 00 8 00 8 00 ns rising edge MIN 0 00 x B1 8 00 CLKOUT rising edge to WAITA and 2 00 2 00 2 00 2 00 ns J94 WAITB invalid MIN 0 00 x B1 2 00 T PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAITA signals are detected in order to freeze or relieve the PCMCIA current cycle The WAITA assertion will be effective only if it is detected two cycles before the PSL timer expiration See the Chapter 16 PCMCIA Interface in the MPC866 PowerQUICC Family User s Manual MPC853T Hardware Specification Rev 1 Freescale Semiconductor 35 Bus Signal Timing Figure 25 provides the PCMCIA acces
10. C11 A9 A11 D10 C10 B8 A10 D9 C9 C8 Three state 3 3V only B11 A8 B10 B9 D8 TSIZO E8 Bidirectional REG Three state 3 3V only TSIZ1 E7 Bidirectional Three state 3 3V only RD WR B1 Bidirectional Three state 3 3V only MPC853T Hardware Specification Rev 1 68 Freescale Semiconductor Table 31 Pin Assignments JEDEC Standard continued Name Pin Number Type BURST G3 Bidirectional Three state 3 3V only BDIP D1 Output GPL B5 TS E2 Bidirectional Active Pull up 3 3V only TA F4 Bidirectional Active Pull up 3 3V only TEA E3 Open drain B D2 Bidirectional Active Pull up 3 3V only IRQ2 G2 Bidirectional RSV Three state 3 3V only IRQ4 J1 Bidirectional KR Three state 3 3V only RETRY SPKROUT CR F1 Input 3 3V only IRQ3 D 0 31 R13 T11 R10 T10 T12 R9 R7 T6 T13 M10 N10 P10 P12 Bidirectional R12 M9 N9 P9 N11 T9 R8 P8 N8 T7 P11 P7 N7 M8 R11 R6 Three state 3 3V only P6 T5 R5 DPO P4 Bidirectional IRQ3 Three state 3 3V only DP1 P5 Bidirectional IRQ4 Three state 3 3V only DP2 T4 Bidirectional IRQ5 Three state 3 3V only DP3 R4 Bidirectional IRQ6 Three state 3 3V only BR E1 Bidirectional 3 3V only BG G4 Bidirectional 3 3V only BB F3 Bidirectional Active Pull up 3 3V only FRZ H4 Bidirectional 3 3V only IRQ6 IRQO P13 Input 3 3V only IRQ1 M11 Input 3 3V only M_TX
11. GE XK E GE XM S Figure 5 Synchronous Output Signals Timing Figure 6 provides the timing for the synchronous active pull up and open drain output signals CLKOUT H S Figure 6 Synchronous Active Pull Up Resistor and Open Drain Outputs Signals Timing MPC853T Hardware Specification Rev 1 Freescale Semiconductor 23 Bus Signal Timing Figure 7 provides the timing for the synchronous input signals o o 5 D UPM in the memory controller XX JUA B16b Figure 7 Synchronous Input Signals Timing Figure 8 provides normal case timing for input data It also applies to normal read accesses under the control of the CLKOUT A Aa ee a o D 0 31 DP 0 3 BB a 7 A MANOS Figure 8 Input Data Timing in Normal Case 24 MPC853T Hardware Specification Rev 1 Freescale Semiconductor Bus Signal Timing Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 1 in the UPM RAM vvords This is only the case vvhere data is latched on the falling edge of CLKOUT CLKOUT KE BO O A ae re D 0 31 DP 0 3 Figure 9 Input Data Timing When Controlled by the UPM in the Memory Controller and DLT3 1 Figure 10 through Figure 13 provide the timing for the external bus read controlled by various GPCM fact
12. SDACK Timing Diagram Peripheral Write Internally Generated TA MPC853T Hardware Specification Rev 1 46 Freescale Semiconductor CPM Electrical Characteristics CLKO Output TS Output RW Output TA Output SDACK Figure 43 SDACK Timing Diagram Peripheral Read Internally Generated TA 13 3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Figure 44 Table 18 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time 10 ns 51 BRGO duty cycle 40 60 52 BRGO cycle 40 ns BRGOX Figure 44 Baud Rate Generator Timing Diagram MPC853T Hardware Specification Rev 1 Freescale Semiconductor 47 CPM Electrical Characteristics 13 4 Timer AC Electrical Specifications Table 19 provides the general purpose timer timings as shovvn in Figure 45 Table 19 Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 ns 62 TIN TGATE low time 1 CLK 63 TIN TGATE high time 2 CLK 64 TIN TGATE cycle time 3 CLK 65 1CLKO low to TOUT valid 3 25 ns CLKO TIN TGATE Input TOUT Output Figure 45 CPM General Purpose Timers Timing Diagram 13 5 Serial Interface AC Electrical Specifi
13. SYNCCLK 2 83 LTRCLKB L1TCLKB width low DSC 1 EA IO ns 83a LTRCLKB L1TCLKB width high DSC 1 EA IO ns 84 L1CLKB edge to L1CLKOB valid DSC 1 30 00 ns 85 LTRQB valid before falling edge of L TSYNCB 1 00 L1TC LK 86 L1GRB setup time 42 00 ns 87 L1GRB hold time 42 00 ns 88 L1CLKB edge to L1SYNCB valid FSD 00 CNT 0000 BYT 0 00 ns DSC 0 1 The ratio SyncCLK L1RCLKB must be greater than 2 5 1 2 These specs are valid for IDL mode only 3 Where P 1 CLKOUT Thus for a 25 MHz CLKOT rate P 40 ns 4 These strobes and TxD on the first bit of the frame become valid after L1CLKB edge or L1SYNCB whichever comes later MPC853T Hardware Specification Rev 1 Freescale Semiconductor 49 CPM Electrical Characteristics L RCLKB FE 0 CE 0 Input L1RCLKB FE 1 CE 1 Input LIRSYNCB Input lt XXX Q L1RXDB Input L1ST 2 1 Output Figure 46 SI Receive Timing Diagram with Normal Clocking DSC 0 MPC853T Hardware Specification Rev 1 50 Freescale Semiconductor CPM Electrical Characteristics 5 L1RCLKB FE 1 CE 1 Input L1RCLKB FE 0 CE 0 Input LIRSYNCB Input L1RXDB Input L1ST 2 1 Output L1CLKOB Output Figure 47 SI Receive Timing with Double Speed Clocking DSC 1 MPC853T Hardware Specification Rev 1 Freescale Sem
14. ns 5 10 31 asserted MAX 0 00 x B1 9 00 MPC853T Hardware Specification Rev 1 16 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B26 CLKOUT rising edge to OE negated MAX 0 00 x B1 9 00 2 00 9 00 2 00 9 00 2 00 9 00 2 00 9 00 ns B27 A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 10 TRLX 1 MIN 1 25 x B1 2 00 35 90 29 30 23 00 16 90 ns B27a A 0 31 and BADDR 28 30 to CS asserted GPCM ACS 11 TRLX 1 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B28 CLKOUT rising edge to WE 0 3 BS_B 0 3 negated GPCM write access CSNT 0 MAX 0 00 x B1 9 00 9 00 9 00 9 00 9 00 ns B28a CLKOUT falling edge to WE 0 3 BS_B 0 3 negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns B28b CLKOUT falling edge to CS negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF MAX 0 25 x B1 6 80 14 30 13 00 11 80 10 50 ns B28c CLKOUT falling edge to WE 0 3 BS_B 0 3 negated GPCM write access TRLX 0 1 CSNT 1 write access TRLX
15. 1 ns Bic Frequeney jitter on EXTCLK 1 0 50 0 50 0 50 0 50 EO Bid CLKOUT phase jitter peak to peak 4 4 4 4 ns for OSCLK x 15 MHz CLKOUT phase jitter peak to peak 5 5 5 5 ns for OSCLK lt 15 MHz B2 1CLKOUT pulse width low 12 1 18 2 10 0 15 0 8 0 12 0 6 1 9 1 ns MIN 0 4 x B1 MAX 0 6 x B1 B3 CLKOUT pulse width high 12 1 18 2 10 0 15 0 8 0 12 0 6 1 9 1 ns MIN 0 4 x B1 MAX 0 6 x B1 B4 1 CLKOUT rise time 4 00 4 00 4 00 4 00 ns B5 CLKOUT fall time 4 00 4 00 4 00 4 00 ns B7 to A 0 31 BADDR 28 30 7 60 6 30 5 00 3 80 ns RD WR BURST D 0 31 DP 0 3 output hold MIN 0 25 x B1 B7a CLKOUT to TSIZ 0 1 REG RSV BDIP 7 60 6 30 5 00 3 80 ns PTR output hold MIN 0 25 x B1 MPC853T Hardware Specification Rev 1 14 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B7b CLKOUT to BR BG FRZ VFLS 0 1 VF 0 2 IWP 0 2 LWP 0 1 STS output hold MIN 0 25 x B1 7 60 6 30 5 00 3 80 ns B8 CLKOUT to A 0 31 BADDR 28 30 RD WR BURST D 0 31 DP 0 3 valid MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns
16. 31 R W BURST CSx Figure 20 Synchronous External Master Access Timing GPCM Handled ACS 00 Figure 21 provides the timing for the asynchronous external master memory access controlled by the GPCM AS A 0 31 TSIZ 0 1 R W CSx Figure 21 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 22 provides the timing for the asynchronous external master control signals negation AS CSx WE 0 3 OE GPLx BS 0 3 Figure 22 Asynchronous External Master Control Signals Negation Timing MPC853T Hardware Specification Rev 1 Freescale Semiconductor 33 Bus Signal Timing Table 10 provides interrupt timing for the MPC853T Table 10 Interrupt Timing All Frequencies Num Characteristic Unit Min Max 139 IROx valid to CLKOUT rising edge setup time 6 00 ns 140 hold time after CLKOUT 2 00 ns 141 IRQx pulse width low 3 00 ns 142 IRQx pulse width high 3 00 ns 143 IRQx edge to edge time 4 x TCLOCKOUT 1 The 139 and 140 timings describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allovv the correct function of the IRQ lines detection circuitry and have
17. 7 0 mA Txd1 pa14 txd2 pa12 IOL 8 9 mA TS TA TEA B BB HRESET SRESET 1 The PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TCK TRST TMS MII_TXEN and MII_MDIO are 5 V tolerant pins Input capacitance is periodically sampled A 0 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 IRQ 3 6 RD VVR BURST RSV IRQ2 IWP 0 1 VFLS 0 1 RXD3 PA11 TXD3 PA10 RXD4 PA9 TXD4 PA8 TIN3 BRGO3 CLK5 PA3 BRGCLK2 TOUT3 CLK6 PA2 TIN4 BRGO4 CLK7 PA1 TOUT4 CLK8 PAO SPISEL PB31 SPICLK PB30 SPIMOSI PB29 BRGO4 SPIMISO PB28 SMTXD1 PB25 SMRXD1 PB24 BRGO3 PB15 RTS1 DREQO PC15 RTS3 PC13 RTS4 PC12 CTS3 PC7 CD3 PC6 CTS4 SDACK1 PC5 CD4 PC4 MII RXD3 PD15 2 14 MII RXD1 PD13 12 MII TXERR RXD3 PD11 MII RX0 TXD3 PD10 MII TXD0 RXD4 PD9 MII RXCLK TXD4 PD8 MII TXD3 PD5 MII RXDV RTS4 PD6 MII RXERR RTS3 PD7 MII TXD2 REJECT3 PD4 MIl TXD1 REJECT4 PD3 MII_CRS MII_MDIO MII_TXEN GOL BDIP GPL_B 5 BR BG FRZ IRQ6 CS 0 5 CS 6 CS 7 WE0 BS_BO IORD WE1 BS_B1 IOWR D wo iN WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A 0 3 GPL_A0 GPL_BO OF GPL_A1 GPL_B1 GPL_A 2 3 GPL_B 2 3 CS 2 3 UPWAITA GPL_A4 GPL_A5 ALE_A CE1_A CE2_A DSCK OP 0 1 OP2 MODCKT STS OP3 MODCK2 DSDO BADDR 28 30 7 Thermal Calculation and Measurement For the following discussions Pp Vppz x Ipp Pyo where Pyo
18. MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns B31b CLKOUT rising edge to CS valid as requested by control bit CST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns B31c CLKOUT rising edge to CS valid as requested by control bit CST3 in the corresponding vvord in the UPM MAX 0 25 x B1 6 30 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns B31d CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 6 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns B32 CLKOUT falling edge to BS valid as requested by control bit BST4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns B32a CLKOUT falling edge to BS valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 0 MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns B32b CLKOUT rising edge to BS valid as requested by control bit BST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns MPC853T Hardware Specification Rev
19. O windows e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions 4 lt gt Each watchpoint can generate a break point internally e Normal high and normal low power modes to conserve power 1 8 V core and 3 3 V I O operation with 5 V TTL compatibility Refer to Table 5 for a listing of the 5 V tolerant pins MPC853T Hardware Specification Rev 1 4 Freescale Semiconductor Features Embedded MPC8xx Processor Core Fast Ethernet Controller 10 100 BaseT edia Access Control Instruction 4 Kbyte System Interface Unit SIU Memory Controller Internal External Interface Bus Interface Unit Unit Bus Instruction Cache Instruction MMU ebe 32 Entry ITLB Load Store 4 Kbyte Bus Data Cache System Functions Data MMU 32 Entry DTLB Parallel O 2 Interrupt Timers Controllers Dual Port RAM PCMCIA ATA Interface 1 Virtual IDMA 2 Baud Rate G 32 Bit RISC Controller and Program ROM enerators Timers amp 8 Serial DMA Channels Time Slot Assigner Serial Interface NMSI v v Figure 1 MPC853T Block Diagram MPC853T Hardware Specification Rev 1 Freescale Semiconductor Maximum Tolerated Ratings 3 Maximum Tolerated Ratings Thi
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21. and DSCK sample MIN 8 00 x B1 MPC853T Hardware Specification Rev 1 40 Freescale Semiconductor Bus Signal Timing Figure 32 shows the reset timing for the data bus configuration HRESET A RSTCONF Figure 32 Reset Timing Configuration from Data Bus Figure 33 provides the reset timing for the data bus vveak drive during configuration HRESET RSTCONF D 0 31 OUT Weak d Figure 33 Reset Timing Data Bus VVeak Drive During Configuration MPC853T Hardware Specification Rev 1 Freescale Semiconductor 41 IEEE 1149 1 Electrical Specifications Figure 34 provides the reset timing for the debug port configuration SRESET SS R80 R80 7 DSCK DSDI Figure 34 Reset Timing Debug Port Configuration 12 IEEE 1149 1 Electrical Specifications Table 15 provides the JTAG timings for the MPC853T shown in Figure 35 to Figure 38 Table 15 JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100 00 ns J83 clock pulse width measured at 1 5 V 40 00 ns J84 1 TCK rise and fall times 0 00 10 00 ns J85 TMS TDI data setup time 5 00 ns J86 TMS TD data hold time 25 00 ns 487 1 TCK low to TDO data valid 27 00 ns 488 1 TCK low to TDO data invalid 0 00 ns J89 TCK low to TDO high impedance 20 00
22. herein are subject to change without notice Freescale Semiconductor Inc 2004 All rights reserved POS ON du Ze b E Ge Ge e EE Gi erre SS RS b b ES Contents He a a ls 1 Features EO ETE Eta 2 Maximum Tolerated Ratings 6 Thermal Characteristics 7 Power Dissipation 7 DC Characteristics 8 Thermal Calculation and Measurement 9 Power Supply and Power Sequencing 11 Mandatory Reset Configurations 12 Layout Practices argk artek gik R OEEk et geie 13 Bus Signal Timing 13 IEEE 1149 1 Electrical Specifications 42 CPM Electrical Characteristics 44 FEC Electrical Characteristics 63 Mechanical Data and Ordering Information 67 References sn tii dices garkia gt aan din 84 Document Revision History 84 ey oe ZT freescale semiconductor Features and incorporates memory management units MMUs instruction and data caches The MPC853T is a subset of this family of devices and is the main focus of this document 2 Features The MPC853T is comprised of three modules that each use the 32 bit internal bus a MPC8xx core a system integration unit SIU and a communications processor module CPM The MPC853T block diagram is sho
23. the printed circuit board per JEDEC JESD51 8 Board temperature is 5 measured on the top surface of the board near the package Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the cold plate temperature used for the case temperature For exposed pad packages where the pad would be expected to be soldered junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51 2 Power Dissipation Table 4 provides power dissipation information The modes are 1 1 where CPU and bus speeds are equal and 2 1 mode where CPU frequency is twice bus speed MPC853T Hardware Specification Rev 1 Freescale Semiconductor 7 DC Characteristics Table 4 Povver Dissipation Pp Die Revision Bus Mode Frequency MHz Typical 1 Maximum Unit 50 110 140 mW b 66 150 180 mW 0 66 140 160 mW 2 1 80 170 200 mW 100 210 250 mW Typical povver dissipation is measured at 1 9 V 2 Maximum power dissipation at Vppu and Vppsyn is at 1 9 V and Vppu is at 3 465 V NOTE Values in Table 4 represent Vpp based power dissipation and do not include I O power dissipation over Vppu I O power dissipation varies widely b
24. 00 B30b WE 0 3 BS_B 0 3 negated to A 0 31 43 50 135 501 28 00 20 701 ns Invalid GPCM BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 MPC853T Hardware Specification Rev 1 18 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B30c WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 MIN 0 375 x B1 3 00 8 40 6 40 4 50 2 70 ns B30d WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or 11 EBDF 1 38 67 31 38 24 50 17 83 ns B31 CLKOUT falling edge to CS valid as requested by control bit CST4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns B31a CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding vvord in the UPM
25. 1 Freescale Semiconductor 19 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B32c CLKOUT rising edge to BS valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit BST3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B32d CLKOUT falling edge to BS valid as 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns requested by control bit BST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 60 B33 CLKOUT falling edge to GPL valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns requested by control bit GxT4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 B33a CLKOUT rising edge to GPL valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit GxT3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B34 A 0 31 BADDR 28 30 and D 0 31 to 5 60 4 30 3 00 1 80 ns CS valid as requested by control bit CST4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 B34a A 0 31 BADDR 28 30 and D 0 31 to 13 20 10 50 8 00 5 60 ns CS valid as requested by control bit CST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 B34b A 0 31 BADDR 28 30 and
26. 1 Freescale Semiconductor 59 CPM Electrical Characteristics 13 8 SPI Master AC Electrical Specifications Table 24 provides the SPI master timings as shovvn in Figure 59 and Figure 60 Table 24 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 toye 161 MASTER clock SCK high or low time 2 512 jas 162 MASTER data setup time inputs 15 ns 163 Master data hold time inputs 0 ns 164 Master data valid after SCK edge 10 ns 165 Master data hold time outputs 0 ns 166 1 Rise time output 15 ns 167 Fall time output 15 ns SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 59 SPI Master CP 0 Timing Diagram MPC853T Hardware Specification Rev 1 60 Freescale Semiconductor SPICLK 1 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output CPM Electrical Characteristics Figure 60 SPI Master CP 1 Timing Diagram 13 9 SPI Slave AC Electrical Specifications Table 25 provides the SPI slave timings as shown in Figure 61 and Figure 62 Table 25 SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 teyc 171 Slave enable lead time 15 ns 172_ Slave enable lag time 15 ns 17
27. 14 CLKOUT to TEA assertion MAX 0 00 x B1 9 00 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns B15 CLKOUT to TEA High Z MIN 0 00 x B1 2 50 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns B16 TA B valid to CLKOUT setup time MIN 0 00 x B1 6 00 6 00 6 00 6 00 6 00 ns B16a TEA KR RETRY CR valid to CLKOUT setup time MIN 0 00 x B1 4 5 4 50 4 50 4 50 4 50 ns B16b BB BG BR valid to CLKOUT setup time 9 4MIN 0 00 x B1 0 00 4 00 4 00 4 00 4 00 ns MPC853T Hardware Specification Rev 1 Freescale Semiconductor 15 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B17 CLKOUT to TA TEA B BB BG BR 1 00 1 00 100 200 ns valid hold time MIN 0 00 x B1 1 00 4 B17a CLKOUT to KR RETRY CR valid hold 2 00 2 00 200 200 ns time MIN 0 00 x B1 2 00 B18 1 D 0 31 DP 0 3 valid to CLKOUT rising 6 00 6 00 6 00 6 00 ns edge setup time 5 MIN 0 00 x B1 6 00 B19 CLKOUT rising edge to D 0 31 DP 0 3 1 00 1 00 1 00 200 ns valid hold time 5 MIN 0 00 x B1 1 00
28. 25 A 35 D 19 7 53 Hd D 19 3 D D D D E Zz 1 i 1 0 2 TOP VIEVV d 19 05 D 15X 1 27E 1 D 0 635 i tb 64 b e ND T 2 O n R SOS D BEK N EHD 15X 1 27 4 M 0 7 L 56 mul 19 05 LJ 0 62 H 14 Ka 1 22 17111 0 50 G Loo 0 635 1 12 F DO 2 54 E 4 212 Tm D DOO 8 i 2545678910 112 14 5 5 256X 08 2 SIDE VIEW 0 3 A B C BOTTOM VIEW O 15 IA NOTES 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 3 MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A 4 DATUM A THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS Note Solder sphere composition is 95 5 Sn 45 Ag 0 5 Cu for MPC853TVRXXX Solder sphere composition is 62 Sn 36 Pb 2 Ag for MPC853TZTXXX Figure 69 Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC853T Hardware Specification Rev 1 Freescale Semiconductor 83 References 16 References Semiconductor Equipment and Materials International 415 964 5111 805 East Middlefield Rd Mountain View CA 94043 MIL SPEC and ETA IESD JEDEC specifications 800 854 7179 or Available from Global Engineering Documents 303 397 7956 JEDEC Specifications http www jedec org 1 C E Triplett and B Joiner An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module Proceed
29. 3 Slave clock SPICLK high or low time 1 teye 174 Slave sequential transfer delay does not require deselect 1 teye 175 Slave data setup time inputs 20 ns 176 Slave data hold time inputs 20 ns 177 Slave access time 50 ns MPC853T Hardware Specification Rev 1 Freescale Semiconductor 61 CPM Electrical Characteristics SPISEL J Input 4 SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 61 SPI Slave CP 0 Timing Diagram MPC853T Hardware Specification Rev 1 62 Freescale Semiconductor FEC Electrical Characteristics SPISEL Input SPICLK 1 0 Input SPICLK Cl 1 Input Gb SPIMISO Output SPIMOSI Input Figure 62 SPI Slave CP 1 Timing Diagram 14 FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller FEC Note that the timing specifications for the MII signals are independent of system clock frequency part speed designation Also MII signals use TTL signal levels compatible with devices operating at either 5 0 V or 3 3 V 14 1 MII Receive Signal Timing MII_RXD 3 0 MII RX DV MII RX ER MII RX CLK The receiver functions correctly up to a MIT RX CLK maximum frequency of 25MHz 1 There is no minimum frequency requirement In ad
30. 7 Input 3 3V only IP_A7 R2 Input 3 3V only DSCK H2 Bidirectional Three state 3 3V only IWP 0 1 H3 G1 Bidirectional 3 3V only VFLS 0 1 OPO K1 Bidirectional 3 3V only OP1 K2 Output OP2 K3 Bidirectional 3 3V only MODCK1 STS OP3 L1 Bidirectional 3 3V only MODCK2 DSDO BADDR 28 29 L3 L2 Output BADDR30 J3 Output REG AS J2 Input 3 3V only PA11 E16 Bidirectional RXD3 Optional Open drain L1TXDB 5V tolerant PA10 H15 Bidirectional TXD3 5V tolerant L1RXDB PAQ J16 Bidirectional RXD4 Optional Open drain 5V tolerant PA8 J15 Bidirectional TXD4 5V tolerant MPC853T Hardware Specification Rev 1 Mechanical Data and Ordering Information Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 31 Pin Assignments JEDEC Standard continued Name Pin Number Type PA3 K16 Bidirectional CLK5 5V tolerant BRGO3 TIN3 PA2 K14 Bidirectional CLK6 5V tolerant TOUT3 LTRCLKB PA1 L15 Bidirectional CLK7 5V tolerant BRGO4 TIN4 PAO M16 Bidirectional CLK8 5V tolerant TOUT4 LTTCLKB PB31 E13 Bidirectional SPISEL Optional Open drain 5V tolerant PB30 F13 Bidirectional SPICLK Optional Open drain 5V tolerant PB29 D15 Bidirectional SPIMOSI Optional Open drain 5V tolerant PB28 G13 Bidirectional SPIMISO Optional Open drain BRGO4 5V tolerant PB25 H14 Bidirectional
31. B8a CLKOUT to TSIZ 0 1 REG RSV BDIP PTR valid MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns B8b CLKOUT to BR BG VFLS 0 1 VF 0 2 IWP 0 2 FRZ LWP 0 1 STS valid 3 MAX 0 25 x B1 6 3 13 80 12 50 11 30 10 00 ns B9 CLKOUT to A 0 31 BADDR 28 30 RD WR BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV PTR High Z MAX 0 25 x B1 6 3 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns B11 CLKOUT to TS BB assertion MAX 0 25 x B1 6 0 7 60 13 60 6 30 12 30 5 00 11 00 3 80 9 80 ns Bila CLKOUT to TA BI assertion when driven by the memory controller or PCMCIA interface MAX 0 00 x B1 9 30 2 50 9 30 2 50 9 30 2 50 9 30 2 50 9 80 ns B12 CLKOUT to TS BB negation MAX 0 25 x B1 4 8 7 60 12 30 6 30 11 00 5 00 9 80 3 80 8 50 ns B12a CLKOUT to TA B negation vvhen driven by the memory controller or PCMCIA interface MAX 0 00 x B1 9 00 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns B13 CLKOUT to TS BB High Z MIN 0 25 x B1 7 60 21 60 6 30 20 30 5 00 19 00 3 80 14 00 ns B13a CLKOUT to TA BI High Z when driven by the memory controller or PCMCIA interface MIN 0 00 x B1 2 5 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns B
32. D 0 31 to 20 70 116 701 113001 9 40 ns CS valid as requested by CST2 in the corresponding word in UPM MIN 0 75 x B1 2 00 B35 A 0 31 BADDR 28 30 to CS valid as 5 60 4 30 3 00 1 80 ns requested by control bit BST4 in the corresponding vvord in the UPM MIN 0 25 x B1 2 00 B35a A 0 31 BADDR 28 30 and D 0 31 to 13 20 110 501 8 00 5 60 ns BS valid as requested by BST1 in the corresponding vvord in the UPM MIN 0 50 x B1 2 00 B35b A 0 31 BADDR 28 30 and D 0 31 to 20 70 116 701 113001 9 40 ns BS valid as requested by control bit BST2 in the corresponding vvord in the UPM MIN 0 75 x B1 2 00 B36 A 0 31 BADDR 28 30 and D 0 31 to 5 60 4 30 3 00 1 80 ns GPL valid as requested by control bit GxT4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 MPC853T Hardware Specification Rev 1 20 Freescale Semiconductor Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B37 UPWAIT valid to CLKOUT falling edge 6 00 6 00 6 00 6 00 ns MIN 0 00 x B1 6 00 B38 CLKOUT falling edge to UPWAIT valid 9 1 00 1 00 1 00 1 00 ns MIN 0 00 x B1 1 00 B39 AS v
33. FEC Electrical Characteristics Table 29 MII Serial Management Channel Timing continued Num Characteristic Min Max Unit M13 MII_MDIO input to MI MDC rising edge hold 0 ns M14 MII_MDC pulse width high 40 60 MII_MDC period M15 MII_MDC pulse width low 40 60 MI MDC period Figure 66 shows the MII serial management channel timing diagram MII_MDC output M14 TY MM15 M10 MII_MDIO output MII_MDIO input x 12 13 Figure 66 MII Serial Management Channel Timing Diagram MPC853T Hardware Specification Rev 1 66 Freescale Semiconductor Table 30 identifies the packages and operating frequencies orderable for the MPC853T Mechanical Data and Ordering Information 15 Mechanical Data and Ordering Information Table 30 MPC853T Package Frequency Orderable Order Number Plastic ball grid array CVR suffix Package Type Temperature Tj Frequency MHz Plastic ball grid array 0 C to 95 C 50 MPC853TVR50 VR and ZT suffix MPC853TZT50 66 MPC853TVR66 MPC853TZT66 80 MPC853TVR80 MPC853TZT80 100 MPC853TVR100 MPC853TZT 100 40 C to 100 C 66 TBD 15 1 Pin Assignments The following sections give the pinout and pin listing for the JEDEC Compliant and the non JEDEC versions of the 16 x 16 PBGA package 15 1 1 The JEDEC Compliant Pinout Figure 67 shows the JEDEC pinout of the PBGA
34. Freescale Semiconductor Advance information MPC853TEC Rev 1 12 2004 MPC853T Hardware Specification This hardware specification contains detailed information on the power considerations DC AC electrical characteristics and AC timing specifications of the MPC853T The MPC853T contains a PowerPC processor core This hardware specification describes pertinent electrical and physical characteristics of the MPC853T For the functional characteristics of the processor refer to the MPC866 PowerQUICC Family User s Manual MPC866UM 1 Overview The MPC853T PowerQUICC is a 0 18 micron derivative of the MPC860 PowerQUICC family It can operate at up to 100 MHz on the MPC8xx core with a 66 MHz external bus The MPC853T has a 1 8 V core and 3 3 V I O operation with 5 V TTL compatibility The MPC853T integrated communications controller is a versatile one chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications It particularly excels in Ethernet control applications including CPE equipment Ethernet routers and hubs VoIP clients and Wi Fi access points The MPC853T is a PowerPC architecture based derivative of Freescale s MPC860 quad integrated communications controller PowerQUICC The CPU on the MPC853T has a MPC8xx core a 32 bit microprocessor that implements the PowerPC architecture This document contains information on a new product Specifications and information
35. H4 Bidirectional Three state 3 3 V only BDIP E2 Output GPL B5 TS F3 Bidirectional Active pull up 3 3 V only TA G5 Bidirectional Active pull up 3 3 V only TEA F4 Open drain BI E3 Bidirectional Active pull up 3 3 V only IRQ2 H3 Bidirectional RSV Three state 3 3 V only IRQ4 K2 Bidirectional KR Three state 3 3 V only RETRY SPKROUT CR G2 Input 3 3 V only IRQ3 D 0 31 T14 U12 T11 U11 U13 T10 T8 U7 U14 N11 P11 R11 R13 Bidirectional T13 N10 P10 R10 P12 U10 T9 R9 P9 U8 R12 R8 P8 N9 Three state 3 3 V only T12 T7 R7 U6 T6 DPO R5 Bidirectional IRQ3 Three state 3 3 V only DP1 R6 Bidirectional IRQ4 Three state 3 3 V only DP2 U5 Bidirectional IRQ5 Three state 3 3 V only DP3 T5 Bidirectional IRQ6 Three state 3 3 V only BR F2 Bidirectional 3 3 V only BG H5 Bidirectional 3 3 V only BB G4 Bidirectional Active pull up 3 3 V only FRZ J5 Bidirectional 3 3 V only IRQ6 MPC853T Hardware Specification Rev 1 76 Freescale Semiconductor Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type IRQO R14 Input 3 3 V only IRQ1 N12 Input 3 3 V only IRQ7 P13 Input 3 3 V only M_TX_CLK CS 0 5 C3 B3 E4 D4 F7 D5 Output CS6 E5 Output CS7 B4 Output WEO E7 Output BS_BO IORD WE1 D7 Output BS_B1 IOWR WE2 B6 Output BS_B2 PC
36. MA SDMA channels Three parallel I O registers with open drain capability e Two baud rate generators Independent can be connected to any SCC3 4 or SMC1 Allow changes during operation Autobaud support option Two SCCs serial communication controllers Ethernet IEEE 802 3 optional on SCC3 amp SCC4 supporting full 10 Mbps operation HDLC SDLC HDLC bus implements an HDLC based local area network LAN Universal asynchronous receiver transmitter UART Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC e SMC serial management channels UART MPC853T Hardware Specification Rev 1 Freescale Semiconductor 3 Features e SPI serial peripheral interface Supports master and slave modes Supports multiple master operation on the same bus MPC853T has a time slot assigner TSA that supports one TDM bus TDMb Allows SCCs and SMC to run in multiplexed and or non multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined 1 8 bit resolution Allows independent transmit and receive routing frame synchronization and clocking Allows dynamic changes Can be internally connected to three serial channels two SCCs and one SMC e PCMCIA interface Master socket interface release 2 1 compliant Supports one independent PCMCIA socket 8 memory or I
37. OE WE3 Output BS B3 PCVVE BS ADG B7 E8 D8 C8 Output GPL_AO D6 Output GPL_BO OE E6 Output GEL AI GPL B1 GPL_A 2 3 B5 C5 Output GPL_B 2 3 CS 2 3 UPWAITA D3 Bidirectional 3 3 V only GPL_A4 GPL_A5 F5 Output PORESET R2 Input 3 3 V only RSTCONF L5 Input 3 3 V only HRESET K5 Open drain SRESET N4 Open drain XTAL P2 Analog output EXTAL N2 Analog Input 3 3 V only MPC853T Hardware Specification Rev 1 Freescale Semiconductor 77 Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type CLKOUT P7 Output EXTCLK P3 nput 3 3 V only AUE A J2 Output CE1_A F6 Output CE2_A C4 Output WAIT_A P4 Input 3 3 V only IP_AO U3 Input 3 3 V only IE A1 N7 Input 3 3 V only IP_A2 T4 Input 3 3 V only 101516 IE NO Input 3 3 V only IP_A4 U4 Input 3 3 V only IP_A5 P6 Input 3 3 V only IP_A6 N8 Input 3 3 V only IP_A7 T3 Input 3 3 V only DSCK J3 Bidirectional Three state 3 3 V only IWP 0 1 J4 H2 Bidirectional 3 3 V only VFLS 0 1 OPO L2 Bidirectional 3 3 V only OP1 L3 Output OP2 L4 Bidirectional 3 3 V only MODCK1 STS OP3 M2 Bidirectional 3 3 V only MODCK2 DSDO BADDR 28 291 M4 M3 Output BADDR30 K4 Output REG AS K3 Input 3 3 V only PA11 F17 Bidirectional RXD3 Optional open drain L1TXDB 5 V tolerant
38. PC853T Value Register Configuration Field binary HRCVV HRCW DBGC Obx1 Hardware reset configuration word SIUMCR SIUMCR DBGC Obx1 SIU module configuration register MBMR MBMR GPLB4DIS 0 Machine B mode register PAPAR PAPAR 4 7 0 Port A pin assignment register PAPAR 12 15 PADIR PADIR 4 7 1 Port A data direction register PADIR 12 15 PBPAR PBPARI141 0 Port B pin assignment register PBPAR 16 231 PBPAR 26 27 PBDIR PBDIR 14 1 Port B Data direction register PBDIR 16 23 PBDIR 26 27 MPC853T Hardware Specification Rev 1 Freescale Semiconductor Layout Practices Table 6 Mandatory Reset Configuration of MPC853T continued p Value Register Configuration Field binary PCPAR PCPAR 8 111 0 Port C pin assignment register PCDIR 14 PCDIR PCDIRI8 111 1 Port C data direction register PCDIR 14 10 Layout Practices Each Vpp pin on the MPC853T should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vpp power supply should be bypassed to ground using at least four 0 1 uF bypass capacitors located as close as possible to the four sides of the package Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required Capacitor
39. QO 5 V tolerant PC13 F15 Bidirectional RTS3 5 V tolerant L1RQB L1ST3 PC12 F16 Bidirectional RTS4 5 V tolerant L1ST4 PC7 K15 Bidirectional LTTSYNCB 5 V tolerant CTS3 PC6 L16 Bidirectional 11 5 5 V tolerant CD3 PC5 K14 Bidirectional CTS4 5 V tolerant SDACK1 PC4 M15 Bidirectional CD4 5 V tolerant PD15 N15 Bidirectional RXD3 5 V tolerant PD14 P17 Bidirectional RXD2 5 V tolerant PD13 L14 Bidirectional RXD1 5 V tolerant PD12 P16 Bidirectional 5 V tolerant PD11 R17 Bidirectional RXD3 5 V tolerant EE PD10 T16 Bidirectional TXD3 5 V tolerant MIl_RXDO MPC853T Hardware Specification Rev 1 80 Freescale Semiconductor Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type PD9 P15 Bidirectional RXD4 5 V tolerant MII_TXDO PD8 N14 Bidirectional TXD4 5 V tolerant MII_RX_CLK PD7 U16 Bidirectional RTS3 5 V tolerant MILRX ER PD6 P14 Bidirectional RTS4 5 V tolerant MIL EO DV PD5 T15 Bidirectional TXD3 5 V tolerant PD4 R15 Bidirectional TXD2 5 V tolerant PD3 N13 Bidirectional TXD1 5 V tolerant TMS G16 nput 5 V tolerant TDI H15 Input DSDI 5 V tolerant TCK J14 Input DSCK 5 V tolerant TRST G17 Input 5 V tolerant TDO G15 Output DSDO 5 V tolerant MI CRS C7 nput MII_MDIO H17 B
40. T 1 EBDF MIN 1 50 x B1 2 00 B29e CS negated to D 0 31 DP 0 3 High Z 43 50 1 135 501 128 001 20 70 ns GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 B29f WE 0 3 BS_B 0 3 negated to D 0 31 5 00 3 00 1 10 0 00 ns DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 EBDF 1 MIN 0 375 x B1 6 30 B29g CS negated to D 0 31 DP 0 3 High Z 5 00 3 00 1 10 0 00 ns GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN 0 375 x B1 6 30 B29h WE 0 3 BS_B 0 3 negated to D 0 31 38 40 131 101 124201 17 50 ns DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 EBDF 1 MIN 0 375 x B1 3 30 B29i CS negated to D 0 31 DP 0 3 High Z 38 40 131 101 124 201 17 50 ns GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN 0 375 x B1 3 30 B30 CS WE 0 3 BS_B 0 3 negated to 5 60 4301 300 1801 ns A 0 31 BADDR 28 30 invalid GPCM write access 5 MIN 0 25 x B1 2 00 B30a WE 0 3 BS_B 0 3 negated to A 0 31 13 20 10 50 8 00 5 60 ns BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF MIN 0 50 x B1 2
41. _CLK N12 Input 3 3V only IRQ7 MPC853T Hardware Specification Rev 1 Mechanical Data and Ordering Information Freescale Semiconductor 69 Mechanical Data and Ordering Information Table 31 Pin Assignments JEDEC Standard continued Name Pin Number Type 510 5 2 A2 D3 C3 E6 C4 Output CS6 D4 Output CS7 A3 Output WEO D6 Output BS_BO IORD VVE1 Output BS B1 IOWR WE2 A5 Output BS_B2 PCOE VVE3 B5 Output BS B3 PCVVE BS_A 0 3 A6 D7 C7 B7 Output GPL_AO C5 Output GPL EO OE D5 Output GPL_A1 GPL_B1 GPL_A 2 3 A4 DA Output GPL_B 2 3 CS 2 3 UPWAITA C2 Bidirectional 3 3V only GPL_A4 GPL EA Output PORESET P1 nput 3 3V only RSTCONF K4 Input 3 3V only HRESET J4 Open drain SRESET M3 Open drain XTAL N1 Analog Output EXTAL M1 Analog Input 1 8V only CLKOUT N6 Output EXTCLK N2 Input 1 8V only ALE_A H1 Output CE1_A E5 Output CE2_A B3 Output MPC853T Hardware Specification Rev 1 70 Freescale Semiconductor Table 31 Pin Assignments JEDEC Standard continued Name Pin Number Type WAIT_A N3 Input 3 3V only IP_AO T2 Input 3 3V only IP_A1 M6 Input 3 3V only IP_A2 R3 Input 3 3V only 101516 M5 Input 3 3V only IP_A4 T3 Input 3 3V only IP_A5 N5 Input 3 3V only IP_A6 M
42. alid to CLKOUT rising edge 7 00 7 00 7 00 7 00 ns MIN 0 00 x B1 7 00 B40 A 0 31 TSIZ 0 1 RD WR BURST 7 00 7 00 7 00 7 00 ns valid to CLKOUT rising edge MIN 0 00 x B1 7 00 B41 TS valid to CLKOUT rising edge setup 7 00 7 00 7 00 7 00 ns time MIN 0 00 x B1 7 00 B42 CLKOUT rising edge to TS valid hold 2 00 2 00 200 200 ns time MIN 0 00 x B1 2 00 B43 AS negation to memory controller TBD TBD m TBD TBD ns signals negation MAX TBD If the rate of change of the frequency of EXTAL is slow that is it does not jump between the minimum and maximum values in one cycle or the frequency of the jitter is fast that is it does not stay at an extreme value for a long time the maximum allowed jitter on EXTAL can be up to 2 For part speeds above 50 MHz use 9 80 ns for B11a The timing required for BR input is relevant when the MPC853T is selected to work with the internal bus arbiter The timing for BG input is relevant when the 85 is selected to work with the external bus arbiter For part speeds above 50 MHz use 2 ns for B17 5 The D 0 31 and DP 0 3 input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted For part speeds above 50 MHz use 2 ns for B19 7 The D 0 31 and DP 0 3 i
43. an be made For this method to work the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance namely a 2s2p board with a power and a ground plane and vias attaching the thermal balls to the ground plane 7 4 Estimation Using Simulation When the board temperature is not known a thermal simulation of the application is needed The simple two resistor model can be used with the thermal simulation of the application 2 or a more accurate and complex model of the package can be used in the thermal simulation MPC853T Hardware Specification Rev 1 10 Freescale Semiconductor Power Supply and Power Sequencing 7 5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available the thermal characterization parameter jr be used It determines the junction temperature with a measurement of the temperature at the top center of the package case using the following equation Ty Tr Yor x Pp where HE rz thermal characterization parameter Tr thermocouple temperature on top of package Pp power dissipation in package The thermal characterization parameter is measured per the JESD51 2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A
44. art Frequency 50 MHz 66 MHz Min Max Min Max Core Frequency 40 50 40 66 67 Bus Frequency 40 50 40 66 67 Table 8 shows the frequency ranges for standard part frequencies in 2 1 bus mode MPC853T Hardware Specification Rev 1 Freescale Semiconductor 13 Bus Signal Timing Table 8 Frequency Ranges for Standard Part Frequencies 2 1 Bus Mode Part Frequency 50 MHz 66 MHz 80 MHz 100 MHz Min Max Min Max Min Max Min Max Core Frequency 40 50 40 66 67 40 80 40 100 Bus Frequency 2 1 20 25 20 33 33 20 40 20 50 Table 9 provides the bus operation timing for the MPC853T at 33 40 50 and 66 MHz The timing for the MPC853T bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays CLKOUT assumes a 100 pF load maximum delay Table 9 Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 1 Bus period CLKOUT see Table 7 ns Bia EXTCLK to CLKOUT phase skew If 2 2 2 2 ns CLKOUT is an integer multiple of EXTCLK then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT For a non integer multiple of EXTCLK this synchronization is lost and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew B1b CLKOUT frequency jitter peak to peak 1 1 1
45. cations Table 20 provides the serial interface SI timings as shown in Figure 46 to Figure 50 Table 20 SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLKB L1TCLKB frequency DSC 0 SYNCCLK 2 MHz 5 71 L1RCLKB L1TCLKB width low DSC 0 P 10 ns 71a L1RCLKB L1TCLKB width high DSC 0 P 10 ns 72 L1TXDB L1ST1 and L1ST2 L1RQ L1CLKO rise fall time 15 00 ns 73 L1RSYNCB L1TSYNCB valid to L1CLKB edge SYNC setup time 20 00 ns 74 L1CLKB edge to L1RSYNCB L1TSYNCB invalid SYNC hold time 35 00 ns MPC853T Hardware Specification Rev 1 48 Freescale Semiconductor CPM Electrical Characteristics Table 20 SI Timing continued All Frequencies Num Characteristic Unit Min Max 75 LIRSYNCB L1TSYNCB rise fall time 15 00 ns 76 L1RXDB valid to L1CLKB edge L1RXDB setup time 17 00 ns 77 edge to L1RXDB invalid L1RXDB hold time 13 00 ns 78 L1CLKB edge to L1ST1 and L1ST2 valid 10 00 45 00 ns 78A 1L1SYNCB valid to L1ST1 and L1ST2 valid 10 00 45 00 ns 79 L1CLKB edge to L1ST1 and L1ST2 invalid 10 00 45 00 ns 80 L1CLKB edge to L1TXDB valid 10 00 55 00 ns 80A L1TSYNCB valid to L1TXDB valid 4 10 00 55 00 ns 81 L1CLKB edge to L1TXDB high impedance 0 00 42 00 ns 82 LTRCLKB L1TCLKB frequency DSC 1 16 00 or MHz
46. dition the processor clock frequency must exceed the RX CLK frequency 1 Table 26 provides information on the MII receive signal timing Table 26 MII Receive Signal Timing AAA MIL RXDI3 0 MI RX DV MIL EK ER to MIl_RX_CLK setup Sl yy GUK to MI RXD 3 0 MI EN DV M L ER hold HA m MII_RX_CLK pulse width high MII_RX_CLK period MII_RX_CLK pulse width low MIL EN 1 period MPC853T Hardware Specification Rev 1 Freescale Semiconductor 63 FEC Electrical Characteristics Figure 63 shows MII receive signal timing CLK input MI RXD 3 01 inputs MIl_RX_DV MI PK MO M1 M2 Figure 63 MII Receive Signal Timing Diagram CE 14 2 Mil Transmit Signal Timing MII TXDI3 01 MI TX EN Mil_TX_ER MII TX CLK The transmitter functions correctly up to a MIL TX CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MIT IK CLK frequency 1 Table 27 provides information on the MH transmit signal timing Table 27 MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MIL TX GUK to MII_TXD 3 0 TX EN MII_TX_ER invalid 5 ns M6 MIL TX CLK to 13 0 MIL TS EN MII_TX_ER valid 25 M7 MI TX CLK pulse width high 3596 65 MIl_TX_CLK period M8 MIL TX CLK pulse width low 35 65 MII_TX_CLK pe
47. ed All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay from TCLK3 rising edge 10 50 ns 135 RSTRT active delay from TCLK3 falling edge 10 50 ns 136 ESTETI inactive delay from TCLK3 falling edge 10 50 ns 137 REJECT width low 1 CLK 138 CLKO1 low to SDACK asserted 20 ns 139 CLKO1 low to SDACK negated 2 20 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater than or equal to 2 1 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory CLSN CTS1 Input Figure 54 Ethernet Collision Timing Diagram RCLK3 RxD3 Input RENA CD3 Input Figure 55 Ethernet Receive Timing Diagram MPC853T Hardware Specification Rev 1 58 Freescale Semiconductor CPM Electrical Characteristics TCLK3 TxD3 Output TENA RTS3 Input RENA CD3 Input NOTE 2 NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is negated before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 56 Ethernet Transmit Timing Diagram RxD3 Start Frame De gt RSTRT Output Figure 57 CAM Interface Receive Start Timing Diagram REJECT Figure 58 CAM Interface REJECT Timing Diagram MPC853T Hardware Specification Rev
48. es and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The PowerPC name is a trademark of IBM Corp and is used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 MPC853TEC Rev 1 12 2004 beia z freescale semiconductor
49. g edge 0 00 50 00 ns 104 RTS3 active inactive delay from TCLK3 falling edge 0 00 50 00 ns 105 CTS3 setup time to TCLK3 rising edge 5 00 ns 106 RXD3 setup time to RCLK rising edge 5 00 ns 107 RXD3 hold time from RCLK3 rising edge 2 5 00 ns 108 CD3 setup Time to RCLK3 rising edge 5 00 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as external sync signals Table 22 provides the NMSI internal clock timing Table 22 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK3 frequency 1 0 00 SYNCCLK 3 MHz 102 RCLK3 and TCLKS rise fall time ns 103 TXD3 active delay from TCLK3 falling edge 0 00 30 00 ns 104 RTS3 active inactive delay from TCLK3 falling edge 0 00 30 00 ns 105 CTS3 setup time to TCLK3 rising edge 40 00 ns 106 RXD3 setup time to RCLK rising edge 40 00 ns 107 RXD3 hold time from RCLKS3 rising edge 2 0 00 ns 108 CD3 setup time to RCLK3 rising edge 40 00 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater than or equal to 3 1 2 Also applies to CD and CTS hold time when they are used as external sync signals MPC853T Hardware Specification Rev 1 Freescale Semiconductor 55 CPM Electrical Characteristics Figure 51 through Figure 53 shovv the NMSI timings
50. iconductor 51 CPM Electrical Characteristics L1TCLKB FE 0 CE 0 Input L1TCLKB FE 1 CE 1 Input LITSYNCB Input L1TXDB Output L1ST 2 1 Output e Figure 48 SI Transmit Timing Diagram DSC 0 MPC853T Hardware Specification Rev 1 52 Freescale Semiconductor L1RCLKB FE 0 CE 0 Input L1RCLKB FE 1 CE 1 Input LIRSYNCB Input L1TXDB Output L1ST 2 1 Output L1CLKOB Output CPM Electrical Characteristics 5 Figure 49 SI Transmit Timing vvith Double Speed Clocking DSC 1 MPC853T Hardware Specification Rev 1 Freescale Semiconductor 53 CPM Electrical Characteristics ndur 8011 ndino goHlT ndino 1 21S11 yndu gqaxu 1 ndino gax l HRU GONASHIT ndul gy1984 41 Figure 50 IDL Timing MPC853T Hardware Specification Rev 1 Freescale Semiconductor 54 CPM Electrical Characteristics 13 6 SCC in NMSI Mode Electrical Specifications Table 21 provides the NMSI external clock timing Table 21 NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK3 width high 1 SYNCCLK ns 101 RCLK3 and TCLK3 vvidth lovv 1 SYNCCLK 5 ns 102 RCLK3 and TCLK3 rise fall time 15 00 ns 103 TXD3 active delay from TCLK3 fallin
51. idirectional 5 V tolerant MIL TX EN U15 Output 5 V tolerant COL G3 Input VsssYN P5 PLL analog GND VsssYN1 R4 PLL analog GND VDDSYN R3 PLL analog Vpp MPC853T Hardware Specification Rev 1 Freescale Semiconductor 81 Mechanical Data and Ordering Information Table 32 Pin Assignments Non JEDEC continued Name Pin Number Type GND H7 H8 H9 H10 H11 H12 J7 J8 J9 J10 J11 J12 K7 K8 K9 Power K10 K11 K12 L7 L8 L9 L10 L11 L12 VDDL B8 D2 E17 H16 M5 N3 T2 N16 U9 Power V G6 G7 G8 G9 G10 G11 G12 G13 H6 H13 J6 J13 K6 K13 Power DDH L6 L13 M6 M7 M8 M9 M10 M11 M12 M13 N C B2 B17 C17 D16 E15 F13 M14 N5 R16 T17 U2 U17 No connect MPC853T Hardware Specification Rev 1 82 Freescale Semiconductor Mechanical Data and Ordering Information 15 2 Mechanical Dimensions of the PBGA Package Figure 69 shovvs the mechanical dimensions of the PBGA package 23 105 SEATING A1 INDEX C E d 256X 0 2 br 1 0
52. impedance MAX 0 00 x B1 20 00 RSTCONF pulse width 515 20 1425 01 340 00 257 60 ns J84 MIN 17 00 x B1 J85 Configuration data to HRESET 504 50 1425 00 1350 001 1277301 ns J86 rising edge setup time MIN 15 00 x B1 50 00 Configuration data to RSTCONF 350 00 1350 001 350 00 350 00 ns J87 rising edge setup time MIN 0 00 x B1 350 00 Configuration data hold time after 0 00 0 00 0 00 0 00 ns J88 RSTCONF negation MIN 0 00 x B1 0 00 Configuration data hold time after 0 00 0 00 0 00 0 00 ns J89 HRESET negation MIN 0 00 x B1 0 00 HRESET and RSTCONF 25 00 25 00 25 00 25 00 ns J90 asserted to data out drive MAX 0 00 x B1 25 00 RSTCONF negated to data out 25 00 25 00 25 00 25 00 ns J91 high impedance MAX 0 00 x B1 25 00 CLKOUT of last rising edge 25 00 25 00 25 00 25 00 ns before chip three states J92 HRESET to data out high impedance MAX 0 00 x B1 25 00 ea DSDI DSCK setup 90 90 75 00 1 60 00 45 50 ns MIN 3 00 x B1 ea DSDI DSCK hold time 0 00 000 000 000 ns MIN 0 00 x B1 0 00 SRESET negated to CLKOUT 242 40 1200 001 160 00 121 20 ns J95 rising edge for DSD
53. ing arrangement on the printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This thermal model is most useful for ceramic packages with heat sinks where some 90 of the heat flows through the case and the heat sink to the ambient environment For most packages a better model is required 7 3 Estimation with Junction to Board Thermal Resistance A simple package thermal model which has demonstrated reasonable accuracy about 20 is a two resistor model consisting of a junction to board and a junction to case thermal resistance The junction to case thermal resistance covers the situation where a heat sink is used or a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature If the board temperature is known an estimate of the junction temperature in the environment can be made using the following equation Ty Tp barn x Pp where Rey Junction to board thermal resistance C W Tp board temperature C Pp power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored acceptable predictions of junction temperature c
54. ings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling Proceedings of SemiTherm San Diego 1999 pp 212 220 17 Document Revision History Table 33 lists significant changes between revisions of this hardware specification Table 33 Document Revision History Revision Number Date Changes 0 10 2003 Initial release 0 1 12 2003 Added overbars to signals CR pin G2 and WAIT_A pin P4 on Figure 62 on page 63 1 0 12 2004 e Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values e Added a footnote to Spec 41 specifying that EDM 1 e Broke the Section 15 1 Pin Assignments into 2 smaller sections for the JEDEC and non JEDEC pinouts MPC853T Hardware Specification Rev 1 84 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC853T Hardware Specification Rev 1 Freescale Semiconductor 85 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC853T Hardware Specification Rev 1 86 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC853T Hardware Specification Rev 1 Freescale Semiconductor 87 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale
55. ion Rev 1 Freescale Semiconductor 29 Bus Signal Timing CLKOUT ADOT WE 0 3 D 0 31 DP 0 3 Figure 16 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 MPC853T Hardware Specification Rev 1 30 Freescale Semiconductor Bus Signal Timing Figure 17 provides the timing for the external bus controlled by the UPM CLKOUT E bel 35a gt 6350 gt gt lt 33 GPL_A O0 5 GPL 10 5 Figure 17 External Bus Timing UPM Controlled Signals MPC853T Hardware Specification Rev 1 Freescale Semiconductor 31 Bus Signal Timing Figure 18 provides the timing for the asynchronous asserted UPVVATT signal controlled by the UPM CLKOUT UPWAIT BS_A 0 3 ADO d X X GPL_B 0 5 Figure 18 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM CLKOUT UPWAIT pm mn E Ge Sane GPL ADO x X GPL_B 0 5 Figure 19 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC853T Hardware Specification Rev 1 32 Freescale Semiconductor Bus Signal Timing Figure 20 provides the timing for the synchronous external master access controlled by the GPCM CLKOUT be TS Al0
56. is the power dissipation of the I O drivers NOTE The Vppsyn power dissipation is negligible 7 1 Estimation with Junction to Ambient Thermal Resistance An estimation of the chip junction temperature T in C can be obtained from the following equation Ty T Roya X Pp where TA ambient temperature C Roya package junction to ambient thermal resistance C W Pp power dissipation in package The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance However the answer is only an estimate test cases have demonstrated that errors of a factor of two in the quantity Ty TA are possible MPC853T Hardware Specification Rev 1 Freescale Semiconductor 9 Thermal Calculation and Measurement 7 2 Estimation with Junction to Case Thermal Resistance Historically the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Rosa Royc Reca where Roya Junction to ambient thermal resistance C W Rerc junction to case thermal resistance C W RocA case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user adjusts the thermal environment to affect the case to ambient thermal resistance bana For instance the user can change the airflow around the device add a heat sink change the mount
57. leads and associated printed circuit traces connecting to chip Vpp and GND should be kept to less than half an inch per capacitor lead At a minimum a four layer board employing two inner layers as Vpp and GND planes should be used All output pins on the MPC853T have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times This recommendation particularly applies to the address and data busses Maximum PC trace lengths of six inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances caused by the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vpp and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins For more information please refer to Section 14 4 3 Clock Synthesizer Power Vppsyn Vsssyn gt Vsssynq in the MPC866 PowerQUICC Family User s Manual 11 Bus Signal Timing The maximum bus speed supported by the MPC853T is 66 MHz Table 7 shows the frequency ranges for standard part frequencies in 1 1 bus mode Table 7 Frequency Ranges for Standard Part Frequencies 1 1 Bus Mode P
58. nput timings B20 and B21 refer to the falling edge of the CLKOUT This timing is valid only for read accesses controlled by chip selects under control of the UPM in the memory controller for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18 10 The AS signal is considered asynchronous to the CLKOUT The timing B39 is specified in order to allow the behavior specified in Figure 21 MPC853T Hardware Specification Rev 1 Freescale Semiconductor 21 Bus Signal Timing Figure 3 provides the control timing diagram CLKOUT Outputs Outputs nputs nputs a Maximum output delay specification B Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 3 Control Timing Figure 4 provides the timing for the external clock CLKOUT Figure 4 External Clock Timing MPC853T Hardware Specification Rev 1 22 Freescale Semiconductor Bus Signal Timing Figure 5 provides the timing for the synchronous output signals CLKOUT OOOO A NAMSOS A NANS sms OKKA I o
59. ns J90 TRST assert time 100 00 ns J91 TRST setup time to TCK low 40 00 ns J92 TCK falling edge to output valid 50 00 ns J93 falling edge to output valid out of high impedance 50 00 ns J94 falling edge to output high impedance 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 ns MPC853T Hardware Specification Rev 1 42 Freescale Semiconductor IEEE 1149 1 Electrical Specifications TCK Figure 35 JTAG Test Clock Input Timing TCK TMS TDI TDO Figure 36 JTAG Test Access Port Timing Diagram TCK 090 J90 TRST Figure 37 JTAG TRST Timing Diagram MPC853T Hardware Specification Rev 1 Freescale Semiconductor 43 CPM Electrical Characteristics TCK Output 1 Signals Signals Output Signals 13 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of be j94 98 E EEA 5 gt J96 er Figure 38 Boundary Scan JTAG Timing Diagram the MPC853T 13 1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C interrupts Table 16 Port C Interrupt Timing 33 34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width l
60. ns circuitry protecting against damage caused by high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vppp MPC853T Hardware Specification Rev 1 Freescale Semiconductor A Thermal Characteristics Thermal Characteristics Table 3 shows the thermal characteristics for the MPC853T Table 3 MPC853T Thermal Resistance Data Rating Environment Symbol Value Unit Junction to ambient 1 Natural convection Single layer board 1s Roya 2 49 C W Four layer board 2s2p Banua 32 Airflow 200 ft min Single layer board 1s Roma 41 Four layer board 2s2p Regma 29 Junction to board Ross 24 Junction to case 5 13 Junction to package top 6 Natural convection WoT 3 Airflow 200 ft min Yir 2 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature airflow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and
61. oducts herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expens
62. ors WE 0 3 D 0 31 DP 0 3 Figure 10 External Bus Read Timing GPCM Controlled ACS 00 MPC853T Hardware Specification Rev 1 Freescale Semiconductor 25 Bus Signal Timing D 0 31 DP 0 3 Figure 11 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 TS CSx OE B18 819 D 0 31 DP 0 3 Figure 12 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MPC853T Hardware Specification Rev 1 26 Freescale Semiconductor Bus Signal Timing CLKOUT CSx ez OE e 627a 6220 22c x Bss ebei a 619 Figure 13 External Bus Read Timing GPCM Controlled TRLX 0 or 1 5 10 ACS 11 Figure 14 through Figure 16 provide the timing for the external bus vvrite controlled by various GPCM factors MPC853T Hardware Specification Rev 1 Freescale Semiconductor 27 Bus Signal Timing CLKOUT A 0 31 WE 0 3 D 0 31 DP 0 3 Figure 14 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 0 MPC853T Hardware Specification Rev 1 28 Freescale Semiconductor Bus Signal Timing ADOT WE 0 3 D 0 31 DP 0 3 Figure 15 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 MPC853T Hardware Specificat
63. ow edge triggered mode 55 ns 36 1 Port C interrupt minimum time between active edges 55 ns Figure 39 shovvs the port C interrupt detection timing gt Port C Input 36 Figure 39 Port C Interrupt Detection Timing MPC853T Hardware Specification Rev 1 44 Freescale Semiconductor CPM Electrical Characteristics 13 2 IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shovvn in Figure 40 to Figure 43 Table 17 IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 ns 41 DREQ hold time from clock high 1 3 ns 42 SDACK assertion delay from clock high 12 ns 43 SDACK negation delay from clock low 12 ns 44 SDACK negation delay from TA low 20 ns 45 SDACK negation delay from clock high 15 ns 46 TA assertion to falling edge of the clock setup time applies to external TA 7 ns Applies to high to low mode EDM 1 CLKO Output dak DREQ Input Figure 40 IDMA External Requests Timing Diagram MPC853T Hardware Specification Rev 1 Freescale Semiconductor 45 CPM Electrical Characteristics CLKO Output TS Output BAN Output TA Input SDACK Figure 41 SDACK Timing Diagram Peripheral Write Externally Generated TA CLKO Output TS Output R W Output TA Output SDACK Figure 42
64. package as viewed from the top surface For additional information see the MPC866 PowerQUICC Family User s Manual MPC853T Hardware Specification Rev 1 Freescale Semiconductor 67 Mechanical Data and Ordering Information NOTE This is the top view of the device 51 m Q CS7 GEL AZ VVE2 BS AO VDDL CSO 2 A GEL VVE3 MIL CRS BS SO VDDL GPL A4 CS3 o O CS5 GPL_AO WE1 BS A2 O BDIP BI 2 80 CS2 CS6 OE VVEO BS_A1 TEA GPL_A5CE_1A CS4 TSIZ1 4 0 N o gt o gt 5 20 sO ND 4 T ba o 0000 000000 000000 000000 000000 000000 000000 m gt i l gt a E o P Bs o E GO GO o x z I 50O a o X o g E a E EO E a E o E 2 T o x O g N N s E o E a o E d E N wo E N PD4 EDO N g N E wo 0 ZA 80 20 FO 8 sO 3 4 5 6 E 8 9 10 11 12 13 14 N C PD10 Q T Figure 67 Pinout of the PBGA Package JEDEC Standard Table 31 contains a list of the MPC853T input and output signals and shows multiplexing and pin assignments Table 31 Pin Assignments JEDEC Standard Name Pin Number Type A 0 31 B15 A15 A14 C14 D13 E11 B14 A13 C13 B13 D12 E10 C12 Bidirectional B12 A12 D11 E9
65. per memory bank Glueless interface to DRAM SIMMS SRAM EPROMs Flash EPROMs and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines four WE lines and one OE line Boot chip select available at reset options for 8 16 or 32 bit memory Variable block sizes 32 Kbytes 256 Mbytes Selectable write protection On chip bus arbitration logic e Fast Ethernet Controller FEC MPC853T Hardware Specification Rev 1 Freescale Semiconductor Features e HGeneral purpose timers Two 16 bit timers or one 32 bit timer Gate mode can enable disable counting Interrupt can be masked on reference match and event capture e System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller IEEE 1149 1 test access port JTAG e Interrupts Seven external interrupt request IRQ lines Seven port pins with interrupt capability Eighteen internal interrupt sources Programmable priority between SCCs Programmable highest priority request e Communications processor module CPM RISC controller Communication specific commands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8 Kbytes of dual port RAM Eight serial D
66. riod MPC853T Hardware Specification Rev 1 64 Freescale Semiconductor FEC Electrical Characteristics Figure 64 shows the MH transmit signal timing diagram M7 1 input 5 MIl_TXD 3 0 outputs MIL EN MIL TX ER M MO 6 Figure 64 MII Transmit Signal Timing Diagram 14 3 MII Async Inputs Signal Timing MII CRS MI Table 28 provides information on the MII async inputs signal timing Table 28 MII Async Inputs Signal Timing Num Characteristic Min Max Unit MO MII_CRS MII_COL minimum pulse width 1 5 MII_TX_CLK period Figure 65 shows the MII asynchronous inputs signal timing diagram 5 MIL GOL M9 Figure 65 MII Async Inputs Timing Diagram 14 4 MII Serial Management Channel Timing MII_MDIO MII_MDC Table 29 provides information on the MII serial management channel signal timing The FEC functions correctly with a maximum MDC frequency in excess of 2 5 MHz The exact upper bound is under investigation Table 29 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 1MII MDC falling edge to MII_MDIO output invalid minimum 0 ns propagation delay M11 MII_MDC falling edge to MII_MDIO output valid max prop delay 25 ns M12 MII_MDIO input to MI rising edge setup 10 ns MPC853T Hardware Specification Rev 1 Freescale Semiconductor 65
67. s HRESET E OP2 OP3 Figure 28 PCMCIA Output Port Timing Figure 29 provides the PCMCIA in put port timing for the MPC853T CLKOUT Input Signals Figure 29 PCMCIA Input Port Timing MPC853T Hardware Specification Rev 1 38 Freescale Semiconductor Bus Signal Timing Table 13 shows the debug port timing for the MPC853T Table 13 Debug Port Timing All Frequencies Num Characteristic Unit Min Max 482 IDSCK cycle time 3 x TCLOCKOUT J83 DSCK clock pulse width 1 25 x TCLOCKOUT J84 DSCK rise and fall times 0 00 3 00 ns J85 DSDI input data setup time 8 00 ns J86 DSDI data hold time 5 00 ns 487 low to DSDO data valid 0 00 15 00 ns J88 DSCK low to DSDO invalid 0 00 2 00 ns Figure 30 provides the input timing for the debug port clock DSCK Figure 30 Debug Port Clock Input Timing Figure 31 provides the timing for the debug port DSCK DSDI Figure 31 Debug Port Timings MPC853T Hardware Specification Rev 1 Freescale Semiconductor 39 Bus Signal Timing Table 14 shows the reset timing for the MPC853T Table 14 Reset Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to HRESET high 20 00 20 00 20 00 20 00 1 ns J82 1impedance MAX 0 00 x B1 20 00 CLKOUT to SRESET high 20 00 20 00 20 00 20 00 1 ns J83
68. s cycle timing for the external bus read PCOE IORD ALE D 0 31 P46 bee P45 MPC853T Hardware Specification Rev 1 ZE Figure 25 PCMCIA Access Cycles Timing External Bus Read 36 Freescale Semiconductor Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus write pen Figure 26 PCMCIA Access Cycles Timing External Bus Write Figure 27 provides the PCMCIA WAIT signals detection timing CLKOUT WAITA Figure 27 PCMCIA WAIT Signals Detection Timing MPC853T Hardware Specification Rev 1 Freescale Semiconductor 37 Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC853T Table 12 PCMCIA Port Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max J95 CLKOUT to OPx valid 19 00 19 00 19 00 119001 ns MAX 0 00 x B1 19 00 J96 HRESET negated to OPx 25 70 121701 118001 11440 ns drive MIN 0 75 x B1 3 00 J97 IP_Xx valid to CLKOUT rising edge 5 00 5 00 5 00 5 00 ns MIN 0 00 x B1 5 00 CLKOUT rising edge to IP Xx invalid 1 00 1 00 1 00 1 00 ns 498 MIN 0 00 x B1 1 00 1 OP2 and OP3 only Figure 28 provides the PCMCIA output port timing for the MPC853T CLKOUT Output Signal
69. s section provides the maximum tolerated voltage and temperature ranges for the MPC853T Table 1 provides the maximum ratings and the operating temperatures Table 1 Maximum Tolerated Ratings Rating Symbol Value Unit Supply voltage 1 Vpp core voltage 0 3 to 3 4 I O voltage 0 to 4 V VDDSYN 0 3 to 3 4 V Difference between VppL 100 mV and VppsYN Input voltage Vin GND 0 3 to VppH V Storage temperature range Tetg 55 to 150 C 1 The power supply of the device must start its ramp from 0 0 V 2 Functional operating conditions are provided with the DC electrical specifications in Table 5 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device Caution All inputs that tolerate 5 V cannot be more than 2 5 V greater than Vppy This restriction applies to power up and normal operation that is if the MPC853T is unpowered a voltage greater than 2 5 V must not be applied to its inputs Table 2 Operating Temperatures Rating Symbol Value Unit Temperature standard Ta 0 eC Tjmax 95 C Temperature extended Ta min 0 C Tjmax 100 C 1 Minimum temperatures are guaranteed as ambient temperature TA Maximum temperatures are guaranteed as junction temperature Tj This device contai
70. small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire 8 Power Supply and Power Sequencing This section provides design considerations for the MPC853T power supply The MPC853T has a core voltage Vppt and PLL voltage Vppsyn which both operate at lower voltages than the I O voltage Vppy The I O section of the MPC853T is supplied with 3 3 V across Vppu and Vss GND The signals PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TCK TRST TMS MII_TXEN and are 5 V tolerant All inputs cannot be more than 2 5 V greater than Vppu n addition 5 V tolerant pins can not exceed 5 5 V and remaining input pins cannot exceed 3 465 V This restriction applies to power up down and normal operation One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates The rates depend on the nature of the power supply the type of load on each power supply and the manner in which different voltages are derived The following restrictions apply VDppL must not exceed Vppu during power up and power down must not exceed 1 9 V and Vppu must not exceed 3 465 V These cautions are necessary for the long term reliabili
71. ty of the part If they are violated the electrostatic discharge ESD protection diodes are forward biased and excessive current can flow through these diodes If the system power supply design does not control the voltage sequencing the circuit shown in Figure 2 can be added to meet these requirements The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up and the 1N5820 diodes regulate the maximum potential difference on power down MPC853T Hardware Specification Rev 1 Freescale Semiconductor 11 Mandatory Reset Configurations VDDL MUR420 1N5820 Figure 2 Example Voltage Sequencing Circuit 9 Mandatory Reset Configurations The MPC853T requires a mandatory configuration during reset If hardware reset configuration word HRCW is enabled the HRCW DBGC value needs to be set to binary X1 in HRCW and the SIUMCR DBGC should be programmed with the same value in the boot code after reset This can be done by asserting the RSTCONF during HRESET assertion If HRCW is disabled the STUMCRIDBGCI should be programmed with binary X1 in the boot code after reset by negating the RSTCONF during the HRESET assertion The MBMR GPLB4DIS PAPAR PADIR PBPAR PBDIR PCPAR and PCDIR registers need to be configured with the mandatory value in Table 6 in the boot code after the reset is negated Table 6 Mandatory Reset Configuration of M
72. wn in Figure 1 The following list summarizes the key MPC853T features e Embedded MPC8xx core up to 100 MHz e Maximum frequency operation of the external bus is 66 MHz The 50 66 MHz core frequencies support both the 1 1 and 2 1 modes The 80 100 MHz core frequencies support 2 1 mode only e Single issue 32 bit core compatible with the PowerPC architecture definition with thirty two 32 bit general purpose registers GPRs The core performs branch prediction with conditional prefetch and without conditional execution 4 Kbyte data cache and 4 Kbyte instruction cache Instruction cache is two way set associative with 128 sets Data cache is two way set associative with 128 sets Cache coherency for both instruction and data caches is maintained on 128 bit 4 word cache blocks Caches are physically addressed implement a least recently used LRU replacement algorithm and are lockable on a cache block basis MMwUs with 32 entry translation look aside buffer TLB fully associative instruction and data TLBs MMUs support multiple page sizes of 4 Kbytes 16 Kbytes 512 Kbytes and 8 Mbytes 16 virtual address spaces and 16 protection groups e Upto 32 bit data bus dynamic bus sizing for 8 16 and 32 bits 32 address lines e Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable
73. y application due to buffer current which depends on external circuitry The Vppsyn power dissipation is negligible 6 DC Characteristics Table 5 provides the DC electrical characteristics for the MPC853T Table 5 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage VDDH 3 135 3 465 V VppL 1 7 1 9 V VDDSYN 17 1 9 V Difference between VppL 100 mV and VppsYN Input high voltage all inputs except PA 0 3 2 0 465 V PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TCK TRST TMS MII_TXEN MII_MDIO 1 Input low voltage GND 0 8 EXTAL EXTCLK input high voltage ViHc 0 7 x VDDH VDDH Input leakage current Vin 5 5 V except the TMS lin 100 HA TRST DSCK and DSDI pins for 5 V tolerant pins 1 Input leakage current Vin Vppu except TMS lin 10 HA TRST DSCK and 0501 Input leakage current Vin 0 V except the TMS lin m 10 HA TRST DSCK and 0501 Input capacitance Cin 20 pF MPC853T Hardware Specification Rev 1 8 Freescale Semiconductor Thermal Calculation and Measurement Table 5 DC Electrical Specifications continued Characteristic Symbol Min Max Unit Output high voltage IOH 2 0 mA Vppy 3 0 V VoH 2 4 V except XTAL and open drain pins Output low voltage VoL 0 5 V IOL 2 0 mA CLKOUT IOL 3 2 mA 3 IOL 5 3 mA 3 IOL

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