CDB49400 Evaluation Board for CS49400 Family DSP
Contents
1. CIRRUS LOGIC APPENDIX G ul no as uvix3 evivacos 21 6vix3 ewaov 05 Zwix3 evivo 05 12 8 1x3 euaov as 1 1 3 01 1 0705 21 LviX3 408705 05 21 Sivia avivo as 23 41 9vix3 sudov 05 9v1X3 S1V1VQ OS 21 cvix3 cuQv as INIX3 Piv1NO GS 21 0 05 giv siv1va as 23 ul 705 wod as 02 8 05 O 013 110 as 21 121 0LvV1X3 0l300V 05 s01x3 9v1vd 08 21 901 3 9 1 0 os oos 121 gt 013 419 65 21 A I I Oon A 3070 FOOT ITTY 1 EE ENGL Seo 865 napona 6651 25 eza MM dn2. Figure 19 Sheet 4 Microcontroller Lv 15V 9 R56 019 33 85 TP86 1k LM39401T 3 3 9 15VBUS 4 3 CA 2 R57 24 2 10446 06 C43 D7 o 121 2 52488 0 tuf 227 100 716 SW GREEN LED 187 GND GND GND t R58 4 500 POT 0 GND C45 08 C46 D9 10uf 16 2 5248 0 tuf AN 100uf 16 W GREENLED NO 18v x R59 4 V J37 15VBUS 4 4 1 GND oe GND 043 3V 0 2 5V HEADER 2X2 AN VL SEL 88 TP89 TP90 91 92 TP93 TP94 GND 95 TP96 97 TP98 45VD 020 99 TP1005 5y 9 9 9 LT2937ET 2 5 9 9 5VD 4 1 vin 4 1 2 R60 R61 D10 _ cso 51 C52 9 121 C53 374 ZMM5248B 22 100 16 1004016 C54 6 3V 100 16 VR2 __ C55 500 gt 10 16 011 w GREENLED M2 E 8 Ae 6 8 GND GND 3 3
3. trn UDSP_AINS OK R256 R252 100K 2200pF R253 150 5 5 34 11 2 34 13470 ADC_OIFY Ras 5VA C235 5VA TEX A 35 032 A t d DIFO HPDEFEAT 11 3 4 5 6 7 8 10 11 3 ori ove S e P49 de 152 2V_WRESET L gt 5 RST 3 4 gt 3 TS AUT POND Lg jour 0225 15V0 330780 Mout vot 7 m A 8248 10K case ANR 35224 hie LRCLK 2 SDATA Ho 0229 063 134 807 FRAME R264 NNN 11 55360 5 5VA 10u 228 R208 tT UDSP_AING are R247 10K 6 wesso79b m R251 4 MC33078D 5 19 8 v 1 100k L C231 R214 10K 2200pF 8250 400 MC33078D 213 10k 15VD i5vb c69 C106 cet 11 ym uF uF 107 97 R207 20 tI UDSP_AIN7 R217 R239 5 2 4 MC33078D 100K 2200pF Y R238 150 T 15VD 5VA 5VA 3 4 11 gt gt 8210 3 4 11 ADC DiF1 L 0 5 5 A uie 54 H TP32 1627 11 5 4 5 6 7 8 0 11 ovr 5 Selec TCR RESET 7 57 VAt TIAN 4 15v0 NC330780 4
4. 84 5 2 112258 se tz 0v1x3 0sd0v 0s EC CDM e Pau OEC ERES vg zaixa zvivo as 10 101 iv1x3 1N00v 0s 35 ivi va idixi ivd os 101 08 5 30 9 10169 S9 AN ig 21 610 49 830 AN 11 zoldS SNV1 VOS p S10ld3 f 3M AN 11 9Z0143 ZNV1V0S 00 49 01 03 001494 01404 01 20idd INVLYOS 81 60145 105 1531 1531 0800 vZold9 ONV1VGS tooa tdl 841 8 EN vaga tion z0149 1y9708 oni 208932103 20492 21 03 1 220149 125 381 2209 125 wwagad 11281 ii now 01494 c1v04 13N 100A 0ld93 v1VQ4 01d94 v1v04 08 ISSA 50199191903 0193 8103 LLYOnv ova 46 30804 011 0 TE 21707 0 0096953 03 IN von 35 in 993 1 S SE M 83 4044 1SH4 01 61 35 Sa3 3 osus 0 63 1910500 bros 955 yon HEE zaoa L01d94 L1V04 101494 L1vG4 HoH essa 12089 12099 110119 1 00 0 01 01025 775 4 010254 25 3 61 Y1VOH SL nive o 19953 0 3 10253 0 3 twon 08108 0 fos 8 85 2 020148 020149 1061 fV1VOH evivar 8 38 58 g 8 99531 3 4 1 3
5. 74 08 J49 SPDIF_TX4 alo 5 87 R69 lo ps lt gt 173 R70 55 J50 8 374 11 44 1 1 R71 93 1 1 T4 67129600 Figure 24 9 1 4 SPDIF_TX1 E md 1 4 SPDIF TX2 Eee 1 4 SPDIF 2 5 SPDIF TX1 alo 5VD O 3 0 c2 HO 173 R3 J5 374 PHONO JACK RA EC 1 74 08 R4 93 1 1 1 67129600 SPDIF_TX2 alo 5VD O alo gt LAS ro 8 20k pon ol s R6 J9 c7 374 4 PHONO JACK RA OU 1 74 08 R7 93 1 1 2 67129600 311 SPDIF_TX3 alo 5VD 3 0 I A out 8 20k 22 40 17 R9 di 13 374 PHONO JACK 3 7 4 10 1 74 08 Sheet 9 S PDIF Receivers Transmitters R10 93 1 196 T3 1 67129600 04 APPENDIX J BILL OF MATERIALS UDSP C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 CAP CERAMIC 0 1UF 50V 1096 X7R 1206 C13 C14 C15 C16 C17 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C39 C40 C42 C44 C47 C51 C53 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C E p 57 C78 C83 C87 C88 C89 1206 104 5 CAP C
6. Tm sv DeSeT T V NE 57 lt 301163 2v VSK miso Gens V SCK 86 JROn S 0 csa7 RS232 Interface ROn S 0 ADDRIs Io ADDRIG ADDRIT 18 RTS SMCTRLO 0 BMCTRLI WRn MUTECTRLO MUTECTRL1 yn MUTECTRLZ 27 8868 PP CTRL O PP_CTRUZ 0 2V DBCK PP STROBER PP STROBER V DBCK2 AV PP_ACKn PACK 2 MRESETR PP STATUS 0 PP STATUSQ 0 5V MRESETn 5 2V_DSP1_RESETn PPORT 2V_DSP2_RESETn Digital Audio Port DAP morg 06 DAP_MCLK ADC SCLK DAP_SCLK DAP_SCLK ADC_SDOUTIA 1 DAP SDOUT S 1 DAP SDINA 1 DAP SDIN 4 1 DSP1 CDL SCLKS DSPI CDI ERCH DSP CDLLRCLK DAP SPDIF_RX1 DSP1 CDI SDIN SPDIF 2 SPDIF RX3 DSP1 DAI 5 LA DSP1_DALLRCLK T DSPi SDIN SPDIF TG SPDIF Du DSP1 DAO DAG SCLIC SPDIF 0521 SCLK SPDIF SCLK DSP1 DAO RCLK SPDIF DSP1 DAO SDOUTIA 1 SPDIF 80007 NODE SEL 7 0 DSP2 CDI 9 DSP7 CDERCD SPARE 6 0 DSP2 CDL LRCLK 0 DSP2 CDI SDIN 85422 DATA RS422 DSP2 DAL 94 RS422 CLKT DSP2 DAL RCLK RS422 CLK2 DS
7. CIRRUS LOGIC CDB49400 Evaluation Board for CS49400 Family DSP Features 8 Discrete analog inputs using CS5360 ADCs 8 Discrete analog outputs using 54392 DACs Supports 16 Channel decoding capability of the CS49400 e 1 Digital input using the CS8415A S PDIF receiver e 3 Digital outputs using the CS8405 S PDIF transmitter e On board memories for special post processing needs e On board debug functionality for DSPC Description The CDB49400 is an evaluation board for the CS49400 144 Pin family of DSPs It allows customers to develop download and test custom algorithms on the CS49400 The onboard PLD on the UDSP can route data to any of the audio data inputs and supply clocks in many different combinations to the CS49400 The board interfaces to a PC via a ECP parallel port Optical and RCA connectors are used to interface with DVD players powered speakers and other test equipment Compressed data can be delivered in IEC61937 format via the S PDIF port PCM data can be accepted through the digital input connector or from the on board ADCs Together these boards supports all the decoding algorithms developed by Cirrus Logic ORDERING INFORMATION CDB49400 Evaluation Board UDSP BOARD REV B PARALLEL RS 422 PORT INTERFACE INTERFACE HEAD PHONE RS232 INTERFACE SRAM 512KX8 ANALOG INPUTS
8. C56 L C57 n C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C73 C74 C75 C76 C78 10uf 16 10 16 10 16 104016 0 1uf 0 tuf O 1uf 0 1uf 0 1uf 0 1uf 0 1uf 0 1uf 0 1uf 0 1uf GND Figure 20 Sheet 5 Power ADOT 8r 5VD RP2 1k RPACK5 5VD RP3 1k RPACK5 15 X_D2 3 14 02 X_D3 4 13 PP D3 X_D4 _ 4 a 4 5 12 05 6 11 PP D5 X D6 1 10 PP D6 X D7 i 8 PP_D7 470 RPACK8 ro 1 X nSTROBE 5 14 nAUTOFEED o l2 X DO 15 nERROR 3 X Di od 16 nINIT X_D2 RTE 15 511 5 X_D3 oss a X_D4 X 05 120 X_D6 9 X_D7 122 1 10 X ACKn 1 nBUSY A e 0412 5 _4 2 13 SELECT J46 DB25M_RA GND RP4 AUD 1k 5 TP65 PP D 7 0 pg 4 X nSTROBE R48 2 2k nAUTOFEED R49 2 2k nINIT R50 2 2k nSELECTIN R51 2 2k RP6 1556 1k 5 PP STROBEn 4 PP CTRLO pg 4 PP CTRL1 pg 4 PP CTRL2 pg 4 PP ACKn pg 4 _5 52 66 68 70 SELECT nERROR PP_STATUS3 Figure 21 Sheet 6 Parallel Port Interface 22 RPACK8 PP_STATUS 3 0 9 4 SND TP72 TP73
9. DF MopESES 927 28 TE 0 30 B ADC_DIFO GND irr 3 34 35 36 937 38 1c osc 49 p SOCKET 20 2 2 Figure 16 Sheet 1 Universal DSP System Platform SERIAL AUDIO I O 2 16 PHONO JACK RA Alot 1 GND ne PHONO JACK RA 6 GND 120 PHONO JACK 1 GND 321 PHONO JACK RA GND 123 PHONO JACK RA los GND 125 PHONO JACK RA 1 lt GND p PHONO JACK RA 6 GND 229 PHONO JACK RA fe GND E PHONO JACK RA GND 333 PHONO JACK RA A1010 1 GND I XIGNIddV SOLLVIWIHOS vv HEADER 16X2 RP8 5 017 22 RPACK8 4 DAP_SDOUT 8 1 L__ gt DAP SDOUT4 2 A 16 DAP SDOUT1 B 500012 RARA DAP_SDOUT2_B Uu DAP SDOUTS 31 DAP SDOUT3 N DAP SDOUT e DAP 500014 B SDOUTS 6 5 12 ___ _5 _ SDOUT6 RCN DAP_SDOUT6_B N DAP SDOUT7 1 500077 B DAP_SDOUTS 9 Pied Ir DAP 500018 B aan GND gd Ga J47 q 1 2p 5 74 541 Otuf 48 3 3 SZ 2 0 ow HEADER 3X2 DAP VL SEL 4 9 4 DAP_MCLK 1 2 9 4 DAP_LRCLK 3 4 pg 4 DAP_SCLK 5500 B 5 L DAP SDOUTB 97 8 DAP SDOUT3 B 11 12 D
10. DAO LRCLK1 GENESIS CDI UNAGAI DAO GENESIS DAI TRIDENT ADCSCLK SA ADC SCL 0 ADC 0015 ADCSDOUI2 ADC SDOUT3 _ 5 ADC SDOUT4 __ CDB49400 Figure 1 Audio Data Clock Routing CIRRUS LOGIC 3 SOFTWARE OVERVIEW A suite of software has been provided with CDB49400 Currently the CDB49400 is controlled by the software described in BOARD CONTROL SOFTWARE on page 21 Figure 2 describes the typical structure of a batch file that used to setup the board and boot the DSP This flow chart describes the flow of the 49400 on page 15 All batch files first call SET INLBAT which gets an environment variable to the location of CDB49400 INI file described on page 19 This INI file contains the board configuration of all the devices on the CDB49400 to the software drivers The SET INLBAT batch file must be executed every time a new DOS session is started Next the file RESET BAT on page 20 is called This batch file mutes the DACs and resets all the devices including the DSP on the CDB49400 board Next the SPDIF_ANA_IN_DIG_ANA_OUT BAT file described on page 17 is called to boot and configure each device except the DSP in the modes described in the batch file The PLD is also configured as shown in Figure3 Sample Data Clock Routing on page 9 At this time all peripherals are setup and ready to accept data The DSP is then booted using the 0
11. 178W 5 Ele RIS A A 2241 433v 12 18 1 OLRCLK HZ YSPDIF_LRCLK 1 1 2 OSCLK He SPDIF SCLK im RXP3 RXP4 5 C24 31651 c10 F XR R141 CS8415A CZ ELEC X7R t 20 25 47uF SPDIF RX2 249 Yo H 1 SPDIF RX3 id y H in SPDIF RX4 Haz 2 5 62 She 0 01uF Mp Reo H3 4163 c9 89 92 ELEC XR Dm ose 115 10 10 Tue uF RX ERR 5VD HO RIB 221 8 n 178 5 pur voc c15 E du UR 3 01K 1788 GND 165 4 12 2880 MHZ coc 2200pF e X7R 0 047UF Figure 8 Sheet 5 S PDIF RCVR gt SPDIF_SDOUT 1 SND R173 5 62 i5vp A A C186 5609F 1 XIR XIR ss C182 1 UV 1 8169 2 12 58 77 5 62 118K iori 2 3 C183 10uF v 4 MC33078D 560 tes 2 EX 5 62K cuo ek b 0G fe 2700F Sem 2 Sins 15v0 2563326 gt of 6 7 10 95 b 2 1
12. page 24 for details on installing the drivers N Connect the supplied parallel port cable to 746 and to the computer s parallel port 3 Connect the optical output from a DVD player to RXI 4 Connect a powered speaker to AIOI The output channels are mapped as follows AIOI Left AIO2 Center AIO3 Right AIO4 Left Surround AIOS Right Surround AIO6 Surround Back Left AIO7 Surround Back Right AIO8 Subwoofer More speakers can be connected to the line level outputs as required by each application 5 Connect the supplied power supply to the power connector on the board Verify that LEDs D1 D7 D9 D11 on the UDSP board and D9 D13 D17 D20 on CDB49400 daughter card are lit LED D2 will flash to indicate that the PLD on the UDSP is functional ON 7 Open a DOS window and navigate to the C CS49400 CDB49400 Configs directory 8 Type in setpld r 99 on the DOS prompt This reads the PLD version register and verifies that the PC can communicate with the board If the driver generates the error message 111 Board does not appear to be connected then your parallel port address may not be 0x378 or your port is not ECP capable If your parallel port address is not 0x378 depress the reset switch S3 and type in setpld r 99 p3bc or setpld r 99 p278 to communicate using a different parallel port address 9 Verify that the value returned is not 0 99 or Oxff an
13. nderit 20 APPENDIX E BOARD CONTROL nanana 21 APPENDIX INSTALLATION OF BOARD CONTROL 24 APPENDIX CDB49400 SCHEMATICS nennen nnns 26 APPENDIX H BILL OF MATERIALS CDB49400 nnana 38 APPENDIX UDSP SCHEMATICS 43 APPENDIX J BILL OF MATERIALS 52 CIRRUS LOGIC LIST OF FIGURES Figure 1 Audio Data Clock 7 Figure 2 Software Figure 3 Sample Data Clock Routing Figure 4 Sheet d DSP 2 Figure 5 2 En e Pee este Figure 6 3 1 25 Figure 7 cheet 42 ADG Figure 8 Sheet 5 S PDIF 44 00000000 essere Figure 9 Sheet 6 DAC 1 Figure 1 7 2 nte e ER EG RT ta eu nes Figure Sheet 8 S PDIF Figure 12 Sheet 9 Buffers
14. 8 4 1 SPDIF ANA DIG ANA OUT BAT essent nennen eren 8 5 BOOT MODES AND DEBUG nnn nasse nnne nnn 9 5 1 Deb g Port for terrere tuos ea ER EA eat tees 9 6 EXTERNAL MEMORY 10 6 1 SBRAM U8 pe Rte se Roe EAT Dn Tea 10 6 2 SRAM Ub certi e Y aa e eect 10 5 3 FLASH UO te E ERE EEUU eoe oe om deat o e ces ed eet 10 DEFAULT JUMPER SETTINGS ON THE CDB49400 eene 11 7 1 Host Interface Boot Modes nennen 11 7 2 Host Interface Boot Mode Jumpers 11 7 3 Debug Port Interface 12 7 A Communication 12 To Goral Aeon 12 7 6 Other Settings ten Edad vine A A ONT AA E 13 8 DEFAULT JUMPER SETTINGS ON 14 APPENDIX A POM 49400 2 15 APPENDIX B SPDIF ANA IN DIG ANA 4 2 2 0001 17 APPENDIX CDB49400 INI 22e eere einer en rasan ceri nena 19 APPENDIX D RESET BAT
15. TP74 TP75 RX_IN RTS IN gt pg 4 ive 8 RTS 5 cts S 0 2 BEAD C34 1uf 16C C35 1uf 16C C36 1uf 16C MAX232CWE V GND C37 C38 1uf 16C 1uf 16C GND GND Figure 22 Sheet 7 RS232 Interface 6t TP76 TP77 TP78 TP79 O 5VD TP80 TP81 TP82 TP83 GND DB9F RA ADOT os DB9F RA DATA1 DATA1 RS422 DATA1 4 RS422 CLK2 4 RS422 4 5VD C90 1uf 16C DS8922A Figure 23 Sheet 8 RS422 Interface SMR LS 5VD 5 ob i 9 5 173 gt SPDIF_RX1 14 24 5 97 els RX PWR 1 6 2 1 ORKAT SPDIF RX2 pg 14 5 2 gt els RX_PWR Qui Je Io gt SPDIF_RX3_pg 1 4 5 el Qo ok cs XE 5 TORX 178 gt SPDIF RX4 pg 1 pg 1 4 SPDIF TX4 ERN N J3 PHONO JACK RA SPDIF R2 75 GND J6 1 p x 3 HEADER 3X1 1 GND 2p _ _ gt s gt SPDIF_RXPO pg 1 PDIF RXNO pg 1
16. ctos va LZ peas CLR Spo Tur coc Z c2 7 16 16208 41020 wr 2700pF S RIBS 2 Saige 5 Ee se Tour wr 2545922 tt c 2 1 2 MMUNZTHLTT 167 MUTECTRLO Figure 9 Sheet 6 DAC 1 R83 10K UDSP AOUT i ADOT 50112 UDSP AOUT2 10 UDSP AOUTS 111 UDSP AOUTA 10 ce 067 810 7 8 010 10 01 6 7 8 10 10 A pres C165 10uF 1 yv VV 2 P Liew uosP_AOUTS 5 62K Wag 2565326 8 7 0 MUTECTRLO 1 R84 2 TER UES i 5 EE n ae a se 5 6 Bee VA BMUTEC je 5 28 UDSP AOUTE 11 LRCLK 2 C155 10uF M 6192 560 1 3 dor lm 7 Ip Tu 10720716 LS 1069 aw 2700 lt RI60 2 rS XR X Sec 362k ae 355 C142 10uF LANA m8 R147 E inse
17. 425v A 920 R29 10K R28 10K R26 DSP BOOT MODE UHS0 6P1018 UHSi GPIOIS 52 05 007 12411 2 5 HORSX1 m FHSO FWRE FOS 19 001 R32 10K IHoR3Xt En moe ux FHSI FRO FR W 19 101 R34 FHS2 FSCDIO 19 101 DSP AB BOOT MODE DBCK Oe tim 2v gt gt DBDA 2V DBDA tn 1 8 _ gt 2 gt HORSX1 amp HORSX1 312 HOR3XI 13 DEBUG DONGLE t191 91 18 01 119 102 119102 tH 2 2 2 21 21 2 2 2 2 01 21 1 21 21 21 1 1 FINTREGF FAI FSCOIN FAO FSCCLK D FHSZ FSCOIO FHSO FWRg FOS FHSI FRO FRZW E FeSO TEST EXTAT E EXTA4 EXTAS EXTAG EXTAT E EXTAB 15 m as to exman a E 3 33 140 B E Hg pi EXTAIB 17 5 89 ZV WRESET 0 5 4562 840 J FDATO FGPIOO 191 1 FDATI FGPIO 019 FDATZ FGPIO2 191 J FDATS FGPIOS 1 9 J FDATA FGPIO4 1 9 FDATS FGPIOS 1
18. 5 THICK FILM 4 7K 1 8W 5 1206 TSMD R18 R19 R21 R22 R28 R31 R32 RES THICK FILM 10K 1 8W 1 1206 R33 R35 R36 R37 R41 R42 R43 R82 R83 R87 R88 R89 R90 ERJ 8ENF1002 PANASONIC Mg R20 R52 R53 R54 R55 ERJ 8GEYJ330 PANASONIC 5 THICK FILM 33 1 8W 5 1206 R23 R24 R25 R34 R39 R40 R48 RES THICK FILM 2 2K 1 8W 5 1206 10 R49 R50 R51 ERJ 8GEYJ222 PANASONIC Pim ERJ 8GEYJ334 PANASONIC 5 THICK FILM 330K 1 8W 5 1206 LUMINE IM ee ERJ 8GEYJ106 PANASONIC RES THICK FILM 10MEG 1 8W 5 1206 ES s Rae RS Fa RET GSE _ _ PANASONIC RES THICK FIM IK VW 2 ERJSENFIZIO PANASONIC RES THIGK FILM 121 178W 1 1206 L ERISGEVIRGN PANASONG RESTHICK FLW OW 5 126 samm oO Bre ROS RBG PANASONIC RES THICK FILM300 5 1208 R74 R75 R76 R77 R78 R79 80 RES 49 9 OHM 1 0805 1 10W Ri ERJ 8GEYJ470V PANASONIC 4610X 101 331 BOURNS RES R PACK9 330 1 8W 296 SIP10 SW1 SW2 SW3 SW4 501 SWITCH SLIDE SPDT 64 765808 GRAYHILL SWITCH DIP 8 POS ROCKER DIP16 eee 94HBB16 GRAYHILL SWITCH DIP ROTARY HEXSM DIP ROTARY HEX SM SE GE 6MM TACT W ESD PIN 130GF 53 PTS645TL50 DPST TP1 2 TP4 TP5 TP6 TP13 TEST POINT PAD62H40 TP14 TP15 TP16 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 TP42 TP43 TP44 TP45 TP46 TP47 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP58 TP5
19. 25 tiam CMPCLK FSCLKN2 SDATANO GPIO24 1 11 CHPREQ LRCLKN SDATANI GPIO25 CMBDAT FSDATAN SPATANZ GPIO26 FSCLKIN STCCLK of lt gt SpaTANS GPIO27 1111 tm FLRCLKNI n 050 FSDATANI OSP Figure 13 Sheet 10 Configs 8415 CONFIG HORSX1 2 ADDRESS E lt sus 05 cm VK DAOO 929 DAO SCLKO L1 DAO LRCLKO 1 111 DAQ AUDATO 1 113 RAAR 18 Da AUDAT 1111 ty 24 MS0 2 5041 147 HORSX1 12C ADDRESS 89 AN TS G dx 8405 CS 8 11 R263 96 16 UDSP_AOUT2 161 UDSP_AOUTI 16 UDSP 014 161 UDSP_AOUT3 7 UDSP_AOUTE 7 UDSP_AOUT5S 7 UDSP_AOUTS t7 UDSP AQUT7 31 UDSP_AIN2 3 005 3 UDSP 31 UDSP AIN3 41 UDSP AING 141 UDSP_AINS 41 UDSP_AIN8 41 UDSP_AIN7 HDRI6X2 2MM ANALOG 1 0 92 SPARE2 1 SPARES SPAREO 29 SPARE MUIECIRLZ 5 MUTECTRU 16 7 MUTECTRLO lt BUCTRLO EX gt PP7MIC_WR 191 ADDRI7 255 SPARE4 150 iRQS 179 IRQS Bo 1101 INTREQFZABOOT 210 CSB415 INT 151 1 101 1 99 22o 18 101840 230 UHS2 CS OUT 12 101 16 7 101 439271 E 2 CS 101 25 1
20. 900 SELECT 588 900 549400 SDRAM 512K X 16 DIGITAL INPUT ooo DSP DSP AB rac BOOT BOOT MODE MODE ANALOG OUTPUTS CDB49400 0 DIGITAL OUTPUTS POWER AUX LT LT LT LT LT LT LT LT LtT LT LT LT LT TT LtT r3 5 15 15 GND AIO1 0000 POWER Preliminary Product Information This document contains information for a new product Cirrus Logic reserves the right to modify this product without notice CIRRUS LOGIC P O Box 17847 Austin Texas 78760 512 445 7222 FAX 512 445 7581 http www cirrus com MAR 02 Copyright Cirrus Logic Inc 2002 All Rights Reserved DS536DB1 1 CIRRUS LOGIC SS TABLE OF CONTENTS FEATURES 1 DESCRIPTION iasant 1 1 0016 5 ERN 4 2 HARDWARE 2 100161 kasaa ada 5 3 SOFTWARE OVERVIEW 5 2 Ta ra aeaaeae aaao t aaee Ce uaaa e a aaa Caa a Eiaeai Aeaaeai 7 4 AUDIO DATA AND CLOCK
21. Daughter card set for SPI mode Set the micro in Run Program mode 1 2 5 micro in Run mode JP2 RAE 2 3 Setthe micro in Program mode Select control mode for DSP ON CDB49400 controlled by Parallel port OFF CDB49400 controlled by RS232 port SW1 Note The RS232 control is not yet sup ported Select which debug port is accessed by the parallel DSPC debug port accessed by paral SW2 lel port OFF Reserved Table 9 Miscellaneous Jumper Switch Default Settings for UDSP Note gt Indicates default position 14 CIRRUS LOGIC APPENDIX A PCM_49400 BAT REM Version Name echo off echo INPUT RX1 to CDI echo ANA OUT PUTS AIO1 L AIO2 C AIO3 R AIO4 Ls AIOS Rs AIO6 Sb1 AIO7 Sbr AIO8 S UB echo DIG OUTPUTS TX1 L C TX2 R Ls TX3 Rs Sbl REM Set Environment variable for command line drivers call set_ini bat REM Reset all devices DSP and initialize debugger Mute DACs call board reset bat 901 2 REM Configure board for SPDIF IN Digital analog out call board spdif_ana_in_dig_ana_out bat 1 2 REM Load these images to DSPAB and DSPC 14014 release uld cos_6dot1_ab_494xx1_04 uld release uld spp_c_494xx1_01 uld 1 REM Configure DSPC REM Slave MCLK master SCLK LRCLK f nw output_al_c cfg ddspc 901 REM Set clock dividers for SCLK MCLK 4 and LRCLK SCLK 64 f nw mclkb4sclkb64_c cfg ddspc 1 REM Remap channels
22. The folder c udsp is recommended 2 Copy the contents of cs49400 directory to c cs49400 3 Edit your c autoexec bat file to include the path to the UDSP drivers This will allow you to use the drivers in any directory without specifying the path to the executables The following line should be added set PATH your_path PATH where your path the directory chosen in step 1 4 Again edit your c autoexec bat file to add the line set PATHzyour pathNCDB49400 ini where your CDB path is the folder chosen in step 2 For the folder c cs49400 cdb49400 this would read set uINI_PATH c cs49400 cdb49400 CDB49400 ini This will allow the drivers to locate the CDB49400 configuration file which contains information about the various devices on this board 5 For the previous few steps to have an effect on your computer for the drivers to be available in any DOS window in any location you will need to reboot it at this time The UDSP drivers have now been successfully installed The CDB49400 kit is now ready for use Several demonstration batch files bat are available in the CDB49400 Configs directory Please see the Quick Start on page 4 for information on the use of these batch files 24 CIRRUS LOGIC Installation on Microsoft Windows NT Windows 2000 and Windows XP and other protected Windows versions 1 Install the DLPortIO driver included with the CDB49400 driver kit Th
23. this message default value EXAMPLE urd d4940c p378 Notes _ If the associated INTREQ pin is not low when URD is executed the program will wait until INTREQ drops for DSP devices ONLY Press the Enter key to exit the read wait loop in this case URST exe Program used to perform hard reset or soft reset on the target device Usage urst dZZZZ mY s v d device ZZZZ device designator eg dspab dspc 8415a m communication mode Y mode designator i I2C s SPI n INTEL m MOTOROLA s Soft Reset p parallel port address XXX address in hex 278 378 or 3bc v enable verbose mode h this message default value U40LD exe Program used to load code onto a DSP Usage u40ld dspab input file uld dspc input file uld mY pXXX v m communication mode Y mode designator i I2C s SPI n INTEL m MOTOROLA p parallel port address XXX address in hex 278 0x378 or 0x3bc v disable verbose mode default value 22 CIRRUS LOGIC SetPLD exe Program used to read and write PLD registers Usage setpld r w RR DD Where r is to read from register RR w is to write data DD into register RR RR and DD are in hex 23 CIRRUS LOGIC APPENDIX F INSTALLATION OF BOARD CONTROL SOFTWARE The UDSP PC driver utility set comes in two versions The Direct Hardware version w
24. 29 J26 7 J26 8 DAO AUDAT4 to DAO AUDATA i J29 5 J26 10 DAO_AUDAT1 to DAO_AUDATB J26 9 J26 10 AUDATS5 to AUDATB J29 6 J26 12 DAO AUDAT 2 to AUDATC J26 11 J26 12 DAO AUDAT6 to AUDATC J29 7 J26 14 DAO AUDATS3 AUDATD J26 13 J26 14 DAO AUDAT7 to AUDATD Table 8 Miscellaneous Jumpers Note gt Indicates default position 13 CIRRUS LOGIC 8 DEFAULT JUMPER SETTINGS ON UDSP The UDSP board has many jumpers and switches All jumpers and switches applicable the CDB49400 daughter card are listed in the table below Do not move any switches or jumpers unless required for a specific application Jumper Purpose Position Function JP1 Enable Disable clock for the PLD 1 2 Clock for PLD 2 3 Disable Clock for PLD Select voltage level for chip selects 1 9 CS0 pulled up to 3 3 V 9 17 CSO pulled up to 2 5 V 2 10 CS1 pulled up to 3 3 V 10 18 51 pulled up to 2 5 V 3 11 CS2 pulled up to 3 3 V 11 19 CS2 pulled up to 2 5 V 4 12 53 pulled up to 3 3 V 12 20 CS3 pulled up to 2 5 V J40 5 13 CS4 pulled up to 3 3 V 13 21 CS4 pulled up to 2 5 V 6 14 CS5 pulled up to 3 3 V 14 22 CS5 pulled up to 2 5 V 7 15 CS6 pulled up to 3 3 V 15 23 CS6 pulled up to 2 5 V 8 16 CS7 pulled up to 3 3 V 16 24 CS7 pulled up to 2 5 V J44 Select communication mode for daughter card 1 2 Daughter card set for pc mode 2 3
25. 8245 10K 0130 FXR E jAwRe gu ADC LRCLK VE LRCK SDATA Hip C67 C138 C56 3 4 8 FRAME R265 2 1 0 xm 55360 5 uF gt e We 3 4 8 1 lt 13 681 c 00500014 18 10 5VA 100F 213 EU UDSP ELEC 7I R244 sox 3078 7 50 8240 J 4 WC330780 5 100K 2200pF Ratt 10K 8241 1o 77000 2 1 5 Figure 7 Sheet 4 ADC 2 TP33 5 R212 10K T NC33078D 525 TP37 ADOT 05 435 136 12 9 1010 2V MISO x 2 _ 05 12 5 6 7 9 0 11 81 2V_MISO_MOSI e 89 C 22V MOSI GND 81 2 5 6 7 9 10 10 2V MOSI lt 0 31 79 43 3V Rza A 1 8W 1 RB 10k 1 u2 Z z so gpovr 5 1 29 2V_SCK 12 6 7 8 910 11 845 05 2 00 5 ADI CDIN 52 4 02 RXP6 25 1801 SPDIF_RX1 en RXPO 2 amp RXNO H S 25 5VD 4 TV A VD 57 t t gt 3 3V AGND 8 21 134 6 7 8 0 SELT owe y OSC 11 5 0 11 tm SPOIF_McLK lt zz 10 Ruck 2 gt cse41s_inT
26. 962 REM This sets the SWCLK bit in the CS8415 to switch to osc when there is no SPDIF source 0180 48415 961 962 REM Set the source for the SPDIF SCLK LRCLK to the ADC SCLK LRCLK setpld w 0d 05 1 2 REM Set the source for the DAO_MCLK to 8415 setpld w 05 01 1 2 REM Set the direction of the DAO_MCLK as an output from the PLD setpld w 06 01 1 2 REM Set data source for the CDI Port to SPDIF and SLCK LRCLK to ADC setpld w 07 ca 901 962 REM Set data source for the DAI Port to ADC2 and SLCK LRCLK to ADC setpld w 08 da 1 962 REM Set 4392 in control port mode and sets power down bit 0530 d4392 1 962 REM Set 4392 in I2S mode 0190 d4392 1 962 17 gt CIRRUS LOGIC REM Set 4392 in control port mode and diables power down bit ucmd 0520 d4392 1 2 REM This sets I2S in the 8405 ucmd 0504 d8405a 1 2 REM This sets the Run bit in the 8405 0440 48405 961 962 18 CIRRUS LOGIC APPENDIX CDB49400 INI Horizontal Fields part I2Caddr SPIaddr SPI CSn reset bit to drop in PLD addr 0x01 INTREQ NUM Print Format ft Parallel word length Parallel CSn Type Vertical Fields board first non comment non blank line parts other lines note reset can only take on values 01 02 Default is CS4930 interface INTREQ NUM is the bit position within the INT register in the PLD Read_
27. C45 C47 C48 C86 C88 C89 C91 5 24 C94 C98 C99 C0805C103J5RAC 6 5 11 54 7 104 173 ECE V1VA100P PANASONIC CAP 10uF ELEC VA SERIES SMT 35V 20 C19 C26 C30 C41 C46 C49 C87 CAP 0 1uF ELEC VA SERIES SMT CASE B 50V 20 E 022 C93 ECE V1HAOR1R PANASONIC C1206C332J5GAC KEMET CAP 3300PF COG 1206 50V 5 C60 C62 C0805C220J5GAC KEMET CAP 22PF 0805 50V 5 C81 C82 C97 C110 C115 C117 CAP 10uF ELEC VA SERIES SMT CASE B 16V 20 C120 C121 C124 C126 C137 C142 C143 C152 C153 C154 C155 C164 C165 C170 C171 C175 C179 C182 C183 C192 C193 C194 C195 C204 C205 C210 C211 C213 C218 C223 10 40 C224 C227 C228 C239 ECE V1CA100R PANASONIC C102 C0805C820J5GAC KEMET CAP 82PF COG 0805 50V 595 65 C103 C1206C224J5RAC KEMET 0 22UF X7R 1206 50V 5 C106 C108 C111 C112 C114 CAP 10pF COG 0805 50V 5 C116 C127 C128 C133 C135 C136 C138 C229 C230 C237 13 16 C238 C0805C100J5GAC C107 C113 C125 C129 C131 CAP 2200PF 0805 50V 5 14 C134 C231 C236 C0805C222J5GAC KEMET C139 C141 C166 C168 C177 CAP 1uF ELEC VS SERIES SMT CASE A 50V 20 15 C181 C206 C208 ECE V1HS010SR PANASONIC C144 C147 C148 C151 C156 CAP 560PF 0805 50V 5 C159 C160 C163 C185 C186 C187 C191 C196 C199 C200 16 16 C203 C0805C561J5GAC C145 C146 C149 C150 C157 CAP 2700PF COG 1206 50V 5 C158 C161 C162 C184 C188 C189 C190 C197 C198 C201 17 16 C202 C1206C272J5GAC KEMET 18 8 5 058040508078 MaDi DIODES NC PANASONIC
28. FLASH MEMORY 512X8 2 HI SN74HC541DW TEXAS INST OCTAL BUFFERS AND LINE DRIVERS SO20 300 AT25F1024N 10SC SPI SERIAL EEPROM IM BIT SO8 150 0 1 U11 2 7 ATMEL 71 12 _____ 74 005 FAIRCHILD QUAD 2 INPUT POS NAND GATES SOIC 150 sun vi UI USUS URS U14 015 017 U18 019 U20 IC DUAL LOW NOISE OP AMP SO8 150 U21 U22 U23 U24 U25 U26 U28 U29 U40 MC33078D MOTOROLA IC 24 BIT 192KHZ STEREO DAC WITH VOLUME SEMICONDUC CONTROL TSSOP20 173 4 030 U31 U37 U41 CS4392 KZ U42 U43 U44 CS8405A CZ CIRRUS LOGIC IC S PDIF TRANSMITTER TSSOP27 173 CCL 6S CRYSTAL PARALLEL CUT 12 288MHZ 20PF HC49S 12 288C5XFC __ Lage PRNTED ORCUTT BOR m3 0 Universal DSP Development platform TSMD t Jis PHONO JACK i GND PHONO JACK RA A1012 GND PHONO JACK RA A1013 GND 322 PHONO JACK RA A1014 GND 324 PHONO JACK RA A1015 9 ND 426 PHONO JACK RA A1016 9 ND 128 TERMINAL BLUE 15 Power di 15VBUS TERMINAL BLACK GND 15vBus 132 TERMINAL GREEN 18v Power 134 TERMINAL RED 5v 1 136 DINSM 5 15VBUS 5 15VBUS GND GND 217 J36 1 2 Los 4 Los HEADER 3X2 GND FOR PHIHONG PS MICROCONTROLLER
29. Figure 13 Sheet 35 Figure 14 Sheet 11 UDSP 00 36 Figure 15 Sheet 12 Power Supplies Figure 16 Sheet 1 Universal DSP System Platform Figure 17 Sheet 2 Digital Audio Port annesso taa a ener Figure 18 Sheet 3 Headphone Amplifier 23 Figure 19 Sheet 4 4 42 Figure 20 Sheetb BI eens Figure 21 Sheet 6 Parallel Port Figure 22 Sheet 7 RS232 Interface Figure 23 Sheet 8 RS422 Interface seie EEEN EEE Figure 24 Sheet 9 S PDIF Receivers Transmitters Contacting Cirrus Logic Support For a complete listing of Direct Sales Distributor and Sales Representative contacts visit the Cirrus Logic web site at http www cirrus com corporate contacts sales cfm IMPORTANT NOTICE Preliminary product information describes products that are in production but for which full characterization data is not yet available Advance product information describes products that are in development and subject to deve
30. IMUN22TILTI 1 2 A c187 Ecoe 2700pr RST aoura ADO CS AOUTAs Hi SCL GCLK AMUTEC 0 uns e 1934 10uF 116 7 8 10 11sp_MCLK Suck H ELEC Ls ucssp7eo 8175 16 7 8103 DAO SCLK 8179 8177 s po 16 7 8 0 DAO_IRCLK LRCK m di D 560 18 1010A0 AUDATA SATA cuour Hf Sr 33v Mani 21 FLT Teer NE Sex 181 b va LZ ssva REC 2006 fe 78 7 16 15175 510175 2700 lt 8176 2 2 97 elec AGHO XIR 5 62K We 38 our ur 2563325 21297218 CS4392 KZ 2 tot c b MMUNZTHLTT 167 WUTECTRIS gt 1 2 R192 5 62k 15v0 C200 5609F c79 XIR XIR 2700 uF A 205 j 10uF IV vn 413 NELEC 2 5 62K 118K 2251 V R197 R195 204 13 2 7 AT a 560 tc 2 EX 5 62K 923 d 2563526 Wag 28336 6 711 MUTECTRLO gt R82 1 2 10K 5 62K ust E coc 2700pF ZV WRESET _ aoura Hg BE 3392 65 84 0 65 He 2v SK 8 150 AMUTEC ias 2v Most RE noure C194 1 px Huo ELEC LM R190 COHR 2 LEES NU coe ad 18 0 DAO AUDATB SDATA cuour H 1206 zl ne 16287 562
31. J27 1 2 High Boot mode select FHS1 2 3 Low J34 1 2 High Boot mode select FHS2 2 3 Low Table 3 Boot Mode Jumpers 11 CIRRUS LOGIC 7 3 Debug Port Interface Jumpers Jumper Position Function J10 1 2 using Debug Dongle J11 Select Debug Port Clock interface for DSPC 2 3 Debug using Parallel Port on UDSP J12 1 2 Debug using Debug Dongle on J11 Select Debug Port Data interface for DSPC 2 3 Debug using Parallel Port on UDSP Table 4 Debug Port Interface Jumpers 7 4 Communication Jumper Position Function 135 Connects the Rx SDA CDOUT pinto either the 2 1 2 SDA CDOUT SPI MISO bus SPI bus 2 3 SDA CDOUT pc SDA bus J36 Connects the Rx AD1 CDIN pin to the SPI bus 1 2 ADI CDIN SPI MOSI bus 2 3 ADI CDIN LO J3g Select the ADO Address Bit for 2 mode 58415 1 2 ADO HI 2 3 ADO LO J47 the ADO Address Bit for 2 mode CS8405 1 2 ADO HI 2 3 ADO LO Table 5 CS8415A S PDIF Receiver and CS8405 S PDIF Transmitter Communications Jumper Purpose Position Function Jg Select the ADO Address Bit for 2 54392 1 2 ADO HI 2 3 ADO LO Table 6 CS4392 DAC Communications 7 5 Serial Audio Jumper Purpose Position Function Selects LRCLK SCLK source for CS8405 U44 1 2 LRCLK DSP LRCLK see J
32. LED 5 3216 GREEN PANASONIC MOLEX MOLEX MOLEX 47 49 J10 J12 J13 J14 J15 J16 STAKE HEADER 3X1 0 1 CTR GOLD J17 J20 J24 J27 J30 J31 J34 24 19 J35 J36 J38 J47 TSW 07 103 G S SAMTEC TSW 105 07 G D SAMTEC STAKE HEADER 5X2 0 1 GOLD J11 J29 TSW 110 07 G S SAMTEC 10X1 0 1 GOLD 27 6 J18 J19 J21 J22 J23 J26 TSW 110 07 G D SAMTEC HEADER 10X2 0 1 CTR GOLD TSW 104 07 G D SAMTEC STAKE HEADER 4X2 0 1 CTR GOLD TSW 102 07 G D SAMTEC STAKE HEADER 2X2 0 1 CTR GOLD J32 J33 TSW 102 07 G S SAMTEC STAKE HEADER 2X1 0 1 CTR GOLD 111213 EXC ML45A910U PANASONIC FERRITE BEAD 1806 Q1 Q6 07 014 017 018 023 024 TRANSISTOR NPN EPITAXIAL TYPE SC59 32 2563326 TOSHIBA TSMD OV Q2 Q5 Q8 Q11 Q15 016 Q19 TRANSISTOR PNP SILICON SMT WITH MONO 3 Q22 MMUN2111LT1 LITHIC BIAS RES NET SOT23 MOTOROLA Q3 Q4 09 010 012 013 020 TRANSISTOR NPN SILICON TRANSISTOR WITH 4 21 MMUN2211LT1 MOTOROLA MONOLITHIC BIAS RES 0723 MMBT3904LT1 MOTOROLA TRANSISTOR NPN SOT23 36 6 R26 R28 R29 R32 R33 R34 CRCW08053301F DALE 100ppmDALERANSISTOR NPN SOT23 R1 R7 R8 R58 R59 R79 R80 RES 10K 0805 1 10W 1 100ppmDALE R81 R82 R83 R84 R85 R86 R87 R116 R121 R123 R124 R126 R127 R128 R136 R137 R138 R199 R201 R203 R204 R206 R211 R212 R213 R214 R216 R217 R232 R233 R234 R235 R236 R243 R244 R245 R246 R247 R248 R255 R256 R257 36 59 R259 R261 R262 R263 CRCWO08051002F R2 R3 R4 Re R11 R16 R17 R20 RES 100 OHM 0603 1 16W
33. any work for resale An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan An export license and or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPER TY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUIT ABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK Cirrus Logic Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks or service marks of their respective owners CIRRUS LOGIC 1 QUICK START A PC with an ECP parallel port an optical S PDIF data source and powered speakers are required to use the CDB49400 1 Install the drivers supplied with the board on the PC Refer to INSTALLATION OF BOARD CONTROL SOFTWARE
34. e SAMTEC_ HEADER OT INHDRTOXT weres SAWTEC HEADER WALE OTINHORBXT Br w SWH 807GT SAMTEC HEADERMALEGINHDRSXS ELECTRON STEREO HEADPHONE JACK 1 CON AD3056 50 ICS ELJ FA470KF PANASONIC INDUCTOR 47UH 1210 36 2 1 ESQT 116 03 G D 375 HEADER FEMALE 2MM SOK16X2 2MM to P2 P5 P6 ESQT 120 03 G D 375 SAMTEC HEADER FEMALE 2MM SOK20X2 2MM 38 1 5 107 03 G D 375 HEADER FEMALE 2 SOK7X2 2MM CONNECTOR D SHELL9 318 MOUNT P8 P7 745781 4 FEMALE 40 J Q1 55137 MOSFET 1 5 0723 1 5VT SOT23 RP1 R14 R27 E i 101 103 BOURNS SS R PACK9 10K 1 8W 2 SIP10 42 2 RP2 RP3 4606X 101 102 BOURNS RES R PACK5 1K 1 8W 2 SIP6 43 2 RP4 RP6 4606X 101 102 BOURNS RES R PACK5 1K 1 8W 2 SIP6 44 1 RP 4816P TO1 220 BOURNS RES R PACK8 221 8W 2 SO16N 45 4 RP7 RP8 R17 R38 4816P TO1 220 BOURNS RES R PACK8 22 1 8W 2 SO16N 46 4 R1 R5 R8 R69 ERJ 8GEYJ822 PANASONIC 5 THICK FILM 8 20 1 8W 5 1206 47 1 RA ERJ 8ENF75RO0 PANASONIC 5 THICK FILM 75 1 8W 5 1206 48 5 R3 R6 R9 R61 R70 ERJ 8ENF3740 PANASONIC RES THICK FILM 374 1 8W 1 1206 49 4 R4 R7 R10 R71 ERJ 8ENF93R1 PANASONIC RES THICK FILM 93 1 1 8W 1 1206 R11 R12 R13 R26 R65 ERJ 8GEYJ472 PANASONIC
35. memory that can be interfaced to CS49400 SRAM SDRAM and FLASH SDRAM and SRAM can be used for additional X data memory on DSPC Use of external SDRAM or SRAM 1 application dependent Please refer to the relevant application code documentation to determine if external memory is required FLASH is used to store application code images for both DSPAB and DSPC The following sections describe these memory types in more detail 6 1 SDRAM U8 The CDB49400 board includes a 16 MBIT IM X 16 bit of 100 MHz SDRAM connected to the glueless SDRAM interface of the CS49400 SDRAM is memory mapped into the internal X memory space and runs at DSP core speed The SDRAM interface shares the same address and data pins as the SRAM and FLASH interface but has separate control pins Although the CS49400 can support using all 3 memories in a given design a typical application would include SDRAM and FLASH or SRAM and FLASH 10 6 2 SRAM 05 The CDB49400 board includes 4 MBits 512K X 8 of SRAM connected to the external memory interface of the CS49400 Like SDRAM SRAM is memory mapped into the external X memory space Please see the CS49400 data sheet for detailed SRAM timing information Both FLASH and SRAM use the same external memory interface on the CS49400 The CDB49400 uses address bit 19 of the CS49400 external address bus to map FLASH into the lower half of the external memory space and SRAM into the upper half of the external memory spa
36. tious vany ova Si B 8E m 5 1008 03814 5 Sa g3 85 gen 2 x gu 1 on 0910317090 omn d 2520252 odzo 810109 0880 wiOldo GSHn 0 BEES 8 55220252 22 222025 gt 282 808980828285 i 25 02 4 LISIINA il ore z e ever Qro L 43534 650 gt IWON o1vanv ova 5252 55 lt gt 1083 gt ow 10 6 ZV1VOH 180035 101 61 irr toren wivon ssl 025 4528 NY1V0S 3 1 1 13315 1254117011 won ae I SQ uM tore 7 1 0 161 tole 205 63 E 21 E zos 2 wl 1 aiz 309E zun 992 0095 s e 0 a n bad 7 25 02 401070 253 19 z 1 aa wT T rh 3 gg 88 4 SIE MLAZ MOK MEK BOXER LXE mosverm oX3 Sezo _ ep ovo std ees isa seo Leap ze e b UA Wu AST 250 70861 26 14 fe 433v
37. 0 8415 CS lt fat 230 cs th 12 5 6 7 8 9 101 Dy 339 565 1 103 2 5 6 7 9401 2V_Mosi lt 21 051 339 2V MISO 12 5 9 101 5V MOS 390 HDR20X2 2MM CONTROL1 1 DSP RESET lt 4 2V DSPi 1o 2V Dsp2 V WEPSET 2V MRESET 5V_MRESET gt 2V_MRESET 1 3 4 5 6 7 8 10 10 2V DBDA 101 2 29 2V_DBCK2 EMADO 119 9 EMADO EMAD EMADI 1 91 81 EMAD2 150 0 9 91 EMAD4 FMADA 150 5191 191 EMADG EMADE 10 MADT 7191 181 Pei 189 EXTMEM thol 15VD 4 250 gt 15VD 250 15VD 4 270 gt 15VD 1 310 2 5 4 359 gt 2 5V 3 3V 350 gt 3 3V 45VD 4 390 gt 5 0 HDR20X2 2MM CONTROL2 POWER 3 4 8 3 4 8 5 5 4 8 15 81 5 SPDIF_RX3 8 SPDIF_TX1 8 SPDIF_TX3 SPDIF_RX1 1101 CMPCLK FSCLKN2 lt 1 101 1 101 11 6 7 1 103 1101 1 10 1 101 11 101 1 101 101 8 101 CMPREQ LRCLKN FSCLKIN STCCLK lt FLRCLKNI DSP_MCLK DAO_SCLKO DAO_LRCLKO lt 11101 DAO_AUDAT1 1101 DAO_SCLK1 DAO_LRCLK1 lt 1 10 DAO_AUDATS 1 10 DAO_AUDAT7 1 10 SDATAN2 GPIO26 ADC_MCLK ADC_LRCLK 500071 ADC 500075 SPDIF _MCLK SPDIF SCLK lt SPDIF SDOUT 3 4 ADC_DIFO 3 41 ADC_DIF1 1 Figure 14 Sheet 11 UDSP Interface SPDIF_RX2 5 SPDIF_
38. 00 150_ 111 Rad M 1 SD_ADDRIO EXTAIO 1 EXIAIO 25 1000 vss 26 EXTAT 100 150 ADOR7 EXTA7 11 R45 R30 SD ADDRO EXTAO 100 SDRAM EXIAR 100 Sb ADORS EXTAS 0 R27 tn S0 ADDRI EXTA 100 EXTAL EXTA 100 Sb ADORS EXTAS ti 874 R25 SD ADDR2 EXTA2 1 100 EXT EXTAA 100 Sb ADORA EXTAA 111 873 100 KM416S11200T GF8 512K X 16 m EXTAT EXTAZ EXTAS EXTAA EXTAS EXTAS EXTAT EXTAB EXTAS EXTATI EXTAIZ EXTAIS EXTA EXTAIS EXTAIS EXTAT EXTAIB 101 EXTAIS SD 3 C89 XIR 2190 ELEC C86 XIR 31687 ELEC NCB NCO NCI NC2 7 1 00 n 9 1 02 lato 1 03 1 04 2 1 05 1 06 1 07 16 Nes A18 NCS un NCB GND t GND SRAM CY7CIO49BV33 122C 512K 112 101 NV_OE GPIO1S 01 2 101 NV_CS GPION4 74ACO0SC 74ACO4SC 112 10 NV_WE GPIOI6 92 ELEC Qr T0 01uF EXTDO EXTDS EXTA EXTDS EXTDS 16 GND FLASH AT29LVO40A 20TC 512K X 8 0 240 NV OEJ GPIO1S 74ACO4SC 74 005 11201 NV_CS GP1014 74ACO4
39. 12 288 Mhz oscillator The ADC is set to master SCLK and LRCLK for the input ports Data from the ADC is routed to the DAI port The S PDIF receiver slaves to SCLK and LRCLK generated by the ADC and sends data to the CDI port of the DSP MCLK is also routed to the DSP The DSP slaves to MCLK from the S PDIF receiver and masters SCLK and LRCLK for the output ports Data routed to the DACs and S PDIF transmitters is selected by jumpers J26 and J29 The digital data is output on RX1 RX2 RX3 and RXA optical connector For RX4 to transmit data DSP must be configured to be a S PDIF transmitter Analog data is output on AIO to AIOS RCA connectors with the following mapping e AIOI Left e AIO2 Center e AIO3 Right e AIO4 Left Surround e AIO5 Right Surround e AIO6 Left Surround Back e AIO7 Right Surround Back e AIO8 Sub woofer The batch file configures the S PDIF receiver DACs and the S PDIF transmitter for I2S data format Please refer to the CS8415A CS4392 and CS8405A data sheets for more info on configuring these devices The batch file use the drivers documented in BOARD CONTROL SOFTWARE on page 21 CIRRUS LOGIC 5 BOOT MODES AND DEBUG PORT The CS49400 has 4 possible boot modes which are selected by appropriately strapping the FHS 2 0 and UHS 2 0 mode select pins Jumper settings for the various boot modes are documented in Table 1 on page 11 and Table 2 on page 11
40. 16 101 DAO_AUDATA L SDIN TCBL SM CS8405A CS 1035 1 8 1x 045 22 Hsos coovr scL ccu k 28 2V SCK 12 5 6 7 8 9 0 11 18 10 11 8405 CS 2400 65 ADI COIN 122 2V MOSI_GND 51 02 TXP Sebir TX2 111 5 810 RXI 28 4 3 06v02 H S 21 5VD lt 7 02 VD 77 P 3 3V 00804 2 1 Lu 003 1 DSP_MCLK 1 6 7 8 10 10 11 3 4 5 6 7 8 10 111 ZV MRESETL RST TP28 Ld Pci int Hg TP43 Tyce nes 8 al 6 7 8 10 DAO_LRCLK nea HE 6 7 810 DAO_SCLK 13 isctk nes HE 16 01 DAO_AUDATB ISDIN TCBL A CS8405A CS eu 1 8W 1 u44 zn Hspa cpout scL cc k 28 12V SCK 12 5 6 7 8 9 10 1 8 0 1 8405 CS 2400 65 ADI CDIN 02 TXP SPDIF _TX3 111 5 8 11 SPDIF_RX1 E 2 H S 450 8 2 vor 23 3 3 DGND4 2 4 0220 0003 7 1 3 4 5 6 7 8 10 11 2V 10 RST 19 t Ts NC1 INT Tyce nes 8 Hes ds 925 14 150 TCBL H 14 2 3 osp_weik 067 840 fo ADC MCLK 3 4 8 111 16 7 8 103 DAO_LRCLK 2 10 E 58405 5 8206 228204 ELA 3 4 1 LRCLK io Vw 2 2 678401 DA 9 99 BET E i ADCLSCLK oo 1 HDR4X2 203 J8 E MCLK 7 0 AUDATC 9 19 23 10 ADC sDoUT 9 3 apc spout 22 39 4 ADC SDOUTS 431 0 00014 9 90 Figure 11 Sheet 8 S PDI
41. 196 200ppm R21 R22 R23 R24 R25 R27 R30 R31 R41 R42 R43 R44 R45 R46 36 TSMD R47 R48 R51 R53 R60 R61 R62 R63 R68 R70 R71 R72 R73 R74 CRCW06031000F DALE 1 CRCW08053011F DALE RES 3 01K 0805 1 10W 1 100ppm 39 3 R9 R15 R18 CRCWO080522R1F DALE RES 22 1 OHMS 0805 1 10W 1 100ppm R10 R55 R131 R133 R239 R240 RES 100K 0805 1 10W 1 100ppm 0 R251 R252 CRCW08051003F DALE 17 R12 R13 R14 R35 R37 R39 R40 RES 0 0805 1 10W 41 R64 R65 R66 R67 R69 R200 R210 R215 R231 R260 CRCWO805000FT R19 R56 R57 R125 R129 R130 RES 150 OHMS 0805 1 10W 1 100ppm R134 R135 R237 R238 R241 42 16 R242 R249 R250 R253 R254 CRCWO08051500F DALE R36 R264 R265 R266 CRCW12062R0J DALE RES 2 OHMS 1206 1 8W 5 300ppm 44 5 R38 R75 R76 R77 R78 DALE RES TBD 0805 1 8W 1 100ppm 45 2 R49 R50 CRCW08051401FT DALE RES 1 4K 0805 1 10W 1 100ppm 46 4 R52 R182 R202 R205 CRCWO08051240F DALE RES 124 OHMS 0805 1 10W 196 100ppm 47 1 CRCW12063300F DALE RES 330 1206 1 10W 1 100ppm Lv Qty Reference Reference PartNumber Number Descipin R117 R120 R122 R140 R207 Menvfactwrer 20 0K 0805 1 10W 1 100ppm R208 R209 CRCW08052002F DALE R118 R119 R142 R143 R146 RES 5 62K 0805 1 10W 1 100ppm R148 R149 R151 R154 R155 R156 R157 R160 R162 R163 R165 R168 R171 R173 R174 R176 R179 R180 R181 R185 R186 R189 R191 R192 R194 R197 R198 CRCW08055621F _ CRCWO0805473 DALE RES 47K 0805 1 8W 596 200ppm a R139 CRCW0603
42. 2002F DALE RES 20 0K 0603 1 16W 196 200ppm RMi 1206511 DALE RES 510 1206 1 8W 5 200ppm a OR R145 R152 R153 R158 RES 1 18K 0805 1 10W 1 100ppm R159 R166 R167 R169 R170 R177 R178 R187 R188 R195 16 R196 CRCW08051181F R147 R150 R161 R164 R172 RES 560 0805 1 10W 1 100ppm 54 R175 R190 R193 CRCWO08055600F DALE TSMD Bs i DALE RES TK 0805 IOW 1 100ppm RES 604 OHMS 0805 110W 1 10 5r 1 me f DALE RES 43 2K 0805 110W 1 100 58 TP1 2 TP5 TP6 7 TP8 062 PAD 042 HOLE NO POP TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP17 TP18 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP31 TP32 TP33 TP34 TP36 TP37 TP38 TP39 TP40 TP42 TP43 TP44 TP45 TP46 TP47 TP48 TP49 SOCKET QFP PROTOTYPING SMT SOCKET WITH 1 149 144 145 55 YAMAICHI POS SOLDER 058415672 CZ CIRRUS LOGIC LOGIC S PDIF RECEIVER 550 28 173 S PDIF RECEIVER TSSOP28 173 CX21AF 12 2880MHZ CRYSTAL E OSCILLATOR 12 288MHZ FULL SIZE CASE 63 1 UA 74AC04SC FAIRCHILD IC HEX INVERTERS SOIC 150 4 1 KM416S1120DT GF8 SAMSUNG SDRAM 512K X 16 TSOP 50 ov AT24C128N 10SC ATMEL IC 2 WIRE SERIAL EEPROM 128K SO8 150 IC 24 BIT STEREO ADC CONVERTER FOR DIGITAL SEMICONDUC AUDIO SSOP20 209 4 U7 U16 U27 U32 CS5360 KS CY7C1049BV33 12ZC CYPRESS SRAM 512X8 TSOP AT29LV040A 20TC ATMEL IC
43. 26 12 TP24 TPIS TP23 TP42 TPIS label as grounds C57 X7R 5VD EL Tee 7590 A A A 36 c20 31658 058 054 C101 C104 R54 R49 XIR R50 uF 47uF 330 uF 10uF 1 4K 10uF 1 4K E 2 a 020 Uh EXC ML45A910U 4173 X7R ELEC C59 Te Figure 15 Sheet 12 Power Supplies 43 3V 2 5V alen ELEC 10uF R52 124 Ny GREEN lt 012 R182 124 aW GREEN 09 025 1 E MMBT3904 R184 JIDOT SNAAID TSMD C96 C100 C101 C105 C109 C118 C119 C122 C123 C130 C132 C140 C167 C169 C172 C174 C176 C178 C180 C207 C209 C212 C214 C215 C216 amp APPENDIX H BILL OF MATERIALS CDB49400 C217 C219 C220 C221 C222 C225 C226 C232 C234 C235 3 C240 C0805C104K5RAC C0805C473J5RAC KEMET CAP 0 047UF X7R 0805 50V 595 4 9 13 14 15 0 1UF 7 0805 50V 10 16 18 C20 C22 C23 C24 C27 C31 C32 C35 C36 C37 C39 C42 C50 C52 C55 C56 C57 C58 C59 C61 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C74 C75 C76 C77 C78 C79 C80 C83 C84 C85 85 Ho C3 C38 C51 C233 C241 ECE V1VA470WP PANASONIC 47uF ELEC VS SERIES SMT CASE D 35V 20 1 5 C1206C222J5GAC KEMET CAP 2200 COG 1206 50V 5 C6 C7 C8 C12 C17 C21 C25 CAP 0 01UF X7R 0805 50V 5 C28 C29 C33 C34 C40 C43 C44
44. 26 J29 J25 3 4 ADC LRCLK 5 6 SCLK DSP LRCLK see J26 J29 7 8 SCLK ADC SCLK J28 Selects MCLK source for CS8405 U44 1 2 MCLK DSP MCLK 3 4 ADC MCLK Selects Data source for CS8405 U44 1 2 SDIN DSP DAO see J26 J29 3 4 SDIN ADC SDOUT1 J8 5 6 SDIN ADC SDOUT2 7 8 SDIN ADC SDOUT3 9 10 SDIN ADC SDOUT4 12 Table 7 CS8405 Clocks Data Input CIRRUS LOGIC 7 6 Other Settings Jumper Position Function Select CLKIN XTAL1 input to the DSP 1 2 External 12 288 OSC to CLKIN J30 2 3 12 288 XTAL to XTAL1 Note J33 must be installed if XTAL1 is used J33 Connect XTALO to an external oscillator 1 2 12 288 XTAL to XTALO Note J30 2 3 must be installed if XTALO is used J31 clock source for DSP 1 2 DSP uses external 12 288 MHz clock 2 3 DSP uses internal PLL 424 Select 3 3V 2 5V power supply for DSP 1 2 3 3V for DSP I O 2 3 2 5V for DSP I O 432 core current 1 2 Use DMM to measure current J7 Setthe ADC to Master Slave SCLK and LRCLK 1 2 ADC slaves to SCLK and LRCLK 2 3 ADC masters SCLK and LRCLK Select the Data Clock source to the CS4392 and J29 2 J26 4 0 SCLKO to DAO_SCLK CS8405 J26 3 J26 4 DAO SCLK1 to SCLK J29 3 J26 6 DAO LRCLKO to LRCLK J26 5 J26 6 DAO LRCLK1 to LRCLK J29 4 J26 8 DAO AUDATO to AUDATA 126
45. 4014 command This command follows the Host Boot Procedure described in the CS49400 datasheet Once code has been downloaded to both DSPAB and DSPC DSPC is configured and kickstarted first Next DSPAB is configured and kickstarted RUN SET_INI BAT RUN RESET BAT SPDIF_ANA_IN_DIG_ANA_OUT BAT RUN U40LD EXE SEND HW SW CONFIG MSG TO DSPC KICKSTART DSPC SEND HW SW CONFIG MSG TO DSPAB KICKSTART DSPAB STOP Figure 2 Software Overview CIRRUS LOGIC 4 AUDIO DATA AND CLOCK ROUTING The audio data and clocks are routed via the PLD The PLD configuration file has been included in SPDIF_ANA_IN_DIG_ANA_OUT BAT page 17 describes how the PLD is set up Depending on the application the appropriate board config batch file needs be called from the main batch file The following commonly used batch file is included with the kit Please contact your FAE for additional batch files if necessary 41 SPDIF ANA IN DIG ANA OUT BAT This batch file configures the board to accept digital data from the RX1 optical connector and analog data on AIOI1 and AIOI2 RCA connectors The clock and data routing is shown in Figure 3 Sample Data Clock Routing on page 9 Few of the signals are routed via the UDSP PLD The S PDIF receiver accepts digital data from RX1 and recovers MCLK for the system If a stream is not present the S PDIF receiver switches to the local
46. 9 10K 5 150 R55 4 330780 s 252 100K 8232 2200pF R56 150 15v0 330780 22 5 13 8 P R233 10K 10uF 8120 EN UDSP_AINS ze R137 qus 4 330780 2200pF v R134 7009 500 5 13 411 ADC_DIFO 0 5 R200 3 41 DIF1 S 5VA 45VA A 027 E 0 1 iro HPDEFEAT 19 7 ous 11 3 4 8 6 7 8 10 19 EE ove 8 deu Toms s ft TRS As 102 1467 tue 00005 jour 672 500 7 4 155 MIT ELEC R128 Tw TU E 2 3 4 8 11 FRAME 206 CS5360 KS lt 2 ADC MCLK 4 81 6 ADC SCLK 13 4 8 11 SS 56002 Uii y c126 139 111 UDSP_AIN4 T lu26 3 1 R127 6 MC33078 3 05 150 4 MC330780 5 p2 gt 0129 2200 R235 RISO 150 d 2 a uCS30780 1928 IP29 5 p25 2 R234 10K Figure 6 Sheet 3 ADC 1 ADC_MCLK 3 4 ADOT 6 wm BR 62 15VD 15VD C238 0232 11 lOuf 239 8209
47. 9 TP60 TP61 TP65 TP66 TP67 TP68 TP69 67 78 TP70 TP71 TP72 T NONE NONE FEN T1 T2 67129600 SCHOTT TRANSFORMER TH 7ACTOSC 74ACTOBSC ZI IC QUAD GATE 50141 AND GATE SO14N 02 010 SN74LVC541ADW _ OCTAL BUFFER SO20 300 251 6401 6 MICROCHIP EEPROM SERIAL SPI 8KX8 SO8N 241 1281 5 MICROCHIP EEPROM I2C SERIAL 16KX8 SO8N TSMD 99 IC OSCILLATOR 12 2880MHZ 50PPM 1 U5 CX21AF 12 2880MHZ CAL CRYSTAL OSC14 8134 5 2 SOCKET POP INSM IC VOLTAGE DETECTOR OD 4 4 4 7V 1 U6 MN13821T PANASONIC 5 59 8 MOSSHCSUSGPGZCFB MOTOROLA MICROCONTROLLER 2 ALTERA CCONFGEEPROMPLCOED 000 z 8 QUAD BUFFER W 3 STATE 5014750 3 SNAHCISHDW CD LOPTRFSTATE 602200 e 1 5 mero ICFLASHSTKXSTSUNSSEPLOO 1 Ut MAXESZCWE WAM TRANSCEIVER 50164 Bb 1 Um MWARCISHAD FAIRCHILD IC BUFFER OCTAL 5020300 85 1 U9 j LM39401T 3 3 NATIONAL SEMI IC VREG POSITIVE 3 3V TO220AB 86 1 LT2937ET 2 5 LINEAR TECH IC VREG POSITIVE 2 5V TO220AB U21 87 1 LM4811MM NATIONAL SEMI HEADPHONE AMPLIFIER MSOP 8 IC RS422 DIFFERENTIAL LINE DRIVER 8 1 U22 DS8922M NATIONAL SEMI SO16 240 BI DIR OCTAL BUFFER TRI STATE 1 U23 TC74VHC245FT TOSHIBA TS
48. 91 FDATG FGPIOG 1 91 FDAT7 FGPIO7 1 91 2 150 CASE R 027 150 5 0 8 02 SD CLK EN 127 SD WERK R 121 150 R 2 150 00 1 8 02 1580 0158 1 150 657 2 EXTDO 21 ExTDI 21 EXTD2 t2 EXTDS 21 21 EXTDS 21 6 21 EXTO7 21 4587 5360 CONFIG a HORSX1 1 gg ExT osc m stave VV ovri 3 L2 rm OK CLKSEL Sank 8 2 R132 E 1 m s 1 1 39 12C ADDRESS umo DAO SCLK 16 781 59 9 89 DAO LRCLK 16 78 5 2 16 83 GIAO 439255 DAOTAUDATS 9 39 DAQ AUDATB 6 83 R267 10K tn DAO AUDATE 9 00 DAOTAUDATC 7 81 0 DAD AUDAT7 9 89 DAOAUDATDL7 IH 16 7 8 10 11 05 5 k 2v mosi gt gt 3 19 2V_sck 50 1 111 INTREOF7ABOOTF JHDATAO 11 91 0 9 SCDIN C a JHOATAY 019 D a JHDATA2 191 tg scoour i JHOATAS 181 119 WR DSE pi JHDATAS 1191 118 i T JHDATAS 181 tin COR 82 8 JUDATAB r8 BE 804147 83 p GREEN 2 2 R202 R205 124 124 122 1 21 112 o f GPlo15 501 022 ttam 112 NV CSJ GPIOI4 39 64
49. AIOI L AIO2 C AIO3 R AIO4 Ls AIOS Rs AIO6 Sbl AIO7 Sbr AIO8 SUB f nw mode011_c cfg ddspc 901 REM Kickstart for DSPC ucmd f sw ks_c cfg ddspc 1 REM DSPC Configured and running REM Configure DSPAB REM Set CDI port for PCM f nw inputa2 cfg ddspab 901 REM Enable PCM Decoding ucmd f sw pcm_ab cfg ddspab 1 REM Set PLL for 75 MHz f nw pll75_ab cfg ddspab 1 REM Kickstart DSPAB with the PLL Enabled ucmd f sw ks_pll_ab cfg ddspab 1 REM DSPAB Configured and running 15 16 CIRRUS LOGIC REM Unmute the DACs setpld w 02 00 1 echo on CIRRUS LOGIC APPENDIX B SPDIF_ANA_IN_DIG_ANA_OUT BAT ECHO OFF REM Version Name echo Configuring Peripherals REM Set up the Board for Compressed Analog In Analog Digital Out REM Inputs CDI RX1 REM Inputs DAI 11 amp AIO12 REM Outputs ANALOG AIO 1 8 REM Outputs DIGITAL TX 1 4 REM Data format to from DSP I2S 24 Bit REM Clocks SDIF RCVR generates MCLK REM ADC masters SCLK and LRCLK for the SPDIF RCVR DAI and CDI port REMDSP Slaves to MCLK and masters SCLK and LRCLK on DAO REM Set the clock source for ADC to SPDIF from DC and set MCLK as an output setpld w 09 1 2 REM set the 8415 in slave mode and the output format to to I2S 16 bit 0604 48415 1 962 REM This sets the Run bit in the CS8415 0440 d8415a 1
50. AP_SDOUT4 B 13 14 DAP SDOUT5 B 15 16 500016 80117 18 DAP 50017 B 19 20 U18 DAP SDOUT8 B pa 4 DAP SDINI4 1 DAP SDIN1 R52 33 DAP SDINi B 15 52 R53 DAP_SDIN2_B N DAP SDINS 2A DAP_SDINS_B 2292 2028 R85 P DAP_SDIN4_B a 31 32 OE 1 2 3 4 DIGITAL AUDIO PORT lt Q 74 125 40 0 1uf Figure 17 Sheet 2 Digital Audio Port pg 1 10 1 U21 VIN1 VOUT1 VIN2 VOUT2 BYPASS CLOCK VDD SHUTDWN UP DWN GND C80 1 J51 100uf 16 C82 100uf 16 8 4 8 1 10 2 vec JF 14150 5VD c81 JF 2 R65 1uf 50 8 4 Tk HEADER 10x2 6 52 5VD R82 R83 10k 10k 024 2 gt St GND ENCODER GI LM4811 Figure 18 Sheet 3 Headphone Amplifier TE OEE 4 3 GND HEADPHONE JACK ADOT 50112 9t SMR a Hus qui
51. ATICS on page 26 The CS49400 has 3 cores in it The decoder core is referred to as DSPAB and the postprocessor is referred to as DSPC Both DSPs can be booted from a PC via a parallel port They can be configured to communicate via SPI or serial interfaces or Motorola Intel parallel interfaces However all the other devices on the board are configured in SPI mode as this is the default configuration of the CDB49400 As seen in Audio Data Clock Routing on page 6 the Compressed Data Input CDI Digital Audio Input DAI and Serial Audio Input inputs of the DSP are connected to the PLD The output of the ADC and S PDIF receiver are connected to the PLD The PLD on the UDSP can be configured to route clocks data from the ADC S PDIF receiver to any input port on the DSP Configuration files for the PLD are supplied for common clocking and data delivery schemes Custom configuration files for data delivery are available on request Four DAC and three S PDIF transmitters are connected to the Digital Audio Output DAO ports of the DSP Data sent to these output devices are selected by jumpers J26 and J29 Three types of memory are available On the CDB49400 SDRAM and SRAM are available for use by applications with any special processing needs FLASH is available to store application code and boot the DSP in a Host Controlled Boot operation Details of the External memory interface will be discussed in Externa
52. Both DSPAB and DSPC must have the same host interface mode Currently the board is configured for SPI host boot and SPI control on both DSPAB and DSPC Please contact the factory if additional boot or control modes are required Other audio devices such as the CS8415A CS8405A and the CS4392 are configured for SPI control and their SPI device addresses are set in the CDB49400 ini file Please see the CS49400 data sheet for further information on the various supported boot and control modes 5 1 Debug Port for DSPC The command line debugger for DSPC is called CID and uses the parallel port interface on the CDB49400 CID is included as part of the software development kit CD ROM Please refer to the documentation in the Software User manual for details on how to use CID DIGITAL RX1 esses SPDIF INPUT 4 RCVR COMPRESSED CS8405 SPDIF TMTR CS8405 SPDIF gt TTR AUDIO PORT sELECT 4 58405 3 SPDIF DIGITAL OUTPUT o o OOOOOOOOO OOOOOOOOO DATA c 5 e N CS4392 M EN DAC Q CS4392 o DAC CS4392 5 11 11 7 CS4392 ule ANALOG OUTPUT Figure 3 Sample Data Clock Routing CIRRUS LOGIC 6 EXTERNAL MEMORY INTERFACE The CDB49400 supports all 3 types of
53. E OVERVIEW The CDB49400 board is designed to allow the user to fully evaluate the CS49400 user programmable audio DSP As seen in block diagram on page 1 the CDB49400 board consists of daughter card plugged into a mother board The mother board referred to as the UDSP has a microcontroller Programmable Logic Device PLD power conditioning input output connectors jumpers switches and many other circuits as seen in UDSP SCHEMATICS on page 43 The microcontroller enables the board to run in stand alone mode and control all the devices on the mother board as well as daughter card The PLD has number of multiplexers which enable the data clocks and control logic to be routed to the DSP in a number of combinations The PLD is controlled by the microcontroller if SW1 is in the OFF position or by the parallel port if SW1 is in the ON default position Input output connectors enable digital or analog data to be sent to from the daughter card Switches enable the microcontroller to perform various operations in standalone mode Currently the standalone features of the board are not supported and a PC must be used to communicate with the board The UDSP has many devices and connectors that are not used for the CDB49400 board The daughter card that plugs into the UDSP has a CS49400 DSP four CS5360 ADCs one CS8415A S PDIF Receiver three CS8405A S PDIF Trans mitters four CS4392 DACs SRAM SDRAM and Flash as seen in CDB49400 SCHEM
54. ERAMIC 100V 10 7 1206 CERAMIC 22PF 100V 5 COG 1206 e CRESS C57 CBEST C1206C10SM4FAG KEMET CAP CERAMIC TUF TV20 1205 5 cat 056 057 058 59 ECE VICATOOSR_ PANASONIC ELECT AL 10UF 16V 20 SM Se A e ELECT AL 100UF T6V 20 SM D 055045 C45 ELECT AL 10UF 16V 20 SMB ELECT AL 10UF 16V 20 SM B LE EIEE VS SERIES SM CASE 1uF ELEC VS SERIES SMT CASE A C79 C81 C84 ECE V1HS010SR PANASONIC 50V 20 DIDi2 D12 LN1251C TR PANASONIC LED RED DIFF 10MA SM Ee 07 09 011 013 014 015 016 LED GREEN DIFF 10MA SM 017 018 019 020 021 LN1351C TR PANASONIC 6845 35 8 esea TSWHUSUTGS SAMTEG HERDERMALEQTINHDRSXI wooren READER MALE 0 1 STAKE HEADER 16X2 T CENTER 8 4 erma TOSHIBA OPTICAL TRANSMITTER J3 45 J9 J13 J15 J16 J17 J18 J19 PHONO JACK RA GOLD J20 J21 J22 J23 J24 J25 J26 J27 J29 J31 J33 J50 ARJ2018 A D ELECT 111 0110 001 E FJOHNSON BINDING POST BLUE BPOST 111 0103 001 E FJOHNSON BINDING POST BLACK BPOST TSMD 111 0104 001 E FJOHNSON BINDING POST GREEN BPOST 24 1 111 0102 001 E FJOHNSON BINDING POST RED BPOST 1 1 5 X 25 TIN X 25 SQUIRES m o JX32 JX34 TIN TYPE E p 55550 __ ae SAWES HENCERWAERTNHORSE wooren SAMEC READER MALE 0 1 NHOREX m 31
55. F XCVR R77 TBD 2 T ADC MCLK R78 TBD 2 11 6 7 8 0 11 3 4 8 11 vt 1 101 11101 11101 1 101 1 10 1 101 11101 1 101 FDAT7 FGPIO7 FDAT6 FGPIO6 FDAT5 FGPIOS FDATA FGPIOA FDAT3 FGPIO3 FDAT2 FGPIO2 FDATI FGPIO1 1 101 1 101 1 10 11 101 1 101 11 101 1 101 1 101 R40 0 1 101 SCDOUT R64 0 11 102 FHS2 FSCDIO lt gt gt 2V_MISO 12 5 10 11 R65 1 103 SCCLK 2 R66 01 10 FAO FSCCLK lt AAA 2V_SCK 12 5 6 7 8 9 10 111 t1 101 SCDIN a nnn R69 01 10 FAT FSCDIN CO 04 2V_MOSI 12 5 5 7 9 10 111 R2 22 NWN NNN NNN FDATO FGPIO0 4 5 NA N 3 22 HDATA7 lt gt EMAD7 11 ANN S 11 5 ANN SEMADS 11 HDATA4 ANN SEMAD4 11 HDATA3 SEMAD3 11 HDATA2 EMAD2 11 NNN S EMADI 111 HDATAO EMADO 111 R12 1 10 FHS0 FWR FDS 0 R13 0 PP MIC WR 111 11 10 WR OS m 0 1 10 FHSI FRD FR W R35 0 PP_MIC_RD RW 1111 01 101 RD RW R37 0 m 6 0138 CO ANN lt gt 2V SCK 2 5 6 7 8 9 10 111 R39 0 E 1 1012 lt AA 2V MOSI 12 5 6 7 9 10 11 PARALLEL PORT MODE 2V_SCK AO IN PP MODE 2V MOSI 1 IN MODE 3 3V 14 x7R U4 A 74ACO4SC Figure 12 Sheet 9 Buffers ADOT SND 96
56. P2 DAL SOIN DIF i 0 a Apc DIF 1 0 DSP2 DAO MCLK PAO SCK UC HACK DSPZ SCLK DC sc DSP2 RCLK DSP2 SDOUTIA 1 MICRO SPDIF vo 5 2502 90 SPDIF TX SPDIF SPDIF TXS RX1 X4 SPOIF_RX2 SPDIF RS422 BUFFER Ql 3422 RS422 RS422_CLK2 RS422 HEADPHONE Alo 10 1 46 304 HEADPHONE DIF 1 0 HACK Aoje Pi 1 A03 3 AIO 5 AIDS 8 I mp AIDE 1 RIOT 17 16 Tod 8 26 AOT 21 220 1013 23 uM 25 2 RIOTS 27 280 RIOTS p 310032 SOCKET 16 2 2 ANALOG I O ch SPARE 6 0 P2 SPARE 6 0 SPARE2 SPARES 1 SPARET 2 4 pieco LO BMCTRLT SBNCTRET BE DSP WRn TADDRIS 9 GND 2p ADDRTG IROn S 0 SPARES 13 MB RURE 18005 GND JROn S 0 ions TROnT TROn 5517 0 TROAO CSn r 0 m nd e 5 5 5 2 C ns 5 Ssni ZV 2V MOST 0 27 0 5V SCK 6Nb 5 5V SOCKET 20X2 2MM CONTROL1 P3 2V_DSP1_RESETa 2V_DS
57. P2_RESETn MRESETh 1 2V DBDA i GND GND EMADU 0 QV DBCKZ ES GND EMADI7 O ES SP EMAD2 EMADI 18004 IH 5 16 18 ND 19 20 GND 315 805 217 222 151805 GND 2 24D GND TSVBUS 25 26D ISVBUS 590 7 28 GNU T 29 30 575 2505 3 E 133V 23236 33 UND 35 3 E 37 38 5 5 0 mo 40 SOCKET 20 2 2 POWER CONTROL2 SPDIF_RXNO SPDI RXT SPDIF RX3 SPDIF TX SPARE 6 0 DSP1 DAO SDOUTJA 1 DSP2_DAO_SDOUT A 1 DSP1 CDI SCLK SOCKET 7 2 2 SPDIF 1 0 5 1 LRCLK DAL SCLK DSP1 DAO SDOUT A 1 n DSPT DRO SDOUT 13 15 16 Dm ap 558 21 END DN 23 24 p USPZUALSUN 25 26 27 28 DSP2 DAO SDOUTI 1 29 30 D DSPr DAC SDOUTI 3 35 36 SOCKET 20X2 2MM SERIAL AUDIO I O 1 ADG_MCLK emery GND ADCSDOUTT 23 4 D ADC SDOUTZ DC 50007 gt 8 DC SDOUT4 dr GND LSPDIF SDOUT 5o GRD DIP MODE SES 21 16 14p _ 17 18 UIP MODE SEDS lt i DI WODESE4 319 20 DIP MODE SEL 921 22 DIP MODE SEL2 423 24p Bie MODE SeLT 9 25 92
58. RX4 5 SPDIF 2 81 DAO_AUDATD 7 101 ADOT 502111 gt CMPDAT FSDATAN 1 10 gt FSDATAN 1 101 J4 SPDIF _RXNO ol SPDIF at 7 SPDIF_RX5 13 4 HDR7X2 2MM SPDIF 1 0 15 DSP1 CDI SCLK 1 DSP1 CDI 1 1 DSP1_CDI_SDIN DSP1 DAL SCLK Sol DSP1 DAL L RCLK Lol DSP1 DAL SDIN DSP1 9 DSP1 lt 115 DSP1 LRCLK 150 05 1_ 500111 DSPi DAQ SDOUT2 155 DSPI DAQ SDQUT3 DSP1 DAQ SDOUTA 17 05 2 CDI SCLK 190 DSP2 CDI LRCLK 210 SCLKN GPIO22 0592 SCIK 23 LRCLKN GPIO23 23 DSP2 DAO MCLK 2 DSP2 DAI SDIN 319 DSP 500011 DAO_AUDATO 11 101 DAO_AUDAT2 1 101 gt SDATANO GPIO24 1 101 gt SDATANI GPIO25 1101 DSP2 500013 DAO_AUDAT4 1 101 DSP2 DAO SDOUI2 335 DSP SPARF4 375 5 SPARE6 39 MCI K_OSC DAO AUDAT6 1 10 SDATAN3 GPIO27 1 001 HDR20X2 2MM SERIAL AUDIO 170 1 ADC MCLK J6 ADC ADC_SCIK OSC 11 5 10 111 500011 ADC SpouT3 ADC 500012 ADC_SCLK ADC_SDOUT2 13 4 81 13 81 SPDIF_MCIK PDIF _SCLK 5996 SPDIF_LRCLK ADC_SDOUT4 SPDIF _LRCLK 151 4 8 SPDIF SNOUT PE 2 PEE BN E 37 OSC 1 5 10 111 HDR20X2 2MM SERIAL AUDIO 1 0 2
59. SC 0 240 NV_WE GP1016 Figure 5 Sheet 2 Memory 3 A0 vec 8 M Re sae GNO SCA AT24CI28N 10SC uo DR po 74ACO0SC 82 1500 R121 10K A c109 poor 105 FXR 1106 XIR lOuf CO R122 20 0k 2 8 he ame 7 22 cos 2200pF R125 vb 45VA Dro 13 01 13 411 ADC go 5VA A vr E 20 forro 01 3 4 5 6 7 8 10 11 Ji Dove son tere 2V MRESET 18 RST VA 5 ELEC XIR 3 V AM pur 1 5 EAM 0330780 4 155 510148 ELEC S ANE 9120 mu AB LR sonra I Pu FRane HO 553 0 5 VA C AUC SCLK Denm 2 ADC SDQUTY yens 1117 UDSP_AIN2 ELEC 7I R5
60. SOP20 EVQ VEMF0224B PANASONIC ROTARY RES POTENTIOMETER 500 25 TURN TOP 2 VR2 VR1 3296Y 501 BOURNS ADJ TH CRYSTAL 32 768 KHZ PARALLEL 12 5PF 1 Y1 CM200832 768KDZFT CITIZEN LOAD STAND OFF 875 1 4 FLAT 4 40 313 6477 032 JOHNSON THREAD H343 ND DIGI KEY SCREW 4 40 5 16 MACHINE UDSP 1B 0 PRINTED CIRCUIT BOARD TSMD gt CIRRUS LOGIC
61. Type can be DSP or normal Word Length is in bytes these settings are for J47 hi J38 lo 9 CDB49400 8415a 2A 20 02 02 ff 01 00 00 normal 8405a 20 20 06 02 ff 01 00 00 normal 4392 22 20 04 02 ff 01 00 00 normal DSPC 82 82 01 01 03 04 04 03 DSP DSPAB 00 00 00 01 02 03 01 00 DSP default 82 82 01 01 03 04 04 03 DSP 19 CIRRUS LOGIC APPENDIX D RESET BAT echo Reset DSP and board REM Mute the DACs setpld w 02 20 961 962 REM reset the board CS8415 shares reset with DACs and ADCs urst d8415a 1 2 REM reset the DSP urst ddspc 1 962 20 CIRRUS LOGIC APPENDIX E BOARD CONTROL SOFTWARE There is a suite of programs used to control the UDSP from a PC DOS command line The software tools are designed to operate from a DOS prompt so that they can be scripted using the MS DOS batch language They will work with any of the 3 parallel port addresses 0 378 Ox3bc 0 278 The default address for all of the programs is 0x378 typically LPT1 but the port address can be changed by using the p option provided with every tool Each time a program is executed the address that was used is echoed to the screen If a program seems to fail verification of the parallel port address should the first step in troubleshooting All of these programs are designed to access the daughter card connected to the UDSP board using 2 serial communication and Intel Mot
62. atur C143 10uF 1 1 2 2 4 wc330780 560 ELEC 5 33V Rus 560pF b 2563326 L enn L 6 70 NUTECTRLO gt 0 AA m wu ADO CS AQUTA Hi So oe AUTE 22 Dro On j cert I DAO LRCLK 9 2 C152 Ve uon 5 560 E 21 ACU 0140 C139 ELEC 5 62 0150 151 va HZ Tur cos COG dem eve 745 Acla 6 1085 487 Wr Tur 2700pF S 8151 560 2 96 ELEC 25078 XR Selec Ke 238 WL LE 1 1 16 741 WOTECTRIO gt e DSP MCLK L gt E Figure 10 Sheet 7 DAC 2 ADOT 6 55 u42 5 2V_MISO_MOSI 4 SDA CDOUT SCL CCLK 28 2V_SCK 12 5 6 7 8 9 10 111 18 10 11 8405 C L gt _ 3a0 CS 56 AD2 TXP SPOIF_TX1 11 15 811 SPDIF RXI 25 1 43 02 H S 5VD 4 5 1 02 vot P 3 3V DGND4 2 4 21020 0005 1058 _MCLK 1 6 7 8 10 m E 1 3 5 6 7 0 1 ZV MRESETI ST ad 5 n nce nes HS L 6 7 8 101 DAO_LRCLK 12 ILRCK HE 6 7 8 101 DAO_SCLK 15 nes
63. ce 6 3 FLASH U9 The CDB49400 board includes 4 Mbits 512K X 8 of byte wide FLASH EPROM connected to the external memory interface of the CS49400 FLASH is used to store application code images for DSPAB and DSPC DSPC also supports in circuit FLASH programming Please contact your FAE for more information on FLASH programming details CIRRUS LOGIC 7 DEFAULT JUMPER SETTINGS ON THE CDB49400 The following tables list the default settings of all the jumpers and switches Do not move any switches or jumpers unless required for a specific application 7 1 Host Interface Boot Modes FHS2 FHS1 FHSO Interface Boot Mode UHS2 UHS1 UHSO Host Interface Boot Mode J34 J27 J17 J15 J16 J20 1 0 0 Serial 229 DSPC 1 Serial 2c External Host 1 0 1 Serial SPI DSPC 1 0 1 Serial SPI Via External Host 1 1 0 8 bit Intel Via DSPC 1 1 8 bit Intel External Host 1 1 1 801 Motorola Via DSPC 8 bit Motorola Via External 1 1 1 Host Table 1 DSPAB Boot Modes Host Interface Table 2 DSPC Boot Modes Host Interface 7 2 Host Interface Boot Mode Jumpers Jumper Purpose Position Function J20 1 2 Boot mode select UHSO 2 3 Low J16 1 2 High Boot mode select UHS1 2 3 Low J15 1 2 Boot mode select UHS2 2 3 Low J17 1 2 High Boot mode select FHS0 2 3 Low
64. d LED D1 has turned OFF 10 If the above steps give an error check all the jumpers and switches as described in DEFAULT JUMPER SETTINGS ON THE CDB49400 on page 11 and repeat the above procedure Refer to BOARD CONTROL SOFTWARE on page 21 and verify that the drivers and PC have been set up as described 11 If the above steps give the expected results type in PCM 49400 49400 p3bc or 49400 p278 depending on your parallel port address at the DOS prompt This batch file will configure the PLD boot the DSP and configure all the peripherals 12 If the batch file loads successfully the GPIO20 LED will flash This indicates that the DSP is running the downloaded code 13 Play a CD to send PCM data to the DSP via the optical connector GPIO21 will turn on and audio will be heard on the output The batch file use various files to configure the software board and the DSP code Each text file has been commented A sample batch file has been included in PCM 49400 BAT on page 15 for reference Various batch files for the commonly used applications have been supplied with the software These batch files can be run from the DOS prompt like the PCM 49400 BAT file Use caution while editing and making changes to these DO NOT move any jumpers or switches unless it is required for additional testing or instructed to do so by a Cirrus Logic FAE CIRRUS LOGIC 2 HARDWAR
65. ill communicate directly with the PC s parallel port to control the UDSP board The DLPortIO version uses the DLPortIO driver to access the parallel port on hardware protected operating systems In general direct hardware capable operating systems such as Microsoft Windows 959 Windows 989 and Windows allow any program to directly control any of the PC s peripherals With the UDSP board this allows for faster interface speeds up to 4 times faster For protected operating systems such as Microsoft Windows NT Windows 2000 Windows XP the UDSP driver set requires the use of the DLPortIO driver This utility allows the UDSP drivers to access the parallel port safely The UDSP driver set requires bidirectional communication with the UDSP board and hence a bidirectional capable parallel port is needed An ECP type port is required Please note that an SPP type port will not work with the UDSP board The type and location I O address of the parallel port installed can be found in the Windows Control Panel please see Windows Help for more information on these settings The UDSP drivers assume by default that the parallel port address is 0x378 Other ports may be used with the pXXX option where XXX is 3bc or 278 Installation on Microsoft Windows 959 989 ME and other direct hardware capable Win dows versions 1 Copy the contents of the udsp_1 4 directhw directory to a suitable location
66. is can be done by running the program port95nt exe and following the instructions given 2 Copy the contents of udsp 1 5 dlportio directory to a suitable location The folder c udsp is recommended 3 Copy the contents of cs49400 directory to c cs49400 4 Edit your c autoexec bat file to include the path to the UDSP drivers This will allow you to use the drivers in any directory without specifying the path to the executables The following line should be added set PATH your_path PATH where your path is the directory chosen in step 1 5 Again edit your c autoexec bat file to add the line set uINI PATHzyour pathNCDB49400 ini where your CDB path is the folder chosen in step 2 For the folder c cs49400 cdb49400 this would read set uINI_PATH c cs49400 cdb49400 CDB49400 ini This will allow the drivers to locate the CDB49400 configuration file which contains information about the various devices on this board 6 For the previous few steps to have an effect on your computer for the drivers to be available in any DOS window in any location you will need to reboot it at this time The UDSP drivers have now been successfully installed The CDB49400 kit is now ready for use Several demonstration batch files bat are available in the CDB49400 Configs directory Please see Quick Start on page 4 for information on the use of these batch files 25 CDB49400 SCHEMATICS dS 1 39945 4
67. l Memory Interface on page 10 LEDs are connected to GPIO20 and GPIO21 and used to indicate the status of application code on the DSP Other LEDs indicate power All signals entering or leaving the DSP are accessible via headers A debug port accessible to a PC via the parallel port is used to develop and debug code on DSPC The CDB49400 board is powered off 15 15V and 5V DC supplies These are regulated and filtered to meet the various voltage requirements of the individual circuits The power supply supplied with the system connected to J35 can be used to power the board Additionally power can be supplied to the board via the binding posts to aid in debug or isolation of noise generation CIRRUS LOGIC cs 8415 DAO MCLK DAO2 SLRCLK MUX DAO1 SLRCLK MUX DAO1 MCLK MUX CDH SCLK MUX x07 DAP SCLK CDi LRCLK MUX x07 DH SDIN MUX SCLK MUX SPDIF LRCLK DAH LRCLK MUX SDIN MUX DAI SCLK MUX ADC SCLK ADC SDOUT3 0 A LRCLK MUX DH SDIN MUX ADC LRCLK ADC 500074 07 SDIN MUX gt gt SDATA ENABLE SHIFT REGISTER 4207 CONTROL Note 1 DAO MCLK is the Master CLK for the system execptthe ADC 2 AUDATS and 7 are routed to XMT connector 3 Change PLD code for new routing CDH SCLK SDIN LRCLK SDIN SCLK 5
68. lopment changes Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufac ture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating
69. orola parallel communication The communication mode can be chosen from the command line with the m option It should be remembered that the mode chosen must correspond to the communication mode used by the devices on the daughter card If the device on the board is set up for one communication mode and the drivers are used with another results will be unpredictable peripherals on the daughter card are configured for SPI serial communication mode The usage of each program will vary depending on the type of card that is installed The programs retrieve a valid list of targets for the current card from a file specified in the uINI path environment variable This file will list all of the recognized mnemonics for the UDSP parallel port drivers along with each target s PCE address SPI address chip select number and reset number for reset capable devices It also specifies how messages from the device should be read For DSP style reads the driver will read until the INTREQ line goes high For non DSP devices the read operation will read out 1 byte Please note that most non DSP devices require an aborted write operation to properly set the MAP pointer before reading The target list file called CDB49400 INI must follow a very specific format An example of this can be found CDB49400 INT on page 19 A list of available drivers and their usage is found below UCMD exe Send commands or configuration files to a ta
70. rget device Usage lt ABCDEF or gt dZZZZz d device mY pWWW v 2222 device designator eg dspab dspc 8415a etc m communication mode Y mode designator i I2C s SPI m MOT n INT ABCDEF hex data 1 100 bytes f send configuration file X cfg file containing configuration parameters p parallel port address WWW address in hex 278 378 or 3bc v enable verbose mode default value Example ucmd 000001 d4341 p3bc Notes A configuration file is a list of commands contained in an ASCII text file This file can be any length and should list the commands in hex with an even number of characters per line Comments can be made in the file by putting a at the beginning of the line The entire line will be interpreted as a comment Please see the accompanying cfg files for examples of a configuration file 21 CIRRUS LOGIC URD exe Program used to read back responses from a target device If the INTREQ pin is not low when URD exe is executed the program will wait until INTREQ drops Press the Enter key to exit the read wait loop Usage urd dZZZZ mY pXXX v h d device ZZZZ device designator eg dspab dspc 8415a etc m communication mode Y mode designator i I2C s SPI m MOT n INT p parallel port address XXX address in hex 278 378 or 3bc v enable verbose mode h
71. un 5 5 675 ez Day wos 5 195 141 157 4945 105 dots Xe tt 2 2 50 LEA oor our oor Powe 0 06 E vss 65 10 62 65 007 10 1 gt Raz SPI EEPROM SD_DATAO ExTDO 10 100 ATISFIG24N 105C 27 UM 128K XB ero R72 100 ake S0 DATAIS EXTAIB 1 R2 100 iu 1 us 48 EXIAT 100 SD_DATAIS EXTAI7 1 50 DATA2 EXTO2 thro vs xii 100 R70 100 5 000 0015 48 1 SD DATAIS EXTAIG 1 50 DATA3 EXTOS ijo 100 868 100 tb 550074 SD_DATAI2 EXTAIS 11 111 SD_DATA4 EXTD4 2 002 0013145 EXTAI R6 100 100 Spas 00 S0 DATAT EXTAM 11 SD 5 EXIDS goa 9000 4 1 R20 00 SD DATAG EXTDG 100 a pas 000 42 100 SD DATAIO EXTAIS 111 HH Hi 50_ 7 7 zum 1 2913 m S0 DATAS EXTAT2 1 R63 100 nowo e exam m Hp ti sc ef t 100 M ol SE VES 150 9 45 tm 50 100 TES 3 Doke je dk n R23 1 SD_RAS 100 D R 150_ _ 1101 R53 R22 m 55729 100 STER Z 100 150 tm an 50 BA EXTATS C i 251 As 8 1
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