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NI Digital Electronics FPGA Board User Manual

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1. what you need to get started 1 5 instrument drivers NI resources B 1 K KnowledgeBase B 1 L LabVIEW 3 1 building a LabVIEW FPGA design 3 1 CLIP 3 5 component level intellectual property 3 5 creating a project 3 1 creating an FPGA target VI 3 2 documentation 3 7 example programs 3 5 FPGA 3 5 installation 1 6 programming the PROM 3 6 running the FPGA VI 3 4 testing the download 3 7 UCF file 3 7 LEDs 2 7 UCF file 4 2 modes NI ELVIS 1 8 stand alone 1 7 ni com National Instruments support and services B 1 NI ELVIS breadboard bank BB4 2 13 breadboard bank BBS 2 13 connector 2 14 mode 1 8 signals table 2 4 NI support and services B 1 0 oscillator 2 12 overview 1 1 P Pmod connectors 2 14 programming examples LabVIEW 3 5 NI resources B 1 Xilinx iMPACT 4 1 the PROM in LabVIEW 3 6 in Xilinx iMPACT 4 3 PROM programming in LabVIEW 3 6 programming in Xilinx iMPACT 4 3 push buttons 2 6 UCF file 4 2 R rotary push button knob and LEDs 2 11 running the FPGA VI 3 4 National Instruments Corporation 1 3 Index S safety information 1 1 signal breadboard area 2 13 descriptions 2 3 slide switches 2 5 UCF file 4 1 software examples LabVIEW 3 5 Xilinx IMPACT 4 1 LabVIEW 3 1 NI resources B 1 Xilinx iMPACT 4 1 specifications A 1 stand alone mode 1 7 support technical B 1 T technical support B 1 testing downloads in LabVIEW
2. LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 User Manual 4 2 ni com Ne Net Net Ne Net Net Ne Net SEGA1 LOC H6 SEGB1 LOC K2 SEGC1 LOC H3 SEGD1 LOC K1 SEGE1 LOC G4 SEGF1 LOC J2 SEGG1 LOC G3 COM1 LOC G2 Chapter 4 Programming with Xilinx iMPACT Software IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 50 MHz Clock Input Source The UCF file constraints for the 50 MHz clock input source are listed as follows Net sys_clk_pin LOC B8 Net sys_clk_pin IOSTANDARD LVCMOS33 System level constraints Net sys_clk_pin TNM_NET sys_clk_pin TIMESPEC TS_sys_clk_pin PERIOD sys_clk_pin 20000 ps Programming the PROM National Instruments Corporation 4 3 To program the
3. 3 7 in Xilinx iMPACT 4 6 training and certification NI resources B 1 troubleshooting NI resources B 1 two digit seven segment display 2 9 UCF file 4 2 U UCF file LabVIEW 3 7 Xilinx iMPACT 4 1 50 MHz clock input source 4 3 LEDs 4 2 push buttons 4 2 slide switches 4 1 two digit seven segment display 4 2 NI Digital Electronics FPGA Board User Manual Index W Web resources B 1 X Xilinx iMPACT 4 1 documentation 4 6 installation 1 6 programming the PROM 4 3 software examples 4 1 testing the download 4 6 UCF file 4 1 NI Digital Electronics FPGA Board User Manual 1 4 ni com
4. DC power supply 15 V GROUND DC power supply ground signal 5V GROUND DC power supply 5 V AI lt 0 5 gt AIGND Analog input channels 0 to 5 These pins are routed to the terminal of the respective channel amplifier AI lt 0 5 gt AIGND Analog input channels 0 to 5 These pins are routed to the terminal of the respective channel amplifier AISENSE Analog input sense In NRSE mode the reference for each AI lt 0 5 gt signal is AI SENSE AIGND Analog input ground The reference point for analog input and analog output signals NI Digital Electronics FPGA Board User Manual 2 4 ni com Chapter 2 Hardware Components Table 2 2 NI ELVIS Mode Signals Continued Bread board Signal Name Reference Description Bank SUPPLY GROUND Variable power supply positive line BBS GROUND Variable power supply ground SUPPLY GROUND Variable power supply negative line DIO lt 0 15 gt GROUND Digital I O channels 0 to 15 Bidirectional digital I O channels 0 through 15 PFI lt 3 4 gt GROUND Programmable Function Interface As an input each PFI terminal can PFI lt 8 9 gt be used to supply an external source for counter timer inputs As a PFI PFI lt 12 13 gt output you can route the counter timer outputs to each PFI terminal GROUND Ground Ground reference for signals Slide Switches The NI Digital Electronics FPGA Board has eight slide switches SW
5. MAINS for measuring purposes NI Digital Electronics FPGA Board User Manual 1 2 ni com Chapter 1 Overview and Setup provided by a standard wall outlet for example 115 AC voltage for U S or 230 AC voltage for Europe Examples of Measurement Category II are measurements performed on household appliances portable tools and similar hardware e Measurement Category III is for measurements performed in the building installation at the distribution level This category refers to measurements on hard wired hardware such as hardware in fixed installations distribution boards and circuit breakers Other examples are wiring including cables bus bars junction boxes switches socket outlets in the fixed installation and stationary motors with permanent connections to fixed installations e Measurement Category IV is for measurements performed at the primary electrical supply installation typically outside buildings Examples include electricity meters and measurements on primary overcurrent protection devices and on ripple control units To obtain the safety certification s for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column ESD Warning A Caution Although this product has been designed to be as robust as possible ESD Electrostatic Discharge can damage or upset this product This product must be protected at all times from ESD Static
6. NI Digital Electronics FPGA Board driver as described in NI Digital Electronics FPGA Board Driver Readme 2 Restart the PC if prompted NI Digital Electronics FPGA Board User Manual 1 6 ni com Chapter 1 Overview and Setup 3 Connect the NI Digital Electronics FPGA Board as described in one of the following sections Stand Alone Mode To connect the NI Digital Electronics FPGA Board in stand alone mode connected only to a PC go to the Stand Alone Mode section NIELVIS Mode To connect the NI Digital Electronics FPGA Board in NI ELVIS mode as an NI ELVIS prototyping board go to the NI ELVIS Mode section Stand Alone Mode The NI Digital Electronics FPGA Board can be used on a desktop as a stand alone or self contained device in stand alone mode The board requires a PC for new program download and optional application control monitoring purposes To install and set up the NI Digital Electronics FPGA Board in stand alone mode complete the following steps 1 Connect the USB type A connector to the USB connector on the host PC 2 Connect the USB type mini B connector to the NI Digital Electronics FPGA Board USB connector 3 Connect the 15 VDC power adapter to the power connector on the NI Digital Electronics FPGA Board then plug the power supply into a wall outlet 4 Power on the NI Digital Electronics FPGA Board by moving the power switch to the ON position Windows XP Windows recognizes any newly insta
7. Output Channels NT 4 Resolutions marian 12 bits Range DACO DAC dits 0 3 3 V DAC DAC sine nus 0 2 5 V Generali Single point O National Instruments Corporation A 1 NI Digital Electronics FPGA Board User Manual Appendix Specifications Analog Input General Bus Interface Channels aut eatin nas 2 RESOU O iia 12 bits simultaneously sampled Range aiii 0 3 3 V Sample and hold acquisition time 39 ns ACQUISITION cies rss nesecita Single point ON OFF power switch 1 Reset Button circa 1 LEDs discrete 8 Slide switches ooonoonccnocnconanancnncnnncnncnnnon 8 Push buttons 4 Seven segment displays eee 2 Rotary encoder with push button shaft oooonoconnncninncnncanocnnono 1 Clock oscillatOr ononcnnncnnnnnocnocnnnncnnnon 50 MHz clock oscillator 12 pin expansion connectors Pmod 6 Digilent Signal breadboard area Bot NT EDCVIS cup 2 For FPG att 3 General purpose breadboard area 1 NI ELVIS connector interface 1 PCI type USB suis teint cise sans pin USB 2 0 Full Speed USB connector Mini USB Type B NI Digital Electronics FPGA Board User Manual A 2 ni com Appendix Specifications Power DC power supply 15 VDC 650 mA Power supplies EUS inicie ii dista 1 5 A maximum 215 Mita 150 mA maximum FINV e et 400 mA maximum Total combined power 06 6 W maximum
8. Physical Dimensions 20 9 cm x 21 6 cm 8 25 in x 8 5 in WelBhit sssisssstitstemnnimantriihisrsines 284 g 10 oz Maximum Working Voltage Breadboard areas are only intended to be used for low voltage circuits lt 42 VAC 60 VDC Environmental Operating temperature 0 to 50 C Storage temperature 0 to 50 C Relative humidity eee 5 to 85 RH noncondensing Pollution Degree indoor use only 2 Maximum altitude ooooooccnnncoccncnononnnnnss 2 000 meters 3 Note Clean the device with a soft non metallic brush Make sure that the device is completely dry and free from contaminants before returning it to service 1 Total combined power of 6 W is available in an idle state Available power will decrease with increased FPGA utilization National Instruments Corporation A 3 NI Digital Electronics FPGA Board User Manual Appendix Specifications Safety This product meets the requirements of the following standards of safety for electrical equipment for measurement control and laboratory use e IEC 61010 1 EN 61010 1 e UL61010 1 CSA 61010 1 AJA Note For UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use e EN 61326 IEC 61326 Class A emiss
9. RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Conventions lt gt gt bold italic monospace monospace bold Platform The following conventions are used in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example AO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the
10. Stop Server button to close the LabVIEW FPGA Compile Server Click OK in the Successful Compile Report window The application is running on the FPGA board at this time Move switch SWO up and down LEDO should correspondingly light and turn off Press button BTNO LED2 should correspondingly light and turn off NI Digital Electronics FPGA Board User Manual 3 4 ni com Chapter 3 Programming with LabVIEW Software More LabVIEW Example Programs You can find additional LabVIEW example programs in the LabVIEW examples folder that installed with the NI Digital Electronics FPGA Board software driver by navigating to LabVIEW 8 6 examples DE FPGA Board For detailed information about LabVIEW examples for the NI Digital Electronics FPGA Board refer to the Developer Zone document NI Digital Electronics FPGA Board LabVIEW Example Programs To access this document go to ni com info and enter the info code defblv LabVIEW FPGA and CLIP The Component Level Intellectual Property CLIP node is a framework for importing external field programmable gate array intellectual property FPGA IP into the NI LabVIEW FPGA Module There are two types of CLIP e User defined CLIP allows users to insert VHDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI The NI Digital Electronics FPGA Board supports user defined CLIP Socketed CLIP provides the same IP integration functionality of the user d
11. external clock generates a 100 kHz to 5 MHz clock frequency that is controlled by rotating the knob You can access the external clock output line using signal line RotClk located on breadboard BB1 For more information about the signal breadboards refer to the Signal Breadboard Area section The external clock output line is not connected to the FPGA 50 MHz Onboard Oscillator The NI Digital Electronics FPGA Board uses a 50 MHz onboard clock oscillator as the clock input The 50 MHz clock output line GCLKO is connected to FPGA line B8 Refer to the UCF File Constraints section of Chapter 4 Programming with Xilinx iMPACT Software for more information about accessing the FPGA signals in iMPACT FPGA Boot Up Options Boot up selection on the NI Digital Electronics FPGA Board is controlled by switch SW9 shown in Figure 2 1 The two FPGA boot up options are described in Table 2 3 Table 2 3 FPGA Boot Up Options FPGA Boot Up Option Switch Position Boot up from ROM default Configures the FPGA from the image stored in the Platform Flash PROM ROM JTAG Boot up from JTAG Does not load anything into the FPGA waits for program download from USB JTAG port ROM JTAG The NI Digital Electronics FPGA Board supports download of FPGA designs directly to the FPGA through the JTAG using the onboard USB interface Switch SW9 should be set in the default position ROM The
12. following it applies only to that platform Contents Chapter 1 Overview and Setup Safety Informations shared tn he hate heat hr 1 1 ESD Warinpsfrnsni nt nn ede oy ees teat laden tasks Bec entr late einen hoes 1 3 Unpacking Transporting and Storage 1 4 Handling and Setip s i i ii sania weiitd atin dani iite Moses 1 4 Op ration sens din esheets sos sheets ries beng Sed nl need 1 4 ESD Prevention Measures ooooonocnconcnononncononnnonncnnncnnonnnconnnn a a i 1 5 Installation and SetUPi indiano ic 1 5 What You Need to Get Started 1 5 Installation and Setup Instructions 00 0 eee eee eeeeeeeseeeseeeeeeeceeeseeseseaeesees 1 6 Stand Alone Mode iii ts 1 7 NEELVIS Modesto c 1 8 Where to Go From Here usine nine na Maine 1 8 Chapter 2 Hardware Components Signal Descriptions ben its 2 3 Side Witches il eet eee A ave eileen ASE ie 2 5 Push Buttons miii ts 2 6 LEDS iros copii di da 2 7 Two Digit Seven Segment Display ss 2 9 GPIO Lines si nn ah dee te vas AR eS AN a aaa 2 11 Rotary Push Button Knob and LEDs 2 11 30 MHz Onboard Oscillator coccion hits 2 12 FPGA Boot Up Op ment rene e atacada iii 2 12 Breadboard Areas ita 2 13 Signal Breadboard Ateca 2 13 General Purpose Breadboard Area 2 13 Digilent Pmod Connectors titi dr atte ii 2 14 NIELVIS Connectors isa ste mans RAR Rien Mn A ee 2 14 National Instruments Corporation v NI Digital Electronics FPGA Board User Manual Contents Chapter 3 Prog
13. for digit 0 and SEGx1 for digit 1 All segment lines are SEGD lt 0 1 gt connected to the FPGA SEGE lt O 1 gt SEGF lt 0 1 gt SEGG lt 0 1 gt COM lt O0 1 gt Seven segment display enable disable lines These are enable disable lines for the corresponding digit low enable Both lines are connected to the FPGA LD lt 0 7 gt LEDs 0 through 7 I O lines connected to the eight LEDs The LEDs are also connected to the FPGA lines 15V GROUND DC power supply 15 V 15V GROUND DC power supply 15 V BB3 GROUND DC power supply ground BB2 BB3 National Instruments Corporation 2 3 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Components Table 2 2 describes the signals found on signal breadboard banks BB4 and BBS These signals are only active when the NI Digital Electronics FPGA Board is used in NI ELVIS mode Table 2 2 NI ELVIS Mode Signals Bread board Signal Name Reference Description Bank BASE DMM base signal BB4 DUT DMM device under test positive line DUT DMM device under test negative line AO lt 0 1 gt AIGND Analog output channels 0 to 1 These terminals supply the voltage output of AO channels 0 to 1 FGEN Function generator signal SYNC Function generator synchronization signal AM Function generator AM signal FM Function generator FM signal 15V GROUND DC power supply 15 V 15V GROUND
14. formatted PROM file into the platform flash PROM through the onboard USB JTAG circuitry connect the USB cable to the NI Digital Electronics FPGA Board apply power to the board move the power switch to the ON position and complete the following steps 1 On the NI Digital Electronics FPGA Board move switch SW9 to the JTAG position ROM JTAG Figure 4 1 Switch SW9 in JTAG Position 2 Launch Xilinx ISE Select File Open Project and navigate to the location of PROM ise Click OK 4 In the Processes pane of the project window expand Configure Target Device 5 Double click Manage Configuration Project IMPACT The Transcript pane of the project window displays the configuration progress NI Digital Electronics FPGA Board User Manual Chapter 4 Programming with Xilinx iMPACT Software The iMPACT Welcome to iMPACT window opens 3 Note Ifthe iMPACT Welcome to iMPACT window does not open launch iMPACT by selecting Start Programs Xilinx ISE Design Suite ISE Accessories iMPACT 6 10 Select Configure devices using Boundary Scan JTAG and Automatically connect to a cable and identify Boundary Scan chain these should be selected by default Click Finish The Assign New Configuration File window opens Select the main bit configuration file in the Assign New Configuration File window Click Open You have the option of selecting additional configuration files Because you do not nee
15. or below the measurement category marked on the hardware label Measurement circuits are subjected to working voltages and transient stresses overvoltage from the circuit to which they are connected during measurement or test Measurement categories establish standard impulse withstand voltage levels that commonly occur in electrical distribution systems The following is a description of measurement categories e Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage This category is for measurements of voltages from specially protected secondary circuits Such voltage measurements include signal levels special hardware limited energy parts of hardware circuits powered by regulated low voltage sources and electronics e Measurement Category II is for measurements performed on circuits directly connected to the electrical distribution system MAINS3 This category refers to local level electrical distribution such as that Measurement categories also referred to as overvoltage or installation categories are defined in electrical safety standard TEC 61010 1 and IEC 60664 1 2 Working voltage is the highest rms value of an AC or DC voltage that can occur across any particular insulation 3 MAINS is defined as a hazardous live electrical supply system that powers hardware Suitably rated measuring circuits may be connected to the
16. 31 Figure 2 7 shows the circuitry of the GPIO lines GPIOO aera GPIO1 Sia Breadboard FPGA GPIO30 nore GPIO31 ae Figure 2 7 GPIO Lines Circuit Diagram Each GPIO line is connected to the FPGA through a 200 Q current limiting resistor You can access the GPIO lines through signal breadboards BB 1 and BB2 For more information about the signal breadboards refer to the Signal Breadboard Area section GPIO lines can be configured in software on a per line basis for input or output GPIO lines are 3 3 V CMOS type and 5 V tolerant Rotary Push Button Knob and LEDs The NI Digital Electronics FPGA Board has a rotary push button knob ROT that is used to set the frequency range and value inside the range for an external clock generated by a microcontroller Pressing the rotary push button knob selects the range which is indicated by frequency range LEDs The rotary push button knob and frequency range LEDs are shown in Figure 2 1 The frequency range LEDs have the following functionality e LD LOW When lit the external clock generates a 1 Hz to 100 Hz clock frequency that is controlled by rotating the knob e LD MID When lit the external clock generates a 100 Hz to 100 kHz clock frequency that is controlled by rotating the knob National Instruments Corporation 2 11 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Components e LD HIGH When lit the
17. DE FPGA Board tree view select SWO and LEDO and drag them onto the block diagram as shown in Figure 3 2 10 In the LabVIEW block diagram wire SWO output to the LEDO input 11 In the Project Explorer window FPGA Target Board1 DE FPGA Board tree view select BTNO and LED2 and drag them onto the block diagram 12 In the LabVIEW block diagram wire BTNO output to the LED2 input 13 Add a While Loop around the resources National Instruments Corporation 3 3 NI Digital Electronics FPGA Board User Manual Chapter 3 Programming with LabVIEW Software 14 Wire a false constant to the stop condition of the While Loop eq Suu swo Si Pan LEDO SaaS Eu Sau erro SP uv LED2 Cala Figure 3 2 Block Diagram Y Tip Click the Clean Up Diagram button on the toolbar to tidy VI block diagrams 15 Save the VI as FPGA_Design vi Running the FPGA VI 1 3 Verify that the USB cable is connected to the NI Digital Electronics FPGA Board and host PC and the power switch is moved to the ON position Open the front panel of FPGA_Design vi Click the Run button to run the VI The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage The Generating Intermediate Files window opens and displays the compilation progress The LabVIEW FPGA Compile Server window opens and runs The compilation takes several minutes When the compilation finishes click the
18. Discussion Forums at ni com forums NI Applications Engineers make sure every question submitted online receives an answer Standard Service Program Membership This program entitles members to direct access to NI Applications Engineers via phone and email for one to one technical support as well as exclusive access to on demand training modules via the Services Resource Center NI offers complementary membership for a full year after purchase after which you may renew to continue your benefits For information about other technical support options in your area visit ni com services or contact your local office at ni com contact Training and Certification Visit ni com training for self paced training eLearning virtual classrooms interactive CDs and Certification program information You also can register for instructor led hands on courses at locations around the world System Integration If you have time constraints limited in house technical resources or other project challenges National Instruments Alliance Partner members can help To learn more call your local NI office or visit ni com alliance B 1 NI Digital Electronics FPGA Board User Manual Appendix B Technical Support and Professional Services Declaration of Conformity DoC A DOC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for ele
19. FPGA Board User Manual 3 6 ni com Testing the Download Chapter 3 Programming with LabVIEW Software To test that the download was successful complete the following steps Verify that switch SW9 is in the ROM position 1 ROM JTAG 2 3 Figure 3 3 Switch SW9 in ROM Position Reboot the NI Digital Electronics FPGA Board by pressing the reset button Verify that the FPGA is running the PROM downloaded application Where to Go from Here The following resources contain information about writing applications for the NI Digital Electronics FPGA Board LabVIEW FPGA documentation National Instruments Corporation Getting Started with LabVIEW FPGA 8 x This KnowledgeBase available at ni com kb provides links to the top resources that can be used to assist in getting started with programming in LabVIEW FPGA FPGA Module book in the LabVIEW Help Select Help Search the LabVIEW Help in LabVIEW to view the LabVIEW Help Browse the FPGA Module book in the Contents tab for information about how to use the FRGA Module to create VIs that run on the NI Digital Electronics FPGA Board LabVIEW FPGA Module Release and Upgrade Notes Contains information about installing the LabVIEW FPGA Module describes new features and provides upgrade information To access this document refer to ni com manuals In LabVIEW 8 0 or later you can also view the LabVIEW Manuals directory that contains this document by
20. File menu select the Page Setup item and select Options from the last dialog box This icon denotes a tip which alerts you to advisory information This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on a product refer to the Safety Information and ESD Warning sections of Chapter 1 Overview and Setup for information about precautions to take Bold text denotes items that you must select or click in the software such as menu items and dialog box options Bold text also denotes parameter names Italic text denotes variables emphasis a cross reference or an introduction to akey concept Italic text also denotes text that is a placeholder for a word or value that you must supply Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions Bold text in this font denotes the messages and responses that the computer automatically prints to the screen This font also emphasizes lines of code that are different from the other examples Text in this font denotes a specific platform and indicates that the text
21. LabVIEW FPGA Module This chapter lists information necessary to program the NI Digital Electronics FPGA Board with LabVIEW and the LabVIEW FPGA Module including a tutorial section that demonstrates how to create and run your own LabVIEW project Building a LabVIEW FGPA Design Creating a Project This section demonstrates how to create a LabVIEW project and FPGA VI that performs the following e Routes switch SWO to LEDO which causes LEDO to light when switch SWO is moved to the ON position and turn off when the switch moved to the OFF position e Routes push button BTNO to LED2 which causes LED2 to light when button BTNO is pressed and turn off when the button is depressed This example also demonstrates how to compile and run the FPGA VI on the NI Digital Electronics FPGA Board To begin programming with LabVIEW connect the USB cable to the NI Digital Electronics FPGA Board apply power to the board and move the power switch to the ON position 1 Launch LabVIEW 2 Inthe Getting Started window click Empty Project The new project opens in the Project Explorer window 3 Save the project as FPGA Design lvproj National Instruments Corporation 3 1 NI Digital Electronics FPGA Board User Manual Chapter 3 Programming with LabVIEW Software Creating an FPGA Target VI 1 In the Project Explorer window right click My Computer and select New Targets and Devices In the Add Targets and Devices on My Co
22. Manual Chapter 1 Overview and Setup Q One of the following software packages NI LabVIEW version 8 6 or later and the LabVIEW FPGA Module version 8 6 or later and the following e PC running Windows Vista or Windows XP Pro x32 Service Pack 1 or 2 The LabVIEW Release Notes and the LabVIEW FPGA Module Release Notes or Xilinx iMPACT software version 10 x or later part of the ISE WebPACK software kit available from www xilinx com ise and the following e PC running Windows Vista XP e The ZSE Design Suite Release Notes and Installation Guide A Optional NI ELVIS II Series Benchtop Workstation AC DC power supply high speed USB 2 0 cable NI ELVISmx 4 0 or later software CD and the Where to Start with NI ELVIS II Series document Installation and Setup Instructions To install and set up the NI Digital Electronics FPGA Board complete the following steps 1 Install the software you are going to use a b Install NI LabVIEW as described in the LabVIEW Release Notes Install the LabVIEW FPGA Module as described in the LabVIEW FPGA Module Release Notes Install the NI Digital Electronics FPGA Board driver as described in NI Digital Electronics FPGA Board Driver Readme Optional Install the NI ELVISmx software as described in the installation instructions on the software CD or Install the Xilinx ISE software kit as described in the SE Design Suite Release Notes and Installation Guide Install the
23. Manual Chapter 2 Hardware Components NI ELVIS Signals oe IBB4 BBS 15U DC ONLYII BB1 BB2 f i POWER SWITCH z CII BEBEBE E HEHE BTN3 BTN2 87m Ms MENTS DIGITAL ELECTRONICS FPGA BOARD swe SW5 SW4 SW3 SW2 e ao oc swag BTNO Jonooon9 fete 0000000 Le SWi0 Do nn e oO 2 a B RESET 8 8 Um amp q 028 35 00 ONIY a g 000000 7 T5 000000 0 o D gt 109 a a qu o S o gfe 8 a a 8 Seo BE sh 5 m LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO o LA of oo O gt Cseses el og 9 oo se sis 0 Power Connector General Purpose Breadboard Banks Signal Breadboard Bank BB2 Power Switch Signal Breadboard Bank BB3 Reset Button D Oo O1 amp 7 Seven Segment Displays 8 USB Connector 9 LD GLED 10 LEDs 11 FPGA 12 Switch SW9 13 Rotary Push Button Knob LEDs 14 Push Buttons 15 Slide Switches 16 Digilent Pmod Connectors 17 Signal Breadboard Bank BB1 18 Signal Breadboard Bank BB4 19 NI ELVIS Connector 20 Signal Breadboard Bank BB5 NI Digital Electronics FPGA Board
24. NI Digital Electronics FPGA Board User Manual Circuit Development Platform May 2009 7 NATIONAL 372809B 01 INSTRUMENTS Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 1800 300 800 Austria 43 662 457990 0 Belgium 32 0 2 757 0020 Brazil 55 11 3262 3599 Canada 800 433 3488 China 86 21 5050 9800 Czech Republic 420 224 235 774 Denmark 45 45 76 26 00 Finland 358 0 9 725 72511 France 01 57 66 24 24 Germany 49 89 7413130 India 91 80 41190000 Israel 972 3 6393737 Italy 39 02 41309277 Japan 0120 527196 Korea 82 02 3451 3400 Lebanon 961 0 1 33 28 28 Malaysia 1800 887710 Mexico 01 800 010 0793 Netherlands 31 0 348 433 466 New Zealand 0800 553 322 Norway 47 0 66 90 76 60 Poland 48 22 328 90 10 Portugal 351 210 311 210 Russia 7 495 783 6851 Singapore 1800 226 5886 Slovenia 386 3 425 42 00 South Africa 27 0 11 805 8197 Spain 34 91 640 0085 Sweden 46 0 8 587 895 00 Switzerland 41 56 2005151 Taiwan 886 02 2377 2222 Thailand 662 278 6777 Turkey 90 212 279 3031 United Kingdom 44 0 1635 523545 For further support information refer to the Technical Support and Professional Services appendix To comment on National Instruments documentation refer to the National Instruments Web site at ni com info and enter the info code feedback 2009 Nationa
25. O through SW7 shown in Figure 2 1 Figure 2 2 shows the circuitry of the slide switches VCC3V3 O R55 swo AM Oswo 2K R58 XS AM swi Sw1 2K Xe R60 swe AM Oswe2 2K O R62 Y Ay 03 Osw3 2K o R63 Xo AM Swa O SW4 2K O R64 Xo Ay M5 OSW5 2K e R65 Xo ANA Swe OSW6 2K O R66 sw7 OSW7 2K GND o o gt o amp Figure 2 2 Slide Switches Circuit Diagram National Instruments Corporation 2 5 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Components The switches typically exhibit about 2 ms of mechanical bounce there is no active debouncing circuitry Switches have an output impedance of 2 kQ When in the up or ON position the switch connects the line to 3 3 V a logic High When in the down or OFF position the switch connects the line to ground a logic Low You can access the slide switch lines through the signal breadboard BB1 For more information about the signal breadboards refer to the Signal Breadboard Area section The switches are also connected directly to the FPGA lines Refer to the UCF File Constraints section of Chapter 4 Programming with Xilinx iMPACT Software for more information about accessing the FPGA signals in iMPACT Push Buttons The NI Digital Electronics FPGA Board has four momentary contact push buttons BTNO through BTN3 shown in Figure 2 1 Figure 2 3 shows the circuitry of the push butt
26. User Manual Figure 2 1 The NI Digital Electronics FPGA Board 2 2 ni com Chapter 2 Signal Descriptions Hardware Components Table 2 1 describes the signals found on the NI Digital Electronics FPGA Board signal breadboard banks BB1 BB2 and BB3 Refer to the Breadboard Areas section for more information about the breadboards Table 2 1 NI Digital Electronics FPGA Board Signals Bread board Signal Name Reference Description Bank DAC lt 0 3 gt GROUND Digital to analog converter signals 0 to 3 BB1 ADC lt 0 1 gt GROUND Analog to digital converter signals 0 to 3 BTN lt 0 3 gt Push Buttons 0 to 3 I O lines connected to the four push buttons The push buttons are also connected to the FPGA lines SW lt 0 7 gt Slide switches 0 to 7 I O lines connected to the eight slide switches The slide switches are also connected to the FPGA lines RotCLK GROUND External clock signal Generates pulses at manually selected frequencies The external clock output line is not connected to the FPGA GPIO lt 24 31 gt GROUND General purpose FPGA lines 24 to 31 GPIO lt 0 23 gt GROUND General purpose FPGA lines 0 to 23 BB2 5 0V GROUND DC power supply 5 0 V SEGA lt O 1 gt Seven segment display signals Controls a specific LED in the seven BB3 SEGB lt 0 1 gt segments of each digit in the seven segment display Segment LEDs are SEGC lt 0 1 gt named SEGx0
27. abVIEW 3 6 the PROM in Xilinx iMPACT 4 3 with LabVIEW software 3 1 with Xilinx iMPACT 4 1 reference diagram figure 2 2 setup 1 5 signal descriptions 2 3 signals table 2 3 software 1 6 specifications A 1 testing the download in LabVIEW 3 7 the download in Xilinx iMPACT 4 6 what you need to get started 1 5 documentation conventions used in the manual iv LabVIEW 3 7 NI resources B 1 Xilinx iMPACT 4 6 download testing in LabVIEW 3 7 in Xilinx iMPACT 4 6 drivers NI resources B 1 NI Digital Electronics FPGA Board User Manual Index E example programs LabVIEW 3 5 Xilinx iMPACT 4 1 examples NI resources B 1 F FPGA and CLIP 3 5 boot up options 2 12 switch positions table 2 12 target adding user defined CLIP 3 5 G general purpose breadboard area 2 13 breadboard bank BB4 in stand alone mode 2 13 breadboard bank BBS in stand alone mode 2 13 GPIO lines 2 11 H hardware components 2 1 50 MHz onboard oscillator 2 12 breadboard areas 2 13 FPGA boot up options 2 12 GPIO lines 2 11 LEDs 2 7 push buttons 2 6 reference diagram figure 2 2 rotary push button knob and LEDs 2 11 slide switches 2 5 switch SW9 table 2 12 two digit seven segment display 2 9 UCF file 4 1 help technical support B 1 NI Digital Electronics FPGA Board User Manual 1 2 iMPACT See Xilinx iMPACT installation 1 5 NIELVIS mode 1 8 safety information 1 1 stand alone mode 1 7
28. agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A
29. al Instruments Corporation 2 9 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Components Each digit is composed of seven segments arranged in a figure 8 pattern with an LED embedded in each segment Segment LEDs are SEGx0 for digit 0 and SEGx1 for digit 1 as shown in Figure 2 6 SEGA mm SEGF1 SEGG1 mmm SEGE1 SEGD1 mmp Digit 1 SEGB1 SEGC1 SEGAO mm SEGFO SEGBO SEG GO mmp SEGEO SEGCO am SEG DO ma Digit O Figure 2 6 Segment Diagram Segment LEDs can be individually illuminated so different patterns can be displayed on a digit by lighting certain LED segments You can access the seven segment display lines through the signal breadboard BB3 To light an individual LED segment drive the associated line High using 3 3 V or 5 V Lines COMO and COMI can be used to enable disable each digit of the display to allow using the display in multiplexed mode For more information about the signal breadboards refer to the Signal Breadboard Area section All segment and COM lines are connected to the FPGA Refer to the UCF File Constraints section of Chapter 4 Programming with Xilinx iMPACT Software for more information about accessing the FPGA signals in iMPACT NI Digital Electronics FPGA Board User Manual 2 10 ni com Chapter 2 Hardware Components GPIO Lines The NI Digital Electronics FPGA Board has 32 general purpose I O lines GPIO0 to GPIO
30. alled device the first time the computer reboots after hardware is installed On some Windows systems the Found New Hardware Wizard opens with a dialog box for every NI device installed Install the software automatically Recommended is selected by default Click Next or Yes to install the software for the device and the USB cable ports The green LD G LED lights indicating a good connection Where to Go From Here You can now program the FPGA using the onboard USB interface with software as described in the following chapters e Chapter 3 Programming with LabVIEW Software or e Chapter 4 Programming with Xilinx iMPACT Software Refer to Chapter 2 Hardware Components for detailed information about the components on the NI Digital Electronics FPGA Board Refer to Appendix A Specifications for device specifications NI Digital Electronics FPGA Board User Manual 1 8 ni com Hardware Components This chapter describes the components on the NI Digital Electronic FPGA Board e Signal Descriptions e Slide Switches e Push Buttons e LEDs e Two Digit Seven Segment Display e GPIO Lines e Rotary Push Button Knob and LEDs e 50 MHz Onboard Oscillator e FPGA Boot Up Options e Breadboard Areas e Digilent Pmod Connectors e NI ELVIS Connector Figure 2 1 shows a reference diagram of the top view of the NI Digital Electronics FPGA Board National Instruments Corporation 2 1 NI Digital Electronics FPGA Board User
31. board boots up in default configuration which can be overwritten by the downloaded FPGA design The downloaded FPGA design is valid as long as the board is not powered down reset or rewritten with a different FPGA design NI Digital Electronics FPGA Board User Manual 2 12 ni com Chapter 2 Hardware Components Breadboard Areas The NI Digital Electronics FPGA Board features two breadboard areas e Signal Breadboard Area e General Purpose Breadboard Area Refer to Figure 2 1 for the location of the breadboard areas Signal Breadboard Area The signal breadboard area is comprised of breadboard banks BB1 BB2 BB3 BB4 and BBS Refer to Figure 2 1 for the locations of the signal breadboard banks Refer to Tables 2 1 and 2 2 for descriptions of signals found on the signal breadboard area e BB1 Breadboard area for the DAC ADC push buttons slide switches external clock and general purpose FPGA lines e BB2 Breadboard area for the general purpose FPGA lines and DC power supplies BB3 Breadboard area for the seven segment displays LEDs and DC power supplies BB4 Breadboard area for the NI ELVIS signals including analog input analog output signals function generator DC power supplies and digital input output signals e BB5 Breadboard area for the NI ELVIS signals including the variable power supplies digital I O signals counter signals and ground references General Purpose Breadboard Area The
32. cations Refer to the hardware s user documentation for more information You must insulate signal connections for the maximum voltage for which the hardware is rated Do not exceed the maximum ratings for the hardware National Instruments Corporation 1 1 NI Digital Electronics FPGA Board User Manual Chapter 1 Overview and Setup Do not install wiring while the hardware is live with electrical signals Do not remove or add connector blocks when power is connected to the system Avoid contact between your body and the connector block signal when hot swapping hardware Remove power from signal lines before connecting them to or disconnecting them from the hardware Operate the hardware only at or below Pollution Degree 2 Pollution is foreign matter in a solid liquid or gaseous state that can reduce dielectric strength or surface resistivity The following is a description of pollution degrees e Pollution Degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence Typical level for sealed components or coated PCBs e Pollution Degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected Typical level for most products e Pollution Degree 3 means that conductive pollution occurs or dry nonconductive pollution occurs that becomes conductive due to condensation Operate the hardware at
33. charges may easily produce potentials of several kilovolts on the human body or equipment which can discharge without detection Industry standard ESD precautions must be employed at all times The NI Digital Electronics FPGA Board is designed and intended for use as a development platform for hardware or software in an educational professional laboratory environment To facilitate usage the board is manufactured with its components and connecting traces openly exposed to the operator and the environment As a result ESD sensitive ESDS components on the board such as the semiconductor integrated circuits can be damaged when exposed to an ESD event To indicate the A ESD sensitivity of the NI Digital Electronics FPGA Board it carries the AL symbol shown at left National Instruments Corporation 1 3 NI Digital Electronics FPGA Board User Manual Chapter 1 Overview and Setup Unpacking Transporting and Storage When unpacking the NI Digital Electronics FPGA Board from its shipping carton do not remove the board from the antistatic packaging material until you are ready to complete the installation Before unwrapping the antistatic packaging discharge yourself by touching a grounded bare metal surface touching an approved anti static mat or wearing an ESD strap When transporting or storing the NI Digital Electronics FPGA Board first place it in an antistatic container or packaging Handling and Setup Operation Handling
34. ctromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events NI Digital Electronics FPGA Board User Manual B 2 ni com Index Numerics 50 MHz clock input source UCF file 4 3 onboard oscillator 2 12 BB1 2 13 BB2 2 13 BB3 2 13 BB4 2 13 BBS 2 13 BB6 and BB7 2 13 breadboard areas 2 13 general purpose 2 13 signal 2 13 buttons push 2 6 UCF file 4 2 C CLIP 3 5 adding user defined CLIP to an FPGA target 3 5 user defined 3 5 component level intellectual property See CLIP connectors Digilent Pmod 2 14 NI ELVIS 2 14 conventions used in the manual iv creating a LabVIEW project 3 1 an FPGA target VI 3 2 National Instruments Corporation D Declaration of Conformity NI resources B 2 diagnostic tools NI resources B 1 Digilent Pmod connectors 2 14 Digital Electronics FPGA Board boot up options 2 12 hardware components 2 1 installation 1 5 NI ELVIS signals table 2 4 overview 1 1 programming the PROM in L
35. d a new configuration click Cancel The Device Programming Properties window opens In the Device Programming Properties window select Device 1 FPGA xc3s500e to program Device 1 The NI Digital Electronics FPGA Board FPGA is a Xilinx XC3S500E Spartan 3E FPGA Click OK The Boundary Scan pane opens in the project window Right click the xcf04s file icon and select Assign New Configuration File to assign the PROM file mcs to the XCF04S platform flash PROM on the JTAG chain Click Open NI Digital Electronics FPGA Board User Manual 4 4 ni com Chapter 4 Programming with Xilinx IMPACT Software El Xilinx ISE C Documents and Settings scollier My Documents UnboxWigital Electronics Board simpletest PROM ise Boundary Scan Woe Kb File Edit View Project Source Process Operations Output Debug Window Help DE x DA BIXDEX Da PtEPPX KSA A BBD AR Y 9 90 00 FRE STITALA AA Ti a SO SN Sources amp 2Boundary Scan 25 SlaveSerial Ea SelectMAP 13 22 Desktop Configuration m Direct SPI Configuration see E SystemACE xc3s500e xc104s E PROM File Formatter main bit myplatformilash m TDO Y Y 3 7 aG Source y Fies g Snap Py Librarie Configuration Processes Available Operations are gt Program gt Verity p Erase gt Blank Check gt Readback gt Get Device ID gt Get Device Checksum Get Device Signature Usercode p Check Idcode l Pr Configura
36. e hardware components listed here The UCF file constraints for the eight slide switches SWO to SW7 are listed as follows SWx refers to the slide switch line LOC indicates the FPGA line location and IOSTANDARD is the I O standard used Net Sw0 LOC J11 IOSTANDARD LVCMOS33 Net Swi LOC J12 IOSTANDARD LVCMOS33 Net SwW2 LOC H16 IOSTANDARD LVCMOS33 Net SW3 LOC H13 IOSTANDARD LVCMOS33 Net Sw4 LOC G12 IOSTANDARD LVCMOS33 Net SwW5 LOC E14 IOSTANDARD LVCMOS33 Net Sw6 LOC D16 IOSTANDARD LVCMOS33 Net SW7 LOC B16 IOSTANDARD LVCMOS33 National Instruments Corporation 4 1 NI Digital Electronics FPGA Board User Manual Chapter 4 Programming with Xilinx iMPACT Software Push Buttons LEDs Net LEDO LOC C11 Net LED1 LOC D11 Net LED2 LOC B11 Net LED3 LOC A12 Net LED4 LOC A13 Net LED5 LOC B13 Net LED6 LOC A14 Net LED7 LOC B14 The UCF file constraints for the four push buttons BTNO to BTN3 are listed as follows BTNx refers to the push button line LOC indicates the FPGA line location and IOSTANDARD is the I O standard used Net BTNO LOC C13 IOSTANDARD LVCMOS33 Net BTN1 LOC D12 IOSTANDARD LVCMOS33 Net BTN2 LOC C12 IOSTANDARD LVCMOS33 Net BTN3 LOC C10 IOSTANDARD LVCMOS33 The UCF file constraints for the eight LEDs LEDO to LED7 are l
37. efined CLIP while also allowing the CLIP to communicate directly with circuitry external to the FPGA Socketed CLIP is not supported in the NI Digital Electronics FPGA Board The CLIP feature targets users with digital design experience a general knowledge of VHDL and a working understanding of XML For the more information refer to the Using VHDL Code as Component Level IP topic in the FPGA Module book of the LabVIEW Help Adding User Defined CLIP to an FPGA Target Refer to the Using VHDL Code as Component Level IP topic in the FPGA Module book of the LabVIEW Help for additional information about using CLIP with the NI Digital Electronics FPGA Board For detailed information about the NI Digital Electronics FPGA Board and CLIP including software tutorials refer to the Developer Zone document Importing External IP into LabVIEW FPGA with the CLIP Node To access this document go to ni com info and enter the info code clipdz National Instruments Corporation 3 5 NI Digital Electronics FPGA Board User Manual Chapter 3 Programming with LabVIEW Software Running a VI in Emulation Mode You can run a VI written for the NI Digital Electronics FPGA Board in emulation mode Emulation mode when the computer executes code written for another target FPGA in this case is useful in the debugging and testing phase of an FPGA application because it reduces the need for repetitive VI compilation during development Compiling an FPGA VI ca
38. ental regulations and directives with which NI complies as well as other environmental information not included in this document Waste Electrical and Electronic Equipment WEEE EU Customers At the end of their life cycle all products must be sent to a WEEE recycling center For more information about WEEE recycling centers and National Instruments WEEE initiatives visit ni com environment weee htm Ds ETARA AAA SEE HE ROHS OH REA National Instruments AP E LF fis m t REMEH EEA ES ROHS XF National Instruments El RoHS 4 1 HS El W ni com environment rohs_ china For information about China RoHS compliance go to ni com environment rohs_china National Instruments Corporation A 5 NI Digital Electronics FPGA Board User Manual Technical Support and Professional Services Visit the following sections of the award winning National Instruments Web site at ni com for technical support and professional services O National Instruments Corporation Support Technical support at ni com support includes the following resources Self Help Technical Resources For answers and solutions visit ni com support for software drivers and updates a searchable KnowledgeBase product manuals step by step troubleshooting wizards thousands of example programs tutorials application notes instrument drivers and so on Registered users also receive access to the NI
39. event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instru
40. general purpose breadboard area contains two breadboard banks These banks are not connected to any board resources Refer to Figure 2 1 for the locations of the general purpose breadboard banks 3 Note Signal breadboard banks BB4 and BB5 can be used as general purpose breadboards when the NI Digital Electronics FPGA Board is used in stand alone mode National Instruments Corporation 2 13 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Components Digilent Pmod Connectors Use the Digilent Pmod connectors shown in Figure 2 1 for connection to up to six Digilent Pmod modules Digilent Pmods are compact modules that can be added to expand the capabilities of the NI Digital Electronics FPGA Board You can connect up to six 1x6 single or 2x6 double Pmod modules to the NI Digital Electronics FPGA Board Refer to the Digilent Web site www digilentinc com for more information about Pmod modules NI ELVIS Connector The NI Digital Electronics FPGA Board features a PCI type connector shown in Figure 2 1 which plugs into an NI ELVIS II Series workstation when the NI Digital Electronics FPGA Board is used in NI ELVIS mode NI Digital Electronics FPGA Board User Manual 2 14 ni com Programming with LabVIEW Software After you install the software and set up the hardware for stand alone mode or NI ELVIS mode as described in Chapter 1 Overview and Setup you are ready to program with NI LabVIEW software and the
41. grammed the Boundary Scan pane displays Program Succeeded 14 Select File Close Project and save all changes Testing the Download To test that the download was successful complete the following steps 1 Verify that switch SW9 is in the ROM position ROM JTAG Figure 4 3 Switch SW9 in ROM Position 2 Reboot the NI Digital Electronics FPGA Board by pressing the reset button 3 Verify that the FPGA is running the PROM downloaded application Where to Go from Here The following resources contain information for writing applications and taking measurements with the NI Digital Electronics FPGA Board e ISE Quick Start Tutorial Contains a step by step description of creating a simple design performing simulation and running implementation e Xilinx ISE Help Describes how to get started with the ISE Design Suite software FPGA design and troubleshoot the software NI Digital Electronics FPGA Board User Manual 4 6 ni com Specifications Specifications listed below are typical at 25 C unless otherwise noted FPGA FPGA iii Bis Xilinx XC3SS00E 4FTG256C System Bates 500 k Logic cells 10 476 Logic family CMOS Platform Flash configuration PROM 4 Mbit Onboard USB based FPGA CPLD download debug interface General Purpose 1 0 GPIO MES escorts inte 32 general purpose digital I O lines 3 3 V 8 mA maximum Analog
42. ions Basic immunity e EN 55011 CISPR 11 Group 1 Class A emissions e AS NZS CISPR 11 Group 1 Class A emissions e FCC 47 CFR Part 15B Class A emissions e ICES 001 Class A emissions B Note For the standards applied to assess the EMC of this product refer to the Online Product Certification section nye Note For EMC compliance operate this product according to the documentation CE Compliance C This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC Online Product Certification Refer to the product Declaration of Conformity DoC for additional regulatory compliance information To obtain product certifications and the DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column NI Digital Electronics FPGA Board User Manual A 4 ni com Appendix Specifications Environmental Management National Instruments is committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial not only to the environment but also to NI customers For additional environmental information refer to the NJ and the Environment Web page at ni com environment This page contains the environm
43. isted as follows LEDx refers to the LED line LOC indicates the FPGA line location IOSTANDARD is the I O standard used SLEW refers to the slew rate the maximum rate of change of a signal and DRIVE indicates the current drive strength on the FPGA in milliamps IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Seven Segment Displays Net SEGAO LOC E3 Net SEGBO LOC E1 Net SEGCO LOC G5 Net SEGDO LOC D1 Net SEGE0O LOC E4 Net SEGFO LOC C1 Net SEGGO LOC C2 Net COMO LOC B2 NI Digital Electronics FPGA Board The UCF file constraints for the seven segment displays are listed as follows SEGxx refers to the display segment line COM lt x refers to the display anode line LOC indicates the FPGA line location IOSTANDARD is the I O standard used SLEW refers to the slew rate the maximum rate of change of a signal and DRIVE indicates the current drive strength on the FPGA in milliamps IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 IOSTANDARD
44. itches buttons knobs and other controls while the board is powered on NI Digital Electronics FPGA Board User Manual 1 4 ni com Chapter 1 Overview and Setup ESD Prevention Measures ESD prevention measures focus on reducing or eliminating the build up of static charge that may result in an ESD event that could damage or upset sensitive electronics To minimize the potential for an ESD event implement the following measures e Perform all work at an approved work station e Use an approved antistatic mat to cover your work surface e Wear a conductive wrist strap attached to the antistatic mat and a good earth ground e Before handling or beginning work equalize your potential with the board by touching one of the ESD discharge pads Installation and Setup This section describes what you need to get started with the NI Digital Electronics FPGA Board and how to install your software and set up your board What You Need to Get Started The following items are necessary to set up and use the NI Digital Electronics FPGA Board Q The NI Digital Electronics FPGA Board kit containing the following National Instruments Corporation The NI Digital Electronics FPGA Board Standard USB type A to mini B cable 15 VDC 650 mA power adapter NI Digital Electronics FPGA Board Driver CD which contains the NI Digital Electronics FPGA Board driver readme and user documentation 1 5 NI Digital Electronics FPGA Board User
45. l Instruments Corporation All rights reserved Important Information Warranty The NI Digital Electronics FPGA Board is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the
46. lled device the first time the computer reboots after hardware is installed On some Windows systems the Found New Hardware Wizard opens with a dialog box for every NI device installed Install the software automatically Recommended is selected by default Click Next or Yes to install the software for the device and the USB cable ports The green LD G LED lights indicating a good connection National Instruments Corporation 1 7 NI Digital Electronics FPGA Board User Manual Chapter 1 Overview and Setup NI ELVIS Mode In NI ELVIS mode the NI Digital Electronics FPGA Board can be used as a prototyping board on an NI ELVIS II Series workstation Install and set up the NI Digital Electronics FPGA Board and NI ELVIS I Series workstation as described in the Where to Start with NI ELVIS IT Series document Where the NI ELVIS II Series installation instructions refer to the prototyping board complete the following instructions 1 Insert the NI Digital Electronics FPGA Board as a prototyping board as described in the Where to Start with NI ELVIS II Series document 2 Connect one end of the NI Digital Electronics FPGA Board USB cable to the NI Digital Electronics FPGA Board USB connector and the other end to the USB connector on the host PC 3 Power on NI ELVIS II Series workstation 4 Power on the NI Digital Electronics FPGA Board by moving the power switch to the ON position Windows XP Windows recognizes any newly inst
47. ments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of others and we ask our users to do the same NI software is protected by copyright and other intellectual property laws Where NI software may be used to reproduce software or other materials belonging to others you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction Trademarks National Instruments NI ni com and LabVIEW are trademarks of National Instruments Corporation Refer to the Terms of Use section on ni com legal for more information about National Instruments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no
48. mputer window select New target or device expand ELVIS and highlight DE FPGA Board Click OK The target is discovered and the target and target properties are loaded into the project tree In the Project Explorer window right click FPGA Target Board1 DE FPGA Board and select New FPGA I O The New FPGA I O window opens In the Available Resources pane expand Slide Switches and select SWO Click Add to move SWO to the New FPGA I O pane This adds this FPGA resource to the project Expand Push Buttons and select BTNO Click Add to move BTNO to the New FPGA I O pane Expand LEDs and select LEDO and LED2 Click Add to move the LEDs to the New FPGA I O pane Click OK Notice that the selected FPGA resources were added to the FPGA Target tree in the Project Explorer window as shown in Figure 3 1 NI Digital Electronics FPGA Board User Manual 3 2 ni com Chapter 3 Programming with LabVIEW Software Project Explorer FPGA_Design lvproj DER Eile Edit View Project Operate Tools Window Help Items Files E a Project FPGA_Design lwproj S E My Computer OnboardClock Dependencies e Build Specifications TP Dependencies h Build Specifications Figure 3 1 FPGA Target Tree with New FPGA Resources 8 Inthe Project Explorer window right click FPGA Target Board1 DE FPGA Board and select New VI A blank VI opens Select the block diagram window 9 Inthe Project Explorer window FPGA Target Board1
49. n take minutes to hours You can test the logic of an FPGA VI written for the NI Digital Electronics FPGA Board before compilation by running the FPGA VI on a development computer with simulated I O When you run an FPGA VI on a development computer with simulated I O LabVIEW generates random data for the inputs or uses a custom VI that you create to simulate I O You can use all traditional LabVIEW debugging techniques such as probes execution highlighting breakpoints and single stepping You cannot test certain aspects of VI behavior such as timing and determinism For detailed information about running an NI Digital Electronics FPGA Board VI in emulation mode including software examples refer to the Developer Zone document Running a Digital Electronics FPGA Board VI in Emulation Mode on a Development Computer To access this document go to ni com info and enter the info code defbem Programming the PROM To change the default FPGA power up application you must download the LabVIEW FPGA VI to the FPGA flash PROM by completing the following steps 1 In the Project Explorer right click the target VI and select Download VI to Flash Memory 2 LabVIEW displays the programming process When the LabVIEW FPGA window displays Download successful click OK You can return to the default power up configuration by using the Flash_Image example located in the LabVIEW 8 6 examples DE FPGA Board folder NI Digital Electronics
50. nents XX LA 390 K ANNA D LDO Ri LDO R2 il AM 4 2K 3 QUA IS 390 AMAN D R11 a Ais A LD1 ANN It Aa 2K H 3 08 I 390 K ANNA 1D LD2 RIS R14 LD2 ee 2K A Hyg 06A eu 390 K AN D R23 LD3 R24 E i MY H 3 068 IS 390 KI AMS D R25 LD4 R26 LD4 Ta 2K A HS Q7A APRES XX 390 K 2 LD5 4 LD5 R34 1 AMAN 44 2K Q7B Ss 390 K ANA D R35 tbe Bae HD LD6 ANS 4 2K Q13A O AR LA A VCC3V3 N D R37 a nae LD7 ANS 4 2K Q13B 5 GND NI Digital Electronics FPGA Board User Manual Each LED is connected on one side through a 390 Q current limiting Figure 2 4 LEDs Circuit Diagram resistor to the power line and connected on the other side through a CMOS driver as shown in Figure 2 4 You can access the LED lines through the signal breadboard BB3 To light an individual LED drive the associated line High 3 3 V or 5 V For more information about the signal breadboards refer to the Signal Breadboard 2 8 ni com Chapter 2 Hardware Components Area section The LEDs are also connected directly to the FPGA lines To light an individual LED drive the associated FPGA control signal High Refer to the UCF File Constraints section of Chapter 4 Programming with Xilinx iMPACT Software for more information about accessing the FPGA signals in iMPACT Tw
51. o Digit Seven Segment Display The NI Digital Electronics FPGA Board has a two digit seven segment display DISP1 in a common cathode configuration Refer to Figure 2 1 for the location of the two seven segment display The two digit seven segment display circuitry is shown in Figure 2 5 SEGDO SEGCO SEGBO SEGAO SEGA1 SEGB1 SEGC1 SEGD1 o 23 EX EX 23 E 83h 235 23 GND GND o o o o o o o o T T T FE ya aT aT ao Al ao po N pe A N pt Q N po ao pt Q pt a ao lt a lt Q lt Q lt 00 a a se t t wo WQ G ej G ej O ago oso EO N o Sir Sie 83E 83 ns HS 38 BS 16 CA1 ca2 H 15 CB1 cB2 10 3 CC1 cc2 8 2 CD1 cp2 6 1 CE1 CE2 5 18 CF1 CF2 12 17 CG1 CG2 Z CDP1 cpp2 9 m o 14 AN1 AN2 13 x o o o oso o o 858 g38 RSs 835 838 oso EST ESA se u a DISP1 FSE a FSE g sia 00 o oo gt mM Cos G G G O VCC3V3 O G O ta af lo af lo af Ju of le af a al uw ale alo ivi ly y a al vi LY ly o a o o o o o o GND GND o o a Sy x Ose esx 3x Six ox BRZAZA Bx Es Ex Ox D13 SEGEO SEGFO SEGGO COMO GND COM1 SEGG1 SEGF1 SEGE1 Figure 2 5 Two Digit Seven Segment Display Circuit Diagram Nation
52. ons VCC3V3 A ss os 2x ox BSS 35 238 B35 R52 GND WY L 470 BTNO R53 Ae 11 470 BTN1 R56 LA e AM a 470 pine MW 4 470 BINS c1 c2 c3 c4 470nF 470nF 470nF 470nF Figure 2 3 Push Buttons Circuit Diagram Pressing a push button connects a logic Low into an inverter which outputs a logic High of 3 3 V into the associated line as shown in Figure 2 3 When the push button is not pressed the power line goes into the inverter which outputs a logic Low into the associated line Debouncing circuitry is implemented using a resistor and a capacitor on the push button signal line NI Digital Electronics FPGA Board User Manual 2 6 ni com Chapter 2 Hardware Components You can access the push button lines through the signal breadboard BB1 For more information about the signal breadboards refer to the Signal Breadboard Area section The buttons are also connected directly to the FPGA lines Refer to the UCF File Constraints section of Chapter 4 Programming with Xilinx iMPACT Software for more information about accessing the FPGA signals in iMPACT LEDs The NI Digital Electronics FPGA Board has eight individual surface mount LEDs LDO through LD7 shown in Figure 2 1 Figure 2 4 shows the circuitry of the LEDs National Instruments Corporation 2 7 NI Digital Electronics FPGA Board User Manual Chapter 2 Hardware Compo
53. ramming with LabVIEW Software Building a LabVIEW FGPA Design ss 3 1 Creating ProjeCl icono aliada cita 3 1 Creating an FPGA Target VL ssel uses urnes 3 2 Running the FPGA VI tint hacked tends Asia nent 3 4 More LabVIEW Example Programs ss 3 5 LabVIEW FPGA and CLIP curia nt aiid alicia aed 3 5 Adding User Defined CLIP to an FPGA Target 3 5 Running a VI in Emulation Mode ss 3 6 Programming the PROM icc serment msn deadeass odia a stands 3 6 Testing the Download nus Haba 3 7 Where to Go from Here cesseiascaccisascisecessatascdesstacsvessadescasesspees ibaz caves sdbescaucesedescadeasitestess 3 7 Chapter 4 Programming with Xilinx iMPACT Software Xilinx IMPACT Software Examples 4 1 UCF File Constr tiennent diet AN M te ed Ae Ct eae 4 1 Slide Witches cria tient steve baat nee M mnt 4 1 Push Buttons is sit in 4 2 LEEDS nes a MAPS rd Cea Ce 4 2 Seven Segment Displays cons 4 2 50 MHz Clock Input Source sise 4 3 Programming the PROM ntm nie ind deis 4 3 T sunp th Downlo ds ss et annales teurs 4 6 Where to Go from re tente la 4 6 Appendix A Specifications Appendix B Technical Support and Professional Services Index NI Digital Electronics FPGA Board User Manual vi ni com Overview and Setup The NI Digital Electronics FPGA Board is a circuit development platform based on the XC3S500E Xilinx Spartan 3E FPGA Besides the FPGA the board contains
54. selecting Start All Programs National Instruments Lab VIEW LabVIEW Manuals LabVIEW FPGA IPNet Offers resources for browsing understanding and downloading LabVIEW FPGA functions or IP Intellectual Property Use this resource to acquire IP that you need for your application download examples to help learn programming techniques and explore the depth of IP offered by the LabVIEW FPGA platform To access the LabVIEW FPGA IPNet visit ni com ipnet 3 7 NI Digital Electronics FPGA Board User Manual Programming with Xilinx iMPACT Software After you install the software and set up the hardware for stand alone mode as described in Chapter 1 Overview and Setup you are ready to program with Xilinx iMPACT software This chapter lists information necessary to program the NI Digital Electronics FPGA Board with Xilinx iMPACT Xilinx iMPACT Software Examples For detailed information about Xilinx iMPACT software examples for the NI Digital Electronics FPGA Board refer to the Developer Zone document Xilinx iMPACT Examples To access this document go to ni com info and enter the info code impactex You can also refer to the Xilinx University Program Web site at www xilinx com univ UCF File Constraints Slide Switches This section lists the UCF file uc constraints for the various hardware components of the NI Digital Electronics FPGA Board Refer to Chapter 2 Hardware Components for more information about th
55. slide switches LEDs a two digit seven segment display push buttons a rotary push button knob and LEDs for one external clock Digilent Pmod terminals for external attachments USB download interface and large breadboard area for digital electronics circuitry experimentation Safety Information The following section contains important safety information that you must follow when installing and using the hardware Do not operate the hardware in a manner not specified in this document and in the user documentation Misuse of the hardware can result in a hazard You can compromise the safety protection if the hardware is damaged in any way If the hardware is damaged return it to National Instruments for repair Clean the hardware with a soft nonmetallic brush Make sure that the hardware is completely dry and free from contaminants before returning it to service Do not substitute parts or modify the hardware except as described in this document Use the hardware only with the chassis modules accessories and cables specified in the installation instructions or specifications You must have all covers and filler panels installed during operation of the hardware Do not operate the hardware in an explosive atmosphere or where there may be flammable gases or fumes unless the hardware is UL U S or Ex EU Certified and marked for hazardous locations The hardware must be in a suitably rated IP 54 minimum enclosure for hazardous lo
56. the NI Digital Electronics FPGA Board can damage the board components if ESD prevention measures are not applied Before handling or setup equalize your potential with the board by touching one of the integrated ESD discharge pads During all handling and setup ESD prevention measures must be applied In addition the NI Digital Electronics FPGA Board should be handled by the edges Touching exposed circuits components or connectors could result in an ESD event When setting up the NI Digital Electronics FPGA Board observe the following guidelines to minimize the potential impact of ESD e Assemble desired custom circuitry in the breadboard area e Set switches and other controls to initial settings e If desired connect the NI Digital Electronics FPGA Board to a computer by using the USB port e Plug the power adapter into the 15 VDC power supply port e Plug the AC DC power supply brick into an appropriate AC outlet Move the board power switch ON When operating the NI Digital Electronics FPGA Board ESD can cause upset as well as damage to the board components Therefore apply ESD prevention measures whenever operating the NI Digital Electronics FPGA Board In addition observe the following guidelines e Do not manipulate or change the circuitry the breadboard area while the board is powered on e Do not touch exposed traces or components on the board while the board is powered on e Exercise caution when manipulating sw
57. tion Operations i PE Processes Configuration Operations Whats New in ISE Design Sute 10 1 Design Summary M Boundary Scan Ara 21 Programming completed successfully mm PROGRESS END End Operation Elapsed time 13 sec e gt E Console Enos g Wamings MTciShel gg Find in Files script Tra Configuration Platform Cable USB 6 MHz usb hs Figure 4 2 PROM ise Project Window Boundary Scan 11 Right click the xcf04s myplatformflash mes icon and select Program 12 In the Device Programming Properties window select Device 2 PROM xcf04s the PROM type to be programmed 13 Put a check mark in the following Device Programming Properties options Verify Verifies the PROM is correctly programmed and matches the downloaded configuration bitstream This option is recommended though it increases overall programming time e Erase Before Programming Erases the platform flash PROM completely before programming ensuring that no previous data lingers This option is recommended though it increases overall programming time Load FPGA Forces the FPGA to reconfigure after programming the platform flash PROM National Instruments Corporation 4 5 NI Digital Electronics FPGA Board User Manual Chapter 4 Programming with Xilinx iMPACT Software Click OK A Progress Dialog window opens and displays the execution progress After the PROM is successfully pro

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