FPD- Link LVDS to FPD-Link II Embedded Clock LVDS Converter
Contents
1. 25 SERIALIZER TX PCB SCHEMATIC 25 DE SERIALIZER RX PCB SCHEMATIC 28 SERIALIZER TX PCB LAYOUT 32 SERIALIZER TX PCB STACKUP 35 DESERIALIZER RX PCB LAYOUT 36 DESERIALIZER RX PCB STACKUP 39 National Semiconductor Corporation Date 5 12 2008 Page 3 of 39 Introduction National Semiconductor s DS99R421 standard multi channel LVDS to FPD Link II translator SERDES evaluation kit contains 1 DS99R421 translator board and 1 DS90UR124 De serializer Rx board and 1 two 2 meter high speed USB 2 0 cable Note the evaluation boards are not for EMI testing The evaluation boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals2. Typical Connection Diagram Rx User Quick Reference ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 ROUT10 ROUT11 ROUT12 ROUT13 ROUT14 ROUT15 ROUT16 ROUT17 ROUT18 ROUT19 ROUT20 ROUT21 ROUT22 ROUT23 RCLK RPWDNB REN RRFB RESRVD RIN RIN VDDOR2 VDDOR3 VDDR1 VDDR0 VDDPR1 VDDPR0 RPWDNB System GPO REN High ON RRFB High Rising edge RESRVD Low GPO 3 3V 3 3V DS90C124 DES C1 C2 C3 C4 C9 C10 R1 C5 C6 VDDIR VDDOR1 LOCK C8 C7 3 3V C1 to C8 0 1 F to 0 01 F C9 100 nF 50 WVDC NPO or X7R C10 100 nF 50 WVDC NPO or X7R R1 100 Serial LVDS Interface LVCMOS Parallel Interface Note VDDs can be combined into a minimum of four 4 groupings as shown above Analog PLL VCO Digital Logic Analog LVDS Digital LVCMOS O P Decoupling specified C1 C8 is the minimum that should be used Figure 7 Typical DS90C124 Rx SERDES Hookup Serial FPD Link II Interface National Semiconductor Corporation Date 5 12 2008 Page 23 of 39 Troubleshooting If the demo boards are not performing properly use the following as a guide for quick solutions to potential problems If the problem persists please contact the local Sales Representative for assistance QUICK CHECKS 1 Check that Power and Ground are connected to both Tx AND Rx boards 2 Check the supply voltage typical 3 3V and also current draw with both Tx and
3. 15 1 P2 USB A USB_TYPE_A_4P 16 1 R5 100 ohm 0402 RES HDC 0402 17 1 R8 5 76K RES HDC 0402 18 7 R10 R11 R12 R13 R14 R15 0 Ohm 0402 RES HDC 0402 R16 19 4 R18 R20 R21 R23 10K RES HDC 0805 20 1 S1 SW DIP 4 DIP 8 21 1 U1 DS99R421 36 ld LLP socket 22 1 VR1 SVR20K Surface Mount 4mm Square 23 2 X2 X1 TP_0402 TP 0402 National Semiconductor Corporation Date 5 12 2008 Page 13 of 39 DS90UR124 Rx De serializer Board The USB connector J2 mini USB on the topside of the board provides the interface connection for FPD Link II signals to the Serializer board Note J1 mini USB on the bottom side is un stuffed and not used with the cable provided in the kit The SERDES de serializer board is powered externally from the J4 VDD and J5 VSS connectors shown below For the de serializer to be operational the Power Down RPWDNB and Receiver Enable REN switches on S1 and S2 must be set HIGH Rising or falling edge reference clock is also selected by S1 HIGH rising or LOW falling The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs J4 J5 FPD Link II INPUTS LVCMOS OUTPUTS FUNCTION CONTROLS POWER SUPPLY J3 S1 JP3 Note Vcc and Gnd MUST be applied externally here J2 JP4 S2 J1 BACKSIDE UNSTUFFED National Semiconductor Corporation Date 5 12 2008 Page 14 of 39 Configuration Settings for the De serializer Board Table 4 S1 S2 De serializer Inp
4. LAYER 3 SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 National Semiconductor Corporation Date 5 12 2008 Page 38 of 39 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 PRIMARY COMP SIDE SOLDER PASTE LAYER 1 PRIMARY COMP SIDE SILKSCREEN LAYER 1 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 5 12 2008 Page 39 of 39 Deserializer Rx PCB Stackup IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer pr
5. National Semiconductor Corporation Date 5 12 2008 Page 1 of 39 FPD to Serdes UR Translator Chip DS99R421 Evaluation Kit User s Manual NSID FPDXSDUR 43USB Rev 0 0 National Semiconductor Corporation Date 5 12 2008 Page 2 of 39 Table of Contents TABLE OF CONTENTS 2 INTRODUCTION 3 CONTENTS OF THE EVALUATION KIT 4 SERDES TYPICAL APPLICATION 4 HOW TO SET UP THE EVALUATION KIT 6 EVALUATION BOARD POWER CONNECTION 6 DS99R421 TRANSLATOR BOARD DESCRIPTION 7 CONFIGURATION SETTINGS FOR THE SERIALIZER BOARD 8 TRANSLATOR INPUT LVDS AND OUTPUT FPD LINK II PIN
6. do not trigger on the probe monitoring the serial stream National Semiconductor Corporation Date 5 12 2008 Page 17 of 39 De serializer LVDS Pinout and LVCMOS by IDC Connector The following two tables illustrate how the LVDS inputs are mapped to the mini USB connector J2 and the Rx outputs are mapped to the IDC connector J3 Note labels are also printed on the demo boards for both the LVDS inputs and TTL outputs LVDS INPUT TTL OUTPUT J2 pin no Symbol J3 pin no Symbol 1 RED 1 ROUT0 2 DIN 3 ROUT1 3 DIN 5 ROUT2 4 NC 7 ROUT3 5 BLK 9 ROUT4 11 ROUT5 13 ROUT6 15 ROUT7 17 ROUT8 19 ROUT9 21 ROUT10 23 ROUT11 25 ROUT12 27 ROUT13 29 ROUT14 31 ROUT15 33 ROUT16 35 ROUT17 37 ROUT18 39 ROUT19 41 ROUT20 43 ROUT21 45 ROUT22 47 ROUT23 49 TCLK all even pins VSS TTL OUTPUT JP3 pin no Symbol 1 LOCK PLL 2 VSS TTL OUTPUT JP4 pin no Symbol 1 PASS BIST 2 VSS National Semiconductor Corporation Date 5 12 2008 Page 18 of 39 BOM Bill of Materials De serializer PCB DS90UR124 Rx USB Demo Board Board Stackup Revised Monday October 23 2006 DS90UR124 Rx USB Demo Board Revision 1 Bill Of Materials October 23 2006 Item Qty Reference Part PCB Footprint ______________________________________________ 1 2 C2 C1 0 1uF CAP HDC 0402 2 27 C3 C7 C8 C9 C10 C11 C12 open0402 CAP HDC 0402 C13 C14 C15
7. C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C42 3 1 C4 2 2uF 3528 21_EIA 4 1 C5 22uF CAP N 5 1 C6 0 1uF CAP HDC 1206 6 8 C32 C33 C34 C41 C47 C50 22uF CAP EIA B 3528 21 C53 C54 7 8 C35 C38 C40 C43 C46 C48 0 1uF CAP HDC 0603 C52 C55 8 8 C36 C37 C39 C44 C45 C49 0 01uF CAP HDC 0603 C51 C56 9 2 JP2 JP1 3 Pin Header Header 3P 10 2 JP4 JP3 2 Pin Header_open Header 2P 11 1 J1 mini USB 5pin_open mini_USB_surface_mount 12 1 J2 Hirose GT17H 4P 2H Hirose GT17H 4P 2H 13 1 J3 IDC2X25_Unshrouded IDC 50 14 2 J4 J5 BANANA CON BANANA S 15 1 LED1 0402_orange_LED 0402 16 1 LED2 0603_green_LED 0603 Super Thin 17 1 R1 100 ohm 0402 RES HDC 0402 18 9 R2 R3 R4 R34 R35 R36 R37 10K RES HDC 0805 R38 R39 19 1 S1 SW DIP 3 DIP 6 20 1 S2 SW DIP 6 DIP 12 21 1 U1 DS90UR124 64 pin TQFP National Semiconductor Corporation Date 5 12 2008 Page 19 of 39 Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller with 18 bit RGB LVDS output 2 Astro Systems VG 835 This video generator may be used for video signal sources for 18 bit RGB LVDS output 3 Any other signal video generator that generates the correct input levels as specified in the datasheet 4 Op
8. OUT BY IDC CONNECTOR 11 BOM BILL OF MATERIALS TRANSLATOR PCB 12 DS90UR124 RX DE SERIALIZER BOARD 13 CONFIGURATION SETTINGS FOR THE DE SERIALIZER BOARD 14 OUTPUT MONITOR PINS FOR THE DE SERIALIZER BOARD 15 DE SERIALIZER LVDS PINOUT AND LVCMOS BY IDC CONNECTOR 17 BOM BILL OF MATERIALS DE SERIALIZER PCB 18 TYPICAL CONNECTION AND TEST EQUIPMENT 19 TYPICAL CONNECTION DIAGRAM DS99R421 USER QUICK REFERENCE 21 TYPICAL CONNECTION DIAGRAM RX USER QUICK REFERENCE 22 TROUBLESHOOTING 23 APPENDIX
9. PER IN JP3 unlocked PLL LOCKED LED2 will illuminate JP4 PASS Monitor Reference Description Output L Output H JP4 PASS Receiver BIST monitor PASS flag Note DO NOT PUT A SHORTING JUMPER IN JP1 FAIL PASS LED1 will illuminate National Semiconductor Corporation Date 5 12 2008 Page 16 of 39 Table 6 JP1 JP2 USB Red and Black wire Reference Description VDD VSS OPEN JP1 Power wire in USB cable thru J2 and J1 not mounted connector Jumper RED to VSS recommended Note Normally VDD in USB application Red wire tied to VDD Red wire tied to VSS Default Red wire floating not recommended JP2 Power wire in USB cable thru J2 and J1 not mounted connector Jumper BLACK to VSS recommended Note Normally VSS in USB application Black wire tied to VDD Black wire tied to VSS Default Black wire floating not recommended NO connect J2 pin 1 pin 5 BLACK WIRE mini USB top side view mounted on component side RED WIRE pin 4 pin 3 pin 2 _ The following picture depicts a typical example of the FPD Link II serial stream This snapshot was taken with a differential probe across the 100 ohm termination resistor R1 on the DS90UR124 Rx evaluation board R1 is the termination resistor to the RxIN Note The scope was triggered with a separate probe on TCLK the input clock into the DS90UR241 Tx To view the serial stream correctly
10. Rx boards The Serializer board should draw about 55 65mA with clock and all data bits switching at 43MHz RPRE 9K The De serializer board should draw about 75 85mA with clock and all data bits switching at 43MHz minimum ROUT loading 3 Verify input clock and input data signals meet requirements for VILmin VILmax VIHmin VIHmax tset thold also verify that data is strobed on the selected rising falling RFB pin edge of the clock 4 Check that the Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING CHART Problem Solution There is only the output clock There is no output data Make sure the data is applied to the correct input pin Make sure data is valid at the input No output data and clock Make sure Power is on Input data and clock are active and connected correctly Make sure that the cable is secured to both demo boards Power ground input data and input clock are connected correctly but no outputs Check the Power Down pins of both Translator and De serializer boards to make sure that the devices are enabled PD Vcc for operation Also check DEN on the Serializer board and REN on the Deserializer board is set HIGH The devices are pulling more than 1A of current Check for shorts in the cables connecting the Translator and RX boards After powering up the demo boards the power supply reads less than 3V when it is set to 3 3V Use a la
11. additional pads for termination loading and multiple connector options The DS99R421 and DS90UR124 chipset supports a variety of display and general purpose applications The single FPD Link II interface is well suited for any display system interface Typical applications include navigation displays automated teller machines ATMs POS video cameras global positioning systems GPS portable equipment instruments factory automation etc The DS99R421 can be used to take existing standard multi channel LVDS and convert them to a single channel FPD Link II format DS99R421 can be used as a 21 bit general purpose LVDS translator used in conjunction with the DS90UR124 FPD Link II De serializer chipset and transmit data at clocks speeds ranging from 5 to 43 MHz The DS99R421 LVDS to FPD Link II translator board accepts four 4 standard LVDS multi channel LVDS input signals and converts them into a single serialized FPD Link II data pair with an embedded LVDS clock The serial data stream toggles at 28 times the base clock rate with an input clock at up to 43 MHz The maximum transmission rate for the FPD Link II line is 1 204Gbps The DS90UR124 de serializer board accepts the FPD Link II serialized data stream with embedded clock and converts the serialized data back into parallel 3 3V_LVCMOS signals and clock Note that NO reference clock is needed to prevent harmonic lock Suggested equipment to evaluate the chipset are a standard LVDS signal source
12. board provides the interface connection to the FPD Link II signals to the De serializer board Note P1 mini USB on the top side is un stuffed and not to be used with the cable provided in the kit Note VDD and VSS MUST be applied externally from here J4 J5 FPD Link II OUTPUT LVDS INPUTS LVCMOS INPUTS FUNCTION CONTROLS POWER SUPPLY 100 FPD Link II OUTPUT VR1 JP6 J1 S1 P2 BACKSIDE Note Connect cable to P2 on BACKSIDE P1 TOPSIDE UNSTUFFED NOT FOR EMI TESTING JP7 R5 NOT FOR EMI TESTING NOT FOR EMI TESTING National Semiconductor Corporation Date 5 12 2008 Page 8 of 39 Configuration Settings for the Serializer Board Table 1 S1 Serializer Input Features Selection Reference Description Input L Input H S1 PWDNB PoWerDowN Bar Powered Down Normal operation Default DEN Serializer Output Data ENabled Disabled Enabled Default VODSEL LVDS output VOD SELect 350mV Default 700mV BISTEN BIST ENabled BIST DISABLED MUST be low for normal operation Default BIST ENABLED Note DS90UR124 BISTEN MUST also be set High see datasheet for operational modes National Semiconductor Corporation Date 5 12 2008 Page 9 of 39 Table 2 JP6 VR1 Pre Emphasis Feature Selection Reference Description OPEN floating CLOSED Path to GND JP6 Pre Emphasis helps to increase the eye pattern opening in the LVDS stream Disabl
13. board to the panel 3 Power for the Tx and Rx boards must be supplied externally through Power Jack VDD Grounds for both boards are connected through Power Jack VSS see section below Evaluation Board Power Connection The translator and de serializer boards must be powered by supplying power externally through J3 VDD and J4 VSS on the translator board and J4 VDD and J5 VSS on de serializer board Note 4V is the absolute MAXIMUM voltage not operating voltage that should ever be applied to the translator DS99R421 or de serializer DS90UR124 VDD terminal Damage to the device s can result if the voltage maximum is exceeded 1 3 4 2 A 1 2 3 4 MIN National Semiconductor Corporation Date 5 12 2008 Page 7 of 39 DS99R421 Translator Board Description The 20 pin IDC connector J1 accepts standard 18 bit 3 channels of LVDS RGB data RxIN0 RxIN1 RxIN2 and clock RxCLK The 100 ohm terminations are integrated in the DS99R421 LVDS RxIN inputs so no external resistors are required The translator board is powered externally from the J3 VDD and J4 VSS connectors shown below For the serializer to be operational the Power Down S1 PWDNB and Data Enable S1 DEN switches on S1 must be set HIGH The board is factory configured JP1 and JP2 are configured from the factory to be shorted to VSS these are the unused power wires in the cable harness The USB connector P2 USB A side on the bottom side of the
14. ed no jumper Default Enabled With jumper JP6 amp VR1 Pre Emphasis adjustment via screw JP6 MUST have a jumper to use VR1 potentiometer VR1 0 to 20K JP6 VR1 6K R6 6K maximum pre emphasis to 26K minimum pre emphasis IPRE 1 2 RPRE x 40 RPRE minimum gt 6K Note maximum is based on resistor value In this case 26K value is based on the 6k fixed resistor plus 20K maximum potentiometer value User can use hundreds of Kohms to reduce the pre emphasis value Clockwise increases RPRE value which decreases pre emphasis Counter Clockwise decreases RPRE value which increases pre emphasis Pre emphasis user note Pre emphasis must be adjusted correctly based on application frequency cable quality cable length and connector quality Maximum pre emphasis should only be used under extreme worse case conditions for example at the upper frequency specification of the part and or low grade cables at maximum cable lengths Typically all that is needed is minimum pre emphasis Users should start with no pre emphasis first and gradually apply pre emphasis until there is clock lock and no data errors The best way to monitor the pre emphasis effect is to hook up a differential probe to the 100 termination resistor R1 on the DS90UR124 Rx demo board NOT to R5 on the DS99R421 demo board The reason for monitoring R1 on the Rx side is because yo
15. ink II outputs LVDS INPUT FPD Link II OUTPUT P1 J1 pin no Symbol P3 pin no Symbol topside 1 VSS 1 RED not mounted 2 RxIN0 2 DOUT FPD Link II OUTPUT 3 RxIN0 3 DOUT pin no name 4 VSS 4 BLK 5 JP2 5 VSS 4 NC 6 RxIN1 3 DOUT 7 RxIN1 2 DOUT 8 VSS 1 JP1 9 VSS 10 RxIN2 11 RxIN2 12 VSS 13 VSS 14 RxCLKIN 15 RxCLKIN 16 VSS 17 VSS 18 NC 19 NC 20 VSS OS INPUT 3 3v_LVCMOS JP3 pin no Symbol 1 OS1 2 VSS 3 OS2 4 VSS 5 OS3 6 VSS National Semiconductor Corporation Date 5 12 2008 Page 12 of 39 BOM Bill of Materials Translator PCB DS99R421 Xlator Bench Board Board Stackup Revised Friday February 29 2008 DS99R421 Xlator Bench Board Revision 1 Bill Of Materials February 29 2008 18 31 46 Item Qty Reference Part PCB Footprint 1 2 C1 C2 0 1uF CAP HDC 0402 2 1 C18 22uF CAP N 3 1 C19 2 2uF 3528 21_EIA 4 1 C20 0 1uF CAP HDC 1206 5 7 C21 C22 C23 C30 C33 C36 22uF CAP EIA B 3528 21 C41 6 7 C24 C26 C28 C32 C35 C37 0 1uF CAP HDC 0603 C40 7 7 C25 C27 C29 C31 C34 C38 0 01uF CAP HDC 0603 C39 8 2 JP2 JP1 3 Pin Header Header 3P 9 1 JP2 2 Pin Header Header 2P 10 1 JP3 2X3 Pin Header Header 2X3P 11 1 J1 2X10 Pin Header open Header 2X10P 12 1 J2 2mm_2X5 CON HDR 10P B 13 2 J5 J4 BANANA CON BANANA S 14 1 P1 mini USB 5pin_open mini_B_USB_surface_mount
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18. lor depth TFT LCD Panels Refer to the proper datasheet information on chipset provided on each board for more detailed information National Semiconductor Corporation Date 5 12 2008 Page 6 of 39 How to set up the Evaluation Kit The PCB routing for the translator LVDS input pins RxIN have been laid out to plug directly into FPD HSL Tx demo board note only 6 bit mapping is used The FPD Link II TxOUT RxIN DOUT RIN interface uses a standard USB 2 0 connector cable assembly The PCB routing for the Rx output pins ROUT are accessed through a 50 pin IDC connector Please follow these steps to set up the evaluation kit for bench testing and performance measurements 1 A two 2 meter high speed USB 2 0 cable has been included in the kit Connect the 4 pin USB A side of cable harness to the DS99R421 board and the other side the 5 pin mini USB jack to the DS90UR124 de serializer board This completes the FPD Link II interface connection NOTE The DS99R421 and DS90C124 are NOT USB compliant and should not be plugged into a USB device nor should a USB device be plugged into the evaluation boards 2 Jumpers and switches have been configured at the factory they should not require any changes for immediate operation of the chipset See text on Configuration settings for more details From the Video Decoder board connect a flat cable not supplied to the translator board and connect another flat cable not supplied from the De serializer
19. nductor Corporation Date 5 12 2008 Page 26 of 39 National Semiconductor Corporation Date 5 12 2008 Page 27 of 39 National Semiconductor Corporation Date 5 12 2008 Page 28 of 39 De serializer Rx PCB Schematic National Semiconductor Corporation Date 5 12 2008 Page 29 of 39 National Semiconductor Corporation Date 5 12 2008 Page 30 of 39 National Semiconductor Corporation Date 5 12 2008 Page 31 of 39 National Semiconductor Corporation Date 5 12 2008 Page 32 of 39 Serializer Tx PCB Layout TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date 5 12 2008 Page 33 of 39 PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 National Semiconductor Corporation Date 5 12 2008 Page 34 of 39 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 PRIMARY COMP SIDE SOLDER PASTE LAYER 1 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 5 12 2008 Page 35 of 39 Serializer Tx PCB Stackup National Semiconductor Corporation Date 5 12 2008 Page 36 of 39 Deserializer Rx PCB Layout TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date 5 12 2008 Page 37 of 39 PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD
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21. rger power supply that will provide enough current for the demo boards a 500mA minimum power supply is recommended National Semiconductor Corporation Date 5 12 2008 Page 24 of 39 Note Please note that the following references are supplied only as a courtesy to our valued customers It is not intended to be an endorsement of any particular equipment or hardware supplier Connector References Hirose Electric Europe B V Beech Avenue 46 1119 PV Schiphol Rijk The Netherlands Phone 31 20 655 7467 Fax 31 20 655 7469 www HiroseEurope com Cable References Nissei Electric Co LTD 1509 Okubo Cho Hamamatsu City Shizuoka Pref 432 8006 Japan Phone 81 53 485 4114 Fax 81 53 485 6908 www nissei el co jp Cable Recommendations For optimal performance we recommend Shielded Twisted Pair STP 100 differential impedance cable for high speed data applications Equipment References Astro Systems 425 S Victory Blvd Suite A Burbank CA 91502 Phone 818 848 7722 Fax 818 848 7799 www astro systems com Digital Video Pattern Generator Astro Systems VG 835 or equivalent Extra Component References TDK Corporation of America 1740 Technology Drive Suite 510 San Jose CA 95110 Phone 408 437 9585 Fax 408 437 9591 www component tdk com Optional EMI Filters TDK Chip Beads or equivalent National Semiconductor Corporation Date 5 12 2008 Page 25 of 39 Appendix Serializer Tx PCB Schematic National Semico
22. such as a video generator or FPD or Channel Link or equivalent transmitter and or word generator or pulse generator and oscilloscope with a bandwidth of at least 43 MHz will be needed The user needs to provide the standard multi channel LVDS inputs to the LVDS translator and also provide a proper interface from the de serializer output to an LCD panel or test equipment The translator and de serializer boards can also be used to evaluate device parameters A cable conversion board or harness scramble may be necessary depending on type of cable connector interface used on the input to the DS99R421 and to the output of the DS90UR124 Example of suggested display setup 1 video generator with an 18 bit data LVDS output 2 18 bit LCD panel with a 3 3V_LVCMOS input interface National Semiconductor Corporation Date 5 12 2008 Page 4 of 39 Contents of the Evaluation Kit 1 One DS99R421 LVDS to FPD Link II translator board 2 One DS90UR124 De serializer board 3 One 2 meter high speed USB 2 0 cable 4 pin USB A to 5 pin mini USB 4 Evaluation Kit Documentation this manual 5 DS99R421 and DS90UR241 124 Datasheet SERDES Typical Application Figure 1a Typical Application 18 bit RGB Color Figure 1b Typical SERDES System Diagram National Semiconductor Corporation Date 5 12 2008 Page 5 of 39 Figures 1a and 1b illustrate the use of the chipset DS99R421 DS90UR124 in a Host to Flat Panel Interface The chipsets support up to 18 bit co
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24. tional Logic Analyzer or Oscilloscope The following is a list of typical test equipment that may be used to monitor the output signals from the RX 1 LCD Display Panel which supports digital RGB 3 3V_LVCMOS inputs 2 National Semiconductor DS99R421 LVDS to FPD Link II translator 3 Optional Logic Analyzer or Oscilloscope 4 Any SCOPE with a bandwidth of at least 43MHz for TTL and or 2GHz for looking at the differential signal LVDS signals may be easily measured with high impedance high bandwidth differential probes such as the TEK P6330 differential probes National Semiconductor Corporation Date 5 12 2008 Page 20 of 39 The picture below shows a typical test set up using a Graphics Controller and LCD Panel Figure 2 Typical SERDES Setup of LCD Panel Application The picture below shows a typical test set up using a generator and scope Figure 3 Typical SERDES Test Setup for Evaluation National Semiconductor Corporation Date 5 12 2008 Page 21 of 39 Typical Connection Diagram DS99R421 User Quick Reference Note VDDs can be combined into four 4 groupings as shown top to bottom 1 Analog LVDS 2 Digital 3 Analog FPD Link II and 4 Analog PLL VCO for best performance Absolute minimum grouping should be Analog Power and Digital Power Decoupling specified C1 C8 is the minimum that should be used Figure 6 Typical DS90C241 Tx SERDES Hookup National Semiconductor Corporation Date 5 12 2008 Page 22 of 39
25. u want to see what the receiver will see the attenuation signal AFTER the cable connector National Semiconductor Corporation Date 5 12 2008 Page 10 of 39 Table 3 JP5 JP8 USB Red and Black wire Reference Description VDD VSS OPEN JP5 Power wire in USB cable thru P2 and P1 not mounted connector Jumper RED to VSS recommended Note Normally VDD in USB application Red wire tied to VDD Red wire tied to VSS Default Red wire floating not recommended JP8 Power wire in USB cable thru P2 and P1 not mounted connector Jumper BLACK to VSS recommended Note Normally VSS in USB application Black wire tied to VDD Black wire tied to VSS Default Black wire floating not recommended pin 2 RED WIRE BLACK WIRE _ pin 4 P2 USB A pin 3 pin 1 top side thru the board view mounted on solder side National Semiconductor Corporation Date 5 12 2008 Page 11 of 39 Translator Input LVDS and Output FPD Link II Pinout by IDC Connector The following four tables illustrate how the LVDS inputs are mapped to the IDC connector J1 the FPD Link II outputs on the USB A connector P3 and the mini USB P1 not mounted pinouts There are also three 3 3 3V_LVCMOS over sampled bits OS1 OS2 OS3 extra unused bits not required for operation see datasheet for description of these bits Note labels are also printed on the evaluation boards for both the LVDS input and FPD L
26. ut Features Selection Reference Description Input L Input H S1 RPWDNB PoWerDowN Bar Power Down Disabled Normal Operational Default PTOSEL Progressive Turn On SELect Enabled Default Disabled RESRVD RESeRVeD Don t care Don t care Reference Description Input L Input H S2 RRFB Latch input data on Rising or Falling edge of TCLK Falling Edge Default Rising Edge REN Receiver Output Data ENabled Disabled Enabled Default BISTEN BIST ENable Note MUST set DS99R421 BISTEN H Use in combination with BISTM pin Normal Operating Mode BIST Disabled Default BIST Mode Enabled BISTM BIST Mode Don t care if BISTEN L BISTEN MUST be High enabled for this pin to be functional Per Channel pass fail RxOUT 23 0 H pass RxOUT 23 0 H fail RxOUT 7 0 binary error counting mode up to 255 errors RxOUT 23 8 normal operation RAOFF RAndomizer OFF Randomizer ON Default Note DS99R421 RAOFF MUST also be set Low Randomizer OFF Note DS99R421 RAOFF MUST also be set High SLEW SLEW rate control for ROUT 23 0 and RCLK Default 2X slew rate 2X drive strength National Semiconductor Corporation Date 5 12 2008 Page 15 of 39 Output Monitor Pins for the De serializer Board Table 5 JP3 Output Lock Monitor Reference Description Output L Output H JP3 LOCK Receiver PLL LOCK Note DO NOT PUT A SHORTING JUM
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