TWR-ADCDAC-LTC Tower Module
Contents
1. freescale TWR ADCDAC LTC Tower Module User s Manual Rev 0 Freescale Semiconductor Inc TWRADCDACLTCUM freescale semiconductor Table of Contents 1 TWR ADCDAC LTC rere nnn nnnm ari 4 1 1 Getting E 5 1 2 Reference DOCUMENTS uuo deerit in 5 2 Hardware Description P 2 1 Linear Technology Devices 2 11 GOO E A E E EEEE EEE A E O E E 21 2 LT62704 tts 2 SUT 62499 nein tenta ZA LTCT859 aues 21 5 ETC3471 iie LENISMISIOP 2 2 SP Lintertace m HR R M SY SCCM POW CMe ED 2 4 Input Output CODReCtOFs eren tires ebria a ene uc Ried epu tnde es epp Rinder Rn 2 4 1 QuikEval Connectors 2 4 2 ADC and DAC Connections 2 4 3 Digital eus Dese 2 Jumper Table 2 6 Tower Elevator Connections ausente 15 TWRADCDA2. 2 1 6 LTC6655 The LTC6655 is a complete family of precision bandgap voltage references offering exceptional noise and drift performance This low noise and drift is ideally suited for the high resolution measurements required by instrumentation and test equipment In addition the LTC6655 is fully specified over the temperature range of 40 C to 125 C ensuring its suitability for demanding automotive and industrial applications Advanced curvature compensation allows this bandgap reference to achieve a drift of less than 2ppm C with a predictable temperature characteristic and an output voltage accurate to 0 025 reducing or eliminating the need for calibration The LTC6655 can be powered from as little as 500mV above the output voltage to as much as 13 2V Superior load regulation with source and sink capability coupled with exceptional line rejection ensures consistent performance over a wide range of operating conditions A shutdown mode is provided for low power applications Available in a small MSOP package the LTC6655 family of references is an excellent choice for demanding precision applications 2 2 SPI Interface There are eight possible SPI devices on the TWR ADCDAC LTC four ADC and DAC devices and four QuikEval connectors The Primary Elevator Connector of the Tower System defines two SPI interface connections but each only offers up to two chip selects Therefore a 74HC138 3 to 8 line decoder along with three GPIO sign
3. EBI_ADO B81 GND Ground X A81 GND Ground 82 3 3V 3 3V Power X A82 3 3V 3 3V Power X TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 17 of 17
4. J17 pin 5 J17 pin 6 J17 pin 7 J17 pin 8 J26 pin 1 J26 pin 2 2 LTC2600 DAC T gt LTC2704 DAC J26 pin 3 J26 pin 4 J26 pin 5 J26 pin 6 J26 pin 7 26 pin 8 J26 pin 9 J26 pin 10 J26 pin 11 J26 pin 12 J27 pin 1 J27 pin 2 J27 pin 3 J27 pin 4 J27 pin 5 J27 pin 6 J27 pin 7 J27 pin 8 J27 pin 9 J27 pin 10 J27 pin 11 J27 pin 12 LTC2498 ADC LTC1859 ADC 2 4 3 Digital Debug Connector A 1x10 0 1 pitch header with many of the digital communication signals is provided for easy debug access Refer to Table 4 to the signal connection details TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 13 of 17 freescale semiconductor Table 4 Digital Debug Connector J38 Pin Number Signal Connection SPI CS DEC4 SPI CS DEC5 SPI CS DEC6 SPI CS DEC7 ray SPI CLK SPI MOSI SPI MISO SCLO SDAO GND BW e e 2 5 Jumper Table There are several jumpers on the TWR ADCDAC LTC that provide configuration selection and signal isolation Refer to the following table for details The default installed jumper settings are shown in bold The default jumper shunt locations are also shown in Figure 8 Table 5 TWR ADCDAC LTC Jumper Table Jumper Setting Description 1 2 Connect signals to QuikEval header 2 3 Connect SPI signals to QuikEval header 1 2 Use SPI CLK signal from SPIO 2 3 Use SPI signal fr
5. PWM6 A38 PWM2 B39 PWM5 A39 PWM1 B40 PWM4 A40 PWMO B41 CANRXO A41 RXDO B42 CANTXO A42 TXDO B43 1WIRE A43 RXD1 B44 SPIO_MISO SPIO_MISO x A44 TXD1 B45 SPIO_MOSI SPIO MOSI X 45 VSS B46 SPIO CSO b SPIO_CSO X x A46 VDDA B47 SPIO_CS1_b SPIO_CS1 x x A47 VREFA1 TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 16 of 17 Te oe 2 freescale semiconductor TWR ADCDAC LTC Primary Connector Side B Pin Side A Usage Used Name Usage Used B48 SPIO CLK SPIO CLK x x A48 VREFA2 B49 GND Ground X A49 GND B50 SCL1 A50 GPIO14 B51 SDA1 51 1 15 52 GPIO5 SD CARD DET A52 GPIO16 B53 USBO DP PDOWN A53 GPIO17 B54 580 DM PDOWN 54 USBO DM B55 IRQ H A55 USBO DP B56 IRQ G A56 USBO ID B57 IRQ F A57 USBO VBUS B58 IRQ E A58 TMR7 B59 IRQ D A59 TMR6 B60 IRQ C A60 TMR5 B61 IRQ B A61 TMR4 B62 IRQ A A62 RSTIN_b B63 EBI_ALE EBI_CS1_b A63 RSTOUT_b B64 EBI_CS0_b A64 CLKOUTO B65 GND Ground X A65 GND Ground X B66 EBI_AD15 A66 EBI_AD14 B67 EBI_AD16 A67 EBI_AD13 B68 EBI_AD17 A68 EBI_AD12 B69 EBI_AD18 A69 EBI_AD11 B70 EBI_AD19 A70 EBI_AD10 B71 EBI_R W_b A71 EBI_AD9 B72 EBI_OE_b A72 EBI_AD8 B73 EBI_D7 A73 EBI AD7 74 06 74 EBI AD6 B75 EBI D5 A75 EBI AD5 B76 D4 A76 EBI AD4 B77 EBI D3 A77 EBI AD3 B78 EBI D2 A78 EBI AD2 B79 EBI D1 A79 EBI_AD1 B80 EBI_DO A80
6. CDAC LTC Primary Connector Side Usage Used B2 GND Ground X A2 GND Ground X B3 3 3V 3 3V Power X A3 3 3V 3 3V Power X B4 ELE_PS_SENSE Power Sense X A4 3 3V 3 3V Power X B5 GND Ground X A5 GND Ground X B6 GND Ground X A6 GND Ground X B7 SDHC CLK SPI1_CLK SPI1 x x A7 SCLO SCLO x X B8 SDHC_D3 SPI1_CS1_b SPI1 CS1 X x A8 SDAO SDAO x X B9 SDHC D3 SPI1 CSO b SPI1 CSO X x A9 GPIO9 CTS1 GPIO9 x x Bio SDHC_CMD SPIi_MOSI SPI1 MOSI X X A10 GPIO8 SDHC 02 GPIO8 x Bil SDHC_DO SPI1 MISO SPI1_MISO X x A11 GPIO7 SD WP DET 7 Xx x C a B12 ETH_COL A12 ETH_CRS B13 ETH_RXER A13 ETH_MDC B14 ETH_TXCLK A14 15 15 ETH RXCLK B16 ETH TXER A16 ETH RXDV B17 ETH TXD3 A17 ETH RXD3 B18 ETH TXD2 A18 ETH RXD2 19 TXD1 19 RXD1 B20 ETH_TXDO A20 ETH RXDO B21 GPIO1 RTS1 A21 SSI MCLK B22 GPIO2 SDHC 01 A22 SSI BCLK B23 A23 SSI FS B24 CLKINO A24 SSI RXD B25 CLKOUT1 A25 SSI_TXD B26 GND Ground X A26 GND Ground X B27 AN7 A27 AN3 B28 AN6 A28 AN2 B29 AN5 A29 AN1 B30 AN4 A30 ANO B31 GND Ground X A31 GND Ground X B32 DAC1 A32 DACO B33 TMR1 B34 TMR2 A34 TMRO B35 GPIO4 A35 GPIO6 B36 3 3V 3 3V Power X A36 3 3V 3 3V Power X B37 PWM7 A37 PWM3 B38
7. CLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 2 of 17 7 freescale List of Figures Figure 1 Freescale Tower System Overview 4 The features of the TWR ADCDAC LTC peripheral module are listed here and pointed out in Figure 2 4 Figure 2 Callouts on top side of the 5 Figure 3 SPI Configuration bdo ODE Mta 9 4 Tei r Tllel c 10 Figure 5 LTC3471 Switching Regulator Eure Resa uta dan dec nde neun 11 Figure 6 LTC6655 5 Voltage ipe EU poer e IRE i bmp cui CD eaa E bene LEUR 11 Figure 7 QuikEval Connectors ex Ret GR OD UD ES OP 12 Figure 8 TWR ADCDAC LTC Default Jumper Settings 15 List of Tables Table 1 SPI Chip Select Decoder Truth Table dace 9 Table 2 Decoded SPI Chip Select Device 5 10 Table 3 Terminal Block COMMGCCIGIS 13 Table 4 Digital Debug Connector uice e ester i dub Dr pnr EE 14 Table 5 TWR ADCDAC LTC Jumper Table oa exea cueste da tan na eoa 14 Table 6 TWR ADCDAC LTC Primary Connector Pinout 15 Revis
8. N asco s Q de d T EB 12 n fe hs Se MO 0 ote TWR ADCDAC 33 1 7 28 908 at ls J a 1 3 oe n4 8 LTC 1 er OS R24 eoo eje C33 8237 34 Figure 8 TWR ADCDAC LTC Default Jumper Settings 2 6 Tower Elevator Connections The TWR ADCDAC LTC features two expansion card edge connectors that interface to the Primary and Secondary Elevator boards in a Tower system The Primary Connector comprised of sides A and B is utilized by the TWR ADCDAC LTC while the Secondary Connector comprised of sides C and D only makes connections to the GND pins Table 6 provides the pinout for the Primary Connector An x the Used column indicates that a connection is made to that pin on the connector An x in the Jmp column indicates that a jumper or other option is provided to remove or configure the connection thus the connection can be removed if required Table 6 TWR ADCDAC LTC Primary Connector Pinout TWR ADCDAC LTC Primary Connector Side Side Usage Used B1 5 5 0V Power X Al 5V 5 0V Power X Used TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 15 of 17 Te freescale semiconductor TWR AD
9. als is used to generate the eight chip select signals needed to accommodate all the possible SPI devices on the board Figure 3 shows the schematic connections for the SPI configuration selections Refer to Section 2 4 3 Jumper Table for more details on the jumper selection options The three signals decoded by the 74HC138 to generate the SPI chip select signals can be driven by GPIO signals from the Primary Elevator Connector GPIO7 9 or they can be set by jumper options J14 J16 Table 1 shows how the logic level on the three decoder inputs map to the SPI chip select signals Table 2 shows the devices to which the decoded chip selects are connected TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 8 of 17 5 semiconductor eio SP CS DECO GPica SPI CS DEC O8 SPLCS DEC2 SPI CS DECA SPI CS SPLCS DECS SPI CS DECS SPI OTs SUL CSI J25 Default 1 2 Pals Pals Pais Pais J9 J710 J12 J13 Default 1 2 Figure 3 SPI Configuration Options Table 1 SPI Chip Select Decoder Truth Table GPIO9 GPIO8 GPIO7 Decoded SPI Chip Select mE ESSE I EL TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 9 of 17 Po freescale semiconductor Table 2 Decoded SPI Chip Se
10. d to measure an external signal from combinations of 16 analog input channels operating in single ended or differential modes or its internal temperature sensor The integrated temperature sensor offers 1 30th resolution and 2 absolute accuracy The LTC2498 allows a wide common mode input range to independent of the reference voltage Any combination of single ended or differential inputs can be selected and the first conversion after a new channel is selected is valid Access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift 2 1 4 LTC1859 The LTC1857 LTC1858 LTC1859 are 8 channel low power 12 14 16 bit 100ksps analog to digital converters ADCs These SoftSpan ADCs can be software programmed for OV to 5V OV to 10V 5V 10 input spans and operate from a single 5V supply The 8 channel multiplexer can be programmed for single ended inputs or pairs of differential inputs or combinations of both In addition all channels are fault protected to 25V A fault condition on any channel will not affect the conversion result of the selected channel An onboard high performance sample and hold and precision reference minimize external components The low 40mW power dissipation is made even more attractive with two user selectable power shutdown modes DC specifications include 3LSB INL fo
11. ion History Date Changes 1 0 Jan 17 2010 Initial Release TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 3 of 17 2 Te freescale semiconductor 1 TWR ADCDAC LTC Overview The TWR ADCDAC LTC is a Tower Peripheral Module compatible with the Freescale Tower System Figure 1 It features two analog to digital converters ADC two digital to analog converters DAC a voltage regulator and high precision voltage reference from Linear Technology SPI and interface signal connections on the Primary Elevator Connector allow any Tower Controller Module with a SPI and I C interface to configure and control all the features of the TWR ADCDAC LTC Controller Module Primary Elevator Tower MCU MPU n 7 Common serial board yu E i Bn bus signals Works stand alone or in Tower System Two 2x80 connectors on Features integrated Zz backside for easy debugging interface SR amp A signal access and for easy programming SSS a side mounting and run control via zm N board LCD module standard USB cable 1 7 Power regulation circuitry Secondary Elevator Standardized signal Additional and assignments secondary serial and expansion bus signals Mounting holes Standardized signal assignments 9 Board Connectors Mounting holes and expansion connectors for side mounting peripheral b
12. ke place 2 1 2 LTC2704 The LTC2704 16 LTC2704 14 LTC2704 12 are serial input 12 14 or 16 bit voltage output SoftSpan DACs that operate from 3V to 5V logic and 5V to 15V analog supplies SoftSpan offers six output spans two unipolar and four bipolar fully programmable through the 3 wire SPI serial interface INL is accurate to 1LSB 2LSB for the LTC2704 16 DNL is accurate to 1LSB for all versions Readback commands allow verification of any on chip register in just one 24 or 32 bit instruction cycle All other commands produce a rolling readback response from the LTC2704 dramatically reducing the needed number of instruction cycles TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 6 of 17 freescale semiconductor A Sleep command allows any combination of DACs to be powered down There is also a reset flag and an offset adjustment pin for each channel 2 1 3 LTC2498 The LTC2498 is a 16 channel 8 differential 24 bit No Latency A2 ADC with Easy Drive technology The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on chip buffering through automatic cancellation of differential input current This allows large external source impedances and rail to rail input signals to be directly digitized while maintaining exceptional DC accuracy The LTC2498 includes a high accuracy temperature sensor and an integrated oscillator This device can be configure
13. lect Device Connections Decoded CS Signal SPI_CS_DECO QuikEval J22 SPI_CS_DEC1 QuikEval J21 SPI_CS_DEC2 QuikEval J20 SPI_CS_DEC3 QuikEval 119 SPI_CS_DEC4 LTC2704 SPI_CS_DEC5 LTC2600 SPI_CS_DEC6 LTC2498 SPI_CS_DEC7 LTC1859 2 3 System Power The Freescale Tower System supplies 3 3V and 5V supplies on the Elevator Connectors However the TWR ADCDAC LTC can and by default does generate its own voltage supply and voltage reference from the 5V input on a standard mini B USB connector J33 As shown in Figure 4 jumper J30 can optionally be used to provide 5V from the Tower Elevator Connectors ELE Figure 4 Power Inputs The LTC3471 dual switching regulator Figure 5 boosts and inverts the 5V input to generate clean 15 and 15V supply rails used by the LTC2704 ADC and the LTC6655 5 voltage regulator TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 10 of 17 e Te freescale semiconductor 45V L12 e aa 2 L10 11 16uH 15uH 100 25V 15v E N D4 1 2 1 tou V MBRM120LT 1 25V 499 LT3471EDD ores d 5 55 5 434 1 R9 47K R19 226K 74 4 SHDN ss2 2 EPAD FBIP VREF 15 1X3 d O33UF 11 100PF 1 734 Default 1 cas J34 Default 1 2 ARIF Figure 5 LTC3471 Switching Regulator The LTC6655 5 precise bandgap voltage reference Figure 6 uses the 15V as the input vo
14. ltage generate a low noise low drift 5 0V reference voltage used by the on board ADCs and DACs 15V DNP 12 2 6 VIN VOUT S A AL E 7 SHDN VOUT F 7 GND2 5 GND3 05 01 only one will be installed Figure 6 LTC6655 5 Voltage Reference Page 11 of 17 TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual freescale semiconductor 2 4 Input Output Connectors All the input and output connections on the TWR ADCDAC LTC are described in the following sections 2 4 1 QuikEval Connectors The QuikEval Connectors utilize either an 12C or SPI interface Jumpers 11 18 are provided to select between 2 and SPI These connectors can be used to connect to any Linear Technology evaluation board that is a member of the QuikEval family Figure 7 QuikEval Connectors 2 4 2 ADC and DAC Connections The inputs and outputs of the four converter devices on the TWR ADCDAC LTC are brought to terminals on screw in terminal blocks The following table provides the information for how the signals are connected to the terminal blocks TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 12 of 17 freescale semiconductor Table 3 Terminal Block Connections LTC Device Signal Connection Label J18 pin 1 J18 pin 2 18 pin 3 J18 pin 4 18 5 J18 pin 6 18 pin 7 J18 pin 8 J18 pin 9 J18 pin 10 J17 pin 1 J17 pin 2 J17 pin 3 J17 pin 4
15. oards Four card edge connectors Uses PCI Express connectors Size Peripheral Module x16 90 mm 3 5 long 164 pins Tower is approx 3 5 Hx 3 5 W Examples include serial interface module x 3 5 D when fully assembled memory expansion module and Wi Fi Figure 1 Freescale Tower System Overview The features of the TWR ADCDAC LTC peripheral module are listed here and pointed out in Figure 2 e Two Linear Technology digital to analog converters DACs with SPI interfaces o LTC2704 16 Quad 16 bit voltage output SoftSpan DAC with readback o LTC2600 Octal 16 bit rail to rail DACs Two Linear Technology analog to digital converters ADCs with SPI interfaces o LTC1859 8 channel 16 bit 100 ksps SoftSpan ADC with shutdown LTC2498 24 bit 8 16 channel delta sigma ADC with Easy Drive input current cancellation e Linear Technology voltage regulator o LTC3471 Dual 1 3A 1 2 MHz boost inverter TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 4 of 17 freescale semiconductor e Linear Technology voltage reference o LTC6655 5 0 25 ppm noise low drift precision buffered 5V reference e Four 14 pin headers for connecting to any Linear Technology QuikEval demonstration board C or SPI LTC2600 _ LTC2498 gt 163471 Analog Outputs Analog Inputs LTC2704 lt LTC1859 Figure 2 Callouts on top side of the TWR ADCDAC LTC 1 1 Get
16. om SPI1 1 2 Select SPIO CSO 2 3 Select SPIO_CS1 1 2 Select 5 1 CSO 2 3 Select 5 1 CS1 1 2 Use SPI MOSI signal from SPIO 2 3 Use SPI MOSI signal from SPI1 1 2 Use SPI MISO signal from SPIO 2 3 Use SPI MISO signal from SPI1 1 2 Use SPIO CSx see J10 2 3 Use SPI1 CSx see J11 1 2 Connected to 3 3V J14 SPI Chip Select Encoding Bit O Setting 2 3 Connected to GND OFF Driven by GPIO9 1 2 Connected to 3 3V J15 SPI Chip Select Encoding Bit 1 Setting 2 3 Connected to GND OFF Driven by GPIO8 1 2 Connected to 3 3V J16 SPI Chip Select Encoding Bit 2 Setting 2 3 Connected to GND OFF Driven by GPIO7 31 38 QuikEval l C SPI Selection J9 SPI Port Selection SPI CLK J10 SPI Port Selection SPIO_CSx J11 SPI Port Selection SPI1 CSx J12 SPI Port Selection SPI MOSI J13 SPI Port Selection SPI MISO J25 SPI Port Selection SPI CS 728 129 ON Connect VOSA VOSB VOSC VOSD to GND E OFF Disconnect VOSx from GND ON Connect on board 5V rail to Tower System J30 T C ti i Isolate on board 5V rail from Tower System TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 14 of 17 freescale semiconductor Setting Description 1 2 LT3471 voltage regulator enabled 2 3 LT3471 voltage regulator disabled ON Use output of LTC6655 5 as reference OFF Use GND as reference LT3471 Shutdown LTC1859 Reference Voltage Selection J35 PRIMARY CONNECTOR 926 INK OUT
17. r the LTC1859 1 5LSB INL for the LTC1858 and 1LSB for the LTC1857 The internal clock is trimmed for 54 maximum conversion time and the sampling rate is guaranteed at 100ksps A separate convert start input and data ready signal BUSY ease connections to FIFOs DSPs and microprocessors 2 1 5 LTC3471 The LT3471 dual switching regulator combines two 42V 1 3A switches with error amplifiers that can sense to ground providing boost and inverting capability The low VCESAT bipolar switches enable the device to deliver high current outputs in a small footprint The LT3471 switches at 1 2MHz allowing the use of tiny low cost and low profile inductors and capacitors High inrush current at start up is eliminated using the programmable soft start function where an external RC sets the current ramp rate A constant frequency current mode PWM architecture results in low predictable output noise that is easy to filter TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 7 of 17 freescale semiconductor The LT3471 switches are rated at 42V making the device ideal for boost converters up to 40 as well as SEPIC and flyback designs Each channel can generate 5V at up to 630mA from a 3 3V supply or 5V at 510mA from four alkaline cells in a SEPIC design The device can be configured as two boosts a boost and inverter or two inverters The LT3471 is available a low profile 0 75mm 10 lead 3mm x 3mm DFN package
18. ting Started The TWR ADCDAC LTC is a Tower Peripheral Module that operates under the control of a Tower Controller Module A software Demo Suite is available and is the best way to get started and exercise the features of the TWR ADCDAC LTC A separate lab guide is available to walk the user through the Demo Suite Refer to the TWR ADCDAC LTC Lab Guide TWRADCDACLTCLAB for a list of the Tower Controller Modules that can run the Demo Suite 1 2 Reference Documents The documents and links listed below should be referenced for more information on the TWR ADCDAC LTC and the Tower System Freescale Tower System www freescale com tower TWR ADCDAC LTC Tool Support Page TWRADCDACLTCQSG Quick Start Guide TWRADCDACLTCLAB Lab Guide and Software TWRADCDACLTCSCH Schematics TWR ADCDAC LTC PWB Design Package Please refer to the following links for information on the Linear Technology devices featured on the TWR ADCDAC LTC e TC2600 Product Details e LTC2704 16 Product Details TWRADCDACLTCUM TWR ADCDAC LTC Tower Module User s Manual Page 5 of 17 freescale semiconductor LTC2498 Product Details LTC1859 Product Details LTC3471 Product Details LTC6655 5 Product Details 2 Hardware Description The TWR ADCDAC LTC features four Linear Technology converter devices a voltage regulator and a high precision voltage reference Each of the ADCs and DACs on the TWR ADCDAC LTC provide a SPI digital interface for configura
19. tion and control In addition the QuikEval headers utilize either a SPI or lC interface This section gives an overview of each of the on board Linear Technology devices and describes the system power and digital interface configuration options 2 1 Linear Technology Devices This section provides a short description of each of the Linear Technology devices on the TWR ADCDAC LTC Refer to the datasheets and product page links in the Reference Documents section for more product information Refer to the TWR ADCDAC LTC schematics to see how these devices are connected on the TWR ADCDAC LTC 2 1 1 LTC2600 The LTC2600 LTC2610 LTC2620 are octal 16 14 and 12 bit 2 5V to 5 5V rail to rail voltage output DACs in 16 lead narrow SSOP and 20 lead 4mm x 5mm packages They have built in high performance output buffers and are guaranteed monotonic These parts establish new board density benchmarks for 16 and 14 bit DACs and advance performance standards for output drive crosstalk and load regulation in single supply voltage output multiples The parts use a simple SPI MICROWIRE compatible 3 wire serial interface which can be operated at clock rates up to SOMHz Daisychain capability and a hardware CLR function are included The LTC2600 LTC2610 LTC2620 incorporates a power on reset circuit During power up the voltage outputs rise less than 10mV above zero scale and after power up they stay at zero scale until a valid write and update ta
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