ECE 499 Final Report - Union College Blogging
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1. enable uio pruss module 53 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 pru init initialize PRU pru open 0 open connection to PRU 0 pru pruintc_init configure interrupt handlers pru exec_program 0 oneshot bin load assembly file counter 0 f open dev mem r b output open results txt w while counter lt 10 start time time pru wait_for_event 0 ddr mem mmap mmap f fileno PRU ICSS LEN offset PRU_ICSS shared struct unpack L ddr mem RAM2 START RAM2 START 4 print shared 0 if shared 0 1 print buffer 1 for i in range 0 500 fifo struct unpack L ddr_mem BUFFER2 START i 4 BUFFER2 START 4 i 4 0 value processRawADC fifo channelNum channelID fifo output write str channelNum str value n counter 4 1 pru clear event 0 elif shared 0 2 shared struct unpack L ddr mem RAM2START RAM2START 4 print buffer 2 for i in range 0 500 fifo struct unpack L ddr_mem BUFFER2 START i 4 BUFFER2 START 4 i 4 0 value processRawADC fifo channelNum channellD fifo output write str channelNum str value n counter 1 pru clear event 0 end time time Zprint end start f close2. macro LD16 mparam dat are LBBO dst src 0x00 2 endm macro LD8 mparam dst src LBBO dst sre 0x00 1 endm macro ST32 mparam src dst SBBO src dst 0x00 4 endm macro ST16 mparam src dst SBBO src dst 0x00 2 endm 46 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 macro ST8 mparam src dst SBBO src dst 0x00 1 endm JI ROO k k k k k k k k k Additions J Vick JI FRO kok ok k k k k k k k k fill the entire DRAM with val 2 byte value macro FILLSHAREDRAM mparam val MOV r3 PRUSHAREDRAMSIZE FILLSHAREDRAMREPEAT 2 SUB r3 r3 2 SBCO val CONSTPRUSHAREDRAM r3 2 QBNE FILLSHAREDRAMREPEAT r3 0 endm ooo okokokokokokokokokokok End addition JJ ORO A CA KK okokokokokokokokokokokokokokokokokokokokokokok kok kk ok ok ok ok ok ok ok ok ok ak ak ak Global Structure Definitions bk struct Global u32 regPointer u32 regVal ends f bk Global Register Assignments Jb assign Global r2 zs global endif PRU memAccess DDR PRUsharedRAM 47 CO JO C amp an NP NP NN NN NN HM ka k F i RP RRP ka RB OO IO O RUN FE O OOo NO G REW NEO 29 30 31 32 33 Appendix D PRU Assembly Code origin 0 offset of the start of the code in PRU memor
3. 3 1 4 Measurement Synchrophasor measurements must be synchronized with the time code source so they can be time aligned with measurements from other PMUs by a PDC Reporting rates are also defined in IEEE C37 118 1 to ensure that multiple PMUs will take measurements at the same rate Reporting Rate The reporting rate measured in phasors per second must be a factor of the nominal system frequency Required rated are listed in Table 3 1 The reporting rate must be selectable by the user via the device s internet interface according to the protocol defined in 13 Phase Estimation There are two categories of phase estimation algorithms PEAs time domain and fre quency domain An example of a time domain PEA is the Weighted Least Squares method WLS uses a Taylor series expansion of the signal to determine the phase In 16 variation 13 ft wasted SB gt LSB 2 2 4 4 M 2 Figure 3 3 Data frame transmission order Source 13 of the number of terms in the series is studied in an attempt to reduce error The Interpo lated Discrete Fourier Transform IpDFT is an example of a frequency domain algorithm The IpDFT is significantly faster than WLS but does not perform as well when distur bances occur A thorough comparison between WLS and IpDFT is carried out in 16 The selection of the PEA will provide the constraints for selection of a processor Total Vector Error Total Vector Error TVE is a measurement of th
4. Design of an Inexpensive Residential Phasor Measurement Unit Jeremy Murray Vick ECE 499 Electrical Engineering Capstone Department of Electrical and Computer Engineering Union College Schenectady NY Advisor Professor Luke Dosiek March 17 2015 Abstract Phasor measurement units PMUs are widely used by power companied to measure the state of transmission lines and the quality of transmitted power The goal of this project is to design a low cost PMU that takes measurements at the residential level of the power grid This device must be easy to manufacture and highly reliable It will communicate results back to a central database via the internet Compliance with IEEE Standard C37 118 1 and C37 118 2 is required The widespread introduction of an inexpensive PMU will increase the data resolution available in Wide Area Monitoring Systems WAMS providing control room operators with a more accurate picture of the state of the power grid Contents 1 Introduction E Motivations 2 e Ee Eel Al E pd ean 1 27 Ereegnes ert M al iid 2 Background 2 Synchrophasor Definition 2e 2 2 Previous Work x eeen RR eh ae ROB RA ego el E Ru ek es 3 Design Requirements 3L Performances nv E is te Big ek dg ET He Vo Qe ad AT A 3 1 1 Step Down and Device Power lt aa a 3 1 2 Analog Filtering srai ab ne A Sum Soho m TP 23359 Liming t ate ae ee Ace AL B AG Sexe emet 3 4 4 Measurement 4 soe 8 A toe ln ee a A 3 1 5 Co
5. 0x00000001 continuous mode SBBO r3 r2 0 4 STEPDELAY1 MOV r2 STEPDELAYI MOV r3 0x0000000E value 1 SBBO r3 r2 0 4 STEPCONFIG2 MOV r2 STEPCONFIG2 MOV r3 0x00280001 continuous mode SBBO r3 r2 0 4 ol 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 STEPDELAY2 MOV r2 STEPDELAY2 MOV r3 0x0000000F sample is value 1 open is not SBBO r3 r2 0 4 Set ADC STEPENABLE MOV r2 STEPENABLE MOV r3 0x00000004 SBBO r3 r2 0 4 Write protect steps enable ADC MOV r2 ADC CTRL MOV r3 0x00000003 SBBO r3 r2 0 4 READADC 52 CO JC C amp WINE WWW b2 b2 b2 b2 NN NN hb2 2 FA k RFP k k RP Fi k PWNrF O O ON O G ASN FE O OOo No Ga AUN E O ce Appendix E Python Code import pypruss as pru import mmap import numpy as np import struct import time ZZ MEMORY LOCATIONS PRU ICSS 0x4A300000 PRU ICSS LEN 512 1024 RAMO START 0x00000000 RAMI START 0x00002000 RAM2 START 0x00012000 TOTAL BUFFER LEN 0x00000F A0 BUFFER LEN TOTAL BUFFER LEN 2 BUFFER1 START RAM2 START 4 BUFFER2 START BUFFER1 START BUFFER LEN ZZ FUNCTION DEFINITIONS 4 def processRawADC value value 0x00000FFF amp value value int value value value 1 8 2 12 return value def channellD value value 0x000F0000 value value value gt gt 16 return value AA PRU SETUP pru modprobe
6. O N13S3H SAS ing Hued k 3 O AS SAS AS SAS Q O asaan ASADA O p a ri O dX3eAe AAA dX3e ad E O ano an9 O N8SENT 3 Ir g m 3 Te O ZL E0ld9 9 EO O vaal lo r S O 6 20ldd 8 20ld9 O LHL ASNA z geceiz O Uu SO OL zodd O el zoldo el eOld9 O O axy siuvn axr siyn a Aer0 dE NSIO ELHVN NSLO v1Hvn METOE oon NSLE ELEVA NSLH rien 4 O NSLH SLHVN NSLO SL8VN O DV aa INV X3 XH Jore O s 20149 ed 20149 ONG XL ssi ve SO z zOld Sddt OND fa 1 O 6c 1Oldd 0 toldo WOLY ON Dai O told W049 O ON ON y SLOD OE 1040 ON Wl ez O E LOD vZAMd8H3a ON dOMOVSA Bid VU 2oldd Le 001Id9 ON QNO ez O vi Logg Sl LOD ONG 13S3UN ei O 98000149 BENMIHHE ON IOA tag O el todo EL 1049 sec O HAN suawiL O 1esdiu GEEELIN MLA zen OQ an vyan O Sd9 H9VJOWW4DA E 10149 Log d O LOD 9 10140 m O ano ano iegeg dnyoeg CO NO OU BUN FE GA Q9 b2 b2 b2 b2 b2 b i KF A a FP OWMOONMDOBRWNFOHOANDWAHRWNF OO Appendix C Texas Instruments Header N B Additions to the example header provided by Texas Instruments are marked with the title Addition IER file PRU mem Access DDR PRUsharedRAM hp brief PRU memAccess DDR PRUsharedRAM assembly constants C Copyright 2012 Texas Instruments Inc author M Watkins e ifndef PRU memAccess DDR PRUsharedRAM HP define PRU memAccess DDR PRUsharedRA
7. 31 Preliminary Circuit Schematic lt lt lt lt lt lt lt lt 4 4 4 42 Final Circuit Schematic 2e 44 List of Tables 3 1 Required synchrophasor reporting rates lt lt lt lt lt lt lt lt lt 4 13 3 2 Data frame organization lt lt 4 4 44 4 4 15 3 3 Summary of design requirements lt lt lt lt lt a 16 bel lt Bill OE Materials perra wale blbe Ee oe k 3148 25 8 1 Proposed weekly schedule for Fall 2014 lt lt lt lt 34 9 1 Proposed budget for PMU components lt lt lt lt 36 9 2 Cost of PMU components 36 10 1 Component and software versions used in this project 39 Chapter 1 Introduction 1 1 Motivation On August 14 2003 North America suffered its largest blackout Major 345 kV transmis sion lines dropped out of service unbeknownst to operators causing a cascading outage that extended across the Midwest Northeast and into Canada 1 An investigation launched by the North American Electric Reliability Corporation NERC found that the blackout could have been confined to a small region had operators known the status of overstressed and failing lines 2 Since this catastrophe steps have been taken to improve real time networked mon itoring of America s electrical transmission and distribution network in order to enable system operators to predict and counteract or confine disturbances Increased situ
8. Once the potentiometer is set the magnitude and phase difference between the 120v wall outlet and signal at the ADC input pin on the BeagleBone Black should be measured with an oscilloscope or other suitable tool These values need to be entered into the Calibration section of the Python code shown in Appendix E Calibration should be performed on an annual basis according to the standards set forth in IEEE C37 119 1 25 37 10 2 Operation Once connected to power the device will boot up and automatically begin to execute the Python code After a strong GPS signal is obtained indicated when the Fix light on the GPS is extinguished the device will begin collecting and processing data The incoming data stream can be viewed using OpenPDC an open source PDC provided by the Grid Protection Alliance 26 As of March 6 2015 the software is now compatible with Mac OS X and Linux operating systems in addition to Windows Server When powering down the device either the command sudo shutdown h now should be issued via a SSH login or the power button on the BeagleBone Black should be pressed These shutdown methods are mandated by the manufacturer in order to prevent damage to the device or loss of data 10 3 Maintenance SSH access is enabled on the BeagleBone Black allowing remote login to update or modify code on the device IP address configuration is currently handled by DHCP so any network changes may alter the IP address T hough an
9. inconvenience this choice was a necessity as the device may be connected to a variety of different networks with different address ranges Connecting a monitor and keyboard to the device and issuing the command ifconfig from the command line is the most reliable way to determine the IP address once the device is installed The revisions of all hardware and software components used by the device are listed in Table 10 1 Monthly software updates should be issued using the command sudo apt get update to update package lists from the Debian repository and sudo apt get upgrade to perform the update Proper backup practices should be followed before these updates to prevent data or functionality loss It is not recommended to update the Linux kernel a process that requires the internal memory of the BeagleBone Black to be flashed with a new image without thorough testing as subsequent versions make major changes to the way in which the PRU is initialized and accessed by the CPU 38 Component Revision Hardware BeagleBone Black C Ultimate GPS Module 3 Software Linux Kernel Debian Python AM335x Driver PyPRUSS 3 8 13 bone47 7 8 2 7 3 Commit e4d44bd on GitHub Commit 6feef2b on Bitbucket Table 10 1 Component and software versions used in this project 39 Chapter 11 Conclusion The goal of this project is to design an inexpensive residential phasor measurement unit Designing an inexpensive PMU will allow the
10. output close pru clear_event 0 pru pru_disable 0 pru exit 54 Bibliography E Lipton R Perez Pena and M Wald Overseers missed big picture as failures led to blackout New York Times September 2003 NERC NERC Final Blackout Reccommendations North American Energy Relia bility Corporation Tech Rep 2004 U S Department of Energy Synchrophasor technologies and their deployment in the recovery act smart grid programs Online August 2013 C P Steinmetz Complex quantities and their use in electrical engineering in Pro ceedings of the International Electrical Congress Held in the City of Chicago August 21st to 25th 1898 American Institute of Electrical Engineers 1894 pp 33 74 S Das and T Sidhu A simple synchrophasor estimation algorithm considering ieee standard c37 118 1 2011 and protection requirements Instrumentation and Measure ment IEEE Transactions on vol 62 no 10 pp 2704 2715 Oct 2013 M Adamiak B Kasztenny and W Premerlani Synchrophasors definition mea surement and application Proceedings of the 59th Annual Georgia Tech Protective Relaying Atlanta GA 2005 K Martin D Hamai M Adamiak S Anderson M Begovic G Benmouyal G Brunello J Burger J Y Cai B Dickerson V Gharpure B Kennedy D Karls son A Phadke J Salj V Skendzic J Sperr Y Song C Huntley B Kasztenny and E Price Exploring th
11. the Timing section of the Design Requirements the time source must be accurate within 26ys in order to achieve the accuracy specified in 11 There are many timing specific GPS modules on the market but their average price is 450 18 which is prohibitive for the budget of this project The Adafruit Ultimate GPS Module is offered at a reasonable 40 and achieves 9us accuracy 19 on its PPS output Though this is not as accurate as timing specific sources some boast sub 5us accuracy 20 it is well within the specifications and budget for this device 4 2 Software Design 4 2 1 Signal Processing From the initial stages of the project Python was the desired programming language for processing raw data into synchrophasor measurements Availability of Python packages for signal processing and ethernet packet transmission cross platform compatibility and the ease with which the language can be interpreted by a lay person were the driving factors in this choice By choosing such a widely known and supported language the code generated in this project can be of greater utility to others researching PMUs However Python is a high level programming language which presents a few challenges when interacting directly with hardware Python code has to be parsed by the Python interpreter before it is executed exacting a performance penalty In addition low level programming languages like C are more suited to direct memory interaction than
12. time tag and sent to a PDC via the internet interface The device must also accept commands transmitted by the PDC 3 1 1 Step Down and Device Power Analog to Digital A D converters are not typically capable of measuring signals at 120v meaning a voltage step down circuit must be designed to reduce the magnitude of the AC signal to match the specified range of the A D The device may only have one connection to the power source meaning the step down circuit must also include a tap and rectification circuit to provide power for the chosen processor The supply circuit should have over 11 120v TU NC Ste Anti Aliasin Synchrophasor Internet Device Power Concentrator Control Commands Phasor Data Concentrator Figure 3 1 rPMU block diagram Low Pass Filter Analog Output 0 f 2 te Figure 3 2 Anti aliasing filter frequency response Source 14 voltage protection to prevent damage to the device and have an output voltage ripple that meets the constraints of the chosen processor 3 1 2 Analog Filtering Since an A D conversion is being performed it necessary to have an analog low pass filter to reduce the bandwidth of the input signal and eliminate aliasing The cutoff frequency for the low pass filter should be just above f 2 the chosen sampling frequency The desired frequency response defined in terms of the sampling frequency is shown in Figure 3 2 12 System Freq
13. used in the filter specifically the LM358 which both met the specifications and was already available in the lab A DC coupled low pass RC active filter design presented in the LM358 datasheet 23 was used as the basis for the design of this circuit Resistor and capacitor values listed in the circuit schematic in Figure 5 2 were calculated using the equations provided in the datasheet with a cutoff frequency of 100Hz gain of 0 2 and quality factor of 1 as the design parameters Filters inherently generate a phase difference between the input and output signals it is important that this phase shift is measured and accounted for in the final calibration of the device 6 1 3 Analog to Digital Conversion Sampling is handled by the touchscreen controller and analog to digital converter subsys tem TS_ADC_SS The systems was designed to be used as a digitizer for touch screen input but can also operate as a regular ADC when set to general purpose mode Analog input can range from 0 to 1 8v and there are 8 channels available on the BeagleBone Black However the 8 channel count is somewhat misleading as there is only one ADC Channels are multiplexed to the ADC as shown in Figure 5 3 meaning that channel capture can only happen sequentially Multiplexing of channels is controlled by a finite state machine with sixteen sequence steps Each step corresponds to the acquisition and storage of data from one channel as outlined in Figure Two steps wil
14. Bone Black 1 55 00 Ultimate GPS 1 39 95 GPS Antenna 1 12 95 5v 2A DC Power Supply 1 7 95 14 1 Power Transformer 1 19 82 NEMA 5 15P Connector 1 15 98 LM358 Single Supply Op Amp 1 0 49 TOTAL Cost 142 16 Table 9 2 Cost of PMU components 36 Chapter 10 User Manual 10 1 Setup Setup of the residential PMU is designed to be quick and simple Device power and measurement input are both drawn from the same connector a NEMA 15 5 plug that is compatible with residential outlets The plug is simply inserted into the wall outlet to provide power and the AC voltage to be measured Transmission of measured data and device management is handled via ethernet the device must be connected to the same network as the server receiving data The GPS antenna is connected to the external antenna connector mounted on the device and should be placed as close to a window or outside wall as possible It may be necessary to experiment with antenna positioning the LED labelled Fix on the GPS module will cease flashing when a strong enough signal is obtained to begin measurements 10 1 1 Calibration In the current iteration of the device a 10kQ potentiometer configured as a voltage divider is connected between the secondary side of the transformer and the input of the low pass filter This allows the magnitude of the incoming signal to be adjusted manually to span the entire 0 to 1 8v range of the ADC thus maximizing measurement resolution
15. Chapter 4 Design Alternatives 4 1 Component Selection 4 1 1 Computing Platform The computing platform is the core of the phasor measurement unit It is responsible for acquiring raw AC voltage waveform data from an Analog to Digital Converter ADC in synchronicity with the GPS Pulse Per Second PPS time code computing the magnitude and phase of the signal packaging the measured data into the IEEE C37 118 2 transmission format and sending the resulting data packet over the internet to a PDC Many options were considered in the choice of the computing platform for this project including the well known Raspberry PI the Arduino BeagleBone Black and Intel Edison The Raspberry PI while it is a relatively powerful platform with thorough documentation and an active user base was dismissed due to the lack of an onboard ADC Choosing a platform with an onboard ADC is important because it simplifies the circuitry and reduces the cost of the device An Arduino while it has an onboard ADC lacks the computing power of the other SOC based alternatives requires additional components to connect to the internet and does not have the ability to be reprogrammed remotely an important consideration when deploying a device in the homes of laymen residents Intel s Edison platform was considered for its high computing power density dual core 500 MHz processor but rejected due to the scarcity of public documentation Ultimately the BeagleBone Black wa
16. DFT at the beginning of this project Other methods such as IpDFT and Weighted Least Squares are shown to provide higher accuracy 24 but DFT will allow a proof of concept The choice of Python as the pro gramming language allows for easy substitution of the phase estimation algorithm Each second of raw data was divided into 30 windows and a DFT performed on each to achieve the desired reporting rate of 30 phasors second 29 Chapter 7 Results There currently exists an issue in the code with the way interrupts are generated by the PRU and handled by the CPU when the two part buffer reaches its capacity As such only one buffer s worth of data can be captured and processed at a time Repeatedly executing the capture process allows the user to overcome this by repeatedly executing the capture operation Figure 7 1 and 7 2 show the change in phase and frequency over one second of time for the measured data 7 1 Evaluation Plan Though the device is not fully functional yet the following evaluation plan has been devised for the device once the coding issues have been resolved 7 1 1 Timing Accuracy Acquiring a highly accurate time source such as an atomic clock to test the accuracy of the timing circuit is impractical due to the cost of such devices However an indirect test can be performed to analyze the stability of the timing circuit Measuring the period of the pulse per second signal provided by the timing source over sixty
17. Enable OCP master port LBCO r0 CONSTPRUCFG 4 4 CLR r0 r0 4 SBCO r0 CONST PRUCFG 4 4 C28 will point to 0x00012000 PRU shared RAM MOV r0 0x00000120 MOV r1 CTPPR 0 ST32 r0 rl Reset SYSConfig Register to 0 MOV r2 0x44E0D010 load register address MOV r3 0x00000000 SBBO r3 12 0 4 set register Wait for ADC to be idle Adcldle MOV r2 0x44E0D044 load register address QBBS Adcldle r2 5 Write enable steps disable ADC MOV r2 ADC_CTRL MOV r3 0x00000004 SBBO r3 r2 0 4 50 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 Set ADC_CLKDIV MOV r2 ADC_CLKDIV MOV r3 0x0000031F value 1 399 0x18F SBBO r3 r2 0 4 MOV r0 0 FILLSHAREDRAM r0 CLEARFIFO MOV r2 FIFOODATA LBBO r3 r2 0 4 MOV r2 FIFOOCOUNT LBBO r3 r2 0 4 QBNE CLEARFIFO r3 O0 Clear any residual interrupts MOV r2 IRQSTATUS MOV r3 0x000007FF SBBO r3 r2 0 4 Disable all interrupts MOV r2 IRQENABLE CLR MOV r3 0x000007FF SBBO r3 r2 0 4 Enable FIFOO interrupt in INTENABLE SET MOV r2 IRQENABLE SET MOV r3 0x00000004 SBBO r3 r2 0 4 Set FIFOOTHRESHOLD MOV r2 FIFOOTHRESHOLD MOV r3 FIFOTHRESHOLD value 1 SBBO r3 r2 0 4 STEPCONFIG1 MOV r2 STEPCONFIG1 MOV r3
18. M HP okokokokokokokokokokokokokokokokokokokokokokok kok ok k k ok ok ok ok ok ok ok ak ak ok Global Macro definitions okokokokokokokokokokokokokokokokokokokokokokok k ok ok k k ok ok ok ok ok ok k ak ok Refer to this mapping in the file prussdrv include pruss_intc_mapping h define PRUO PRUI INTERRUPT 17 define PRUI PRUOINTERRUPT 18 define PRUO ARM INTERRUPT 19 define PRUI ARM INTERRUPT 20 define ARM PRUOINTERRUPT 21 define ARM PRULINTERRUPT 22 define CONST PRUCFG C4 define CONST PRUDRAM C24 define CONST PRUSHAREDRAM C28 define CONST DDR C31 45 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 FRR AOR A A IK Addition J Vick JI ooo okokokokook kok ok okokokokokokokokok define PRUSHAREDRAM 0x00010000 12kB define PRUDRAM1 0x00000000 define PRUDRAM2 0x00002000 define PRUDRAMSIZE 8192 define PRUSHAREDRAMSIZE 12288 ROR ORO A I A AK End addition RRR OR AO ACK Address for the Constant table Block Index Register CTBIR define CTBIR 0x22020 Address for the Constant table Programmable Pointer Register O CTPPR 0 define CTPPR 0 0x22028 Address for the Constant table Programmable Pointer Register 1 CTPPR 1 T define CTPPR 1 0x2202C macro LD32 mparam dat are LBBO dst src 0x00 4 endm
19. OU Zen O O vas zoe ws eod O O vas Lei ws to O O S8uUWMdHH3 91 LOD O viWMdHH3 axr rien O O sc 1049 Ou vuuwn O O NLIS SAS ing uMd O O As sis AS SAS O O s aan AS aan O dX30A8 GAA dX3c Gan O ano9 ano O Ir e 20149 92049 a 6 ZOIJO 8 2099 Z 86SELZ W 20149 0L ZOld5 EL ZOld9 2t 2Old9 oxy siuvn AXL Sien NSLO Eilen NSLO rien NS1H 14vn NS1Y v1HVn NSIY Sien NSLO Suen sz zOld9 ES SO ve 20149 ze 2049 SS LOld9 0 LOId9 t LOIdD P LOld9 10149 oe LOIJD te LOldD YEWM dHH3 tzoldo ZE 001d9 vr 1049 SL LOIJD 92 00149 BENMdHH3 SL LOIJD EL LOIJD 9H3WIL SHINIL 4H3WIL vH3WIL 1Old9 10149 4 10149 9 10149 ONS ONS AtoZ dNMIVBA ANOVA ONS 13S3HN Sd9 HIVIONIWADI 0 o 0 O 0 0 o 0 O O 0 0 0 O O 00999090990999999990900 42 Appendix B Final Circuit Diagram 43 usisop K eug jo orjeurouos nano Tg om 3NMLNO_3NOg319V39 44 8d 2 Ady yoRIg euoqejBeeg isn and an9 O an9 ano LoOold9 zinono o Ni ONIV O ENIV zNV O SNIV ONIV O AV VaN5 yNiv O ava oav aan IOS tds O O Id bas od tes e 3 O 0S9 tds 6r todo O axu Liuvn L 0ld9 O O AXL biyvn AU Ode O axy Sien AXL zyn m O vas eoa Jos eod O IH vas ioa Tos toe O IM O 8iNMdHH3 91 Log O vINMdHH3 AXL ron Q 8 L0Id9 axd rien O
20. Python It was possible to use Python despite its deficiencies in this project because the heavy lifting is handled by the PRU Samples generated by the ADC are stored in shared memory accessible from the CPU by the PRU which ensures that latency between sample acqui sition and storage in memory is a fixed known value Texas Instruments the designer of the AM335x processor onboard the BeagleBone Black provides a library for sending assembly code to and monitoring interrupts from the PRU written in C another obstacle Fortunately PyPRUSS a community project focused on 3D printing with the Black 21 18 incorporates a Python wrapper for the C library enabling its functions to be called within Python code 4 2 2 Signal Acquisition Acquisition of data with the BeagleBone Black s onboard ADC can either be handled by the CPU or by the PRU The host CPU runs Debian a variant of linux which is not a realtime operating system Any processes interacting with the ADC are scheduled at the mercy of the operating system which is not a desirable characteristic in an application where precise timing is of the utmost importance Therefore the PRU was used to communicate with the ADC subsystem The PRU is controlled with assembly code loaded by the CPU Coding in assembly presents a few challenges operations involve direct manipulation of registers and memory locations which is time consuming and potentially catastrophic as the PRU has access to th
21. TREF dr E gt nili no internal ontro PENCTR lt 1 0 gt 1 vssa Apc d VDDA ADC Ab 5 z SEL INM lt 3 0 gt SEL RFM lt 1 0 gt REXT Das 5 5 5 2 2 2 2 no internal E d amp Z Blue pins are O pads connection Figure 5 3 Block diagram of ADC analog front end operation Source 22 5 2 Signal Processing 5 2 1 Sampling Rate The sampling rate of ADC acquisitions is controlled both by dividing the ADC clock and by increasing the delay between measurement steps Both methods will be implemented to achieve sampling at an integer multiple of 60Hz desired to ease the processing requirements once sampled 5 2 2 Raw Data Processing Data from the ADC is stored as a 32 bit hex value Both the four bit channel ID and the twelve bit converted value are contained within these 32 bits Two bitwise shift operations are used to extract each component and then the values are converted to integers for further processing 5 2 3 Synchrophasor Estimation Synchrophasor estimation will be handled by a basic DFT at the beginning of this project Other methods such as IpDFT and Weighted Least Squares are shown to provide higher accuracy 24 but DFT will allow a proof of concept The choice of Python as the pro gramming language allows for easy substitution of the phase estimation algorithm Eac
22. ational awareness can also allow the dynamic calculation of maximum load ratings based on en vironmental conditions Overall improved monitoring allows utilities to provide power to customers in a more efficient more reliable and safer way The installation of phasor measurement units PMUs provides a real time image of operating conditions Increasing the number of PMUs improves the resolution of data available to control room operators It also creates the possibility for implementation of automatic control systems to correct disturbances or failures However these devices are costly approximately 43 400 per installation and are hard to install 3 They also require dedicated communication networks to feed data back to centralized processors known as phasor data concentrators PDCs PMUS can offer a new insight when installed at the distribution level of the power grid The prevalence of distributed generation smaller power plants that supply communities rather than regions is increasing due to the fact that renewable power generation is better suited for communities This increase causes an increase in dynamic events at the distribu tion level as wind turbines and solar farms increase and decrease their output in step with the weather Having PMUs measuring at the distribution level will give a more accurate picture of how the increase in distributed generation affects the power grid on a day to day and long term basis 1 2 Objectiv
23. beani RE BE OR oe hd PAM mains Accuracy ii A ieee Peas eee quete 7 1 2 Measurement 1 1 8 Communication 2 4 os Loon s k X fe o Romy EU Production Schedule Cost analysis 10 User Manual LOA Setup aiino de oom Bade pudl eB eae E ob es d Ede ae ee TOEIC Gallbration arrasa cete cwe3ci elas 10 2 Operation zn wr etat as Eme ERU A ae E nl 10 3 Maintenance 2 ste meses ena ald oe Bertie ox a Oe E 11 Conclusion A Preliminary Circuit Diagram B Final Circuit Diagram C Texas Instruments Header D PRU Assembly Code 30 30 30 30 32 33 35 37 37 37 38 38 40 41 43 45 48 E Python Code 53 List of Figures 2 1 2 2 2 3 3 1 3 2 3 3 5 1 5 2 5 3 5 4 6 1 7 1 7 2 Al B 1 Phase calculation based on UTC reference lt lt lt lt lt lt 9 Angle convention for synchrophasors e 9 OpenPMU block diagram 10 rPMU block diagram 12 Anti aliasing filter frequency response lt lt lt lt lt lt lt lt lt 12 Data frame transmission order lt lt lt 4 lt lt 14 DO Bras GTC essen R Sat doo Se AAS ud Jaz kl ca Lo le 21 Anti Aliasing Filter Circuit e 22 Analog Front End Block Diagram lt lt lt lt lt lt 23 ADC Sequencer Flowchart lt lt lt lt lt lt lt lt 4 24 ADC Block Diagram een 28 Phase VS TIME paa a a da mde A a 31 Frequency vs Time lt lt lt aa a E ea ar Eat eee
24. cations IEEE Std C37 238 2011 pp 1 66 July 2011 D Belega D Macii and D Petri Fast synchrophasor estimation by means of frequency domain and time domain algorithms Instrumentation and Measurement IEEE Transactions on vol 63 no 2 pp 388 401 Feb 2014 National Fire Protection Association National Electrical Code 2011 ser International electrical code series National Fire Protection Association 2010 WI125 Specifications Connor Winfield 1 2015 J Delano FGPMMOPAG6H gps standalone module data sheet Globaltop Technol ogy Inc Tech Rep 2012 125 Series Wi125 GPS Receiver Connor Winfield 01 2015 E Bakken PyPRUSS Hipster Circuits March 2014 Texas Instruments Am335x sitara processors technical reference manual Online October 2011 LMz58 N Dual Operational Amplifiers Rev i ed Texas Instruments January 2000 G Barchi D Macii and D Petri Synchrophasor estimators accuracy A compar ative analysis Instrumentation and Measurement IEEE Transactions on vol 62 no 5 pp 963 973 May 2013 Ieee standard for synchrophasors for power systems IEEE Std C37 118 2005 Re vision of IEEE Std 1344 1995 pp 01 57 2006 56 26 Grid Protection Alliance Openpde March 2015 Online Available http openpdc codeplex com 57
25. ctronics Association NMEA sentences a standard format for GPS data are received from the GPS via UART and used to assign UTC time tags to phase measurements The PPS signal was acquired via the onboard ADC in conjunction with the AC voltage waveform The signal is a pulse width modulation signal with a frequency of 1Hz and a magnitude of 3 3v A simple voltage divider was used to divide this signal in half to fit the 1 8v maximum on the ADC inputs This signal serves as the marker for the start of a Discrete Fourier Transform DFT window The output of VFix which is pulled low when a strong signal is found 19 is connected to a general purpose input output indicating when the GPS is ready for measurement to begin 6 2 Signal Processing 6 2 1 Sampling Rate The sampling rate of ADC acquisitions is controlled both by dividing the ADC clock and by increasing the delay between measurement steps Both methods will be implemented to achieve sampling at an integer multiple of 60Hz desired to ease the processing requirements once sampled 28 6 2 2 Raw Data Processing Data from the ADC is stored as a 32 bit hex value Both the four bit channel ID and the twelve bit converted value are contained within these 32 bits Two bitwise shift operations are used to extract each component and then the values are converted to integers for further processing 6 2 3 Synchrophasor Estimation Synchrophasor estimation will be handled by a basic
26. e The goal of this project is to design a low cost PMU that takes measurements at the residential level of the power grid This device should be easy to manufacture and highly reliable It should communicate results back to a central database using the protocol described in the IEEE Standard for Syncrophasor Data Transmission Chapter 2 Background 2 1 Synchrophasor Definition Alternating Current AC is mathematically represented by a cosine wave x Acos 27 fact 2 1 where fac 60Hz in North America Using a technique proposed by Charles Proteus Steinmetz in 4 AC can be represented as a simplified guantity called a phasor When representing a cosine as a phasor it is assumed that the freguency of the signal remains the same Therefore the variable guantities are magnitude and phase For AC magnitude is commonly defined as the root mean sguare of voltage Eguation 2 1 becomes A X l 2 2 Establishing phase requires either a signal or time reference Synchrophasors calculate phase using an absolute time reference commonly Coordinated Universal Time UTC Figure 2 1 shows a cosine superimposed on a UTC time pulse The synchrophasor is defined to be 0 if the cosine has a maximum during the pulse and 90 if the cosine has a zero crossing at the pulse Values between 0 and 90 are calculated according to the selected phasor estimation algorithm 5 Previously phasor measurement at generators and nodes in the tran
27. e difference between a perfect theoretical phasor and the actual phasor measured by the PMU The IEEE Std C37 118 1 defines TVE as TVE n y ES ES A 3 1 Where X n and X n are the real and imaginary components respectively of the mea sured phasor and X n and X n are the components of the theoretical phasor The standard specified that TVE must be less than 1 Sources of TVE include timing inac curacy off nominal signal frequency and low frequency oscillations 3 1 5 Communication Communication between the PMU and PDC will take place via the internet Data packets will be sent using Transmission Control Protocol TCP Data packets are subdivided into frames each containing a specific piece of data The frames required for sending phasor data as defined in IEEE C37 118 2 to a PDC are listed in Table 3 2 The phasor itself is transmitted in frame 7 The DIGITAL frame can be used to transmit extra device status indicators not included in the STAT frame relay statuses breaker statuses or other information The generic order of frame transmission is shown in Figure 3 3 where DATA1 DATA2 etc are frames 7 11 from Table 3 2 14 No Field Size bytes Description 1 SYNC 2 Sync byte followed by frame type and version number 2 FRAMESIZE 2 Number of bytes in frame 3 IDCODE 2 PMU ID number 4 SOC 4 Second Of Century time stamp 5 FRACSEC 4 Fraction of Second and Time Quality 6 STAT 2 PMU status fla
28. e ieee standard c37 118 2005 synchrophasors for power systems Power Delivery IEEE Transactions on vol 23 no 4 pp 1805 1811 Oct 2008 K Kirihara B Pinte and A Yoon Phasor measurement unit Online February 2013 B R Miller Concept for next generation phasor measurement A low cost self contained and wireless design Master s thesis University of Tennessee 2010 95 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 D Laverty D J Morrow A McKinley and M Cregan Openpmu Open source platform for synchrophasor applications and research in Power and Energy Society General Meeting 2011 IEEE July 2011 pp 1 6 Teee standard for synchrophasor measurements for power systems IEEE Std C37 118 1 2011 Revision of IEEE Std C37 118 2005 pp 1 61 Dec 2011 IEEE standard for synchrophasor measurements for power systems amendment 1 Modification of selected performance requirements IEEE Std C87 118 1a 2014 Amendment to IEEE Std C37 118 1 2011 pp 1 25 April 2014 IEEE standard for synchrophasor data transfer for power systems IEEE Std C37 118 2 2011 Revision of IEEE Std C37 118 2005 pp 1 53 Dec 2011 B C Baker Anti aliasing analog filters for data acquisition systems Microchip Technology Inc Tech Rep 1999 Teee standard profile for use of ieee 1588 precision time protocol in power system appli
29. e memory and storage used by the operating system Ultimately the tight timing constraints imposed by the design requirements necessitate the use of the PRU despite the faults of coding in assembly 19 Chapter 5 Preliminary Proposed Design 5 1 Hardware Design 5 1 1 Voltage Step Down Connection to the wall will be made with a NEMA 5 15 compliant connector the common standard for residential outlets 17 The ADC input range of the BeagleBone Black is 0 to 1 8v 22 but going directly to this range would require a transformer ratio of 66 7 1 or greater something that is not commonly found in 120v transformer offerings A 14 1 transformer was chosen instead because of its availability and price This transformer yields a 8 57v peak to peak output when connected to the 120v wall outlet The voltage is further reduced into the ADC range by attenuation in the low pass filtering circuit Input Protection Although 120v is not as dangerous as the high voltage that commercial PMUs measure it is important that this device have safety features to protect both the low voltage electronics and the end user A 0 5A fast acting fuse was placed between the hot wire of the plug and the device as the power supply for chosen for the BeagleBone Black has a maximum current draw of 0 3A The digital DGND analog GND_ADC and earth grounds as well as the neutral wire are all tied together to ensure that there are no ground loops that might affect measure
30. g and the device as the power supply for chosen for the BeagleBone Black has a maximum current draw of 0 3A The digital DGND analog GND_ADC and earth grounds as well as the neutral wire are all tied together to ensure that there are no ground loops that might affect measurement but also to ensure that any shorts or loose wires will not generate unexpected voltages throughout the circuit DC Bias It is also necessary to add a DC bias to the AC signal in order to fall within the 0 to 1 8v range This is accomplished by a simple DC bias circuit shown in Figure 5 1 The resistor connected from the input terminal to ground is important because it ensures that the input is at Ov before a connection is made protecting the measurement source from any 26 unexpected charge on the capacitor The DC bias voltage will be generated by a voltage divider between VDD_ADC and ADC_GND with equal value resistors to ensure the mean of AC signal falls exactly in the middle of the input range 6 1 2 Anti Aliasing Filter PMUs typically sample at relatively low rates 3kHz or less as the nominal frequency of the power grid is only 60Hz It is essential to low pass filter the signal before it is sampled as sampling at such a low rate means there is a much higher chance of aliasing As gain reduction is desired a non inverting active low pass filter was chosen The BeagleBone Black is a single supply board necessitating a single supply operational amplifier be
31. g variable 55 QBA READ 56 57 INITV 58 MOV r5 0 Shared RAM address of ADC Saving position 59 MOV r6 BUFF SIZE Counting variable 60 QBNE EMPTYFIFO r14 0 61 QBA READ 62 63 READ 64 MOV r3 0x0000000F 65 SBBO r3 r13 0 1 66 67 FIFOWAIT 68 69 MOV r14 HFOTHRESHOLDNUM 70 EMPTYFIFO 71 LBBO 13 r12 0 3 72 ADD r5 r5 4 73 SBCO r3 CONSTPRUSHAREDRAM r5 3 74 75 SUB r14 r14 1 76 SUB r6 r6 4 77 QBEQ CHBUFFSTATUSI r6 r7 If first buffer is ready 78 QBEQ CHBUFFSTATUS2 r6 0 If second buffer is ready 79 80 QBNE EMPTYFIFO r14 0 81 82 QBA READ 49 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Change buffer status to 1 CHBUFFSTATUS1 MOV r3 0x00000001 SBCO r3 CONSTPRUSHAREDRAM 0 4 QBNE EMPTYFIFO 114 0 MOV r31 b0 PRUOARMINTERRUPT 16 QBA READ Change buffer status to 2 CHBUFFSTATUS2 MOV r3 0x00000002 SBCO r3 CONSTPRUSHAREDRAM 0 4 MOV r31 b0 PRUO ARM INTERRUPT 16 QBA INITV Send event to host program END MOV r31 b0 PRUO ARM INTERRUPT 4 16 HALT endm NIDI NININININ HHHH TUTETE TT TT AT AT AT TT AT AT AT TT AT TT TT TT AT AT TT Initialize ADC H H H H H HH HHHH H H H H H H H H H H TUTETE TT TT TT ATT AT AT TETTE TT TT ATT TT IT TT AT TT TT START
32. gs PHASOR 4 Phasor estimate May be single phase or 3 phase positive negative or zero sequence 8 FREQ 2 4 Frequency 9 DFREQ 2 4 Rate Of Change Of Frequency 10 ANALOG 2 Analog data available for extra features 11 DIGITAL 2 Digital data available for extra features 12 CHK 2 Cyclic redundancy check CRC CCITT Table 3 2 Data frame organization Source 13 3 2 Safety The device must comply with the National Electric Code regulations for connection spacing and insulation for 120v connections 17 The connection to the wall outlet should be made with a NEMA 5 15 compliant connector as it is the most common outlet found in residences The connector is rated for a maximum voltage of 125v sufficient for the requirements of this project 3 3 Commercial PMUs cost an average of 43 400 per installation 3 This device will be in stalled en masse in residences and should have a cost commensurate with mass production Cost The target cost for this project is under 1 000 15 Section Comments Step down Step down 120v measurement source to acceptable range for A D converter Device power Determined by the choice of processor Analog filtering Low pass filter with f just above f 2 Timing Either internet or GPS based Phase estimation Either WLS or IpDFT Safety Must follow all wiring and spacing regulations for 120v Cost Target cost is under 1000 Table 3 3 Summary of design requirements 16
33. h second of raw data was divided into 30 windows and a DFT performed on each to achieve the desired reporting rate of 30 phasors second Once the DFT for each window is 23 IDLE apply Idle Step Config Update Shadow StepEnable Reg StepEnable N 1 Set N 0 1 No Set pen down flag 1 Yes Set pen override mask 1 If preempt flag 1 increment N Ignore Pen IRQs No else set N to first SW Stepconfig Reset Preempt flag Yes Yes No Set preempt flag 1 Save N If HW N and StepEnable N If sw N and No StepEnable N Yes Preemption Yes enabled Apply StepConfig N Yes Apply StepConfig N Wait OpenDelay N Wait OpenDelay N Wait SampleDelay N Wait SampleDelay N ADC Conversion I AVGIN Yes ADC Conversion AVGIN Reset StepEnable n if One Shot n Looped all enabled No Reset StepEnable n if One Shot n i HW steps Ke No Looped all enabled Reset pen override mask SW steps Yes If TS Charge step is enabled apply TS Charge StepConfig and OpenDelay ignore any pen irq during this step Generate END OF SEQUENCE int If pen down flag 1 and now pen is up then generate PEN UP interrupt and reset pen down flag If preempt flag is 1 restore N elseset N to first SW Stepconfig HW event can either be Pen down or input HW event but not both Fig
34. ign presented in the LM358 datasheet 23 was used as the basis for the design of this circuit Resistor and capacitor values listed in the circuit schematic in Figure 5 2 were calculated using the equations provided in the datasheet with a cutoff frequency of 100Hz gain of 0 2 and quality factor of 1 as the design parameters Filters inherently generate a phase difference between the input and output signals it is important that this phase shift is measured and accounted for in the final calibration of the device 5 1 3 Analog to Digital Conversion Sampling is handled by the touchscreen controller and analog to digital converter subsys tem TS_ADC_SS The systems was designed to be used as a digitizer for touch screen input but can also operate as a regular ADC when set to general purpose mode Analog input can range from 0 to 1 8v and there are 8 channels available on the BeagleBone Black However the 8 channel count is somewhat misleading as there is only one ADC Channels 21 3 tuF R3 R2 d INPUT W AA e 3 IC2A 10k 10k 1 LM358N 100k R1 100k AMW R4 Figure 5 2 Schematic of anti aliasing filter Design adapted from the LM358 datasheet 23 are multiplexed to the ADC as shown in Figure 5 3 meaning that channel capture can only happen sequentially Multiplexing of channels is controlled by a finite state machine with sixteen sequence steps Each step corresponds to the acquisition and storage of da
35. l be used to acquire both the AC voltage waveform and the pulse per second signal from the GPS The minimum delay between sampling steps is 15 ADC clock cycles a value that must be taken into account in the calibration of the device Values from the ADC are stored in a FIFO buffer as shown in Figure 6 1 Samples are retrieved from this buffer by the PRU via the code shown in Appendix D They are moved into shared memory accessible from the CPU via a two part linear buffer When the first segment of this buffer is full an interrupt is generated signaling the CPU to read the data from memory and store it within a Python array 27 CLK M OSC pd_wkup_adc folk TSC_ADC Subsystem L3Slow Interconnect L4Wakeup Interconnect TSC_ADC Pads AN MPU Subsystem PRU ICSS WakeM3 Figure 6 1 Block diagram for ADC sample acguisition and storage Source 22 6 1 4 GPS Timing The Ultimate GPS module from Adafruit is largely self contained necessitating only a few external connections to enable functionality of the chip An onboard voltage regulator enables the use of sources from 3 3 to 5v both of which are available on the pinout of the BeagleBone Black 3 3v was chosen for the supply voltage simply because the 5v pin was already connected to the low pass filter circuit Communication between the GPS module and the Black is handled by the Universal Asynchronous Receiver Transmitter UART National Marine Ele
36. lable for 1 10 the cost of timing specific offerings Replacement of the proposed FPGA development board with a single board computer also enabled a large cost reduction The change in computing platform was based on the need for remote management access something that would have been impossible to reliably implement on an FPGA A transformer and the LM358 chip were obtained from previous projects within the department The transformer also included a NEMA 15 5 plug Components obtained for free are indicated in parentheses in the cost summary shown in Table 9 2 Construction of this residential phasor measurement unit came in well below the 14 000 estimated cost of commercial offerings 3 Achieving such a substantial cost reduction is made possible by the fact that this device takes measurements at low voltage levels removing a large number of insulation and protection requirements for high voltage PMUs Commercial devices are more accurate than this residential PMU but the low cost of this device will enable installation in more locations offsetting accuracy shortfalls with an increased volume of data 35 Component Quantity Cost Subtotal Project Enclosure 1 20 20 NEMA 5 15P Connector 1 16 16 Transformer 12 1 1 20 20 AC DC Converter 1 21 21 GPS Time Code Receiver 1 400 400 FPGA Altera DE2 1 269 269 TOTAL PROJECTED COST 746 Table 9 1 Proposed budget for PMU components Component Quantity Cost Beagle
37. ment but also to ensure that any shorts or loose wires will not generate unexpected voltages throughout the circuit DC Bias It is also necessary to add a DC bias to the AC signal in order to fall within the 0 to 1 8v range This is accomplished by a simple DC bias circuit shown in Figure 5 1 The resistor connected from the input terminal to ground is important because it ensures that the input is at Ov before a connection is made protecting the measurement source from any 20 VDD_ADC R1 ANW 100k INPUT Il OUTPUT R3 10k R2 WW 100k Figure 5 1 Schematic of DC bias circuit unexpected charge on the capacitor The DC bias voltage will be generated by a voltage divider between VDD ADC and ADC GND with egual value resistors to ensure the mean of AC signal falls exactly in the middle of the input range 5 1 2 Anti Aliasing Filter PMUs typically sample at relatively low rates 3kHz or less as the nominal freguency of the power grid is only 60Hz It is essential to low pass filter the signal before it is sampled as sampling at such a low rate means there is a much higher chance of aliasing As gain reduction is desired a non inverting active low pass filter was chosen The BeagleBone Black is a single supply board necessitating a single supply operational amplifier be used in the filter specifically the LM358 which both met the specifications and was already available in the lab A DC coupled low pass RC active filter des
38. minutes will give a good indication of the short term stability of the time source and local oscillator 7 1 2 Measurement The reference conditions for each testing parameter as specified in section 5 5 4 of IEEE C37 118 1 are listed below Each parameter should remain constant unless it is currently being tested e Voltage at nominal 30 Phase degrees anj Phase Angle vs Time T T 1 L T T os 06 Time s Figure 7 1 Plot of phase vs time for one second of measured data Freguency vs Time T T 60 2 Frequency Hz ser 1 L Figure 7 2 Plot of frequency vs time for os 06 Time s 31 one second of measured data e Current at nominal e Frequency at nominal e Voltage current phase and frequency constant e All interfering signals lt 0 2 of the nominal frequency 60Hz e Temperature 23 3 C e Humidity gt 90 Synchrophasor Estimation Synchrophasor estimation should be tested by calculating the TVE as defined in 3 1 for each testing condition listed in Table 3 of 11 The TVE should remain below 1 in all testing conditions The signal generator and oscilloscope must have a testing uncertainty ratio of 4 i e for desired TVE of 1 the devices should be able to measure TVE within 0 25 7 1 3 Communication Confirmation of the proper communication protocol specified in IEEE C37 118 2 will be verified using the PMU Connectio
39. mmunication 9 27 3Saleby aiken s on Ro eai gr at e e MENU Au Iure M isi li 33 OSL Hie ra oh Boal Msn te Ae Eade he his acm 4 Design Alternatives 4 1 Component Selection lt ooa a 4 1 1 Computing Platform 412 GPS Mod le 57 ange om Rea RR eR e Ce iR 42 Software Design ss ouk k sb M ee Ens cene 4 24 Signal Processing sc c o ike e VOR E eR E d 4 2 2 Signal Acquisition lt lt lt lt 44 44 E o a a a ea a 5 Preliminary Proposed Design 5 1 Hardware Design 5 1 1 Voltage Step Down 5 1 2 Anti Aliasing Filter lt lt lt lt a 5 1 3 Analog to Digital Conversion lt lt 4 44 o 00 11 11 11 12 13 13 14 15 15 17 17 17 18 18 18 19 8 9 FLA GPS Timing ss Ga onee a bk bd ven ex ele bone 5 2 Signal Processing 5 21 Sampling Rate llle 5 2 2 Raw Data Processing s ou o eu 5 2 8 Synchrophasor Estimation lt lt lt 4 4 lt Final Design 6 1 Hardware Design 4 4 4 2 o KX a Rop d ac ee ka doo 6 1 1 Voltage Step Down 6 1 2 Anti Aliasing Filter lt aaa 6 1 3 Analog to Digital Conversion lt lt lt 4 44 GLA GPS Timings uoo eek beat eae ba Soe WIE eo eeng A 6 2 Sienal ProcessinP is hae Ee ta 6 21 Sampling Rate oeste o Fog eer ae G 6 2 2 Raw Data Processing cs 6 2 8 Synchrophasor Estimation lt lt lt 4 20200000204 Results TL Evaluation Plam 13 udis ene
40. n Tester software package provided by the Grid Protec tion Alliance If necessary the Wireshark filter for IEEE C37 118 communication may be used to examine the raw data frames l The software can be found at http pmuconnectiontester codeplex com 2 A more detailed summary of the filter can be found at http www wireshark org docs dfref s synphasor html 32 Chapter 8 Production Schedule For the most part time estimates proposed at the beginning of the project and reproduced in 8 1 were accurate The order of the weeks was shuffled around in order to prioritize the selection of more important components over the design of voltage step down and filtering circuits 33 Week Objective 1 Design voltage step down and device power circuit 2 Design anti aliasing filter select sampling frequency and A D converter 3 Research on and selection of time code source 4 Design timing and synchronization circuit 5 Select phase estimation algorithm 6 7 Design synchrophasor estimator 8 Design internet interface 9 Construction and testing of voltage step down and device power circuit 10 Construction of anti aliasing filter Table 8 1 Proposed weekly schedule for Fall 2014 34 Chapter 9 Cost analysis The final cost for this project came in well below the initial proposed budget reproduced in Table 9 1 A number of factors contributed to this most notably the identification of a sufficiently accurate GPS module avai
41. proliferation of real time networked moni toring devices across the grid Doing so increases the resolution of data available to control room operators and regional administrators This will allow for the design of automatic control systems that can react faster than control room operators to counteract and confine disturbances on the grid The device will be entirely self contained with the only external connections to the internet and the residential wall outlet There should be no interaction between the resident of the house and the device initial installation will be done by the power company The device will be designed in compliance with the IEEE Std C37 118 in order to ensure compatibility with existing phasor data concentrators and visualization software Having an inexpensive PMU on the market opens up many possibilities for future development and supports some of the objectives of the smart grid In particular it will support increased use of distributed generation Distributed generation allows for the use of small sustainable sources to supplement or be the sole power source of small areas This capability is key to the spread of sustainable power 40 Appendix A Preliminary Circuit Diagram 41 usisop pesodoid reurumjord jo orjeureqos MOI IV 910314 3NMUNO_ 3NO9319V39 O and O ano o 0015 o O we O O ewe o O Niy o O oav VOND O O oav aan o O Id uds o O 089 tes o O ou uuvn o O axi Lien O O 0x8 ziuvn
42. s but has yet to achieve full compliance with IEEE C37 118 1 10 Chapter 3 Design Requirements 3 1 Performance A vast majority of the performance requirements for this project are drawn from the IEEE Standard for Synchrophasor Measurements for Power Systems 11 its 2014 amendment 12 and the IEEE Standard for Synchrophasor Data Transfer for Power Systems 13 Two classes of performance are laid out in the standards P for fast response with no explicit filtering and M for analytic measurements sttausceptible to aliasing Adherence to these standards will ensure that the device is compatible with existing phasor data concentrators PDCs and visualization software The device is broken down into seven different component parts as shown in Figure 3 1 The measurement source is a 120v residential outlet A step down circuit lowers the voltage of the measurement source into the range of the A D converter This circuit will also provide DC power for the device itself An analog anti aliasing filter will be used to limit the signal bandwidth before sampling The signal passes through an A D converter that samples in synchronicity with the time source The time source provides an absolute time reference to the A D converter and the Synchrophasor Estimator The Synchrophasor Estimator will calculate the magnitude of digital signal and run it through a phase estimation algorithm PEA The resulting magnitude and phase estimation will be given a
43. s chosen as the computing platform It has a 1 GHz proces sor which outperforms the Raspberry PI s 700 MHz a built in ethernet port for internet connection and an onboard ADC with eight input channels The Black also can run the Debian or Ubuntu Linux distributions Using these Linux distributions provides built in support for remotely accessing the device and a large package database to pull from when implementing components of the project Of the most consequence in choosing this board was the NEON and Programmable Realtime Unit PRU subsystems The NEON subsys tem provides hardware acceleration for floating point calculations and a implementation of 17 the Fast Fourier Transform that utilizes this capability has already been developed Uti lizing this library will allow for the reduction of the computational load on the processor which in turn should enable the device to achieve a higher reporting rate The PRU es sentially an onboard microcontroller in which the execution of each instruction is fixe is significant because all of the instructions available in this subsystem have a fixed execu tion time of 5ns The PRU interfaces directly with the ADC subsystem and the Black s onboard memory meaning it can acquire data from both the GPS and AC voltage inputs to the ADC and store it for processing in a fixed known amount of time that can be easily compensated for in the final calibration of the device 4 1 2 GPS Module As stated in
44. smission network was impractical due to geographic separation between the two Implementation of synchrophasors allows for easy calculation of magnitude and phase differences between nodes based off a shared standard time 2 2 Previous Work The concept of a synchrophasor was first introduced in the 1980s and has since generated a large body of commercial and academic research It is impossible to address all work p t0 Corrected for any filter delay Cosine Reference Cosine Reference UTC Time Reference 1 UTC Time Reference 2 Figure 2 1 Phase calculation based on UTC reference Source 6 a time tag 90 time phasor representation b time tag 90 z gt 80 A Dh time phasor representation Figure 2 2 Angle convention for synchrophasors Source 7 OpenPMU Time Source Receiver Disciplined Oscillator Local Clock Time Signal Input Signals Synchrophasor nd Data Signal K HH j Figure 2 3 OpenPMU block diagram Source 10 on synchrophasors and their applications in the scope of this project so emphasis will be placed on development of inexpensive PMUs K Kirihara B Pinte and A Yoon designed and tested a relatively low cost approx imately 1050 PMU as part of an undergraduate senior project described in 8 Their project utilized a National Instruments sbRIO for digital filtering and calculation of syn chrophasors Global Positioning Sy
45. stem GPS was used to generate the time reference The project was able to successfully measure phasors but utilized only the National Elec trical Code residential voltage standards to test the PMU ignoring IEEE C37 118 1 T he group also did not address the transmission of synchrophasors to a centralized server or phasor data concentrator PDC In Brian Miller s Masters thesis 9 alternatives for conventional current transducers are considered Miller also examines the use of wireless networks for time synchronization under the IEEE 1588 standard Use of wireless networks is found to provide a viable alternative to GPS synchronization useful in areas where signal strength is diminished It would also provide a cost reduction due to the elimination of the GPS module These proposed changes were found to be viable improvements while remaining compliant with the IEEE C37 118 1 standard In order to lessen the restrictions of proprietary hardware and algorithms on the progress of PMU development the OpenPMU 10 group was formed dedicated to de signing open source platform for synchrophasor applications and research The group utilizes a standard data acquisition device DAQ from National Instruments and a GPS receiver from Garmin as the basis for the OpenPMU A PIC from Microchip synchronizes the DAQ to the GPS timecode The OpenPMU uses the Python scripting language run ning on Microsoft Windows It is currently able to measure synchrophasor
46. ta from one channel as outlined in Figure Two steps will be used to acquire both the AC voltage waveform and the pulse per second signal from the GPS The minimum delay between sampling steps is 15 ADC clock cycles a value that must be taken into account in the calibration of the device 5 1 4 GPS Timing The Ultimate GPS module from Adafruit is largely self contained necessitating only a few external connections to enable functionality of the chip An onboard voltage regulator enables the use of sources from 3 3 to 5v both of which are available on the pinout of the BeagleBone Black 3 3v was chosen for the supply voltage simply because the 5v pin was already connected to the low pass filter circuit Communication between the GPS module and the Black is handled by the Universal Asynchronous Receiver Transmitter UART National Marine Electronics Association NMEA sentences a standard format for GPS data are received from the GPS via UART and used to assign UTC time tags to phase measurements The PPS signal is acquired via the onboard ADC in conjunction with the AC voltage waveform This signal serves as the marker for the start of a Discrete Fourier Transform DFT window The output of VFix which is pulled low when a strong signal is found is connected to a general purpose input output indicating when the GPS is ready for measurement to begin 22 8 8 HHV VDDA 2 2 p Domain E Z g o PENIRO lt 1 0 gt IN
47. uency 50 Hz 60 Hz Reporting Rates frames per second 10 25 10 12 15 20 30 Table 3 1 Required synchrophasor reporting rates Source 13 3 1 3 Timing Synchrophasors must by definition be recorded with respect to an absolute time reference The absolute reference used by IEEE C37 118 1 is Coordinated Universal Time UTC UTC can be obtained from either a GPS receiver or through the internet based Precision Time Protocol PTP 15 The time must be accurate within 26us according to the standard Receiving UTC via the internet is more practical for the scope of this project as GPS signals can be very weak indoors However testing is needed to confirm that synchronization with internet time servers can be achieved with sufficient accuracy Each synchrophasor must be given a time tag according to Coordinated Universal Time UTC The time tag consists of three numbers a System On a Chip SOC count a fraction of second count and a time status value SOC is specified as a 4 byte binary count of the number of seconds since the Unix epoch 00 00 January 1 1970 Occasionally a leap second must be inserted to keep SOC synchronized with UTC which is specified using a special case of the fraction of second as specified in section 4 3 of 11 Time status indicates the reliability of the clock which can become unsynchronized due to loss of signal Values for time status are specified in Table 6 of 11
48. ure 5 4 Flowchart for ADC subsystem step sequencer Source 22 24 completed it is paired with its corresponding GPS time tag and transmitted via ethernet Component Source Mfr Part Num Cost BeagleBone Black Adafruit 1876 55 00 Ultimate GPS Adafruit 746 39 95 GPS Antenna Adafruit 960 12 95 5v 2A DC Power Supply Adafruit 276 7 95 14 1 Power Transformer DigiKey HM510 ND 19 82 LM358 Single Supply Op Amp DigiKey LM358NFS ND 0 49 Table 5 1 Bill of Materials 25 Chapter 6 Final Design 6 1 Hardware Design 6 1 1 Voltage Step Down Connection to the wall will be made with a NEMA 5 15 compliant connector the common standard for residential outlets 17 The ADC input range of the BeagleBone Black is 0 to 1 8v 22 but going directly to this range would require a transformer ratio of 66 7 1 or greater something that is not commonly found in 120v transformer offerings A 14 1 transformer was chosen instead because of its availability and price This transformer yields a 8 57v peak to peak output when connected to the 120v wall outlet The voltage is further reduced into the ADC range by attenuation in the low pass filtering circuit Input Protection Although 120v is not as dangerous as the high voltage that commercial PMUs measure it is important that this device have safety features to protect both the low voltage electronics and the end user A 0 5A fast acting fuse was placed between the hot wire of the plu
49. y entrypoint START program entry point used by debugger only include ADCOCollector hp REGISTER ADDRESS DEFINITIONS define ADC CTRL 0x44E0D040 FF define SYSCONFIG 0x44E0D010 define ADCSTAT 0x44E0D044 define ADC_CLKDIV 0x44E0D04C define IRQENABLESET 0x44E0D02C define IRQENABLE CLR 0x44E0D030 define IRQSTATUS 0x44E0D028 define FIFOOCOUNT 0x44E0D0E4 define FIFOOTHRESHOLD 0x44E0D0E8 define STEPENABLE 0x44E0D054 define STEPCONFIGI 0x44E0D064 define STEPDELAYI 0x44E0D068 define STEPCONFIG2 0x44E0D06C define STEPDELAY2 0x44E0D070 Data locations define FIFOODATA 0x44E0D100 Variable definitions define BUFF SIZE 0x0000FA0 Total buff size 2kbyte 500 piece of data define HALF SIZE BUFF SIZE 2 define FIFOTHRESHOLD 0x00000031 value 1 7 define FIFOTHRESHOLDNUM FIFOTHRESHOLD 1 Ho pp Sf UMM AT AT AT TT AT TT ATT TT TT TT TT TT TT TT TT TT TTT TT 48 4kbyte Each buffer has 34 MACRO DEFINITIONS 35 EE 36 37 macro FIFOWAIT 38 FIFO 39 LBBO r3 r13 0 4 40 QBBC FIFO r3 t2 41 endm 42 43 macro READADC 44 Initialize buffer status 0 empty 1 first buffer is ready 2 second buffer is ready 45 MOV r2 0x0 46 SBCO r2 CONSTPRUSHAREDRAM 0 4 47 MOV r7 HALF_SIZE 48 49 MOV r12 FIFOODATA 50 MOV r10 FIFOOCOUNT 51 MOV r13 IRQSTATUS 52 53 MOV r5 0 Shared RAM address of ADC Saving position 54 MOV r6 BUFF SIZE Countin
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