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AT-DIO-32F User Manual

1. register int chiy clos if chi fgetc who EOF EOF will be word length return EOF Don t read beyond EOF clo fgetc who Read the high byte return chi amp OxFF 8 clo amp OxFF Return word End getwd putwd is a unix command Note that the functions place characters in the file one at a time and checks for an EOF with every character This prevents writing EOF to a file ar putw word who int word FILE who if word gt gt 8 amp OxFF EOF return EOF else National Instruments Corporation C 9 AT DIO 32F User Manual Application Notes Appendix C fputc word gt gt 8 amp OxFF who if word amp OxFF EOF return EOF else fputc word amp OxFF who return word End putw The AT DIO 32F and I O Module Racks The AT DIO 32F is pin compatible with several 32 channel I O module racks produced by several different companies Any I O module rack pin compatible with the DEC DRV11 J parallel interface is pin compatible with the AT DIO 32F The AT DIO 32F can also be used with I O module racks that are not pin compatible if a special cable is built The AT DIO 32F is directly pin compatible with the following I O module racks opT0 22 PB32DEC PB 32SM PB 32Q PB32D The AT DIO 32F can be used with the following I O module racks if connected with a cable indicated
2. eee 4 40 Figure 4 3 Leading Edge Mode Write Handshake Timing LPULSEx cleared 4 41 Figure 4 4 Leading Edge Mode Read Handshake Timing LPULSEx cleared 4 41 Figure 4 5 Leading Edge Mode Read Write ACK Pulse Width with LPULSEX OF GEGA Set 22e atte perta rte PE Seu Exo FUROR LIMES Int AREAS 4 41 Figure 4 6 Trailing Edge Mode Write Handshake Timing eee 4 42 Figure 4 7 Trailing Edge Mode Read Handshake Timing eee 4 42 Pigured 5 Pattern Generation za oec a a heen Ab aetna 4 51 Figure 4 9 RTSI Switch Control PaHert oues oie iiu ont esa IUe nna 4 54 Figure B 1 AT DIO 32F W O Connector euro oreet eRe ade B 1 AT DIO 32F User Manual viii National Instruments Corporation Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table C 1 Contents Tables AT DIO 32F Factory Set Jumper and Switch Settings se 2 2 Default Settings of National Instruments Products for the PC 2 6 Switch Settings with Corresponding Base I O Address and Base lO Address Spuee ates secte dutmutedetindadtutunddtsbpas tte ae f orsa ce dl pht 2 7 DMA Channels for the AT DIO 32F i niue etoile herede iet peace 2 8 Configurations for RTSI Bus Clock Selection sees 2 11 AT DIO 32F Register Map rnm e raet en ran ehh
3. 7 Write hex A414 to the CFG3 Register to start pattern generation on Counter 1 set the CNTIEN bit The counter is loaded with the initial count in the CNTRI Register and when the CNT1EN bit is set the counter is decremented by 1 on each clock pulse REQI is initially high When the counter decrements to 1 REQI goes low for one clock pulse and then returns to high The counter is then reloaded from the CNTR1 Register and decrementing continues The trailing edge of REQI causes the DRDYI bit to go high The DRDYI bit can be monitored by a polling loop by interrupt request generation or by DMA request generation With one of these methods data can then be written out to Port A The programming steps to set up Counter 2 for pattern generation are as follows 1 Setup Counter 2 for rate generation by writing hex 54 to the CNTRCMD Register for an 8 bit count or by writing hex 74 to the CNTRCMD Register for a 16 bit count 2 Write the count to the CNTR2 Register see Table 4 5 If the count is a 16 bit value write the least significant byte first then the most significant 3 Write hex 20 to the CFG3 Register to enable Counter 2 for pattern generation set the CNT2HSEN bit 4 Setup Group 2 for trailing pulse mode and to clear handshaking write hex 0378 to the CFG2 Register for an 8 bit Port C or write hex 0778 to the CFG2 Register for a 16 bit Port C 5 Write hex 0278 for 8 bit or 0678 for 16 bit to the CFG2 Register to f
4. fp fopen filename r Open file for reading if valid_file Test if valid file send_file Read file and send fclose fp End send main Send a file to the AT DIO 32F send file int word Read in words from file and send do while no EOF in low byte while word getwd fp amp OxOOFF lowEOF send_word word send word word This last word read and sent contains an EOF End send_file Send a word to the AT DIO 32F send word wd int wd while data out rdy Wait until ok for data to be written putw wd stdout Echo characters to screen outpw PORTC wd Send a 16 bit word to the MC DIO 32F Return non zero value if the AT DIO 32F is ready to be written more data data out rdy return inpw STAT1 amp 0x0004 Returns DRDY2 bit RR KKK KKK KK ke ke KK KKK Routines for Receiving Data eR KK KK RK KK f Receive 16 bit data from the other AT DIO 32F get main int word printf nEnter the name of the file to receive data n scanf s filename fp fopen filename w Open file for writing printf nWaiting to receive data n n Gets chars until an EOF is received in the low byte while word in_word amp OxOFF lowEOF putw word stdout Echo word to screen p
5. 5 4 RWSEL lt 1 0 gt The Counter Latch command latches the current count of the register selected by CNTRSEL1 and CNTRSELO The next read from the selected counter returns the latched data 3 1 MODESEL 2 0 Counter Mode Select Bits These bits select the counting mode of the selected counter The following table lists six available modes and the corresponding bit settings Refer to Appendix D ntel Data Sheet for additional information MODESEL2 MODESEL1 MODESELO Mode 0 Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot 1 Mode 2 Rate Generator 1 1 Mode 4 Software Retriggerable Strobe 1 Mode 5 Hardware Retriggerable Strobe Ult 1 Mode 3 Square Wave Mode Baha 0 BCDSEL Binary Coded Decimal Select Bit If BCDSEL is set the selected counter keeps count in BCD If BCDSEL is cleared the selected counter keeps count in 16 bit binary AT DIO 32F User Manual 4 34 National Instruments Corporation Chapter 4 Programming Read Back Command When bits 7 and 6 CNTRSELI and CNTRSELO are 1 the CNTRCMD Register can be used to execute the Read Back command With the Read Back command the current totals of multiple counters can be latched in one command The Read Back command also can latch the status of selected counters The control word format used for the Read Back command is as follows 7 6 5 4 3 2 1 0 CNTRSELI CNTRSELO COUNT STATUS CNTR3 CNTR2 CNTRI 0 Bit N
6. MEE Ce NE H T13 single buffered Data output mode MEM a ae double buffered I T10d 9 T10c Name Description Minimum Maximum TOa REQ pulse width in level mode 125 TObc REQ pulse width in leading or trailing edge 100 mode TI REQ low duration 160 T2ab REQ to DRDY in level or leading edge mode 0 225 T2c REQ inactive to DRDY in trailing edge mode 0 100 T3 Start of read or write to DRDY inactive 50 240 T4 DRDY to read or write 0 T5 End of read or write to TDELAY with TDELAY equal to 0 0 175 with TDELAY not equal to 0 50 360 T6 TDELAY programmable 0 700 T7ab TDELAY to ACK in level mode or in 10 100 leading edge mode without LPULSE T7c Start of read or write to ACK in trailing edge 60 220 mode T7d End of read or write to ACK in leading edge 0 180 AT DIO 32F User Manual mode with LPULSE set 2 18 National Instruments Corporation Chapter 2 T8a T8b T8c T9a T9b T9c T10ab T10c T10d T11 T12 T13 T14 T15 T16 T17 REQ to ACK inactive in level mode REQ inactive to ACK inactive in leading edge mode but T9b can prolong ACK TDELAY to ACK inactive in trailing edge mode ACK pulse width in level mode delaying REQ prolongs ACK ACK pulse width in leading edge mode without LPULSE but T8b can prolong ACK ACK pulse width in trailing edge mode increasing TDELAY prolongs ACK ACK to next REQ in level mode or in leading edge mode without LPULSE ACK inactive to
7. When another rising edge pulse on Counter 3 is received software control again jumps to the interrupt service routine National Instruments Corporation 4 47 AT DIO 32F User Manual Programming Chapter 4 DMA Transfers DMA increases transfer rates when handshaking data is transferred to or from the PC memory Each handshaking group can be assigned a separate DMA channel by setting the jumper on W1 see Chapter 2 Configuration and Installation for details There are two DMA modes single channel DMA for Groups 1 and 2 and double channel DMA using Group 1 handshaking In single DMA mode enable DMA transfers for each group by setting DMAENI and DMAEN2 in the CFG1 and CFG2 Registers for Group 1 and Group 2 respectively The DMA request is asserted when the DRDY bit for the enabled group is set The DMA controller sends a terminal count when the value in its Terminal Count Register changes from hex 0000 to hex FFFF See the nterrupt Handling section earlier in this chapter for information about generating an interrupt on the DMA terminal count Refer to the JBM Personal Computer AT Technical Reference manual for additional information about programming the DMA controller In double DMA mode DBLDMA bit set in the CFG3 Register only Group 1 handshaking lines are used for 16 bit DMA transfer but both DMA channels should be enabled DMA transfers use the DMA channel for Group 1 until a DMA terminal count for Group 1 is received then the D
8. o O 0 LPULSE2Z LPULSE DBLBUFD REVC Bit Name Description 15 4 Reserved Bits These bits must be set to zero 3 LPULSE2 Long Pulse Bit for Group 2 This bit selects the data settling delay mode of the leading edge pulse handshaking mode for Group 2 If this bit is set the delay is added after the leading edge of the ACK pulse therefore the pulse width is lengthened The delay is 0 to 700 nsec depending on the settings of T2S lt 2 0 gt If this bit is cleared the delay is added before the leading edge of the pulse therefore the pulse width is fixed 2 LPULSEI Long Pulse Bit for Group 1 This bit selects the data settling delay mode of the leading edge pulse handshaking mode for Group 1 If this bit is set the delay is added after the leading edge of the ACK pulse therefore the pulse width is lengthened The delay is 0 to 700 nsec depending on the settings of T1S lt 2 0 gt If this bit is cleared the delay is added before the leading edge of the pulse therefore the pulse width is fixed AT DIO 32F User Manual 4 14 National Instruments Corporation Chapter 4 Bit 1 0 Name DBLBUFD REVC Programming Description continued Port D Double Buffer Enable Bit If DBLBUFD is set Port D is double buffered When Port D is configured as an output port a write operation to the port loads data into the first buffer of the port When a REQ is received the data is transferred to
9. Chapter 2 Configuration and Installation explains the installation of the AT DIO 32F board into your computer signal connections to the AT DIO 32F board and cable wiring Chapter 3 Theory of Operation explains the basic operation of the AT DIO 32F circuitry e Chapter 4 Programming describes in detail the address and function of each of the AT DIO 32F control and status registers This chapter also includes important information about programming the AT DIO 32F Appendix A Specifications lists the specifications for the AT DIO 32F e Appendix B O Connector and Register Descriptions contains a description of the AT DIO 32F I O connector and references to the registers of the AT DIO 32F e Appendix C Application Notes contains the application notes for the AT DIO 32F board e Appendix D Intel Data Sheet contains the 8254 Programmable Interval Timer Intel Corporation data sheet This counter timer device is used on the AT DIO 32F board e Appendix E Customer Communication contains forms for you to complete to facilitate communications with National Instruments concerning our products The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics symbols and terms The ndex alphabetically lists topics covered in this manual including the page where the topic can be found National Instruments Corporation xi AT DIO 32
10. Figure 3 2 shows the clock routing scheme National Instruments Corporation 3 3 AT DIO 32F User Manual Theory of Operation Chapter 3 20 MHz RTSICLK pin oscillator of RTSI bus To handshaking circuitry BRDCLK BRDCLK Counter 3 Figure 3 2 AT DIO 32F Clock Routing Scheme Digital I O Connector All digital I O is through a standard 50 pin male connector The pin assignments for this connector are compatible with the DEC DRV11 J parallel interface and most 32 channel I O module racks Refer to Signal Connections in Chapter 2 Configuration and Installation for pin assignments and additional information Handshaking Circuitry The four 8 bit digital I O ports are divided into two handshaking groups Group and Group 2 These groups are independent of each other so two separate transfers can occur simultaneously AT DIO 32F User Manual 3 4 National Instruments Corporation Chapter 3 Theory of Operation Group 1 handshaking is controlled by REQ1 and ACK1 Group 2 handshaking is controlled by REQ 2 and ACK2 The handshaking circuitry controls these handshaking signals and the data flow through the digital I O data latches and drivers Each group can be programmed to operate in one of three handshaking modes level signals leading edge signals or trailing edge signals Refer to Chapter 2 Configuration and Installation and Chapter 4 Programming for the timing diagrams for each of these modes The state diagrams
11. The output of Counter 3 is programmed as follows 1 Set up Counter 3 for square wave generation by writing hex 96 to the CNTRCMD Register for an 8 bit count or hex B6 for a 16 bit count 2 Write the count to the CNTR3 Register see Table 4 4 If the count is a 16 bit value write the least significant byte first then the most significant The following equation is used to calculate the output frequency of Counter 3 Counter 3 Output Frequency 2000000 data written to counter Counters 1 and 2 can use either a 10 MHz clock or the output of Counter 3 as the counting source If the counting source is the 10 MHz square wave then the following equation is used to calculate the output frequency of the counter Counter 1 2 Output Frequency 10000000 data written to counter If the counting source is the output of Counter 3 then the following equation is used for calculating the output frequency of the counter Counter 1 2 Output Frequency Counter 3 output frequency data written to counter Table 4 5 Counters 1 and 2 Programmable Frequency Output Source 10 MHz Data Written to CNTR1 Counter Output Frequency Pattern Interval or CNTR2 hex 6 58 msec 3 28 msec 1 67 msec 820 0 usec 410 0 usec 260 0 usec 200 0 usec 100 0 usec 25 6 sec usec usec usec usec usec usec usec nsec nsec AT DIO 32F User Manual 4 50 National Instruments Corporation Chapter 4 Programming The ports used for pattern generation
12. This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK puise and counting will continue from the AT DIO 32F User Manual AT DIO 32F User Manual Intel Data Sheet Appendix D I letwdwtotetsls fe dsls CWz14 LSB 3 0 0 0 a lujw wim s s s s LSB a4 CWa14 0 3 ERE LSB 5 pone erret Imlelelededsiolsdedels NOTE A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely D 14 Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK puise and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When
13. To use the Group 1 DMA terminal count interrupt service routine follow these steps 1 Setup Group 1 with the desired handshaking mode and direction 2 Setthe TCINTENI bit in the CFG3 Register to enable interrupts on Group 1 DMA terminal counts 3 Enable DMA for Group 1 transfers 4 Program the PC DMA controller 5 When a Group 1 DMA terminal count is received an interrupt request is asserted and software control enters the interrupt service routine In the interrupt service routine follow these steps a Check the DMATCI bit in the STAT Register to verify that the current interrupt was generated by a Group 1 DMA terminal count condition b Perform the desired work c Write to the DMACLRI Register to acknowledge that the Group 1 DMA terminal count interrupt condition has been serviced When another Group 1 DMA terminal count is received software control again jumps to the interrupt service routine AT DIO 32F User Manual 4 46 National Instruments Corporation Chapter 4 Programming Example Interrupt Generation on Group 2 DMA Terminal Count To use the Group 2 DMA terminal count interrupt service routine follow these steps 1 2 Set up Group 2 with the desired handshaking mode and direction Set the TCINTENO bit in the CFG3 Register to enable interrupts on Group 2 DMA terminal counts Enable DMA for Group 2 transfers Program the PC DMA controller When a Group 2 DMA terminal count is received an i
14. an interrupt request is asserted and software control enters the interrupt service routine In the interrupt service routine follow these steps a Check the DRDYI bit in the STAT Register to verify that the current interrupt was generated by a DRDY 1 condition b Write or read data to or from Group 1 When DRDY 1 becomes set again software control again jumps to the interrupt service routine National Instruments Corporation 4 45 AT DIO 32F User Manual Programming Chapter 4 Example Interrupt Generation on DRDY2 Instead of polling the DRDY2 bit interrupts can be used to wait for the DRDY2 condition The interrupt service routine can then write or read the data to or from Group 2 To use interrupts for this task follow these steps 1 Set up Group 2 with the desired handshaking mode and direction 2 Set the INTEN2 bit in the CFG2 Register to enable interrupts on DRDY2 3 When DRDY 2 is set an interrupt request is asserted and software control enters the interrupt service routine In the interrupt service routine follow these steps a Check the DRDY2 bit in the STAT Register to verify that the current interrupt was generated by a DRDY2 condition b Write or read data to or from Group 2 When DRDY2 becomes set again software control again jumps to the interrupt service routine Example Interrupt Generation on Group 1 DMA Terminal Count The DMA terminal count signals the end of the current DMA transfer
15. char filename 80 main int i base address is input from the key board printf NMnEnter the base address Hex 4 scanf x amp base address printf nbase_address x Hex base address echo print calculate registers address cfgl base address CFGloffset cfg2 base address CFG2offset cfg3 base address CFG3offset cfg4 base address CFG4offset tstat base_address STAToffset porta base_address PORTAoffset AT DIO 32F User Manual C 2 National Instruments Corporation Appendix C Application Notes set up AT DIO 32F to communicate with printer Setup DIO setup the AT DIO 32F get the chars to print and send out printf nEnter the name of the file to print n scanf s filename gets filename fp fopen filename r if Valid file test if a valid file opened Read n Write read the file and send to printer fclose fp main RK KKK Kok k ke e ke ke Kk kkk functions OKCKCKCkCkCk kc k Ck kc k Ck kck ck kck ck kckck ck ok ck ckok ck ke kk ke ke e x kx x f read file and print Read n Write char ch while ch fgetc fp EOF print chars until EOF is reached Print_char ch Print_char 0x0OD send linefeed to complete printing check whether given filename is valid Valid_file if fp NULL printf n
16. hex 8 bit write only Bit map not applicable no bits used CNTRI1 Register REQ1 Generator Base Address Offset 18 hex 8 bit read and write 7 6 5 4 3 2 1 0 CNTR2 Register REQ2 Generator Base Address Offset 1A hex 8 bit read and write 7 6 5 4 3 2 1 0 CNTR2B7 CNTR2B6 CNTR2B5 CNTR2B4 CNTR2B3 CNTR2B2 CNTR2B1 CNTR2BO AT DIO 32F User Manual B 4 National Instruments Corporation Appendix B I O Connector and Register Descriptions CNTR3 Register Timebase Generator Base Address Offset 1C hex 8 bit read and write 7 6 5 4 3 2 1 0 CNTR3B7 CNTR3B6 CNTR3B5 CNTR3B4 CNTR3B3 CNTR3B2 CNTR3BI CNTR3BO CNTRCMD Register Base Address Offset 2 1E hex 8 bit write only 7 6 5 4 3 2 1 0 CNTRSELI CNTRSELO RWSEL1 RWSELO MODESEL2 MODESEL1 MODESELO BCDSEL Read Back Command 7 6 5 4 3 2 1 0 CNTRSELI CNTRSELO COUNT STATUS CNTR3 CNTR2 CNTRI 0 Status Byte 7 6 5 4 3 2 1 0 National Instruments Corporation B 5 AT DIO 32F User Manual Appendix C Application Notes This appendix contains the application notes for the AT DIO 32F board The versatile AT DIO 32F can interface the PC to almost any 8 bit 16 bit or 32 bit parallel device or I O module rack These programs explore the several handshaking modes of the AT DIO 32F and can easily be modified to fulfill your own specialized communication needs All programs were written in Microsoft C Functions within the prog
17. the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software aiso Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When haif the AT DIO 32F User Manual Intel Data Sheet Appendix D intel 8254 BBBDHHY CW 10 LSB 3 Ieleteledsisledsie tele CWz 0 15823 LSB a2 Injini saele NOTE The following conventions apply to ali mode timing diagrams 1 Counters are programmed for binary not BCD counting an
18. 32F User Manual Intel Data Sheet Appendix D intel 8254 WAVEFORMS Continued RECOVERY 231164 15 231164 16 A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT DESC 231164 17 I AC Testing Inputs are driven at 2 4V for a Logic 1 and 0 45V for a Logic 0 Timing measurements are made at 20V fora Logic 1 and 0 8V for a Logic 0 231164 18 C 150 pF C Includes Jig Capacitance AT DIO 32F User Manual D 22 National Instruments Corporation Appendix E Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 00 Germa
19. C New Count is loaded into Null Count 0 CE CR CE NOTE 1 Only the counter specified by the contro word will have its Null Count set to 1 Null count bits of other counters are unaffected 2 If the counter is programmed for two byte counts least significant byte then most significant byte Null Count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both Command D Dg Ds D4 D3 D2 D Do Read back count and status of Count and status latched Counter 0 pov IUE Counter 0 rir r o or fo fo ressback ss rot Read back status of Counter 1 Status latched for Counter 1 Read back status of Counters 2 1 Status latched for Counter eee but not Counter 1 Pits Pots sf ole o reeds oouo vm M Read back count of Counter 2 Count latched for Counter 2 Read back count and status of Count latched for Counter 1 Counter 1 but not status Ld Ll lames COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count an
20. Figure 2 5 DMA Jumper Settings for Disabling DMA Transfers ees 2 9 Figure 2 6 Interrupt Jumper Settings IRQ11 and IRQ12 Factory Settings 2 9 Figure 2 7 Interrupt Jumper Settings for Disabling Interrupts sees 2 10 Figure 2 8 Interrupt Jumper Setting IRQ5 Only eee 2 10 Figure 2 9 Disconnect from RTSI Bus Clock Use Onboard Oscillator Factory Settings sene 2 11 Figure 2 10 Receive RTSI Bus Clock Signal 1522 eo eee ton be e pte panis 2 11 Figure 2 11 Drive RTSI Bus Clock Signal with Onboard Oscillator 2 11 Figure 2 12 Digital I O Connector Pin Assignments seen 2 13 Figure 3 1 AT DIO 32F Block Diagram aiu tace qe adt itti emet 3 1 Figure 3 2 AT DIO 32F Clock Routing Scheme seen 3 4 Fig re 3 3 Level Modes Redd niseni oaie eE Ee ta e Loss ede eei vociaip m idee 3 5 Figure 3 4 Level Mode Write 1 cniaoidiieep eii De ped ie ira EU isinisi eed 3 6 Figure 3 5 Leading Edge Mode Bead hoon iere topi Attia enna 3 7 Figure 3 6 Leading Edge Mode WIE see eodeni Beto Ue IMS 3 8 Figure 3 7 Trailing Edge Mode Reales ius qed scere radit pnt EO RO RE pee 3 9 Figure 3 8 Trailing Edge Mode Write ose ie ee ie 3 10 Figure 4 1 Level Mode Write Handshake Timing eee 4 40 Figure 4 2 Level Mode Read Handshake Timing
21. Instruments Corporation Appendix C Application Notes End of setup_dio Ask to send or receive data and then do it choose what char ch choose_msg ch getch I while ch e amp amp ch E switch ch case S case s User wants to send data send main Send data choose msg Give choice again break End case s case R case r User wants to receive data get main Get the data choose msg Give choice again break End case r End switch ch getch End while printf nExit requested User selected e for exit P End choose what Message for choose what choose msg printf n nDo you want to send s or receive r data or exit e End choose msg Check whether given filename is valid valid file if fp NULL printf can t open the file s n filename return 0 End if else return 1 file exists go ahead End valid file RR KKK KKK ke e ke KKK Routines for sending data XOkckckck ck ko KK e x e KK Get data and send to another board send main printf nEnter the name of the file to send n scanf s filename National Instruments Corporation C 7 AT DIO 32F User Manual Application Notes Appendix C
22. Instruments Corporation Appendix D Intel Data Sheet This appendix contains the 5254 Programmable Interval Timer Intel Corporation data sheet This counter timer device is used on the AT DIO 32F board Copyright O Intel Corporation 1989 Reprinted with permission of copyright owner All rights reserved Intel Corporation 1989 Data Book Microprocessor and Peripheral Handbook Volume II Peripheral National Instruments Corporation D 1 AT DIO 32F User Manual Intel Data Sheet Appendix D intel 8254 PROGRAMMABLE INTERVAL TIMER a Compatible with All intel and Most B Six Programmabie Counter Modes Other Microprocessors B Three Independent 16 Bit Counters mg Handles Inputs from DC to 10 MHz r 5 MHz 8254 5 E etary or BCD Counting 8 MHz 8254 m Single 5V Supply 10 MHz 8254 2 m Available in EXPRESS w Status Read Back Command Standard Temperature Range The intel 8254 is a counter timer device designed to solve the common timing control problems in micro computer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmabie The 8254 is a superset of the 8253 The 8254 uses HMOS technology and comes in a 24 pin plastic or CERDIP package BUS BYFFER 231164 2 Figure 2 Pin Configuration 231164 1 Figure 1 8254 Block Diagram August 1987 6 25 Order Number 231164 004 AT DIO 32F User Manual D 2 National
23. Interface eun onis ett ents 4 53 Programming the RTSI Bus Switch eeeeeereee 4 54 Initializing the RTSI Bus Switch usu eid teen eases 4 55 Appendix A Specifications icra iade aie he opines dts esiti o ond id i cba iv totos iam A 1 Appendix B I O Connector and Register Descriptions sese B 1 D O Cone CEO ooa de ote otis abe Sc Stele es pee Ed ee eee eater teeta B 1 AT DIO 32F Register DeSCHDOFTS oos ohode e eo be seacdaseqachaisgacsdcsesaeeeatanccansonancisasncenienes B 2 E E EA A EA EESE A opino ead ttem acd E sdb B 2 CFO RGBISIGE erore e ea trn aen a ead ree 1a Pat aer oO ovi aede oen B 2 CGS Register T E B 2 CBGIA IRE CISUCT aate chien cette r caet e e a o a Ee a e aS eh B 2 STAT Resisti sa escena diu OO Wisin EN Dd neta pi Reb B 3 CNTINTCLER REPISUE cuis est n eO Have D E ocior lana testes Evo Une Revo quts B 3 DMACLR I R gister oon teteeaniiennes B 3 DMACER BOSISISE canas n Ne pe E e A ES B 3 POCA RESISTE aoin na e a r we cana a Ste IM UR B 3 Port TS Resister r sinnini Ee E ay E E E aca B 3 POLL C RO SISIeT aen addit qua A seme A O EENG B 4 POIL D Reblslet o5 oeste desto oh cans ups e daten o gates tes teas Albun iat B 4 RISISHET Registe scs nomade estas mu imn ict S mE B 4 RTS US TRE RSIS UCR opis ee atc isn e GNI E oe uad km eats ce s ee DE B 4 CNTRI Register REQI Generator essen B 4 CNTR2 Register REQ2 Generator csscecssccssssscsensscsensscessaccs
24. LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEWS NI DAQS and RTSI are trademarks of National Instruments Corporation Product and company names liste
25. PC for specific instructions and warnings 1 2 Turn off your computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Insert the AT DIO 32F into a 16 bit slot It may be a tight fit but do not force the board into place If you want to connect multiple AT Series boards attach a RTSI cable to the RTSI connector at this time Screw the mounting bracket of the AT DIO 32F to the back panel rail of the computer Check the installation Replace the cover The AT DIO 32F board is installed and ready for operation AT DIO 32F User Manual 2 12 National Instruments Corporation Chapter 2 Configuration and Installation Signal Connections I O Connector Pin Description Figure 2 12 shows the pin assignments for the AT DIO 32F digital I O connector Warning Connections that exceed any of the maximum ratings of input or output signals on the AT DIO 32F may result in damage to the AT DIO 32F board and to the PC Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from any such signal connections O Nn BYR BRL BRI Bl QS OO OD OTTO DO NON NMI NPR AIN eOojoj n5jmjojojo jo rjojo jo ro jojo o A ro o 9 Figure 2 12 Digital I O Connector Pin Assignments National Instruments Corporation 2 13 AT DIO 32F User Manual C
26. RTSI switch can drive any of the signals at pins A lt 6 0 gt onto any one or more of the seven RTSI bus trigger lines and drive any of the seven trigger line signals onto any one or more of the pins A lt 6 0 gt With this capability any AT Series board sharing the RTSI bus has a completely flexible signal interconnection scheme The RTSI switch is programmed via its select and data inputs On the AT DIO 32F board seven signals are connected to pins A lt 6 0 gt of the RTSI switch REQI REQ2 ACKI ACK2 INI RWGRPI and RWGRP2 These signals can be controlled over the RTSI bus or externally across the I O connector The RTSI bus connections send timing signals to other AT boards connected to the RTSI bus National Instruments Corporation 3 11 AT DIO 32F User Manual Chapter 4 Programming This chapter describes in detail the address and function of each of the AT DIO 32F control and status registers This chapter also includes important information about programming the AT DIO 32F The AT DIO 32F has four 8 bit ports divided into two handshaking groups Group 1 and Group 2 Each group can be independently programmed for input or output and a handshaking mode Counters onboard can be used for pattern generation for one or both handshaking groups A signal from another AT Series board can be sent across the RTSI bus to implement pattern generation as well This chapter contains the register descriptions and functional descriptions nece
27. User Manual Introduction Optional Equipment Equipment Signal Conditioning Accessories Cable Adapter Board for Signal Conditioning SC 2052 and 50 conductor cable 0 5m 1 0m Optically Isolated Digital Input SC 2060 and 26 conductor cable 0 2m 0 4m Optically Isolated Digital Output SC 2061 and 26 conductor cable 0 2m 0 4m Electromechanical Relay Digital Control SC 2062 and 26 conductor cable 0 2m 0 4m General Purpose Termination Breadboard SC 2072 with 50 conductor cable 0 5 m 1 0m Digital Signal Conditioning Modules SSR Series mounting rack and 1 0 m cable 32 channel 24 channel 16 channel 8 channel CB 50 I O connector block 50 screw terminals with 0 5 m type NBI cable with 1 0 m type NBI cable AT Series RTSI bus cables for 2 boards 3 boards 4 boards 5 boards Standard ribbon cable 0 5m 1 0m Shielded ribbon cable 0 5 m 1 0 m Ribbon cable with edge connection at one end 0 5m 1 0m Part Number 776335 02 776335 12 776336 00 776336 10 776336 01 776336 11 776336 02 776336 12 776358 02 776358 12 776290 32 776290 24 776290 16 776290 08 776164 01 776164 02 776249 02 776249 03 776249 04 776249 05 180524 05 180524 10 180554 05 180554 10 180723 05 180723 10 Chapter 1 The AT DIO 32F is equipped with an EMI shield on the I O connector that can be used to connect the shield of a shielded ribbon cable to the computer chassis Shielded ribbon cables are nec
28. by the specifications in Table C 1 Any pins not listed are not connected and should be left open Table C 1 Cable Specification for Connections to 8 16 or 24 Channel I O Module Racks OPTO 22 Potter amp Brumfield AT DIO 32F User Manual C 10 National Instruments Corporation Appendix C Application Notes AT DIO 32F I O Rack AT DIO 32F 1 V O Rack PAO 37 47 DataO PCO 14 15 Data 16 PAI 39 45 Datal PCI 12 13 Datal7 PA2 38 43 Data2 PC2 13 11 Data l8 PA3 40 4 Data3 PC3 11 9 Data 19 PA4 35 39 Data 4 PC4 16 7 Data 20 PA5 42 37 Data5 PC5 9 5 Data 21 PA6 36 35 Data6 PC6 15 3 Data22 PA7 41 33 Data7 PC7 10 Data23 PBO 47 31 Data8 GND 17 16 GND PB1 50 29 Data9 GND 19 18 GND PB2 44 27 Data 10 GND 21 20 GND PB3 48 25 Datall GND 23 22 GND PB4 49 23 Data 12 GND 28 28 GND PB5 43 21 Data 13 GND 30 30 GND PB6 46 19 Data 14 GND 32 32 GND PB7 45 17 Datal5 GND 34 34 GND The majority of these racks interface to parallel data through a 50 pin edge connector A cable must be made with a 50 pin edge connector on one end and a 50 pin header connector on the other The AT DIO 32F I O connector is a 50 pin male ribbon cable header Recommended manufacturer part numbers for this header are Electronic Products Division 3M part number 3596 5002 T amp B Ansley Corporation part number 609 5007 The mating connector for the AT DIO 32F is a 50 position polarized ribbon socket connector with strain relief National Instruments use
29. byte and the next one read for 8 bit mode or two reads for 16 bit mode returns the count bytes regardless of the order in which the information was latched National Instruments Corporation 4 31 AT DIO 32F User Manual Programming Chapter 4 CNTR3 Register Timebase Generator The CNTR3 Register contains eight bits that are used to load a value into Counter 3 or to read back the value of Counter 3 The CNTR3 Register can be used as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 1C hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTR3B7 CNTR3B6 CNTR3B5 CNTR3B4 CNTR3B3 CNTR3B2 CNTR3B1 CNTR3BO Bit Name Description 7 0 CNTR3B lt 7 0 gt Counter 3 Load Read Bits Writing a data value to these bits loads the starting value into Counter 3 Reading these bits returns the current count of Counter 3 or latched data for Counter 3 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 3 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the le
30. command may also be used to latch Status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system Ds D4 D3 D2 D omer le 1 OUT Pinis 1 0 OUT Pin is 0 Null Count 0 Count available for reading De Ds Do Counter programmed mode see Figure 7 Figure 11 Status Byte AT DIO 32F User Manual AT DIO 32F User Manual Intel Data Sheet Appendix D intel 8254 NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 This Action Causes A Write to the control word register 1 Null Count 1 B Write to the count register CR 2 Null Count 1
31. connector If DBLBUFA is cleared the port is transparent that is a read operation reads the data on the I O connector Group 1 Pulse Mode Bit When PULSE is set the Group 1 handshaking signals REQ1 and ACKI are configured as pulse signals When PULSE is cleared the Group 1 handshaking signals are configured as level signals Group 1 Leading Trailing Pulse Mode Bit When EDGEI and PULSE are both set the Group 1 handshaking signals are active on the trailing edge of the pulse When EDGEI is cleared and PULSE is set the Group 1 handshaking signals are active on the leading edge of the pulse 4 6 National Instruments Corporation Chapter 4 Programming Bit Name Description continued 2 INVACKI Group 1 Acknowledge Invert Bit When INVACK1 is set the handshaking acknowledge signal ACKI is configured as an active low signal Group 1 sends ACK1 as a low signal to acknowledge the end of a data transfer When INVACKI is cleared ACKI is configured as an active high signal Group 1 sends ACKI as a high signal to acknowledge the end of a data transfer 1 SETACKI Group 1 Acknowledge Control Bit Setting and clearing SETACKI controls the ACKI bit on the digital I O connector 0 OUTI Extra Output Bit 1 Setting and clearing OUTI controls the OUTI bit on the digital I O connector National Instruments Corporation 4 7 AT DIO 32F User Manual Programming Chapter 4 CFG2 Register The CFG2 Register contains 16 bits that con
32. consists of two buffers the write buffer and the output buffer Data written to the port is loaded into the write buffer When a handshaking request REQ1 or REQO is received on the I O connector for the double buffered group the contents of the write buffer are loaded into the output buffer Data loaded in the output buffer is driven on the digital I O lines Onboard Counters The AT DIO 32F includes three onboard counters useful for pattern generation and periodic data acquisition Counter 1 can be programmed to generate group 1 handshaking requests on the REQI line Likewise counter 2 can be programmed to generate group 2 handshaking requests on the REQ2 line Counter 3 can alter the counting rate of the other two counters and can also be programmed to generate periodic interrupts The clock that runs the counters BRDCLK connects to a 10 MHz clock source either an onboard clock OSC or to the RTSI clock line RTSICLK With BRDCLK connected to both OSC and RTSICLK the onboard clock source can drive both the counters and the RTSI clock line See RTSI Bus Clock Selection in Chapter 2 Configuration and Installation for information about connecting the BRDCLK signal The signal you select for BRDCLK is slowed by a factor of 5 creating a 2 MHz clock signal that operates Counter 3 The output of Counter 3 forms a time base for Counters 1 and 2 but Counters 1 and 2 can also run directly from the BRDCLK clock if so directed in CFG3 register
33. counter designed for use with Intel microcomputer systems Digital one shot It is a general purpose multi timing element that can e Programmable rate generator i in th ke bongs as an array of O ports in the system Square wave generator e Binary rate multiplier The 8254 solves one of the most common problems e Compt f in any microcomputer system the generation of ac Ores waveform generator curate time delays under software control Instead of Complex motor controller setting up timing loops in software the programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay Block Diagram After the desired delay the 8254 will interrupt the CPU Software overhead is minimal and variable DATA BUS BUFFER length delays can easily be accommodated This 3 state bi directional 8 bit buffer is used to in terface the 8254 to the system bus see Figure 3 6 26 National Instruments Corporation D 3 AT DIO 32F User Manual AT DIO 32F User Manual Intel Data Sheet INTERNAL BUS Appendix D 8254 E Th Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 8254 A4 and Ap select one of the three counters or the Control Word Register to be read from written into A low on the HD in put tells the 8254 th
34. every LRESET1 this bit must first be cleared and then set again for reintializing handshaking purposes or clear and set DIOBEN of the CFGI Register National Instruments Corporation 4 11 AT DIO 32F User Manual Programming Bit 12 11 10 Name TRANS32 WRITEC WRITEA CNT2SRC CNTISRC DBLDMA AT DIO 32F User Manual Chapter 4 Description continued 32 Bit Transfer Enable When TRANS32 is set the AT DIO 32F is in 32 bit transfer mode This mode uses the Group handshaking lines REQ1 and ACK1 When REQ is received DRDY1 and DRDY2 are both set When data is read or written for both Group 1 and Group 2 the ACKI line is asserted Two read or write operations are required for each 32 bit transfer If TRANS32 is cleared the AT DIO 32F is in regular 16 bit mode Port C Write Read Bit When WRITEC is set Port C is configured for a write operation When WRITEC is cleared Port C is configured for a read operation If Port C is configured for a write operation after every LRESET 2 this bit must first be cleared and then set again for reinitializing handshaking purposes or clear and set DIOCEN of the CFG2 Register Port A Write Read Bit When WRITEA is set Port A is configured for a write operation When WRITEA is cleared Port A is configured for a read operation If Port A is configured for a write operation after every LRESETI this bit must first be cleared and then set again for reinitializin
35. in read mode this signal becomes active when the available data on the data lines has been read The polarity of this signal is configured by the INVACK2 bit in the CFG2 Register Bidirectional data lines for Port C DIOC7 is the MSB DIOCO is the LSB Bidirectional data lines for Port D DIOD7 is the MSB DIODO is the LSB These signals are connected to the ground signal of the PC 2 15 AT DIO 32F User Manual Configuration and Installation Chapter 2 I O Connector Electrical Specifications 1 O Signals Rating Absolute maximum voltage input rating 0 5 to Vcc 0 5 V Vcc 0 5 V to 6 0 V Input Signal Specifications Minimum Maximum Input logic high voltage 2V 5 5 V Input logic low voltage OV 0 8 V Input current at Vec 5 5 V Vin 5 5 V 10 uA Output Signal Specifications Minimum Maximum Output logic high voltage at Ioyt 15 mA 2 44 V 5V Output logic low voltage at Igyt 48 mA 0V 0 5 V Output logic high current 30 mA Output logic low current 70 mA Timing Specifications This section lists the timing specifications for handshaking with the AT DIO 32F The REQ and ACK signals are available on the I O connector and in the following diagrams they are non inverted The digital I O ports are divided into two groups Group 1 and Group 2 The timing specifications for Group 1 and Group 2 handshaking are identical The following signals are used in the timing diagrams later in this chapter Name Type De
36. jumper W2 selects the interrupt enable lines The DIP switch is used to set the base I O address AT Bus Interface The AT DIO 32F is configured at the factory to use a base I O address of hex 240 to use interrupt lines 11 and 12 to use DMA channels 5 and 6 and to disconnect the board from the RTSI clock These settings shown in Table 2 1 are suitable for most systems However if your system has other hardware at this base I O address interrupt level or DMA channel you need to change these settings on the AT DIO 32F as described in the following pages or on the other hardware Record your settings in the AT DIO 32F Hardware and Software Configuration Form in Appendix E Customer Communication National Instruments Corporation 2 1 AT DIO 32F User Manual Configuration and Installation Chapter 2 Table 2 1 AT DIO 32F Factory Set Jumper and Switch Settings Base I O Address Hex 240 factory setting U6l m 9 8 6 5 CE ofA Comm 3947 mca 4 4 Comm 5 The black side indicates the side that is pushed down DMA Channel Bank A Channel 5 W1 Upper right two rows Bank B Channel 6 W1 Lower middle two rows factory setting Interrupt Level Lines 11 and 12 selected W2 Row 4 from left factory setting W2 Row 3 from left RTSI Clock Disconnect board from RTSI W3 STANDBY clock use onboard oscillator BRDCLK OSC factory setting AT DIO 32F User Manual 2 2 National Instruments Corporation Configu
37. jumper selections are shown in Table 2 5 AT DIO 32F User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 5 Configurations for RTSI Bus Clock Selection Disconnect board from RTSI bus clock use local STANDBY BRDCLK OSC oscillator factory setting Receive RTSI bus clock signal STANDBY BRDCLK RTSICLK Drive RTSI bus clock signal with local oscillator BRDCLK OSC BRDCLK RTSICLK Figures 2 9 2 10 and 2 11 show the jumper positions for each of the preceding configurations STANDBY BRDCLK OSC BRDCLK RTSICLK Figure 2 9 Disconnect from RTSI Bus Clock Use Onboard Oscillator Factory Settings STANDBY BRDCLK OSC BRDCLK RTSICLK Figure 2 10 Receive RTSI Bus Clock Signal STANDBY BRDCLK OSC BRDCLK RTSICLK Figure 2 11 Drive RTSI Bus Clock Signal with Onboard Oscillator National Instruments Corporation 2 11 AT DIO 32F User Manual Configuration and Installation Chapter 2 Installation The AT DIO 32F can be installed in any available 16 bit expansion slot AT style in your computer The AT DIO 32F does not work if installed in an 8 bit expansion slot PC style After you have made any necessary changes verified and recorded the switch settings and jumper settings a form is given in Appendix E you are ready to install the AT DIO 32F The following are general installation instructions but consult the user manual or technical reference manual of your
38. next REQ inactive in trailing edge mode ACK inactive to next REQ in leading edge mode with LPULSE set Input data valid before REQ Input data valid after REQ double buffered input Input data valid after ACK single buffered input Old output data invalid after write single buffered output Output data valid before TDELAY single buffered output Old output data invalid after REQ double buffered output Output data valid after REQ double buffered output All timing values are in nanoseconds Cabling 110 110 50 225 125 225 35 Configuration and Installation 320 320 90 175 100 The AT DIO 32F can be interfaced to a wide range of printers plotters test instruments I O racks and modules screw terminal panels and almost any device with a parallel interface The AT DIO 32F digital I O connector is a standard 50 pin header connector The pin assignments are compatible with the DEC DRV11J parallel interface and most standard 32 channel I O module mounting racks such as those manufactured by Opto 22 and Gordos The CB 50 a cable termination accessory is available from National Instruments for use with the AT DIO 32F board This kit includes a 50 conductor flat ribbon cable and a connector block Signal input and output wires can be attached to screw terminals on the connector block and thereby connected to the AT DIO 32F I O connector The CB 50 is useful for initially prototyping an applicati
39. sewem 9 0 tes cassem so ten Gate Setup Tine Atrix m o 9 Ceo ouput Deuy romo L fo oo e ions ouput Deuy tomsas 10 va 00 e wc cik Doty trtoadne 9 s o 9 9 9 5 we Gato Doisy tor Sampang s so s so s 4 e wo OUT Deisy rom moewa 2 eeo 2 Cie eksetptrcemuam ar 5 4 2 0 os NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns tor the 8254 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpw tew may cause errors requiring counter reprogramming 4 Sampled not 100 tested Ta 25 C 5 if CLK present at TWC min then Count equals N 2 CLK pulses TWC max equals Count N 1 CLK pulse TWC min to TWC max count will be either N 1 or N 2 CLK pulses 6 In Modes 1 and 5 if GATE is present when writing a new Count value at TWG min Counter will not be triggered at TWG max Counter will be tri 7 If CLK present when writing a Counter Latch or ReadBack Command at TCL min CLK wili be reflected in count value latched at TCL max CLK will not be reflected in the count value la AT DIO 32F User Manual D 20 National Instruments Corporation Appendix D Intel Data Sheet intel 8254 WAVEFORMS DATA BUS 231164 13 tor a T 231164 14 National Instruments Corporation D 21 AT DIO
40. should be configured for double buffered outputs Ports A and B are double buffered when the DBLBUFA and DBLBUEFB bits in the CFG1 Register are set Ports C and D are double buffered when the DBLBUFC and DBLBUFD bits in the CFG2 Register are set Double buffering means that the port has two buffers a write buffer and an output buffer Writing to the port loads the write buffer Contents of the write buffer are loaded into the output buffer when the corresponding REQ is active The output buffer is connected to the digital I O connector After a double buffered port has been configured for handshaking the first data pattern should be written to the port This write loads the data pattern into the write buffer of the port When a REQ is received the data in the write buffer is transferred to the output buffer of the port which is connected to the digital I O connector The trailing edge of REQ also sets the DRDY bit for the group A polling routine interrupt routine or DMA can be used to detect the DRDY condition and then write the data pattern to the port The double buffered configuration sends the data pattern as soon as a REQ is received In the normal mode of operation the data pattern is not dumped to the digital I O connector until the DRDY bit is detected and the data is written to the port The output of the counters is an active low pulse The handshaking mode for pattern generation must be set to active low REQ trailing edge mode INVR
41. signals input specifications 2 16 A 1 output specifications 2 16 A 1 timing signals 2 16 to 2 18 specifications I O connector electrical specifications 2 16 AT DIO 32F User Manual Intel 8254 programmable interval timer D 19 to D 20 I O connector electrical specifications input signal A 1 output signal A 1 operating environment A 2 physical A 2 power requirements A 2 storage environment A 2 timing specifications 2 16 to 2 18 transfer rates A 1 STAT Register description 4 16 to 4 17 B 3 register map 4 2 STATUS bit 4 35 status byte 4 36 B 5 storage environment specifications A 2 support technical vii switch control patterns RTSI 4 54 switch settings See jumper and switch settings T TCINTENI bit 4 13 TDELAY signal 2 17 technical support xii theory of operation address decoder 3 2 AT DIO 32F block diagram 3 1 bus transceivers 3 2 configuration and status registers 3 2 data latches and drivers 3 2 to 3 3 digital I O connector 3 4 DMA control circuitry 3 10 handshaking circuitry 3 4 to 3 10 leading edge mode 3 7 to 3 8 level mode 3 5 to 3 6 trailing edge mode 3 9 to 3 10 interrupt control circuitry 3 10 onboard counters 3 3 PC I O channel control circuitry 3 2 RTSI bus interface 3 11 timing specifications read and write timing 2 19 to 2 20 signals for 2 16 to 2 18 TIS 2 0 bit 4 5 trailing edge mode See handshaking National Instruments Corporation TRANS32 b
42. then an initial count The Control Words are written into the Control Word Register which is selected when A4 g 11 The Control Word itself specifies which Counter is being programmed ADORESS BUS 16 Av Ae CS COUNTER 0 OUT GATE CLK OUT De07 COUNTER 1 ee cm COUNTER 2 GATE CLK OUT GATE CLK 231164 6 Figure 6 8254 System Interface 6 29 D6 National Instruments Corporation Appendix D National Instruments Corporation intel Intel Data Sheet 8254 Control Word Format Ds D4 D Dz D elev oe e Pe sci sco o o seexcemwo e 3 saec counters 4 9 sect Gourtr2 Read Back Command see Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations o 1 Read Write least significant byte only significant byte E 1 o Read Write most significant byte only Read Write least significant byte then most significant byte BCD O Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades NOTE Don t care bits X should be 0 to insure compatibility with future Intel products mem Figure 7 Control Word Format By contrast initial counts are written into the Coun ters not the Control Word Register The A4 g in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used Write Operations The programming procedure for
43. tutae o gat tdt Eccle 3 10 RESI B s Intetfdbe nia eas ainnean ies con idis eto tee auca se diis taxes irent ase 3 11 Chapter 4 Pr srammiieg 2252522 pta uc tasa ties pi I testes 4 Resister Mp ose esas a pedcs autas bm oh addet eA Lcd 4 1 JELATA SI eS escis iem opi ital isa iedca nasus iunio dia E ET 4 3 Register Description udo egeo eae EEE Eu NTR Eee 4 3 Register Description Format icio endende toe cos nesciat ire eo salse pa RES 4 3 Configuration and Status Register Group eene 4 4 CPG BebPISiCE ue ineo ve ocats Rd E Mi pests ast en d ear 4 5 MESE rcc MR Mo teas ae Managua E sates cee nsec 4 8 CECI RE DISET otiosi soot ta Preis us Berigse erige Pius tuc rp ihe Ean 4 11 CEG4 guid H 4 14 STIS TING S18 i coc hte tide oeste teV tamdiu as vite Vtde iip dede 4 16 CNTINTCLER Re2IStGE ov nusice IC MR Spent teen eS EIE PH REESE 4 18 DNIACIER T RESISIBE uin oit pp eee uod reos Og OP aer endete quce oq 4 19 DMACLR2 Register cie nent eat rarae tone ni rad eti nna E eaa pue 4 20 Digital I O Port Register Group eet rin et nnt Ito rero en e et aeta nnns 4 21 Port A Resistere ec eiiam ated ose Ita ue Me mca pta merde 4 22 Port FR COIS PCT edendi a del eO I aet pdens Oa aa e nnd x n Da 4 23 Port C Resiste 5 neo tecto sous aptos sume tuse tes eer ieu acea Re 4 24 Port D Resister ois seite oq ete an donne ees ott afo Md qaticgak 4 25 RISI Bus Register Grop d odo to ade dais n I od e t NEM 4 26 RESISHET REC I
44. two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte 6 27 D4 National Instruments Corporation Appendix D Intel Data Sheet intel 8254 BUS BUFFER Figure 4 Block Diagram Showing Control Word Register and Counter Functions 231164 5 Figure 5 internal Block Diagram of a Counter 6 28 National Instruments Corporation D 5 AT DIO 32F User Manual AT DIO 32F User Manual Intel Data Sheet intel respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 8254 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRM and CR for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is stored in the CR and later transferred to the CE The Contro Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneous
45. which means that the pulse width of ACK is equivalent to TDELAY If TDELAY is programmed to 0 the pulse width of ACK is 100 nsec When another trailing edge of REQ is received DRDY is set and the AT DIO 32F is ready for another cycle Figure 3 7 shows a read transfer in trailing edge mode LRESET or Power On When REQ asserted When REQ unasserted When REQ After data asserted read Send ACK Start TDELAY After TDELAY Figure 3 7 Trailing Edge Mode Read National Instruments Corporation 3 9 AT DIO 32F User Manual Theory of Operation Chapter 3 Figure 3 8 shows a write transfer in trailing edge mode LRESET or Power On When WRITE bit and DIOXEN bit for group are set REQ unasserted REQ asserted Send ACK Start TDELAY After TDELAY Figure 3 8 Trailing Edge Mode Write Interrupt Control Circuitry The interrupt control circuitry routes any enabled interrupts to the selected interrupt request lines Eleven interrupt request lines are available for use by the AT DIO 32F IRQ3 IRQ4 IRQS IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQ15 Group 1 and Group 2 can each be set to have an interrupt request line With the interrupt requests which are tri state output signals the AT DIO 32F board can share the interrupt lines with other devices Five different interrupts can be generated by the AT DIO 32F DRDY1 set DRDY2 set Group 1 DMA terminal count received Group 2 DMA terminal count recei
46. 0 GND PE 12 20 IN2 GND 30 32 GND ATFD 14 31 OUTI GND 33 34 GND INIT 31 22 OUT2 National Instruments Corporation C 1 AT DIO 32F User Manual Application Notes Appendix C Sending Files to be Printed A selected disk file can be printed with the following program which is written in C The program begins by prompting the user to enter the base address of the board and the name of the file to be printed After verifying that the file exists the program reads characters from the file and writes them to the port A data lines Handshaking is automatic using the group 1 REQ and ACK lines The Centronics specification requires the handshaking acknowledge signal to be a minimum of 500 nsec This is accomplished by setting the Data Settling Delay bits in the CFGI Register A 500 nsec delay is sufficient for the printer to recognize communication as Send a file from the PC to a Centronics printer via the National Instruments AT DIO 32F include stdio h define CFGloffset 0x00 define CFG2offset 0x02 define CFG3offset 0x04 define CFG4offset 0x14 define STAToffset 0x00 define PORTAoffset 0x06 int base address base address of the AT DIO 32F board cfgl address of CFG1 register cfg2 address of CFG2 register cfg3 address of CFG3 register cfg4 address of CFG4 register tstat address of STAT register porta address of PORTA register FILE fp FILE fopen
47. 2 Write to the RTSI Strobe Register to load the pattern into the RTSI switch Write 0 to the RTSI Strobe Register base address 12 hex At startup the RTSI bus switch is automatically initialized National Instruments Corporation 4 55 AT DIO 32F User Manual Appendix A Specifications This appendix lists the specifications for the AT DIO 32F These specifications are typical at 25 C unless otherwise noted Digital I O Number of channels uec ti rettet ertet 32 I O Compatibility eese ener TTL Digital Logic levels iiiar ttt meri Input low voltage Input high voltage Input high current Vin 5 V Output low voltage lout 48 mA Output high voltage lout 15 mA Transfer rate 1 word 16 bits Absolute max Programmed I O essen 450 kwords s TOMA iode ER berti ire arte iore 330 kwords s Handshaking 5 da ton tote eene reete tees 2 wire Poweron Stat xor eter res Configured as inputs Data transfers cetero eere sven dateovsies DMA interrupts programmed I O Transfer rate depends on the computer and software These tests were made using Assembly language programs running on a 16 MHz IBM PC AT compatible RTSI Trigger mes corr tege retenta de Peta e sus NC Es 7 Power Requirement X5 VDC CE1096 3i atit ete de S 1 05 A typ Physical Dimensions epe tege ue 34 0 by 12 7 cm 13 4 by 5 0 in V O connector ttt tte tie eret 50 pin male Nation
48. 3 35 PA4 42 PAS 36 PAG 4l PAT 47 PBO 50 PBI 44 PB2 48 PB3 49 PB4 43 PB5 46 PB6 45 PBT 27 ACKI 33 REQI 28 GND 30 GND 32 GND 34 GND The following program is divided into two functional parts one for sending files from the AT DIO 32F and the other for receiving files Both are structured similarly and check for the EOF marker which marks the end of transmission The handshaking between the AT DIO 32F boards is fully automatic and requires no software toggling of lines For 16 bit communications the program compresses two 8 bit characters into one 16 bit word using the functions getw and putw from the standard unix library The function getw is modified to the new function getwd to recognize and return both 8 bit and 16 bit EOF markers Both getwd and putw are included at the end of the program and either function can be expanded to handle 32 bit words Notice that Port A and Port B are declared 16 bit type int This program allows the AT DIO 32F to send and receive 16 bit data to and from an AT DIO 32F in another PC x include lt stdio h gt National Instruments Corporation C 5 AT DIO 32F User Manual Application Notes fin fin fin fin fin fin fin 2aaaaaga c nsigned int nsigned int c 0x00 0x02 0x04 0x14 0x00 0x06 0x08 base addr CFG1 CFG2 CFG3 CFG4 STAT1 PORTA PORTC FILE char int main fs print
49. 3 Register configures Ports A and B as read ports Similarly writing hex 4800 to the CFG3 Register configures Ports C and D as write ports and clearing bit 11 and bit 14 of the CFG3 Register configures Ports C and D as read ports Each port can be assigned a direction independently Mode 1 Programming Each group of ports has its own set of handshaking lines Group 1 Ports A and B handshaking lines are REQI and ACK1 Group 2 Ports C and D handshaking lines are REQ2 and ACK2 The individual ports in a group must be enabled for handshaking within each group by setting DIOAEN DIOBEN DIOCEN and DIODEN For 8 bit transfers only one port should be enabled for handshaking in a group For 16 bit transfers both ports in a group should be enabled The direction of handshaking for each group is determined by the corresponding WRITE bit If data is to be driven by the group the corresponding WRITE bit must be set If a write port is read the result is the data currently driven on that port If data is to be received by the group the corresponding WRITE bit must be cleared Any ports not enabled for handshaking can be used for Mode 0 operations that is for reading additional status data or for driving additional control lines For example if Port B is enabled for handshaking and is configured as a read port Port A can be used to read or write data lines in Mode 0 operations For example to set up Group 1 as a 16 bit handshaking write port wit
50. 4 Register Base Address Offset 14 hex 16 bit write only 15 14 13 12 11 10 9 8 9 eS ee Ee fi 6 5 4 3 2 1 0 0 0 0 0 IPULSE LPULSE DBLBUFD REVC AT DIO 32F User Manual B 2 National Instruments Corporation Appendix B I O Connector and Register Descriptions STAT Register Base Address Offset 00 hex 16 bit read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REQ ACKI IO O X DRDY2 REQ ACK CNTINTCLR Register Base Address Offset OA hex 16 bit write only Bit map not applicable no bits used DMACLRI Register Base Address Offset 2 0C hex 16 bit write only Bit map not applicable no bits used DMACLR2 Register Base Address Offset 2 OE hex 16 bit write only Bit map not applicable no bits used Port A Register Base Address Offset 06 hex 8 bit or 16 bit read and write 7 6 5 4 3 2 1 0 DIOA7 DIOA6 DIOAS DIOA4 DIOA3 DIOA2 DIOA1 DIOAO Port B Register Base Address Offset 07 hex 8 bit read and write 7 6 5 4 3 2 1 0 National Instruments Corporation B 3 AT DIO 32F User Manual I O Connector and Register Descriptions Appendix B Port C Register Base Address Offset 08 hex 8 bit or 16 bit read and write 7 6 5 4 3 2 1 0 Port D Register Base Address Offset 09 hex 8 bit read and write 7 6 3 4 3 2 1 0 RTSISHFT Register Base Address Offset 10 hex 8 bit write only 7 6 5 4 3 2 1 0 RTSISTRB Register Base Address Offset 12
51. AT DIO 32F User Manual High Speed 32 Bit Parallel Digital I O Interface for the PC April 1995 Edition Part Number 320147 01 Copyright 1989 1995 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 Limited Warranty The AT DIO 32F is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other document
52. CFG2 Register is set data is latched into Port C on the active level or active edge of REQI In level mode data is latched during the active level of REQ2 until REQ2 is inactive In pulse mode data is latched on the active edge of REQ2 until the data is read from the port Either 8 bit or 16 bit transfers can be performed on Port C 16 Bit Write or Read from Port C Port D Port C 71615 4 3 2 1 017 6 15 4 3 2 1 0 8 Bit Write or Read from Port C Port C 7161514 3 124140 AT DIO 32F User Manual 4 24 National Instruments Corporation Chapter 4 Programming Port D Register The Port D Register contains eight bits that connect to the digital I O connector and can either be read from or written to Address Base address 09 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 When Port D is configured as a write port writing data to this register latches the data into Port D and sends the data out on Port D Reading Port D when it is in write mode returns the value that is currently driven on the port If the DBLBUFD bit in the CFG4 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ2 level or pulse is received During an active REQ2 level or pulse the data is dumped to the I O connector When Port D is configured as a read port reading Port D returns the current data at Port D If the DBLBUPFD bit in t
53. Can t open the file s filename return 0 no file access else return 1 file exists go ahead setup the AT DIO 32F board Setup DIO initialize the board outpw cfgl 0x0000 outpw cfg2 0x0000 outpw cfg3 0x0000 outpw cfg4 0x0001 outpw cfg2 0x001 OUT2 INIT high outpw cfgl 0x2B44 reset porta handshaking outpw cfgl 0x2A44 porta level invert ACK1 and REQ1 delay 500ns outpw cfg3 0x0400 porta write check printer is ready Printer_Rdy int err 0 National Instruments Corporation C 3 AT DIO 32F User Manual Application Notes Appendix C if Read_Stat amp 0x20 get IN2 paper error bit printf nPrinter out of paper printf nStat x Read_Stat err 1 while Read Stat amp 0x0800 wait until IN1 BUSY is not set return err read the stat register Read Stat return inpw tstat send a character to the printer by writing to porta Print_char ch char ch int i 0 err err Printer_Rdy check for paper error or BUSY if err printf nCan t get printer ready e xit 1 while Read Stat amp 0x0100 amp amp i lt 20000 wait for DRDY1 bit set itt if i 20000 printf nCan t get DRDY1 set printf nStat x Read_Stat exit 1
54. EDGE bits are cleared Figures 4 1 and 4 2 show active high level ACK and REQ signals National Instruments Corporation 4 39 AT DIO 32F User Manual Programming Chapter 4 GO REQ DRDY WR TDELAY ACK Figure 4 1 Level Mode Write Handshake Timing RD TDELAY ACK Figure 4 2 Level Mode Read Handshake Timing Leading Edge Mode In leading edge mode REQ and ACK are viewed as pulses that are active on the leading edge of the pulse A handshaking group is in leading edge mode when its PULSE bit is set and its EDGE bit is cleared Figures 4 3 4 4 and 4 5 show the timing diagrams for leading edge mode For detailed timing information refer to Chapter 2 Configuration and Installation AT DIO 32F User Manual 4 40 National Instruments Corporation Chapter 4 Programming WR TDELAY ACK Figure 4 3 Leading Edge Mode Write Handshake Timing LPULSEx cleared RD TDELAY ACK Figure 4 4 Leading Edge Mode Read Handshake Timing LPULSEx cleared RD WR TDELAY ACK with LPULSE set Figure 4 5 Leading Edge Mode Read Write ACK Pulse Width with LPULSEx of CFG4 Set National Instruments Corporation 4 4 AT DIO 32F User Manual Programming Chapter 4 Trailing Edge Mode In trailing edge mode REQ and ACK are treated as pulses that are active on the trailing edge of the pulse A handshaking group is in trailing edge mode when its PULSE and EDGE bits are set Figures 4 6 and 4 7 show t
55. EQ PULSE and EDGE are set Therefore the latched data can be driven to the output lines during the active REQ pulse and new patterns can be written and latched after the active REQ duration Counter Output REQ DRDY is set by this 1 Clock trailing edge and a new pattern is written to the buffer after DRDY is set Pattern is dumped to I O connector Figure 4 8 Pattern Generation The programming steps to set up Counter for pattern generation are as follows 1 Set up Counter 1 for rate generation by writing hex 14 to the CNTRCMD Register for an 8 bit count or by writing hex 34 to the CNTRCMD Register for a 16 bit count 2 Write the count to the CNTR1 Register see Table 4 5 If the count is a 16 bit value write the least significant byte first then the most significant 3 Write hex 10 to the CFG3 Register to enable Counter for pattern generation set the CNTIHSEN bit 4 Set up Group to select double buffered trailing pulse mode and to clear handshaking write hex 0378 to the CFG1 Register for an 8 bit Port A or write hex 07F8 to the CFG1 Register for a 16 bit Port A National Instruments Corporation 4 51 AT DIO 32F User Manual Programming Chapter 4 5 Write hex 0278 for 8 bit or 0678 for 16 bit to the CFG1 Register to finish clearing handshaking 6 Write hex A410 to the CFG3 Register to enable Counter 1 for pattern generation and to set Group 1 in write mode set the WRITEA and WRITEB bits
56. ERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero D 11 Intel Data Sheet 8254 OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK puise thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycies in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one Shot pulse the current one shot is not affected un less the counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typically used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N
57. F User Manual About This Manual Conventions Used in This Manual The following conventions are used throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept NI DAQ NI DAQ is used throughout this manual to refer to the NI DAQ software for DOS Windows LabWindows unless otherwise noted PC PC refers to the IBM PC AT and compatible computers Related Documentation The following manual contains information that you may find helpful as you read this manual IBM Personal Computer AT Technical Reference manual You may also want to consult the following manual if you plan to program the Intel 8254 2 Counter Timer used on the AT DIO 32F e Intel 8254 System Timing Controller technical manual Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix E Customer Communication at the end of this manual AT DIO 32F User Manual xii National Instruments Corporation Chapter 1 Introduction This chapter describes the AT DIO 32F lists the contents of your AT DIO 32F kit and explains how to unpack the AT DIO 32F kit The AT DIO 32F is a high speed 32 bit parallel digita
58. F User Manual 3 6 National Instruments Corporation Chapter 3 Theory of Operation Leading Edge Mode In leading edge mode the handshaking lines REQ and ACK are viewed as pulses that are active on the leading edge of the pulse Once the data is read or written TDELAY begins After TDELAY ACK is sent to the digital I O connector When another leading edge of REQ is received DRDY is set and the AT DIO 32F is ready for another cycle Figure 3 5 shows a read transfer in leading edge mode LRESET or Power On When REQ asserted When REQ asserted When REQ unasserted After data read After TDELAY Figure 3 5 Leading Edge Mode Read Note If LPULSE is set ACK starts when TDELAY starts National Instruments Corporation 3 7 AT DIO 32F User Manual Theory of Operation Chapter 3 Figure 3 6 shows a write transfer in leading edge mode LRESET or Power on When WRITE bit and DIOXxEN bit for the group are set When REQ asserted When REQ unasserted written After TDELAY Figure 3 6 Leading Edge Mode Write Note If LPULSE is set ACK starts when TDELAY starts AT DIO 32F User Manual 3 6 National Instruments Corporation Chapter 3 Theory of Operation Trailing Edge Mode In trailing edge mode REQ and ACK are treated as pulses that are active on the trailing edge of the pulse Once the data is read or written ACK is asserted At this time TDELAY begins After TDELAY ACK is cleared
59. IO 32F User Manual 4 30 National Instruments Corporation Chapter 4 Programming CNTR2 Register REQ2 Generator The CNTR2 Register contains eight bits that are used to load a value into Counter 2 or to read back the value of Counter 2 The CNTR2 Register can be used as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 1A hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTR2B7 CNTR2B6 CNTR2B5 CNTR2BA4 CNTR2B3 CNTR2B2 CNTR2BI CNTR2BO Bit Name Description 7 0 CNTR2B 7 0 Counter 2 Load Read Bits Writing a data value to these bits loads the starting value into Counter 2 Reading these bits returns the current count of Counter 2 or latched data for Counter 2 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 2 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the least significant byte and the second read returns the most significant byte If status and count information are both latched the first read to this register returns the status
60. Instruments Corporation Appendix D Intel Data Sheet inte 8254 Table 1 Pin Description DE D Vo DATA Bi directional three state data bus lines connected to system data bus cko 9 t CLOCKO Clock input of Counter 0 outro 10 O OUTPUTO Output of Counter 0 GATEo t1 GATE 0 Gate input of Counter 0 GND 12 GROUND Power supply connection Voc 24 POWER 5V power supply connection WR 23 WRITECONTROL This inputis low during CPU write operations READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 8254 to respond to RD and WR signals RD and WH are ignored otherwise ADDRESS Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus 18 1 CLOCK 2 Clock input of Counter 2 OUT2 17 O OUT 2 Output of Counter 2 GaTE2 16 i GATE 2 Gate input of Counter 2 cki 15 CLOCK t Clock input of Counter 1 GATE1 14 GATE 1 Gate input of Counter 1 ouri 13 O j OUT 4 Output of Counter 1 Some of the other counter timer functions common FUNCTIONAL DESCRIPTION to microcomputers which can be implemented with the 8254 are General Real time clock The 8254 i a programmable interval timer counter Event
61. MA transfers switch to the DMA channel for Group 2 When a DMA terminal count is received for Group 2 the DMA transfers switch back to the Group 1 DMA channel While one DMA channel is acquiring data the other channel can service the acquired data The DMACH bit in the STAT Register indicates which group s DMA channel is currently in use If DMACH is cleared the DMA channel for Group 1 is currently in use if DMACH is set the DMA channel for Group 2 is currently in use If the DMA controller is programmed for auto reinitialize mode the two DMA channels are continuously served in turn 32 Bit Transfers The four digital I O ports are divided into two 16 bit groups Group 1 and Group 2 Either 8 bit or 16 bit operations can be performed on these groups When the TRANS32 bit is set in the CFG3 Register 32 bit operations can also be performed For 32 bit transfer mode Groups 1 and 2 must be enabled for handshaking DIOAEN DIOBEN DIOCEN and DIODEN must be set The two groups should be programmed for identical configurations with the same PULSE EDGE LPULSE and TS TDELA Y values Requests should not begin on the REQI line until both groups are fully configured Configured in this way the AT DIO 32F can transfer data to or from all 32 of its data lines simultaneously using only the ACK1 and REQI handshaking lines ACK2 and REQ can be ignored When a REQI is received both DRDY1 and DRDY2 are set When data has been written or read for both G
62. O Srenals dates osa see sot deve a tere t eut testa sce A ea teen ates 2 16 Input Signal Speciticaions ssn titel ere aie een 2 16 Output Signal Specifications ceo odes hn e bove hai ddl cecal 2 16 Timme SPE Ci CAO x cT E 2 16 AT DIO 32F Read and Write Timing eese 2 18 Cabling oot ose reo aires caufa deis esa AO Aen ee 2 19 Chapter 3 Theory of Operationen onto trames Adie Durie nau nett aa tabnesten te et 3 1 PROCESS IG COREL cs tase seizes eval isis as s dai es sees sacl co de eee 3 2 PSUS PATS CEL VSI S esatto et iSo tun gd itbo ea da tanlets satelite Sal ae aloha ad NL 3 2 PC I O Channel Control CI elftEy user oae CO I BD IRR RI IEEE METER URSUS 3 2 Configuration and Status Registers odo Ras onae ves conen Quies ede ose Meese eb desess one 3 2 Data Latches and Or Vers xseccs ces hsssnvesds Git atq died s Da te dean pU QU UNE 3 2 Onboard Counters aen becadetob At A odo eps dota tL LC ca o eMe 3 3 Digital VO Connector toc esp Io a taxa secat aloe Leap era cn 3 4 National Instruments Corporation v AT DIO 32F User Manual Contents Handshakinig Circuitry s siv gsacieeavetsisspeateasuaeeeaaseseauaascagaceasesecueasvesnase EE Eaa S Eain 3 4 Level Modene a tint tae bcp o Do A ARE 3 5 Leading Edge Mode 5 ere nen OI RU SUR a i EINE e E 3 7 Trailing Edse Modesa rere i EE teen EE TE N E E ERRE 3 9 Interrupt Control C Irc Use ofer Gus qe EA Ste aE E ete E mene 3 10 INL Control Circuitry erea ck gah Sad ox Stat ogee
63. RR eet oce in Exe eode xii Related DOCUMEMLAT OM cnesta xii Customer Communication 2 erret tee tr ieina A e Ue Ehe eR po ea NE Syn Pet aUa De Pe Pee ERN e agde xii Chapter 1 Introduction s es Dn ea iu iod ee 1 1 What Your Kit Should Contam s e oi e ease peat ose nue eA esie uide e m eaten 1 2 Optional SoftWare sie etre PO EYE ESOS UR UR SR eS EEEE E QNT UR Pos Una UI paa ee HERE EA 1 3 Optional EQUIDIDOBL us corta iti Ro Rp itii e toit tts plus tut nm tuc tees e 1 4 Wrap ett 9 a 1 5 Chapter 2 Configuration and Installation sese 2 1 Board OM MOU ALTOS ossi IS nh fonder penus eiua o AES c oL desse fae 2 1 AI Bis Ier FACS 52 055 ded tos udp D euet E vu a a e cuu quse dus 2 1 Base V O Address Selections dccerni e th osea da ote a oe ea Ee x Sr NE 2 4 DMA Channel Selection ooa ehe teas etus a antes itus e ondas Adda UN 2 7 Interrupt SEE CHOI x sena o n odds esta asm pim E E pr O deos 2 9 RTSI Bus Clock Selection ciet tero de i 2 10 ROIS CAN AION c oa 2 12 Signal Connections soins ipene Etana dye EESE EEA RT as EEn 2 13 I O Connector Pin Description ssssssesesesesessseesseesseessereseesseeessressersseresseesssees 2 13 Signal Connection Descriptions s sssssseesseessessereseeeessttssresseesseeesseeessresseesse 2 14 V O Connector Electrical Specifications uec pes toca terdues Brev iocs ena ee Ephes eiecit uod Pow cotd 2 16 V
64. SG CT iicet ouo A lieb E setae ceased oak 4 27 REISISTEB REZISULE seront HO Hr IR Beiliae tr a e Lan 4 28 Counter Register GrOUp uicese cert Ie INEST UU ESRB SER TN ke UN BR e AER TR NS Fe eae GS 4 29 CNTRI Register REQ Generator eee ren e eterne nna 4 30 CNTR2 Register REQ2 Generator eseeeeeeereeenenn 4 31 CNTR3 Register Timebase Generator eene 4 32 CNTRCMD RGBISIGE neciesa ni S e Pune e e aba e Pee aee eue 4 33 Programming Considerations c oe eese ngo eese ucro cie MOREM idr o qoe nut Der Tei RU aepo Ups 4 37 Initializing the AT DIO 32F Board eene 4 37 M de 0 ProstaMmmin T so e e MM Nd 4 38 M de 1 Programming sie en e tus E ecd ine E Ne 4 38 p adme Edge IM OG sss thas a E r o d te vacnasenels 4 4 raring Edse MOUG 4 uso yo otn ursa et deter 4 42 IDatacsculine Delay ideo Ren viste Ra dtm Mo du alata 4 43 Programmed DO Transfers dace eiae aT tee bd ee REUS RUE de 4 43 Input Data Lath M pD iiaa 4 44 Interr pt Handling osse oia teet as qi pesos a ui qune tt ideo pu deus 4 44 DMA Transfers iine Lc ie eb E LU eerste 4 48 S45 Bit TraniSfete ee ond tends ceidt qo dite Quas tal tam assetec utei aad 4 48 Pattern Generation Using Onboard Counters eese 4 49 AT DIO 32F User Manual vi National Instruments Corporation Contents Pattern Generation Using an External Signal eese 4 53 Programming the RTSI Bus
65. Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Setting Base I O Address Base I O Address A9 A8 A7 A6 A5 hex Space Used hex 000 O1F 020 03F 040 OSF 060 07F 080 09F OAO OBF 0CO ODF OEO OFF 100 11F 120 13F 140 15F 160 17F 180 19F 1A0 IBF 1C0 IDF 1E0 1FF 200 21F 220 23F 240 25F 260 27F 280 29F 2A0 2BF 2CO 2DF 2E0 2FF 300 3IF 320 33F 340 35F 360 37F 380 39F 3A0 3BF 3C0 3DF 3E0 3FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EERE Rr OOO OOOO OF Re Re Re ee RP Re rR OOCOCCOCUCCCOCOCUCcCCOCCOC mer rr OOO OrR RP RFR OOO OCOrR RR Rr OO OOrR RRR OCC Oo er OOrFrFOOrRrFOCOOrRFrFOOFRFOCOOrRFrOCOOrFRFrFOCOOFrF CO RPOoOrOrFOrOr Or Or Or OFrROFrF OF Or OrOF OF OCOF OC Note Base I O address values hex 000 through OFF are reserved for system use Base I O address values hex 100 through 3FF are available on the I O channel DMA Channel Selection The DMA channel used by the AT DIO 32F is selected by jumpers on W1 see Figure 2 1 The AT DIO 32F is set at the factory to use DMA Channels 5 and 6 These are the default DMA channels used by the AT DIO 32F software handler Verify that these DMA channels are not also used by equipment already installed in your computer If any device uses DMA Channel 5 and or Channel 6 change the DMA channel used by either the AT DIO 32F
66. TIEN bit in the CFG3 Register enables Counter 1 for counting the CNT2EN bit in the CFG3 Register enables Counter 2 for counting and both counters can be enabled or disabled by external signals INI and IN2 respectively When INI and IN2 are used to control the counters CNTIEN and CNT2EN must be set so that an active high level signal on INI can enable Counter 1 and an active high level signal on IN2 can enable Counter 2 Counters 1 and 2 can be used for pattern generation Counter 1 implements pattern generation for Group 1 and Counter 2 implements pattern generation for Group 2 When the CNTIHSEN bit in the CFG3 Register is set the output of Counter 1 controls the REQI line When the CNT2HSEN bit in the CFG3 Register is set the output of Counter 2 controls the REQ2 line If a counter is used for pattern generation the corresponding REQ line on the digital I O connector should be disconnected or in a high impedance state Table 4 4 Counter 3 Programmable Frequency Output Data Written to CNTR3 hex Counter 3 Output Frequency The CNTISRC and CNT2SRC bits in the CFG3 Register select the counting source for Counter and Counter 2 respectively If the CNTISRC bit is cleared the counting source for Counter 1 National Instruments Corporation 4 49 AT DIO 32F User Manual Programming Chapter 4 is a 10 MBz square wave If the CNTISRC bit is set the counting source for Counter 1 is the output of Counter 3 The same applies for Counter 2
67. Uo sa AI Eom eee aGa ra eue nedsectenoeses 4 2 CPGI Data Settling Time Settlps eine tiet tiges tocar bet ee IR ERE Eee N 4 43 Interrupt Condition and Status sessssseseeeeeeeeee nennen 4 45 Counter 3 Programmable Frequency Output seen 4 49 Counters 1 and 2 Programmable Frequency Output Source 10 MHZ 4 50 RTSI Switch Signal COnnDector edi bre eine cn saevi wena 4 53 Cable Specification for Connections to 8 16 or 24 channel I O Module Racks C 10 National Instruments Corporation ix AT DIO 32F User Manual About This Manual Introduction to the AT DIO 32F The AT DIO 32F is a high speed 32 bit parallel digital I O interface The AT DIO 32F is a member of the National Instruments AT Series of PC AT I O channel expansion boards for the IBM PC AT and compatible computers These boards are designed for high performance data acquisition and control for applications in laboratory testing production testing and industrial process monitoring and control This manual describes the installation basic programming considerations and theory of operation for the AT DIO 32F Example programs are provided in the C programming language Organization of This Manual The manual is divided into the following chapters and appendixes e Chapter 1 Introduction describes the AT DIO 32F lists the contents of your AT DIO 32F kit and explains how to unpack the AT DIO 32F kit
68. al Instruments Corporation A I AT DIO 32F User Manual Specifications Appendix A Environment Operating temperature essere 0 to 50 C Storage temperature sssssssseeeeenere rennen 40 to 100 C Relative humidity 2n ettet tht 596 to 9096 noncondensing Noise Emission FCC Class A verified only with shielded ribbon cable AT DIO 32F User Manual A 2 National Instruments Corporation Appendix B I O Connector and Register Descriptions This appendix contains a description of the AT DIO 32F I O connector and references to the registers of the AT DIO 32F I O Connector Figure B 1 shows the pinout and signal names for the AT DIO 32F 50 pin I O connector Figure B 1 AT DIO 32F I O Connector Detailed signal specifications are included in Chapter 2 Configuration and Installation National Instruments Corporation B 1 AT DIO 32F User Manual I O Connector and Register Descriptions Appendix B AT DIO 32F Register Descriptions A quick reference for the AT DIO 32F appears on the following pages CFG1 Register Base Address Offset 2 00 hex 16 bit write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG2 Register Base Address Offset 02 hex 16 bit write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG3 Register Base Address Offset 04 hex 16 bit write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBLDMA CNTINTEN CNT2HSEN CNTIHSEN CNT2EN CNTIEN TCINTEN2 TCINTENI CFG
69. ame Description 7 6 CNTRSEL lt 1 0 gt Counter Select Bits Both bits must be one for the Read Back command to be used 5 COUNT Read Back Count Command If COUNT is cleared the current count in each of the selected counters is latched The next read from the selected counter returns the latched data 4 STATUS Read Back Status Command If STATUS is cleared the current status in each of the selected counters is latched The next read from the selected counter returns the latched data 3 1 CNTR lt 3 1 gt Counter Select Bits for Read Back Command These bits select the counters for the Read Back command that is if CNTR3 and CNTRI are set the Read Back command latches data for Counter 3 and Counter 1 0 0 Zero Bit This bit must be zero for proper operation of the AT DIO 32F National Instruments Corporation 4 35 AT DIO 32F User Manual Programming Chapter 4 Status Byte If the STATUS bit is zero in the Read Back command status information for the selected counters is latched The status byte format is as follows Er Oe ee et e e A Bit Name Description 7 OUT Counter Output The OUT bit reflects the current status of the counter output 6 NULL Last Count Written Status If NULL is zero the last count written to the selected counter has been loaded into the counter If NULL is set the last count written to the counter has not been loaded 5 4 RW lt 1 0 gt RWSEL and RWSELO Status The RW1 and RWO bits refle
70. and place them on the new pins IRQ 1514 12111097 6 54 3 INTRI INTR2 Figure 2 6 Interrupt Jumper Settings IRQ11 and IRQ12 Factory Settings National Instruments Corporation 2 9 AT DIO 32F User Manual Configuration and Installation Chapter 2 If you do not want to use interrupts place the jumper on W2 in the positions shown in Figure 2 7 This setting disables the AT DIO 32F from asserting any interrupt lines on the PC I O channel IRQ 15141211109 765 4 3 Figure 2 7 Interrupt Jumper Settings for Disabling Interrupts Figure 2 8 shows the Group 2 interrupts disabled and interrupt line 5 is selected for Group 1 IRQ 15141211109 765 4 3 Figure 2 8 Interrupt Jumper Setting IRQ5 Only RTSI Bus Clock Selection When multiple AT Series boards are connected via the RTSI bus you may want to have all the boards use the same 10 MHz clock This arrangement is useful for applications that require counter timer synchronization between boards Each AT Series board with a RTSI bus interface has an onboard oscillator Thus one board can drive the RTSI bus clock signal and the other boards can receive this signal or disconnect from it The configuration for jumper W3 determines whether a board drives the onboard 10 MHz clock onto the RTSI bus receives the RTSI bus clock or disconnects from the RTSI bus clock This clock source whether a local or RTSI signal is then used as the onboard counter frequency source The
71. ast significant byte and the second read returns the most significant byte If status and count information are both latched the first read to this register returns the status byte and the next one read for 8 bit mode or two reads for 16 bit mode return the count bytes regardless of the order in which the information was latched AT DIO 32F User Manual 4 32 National Instruments Corporation Chapter 4 Programming CNTRCMD Register The CNTRCMD Register contains eight bits that determine the counter selection counter size counting format and operation mode Address Base address 1E hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTRSELI CNTRSELO RWSELI RWSELO MODESEL2 MODESEL1 MODESELO BCDSEL Bit Name Description 7 6 CNTRSEL lt 1 0 gt Counter Select Bits These bits select the counter on which the command operates CNTRSELI CNTRSELO Select Counter 1 Select Counter 2 Select Counter 3 Read Back command 5 4 RWSEL lt 1 0 gt Read Write Select Bits These bits select data written to or read from a counter or these bits send a Counter Latch command 0 0 Counter Latch command 0 1 Read and write least significant byte only 1 0 Read and write most significant byte only 1 1 Read and write least significant byte then most significant byte National Instruments Corporation 4 33 AT DIO 32F User Manual Programming Chapter 4 Bit Name Description continued
72. at the CPU is reading one of the counters A low on the WR input tells the 8254 that the CPU is writing either a Contro Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored uniess the 8254 has been selected by holding CS low CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when As Ao 11 If the CPU then does a write operation to the 8254 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates The status register shown in Figure 5 when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment it is a 16 bit presettable synchronous down counter OL and OL are
73. ation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE
74. ations with the PC byte 8 bit and word 16 bit Table 4 1 shows the size of each AT DIO 32F register For example reading the STAT Register requires a 16 bit word read operation at the selected address whereas writing to the RTSISHFT Register requires an 8 bit byte write operation at the selected address Addresses selected as 8 bit locations can also be accessed with a 16 bit operation the upper byte in this case should be thought of as eight don t care bits Register Description Table 4 1 divides the AT DIO 32F registers into four different register groups A bit description of each of the registers making up these groups is included later in this chapter The Configuration and Status Register Group controls the overall operation of the AT DIO 32F hardware The configuration registers are used to program the digital I O handshaking modes and to enable DMA or interrupt requests The status registers reflect the state of the digital I O handshaking interrupt requests and DMA requests The registers in the Digital I O Port Group access the four 8 bit digital I O ports The Counter Register Group selects the counting mode and initial count of the three counters The RTSI Bus Register Group configures the RTSI bus switch Register Description Format The remainder of this section discusses each of the AT DIO 32F registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each re
75. byte count is writ ten the following happens 1 Writing the first byte has no effect on Soi 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written 231164 11 Figure 19 Mode 4 D 16 National Instruments Corporation Appendix D National Instruments Corporation intel Intel Data Sheet 8254 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and Counting
76. cription 4 8 to 4 10 register map 4 2 CFG3 Register description 4 11 to 4 13 B 2 register map 4 2 CFG4 Register description 4 14 to 4 15 B 2 register map 4 2 channel control circuitry 3 2 CNTIEN bit 4 13 CNTIHSEN bit 4 13 AT DIO 32F User Manual Index CNTISRC bit 4 12 CNT2EN bit 4 13 CNT2HSEN bit 4 13 CNT2SRC bit 4 12 CNTINT bit 4 16 CNTINTCLR Register description 4 18 B 3 register map 4 2 CNTINTEN bit 4 12 CNTINTEN bit 4 13 CNTR lt 3 0 gt bit 4 35 CNTRIB lt 7 0 gt bit 4 30 CNTR2B lt 7 0 gt bit 4 31 CNTR3B lt 7 0 gt bit 4 32 CNTRI Register REQI generator description 4 30 B 4 register map 4 2 CNTR2 Register REQ2 generator description 4 31 B 4 register map 4 2 CNTR3 Register timebase generator description 4 32 B 5 register map 4 2 CNTRCMD Register description 4 33 to 4 36 B 5 register map 4 2 CNTRSEL lt 1 0 gt bit 4 33 4 35 compatibility with I O applications and devices 1 1 to 1 2 configuration base I O address selection 2 4 to 2 7 AT bus interface 2 1 DMA channel selection 2 7 to 2 9 interrupt selection 2 9 to 2 10 RTSI bus clock selection 2 10 to 2 11 Configuration and Status Register Group CFGI Register 4 5 to 4 7 B 2 CFG2 Register 4 8 to 4 10 B 2 CFG3 Register 4 11 to 4 13 B 2 CFG4 Register 4 14 to 4 15 B 2 CNTINTCLR Register 4 18 B 3 DMACLRI Register 4 19 DMACLR2 Register 4 20 overview 4 4 register map 4 2 STAT R
77. ct the status of the RWSEL1 and RWSELO bits of the selected counter 3 1 MODE lt 2 0 gt MODE2 MODEI and MODEO Status The MODE2 MODEI and MODEO bits reflect the state of the MODESEL2 MODESEL1 and MODESELO bits of the selected counter 0 BCD Binary Coded Decimal Select BCDSEL Status The BCD bit reflects the status of the BCDSEL bit of the selected counter Refer to Appendix D ntel Data Sheet for more information on programming the counters AT DIO 32F User Manual 4 56 National Instruments Corporation Chapter 4 Programming Programming Considerations The AT DIO 32F has four 8 bit digital I O ports These ports are organized into two groups Group 1 contains Ports A and B and Group 2 contains Ports C and D The AT DIO 32F can also operate in two modes Mode 0 and Mode 1 Mode 0 is basic I O where each port can be configured as a read or write port Mode 1 is strobed I O Two handshaking lines are used to synchronize the sending and receiving of data for each port Mode 1 can also act as a pattern generator by using the onboard counters or by using a signal routed across the RTSI bus interface from another AT Series board The following paragraphs discuss Mode 0 Mode 1 and pattern generation Initializing the AT DIO 32F Board The AT DIO 32F hardware must be initialized in order for the AT DIO 32F circuitry to operate properly To initialize the AT DIO 32F hardware complete the following steps 1 Write hex 0100 to t
78. d are trademarks or trade names of their respective companies Warning Regarding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual 5 np RUD ERRORI ln ep biam xi Introduction to the AT DIQ 32E ise e eee seen eaten ea rane enn oe saa ele Ene Te nne a deb nC Tena eu odas xi Orzanizauomot This Ma n al uou iier ben ett dede a plein tud do Qul viae seus qut dues xi Conventions Used in This Manual 4 enne Ires thee E
79. d for reading writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 HEX is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to read write LSB only the most significant byte cannot be read N stands for an undefined count Vertical fines show transitions between count values Figure 15 Mode 0 AT DIO 32F User Manual D 12 National Instruments Corporation Appendix D National Instruments Corporation Intel Data Sheet 8254 linn n n 2121202 202 02 CW 12 LSB z2 in In In ndn diiil s miniis Figure 16 Mode 1 initial count has expired OUT goes low for the re mainder of the count Mode 3 is periodic the se quence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting if GATE goes low while OUT is low OUT set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter D 13 After writing a Control Word and initial count the Counter will be loaded on the next CLK puise
80. d or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Fe RS WR x m Fo r o o 0 witeino Goumer_ Fo a o o1 witeinto Counter For 9 witinto counter Foro 1 1 mite contt word Fo o 10 0 Read tom Counter Fo fo o1 Read tom Counter Fo o 11 0 Read fom Courter2 Fo o 11 1 No Operaton st Pr x x x X No operaton 6 Sure Fo 1 t x x no operaton State Figure 14 Read Write Operations Summary Command ignored status already latched for Counter 1 Figure 13 Read Back Command Example D 10 National Instruments Corporation National Instruments Corporation Appendix D Mode Definitions The following are defined for use in eens the operation of the 8254 CLK Pulse a rising edge then a falling edge in that order of a Counter s CLK in put Trigger 4 rising edge of a Counter s GATE i input Counter loading the transfer of a count from the CR to the CE refer to the Functional Descripti
81. d port reading Port A returns the current data at Port A If the DBLBUFA bit in the CFGI Register is set data is latched into Port A on the active level or active edge of REQI In level mode data is latched during the active level of REQI until REQI is inactive In pulse mode data is latched on the active edge of REQI until the data is read from the port Either 8 bit or 16 bit transfers can be performed on Port A 16 Bit Write or Read from Port A Port B Port A 7 615 4 3 2 1 017 615 4 3 2 1 0 8 Bit Write or Read from Port A Port A 7161514 3 1241 Jo AT DIO 32F User Manual 4 22 National Instruments Corporation Chapter 4 Programming Port B Register The Port B Register contains eight bits that connect to the digital I O connector and can either be read from or written to Address Base address 07 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 When Port B is configured as a write port writing data to this register latches the data into Port B and sends the data out on Port B Reading Port B when it is in write mode returns the value that is currently driven on the port If the DBLBUFB bit in the CFG3 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ level or pulse is received During an active REQ level or pulse the data is dumped to the I O connector When Port B is configured as a
82. e Verify that this space is not already used by other equipment installed in your computer If any equipment in your computer uses this base I O address space change the base I O address of the AT DIO 32F or of the other device If you change the AT DIO 32F base I O address make a corresponding change to any software packages you use with the AT DIO 32F Table 2 2 lists the default settings of other National Instruments products for the PC For more information about the I O address of your PC refer to the technical reference manual for your computer AT DIO 32F User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Each switch in U61 corresponds to one of the address lines A9 through A5 Press the side marked OFF to select a binary value of 1 for the corresponding address bit Press the other side of the switch to select a binary value of 0 for the corresponding address bit Figure 2 2 shows two possible switch settings The shaded portion indicates the side of the switch that is pressed down This side down for 1 This side down for 0 A Switches Set to Base I O Address of Hex 000 U61 This side down for 1 This side down for 0 B Switches Set to Base I O Address of Hex 240 Factory Setting Figure 2 2 Example Base I O Address Switch Settings The five LSBs of the address A4 through AO are decoded by the AT DIO 32F to select the appropriate AT DIO 32F register To change the base I O addre
83. ed to load a value into Counter 1 or to read back the value of Counter 1 The CNTR1 Register can be used as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 18 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTRIB7 CNTRIB6 CNTRIB5 CNTRIB4 CNTRIB3 CNTR1B2 CNTRIBI CNTR1BO Bit Name Description 7 0 CNTRIB lt 7 0 gt Counter 1 Load Read Bits Writing a data value to these bits loads the starting value into Counter 1 Reading these bits returns the current count of Counter 1 or latched data for Counter 1 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 1 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the least significant byte and the second read returns the most significant byte If status and count information are both latched the first read from this register returns the status byte and the next one read for 8 bit mode or two reads for 16 bit mode return the count bytes regardless of the order in which the information was latched AT D
84. egister 4 16 to 4 17 B 3 theory of operation 3 2 COUNT bit 4 35 Counter 1 and Counter 2 B 3 B 3 AT DIO 32F User Manual pattern generation 4 50 to 4 52 Counter 3 pattern generation 4 49 to 4 50 programming example 4 47 Counter Register Group CNTRI Register REQI generator 4 30 B 4 CNTR2 Register REQ2 generator 4 31 B 4 CNTR3 Register timebase generator 4 32 B 5 CNTRCMD Register 4 33 to 4 36 B 5 overview 4 29 register map 4 2 counters onboard See onboard counters customer communication xii D data latches and drivers 3 2 to 3 3 data settling delay See handshaking DATA signal 2 18 DBLBUFA bit 4 6 DBLBUFB bit 4 11 DBLBUFC bit 4 9 DBLBUPFD bit 4 15 DBLDMA bit 4 12 digital I O connector 3 4 Digital I O Port Register Group overview 4 21 Port A Register 4 22 B 3 Port B Register 4 23 B 3 Port C Register 4 24 B 4 Port D Register 4 25 B 4 register map 4 2 DIOAO through DIOA7 signals 2 14 DIOAEN bit 4 6 DIOBO through DIOB7 signals 2 14 DIOBEN bit 4 6 DIOCO through DIOC7 signals 2 15 DIOCEN bit 4 9 DIODO through DIOD7 signals 2 15 DIODEN bit 4 9 DMA channel configuration 2 7 to 2 9 default settings chart 2 2 default settings for National Instruments products 2 6 jumper settings 2 8 to 2 9 National Instruments Corporation theory of operation 3 10 DMA terminal count Group 1 DMA terminal count example 4 46 Group 2 DMA terminal count example 4 47 DMA t
85. enscceenscesenseseenes B 4 CNTR3 Register Timebase Generator ce eee tuti debuts B 5 CNTRCMD RGEISIET roa ert D S Re SER D urea es RE SA Deed Ras e tee b Ue ror ea e Reus B 5 Read Back COmfIald ose pee d uie steets B 5 Status BRAG PP B 5 Appendix C Application NOLES 5 22 eee tp ahaha A a ca ue cha eh E n C 1 Comm nicating witha Printer o o ereis e bios aeresu ix Pov etu touch obi ai odes C 1 Cabling qm C 1 Sending Pilesto be Printed sss ose cte ene e S Me stu IN Cen MES Hei Ede qet C 2 AT DIO 32F to AT DIO 32F 16 Bit Communications eene C 4 Cabin E oer DE Cm C 5 Sending and Receiving files with the AT DIO 32F eee C 5 The AT DIO 32F and I O Module Racks 3 4 28 asses ea Pto at eee dope edenda C 10 Appendix D Intel Data SBeep oit o uma iso Dota italia aaa tmu ts D 1 National Instruments Corporation vii AT DIO 32F User Manual Contents Appendix E Customer Communication sse tette tenentes E 1 GIOSSaEV oio ses anges ay aac ella tees ay Aie Ut ed a e Aah Glossary 1 lo HT Index 1 Figures Figure 2 1 AT DIO 32 F Parts Locator Diagram eese 2 3 Figure 2 2 Example Base I O Address Switch Settings see 2 5 Figure 2 3 DMA Jumper Settings for DMA Channels 5 and 6 Factory Settings 2 8 Figure 2 4 DMA Jumper Settings for DMA Channel 5 Only eee 2 8
86. ents The AT DIO 32F I O bracket has been designed so that the shield of the I O cable can be grounded through the computer chassis when a mating connector such as the following is used AMP Special Industries part number 2 746483 2 Many varieties of shielded ribbon cable can work with the preceding mating connector One type of shielded cable encloses a standard ribbon cable with a shielded jacket Recommended manufacturers and the appropriate part numbers for this type of cable are as follows Belden Electronic Wire and Cable part number 9L28350 T amp B Ansley Corporation part number 187 50 AT DIO 32F User Manual 2 20 National Instruments Corporation Chapter 3 Theory of Operation This chapter explains the basic operation of the AT DIO 32F circuitry The AT DIO 32F is a high speed 32 bit parallel digital I O interface for the PC The 32 lines of digital I O on the AT DIO 32F are divided into four 8 bit ports DIOA DIOB DIOC and DIOD Ports A and B are assigned to handshaking Group 1 and Ports C and D are assigned to handshaking Group 2 Each group can be programmed as either an input or an output group and each group has its own independent handshaking signals for data transfers The key functional components of the hardware are illustrated in the block diagram shown in Figure 3 1 Address Configuration and Status Decoding Registers Circuitry Data m e RENT Lacne M Drivers T O a Channel A andoian Con
87. ernal signal 4 53 using onboard counters 4 49 to 4 52 Counter 3 4 49 to 4 50 Counters 1 and 2 4 50 to 4 52 PC I O channel control circuitry 3 2 physical specifications A 2 pin description compatibility 1 1 for Intel 8254 programmable interval timer D 3 I O connector 2 13 B 1 port registers See Digital I O Port Register Group power requirement specifications A 2 printer communications building a cable C 1 sending files to printers C 2 to C 4 programmable interval timer See Intel 8254 programmable interval timer programming See also application notes registers 32 bit transfers 4 48 considerations 4 37 data settling delay 4 43 DMA transfers 4 48 handshaking modes 4 39 to 4 42 input data latch 4 44 interrupt handling 4 44 to 4 47 National Instruments Corporation Index 5 Index I O transfers 4 43 to 4 44 Mode 0 4 37 Mode 1 4 38 to 4 39 pattern generation using external signals 4 53 using onboard counters 4 49 to 4 52 RTSI bus interface 4 53 to 4 55 RTSI bus switch 4 54 to 4 55 PULSE bit 4 6 PULSE2 bit 4 9 RD signal 2 17 Read Back command 4 35 B 5 read handshake timing See handshaking read and write timing 2 19 to 2 20 registers Configuration and Status Register Group 4 4 to 4 20 CFGI Register 4 5 to 4 7 B 2 CFG2 Register 4 8 to 4 10 B 2 CFG3 Register 4 11 to 4 13 B 2 CFG4 Register 4 14 to 4 15 B 2 CNTINTCLR Register 4 18 B 3 DMACLRI Regis
88. essary to meet FCC Class A Emission Limits AT DIO 32F User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Refer to the Cabling section in Chapter 2 Configuration and Installation for additional information on cabling and connectors Unpacking Your AT DIO 32F board is shipped in an antistatic plastic package to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions Touch the plastic package to a metal part of your PC chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer National Instruments Corporation 1 5 AT DIO 32F User Manual Chapter 2 Configuration and Installation This chapter explains the installation of the AT DIO 32F board into your computer signal connections to the AT DIO 32F board and cable wiring Board Configuration The AT DIO 32F contains three jumpers and one DIP switch to configure the AT bus interface and board clock settings The jumpers are shown in the parts locator diagram in Figure 2 1 Jumper W3 selects the clock signal used by the board and the clock pin on the RTSI bus Jumper W1 selects the DMA channel and
89. f nl scanf x CFG1 CFG2 CFG3 CFG4 STATI PORTA PORTC lowEOF byte only set End main y up dio choose wha fp filename 81 lowl EOF n CFGlos CFG2os CFG3os CFG4os STATos PORTAos 4 PORTCos 4 t EOF amp 0x00ff Enter the base address amp base addr base addr base addr base addr base addr base addr base addr t base addr address offset of the registers of AT DIO 32F CFGlos CFG20s CFG3os CFG4os STATos PORTAos PORTCos Appendix C Registers of AT DIO 32F base address is input from the keyboard of the AT MIO 32F Hex Set so that D EOF character is in the low Pesce iuda Sets up AT DIO 32F Ke setup dio outpw CFG1 0x00 Initialize the board outpw CFG2 0x00 outpw CFG3 0x00 outpw CFG4 0x01 Set for Rev C board Set up for leading edge outpw CFG1 0x710 Enable DIOAEN and DIOBEN PULSE1 is high EDGE1 is low and LRESET1 outpw CFG2 0x710 Enable DIOCEN and DIODEN PULSE2 is high EDGE2 is low and LRESET2 outpw CFG1 0x610 Reconfigure after reset outpw CFG2 0x610 outpw CFG3 0x4800 Enable WRITEC and WRITED to write WRITEA and WRITEB are configured to read AT DIO 32F User Manual National
90. for handshaking Port A Handshaking Enable Bit When DIOAEN is set Port A is enabled for handshaking Local Reset for Group 1 Bit Setting and clearing LRESET1 resets the handshaking circuitry for Group 1 Handshaking configuration bits must be reset after an LRESETI Don t Care Bit This bit is unused on the Revision C and later revisions of the board On the Revision B board this bit is used as the Group 1 Handshaking Enable Bit Group 1 Request Invert Bit When INVRQOI is set the handshaking request REQI is considered an active low signal Group 1 recognizes a request when REQI is low When INVRQ 1 is cleared REQ is considered an active high signal Group recognizes a request when REQ is high Port A Double Buffer Enable Bit If DBLBUFA is set Port A is double buffered When Port A is configured as an output port a write operation to the port loads data into the first buffer of the port When a REQ is received the data is transferred to the second buffer of the port which dumps the data to the digital I O connector Double buffering is usually used for pattern generation If DBLBUFA is cleared Port A is a single buffer that is data written to the port is immediately dumped to the digital I O connector When Port A is configured as an input port and DBLBUFA is set an active level or edge of a REQ signal latches the data into the input buffer of Port A A read operation reads the data in the buffer instead of the I O
91. g handshaking purposes or clear and set DIOAEN of the CFGI Register Counter 2 Source Select Bit The CNT2SRC bit selects the counting source for Counter 2 If CNT2SRC is set the output of Counter 3 is used as the counting source for Counter 2 If CNT2SRC is cleared a 10 MHz clock is used as the counting source for Counter 2 Counter 1 Source Select Bit The CNTISRC bit selects the counting source for Counter 1 If CNTISRC is set the output of Counter 3 is used as the counting source for Counter 1 If CNTISRC is cleared a 10 MHz clock is used as the counting source for Counter 1 Double DMA Mode Enable Bit When DBLDMA is set the AT DIO 32F is in double DMA channel mode In double DMA mode only the Group 1 handshaking lines are used DMA transfers use the DMA channel selected for Group 1 until a DMA terminal count is received then the DMA channel selected for Group 2 is used for the Group 1 DMA transfers until a DMA terminal count for that channel is received DMA transfers switch between the two channels This configuration transfers data on one DMA channel and services data on another channel at the same time 4 12 National Instruments Corporation Chapter 4 Bit Name 6 CNTINTEN 5 CNT2HSEN 4 CNTIHSEN 3 CNT2EN 2 CNTIEN 1 TCINTEN2 0 TCINTENI Programming Description continued Counter Interrupt Enable Bit When CNTINTEN is set interrupts are enabled for Counter 3 An interrupt request is asserted when a r
92. gister The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB bit 15 for a 16 bit register bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside this square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers one or more bits are labeled with Xs indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance When a register is written to setting or clearing these bit locations has no effect on the AT DIO 32F hardware National Instruments Corporation 4 3 AT DIO 32F User Manual Programming Chapter 4 Configuration and Status Register Group The seven registers making up the Configuration and Status Register Group can be used for general monitoring and control of the AT DIO 32F hardware The four configuration registers CFG1 CFG2 CFG3 and CFG4 control the digital I O modes handshaking modes interrupt and DMA operations The other three configuration registers CNTINTCLR DMACLRI and DMACLR2 clear various interrupt status bits The status register STAT reflects the DMA interrupt and handshaking signal status Bit description
93. h REQ1 and ACKI as negative logic follow these steps 1 Write hex 0644 to the CFGI Register to set up the handshaking mode 2 Write hex 2400 to the CFG3 Register to set up the group as a write port if the port is a read port skip this step Reading the STAT Register returns the status of REQI ACKI and the DRDYI bit The polarity of the handshaking lines for each group is programmable If the external signal connected to REQ1 or REQ is active low INVRQI or INVRQO respectively should be set If the external signal connected to ACK1 or ACK2 is active low INVACKI or INVACK2 respectively should be set The status of REQ1 REQ2 ACK1 and ACK2 as seen at the digital I O connector can be read from the STAT Register If handshaking is not enabled the ACK lines can be used as extra AT DIO 32F User Manual 4 56 National Instruments Corporation Chapter 4 Programming output lines on the digital I O connector These lines can be controlled by setting and clearing the SETACKI and SETACK2 bits Each handshaking group has an LRESET bit Setting and then clearing this bit resets the handshaking circuitry for that group To perform another handshaking write operation after an LRESET the appropriate WRITE bit must first be cleared and then set to logic high to set up the circuitry for another transfer For example to set up Port C as an 8 bit handshaking write port with REQ2 and ACK2 as positive logic follow these steps 1 Write
94. he CFG1 Register 2 Write hex 0100 to the CFG2 Register 3 Write 0000 to the CFG3 Register 4 Write 0000 to the CFG1 Register 5 Write 0000 to the CFG2 Register 6 Write 0001 to the CFG4 Register only for Revision D and newer versions of the board 7 Write hex 14 to the CNTRCMD Register 8 Write hex 54 to the CNTRCMD Register 9 Write 0 to the DMACLRI Register 10 Write 0 to the DMACLR2 Register 11 Write 0 to the CNTINTCLR Register This sequence leaves the AT DIO 32F circuitry in the following state All digital I O ports are in input mode All interrupts are cleared and disabled The outputs of Counter 0 and Counter 1 are high The handshaking circuitry are cleared National Instruments Corporation 4 37 AT DIO 32F User Manual Programming Chapter 4 Mode 0 Programming Whenever the AT DIO 32F is started up each digital I O port is configured as a read port The status of the lines connected to each port can be determined by reading that port To configure a port as a write port the port s corresponding WRITE bit must be set If a write port is read the result is the data currently driven on that port Any value written to a write port is then driven on the corresponding digital I O lines When the WRITE bit for a port is cleared the port is once again configured as a read port For example to use Ports A and B as write ports write hex 2400 to the CFG3 Register Clearing bit 10 and bit 13 of the CFG
95. he CFG4 Register is set data is latched into Port D on the active level or active edge of REQI In level mode data is latched during the active level of REQ2 until REQ2 is inactive In pulse mode data is latched on the active edge of REQ2 until the data is read from the port Only 8 bit transfers can be performed on Port D 8 Bit Write or Read from Port D Port D 7 6 5 4 3 2 1 0 National Instruments Corporation 4 25 AT DIO 32F User Manual Programming Chapter 4 RTSI Bus Register Group The two registers making up the RTSI Bus Register Group program the AT DIO 32F RTSI switch for routing of signals on the RTSI bus trigger lines to and from AT DIO 32F request REQ and acknowledge ACK signal lines Bit descriptions of the two registers making up the RTSI Bus Register Group are given on the following pages AT DIO 32F User Manual 4 26 National Instruments Corporation Chapter 4 Programming RTSISHFT Register The RTSISHFT Register contains one bit RSI that is a serial input to the RTSI switch RSI must be written to 56 times to load the internal 56 bit RTSI control register Address Base address 10 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Bit Name Description 7 1 x Don t Care Bits 0 RSI RTSI Switch Serial Input This bit is the serial input to the RTSI switch Each time the RSI bit is written to the value written is shifted into the RTSI switch internal 56 bit contr
96. he timing diagrams for trailing edge mode For detailed timing information refer to Chapter 2 Configuration and Installation WR TDELAY ACK Figure 4 6 Trailing Edge Mode Write Handshake Timing RD TDELAY ACK Figure 4 7 Trailing Edge Mode Read Handshake Timing AT DIO 32F User Manual 4 42 National Instruments Corporation Chapter 4 Programming Data Settling Delay Each handshaking group has a set of bits to select a data settling time TDELA Y between each transfer For short cable lengths this delay is usually zero For longer cable lengths noisy environments or special handshaking specifications a longer data settling time may be required This delay can also be used to lengthen the ACK pulse Table 4 2 shows these data settling time settings Table 4 2 CFGI Data Settling Time Settings T1S2 T1S1 T1S0 Delay nsec T2S2 T2S1 T2S0 Delay nsec 0 0 100 200 300 500 600 700 Programmed I O Transfers To perform programmed I O handshaking the DRDY bit in the STAT Register must be polled by software When the bit is set the software can then write or read data to or from the digital I O port First configure the handshaking group to be used and enable the ports to be used for handshaking Be sure that the direction of each group is programmed correctly In write mode the external device is ready to receive data when the DRDY bit in the STAT Register is set The program waits until DRDY i
97. hex 0200 to the CFG2 Register to set up the Port C handshaking mode 2 Write hex 0800 to the CFG3 Register to set up Port C as a write port if the port is a read port do not set bit 11 of the CFG3 Register Write hex 0300 to the CFG2 Register to reset Group 2 handshaking status Write hex 0200 to the CFG2 Register Write hex 0000 to the CFG3 Register to clear the WRITEC bit after the LRESET Dy ade Write hex 0800 to the CFG3 Register to set the WRITEC bit again after the LRESET Reading the STAT Register returns the status of REQ2 ACK2 and the DRDY2 bit Handshaking Modes The AT DIO 32F can be programmed for one of three types of handshake timing level mode leading edge mode and trailing edge mode These modes are described in detail in the following pages For detailed timing information refer to Chapter 2 Configuration and Installation In the following timing diagrams REQ and ACK are shown as positive logic that is INVRQ and INVACK are cleared When the WRITE bit is set an internal pulse called GO initializes a write transfer DRDY is the data transfer ready bit as seen in the STAT Register WR and RD are the write and read pulses from the PC TDELAY is the programmable data settling delay which is set either in the CFG1 Register or the CFG2 Register This delay is between 0 and 700 nsec Level Mode In level mode ACK remains active until another REQ is received A handshaking group is in level mode when its PULSE and
98. ields labeled A6 through AO and B6 through BO are the 4 bit control fields for each RTSI switch pin of the same name The 4 bit control field for pin AO is shown in Figure 4 9 AT DIO 32F User Manual 4 54 National Instruments Corporation Chapter 4 Programming The bits labeled S2 through SO are the signal source selection bits for the pin One of seven source signals can be selected Pins A6 through AO select any of the pins B6 through BO as signal sources Pins B6 through BO select any of the pins A6 through AO as signal sources For example the pattern 011 for S2 through SO in the AO control field selects the signal connected to pin B3 as the signal source for pin AO The bit labeled OUTEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regardless of the source signal selected instead the pin can be used as an input pin If the A3 control field in Figure 4 9 contains the pattern 0111 the signal connected to pin B3 Trigger Line 3 appears at pin A3 With this arrangement the REQ2 signal can be driven by Trigger Line 3 Conversely if the B4 control field contains the pattern 1011 the signal connected to pin A5 appears at pin B4 With this arrangement Trigger Line 4 can be driven by the AT DIO 32F ACK2 signal In this way boards connected via the RTSI bus can send signals to each other over
99. in read mode and enabled for handshaking DRDY 2 is set when data can be read at the I O connector When Group 2 is in write mode DRDY2 is set when the external device is ready to receive the data Group 2 Handshaking Request Status REQ reflects the status of the Group 2 handshaking request line as seen at the digital I O connector Group 2 Handshaking Acknowledge Status Bit ACK2 reflects the status of the Group 2 handshaking acknowledge signal as seen at the digital I O connector AT DIO 32F User Manual Programming Chapter 4 CNTINTCLR Register Writing to the CNTINTCLR Register clears the interrupt request asserted when a rising edge on the Counter 3 output is detected Address Base address OA hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used AT DIO 32F User Manual 4 18 National Instruments Corporation Chapter 4 Programming DMACLRI Register Writing to the DMACLRI Register clears the interrupt request asserted when the DMA terminal count signal of Group 1 is detected Address Base address OC hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 19 AT DIO 32F User Manual Programming Chapter 4 DMACLR2 Register Writing to the DMACLR2 Register clears the interrupt request asserted when the DMA terminal count signal of Group 2 is detected Address Base address OE hex Type Write only Word Size 16 bi
100. inish clearing handshaking 6 Write hex 4820 to the CFG3 Register to enable Counter 2 for pattern generation and to set Group 2 in write mode set the WRITEC and WRITED bits 7 Write hex 003 to the CFG4 Register to set double buffer output of Port D 8 Write hex 4828 to the CFG3 Register to start pattern generation on Counter 2 set the CNT2EN bit The counter is loaded with the initial count in the CNTR2 Register and when the CNT2EN bit is set the counter is decremented by 1 on each clock pulse REQ2 is initially high When the counter decrements to 1 REQ2 goes low for one clock pulse and then returns to high The counter is then reloaded from the CNTR2 Register and decrementing continues The trailing edge of REQ2 causes the DRDY2 bit to go high The DRDY2 bit can be monitored by a polling loop by interrupt request generation or by DMA request generation With one of these methods data can then be written out to Port C To use DMA for pattern generation you must set the DMAEN bit then program the DMA controller between steps 5 and 6 AT DIO 32F User Manual 4 52 National Instruments Corporation Chapter 4 Programming Pattern Generation Using an External Signal An external signal connected to the REQ line of a group can be used for pattern generation The programming steps to configure Group 1 for 16 bit pattern generation on an external signal are as follows 1 Connect the external signal to the REQ line 2 If the ex
101. irection RWGRPI RWGRP2 REQI REQ2 ACKI ACK2 INI continues National Instruments Corporation 4 53 AT DIO 32F User Manual Programming Chapter 4 Table 4 6 RTSI Switch Signal Connections Continued RTSISwitch Pin Signal Name TRIGGERO Bidirectional TRIGGER 1 Bidirectional TRIGGER2 Bidirectional TRIGGER3 Bidirectional TRIGGER4 Bidirectional TRIGGERS Bidirectional TRIGGER6 Bidirectional Programming the RTSI Bus Switch The RTSI switch can be programmed to connect any of the signals on Side A to any of the signals on Side B and vice versa To do this a 56 bit pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Shift Register and then writing to the RTSI Strobe Register to load the pattern into the RTSI switch The 56 bit pattern is made up of two 28 bit patterns one for Side A and one for Side B of the RTSI switch The low order 28 bits select the signal sources for the Side B pins The high order 28 bits select the signal sources for the Side A pins Each of the 28 bit patterns are made up of seven 4 bit fields one for each pin The 4 bit field selects the signal source and the output enable for the pin Figure 4 9 shows the bit map of the RTSI switch 56 bit pattern BIT 55 51 47 43 39 35 31 27 23 19 15 11 7 3 O ajeje eA SERICO B MS LSB AO Control BIT 31 30 29 28 Figure 4 9 RTSI Switch Control Pattern In Figure 4 9 the f
102. is information helps us provide quality products to meet your needs Title X AT DIO 32F User Manual Edition Date April 1995 Part Number 320147 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678 Glossary AC AWG BCD D A dB DMA hex Hz in INTR I O Tout LSB MB MSB RAM RTSI VDC Vee Vin National Instruments Corporation degrees percent amperes alternating current American Wire Gauge binary coded decimal Celsius digital to analog decibels direct current direct memory access Farads hexadecimal hertz inches Interrupt signal input output output current least significant bit meters megabytes of memory most significant bit random access memory Real Time System Integration seconds volts volts direct current positive voltage supply volts in watts Glossary 1 AT DIO 32F User Manual Index Numbers 0 bit 4 17 4 35 16 bit communications See AT DIO 32F to AT DIO 32F 16 bit communications 32 bit t
103. ising edge is received on the output of Counter 3 This interrupt request is put on the interrupt line that is set for Group 2 Counter 2 Handshake Enable Bit If CNT2HSEN is set the output of Counter 2 generates the handshaking request for Group 2 Counter 1 Handshake Enable Bit If CNTIHSEN is set the output of Counter 1 generates the handshaking request for Group 1 Counter 2 Enable Bit If CNT2EN is set and the IN2 line is high Counter 2 is enabled for counting Counter Enable Bit If CNTIEN is set and the IN2 line is high Counter 1 is enabled for counting Group 2 Terminal Count Interrupt Enable Bit When TCINTENG is set interrupts are enabled for Group 2 DMA terminal counts An interrupt request is asserted when a DMA terminal count for Group 2 is received Group 1 Terminal Count Interrupt Enable Bit When TCINTENI is set interrupts are enabled for Group 1 DMA terminal counts An interrupt request is asserted when a DMA terminal count for Group 1 is received National Instruments Corporation 4 13 AT DIO 32F User Manual Programming Chapter 4 CFG4 Register Revision C and later versions of the AT DIO 32F have a CFG4 Register This register contains four bits that set the leading pulse delay mode Port D double buffer mode and version compatibility Address Base address 14 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 o o 0 o o o o 0o 7 6 5 4 3 2 1 0 0
104. it 4 12 4 16 transfers 32 bit 4 48 DMA 4 48 programmed I O transfers 4 43 to 4 44 rate specifications A 1 TS2 lt 2 0 gt bit 4 8 U unpacking the AT DIO 32F 1 5 W WR signal 2 17 write handshake timing See handshaking write timing 2 19 to 2 20 WRITEA bit 4 12 WRITEB bit 4 11 WRITEC bit 4 12 WRITED bit 4 11 X X Don t Care bit 4 6 4 9 4 16 4 17 National Instruments Corporation Index 7 Index AT DIO 32F User Manual
105. l BASIC Turbo Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and Visual Basic Turbo Pascal Microsoft C with SDK and Borland C for Windows NI DAQ software is on high density 5 25 in and 3 5 in diskettes AT DIO 32F User Manual 1 2 National Instruments Corporation Chapter 1 Introduction Optional Software This manual contains complete instructions for directly programming the AT DIO 32F Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT DIO 32F is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming described in Chapter 4 Programming You can use the AT DIO 32F with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows enhances Microsoft C and QuickBASIC Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation Part numbers for these software packages are listed in the following table LabVIEW for Windows 776670 01 LabWindows Standard package 776473 01 Advanced Analysis Library 776474 01 Standard package with the Advanced Analysis Library 776475 01 National Instruments Corporation 1 3 AT DIO 32F
106. l I O interface board for the PC The 32 lines of digital I O are organized into four 8 bit ports With the various handshaking options available the AT DIO 32F is compatible with a wide range of peripheral devices and other computers The AT DIO 32F can be used for interrupt handling and DMA transfers on two DMA channels Onboard counters can be used for pattern generation A RTSI bus interface can transfer signals from other AT Series boards to the AT DIO 32F All digital I O is transferred through a standard 50 pin male connector The pin assignments for this connector are compatible with the DEC DRV11J parallel interface and most standard 32 channel digital I O applications The AT DIO 32F can be used in a wide range of digital I O applications With the AT DIO 32F a digital pattern generator can be implemented or the PC can be interfaced to any of the following Other computers Another IBM PC XT PC AT or compatible computer with a National Instruments PC DIO 24 or AT DIO 32F IBM Personal System 2 computer with a National Instruments MC DIO 24 or MC DIO 32F Apple Macintosh II computer with a National Instruments NB DIO 24 or NB DIO 32F DEC UNIBUS or Q BUS system with a 16 bit interface DEC LSI 11 microcomputer with a 32 bit DRV11J interface Any other computer with an 8 bit 16 bit or 32 bit parallel interface e Centronics compatible printers and plotters e Panel meters Instruments and test equipment
107. l of the digital I O modes of the AT DIO 32F The other configuration registers are used to configure three onboard counters and the RTSI bus and to clear certain interrupt status bits The 16 bit status register STAT contains DMA interrupt and handshaking signal status information Refer to Chapter 4 Programming for additional information about these registers Data Latches and Drivers The four 8 bit digital I O ports are divided into two handshaking groups Ports A and B are assigned to handshaking Group 1 Ports C and D are assigned to handshaking Group 2 Each port can be configured as read or write and single buffered or doubled buffered When the board is first turned on each port is configured as a single buffered read port Reading a single buffered input port returns the data currently available for that port at the I O connector Data is latched in a read port on the appropriate active edge of the handshaking request line REQ or REQ2 when the port is configured as a double buffered input port AT DIO 32F User Manual 3 2 National Instruments Corporation Chapter 3 Theory of Operation If a port is configured as a single buffered write port the data written to that port is latched into the port and driven on the corresponding digital I O lines Reading the port returns the data that is currently driven by the port Write ports configured for double buffering are often used for pattern generation A double buffered write port
108. ly CRy and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Contro Logic is aiso shown in the diagram CLK n GATE n and OUT n are all connected to the outside world through the Control Logic 8254 SYSTEM INTERFACE The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner as all Appendix D 8254 other peripherals of the family It is treated by the system s software as an array of peripheral 1 0 ports three are counters and the fourth is a control register for MODE programming Basically the select inputs Ag A4 connect to the Ap A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems OPERATIONAL DESCRIPTION General After power up the state of the 8254 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Programming the 8254 Counters are programmed by writing a Control Word and
109. mmand This command allows the user to check the count value programmed Mode and current states of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 National Instruments Corporation AO A1 CS 0 RD 1 WR 0 Do D De Ds Ds D O02 D L1 x count status ewr 2 ewr enro o Ds 0 Latch count of selected counter s D4 0 Latch status of selected counters s Da 1 Select Counter 2 De 1 Select Counter 1 D4 1 Select Counter 0 Do Reserved for future expansion Must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi le counter output latches OL by setting the COUNT bit DS 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed The counter is automatically unlatched when read but other counters remain latched untii they are read If multiple count read back commands are issued to the same counter without reading the count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back
110. n the Revision C board On the Revision B board this bit is used as the Group 1 Handshaking Enable Bit Group 2 Request Invert Bit When INVRQ is set the handshaking request REQ2 is considered an active low signal Group 2 recognizes a request when REQ2 is low When INVRQ 2 is cleared REQ2 is considered an active high signal Group 2 recognizes a request when REQI is high Port C Double Buffer Enable Bit If DBLBUFC is set Port C is double buffered When Port C is configured as an output port a write operation to the port loads data into the first buffer of the port When a REQ is received the data is transferred to the second buffer of the port which dumps the data to the digital I O connector Double buffering is usually used for pattern generation If DBLBUFC is cleared Port C is a single buffer that is data written to the port is immediately dumped to the digital I O connector When Port C is configured as an input port and DBLBUFC is set an active level or edge of a REQ signal latches the data into the input buffer of Port C A read operation reads the data in the buffer instead of the I O connector If DBLBUFC is cleared the port is transparent that is a read operation reads the data on the I O connector Group 2 Pulse Mode Bit When PULSE2 is set the Group 2 handshaking signals REQ2 and ACK2 are configured as pulse signals When PULSE2 is cleared the Group 2 handshaking signals are configured as level signals Grou
111. nsfers Interrupt Selection The AT DIO 32F board can connect to one or two of any of the 11 interrupt lines of the PC I O channel The interrupt lines are selected by jumper W2 which is located above the I O slot edge connector on the AT DIO 32F see Figure 2 1 To use the interrupt capability of the AT DIO 32F select one or two interrupt lines and place the jumpers in the appropriate positions to enable the particular interrupt lines The Group 1 interrupt uses the upper two rows of jumper W2 and the Group 2 interrupt uses the lower two rows of jumper W2 The AT DIO 32F can share interrupt lines with other devices by using a tri state driver to drive its selected interrupt line The AT DIO 32F hardware can use the following interrupt lines IRQ3 IRQ4 IRQS5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQI5 Note Do not use interrupt line 6 or interrupt line 14 Interrupt line 6 is used by the diskette drive controller and interrupt line 14 is used by the hard disk controller on most PCs Once you have selected an interrupt level place the interrupt jumper on the appropriate pins to enable the interrupt line The default interrupt lines are IRQ11 for Group 1 and IRQ12 for Group 2 These lines are selected by placing the jumper on the pins in row 11 of W1 and row 12 of W1 respectively Figure 2 6 shows the default interrupt jumper setting IRQ11 and IRQ12 To change the default setting remove the jumpers from their current settings
112. nterrupt request is asserted and software control enters the interrupt service routine In the interrupt service routine follow these steps a Check the DMATC2 bit in the STAT Register to verify that the current interrupt was generated by a Group 2 DMA terminal count condition b Perform the desired work c Write to the DMACLR2 Register to acknowledge that the Group 2 DMA terminal count interrupt condition has been serviced When another Group 2 DMA terminal count is received software control again jumps to the interrupt service routine Example Interrupt Generation on Counter 3 Counter 3 can be programmed to generate pulses at a specified time interval A rising edge on Counter 3 generates an interrupt request To use an interrupt service routine follow these steps 1 2 3 4 Set up rate generation mode for Counter 3 Set up Counter 3 for the desired time interval between data patterns Set the CNTINTEN bit in the CFG3 Register to enable interrupts on Counter 3 When a rising edge pulse on Counter 3 is received an interrupt request is asserted and software control enters the interrupt service routine In the interrupt service routine follow these steps a Check the CNTINT bit in the STAT Register to verify that the current interrupt was generated by a Counter 3 pulse b Perform the desired work c Write to the CNTINTCLR Register to acknowledge that the Counter 3 interrupt condition has been serviced
113. ny 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 848400 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 National Instruments Corporation E 1 Fax Number 03 879 9179 0662 437010 19 02 757 03 11 45 76 71 11 90 502 2930 1 48 14 24 14 089 714 60 35 02 48301915 03 3788 1923 95 800 010 0793 03480 30673 32 848600 2265887 91 640 0533 08 730 43 70 056 20 51 55 02 737 4644 0635 523154 AT DIO 32F User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax ___ Phone ___ Computer brand Model Processor Operating system Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software pr
114. oduct Version Configuration The problem is List any error messages The following steps will reproduce the problem AT DIO 32F Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products Base I O Address of AT DIO 32F Factory Setting hex 240 DMA Channels of AT DIO 32F Factory Setting 5 and 6 Interrupt Levels of AT DIO 32F Factory Setting 11 and 12 RTSI Clock Setting Factory Setting disconnect board from RTSI clock NI DAQ or LabWindows Version Handshaking Mode Other Products Computer Make and Model Microprocessor Clock Frequency Type of Video Board Installed DOS Version Programming Language Programming Language Version Other Boards in System Base I O Address of Other Boards DMA Channels of Other Boards Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products Th
115. ol register The data in the control register routes information for switching signals to and from the RTSI bus trigger lines The RSI bit must be written to 56 times to shift the 56 bits of routing data into the internal control register See Programming the RTSI Switch later in this chapter for more information National Instruments Corporation 4 27 AT DIO 32F User Manual Programming Chapter 4 RTSISTRB Register Writing to the RTSISTRB Register loads the contents of the RTSI Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSISTRB Register is written to after shifting the 56 bit routing pattern into the RTSISHFT Register Address Base address 12 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used AT DIO 32F User Manual 4 28 National Instruments Corporation Chapter 4 Programming Counter Register Group The four registers making up the Counter Register Group access the onboard 8254 2 Counter Timer The 8254 2 contains three counters Counters 1 2 and 3 can be used for pattern generation and Counter 3 can also be used to generate timed interrupts Bit descriptions of the four registers making up the Counter Register Group are given on the following pages National Instruments Corporation 4 29 AT DIO 32F User Manual Programming Chapter 4 CNTRI Register REQ1 Generator The CNTRI Register contains eight bits that are us
116. on MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Controi Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE counting GATE has no effect on OUT 0 disables After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK puise This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK puise is needed to load the Counter as this has already been done MODE 1 HARDWARE RETRIGG
117. on or in situations where AT DIO 32F interconnections are frequently changed Once a final field wiring scheme has been developed however you may want to develop your own cable This section contains information and guidelines for the design of such a cable National Instruments Corporation 2 19 AT DIO 32F User Manual Configuration and Installation Chapter 2 The AT DIO 32F I O connector is a 50 pin male ribbon cable header Recommended manufacturers and the appropriate part numbers for this header are as follows Electronic Products Division 3M part number 3596 5002 T amp B Ansley Corporation part number 609 5007 The mating connector for the AT DIO 32F is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the AT DIO 32F Recommended manufacturers and the appropriate part numbers for this mating connector are as follows Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part number 609 5041CE Recommended manufacturers and the appropriate part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are as follows Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 If you plan to use the AT DIO 32F for a communications application you may need shielded cables to meet FCC requirem
118. onfiguration and Installation Signal Connection Descriptions Pins Signal Names 43 50 DIOB lt 0 7 gt 35 42 DIOA lt 0 7 gt 33 REQI 31 OUTI INI 27 ACKI 24 REQ2 AT DIO 32F User Manual Chapter 2 Description Bidirectional data lines for Port B DIOB7 is the MSB DIOBO is the LSB Bidirectional data lines for Port A DIOA7 is the MSB DIOAO is the LSB Input handshaking request line for Group 1 When the AT DIO 32F is in write mode the external device activates this signal to indicate that it is ready to receive data When the AT DIO 32F is in read mode the external device activates this signal if data can be read on the data lines The polarity of this signal is changed by the INVRQI bit in the CFGI Register Extra output signal 1 This additional output signal can be connected to extra control lines and is controlled by the OUTI bit in the CFGI Register Extra input signal 1 This additional input signal is pulled up to 5 V by an onboard resistor The status of this signal can be obtained by reading the IN1 bit in the STAT Register This input signal can be used as an extra input signal line or as an external enable signal of Counter 1 of the board Output handshaking acknowledge signal for Group 1 When the AT DIO 32F is in write mode this signal becomes active when data has been written to the data lines When the AT DIO 32F is in read mode this signal becomes active when the available data on the da
119. ontro Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 OOn D0O4P oy Control Word Counter 0 Control Word Counter 1 Control Word Counter 2 LSB of count Counter 2 LSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 MSB of count Counter 1 MSB of count Counter 2 NOTE ocoo0o4 in uP o2 oo2coaoljP programming sequences In ail four examples all Counters are programmed to read write two byte counts These are only four of many possible Control Word Counter 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 oo22o0o2a2a Control Word Counter 1 Control Word Counter 0 LSB of count Counter 1 Control Word Counter 2 LSB of count Counter 0 MSB of count Counter 1 LSB of count Counter 2 MSB of count Counter 0 MSB of count Counter 2 O OOO P C E EE E a Figure 8 A Few Possibie Programming Sequences Read Operations it is often desirable to read the value ofa Counter without disturbing the count i in progress This is easi ly done in the 8254 haa fred poles nass toe ena ipa counters a simple read operation the Counter Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Co
120. or the other device National Instruments Corporation 2 7 AT DIO 32F User Manual Configuration and Installation Chapter 2 The AT DIO 32F hardware can only use Channels 5 6 and 7 as DMA channels Notice that these are the three available 16 bit channels on the PC I O channel The AT DIO 32F does not use and cannot be configured to use the 8 bit DMA channels on the PC I O channel Each DMA channel consists of two signal lines as shown in Table 2 4 Table 2 4 DMA Channels for the AT DIO 32F DMA DMA DMA Channel Acknowledge Request DRQS5 DRQ6 DRQ7 Two jumpers must be installed to select a DMA channel The switch BANK A is used to select the DMA channel for Group 1 and the switch BANK B is used to select the DMA channel for Group 2 Figure 2 3 displays the jumper positions for selecting DMA Channels 5 and 6 In this setting Group 1 uses DMA Channel 5 and Group 2 uses DMA Channel 6 Figure 2 3 DMA Jumper Settings for DMA Channels 5 and 6 Factory Settings If you want to use only one DMA channel then place the configuration jumpers in the positions shown in Figure 2 4 Figure 2 4 DMA Jumper Settings for DMA Channel 5 Only AT DIO 32F User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation If you do not want to use DMA for AT DIO 32F transfers then place the configuration jumpers in the positions shown in Figure 2 5 Figure 2 5 DMA Jumper Settings for Disabling DMA Tra
121. outp porta ch printf Sc ch echo character to screen AT DIO 32F to AT DIO 32F 16 Bit Communications This program transmits 16 bit words between two AT DIO 32F boards in separate PC computers With the program the AT DIO 32F can communicate with National Instruments MC DIO 32F or NB DIO 32F Ports A and B function as the 16 bit read channel with Group 1 handshaking and Ports C and D comprise the 16 bit write channel utilizing Group 2 handshaking AT DIO 32F User Manual C 4 National Instruments Corporation Appendix C Cabling Application Notes Use the following cable to connect the two AT DIO 32F boards Both connectors are 50 pin female ribbon cable connectors Any pins not listed are not used and should be left open The signal names PA PB PC and PD refer to Port A Port B Port C and Port D respectively Refer to Chapter 2 of this manual for connector and cable specifications AT DIO 32F 1 AT DIO 32F 2 PAO PAI PA2 PA3 PA4 PAS PA6 PAT PBO PBI PB2 PB3 PB4 PB5 PB6 PB7 REQI ACKI GND GND GND GND 21 23 14 12 13 11 16 9 15 10 PCO PCI PC2 PC3 PC4 PC5 PC6 PC7 PDO PDO PD2 PD3 PD4 PDS PD6 PD7 ACK2 REQ2 GND GND GND GND AT DIO 32F 1 AT DIO 32F 2 PCO PCI PC2 PC3 PC4 PC5 PC6 PC7 PDO PDI PD2 PD3 PD4 PD5 PD6 PD7 REQ2 ACK2 GND GND GND GND Sending and Receiving files with the AT DIO 32F 14 12 13 11 37 PAO 39 PAI 38 PA2 40 PA
122. p 2 Leading Trailing Pulse Mode Bit When EDGE2 and PULSE2 are both set the Group 2 handshaking signals are active on the trailing edge of the pulse When EDGE2 is cleared and PULSE2 is set the Group 2 handshaking signals are active on the leading edge of the pulse National Instruments Corporation 4 9 AT DIO 32F User Manual Programming Bit Name 2 INVACK2 1 SETACK2 0 OUT2 AT DIO 32F User Manual Chapter 4 Description continued Group 2 Acknowledge Invert Bit When INVACK2 is set the handshaking acknowledge signal ACK2 is configured as an active low signal Group 2 sends ACK2 as a low signal to acknowledge the end of a data transfer When INVACK2 is cleared ACK2 is configured as an active high signal Group 2 sends ACK2 as a high signal to acknowledge the end of a data transfer Group 2 Acknowledge Control Bit Setting and clearing SETACK2 controls the ACK2 bit on the digital I O connector Extra Output Bit 2 Setting and clearing OUT2 controls the OUT2 bit on the digital I O connector 4 10 National Instruments Corporation Chapter 4 Programming CFG3 Register The CFG3 Register contains 13 bits that control the Counter 1 and Counter 2 operations clock selection and I O port transfer mode Address Base address 04 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBLDMA CNTINTEN CNT2HSEN CNTIHSEN CNT2EN CNTIEN TCINTEN2 TCINTENI Bit Name Descri
123. ption 15 DBLBUFB Port B Double Buffer Enable Bit If DBLBUFB is set Port B is double buffered When Port B is configured as an output port a write operation to the port loads data into the first buffer of the port When a REQ is received the data is transferred to the second buffer of the port which dumps the data to the digital I O connector Double buffering is usually used for pattern generation If DBLBUFB is cleared Port B is a single buffer that is data written to the port is immediately dumped to the digital I O connector When Port B is configured as an input port and DBLBUFB is set an active level or edge of a REQ signal latches the data into the input buffer of Port B A read operation reads the data in the buffer instead of the I O connector If DBLBUFB is cleared the port is transparent that is a read operation reads the data on the I O connector 14 WRITED Port D Write Read Bit When WRITED is set Port D is configured for a write operation When WRITED is cleared Port D is configured for a read operation If Port D is configured for a write operation after every LRESET2 this bit must first be cleared and then set again for reintializing handshaking purposes or clear and set DIODEN of the CFG2 Register 13 WRITEB Port B Write Read Bit When WRITEB is set Port B is configured for a write operation When WRITEB is cleared Port B is configured for a read operation If Port B is configured for a write operation after
124. r Read signal This signal is the read signal generated from the control lines of the PC This signal is not available on the I O connector Write signal This signal is the write signal generated from the control lines of the PC This signal is not available on the I O connector Data transmission delay A data settling delay is added to ensure that data has settled during a transfer The delay for Group 1 is controlled by bits T1S2 through T150 in the CFGI Register The delay for Group 2 is controlled by bits T2S2 through T2580 in CFG2 This signal is not available on the I O connector Data signals on the I O connector In write mode these lines are driven by the AT DIO 32F and data is transfered from memory to the external device In read mode these lines are driven by the external device and data is transfered from the external device to memory 2 17 AT DIO 32F User Manual Configuration and Installation Chapter 2 AT DIO 32F Read and Write Timing lt lt TO D Tb _ lt ___________ _ ___ gt lt T2c la T2ab sa REQ DRDY Read or Write TDELAY ACK level mode ACK leading edge mode ACK trailing edge mode Data input mode Data output mode T4 T7a T9a T8a 4 T10ab 4 T8b e FT T7b T9b k re A 18e T9c T12 Tu C2 S WN IT15l
125. rams are designed as independent modules with the necessary parameters passed in the function call Therefore the functions can easily be transported to your own program Several software packages that support the AT DIO 32F are also available from National Instruments These packages simplify programming thus decreasing software development time For more information about optional software see Chapter 1 Introduction Communicating with a Printer The National Instruments AT DIO 32F can interface the PC to any Centronics or Centronics compatible printer In the following program Port A is configured for Group 1 handshaking and is connected to the printer s data lines Ports B C and D are not used and can be configured in Group 2 to communicate with another device Cabling Build a cable according to the following list to connect the AT DIO 32F 50 pin connector to the printer 36 pin connector Any pins not listed are not connected and should be left open Refer to Chapter 2 Configuration and Installation of this manual for connector and cable specifications Centronics AT DIO 32F Centronics AT DIO 32F STROBE 1 27 ACKI GND 19 17 GND DataO 2 37 DIOAO GND 20 17 GND Datal 3 39 DIOA1 GND 21 19 GND Data2 4 38 DIOA2 GND 22 19 GND Data3 5 40 DIOA3 GND 23 21 GND Data4 6 35 DIOA4 GND 24 21 GND Data5 7 42 DIOAS GND 25 23 GND Data6 8 36 DIOA6 GND 26 23 GND Data7 9 41 DIOA7 GND 27 28 GND ACKN 10 33 REQI GND 28 28 GND BUSY 11 29 INI GND 29 3
126. ransfers 4 48 A ACK signal 2 17 ACK 1 bit 4 17 ACK 1 signal 2 14 ACK2 bit 4 17 ACK2 signal 2 15 address decoder 3 2 address switch settings See base I O address application notes AT DIO 32F and I O module racks C 10 to C 11 AT DIO 32F to AT DIO 32F 16 bit communications cabling C 5 sending and receiving files C 5 to C 10 printer communications cabling C 7 sending files to printers C 8 to C 4 AT DIO 32F See also theory of operation block diagram 3 1 contents of kits 1 2 installation 2 2 overview xi 1 1 parts locator diagram 2 3 unpacking 1 5 AT DIO 32F and I O module racks C 10 to C 11 AT DIO 32F to AT DIO 32F 16 bit communications cabling C 5 sending and receiving files C 5 to C 10 National Instruments Corporation B base I O address avoiding device conflicts 2 4 configuration 2 4 to 2 5 default addresses 2 4 default settings for National Instruments products 2 6 example switch settings 2 5 factory settings chart 2 2 switch settings with base I O address and base I O address space 2 7 BCD bit 4 36 BCDSEL bit 4 34 bus See RTSI bus bus transceivers 3 2 C cabling AT DIO 32F and I O module racks C 10 to C 11 building printer cables C 7 cable for AT DIO 32F to AT DIO 32F 16 bit communications C 5 cable termination accessory CB 50 2 20 interfacing with other devices 2 23 CFGI Register description 4 5 to 4 7 B 2 register map 4 2 CFG2 Register B 2 des
127. ransfers 4 48 See also interrupt handling DMACH bit 4 16 DMACLRI Register description 4 19 B 3 register map 4 2 DMACLRQ2 Register description 4 20 B 3 register map 4 2 DMAENI bit 4 5 DMAEN bit 4 8 DMATCI bit 4 17 DMATC2 bit 4 17 documentation conventions used in the manual xii related documentation xii Don t Care bit See X Don t Care bit DRDY signal 2 17 DRDY 1 bit 4 17 DRDY1 programming example 4 45 DRDY bit 4 17 DRDY2 programming example 4 46 E EDGE bit 4 6 EDGE2 bit 4 9 electrical specifications I O signal rating 2 16 input signal 2 16 A 1 output signal 2 16 A 1 electrostatic damage prevention of 1 5 equipment optional 1 4 external signal for pattern generation 4 53 G GND signal 2 15 GO signal 2 16 National Instruments Corporation Index H handshaking data latches and drivers 3 2 to 3 3 data settling delay 4 43 input data latch 4 44 leading edge mode 3 5 to 3 6 4 40 to 4 41 level mode 3 5 4 39 overview 4 37 to 4 38 programmed I O transfers 4 43 to 4 44 theory of operation 3 4 to 3 10 trailing edge mode 3 9 to 3 10 4 42 hardware configuration See configuration hardware installation 2 12 I INI bit 4 16 INI signal 2 14 IN2 bit 4 17 IN2 signal 2 15 input data latch 4 44 input signal specifications 2 16 A 1 installation procedure for 2 12 unpacking the AT DIO 32F 1 5 Intel 8254 programmable interval timer absolute maxim
128. ration and Installation Chapter 2 asn 2 51 cf 8 SER eos off Cesi esn eztsie aan orn s sess e nssi cE tr Tian 2B 8 in E een sees e n vo secooce E sin a sees cf rociseoec B 920 EL iesi sB can z n ier 1B vo vecooce h vss B sea To 2 zoo c6 E tin rororo E ELI flo sestoe sE oreore i sis 2B Lass 88 CRD Coreg etn tin iss gB gen etn re vezooz Cf 5913398 ezn etn Carp ttn ttn HswiB 5B ban fan pzw3B CERE cin ain mg Cong gin Cea PEER ca 6355 a _ sersie hy on 115 LI 32 na38 T10 SEc0BT 3et 0I0 1U 066109 Persis f essi GB n en yest sB IEIIUES UE OB 081 qf L iess p 90171 ELIG if Figure 2 1 AT DIO 32F Parts Locator Diagram AT DIO 32F User Manual National Instruments Corporation Configuration and Installation Chapter 2 Base I O Address Selection The base I O address for the AT DIO 32F is determined by the switches at position U61 see Figure 2 1 The switches are set at the factory for the base I O address hex 240 This factory setting is used as the default base I O address value by National Instruments software packages using the AT DIO 32F The AT DIO 32F uses the base I O address space hex 240 through 25F with the factory setting Not
129. read port reading Port B returns the current data at Port B If the DBLBUFB bit in the CFG3 Register is set data is latched into Port B on the active level or active edge of REQ1 In level mode data is latched during the active level of REQI until REQI is inactive In pulse mode data is latched on the active edge of REQI until the data is read from the port Only 8 bit transfers can be performed on Port B 8 Bit Write or Read from Port B Port B 716 5 4 3 2 1 National Instruments Corporation 4 23 AT DIO 32F User Manual Programming Chapter 4 Port C Register The Port C Register contains eight bits that connect to the digital I O connector and can either be read from or written to Address Base address 08 hex Type Read and write Word Size 8 bit or 16 bit Bit Map 7 6 5 4 3 2 1 0 When Port C is configured as a write port writing data to this register latches the data into Port C and sends the data out on Port C Reading Port C when it is in write mode returns the value that is currently driven on the port If the DBLBUFC bit in the CFG2 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ2 level or pulse is received During an active REQ2 level or pulse the data is dumped to the I O connector When Port C is configured as a read port reading Port C returns the current data at Port C If the DBLBUFC bit in the
130. roup 1 and Group 2 the ACKI line asserts Two write or read operations are required for each 32 bit transfer one to Group 1 for the lower word and one to Group 2 for the upper word of the 32 bit datum Asserting both LRESETI and LRESET2 resets both groups and reinitializes the 32 bit transfer DMA can be used in conjunction with the 32 bit transfer mode for high speed 32 bit transfers The Group 1 data transfer and the Group 2 data transfer both use the DMA channel selected for Group 1 The count written to the DMA Terminal Count Register of the DMA controller should be twice the selected number of 32 bit transfers to be performed If double DMA mode is used the DMA channel used for the transfers swaps after each terminal count AT DIO 32F User Manual 4 48 National Instruments Corporation Chapter 4 Programming Pattern Generation Using Onboard Counters There are three onboard counters on the AT DIO 32F each designated for a specific purpose The output of Counter 1 is connected to the Group 1 handshaking request line REQ1 The output of Counter 2 is connected to the Group 2 handshaking request line REQ2 The output of Counter 3 can be used as the counting source for Counter 1 or 2 The counting source for Counter 3 is a 2 MHz square wave The output of Counter 3 can also be used to generate interrupts Counters 1 and 2 have counting enable bits that connect to the gate input of the counter The output of Counter 3 is always enabled The CN
131. rupts by setting the appropriate enable bit in the CFG Registers When the interrupt service routine is entered the appropriate status bits of the STAT Register reflect which interrupt requests are active When the interrupt condition has been serviced writing to an interrupt clear register may be necessary to clear the interrupt status bit Table 4 3 lists all of the interrupt conditions and status AT DIO 32F User Manual 4 44 National Instruments Corporation Chapter 4 Programming Table 4 3 Interrupt Condition and Status Interrupt Enable Bit Status Bit in the Type of Interrupt To Clear the in the CFG Register STAT Register Status Bit INTEN1 DRDY1 Data ready of Group 1 Read write data INTEN2 DRDY2 Data ready of Group 2 Read write data TCINTENI DMATCI DMA terminal count of Write to DMACLRI Group 1 Register TCINTEN2 DMATC2 DMA terminal count of Write to DMACLR2 Group 2 Register CNTINTEN CNTINT Counter 3 interrupt Write to CNTINTCLR Register Note Counter 3 interrupts use the interrupt line for Group 2 Example Interrupt Generation on DRDY1 Instead of polling the DRDY1 bit interrupts can be used to wait for the DRDY1 condition The interrupt service routine can then write or read the data to or from Group 1 To use interrupts for this task follow these steps 1 Setup Group 1 with the desired handshaking mode and direction 2 Set the INTENI bit in the CFG1 Register to enable interrupts on DRDY1 3 When DRDYI is set
132. s a polarized keyed connector to prevent inadvertent upside down connection to the AT DIO 32F Recommended manufacturer part numbers for this mating connector are Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part number 609 5041CE Recommended manufacturer part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 Recommended manufacturer part numbers for the 50 pin edge connector that connects a module rack to an edge connector are Electronic Products Division 3M part number 3415 0001 T amp B Ansley Corporation part number 609 5015M National Instruments Corporation C 11 AT DIO 32F User Manual Application Notes Appendix C A polarizing key can be plugged into these edge connectors to prevent inadvertent upside down connection to the I O module rack The location of this key varies from rack to rack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key are Electronic Products Division 3M part number 3439 2 T amp B Ansley Corporation part number 609 0005 Use Mode 0 when communicating with I O module racks Refer to Chapter 3 Theory of Operation of this manual for programming information AT DIO 32F User Manual C 12 National
133. s of the seven registers making up the Configuration and Status Register Group are given on the following pages AT DIO 32F User Manual 4 4 National Instruments Corporation Chapter 4 Programming CFG1 Register The CFG1 Register contains 16 bits that control the Group 1 I O mode handshaking mode and interrupt and DMA operations Address Base address 00 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 DMAENI Group 1 DMA Enable Bit When DMAENI is set DMA is enabled for Group 1 handshaking A DMA request is asserted when DRDY 1 is set 14 INTENI Group 1 Interrupt Enable Bit When INTENI is set interrupts are enabled for Group 1 handshaking An interrupt request is asserted when DRDY 1 is set 13 11 T1S lt 2 0 gt Group 1 Data Transmission Delay TDELAY 1 Bits These bits select the data settling delay used by Group 1 handshaking Long cable lengths or special handshaking specifications may require a data settling delay to ensure proper data transmission T1S2 T1S1 T1S0 TDELAY1 nsec 0 0 0 0 0 1 0 1 0 0 1 1 T 0 0 1 0 1 1 1 0 1 1 1 National Instruments Corporation 4 5 AT DIO 32F User Manual Programming Bit Name 10 DIOBEN 9 DIOAEN 8 LRESETI 7 X 6 INVRQI 5 DBLBUFA 4 PULSEI 3 EDGEI AT DIO 32F User Manual Chapter 4 Description continued Port B Handshaking Enable Bit When DIOBEN is set Port B is enabled
134. s set then writes the data to the appropriate output port The circuitry handshakes the data and sets DRDY again when the external device is ready for another transfer In write mode set the WRITE bit again after a reset of that group To perform Group 1 16 bit write programmed I O transfers using positive level handshaking follow these steps 1 Write hex 0600 to the CFG1 Register to set up the handshaking mode Write hex 2400 to the CFG3 Register to set up the group as a write port Wait until DRDY1 becomes set poll the STAT Register 2 3 4 Write the 16 bit data to Port A 5 Wait until DRDY1 becomes set then write the next data value to Port A 6 Repeat step 5 until all data has been written to Port A National Instruments Corporation 4 43 AT DIO 32F User Manual Programming Chapter 4 In read mode data is available for reading when the DRDY bit is set The program waits until the DRDY bit is set then reads the data from the enabled port Each time the DRDY bit is set another data value has been latched and can be read To perform read programmed I O transfers follow these steps 1 Write hex 0600 to the CFG1 Register to set up the handshaking mode 2 Wait until DRDY1 becomes set poll the STAT Register 3 Read the 16 bit data from Port A 4 Wait until DRDY1 becomes set then read the next data value from Port A 5 Repeat step 4 until all data has been read from Port A The digital I O connector has t
135. scription GO Internal Internal GO pulse This pulse is sent to the handshaking circuitry when the group s WRITE bit is set This signal initializes the circuitry for a data write transfer The GO signal is not available on the I O connector continues AT DIO 32F User Manual 2 16 National Instruments Corporation Chapter 2 Name REQ ACK DRDY RD WR TDELAY DATA Type Input Output Internal Internal Internal Internal I O National Instruments Corporation Configuration and Installation Description continued Handshaking request signal If the AT DIO 32F is in write mode this signal is asserted when the external device is ready to receive data If the AT DIO 32F is in read mode this signal is asserted when data is available to be read This signal is available on the I O connector Handshaking acknowledge signal If the AT DIO 32F is in read mode this signal is asserted by the AT DIO 32F when it has read the available data If the AT DIO 32F is in write mode this signal is asserted when the AT DIO 32F has written the data to the specified port This signal is available on the I O connector Data transfer ready In read mode this signal is high when data is available to be read In write mode this signal is high when the external device is ready to receive the data The status of this signal is available in the STAT register This signal is not available on the I O connecto
136. ss remove the plastic cover on U61 press each switch to the desired position verify that each switch is completely pressed down and replace the plastic cover Make a note of the new AT DIO 32F base I O address for use when configuring the AT DIO 32F software a form is included for you in Appendix E Table 2 3 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting National Instruments Corporation 2 5 AT DIO 32F User Manual Configuration and Installation Chapter 2 Table 2 2 Default Settings of National Instruments Products for the PC AT A2150 None None 120 hex AT AO 6 10 Channel 5 Lines 11 12 1C0 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None None 120 hex AT GPIB Channel 5 Line 11 2CO hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Lines 5 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex AT MIO 64F 5 None None 220 hex GPIB PCII Channel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 02E1 hex GPIB PCIII Channel 1 Line 7 280 hex Lab PC Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time AT DIO 32F User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 3
137. ssary to program the many modes of the AT DIO 32F Note If you plan to use a programming software package such as NI DAQ or LabWindows with your AT DIO 32F board you need not read this chapter Register Map The register map for the AT DIO 32F is shown in Table 4 1 This table gives the register name the register address the type of the register read only write only or read and write and the size of the register in bits National Instruments Corporation 4 1 AT DIO 32F User Manual Programming Chapter 4 Table 4 1 AT DIO 32F Register Map Configuration and Status Register Group CFG1 Register CFG2 Register CFG3 Register CFG4 Register STAT Register CNTINTCLR Register DMACLRI Register DMACLR2 Register Digital I O Port Register Group PORT A Register PORT B Register PORT C Register PORT D Register RTSI Bus Register Group RTSISHFT Register RTSISTRB Register Counter Register Group CNTR Register CNTR2 Register CNTR3 Register CNTRCMD Register AT DIO 32F User Manual 4 2 Write only Write only Write only Write only Read only Write only Write only Write only Read and write 8 bit or 16 bit Read and write 8 bit Read and write 8 bit or 16 bit Read and write 8 bit Write only Write only Read and write Read and write Read and write Write only National Instruments Corporation Chapter 4 Programming Register Sizes Two different transfer sizes can be used for read and write oper
138. t o ma Vin VoctotV E EMNTUT SEN NN MN TIN a a 1 0 Capacitance M pins returned to Vss 4 A C CHARACTERISTICS Ta Q C to 70 C Voc 5V 10 GND OV Bus Parameters 1 READ CYCLE gp ee eS n CSsuseBeoeRD 1 o of Jof frs ma AddressHoldTimeafterADT o o lof J m tan AD Putse width 150 ap Data Detay trom address 220 220 185 ms DEED MERKEN NEN tv Command Recovery Time 200 200 ts ms NOTE 1 AC timings measured at Voy 20V Vo 0 8V O National Instruments Corporation D 19 AT DIO 32F User Manual Intel Data Sheet Appendix D intel f 8254 A C CHARACTERISTICS 74 0 C to 70 C Voc 5V x 1096 GND OV Continued WRITE CYCLE eae Tae in wax win wax Mm wax Lus aessuese WR oe 9 Cien S samo ereas o o oi ia Adetoss Hod Time aterWA o o 9 mw Lum Wimmewan aso paso ts e Mow Data Soup Tmo Bere WA T 3m m 5 ms iwo Dated tineatermmt o 9 o Mav commandReooveyTine 200 a0 3 CLOCK AND GATE Symbol Parameter Fux oora ae oc s oc 00 oc sw Fe Hion pasewan me oom ao ns em towPucewen eo oo som ns a 2 s Fe eram m ten Gato wanvign 39 lol oj h Fw
139. t Bit Map Not applicable no bits used AT DIO 32F User Manual 4 20 National Instruments Corporation Chapter 4 Programming Digital I O Port Register Group The four registers making up the Digital I O Register Group monitor and control the AT DIO 32F digital I O lines There are four 8 bit ports on the AT DIO 32F These ports are grouped so that either 8 bit or 16 bit operations can be performed Bit descriptions for the registers making up the Digital I O Port Register Group are given on the following pages National Instruments Corporation 4 21 AT DIO 32F User Manual Programming Chapter 4 Port A Register The Port A Register contains eight bits that connect to the digital I O connector and can either be read from or written to Address Base address 06 hex Type Read and write Word Size 8 bit or 16 bit Bit Map 7 6 5 4 3 2 1 0 When Port A is configured as a write port writing data to this register latches or stores the data into Port A and sends the data out on Port A on the digital I O connector Reading Port A when it is in write mode returns the value that is currently driven on the port If the DBLBUFA bit in the CFG1 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQI level or pulse is received During an active REQ level or pulse the data is dumped to the I O connector When Port A is configured as a rea
140. t 4 9 INVRQI bit 4 6 INVRQ bit 4 9 I O channel control circuitry 3 2 I O connector electrical specifications input signal 2 16 A 1 output signal 2 16 A 1 pin descriptions 2 13 B 1 theory of operation 3 4 I O signal rating 2 16 I O transfers programmed 4 43 to 4 44 AT DIO 32F User Manual J jumper and switch settings base I O address and base I O address space chart 2 7 base I O address selection 2 4 to 2 7 default settings 2 1 default settings for National Instruments products 2 6 DMA channel 2 7 to 2 9 factory settings for chart 2 2 interrupts 2 9 to 2 10 RTSI bus clock 2 11 K kit contents 1 2 L LabWindows software 1 3 leading edge mode See handshaking level mode See handshaking LPULSEI bit 4 14 LPULSE2 bit 4 14 LRESETI bit 4 6 LRESET2 bit 4 9 M Mode 0 programming 4 38 Mode 1 programming 4 38 to 4 39 MODE lt 2 0 gt bit 4 36 MODESEL 2 0 bit 4 34 module racks connecting C 10 to C 11 N NI DAQ for DOS Windows LabWindows 1 3 NULL bit 4 36 National Instruments Corporation O onboard counters pattern generation 4 49 to 4 52 theory of operation 3 3 operating environment specifications A 2 optional equipment 1 4 optional software LabWindows 1 3 OUT bit 4 36 OUT bit 4 7 OUT signal 2 14 OUT 2 bit 4 10 OUT2 signal 2 14 output signal specifications 2 16 A 1 P parts locator diagram 2 3 pattern generation using ext
141. ta lines has been read The polarity of this signal is configured by the INVACKI bit in the CFGI Register Input handshaking request line for Group 2 When the AT DIO 32F is in write mode the external device should activate this signal to indicate that it is ready to receive data When the AT DIO 32F is in read mode the external device should activate this signal if data is available to be read on the data lines The polarity of this signal is changed by the INVRQ2 bit in the CFG2 Register 2 14 National Instruments Corporation Chapter 2 Pins 22 20 18 9 16 1 8 17 19 21 23 25 26 28 30 32 34 Signal Names OUT2 IN2 ACK2 DIOC lt 0 7 gt DIOD lt 0 7 gt GND National Instruments Corporation Configuration and Installation Description continued Extra output signal 2 This additional output signal can be connected to extra control lines and is controlled by the OUT2 bit in the CFG2 Register Extra input signal 2 This additional input signal is pulled up to 5 V by an onboard resistor The status of this signal can be obtained by reading the IN2 bit in the STAT Register This input signal can be used as an extra input signal line or as an external enable signal of Counter 2 of the board Output handshaking acknowledge signal for Group 2 When the AT DIO 32F is in write mode this signal becomes active when data has been written to the data lines When the AT DIO 32F is
142. ter 4 19 B 3 DMACLRQ2 Register 4 20 B 3 overview 4 4 STAT Register 4 16 to 4 17 B 3 Counter Register Group CNTRI Register REQI generator 4 30 B 4 CNTR2 Register REQ2 generator 4 31 B 4 CNTR3 Register timebase generator 4 32 B 5 CNTRCMD Register 4 33 to 4 36 B 5 overview 4 29 description 4 3 Digital I O Port Register Group overview 4 21 Port A Register 4 22 B 3 Port B Register 4 23 B 3 Port C Register 4 24 B 4 Port D Register 4 25 B 4 Read Back command B 5 D 9 to D 10 register map 4 1 to 4 2 AT DIO 32F User Manual Index RTSI Bus Register Group overview 4 26 RTSISHFT Register 4 27 B 4 RTSISTRB Register 4 28 B 4 sizes of 4 3 status byte B 5 REQ signal 2 17 REQI bit 4 17 REQ signal 2 14 REQ bit 4 17 REQ signal 2 14 REVC bit 4 15 RTSI bus clock configuration 2 10 to 2 11 RTSI bus interface default settings chart 2 2 programming 4 53 to 4 55 theory of operation 3 9 RTSI Bus Register Group overview 4 26 register map 4 2 RTSISHFT Register 4 27 B 4 RTSISTRB Register 4 28 B 4 RTSI bus switch programming control patterns 4 54 initializing 4 55 overview 4 53 switch signal connections 4 54 RTSISHFT Register 4 27 B 4 RTSISTRB Register 4 28 B 4 RW lt 1 0 gt bit 4 36 RWSEL lt 1 0 gt bit 4 33 to 4 34 S SETACKI bit 4 7 SETACK2 bit 4 10 signal connections descriptions of 2 14 to 2 15 I O connector pin description 2 13 RTSI bus switch 4 54
143. ter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to NOTE the highest count either FFFF hex for binary count d E ponti to 216 for binary counting and 104 for ing or 9999 for BCD counting and continues count ng ing Modes 2 and 3 are periodic the Counter reloads Figure 22 Minimum and Maximum Initial Counts poses ee the initial count and continues counting 6 41 AT DIO 32F User Manual D 18 National Instruments Corporation Appendix D Intel Data Sheet intel 8254 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso i jute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 Cto 150 C functional operation of the device at these or any Voltage on Any Pin with other conditions above those indicated in the opera Respect to Ground Q 5Vto 7v POnal sections of this specification is not implied Ex posure to absolute maximum rating conditions for Power Dissipation uique vn e a Y s Bord 1W extended periods may affect device reliability D C CHARACTERISTICS 7T 0 C to 70 C Voc 5V 10 Units Cond vu wttowvotage os os v ver input righ vonage 20 voros v SSS Cva outputtowvotage os v 729m Vou outputhigh votage 24 V tow 400 m inputtoad Curen
144. ternal signal is active high pulse write hex 0638 to the CFGI Register If the external signal is active low pulse write hex 0678 to the CFG1 Register 3 Write hex A400 to the CFG3 Register 4 Write the first pattern to Port A This operation stores the pattern in the write buffer of the port 5 When REQ is received the first pattern loaded in the write buffer of the port is transferred to the output buffer of the port therefore the first pattern is available on the digital I O connector 6 The received REQI sets the DRDYI bit Write the next pattern to Port A 7 The next REQI received dumps the second pattern to the digital I O connector The sequence continues until an LRESET1 is received The programming steps are similar for configuring Group 2 for pattern generation with an external signal Programming the RTSI Bus Interface The RTSI switch connects signals on the AT DIO 32F to the seven RTSI bus trigger lines The RTSI switch has seven pins labeled A lt 6 0 gt connected to AT DIO 32F signals and seven pins labeled B lt 6 0 gt connected to the seven RTSI bus trigger lines The signals connected to each pin are given in Table 4 6 RWGRP1 and RWGRP2 are board generated active low pulse signals that are 250 nsec to 500 nsec wide RWGRP1 is the read write signal for Port A and Port B RWGRP2 is the read write signal for Port C and Port D Table 4 6 RTSI Switch Signal Connections RTSI Switch Pin Signal Name Signal D
145. that describe each handshaking mode are shown later in this chapter After start up or LRESET the handshaking circuitry is in the INIT state During a read transfer DRDY is set once a REQ is received DRDY remains set until the data is read from the selected ports During a write transfer DRDY is set as soon as the group s WRITE bit is set indicating that the group is in write mode DRDY remains set until data is written to the selected ports In the Figures 3 3 and 3 4 REQ and ACK are shown as active high logic that is INVRQ and INVACK are cleared Level Mode In level mode once the data is read or written TDELAY begins TDELAY is the data settling delay that is programmed by setting bits in CFG1 or CFG2 After the delay ACK is sent to the digital I O connector The circuitry waits for REQ to go low When REQ is received again ACK is cleared then DRDY is set again and the cycle continues Figure 3 3 shows a read transfer in level mode LRESET or Power On When REQ asserted When REQ asserted When REQ unasserted Figure 3 3 Level Mode Read National Instruments Corporation 3 5 AT DIO 32F User Manual Theory of Operation Figure 3 4 shows a write transfer in level mode LRESET or Power On When REQ asserted Continue sending ACK When REQ unasserted After TDELAY Chapter 3 When WRITE bit and DIOxEN bit for group are set After data written Figure 3 4 Level Mode Write AT DIO 32
146. the 8254 is very flexible Only two conventions need to be remem bered 1 For each Counter the Contro Word must be writ ten before the initial count is written 2 The initial count must follow the count format specified in the Contro Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A4 Ao inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in Struction sequence is required Any programming sequence that follows the conventions in Figure 7 is acceptable A new initial count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count rnust follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count AT DIO 32F User Manual Intel Data Sheet intel 8254 Appendix D Control Word Counter 0 LSB of count Counter 0 MSB of count Counter 0 Control Word Counter 1 LSB of count Counter 1 MSB of count Counter 1 C
147. the DMA operation for Group 1 If DMACH is cleared the DMA channel selected for Group 1 is in use If DMACH is set the DMA channel selected for Group 2 is in use The DBLDMA bit selects the double DMA mode in which DMA transfers for Group 1 switch between the two DMA channels 14 CNTINT Counter 3 Interrupt Status Bit This bit reflects the status of the Counter 3 interrupt CNTINT is set whenever the CNTINTEN bit in the CFG3 Register is set and a rising edge on Counter 3 output is detected CNTINT is cleared by writing to the CNTINTCLR Register 13 X Don t Care Bit 12 TRANS32 16 Bit 32 Bit Transfer Indicator Bit This bit is set when Group 1 and Group 2 are configured to transfer 32 bit data Otherwise TRANS32 is cleared See the 32 Bit Transfers section at the end of this chapter for more information about 32 bit transfer mode 11 INI Extra Input Line 1 Bit INI is pulled up to 5 V and is connected to input line INI on the digital I O connector IN1 can be used as an extra input line INI is ANDed with CNT1EN and therefore can also be used as an external control signal to enable disable Counter 1 AT DIO 32F User Manual 4 16 National Instruments Corporation Chapter 4 Bit 10 National Instruments Corporation 4 17 Name DMATC2 DMATCI DRDYI REQI ACKI IN2 DRDY2 REQ2 ACK2 Programming Description continued DMA2 Terminal Count Indicator Bit This bit reflects the status of DMA for the Gro
148. the RTSI bus trigger lines To program the RTSI switch follow these steps 1 Calculate the 56 bit pattern based on the desired signal routing a Clear the OUTEN bit for dll input pins and for all unused pins b Specify the signal source pin for all output pins by setting bits S2 through SO to the source pin number Set the OUTEN bit for all output pins 2 Fori 0 to 55 follow these steps a Copy bit i of the 56 bit pattern to bit 0 of an 8 bit temporary variable b Wirite the temporary variable to the RTSI Shift Register 8 bit write 3 Write 0 to the RTSI Strobe Register 8 bit write This operation loads the 56 bit pattern into the RTSI switch At this point the new signal routing goes into effect Step 2 can be performed by writing the low order 8 bits of the 56 bit pattern to the RTSI Shift Register then shifting the 56 bit pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Shift Register is used The higher order bits are ignored Initializing the RTSI Bus Switch Use the following sequence to initialize the RTSI bus switch This sequence configures all signals to the RTSI bus switch as read signals rather than drive signals Drive signals may cause undesirable results All writes are 8 bit write operations 1 Load the RTSI switch with the program data pattern For i 0 to 55 decimal write 0 to the RTSI Shift Register base address 10 hex
149. the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts National Instruments Corporation Appendix D Intel Data Sheet intel 8254 Hl Lp HIEILDLHHEHEHHEHHEH CWs 16 138 5 GATE ap E HMNBEBHHHUIBETHIIT CWas16 LSB 4 HHHRDHHHHHHBRHHITEN NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 National Instruments Corporation D 15 AT DIO 32F User Manual AT DIO 32F User Manual Intel Data Sheet intel Appendix D 8254 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Contro Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an CILICIJE CW x18 LSB 23 CWz18 LSBx3 initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two
150. the second buffer of the port which dumps the data to the digital I O connector Double buffering is usually used for pattern generation If DBLBUEFD is cleared Port D is a single buffer that is data written to the port is immediately dumped to the digital I O connector When Port D is configured as an input port and DBLBUFD is set an active level or edge of a REQ signal latches the data into the input buffer of Port D A read operation reads the data in the buffer instead of the I O connector If DBLBUFD is cleared the port is transparent that is a read operation reads the data on the I O connector Version Compatibility Bit Writing zero to this bit causes a Revision C board to function like a Revision B board Therefore the Revision C board is compatible with Revision B board software Writing one to this bit adds the Revision C feature to the board This bit is automatically cleared at startup National Instruments Corporation 4 15 AT DIO 32F User Manual Programming Chapter 4 STAT Register The STAT Register contains 13 bits that reflect the handshaking state of Group 1 and Group 2 Address Base address 00 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REQ ACK IO O X DRDY2 REQ ACK2 Bit Name Description 15 DMACH Current DMA Channel Bit If the DBLDMA bit in the CFG3 Register is set the DMACH bit indicates which DMA channel is currently in use for
151. ting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro gramming operations of other Counters may be in serted between them Another feature of the 8254 is that reads and writes of the same Counter may be interleaved for exam ple if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back Co
152. trol Circuitry Circuitry o g g G p O Q lt Q amp Interrupt Control Circuitry Control Circuitry Figure 3 1 AT DIO 32F Block Diagram National Instruments Corporation 3 1 AT DIO 32F User Manual Theory of Operation Chapter 3 The AT DIO 32F board is a full size 16 bit PC I O channel adapter The PC I O channel consists of a 24 bit address bus a 16 bit data bus a DMA arbitration bus interrupt lines and several control and support signals Address Decoder The PC I O channel has 24 address lines the AT DIO 32F uses ten of these lines to decode the board address Therefore the board address range is hex 000 to 3FF Address lines SA5 through SA9 are used to generate the board enable signal SAO through SA4 are used to select the onboard registers Bus Transceivers The bus transceivers control the sending and receiving of the data lines to and from the PC I O channel PC I O Channel Control Circuitry This circuitry monitors and transmits the PC I O channel control and support signals The control signals identify transfers as read or write configuration or I O and 8 bit or 16 bit A support signal is returned to the PC I O channel from the AT DIO 32F to indicate the size of the current data transfer Configuration and Status Registers The AT DIO 32F has seven configuration registers and a status register Four 16 bit configuration registers CFG1 CFG2 CFG3 and CFG4 are used to program al
153. trol the Group 2 I O mode and the handshaking mode Address Base address 02 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 DMAEN2 Group 2 DMA Enable Bit When DMAENG is set DMA is enabled for Group 2 handshaking A DMA request is asserted when DRDY2 is set 14 INTEN2 Group 2 Interrupt Enable Bit When INTEN2 is set interrupts are enabled for Group 2 handshaking An interrupt request is asserted when DRDY2 is set 13 11 T2S lt 2 0 gt Group 2 Data Transmission Delay TDELAY72 Bit These bits select the data settling delay used by Group 2 handshaking Long cable lengths or special handshaking specifications may require a data settling delay to ensure proper data transmission T2S2 T2S1 T2S0 TDELA Y2 nsec 0 0 0 0 0 1 0 1 0 0 1 1 I 0 0 1 0 1 1 1 0 1 1 1 AT DIO 32F User Manual 4 8 National Instruments Corporation Chapter 4 Bit Name 10 DIODEN 9 DIOCEN 8 LRESET2 7 X 6 INVRQ2 5 DBLBUFC 4 PULSE2 3 EDGE2 Programming Description continued Port D Handshaking Enable Bit When DIODEN is set Port D is enabled for handshaking Port C Handshaking Enable Bit When DIOCEN is set Port C is enabled for handshaking Local Reset for Group 2 Bit Setting and then clearing LRESET2 resets the handshaking circuitry for Group 2 Handshaking configuration bits must be reset after an LRESET2 Don t Care Bit This bit is unused o
154. um ratings D 19 A C characteristics D 19 to D 20 block diagram D 2 clock and gate D 20 control word format D 7 control word register D 4 counter latch command D 8 counters D 4 to D 6 D 18 block diagram of D 5 D C characteristics D 19 functional description of D 3 to D 6 gate programming D 18 mode definitions Mode 0 interrupt on terminal count D 11 Mode 1 hardware retriggerable one shot D 11 Mode 2 rate generator D 11 Mode 3 square wave mode D 11 to D 15 AT DIO 32F User Manual Index Mode 4 software triggered strobe D 16 Mode 5 hardware triggered strobe retriggerable D 17 null count operation D 10 operational description of D 6 to D 18 pin description for D 3 programming D 6 to D 18 read back command D 9 to D 10 read operations D 8 to D 9 read write logic D 4 square wave mode D 11 to D 15 system interface D 6 waveforms D 21 to D 22 write operations D 7 INTENI bit 4 5 INTEN2 bit 4 8 interface compatibility 1 1 to 1 2 interrupt control circuitry 3 10 interrupt handling condition and status chart 4 45 control circuitry 3 10 Counter 3 4 47 to 4 48 DRDYI1 example 4 45 DRDY2 example 4 46 Group 1 DMA terminal count example 4 46 Group 2 DMA terminal count example 4 47 overview 4 44 interrupt level configuration 2 9 to 2 10 default jumper settings 2 9 default settings chart 2 2 default settings for National Instruments products 2 6 INVACKI bit 4 6 INVACK2 bi
155. unter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when Ay Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word AT DIO 32F User Manual sae 0 RD 1 WR 0 Ds Ds D 2s 2z a Soise iari be latched SC1 Sco _Counter 0 1 2 Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility D8 with future intel products Figure 9 Counter Latching Command Format O National Instruments Corporation Appendix D intel Intel Data Sheet _ 8254 The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting coun
156. up 2 terminal count If this bit and TCINTEN2 in the CFG3 Register are both set then a DMA terminal count interrupt has occurred This bit is cleared by writing to the DMACLR2 Register DMAI Terminal Count Indicator Bit This bit reflects the status of DMA for the Group 1 terminal count If this bit and TCINTENI in the CFG3 Register are both set then a DMA terminal count interrupt has occurred This bit is cleared by writing to the DMACLRI Register Group 1 Data Transfer Ready When Group is in read mode and enabled for handshaking DRDYI is set when data can be read at the I O connector When Group 1 is in write mode DRDY1 is set when the external device is ready to receive the data Group 1 Handshaking Request Status REQI reflects the status of the Group 1 handshaking request line as seen at the digital I O connector Group 1 Handshaking Acknowledge Status Bit ACKI reflects the status of the Group 1 handshaking acknowledge signal as seen at the digital I O connector Extra Input Line 2 IN2 is pulled up to 5 V and is connected to input line IN2 on the digital I O connector IN2 can be used as an extra input line IN2 is ANDed with CNTEN2 and therefore can also be used as an external control signal to enable disable Counter 2 Revision C ID Bit If this bit is cleared the board is a Revision C board If this bit is set the board is a Revision B board Don t Care Bit Group 2 Data Transfer Ready When Group 2 is
157. utw word fp Put word in file End while Put final word received containing an EOF into the file putw word fp Put char and EOF in file putw word stdout Echo word to screen AT DIO 32F User Manual C 8 National Instruments Corporation Appendix C Application Notes printf nAn End of File has been received n fclose fp End get_main Get the 16 bit word from the AT DIO 32F in word int wd while data_in_rdy Wait until data is ready wd inpw PORTA return wd Return 16 bit data End in word Return non zero value if data is ready to be read data in rdy return inpw STAT1 amp 0x0100 Return value of DRDY1 bit End data in rdy RR KK KK KKK kk ko ke ke ke ke k ke k k Modified Unix Commands XOKCkckckck kok ck ko ke x ke ke e e e e x x x getwd is a modification of the unix h function getw The returned parameter is the only change in the unix function getwd will return an int EOF OxFFFF if either the first or second byte read was an EOF The function getwd however returns the following OxFFFFE int EOF if the high byte is an EOF char Ox FF a char EOF in the low byte if a valid char was read in the high byte Ose sided a valid char in the high and low byte if no EOF was read in either foe ky getwd who FILE who
158. ved and a rising edge on Counter 3 received Each one of these interrupts is individually enabled and cleared See Chapter 4 Programming for additional information about programming with interrupts DMA Control Circuitry Each handshaking group can be assigned a separate DMA channel for 16 bit data transfer and each group has a DMA enable bit DMAEN When DMA is enabled the AT DIO 32F sends a DMA request to a port that is ready to receive data during a write transfer or to a port that is ready to read data during a read transfer DMA channels 5 6 and 7 of the PC I O channel are available for such transfers AT DIO 32F User Manual 3 10 National Instruments Corporation Chapter 3 Theory of Operation RTSI Bus Interface The AT DIO 32F is interfaced to the National Instrument RTSI bus The RTSI bus has seven trigger lines and a system clock line All National Instruments AT Series boards that have RTSI bus connectors can be wired together inside the PC to share these signals The RTSI bus RTSICLK line can be used to send a 10 MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus MYCLK is the system clock used by the AT DIO 32F The RTSI switch is a National Instruments custom integrated circuit that acts as a seven by seven crossbar switch Pins B lt 6 0 gt are connected to the seven RTSI bus trigger lines Pins A lt 6 0 gt are connected to seven signals on the board The
159. will continue from there Ininininie ileitieimisl CWz1A LS8 3 fie a el ea D 17 0 0 pa 0 9 o FF FE 231164 12 AT DIO 32F User Manual Intel Data Sheet Appendix D Operation Common to All Modes PROGRAMMING When a Control Word is written to a Counter ali Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip fiop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Coun
160. with BCD readouts and or controls e Opto isolated solid state relays and I O module mounting racks With the AT DIO 32F the PC can serve as a digital I O system controller for laboratory testing production testing and industrial process monitoring and control National Instruments Corporation 1 1 AT DIO 32F User Manual Introduction Chapter 1 What Your Kit Should Contain The contents of the AT DIO 32F kit part number 776246 01 are listed as follows Kit Component Part Number AT DIO 32F board 180735 01 AT DIO 32F User Manual 320147 01 NI DAQ software for DOS Windows LabWindows with manuals 776250 01 NI DAQ Software Reference Manual for DOS Windows LabWindows 320498 01 NI DAQ Function Reference Manual for DOS Windows LabWindows 320499 01 If your kit is missing any of the components contact National Instruments Your AT DIO 32F is shipped with the NI DAQ software for DOS Windows LabWindows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code NI DAQ comes with language interfaces for Professiona
161. wo extra input lines and two extra output lines The status of the input lines IN1 and IN2 can be read from the STAT Register The output lines OUT1 and OUT2 are controlled by bits in the CFG1 and CFG2 Registers These lines are useful for reading and sending status or control information needed in addition to the handshaking lines These extra lines are independent of the group designations Input Data Latch When an I O port is configured as an input port read mode and the corresponding DBLBUF bit is cleared reading the port returns the current data on the I O lines whether or not handshaking is enabled When an I O port is configured as a double buffered input port that is the corresponding DBLBUF bit is set and the handshaking is enabled the REQ signal latches the data into the port e Level Mode In either the active high or active low level mode data is latched into the port on the leading edge of REQ until the REQ is inactive e Pulse Mode The active edge leading edge or trailing edge of REQ latches data into the port until the data in the input buffer is read Interrupt Handling Five conditions can generate an interrupt DRDYI set DRDY2 set Group 1 DMA terminal count received Group 2 DMA terminal count received and a rising edge on Counter 3 received Each of these conditions has an interrupt enable bit in a CFG Register and an interrupt status bit in the STAT Register The interrupt condition is enabled to generate inter

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