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UM10741 Fm+ development kit OM13320

1. 3V3 5V 3V3 H R9 Q4 ES R10 10kQ SI2325DS 10 INT R8 RESET 8200 D20 LTST C170CKT RED INT LED GND Fig 48 INT and RST indicators circuit os EA SI2325DS R7 820 Q D19 gt LTST C170CKT RED RSTLED GND aaa 012048 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 36 of 61 NXP Semiconductors UM10741 Fm development kit OM13320 Fig 49 INT and RST indicators section 020 tae we REMN Q4 015 rin 8 fe Q5 R29 RBA any INSIM KIN 06 07 N ota Mets Mo cy aaa 012296 5 12 Prototype area Additional circuits may be required to for an application beyond the intended scope of the Fm Development Board OM13260 For example using different value pull up resistors than those supplied or other circuit experiments The prototype area is available and consists of pads and holes on a 100 mil 2 54 mm grid Power for these components is made available at several connector points CN15 is ground CN21 is 3 3 V and CN22 is 5 V See Figure 50 and Figure 51 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 37 of 61 NXP Semiconductors U M1
2. T Bus UM10741 Fm development kit OM13320 Rev 1 1 April 2014 User manual Document information Info Content Keywords I2C bus Fm development tool PCA9672 PCA9955 Abstract User manual for the Fm development board OM13260 kit OM13320 NXP Semiconductors U M1 0741 Fm development kit OM13320 Revision history Rev Date Description 1 0 20140401 User manual initial release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 2 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 1 Introduction The Fm Development Kit OM13320 is intended for several different tasks from a hands on introduction understanding and use of the I C bus Inter Integrated Circuit bus to 12C device evaluation and as a simple product demonstration platform for trade shows and sales pitches The kit has a core Printed Circuit Board PCB assembly and three add on PCBs Other PCBs are available for advanced use or to support newly released I C bus components as they are introduced to the market The Fm Development Kit OM13320 is supported by a Graphics User Interface GUI softw
3. 1 April 2014 20 of 61 NXP Semiconductors U M1 0741 5 3 3 UM10741 Fm development kit OM13320 aaa 012278 Fig 20 Bus1 pull ups section Table 3 Bus pull up resistors Strength Position Value Bus1 SCL Bus1 SDA 2 SCL Bus2 SDA LOW A 1 1 KQ R16 R13 R26 R23 MID B 634 Q R15 R12 R25 R22 HIGH 324 Q R14 R11 R24 R21 LED driver slave PCA9955 Bus1 is also used to control the LED Driver PCA9955 IC6 The LED Driver has constant current outputs and is directly connected to the LEDs without customary series resistors The LEDs are powered directly from the 5 V supply thus avoiding further power dissipation in the 3 3 V linear regulator IC1 The sixteen channels drive eight LED clusters consisting of four White LEDs LED12 LED15 and four RGB LED clusters LEDO LED11 The maximum current available for each channel is set by R35 and the variable resistor R36 The LEDs use the PCB top metal for heat dissipation the LED driver is in the HTSSOP28 package has a thermal pad ground connection and operates from the main 3 3 V supply See Figure 21 and Figure 22 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 21 of 61 NXP Semiconductors UM10741 Fm development kit OM13320 3V3 Fig 21 Bus1 LED driver 16 channel 3V3 IC6G
4. T 5V I2C bus 1 PULL UP I2C bus 1 RESISTORS 9672 8 channel GPIO aaa 012039 Fig 10 Fm development board bus structure UM10741 An I C bus requires a Master and one or more Slaves The two bus signals clock SCL and data SDA are wired OR and require pull ups to a DC power supply Two similar but separate I C buses each support one Master and at least one Slave device on the board The two buses may be linked by either a Bus Buffer Board OM13398 supplied in the kit or a wire jumper at the Port E connector CN12 The signals from both buses are available simultaneously at each of four connectors Port A through Port D CN1 through CN4 respectively These are intended for attachment of accessory daughter cards which will be made available as future I C bus devices are released The size of the pull up resistors can be changed by moving shorting jumpers JP1 JP2 JP11 and JP12 providing selection of Low Med and High resistor values scaled to the Fm I C bus drive strength When both buses are joined by a jumper wire the pull ups are effectively in parallel and have one half the stated resistance values Operating voltage of the 2 depends upon the shorting jumpers JP13 and JP23 that select either 3 3 V or 5 V connected to the pull up resistors Compliant I2C bus devices can tolerate 5 5 V maximum regardless of the device operating voltage All information provided in this document is s
5. The actual voltage is seldom 5 V due to cable losses plus an additional drop in a series connected diode used to OR the two inputs Whichever has the highest voltage has priority A shunt Zener diode 6 2 V protects the board from reverse polarity and overvoltage at the DC Power connector CN6 To aid in understanding digital signal levels on the board two logic probe circuits are provided These are buffered LEDs Green D6 and Red D7 which light if their respective inputs CN11 are grounded Two global digital signal nets called INT interrupt and RST reset connect all 12 devices on the board and also the Port A Port E Daughter Card connectors These are also connected to the Master MCU IC5 on Bus 1 the Master Bus Controller IC4 and the LPC Xpresso module Remark The 12 global Reset is not the same as the MCU Reset Resetting the MCU will only reset the I C bus if the MCU firmware is intended to create a global reset The test points provide monitoring of interrupts usually generated by 1 C bus Slaves and software reset of Fm class I C bus devices that have that feature Additional buffered LEDs are provided D19 RST and D20 Interrupt on the Fm Development Board OM13260 for visual indication Various MCU and LPC Xpresso signals are made available through additional connectors These include a serial Port CN7 with EIA232 voltage level translation IC2 and SPI Bus signals SPO CN9 and SP1
6. CN8 from the LPC Xpresso module together with SPI Bus SP2 CN16 from the MCU IC5 A prototyping area is provided for solder connection of components that may be required by an application circuit beyond this board s design Power supplies and other signals are readily available All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 14 of 61 NXP Semiconductors U M1 0741 UM10741 5 2 5 2 1 Fm development kit OM13320 On the Fm Development Board OM13260 V3 0 there is an LED Blinker device PCA9901 IC3 and LED indicator 010 while not strictly an 12 device as it uses a one wire protocol it belongs to the NXP I C bus product portfolio Remark The PCA9901 will be made obsolete and will not be present on future versions of the Fm Development Board OM13260 The operation of the Fm Development Board OM13260 is greatly enhanced by third party tools not supplied in the kit that may be attached to either I C bus through dedicated connectors Bus1 CN17 and Bus2 CN18 labeled TESTER Circuit description The schematic diagram has multiple sheets For clarification only fragments of the schematic are shown here The full schematic should be downloaded if required The following pages are divided in to several sections covering the power supply USB interface Bus1 Bus2 and support circuits Power
7. 0741 Fm development kit OM13320 5V 1 9 CN22 4 gt CN22 3 1 CN22 2 CN22 1 3V3 1 CN21 4 gt CN21 3 gt CN21 2 gt CN21 1 gt CN15 4 1 9 CN15 3 1 9 CN15 2 1 9 CN15 1 GND UTILITY POWER aaa 012049 Fig 50 Prototype area circuit aaa 012297 Fig 51 Prototype area section UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 38 of 61 NXP Semiconductors UM10741 UM10741 Fm development kit OM13320 5 13 LED blinker PCA9901 On the Fm Development Board OM13260 V3 0 there is an LED Blinker device PCA9901 IC3 and LED indicator D10 While not strictly an I C bus device as it uses a one wire protocol it belongs to the NXP I C bus product portfolio Remark The PCA9901 will be made obsolete and will not be present on future versions of the Fm Development Board OM13260 Refer to the PCA9901 data sheet for details of this device Note that it is not connected to either 12 Bus on the Fm Development Board OM13260 It is connected to the LPC Xpresso module PIO 0 7 and that module must be present and programmed to drive the PCA9901 device See Figure 52 and Figure 53 GND ISET R19 WV D10 47 KQ X LTST C170CKT RED GND GND Fig 52 LED blinker PCA9901 PCA9901DP
8. 2 IC6G 1 GND10 GND9 JP5 1 2 SDA1 GND8 JP5 2 3 bs osa SCL1 35 GNp7 JP5 3 lt Es 4 RESET GND6 5 GND5 GND LEDO 6 rc LED15 GND 22 onos Iset f jj pena R36 t ues woo ue al mee 30 5 2 PCA9955 Address OxCOh OxDOh 29 GND1 GND 9955 GND Lep4 1011 18 LED GND ics grum P PCA9955PW LED O 11 PCA9955 16 ch CONSTANT CURRENT LED DRIVER LED 12 15 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED7 LED8 LED9 LED10 LED11 TADUR lt 0116 X D11B A D12R D12G D12B INT v VA D13R 1 D13G D13B IN IN D14R D14G INT INT INT D14B RGB LEDs 5V 4 LED12 a LED13 NT g Ei LED14 E 3 LED15 A 5V 1745 WHITE LEDs L c5 22 pF 16 V aaa 011879 UM10741 Fig 22 Bus1 LED driver 16 channel section H P e an P o 012279 Operation of all sixteen LEDs at maximum current will overheat the LED driver which is protected by an internal thermal limiter The device will shut down and recover when the temperature has fallen When powered from the USB port CN5 the USB Host is typically limited to 500 mA and it will shut down before the LEDs reach maximum current Operation from an external DC power s
9. 74 Fm development board OM13260 connector CN3 The connector on the Bridge Board OM13399 matches the Port connectors on the Fm Development Board OM13260 See Figure 74 A Bridge Board OM13399 can be attached to any Port A Port D inclusive It cannot be connected to Port E due to mechanical arrangement of the Port E connector The Development Board has two separate I C buses Bus1 and Bus2 and one of these is selected by two jumpers JP2 for SCL and JP3 for SDA All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 53 of 61 NXP Semiconductors U M1 0741 UM10741 8 2 2 8 2 3 Fm development kit OM13320 Power supply select JP1 and JP4 VDD PWR NN 0 tot t lol 6565 8 Q Q ial 0 e gt io SEL POWER SOURCE aaa 012149 Fig 75 Power supply selector There are two power sources available to the Bridge Board OM13399 depending upon whether it is connected to the Fm Development Board OM13260 or powered by a third party tool see Section 9 The Tester socket provides 5 V and the Fm Development Board 1 3260 provides both 3 3 V or 5 V Jumper JP1 selects the source of the 5 V power JP4 selects either 3 3 V or 5 V as needed Remark When the Bridge Board OM13399 is not attached to the Fm Development Board and powered
10. D8 which is set to blink at about one per second 3V3 R20 R17 8200 8200 D8 D9 LTST C170KGKT GRN LTST C170KGKT GRN X CONFIG AX CONNECT 24 mos USB LED 10kQ CON EN Q1 T 1 PDTA123YT USB_CONNECT 2 2 SOFTCONNECT R18 IC5G 8 1 5kQ USB_DP 14 R27 330 l DP CN5 3 USB Dm 13 R28 330 DM CN5 2 LPC134X_HVQFN32 ___ VBUS 5 CN5 1 GND s CN5 4 a Zz OO PRTR5VOU2X GND VBUS GND USB INTERFACE USB PORT aaa 011873 Fig 13 USB interface UM10741 5 3 one Bus1 5 3 1 There are two almost identical 12C buses on the Fm Development Board OM13260 called Bus1 and Bus2 These share a ground and power connection but may be operated independently Remark The bus voltage for each 12 may be different for example 3 3 V for one I2C bus 5 V for the other I2C bus Bus1 master MCU LPC1343 Microcontroller MCU LPC1343 IC5 serves as the Bus1 Master and the USB Bridge Firmware installed on the Fm Development Board OM13260 is stored in non volatile memory which has a limit of 32 The MCU may be programmed through the USB port or the JTAG connector CN 19 using Single Wire Debug SWD see Figure 14 and Figure 15 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual
11. Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 12 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the pro
12. OM13398 Bridge board OM13399 Cable USB Type A to Type B Ribbon cable 10 position bag of two Jumper wires with female terminals bag of ten Shorting jumpers bag of twenty Hardware bag of M3 screws and standoffs Box contents The Fm Development Kit OM13320 contains four PCB assemblies cables and loose hardware These should be retained in the box for future access Depending upon the desired use some of the PCB assemblies may be attached to each other either by plug connection or by stacking the GPIO PCB assemblies above the Development Board OM13260 using the supplied ribbon cables and hardware All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 5 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 3 2 Supplied PCB assemblies 3 2 1 UM10741 There are four PCB assemblies in the kit Each has a specific function and not all of them are used at the same time Fm Development Board OM13260 The large PCB Figure 2 contains two separate I C bus structures together with supporting circuitry Each bus has a bus master one or more bus slaves and user options to change the bus voltage and bus pull up resistors Adjusting these changes the operation of the buses to suit various goals In addition the two buses may be linked together to operate a one I C bus structure This can
13. Rev 1 1 April 2014 17 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 During programming or at other times it may be necessary to reset the MCU by briefly shorting JP4 see Figure 15 Remark An MCU Reset is not the same as an I C Bus Reset Resetting the MCU will not affect the I C bus unless the MCU firmware is designed to issue an 12C Bus Reset when it is reset CN19 10 SWD RESET 3V3 CN19 8 CN19 7 lt 4 4 CN19 6 A RST CN19 5 lt 100 kQ JP4 1 CN19 4 lt MCU SCEK JP4 2 supo cb CN19 1 lt I LPC SWD PROG CONNECTOR GND aaa 011874 Fig 14 MCU SWD interface aaa 012089 Fig 15 MCU SWD interface section MCU Port0 and Port1 provide most of the signals used by the Fm Development Board OM13260 see Figure 16 and Figure 17 12 Bus1 is connected to the MCU Porto via RC edge rate control networks that provide bus fall time control SCL1 R42 and C18 SDA1 R43 and C17 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 18 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 3V3 VAN LPC134X_HVQFN32 RESET PIOO 0 SWD RESET one ISP PIO0_1 CL
14. SPI connectors NT C cN16 8 SND gt CN16 6 CNIS 3 6 4 gt CN16 3 9 6 2 3 6 1 SPI 2 aaa 012046 Fig 44 SPI 2 Bus1 MCU connector aaa 012293 Fig 45 SPI 0 and SPI 1 Bus2 LPC Xpresso connectors aaa 012294 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 34 of 61 UM10741 Fm development kit OM13320 NXP Semiconductors 5 10 Logic probe Most of the I2C bus slaves produce logic signals on their input output ports It is necessary to know a logic state To facilitate this test there are two LEDs with buffers that may be used as a simple logic probe To prevent circuit loading the LEDs are buffered by FETs as shown in Figure 46 Green LED D6 is driven by FET Q2 when CN11 1 is at or near ground When CN11 1 is open or logic 1 the FET is non conducting and the LED is off Red LED D7 is driven by FET Q3 when CN11 4 is at or near ground When CN11 4 is open or logic 1 the FET is non conducting and the LED is off See Figure 47 Note that the threshold voltage Vin of the FET is 2 5 V to 4 5 V to ensure it operates correctly on both 3 3 V and 5 V logic levels The FET source is tied to 5 V and the gate must therefore be at 2 5 V or lower relative to ground to
15. aaa 012145 Fig 69 Supply select jumpers 7 2 4 Variable voltage regulator The low voltage bus bias is generated by an LDO Low Drop Out voltage regulator IC5 The output voltage is set by resistor divider R3 R4 and R5 and provides a range of 1 0 V to 3 2 V The LDO provides a Power Good signal which is pulled HIGH by R6 and buffered by Q1 When the LDO is working correctly the blue LED D2 is turned ON See Figure 69 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Rev 1 1 April 2014 50 of 61 UM10741 User manual NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 7 2 5 Connector The connector on the Bus Buffer Board OM13398 matches the Port E connector on the Fm Development Board OM13260 See Figure 70 and Figure 71 The signals are arranged to be symmetrical so that the Bus Buffer Board OM13398 can be rotated 180 causing the signals from the Fm Development Board OM13260 to flow in the opposite direction For example from Bus1 to Bus2 or from Bus2 to Bus1 when the Bus Buffer Board OM13398 is rotated in the Port E connector See Figure 71 The ability to reverse the signal flow is necessary when examining different 12 buffers or comparing one NXP device to a non NXP device CN1 14 5 SCL1 CN1 13 5 SDA2 CN1 12 2 1 CN1 11 5 RESET CN1 10 gt CN1 9 2 3
16. are connected to the two 9 position connectors and depending upon the position of JP2 and JP3 to the Fm Development Board Bus1 or Bus2 Take care to avoid double termination of the 12 buses 8 2 5 LED indicators and pull ups an QA Q a a a a gt gt gt gt 2 R1 amp R2 R3 R4 8200 amp 8200 10 kQ 10 ka is 9 ae x y NJ 01 y NJ 02 54 5 hi SCL o 2 H 1 SDA GND PWR INT gt R5 INT 10 RESET aaa 012152 Fig 78 LED indicators and pull ups Two LEDs provide indication of power D1 Green and INT interrupt status D2 Red To prevent malfunction of the I C bus if the Bridge Board OM13399 is used in manner that does not have pull up on either SCL or SDA there are weak pull ups R3 R4 These may be replaced with lower value resistors or removed as needed All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 55 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 8 3 Example using PCA9632 OM13269 012309 Fig 79 Bridge board OM13399 used to attach 9632 OM13269 The Bridge Board OM13399 supplied in the kit provides attachment of old style with a 9 pin in line non polarized connector NXP designed I2C demo boards to the F
17. be done with a two wire jumper supplied or the Bus Buffer Board OM133998 supplied See figure 3 5 Four identical ports provide access for add on boards that contain additional I C bus devices aaa 011941 Fig 2 OM13260 Fm development board PCB assembly All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 6 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 3 2 2 GPIO target board OM13303 Outputs from the GPIO devices on the Fm Development Board OM13260 and those when using GPIO daughter cards not supplied in the kit require the GPIO Target Board OM13303 Each one has eight channels of LED indicator and push button switches for user input See Figure 3 011942 Fig 3 13303 GPIO target board PCB assembly 3 2 3 PCA9617A bus buffer demo board OM13398 Bus buffers bridge two I2C bus segments which are provided on the Fm Development Board OM13260 by Bus1 and Bus2 Bus buffer daughter cards such as the PCA9617A Bus Buffer Demo Board OM13398 supplied in the kit can be installed directly on Port E CN12 See Figure 4 011943 Fig 4 13260 bus buffer PCB assembly UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 7 o
18. by the Tester the only option is 5 V 9 position connectors CN1 and CN2 CN2 1 28 CN1 1 gt 8 _ CN2 2 NSW CN1 2 5 5VS9W CN2 3 lt 3V3__ CN1 3 5 H3V3 CN2 4 3V3SW CN1 4 5 3V3SW CN2 5 SCL CN1 5 gt SL CN2 6 SND CN1 6 gt GND__ CN2 7 lt SDA CN1 7 5 DA CN2 8 hNI 8 5 INI CN2 9 RESET cn1 9 5 RESET 9POS MALE HEADER 9POS FEMALE SOCKET aaa 012150 Fig 76 9 position connectors CN1 and CN2 Two 9 position connectors are provided both carry exactly the same signals CN1 is female CN2 is male Remark These connectors are not polarized or keyed Take care to make connection correctly All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 54 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 8 2 4 Tester connector CN4 10 lt _GND_ CN4 9 lt CN4 8 lt CN4 7 lt 5V_TSTR CN4 6 CN4 5 lt CN4 4 CN4 3 lt SDA CN4 2 SND CN4 1 SCL 12C TESTER aaa 012151 Fig 77 Tester connection CN4 The 10 position 2 x 5 shrouded header connector CN4 mates with third party tools see Section 9 Only I C bus signals and available 5 V power are connected Remark The Tester s bus signals
19. fall time control SCL2 R45 and C23 SDA1 R44 and C19 See Figure 28 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 25 of 61 NXP Semiconductors UM10741 UM10741 Fm development kit OM13320 aaa 012283 Fig 27 LPC Xpresso power JP1 3V3 JP1 1 p CP on CN14 1 5 JP1 2 eus lt CN13 2 CN14 2 PWR 4 CN13 3 CN14 3 5 lt CN13 4 CN14 4 5 migo lt 3 5 CN14 5 gt MISO CN13 6 CN14 6 5 SoK CN13 7 CN14 7 5 SSNO c CN13 8 CN14 8 gt IXD C CN13 9 CN14 9 5 BEXD lt CN13 10 CN14 10 5 po CN13 11 CN14 11 gt R44 SDA2 pr CN13 12 c SDA A d D1 c CN13 13 CN14 13 D2 on 3 14 CN14 14 S SCL2A t lt CN13 15 CN14 15 gt 1000 CN13 16 CN14 16 gt C23 C19 4 CN13 17 CN14 17 5 10 pF 10 pF 4 CN13 18 CN14 18 2 03 4 CN13 19 CN14 19 5 D4 4 CN13 20 CN14 20 5 D3 lt CN13 21 CN14 21 gt D6__ GND GND ssn4 lt ON13 22 CN14 22 M 7 CN13 23 CN14 23 i A TF EDGE RATE CONTROL lt CN13 24 CN14 24 gt 1 CE CN13 25 CN14 25 RES WR 4 CN13 26 CN14 26 NT ___ RD___ CN13 27 CN14 2
20. kit OM13320 aaa 012301 Fig 57 Input ramp yellow trace green LED drive green trace Fig 58 Input ramp yellow trace red LED drive green trace UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 42 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 6 2 2 Push switches Each channel has a push switch S01 through S71 that connects the appropriate IO pin to ground when pressed Series resistors R01 through R71 limit the current in the event that the IO pin is being driven HIGH by the connected GPIO device when the push switch is closed Each input is biased to VC one half the supply voltage in the event that the IO pin is left open This extinguishes both the green and red LEDs of that channel preventing false readings See Figure 59 vc e sg S alg of Ig ELIO x ELIO ELIO ELIO ELIO ELIO 100 101 103 104 105 106 107 4 4 4 _ a ome me me moe ale e le ge le EIE o N N N N N N N N TIN TIN TIN TIN TIN TIN ON H H H H H H H F Fy i s s S01 S11 S31 S41 S51 S61 S71 GND GND GND GND GND GND GND GND aaa 012139 Fig 59 Push switches 6 2 3 Bi
21. manual UM10785 Ref 1 is available for a complete explanation of the process A quick overview is presented here 1 Download Fm Board V1 0 Installation zip from www nxp com demoboard OM13320 html documentation 2 Extract NXP Fm Board V1 0 Installation exe and run 3 Follow the instruction prompts Select the default answers This GUI uses a USB Human Interface Driver HID so no driver installation is required If the firmware and GUI installs are successful an Fm Development Board block diagram is displayed when the GUI executes Figure 10 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 12 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 5 Fm development board OM13260 The Fm Development Board OM13260 PCB assembly is self contained requiring only DC power to operate Depending upon the firmware installed on the Fm Development Board OM13260 it can also operate with a connected Personal Computer PC via a USB cable The modular design of the kit and this board in particular allows accessory boards to be easily connected 5 1 Theory of operation LPC XPresso lt parallel port LPC1343 MCU PCA9672 8 channel GPIO N 33v 5V I2C bus 2 I2C bus 2 PULL UP RESISTORS PCA9665 PCA9955 BUS 16 channel LED CONTROLLER AA AUN 3 3 V
22. turn on the FET and light the LED 5V R29 R31 10 KQ 10 KQ 12325DS SI2325DS CN11 1 CN11 2 lt R30 R32 CN11 3 lt 8200 8200 CN11 4 D6 L LTST C170KGKT GRN I LTST C170CKT RED GRN RED GND GND GND UTILITY LED INDICATORS Fig 46 Logic probe circuit UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 35 of 61 NXP Semiconductors UM10741 UM10741 5 11 Fm development kit OM13320 vl e De 07 aN m a ro 8B Fig 47 Logic probe section shown monitoring two GPIO channels from Bus1 aaa 012295 INT and RST indicators Two global digital signal nets called INT interrupt and RST reset connect all 12 devices on the board and also the Port A Port E daughter card connectors These are also connected to the Master MCU IC5 on Bus1 the Master Bus Controller IC4 and the LPC Xpresso module See Figure 48 and Figure 49 Additional buffered LEDs are provided D19 RST and D20 Interrupt the Fm Development Board OM13260 for visual indication These buffered LEDs operate in the same fashion as the logic probe see Section 5 10 Logic probe 5V
23. 11 of 61 NXP Semiconductors U M1 0741 4 6 4 7 UM10741 Fm development kit OM13320 NXP firmware installation The micro on the Fm Development Board needs firmware running on it to interface with the GUI running on a Windows 7 PC over USB The board is shipped with a blank microprocessor so user action is necessary for proper operation An installation user manual UM10785 Ref 1 is available at for a complete explanation of the process A quick overview is presented here 1 Download NXP_Fm _Eval_Board_V1_0_firmware zip from www nxp com demoboard OM13320 html documentation Connect a USB cable from the PC USB port to CN5 Install the Connect JP3 jumper to connect the USB communications Install the ISP JP6 jumper to put the MCU into In System Programming mode Install and then remove RST JP4 jumper to reset the MCU The MCU will enumerate on the PC as a disk drive called CRP_DISABLD Delete the file on the MCU size may vary up to 32 kB DOO A C PD Copy the new firmware file NXP Fm Eval Board V1 O bin extracted from the zip file to the MCU 9 Remove the ISP JP6 jumper 10 Install and then remove RST JP4 jumper to reset the MCU NXP GUI installation A Graphical User Interface GUI is provided which allows easy manipulation of the devices included on the Fm Development Board and many others that can be connected to the board via daughter cards An installation user
24. 25 R22 HIGH 324 Q R14 R11 R24 R21 5 5 Daughter card ports Accessory circuit cards called Daughter Cards may be attached to any ports Port A Port D connectors CN1 CN4 respectively see Figure 34 Each port carries the same signals regardless of physical location Daughter Cards have jumpers to select whether connection to Bus1 or Bus2 is required Port A is shown in Figure 33 Port B Port D are identical and effectively in parallel SCL CN1 14 SCL BUS1 D gt CN1 13 SDA BUS2 5 CN1 12 INT RESET gt cN1 1 RESET 39V 9 CN1 40 5V 33V8 5 CNI 9 3V3 GND 5 CNI 8 GND GND 5 CN1 7 GND 3V3 gt CNI 6 3V3 HV N15 5V RESET gt RESET INT INT SDA1___s 2 SDA BUS1 SCL2 __s CN1 1 SCL BUS2 aaa 012042 Fig 33 PortA aaa 012286 Fig 34 Daughter card connectors Port A and Port B shown UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 29 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 5 6 PortE 5 6 1 The two independent I2C Buses Bus1 and Bus2 can be joined electrically to create a single I2C bus The link may be made by wire jumper or by an add on board with an 12C Bus Buffer device installed The PCA9617A Bus Buffer Demo Board OM1 3398 supplied in the kit is an example The Fm Develop
25. 29 325201505 12 2 Disclaimers 12 3 Trademarks 13 Contents cux nerd kainan rias Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2014 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com All rights reserved Date of release 1 April 2014 Document identifier UM10741
26. 3 CN1 8 5 QND CN1 7 5 QND CN1 6 2 33 CN1 5 2 8 RESET CN1 3 gt MT CN1 2 gt SDAI CN1 1 52 862 Fm BOARD PORT E aaa 012146 Fig 70 Bus buffer board connector O 7 a 4 3 EC SCL2 INT 5V GND 3V3 aaa 012147 Fig 71 Fm development board Port E connector All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 51 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 8 Bridge board OM13399 The Bridge Board OM13399 supplied in the kit provides attachment of old style with a 9 pin in line non polarized connector NXP designed I C demo boards to the Fm Development Board OM13260 The Bridge Board OM13399 can attach to any daughter card Port A D inclusive See Figure 72 and Figure 73 012307 Fig 72 Bridge board OM13399 attached to the Fm development board OM13260 aaa 012308 Fig 73 Bridge board OM13399 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 52 of 61 NXP Semiconductors U M1 0741 UM10741 8 1 8 2 Fm development kit OM13320 Theory of operation The Bridge Board is mostly a mechanical plat
27. 5 012305 Fig 64 Bus buffer board OM13398 012306 Fig 65 Bus buffer board OM13398 attached to the Fm development board OM13260 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 46 of 61 NXP Semiconductors U M1 0741 UM10741 7 1 7 2 Fm development kit OM13320 Theory of operation Two identical bus buffer devices are connected in series between the Bus1 and Bus2 segments on the Fm Development Board OM13260 Each Bus Buffer has two identical channels one for 12C clock SCL and the second for 12C data SDA Only one channel will be described in detail Each PCA9617A bus buffer device has two power supply connections Veca and Vccip to allow voltage level shifting between one I2C bus segment and another I2C bus segment Jumpers on the Bus Buffer Board OM13398 select the voltage source of each of the two device power supplies To demonstrate the voltage level translator ability the link between the two bus buffers is supplied from a variable voltage regulator which in turn can be set by the user anywhere between 1 0 V and 3 2 V The pull up resistor on the Low Voltage Bus section is selected by jumpers Circuit description The schematic diagram has multiple sheets For clarification only fragments of the schematic are shown here The full schema
28. 7 1 GND LPCXPRESSO SOCKET Fig 28 Bus2 master LPC Xpresso aaa 012041 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 26 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 5 4 2 Bus2 bus master PCA9665 A second Bus Master is connected to Bus2 using a dedicated Bus Controller device PCA9665 Fm parallel bus to I C bus controller IC4 The parallel port side is connected to the LPC Xpresso module LPC1343 PIO2 and PIO3 The 12C side is connected via RC edge rate control networks that provide bus fall time control SCL2 R47 and C21 SDA2 R46 and C22 See Figure 29 and Figure 30 Note IC4 is physically underneath the LPC Xpresso module 3V3 C11 100 nF GND SPAB R46 SDA2 sci R47 a SCL2 1000 tai C22 T 10 pF 10 pF GND GND PCA9665PW GND TF EDGE RATE CONTROL PCA9665 I2C BUS CONTROLLER aaa 011880 Fig 29 Bus2 master PCA9665 Lo 4 846 LU o f eA D C12 C13 C15 ge a FSI aaa 012284 Fig 30 Bus2 master PCA9665 section UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 27 of 61 UM10741 Fm development kit OM13320 NXP Sem
29. 8200 USB V MCU VBUS c2 100 pF 10 V D4 r3 r3 4 N LTST C170KGKT GRN R1 R3 45V 10 kQ 10 kQ GND GND GND Max input 6 2 V DC Di 3V3 CN6 STPS2L40U l v 4 IC1 GND DD JACK GMT R40 ZLDO1117G33TA 20 KQ R6 EXT_V l 8200 6v2 100 pF 10 V D5 703 R390 LTST C170KGKT GRN 1SMB5920BT3 10 kQ 3 8 V GND GND GND GND EXT POWER 3V3 REGULATOR aaa 011872 Fig 11 Power supply C m A 5 C1 IC id E 5 s nate Oo aaa 012088 Fig 12 Power supply and USB section UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 16 of 61 NXP Semiconductors UM10741 Fm development kit OM13320 5 2 2 USB interface The USB Host connector CN5 provides DC power and USB connectivity using the MCU IC5 hardware interface see Figure 12 and Figure 13 USB data lines are terminated by resistors R27 and R28 and protected by an ESD network IC7 To signal to the host that the USB connection is required the USB signal DP is pulled to 3 3 V via a resistor R18 and a transistor Q1 USB Connection is controlled by the MCU IC5 via signal CON EN and can be disabled by removing a jumper JP3 CONNECT When the MCU requests a USB connection and the jumper JP3 is installed the green LED D9 is ON MCU activity is displayed by the Heart Beat green LED
30. AGE JP5 PCA9955 JP6 ISP JP3 CONNECT JP2 HDD ADDRESS JP4 RST Fig 7 13260 test point locations m E E 2 c 4 4 OM13260 Port E bypass Depending up the intended operation of the Fm Development Board OM13260 Port E CN12 should be left open or linked with a jumper wire or for the attachment of a Bus Buffer Board The PCA9617A Bus Buffer Demo Board OM13398 is supplied in the kit For the purpose of this quick setup section install the two wire jumper supplied as shown in Figure 8 Remark The two wire jumper requires a twist as shown The diagonally opposite pins are linked UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 10 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 aaa 012075 Fig 8 OM13260 Port E jumper 4 5 OM13260 mounting hardware To prevent damage to the table surface it is recommended that metal hardware supplied in the kit is installed in the four mounting holes This raises the PCB assembly about 6 mm See Figure 9 aaa 012076 Fig 9 13260 mounting hardware Remark Save the completed Fm Development Board now install the NXP USB Driver UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014
31. Install Firmware on the Development Board OM13260 see Section 4 6 3 Install the NXP GUI Software on the computer to be used with the kit see Section 4 7 First time setup of the Fm development board OM13260 Several jumpers must be installed before using the Fm Development Board OM13260 PCB The on board microcontroller MCU must contain the appropriate firmware To install the firmware requires the connection to a Personal Computer PC running Microsoft Windows 7 64 Operating System and a USB port OM132680 jumpers The jumpers and their function are shown in Table 2 Using Figure 7 and the table data install the jumpers Table 2 OM13260 jumpers Jumper Label Function First time JP1 XPRESSO POWER Close JP2 HDD Open CONNECT Close JP4 RST Open JP5 PCA9955 address GND JP6 ISP Open JP7 SPI SEL 1 JP10 PCA9672 address GND JP11 SDA1 pull up A JP12 SCL1 pull up A JP13 Bus1 bus voltage 3V3 JP20 PCA9672 address GND JP21 SDA2 pull up A JP22 SCL2 pull up A JP23 Bus2 bus voltage 3V3 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 9 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 JP21 SDA2 PULL UP JP22 SCL2 PULL UP JP20 PCA9672 ADDRESS JP23 BUS2 BUS VOLTAGE JP11 SDA2 PULL UP JP10 PCA9672 ADDRESS JP12 SCL1 PULL UP JP13 BUS1 BUS VOLT
32. KOUT CT32B0_MAT2 USB_TOGGLE JP6 1 PIO0_2 SSP_SSEL CT16B0_CAPo 5 MCU_SSN gt JP6 2 1 2 MCU_VBUS db R42 Plo0 4 i2c sci 19 2 R43 5 I2C SpA 11 SDATA SERI 1000 PIO0 6 USB CONNECT sck 15 CON EN C18 10 pF 10 pF Pion vers 2 Uae LED PIO0_8 SSP_MISO CT16B0_MATO 17 8 aa PIO0_9 SSP_MOSI CT16B0_MAT1 swp 5 MCU MOSI SWCLK PIOO 40 SSP CLK CT16B0 MAT2 12 MCU_SCLK TF EDGE RATE CONTROL R PIOO 1 ADCO CT32B0 MAT3 2 HNT IC5G 1 aaa 011875 Fig 16 IC5 MCU Porto 3V3 LPC134X_HVQFN32 R PIO1 O ADC1 CT32B1 CAPO ey NOK R PIO1 1 ADC2 CT32B1 MATO pe HDD R PIO1 2 ADC3 CT32B1 MAT1 JP2 1 SWDIO SWDIO PIO1 3 ADCA CT32B1 MAT2 gt JP22 PIO1 4 ADC5 CT32B1 MAT3 WAKEUP cb LPC134X HVOFN32 PIO1 5 UART RTS CT32B0 CAPO 1 PIO2_0 UART_DTR PIO1_6 UART_RXD CT32B0_MATO IC5G 3 PIO1_7 UART_TXD CT32B0_MAT1 LPC134X_HVQFN32 PIO1 8 CT16B0 CAPO en PIO1 9 CT16B1 MATO PIOS 2 PIO1 10 ADC6 CT16B1 MAT1 IC5G 4 PIO1_11 ADC7 IC5G 2 aaa 011876 Fig 17 IC5 MCU Port1 The HVQN32 package has a thermal pad ground connection and operates from the main 3 8 V supply The MCU operates with a 12 00 MHz crystal controlled oscillator The frequency value and accuracy is necessary for correct USB timing see Figure 18 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 19
33. L5 JP7 2 MOSI 5 CN18 8 MESS 08 CN17 8 SSN1__s SCLK gt CN187 Mey Sek 33 1 gt CN18 6 3V3 2 gt CN17 6 MISO CN18 5 Med Mie R34 R48 CN18 4 Ls CN17 4 SDA2 5 cnig 3 SDAI 5 CN17 8 GND Morn N72 SCL2 ss ONITA BUS2 TEST BUS1 TEST aaa 012043 Fig 37 Bus1 and Bus2 tester connectors All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 31 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 aaa 012289 Fig 38 Bus1 tester connectors aaa 012290 Fig 39 Bus2 tester connectors 5 8 Serial communication port The LCP Xpresso module has a serial comms communications port EIA232 standards compliant using IC2 a voltage level translator See Figure 40 This is provided for connection to 12C Bridge devices that require Serial Communications To save space on the PCB a small mini DIN connector CN7 replaces the standard 9 pin DE shell connector For connection to standard serial comms cables an adapter is required see Figure 41 The recommended Mini DIN to DE 9 Adapter is Digikey PN AE1393 ND not supplied See Figure 42 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 32 of 61 NXP Semiconduc
34. PCA9901 LED BLINKER CTRL GND aaa 012137 2 U o z t o at TR e 3 p Fig 53 LED blinker PCA9901 section Ww TT R45 C23 5 i Qu PETATE on ne ns Vu gt aaa 012298 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 39 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 6 GPIO target board OM13303 The GPIO Target Board OM13303 is used to monitor the Input Output I O signals from a GPIO The board has eight channels each with a push switch and an LED indicator See Figure 54 aaa 012299 Fig 54 OM13303 GPIO target board PCB assembly front side 6 1 Theory of operation Each of the eight channels operates independently and in the same way The voltage applied to the input pin is compared in a Windows comparator which in turn drives a dual color LED The thresholds for the comparators are set to one third logic zero and two thirds logic one of the supply voltage These values correspond to the I C bus logic threshold voltages for the I2C bus specification When a push button is pressed a logic zero is applied the channel which can be read by the GPIO device to which the GPIO Target Board is attached A 2 x 5 header is used to connect to
35. are program that runs on a Personal Computer PC under the Microsoft Windows 7 Operation System In some uses the GUI is not required and the Fm Development Kit OM13320 can be run as a standalone demonstration requiring only an external power adapter not included 2 Key features I C bus masters Self contained PCB with two independent I C buses Bus 1 On card IC MCU master LPC1343 Bus 2 NXP LPC Xpresso MCU module not included and NXP PCA9665 bus controller USB interface to on card MCU for connection to a PC running the GUI software I C bus slaves General Purpose Input Output GPIO PCA9672 one each on Bus1 and Bus2 LED driver with 16 constant current outputs PCA9955 with four RGB and four White LEDs on Bust Accessory sockets Connectors for up to four daughter cards each providing power Bus1 and Bus2 12C signals Connector for the Bus Buffer Board OM13398 supplied containing two PCA9617A bus buffers Connector for a third party I C bus logger or I C bus controller Beagle and Aardvark from Total Phase 12C buses I C bus voltage jumper select 5 V external or 3 3 V on card 3 3 V regulator I2C bus pull up resistors jumper select of high med or low loading UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 3 of 61 NXP Semiconductors U M1 0741 Fm developmen
36. as circuit Each channel requires three reference voltages VL VC and VH from the bias circuit A resistor divider chain R01 R02 R03 and R04 divides the supply voltage to produce one third VL one half VC and two thirds VH Each value is buffered by an op amp sections of IC80 Test points are provided as PCB pads for VH high VC center and VL low The fourth section of the quad op amp IC80 is not used Noise spikes on each bias supply are removed by capacitors C89 C90 and C91 power supply variations are removed by capacitors C86 and C87 See Figure 60 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 43 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 TP3 R81 C89 LMV324MZ 100 nF GND TP4 R82 5 1 kO IC80B LMV324MZ C90 100 nF C87 4 7 UF 6 3 V GND TP2 GND R83 5 1 KQ IC80A C91 C86 LMV324MZ 100 nF 4 7 UF 6 3 V GND GND T FS IC80C LMV324MZ R84 10 kQ aaa 012140 Fig 60 Bias circuit 6 2 4 Connectors The GPIO Target Board OM13303 is intended to be connected to the Fm Development Board OM13260 or other GPIO daughter cards via a 10 pin ribbon cable There are two identical connectors one on each end of the GPIO Target Board to al
37. ccepts no liability for any assistance with applications or customer product UM10741 All information provided in this document is subject to legal disclaimers design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affil
38. ducts described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors a
39. elopment kit OM13320 aaa 01231T Fig 82 Beagle Bus Logger connected to the Fm development board OM13260 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 58 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 10 Abbreviations Table 7 Abbreviations Acronym Description DLL Dynamic Link Library EVM Evaluation Module FET Field Effect Transistor Fm Fast mode Plus GPIO General Purpose Input Output GUI Graphical User Interface HID Human Interface Driver I2C bus Inter Integrated Circuit bus VO Input Output ISP In System Programmable JTAG Joint Test Action Group LDO Low Drop Out LED Light Emitting Diode MCU MicroController Unit OS Operating System PC Personal Computer PCB Printed Circuit Board RC Resistor Capacitor network RGB Red Green Blue SPI Serial Peripheral Interface SWD Single Wire Debug USB Universal Serial Port 11 References 1 UM10785 Fm Demo Board Software Installation Guide NXP Semiconductors 25 February 2014 www nxp com documents user_manual UM10785 paf UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 59 of 61 NXP Semiconductors UM10741 12 Legal information Fm development kit OM13320 12 1
40. f 61 UM10741 Fm development kit OM13320 NXP Semiconductors 3 2 4 Bridge board OM13398 Some existing Demo Boards used a single row connector with nine pins To use these with the Fm Development Kit requires the Bridge Board OM13399 supplied in the kit See Figure 5 aaa 0011944 Fig 5 OM13399 bridge board PCB assembly 3 2 5 Daughter cards not supplied in the kit These are not in the OM13230 kit and should be obtained separately Daughter cards hedge against obsolescence so that the Fm Development Kit OM13320 can be used with future devices by adding newly released daughter cards as they become available An example daughter card is shown in Figure 6 aaa 011945 Fig 6 Example daughter card PCB assembly All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Rev 1 1 April 2014 8 of 61 UM10741 User manual NXP Semiconductors U M1 0741 Fm development kit OM13320 4 First time setup Fm development board kit OM13320 UM10741 4 1 4 2 4 3 Before you begin To use the Fm Development Kit OM13320 for the first time requires some hardware setup and installation of both firmware on the Development Board OM13260 and software on the attached computer The following three steps must be completed 1 Install Jumpers on the Fm Development Board OM13260 see Section 4 3 2
41. form for the old style with a 9 pin in line non polarized connector of NXP designed 12C demo boards that use a non polarized nine position connector Previous NXP I C demo boards were released with both vertical and horizontal mounting and both male pins and female sockets The Bridge Board OM13399 therefore has both styles There is also a Tester connector that allows direct connection of the third party tools see Section 9 The old style with a 9 pin in line non polarized nine circuit connector had only one I C bus with SCL and SDA signals The Fm Development Board Daughter Card ports have two I C Buses Bus1 and Bus2 signals One or other I2C Bus can be selected by jumpers The power source may also be selected by jumper Circuit description The schematic diagram has a single sheet For clarification only fragments of the schematic are shown here The full schematic should be downloaded if required The circuit is simple 8 2 1 Fm development board OM13260 connector CN3 CN3 14 SCLT gt JPZ3 CN3 13 gt SDA2 _ SCL Ss JP22 12 3 INU gt JP24 N CN3 11 5 RESET CN3 10 35 SV CN3 9 5 HV9 CN3 8 5 9ND CN3 7 5 SND SDA CN3 6 gt CN3 5 35 SV CN3 4 5 RESET SEL Fm BUS CN3 3 35 INT bun SDA1 CN3 1 SCL2 gt JP 3 gt JP3 2 gt JP3 1 Fm BOARD aaa 012148 Fig
42. iates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent pe
43. iconductors 5 4 3 Bus2 pull up resistors The Bus2 is pulled up to either the 3 3 V or 5 V supplies via JP23 Three different value pull up resistors are provided by jumper selection JP21 and JP22 The values of the pull up resistors are shown in Table 6 Separate pull ups are provided for the SCL and SDA signal lines See Figure 31 and Figure 32 Bus1 has a similar arrangement see Section 5 3 2 45V 1 1 KQ 3V3 R26 L JP22 6 JP22 5 lt 634 Q gt JP22 4 JP22 3 lt SCL2 JP23 1 324 0 9 JP22 2 JP22 1 JP23 2 4 4 R4 JP23 3 lt lt 14 KQ R23 5 JP21 6 JP21 5 lt 634 Q T gt JP21 4 JP21 3 4 1 spA2 324 0 9 JP21 2 JP21 1 R21 C10 100 nF 12C BUS 2 PULL UP RESISTOR NETWORK aaa 011881 Fig 31 Bus2 pull ups and bus voltage selector R24 250 012285 Fig 32 Bus2 pull ups section UM10741 All information provided in this document is subject to legal disclaimers Rev 1 1 April 2014 NXP B V 2014 All rights reserved 28 of 61 User manual NXP Semiconductors U M1 0741 Fm development kit OM13320 Table 6 pull up resistors Strength Position Value Bus1 SCL 1 SDA Bus2SCL Bus2 SDA LOW A 1 1 KQ R16 R13 R26 R23 MID B 634 Q R15 R12 R
44. ll information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 23 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 3V3 3V3 3V3 N GPIO4 0 7 GPIO1 7 GPIO1 6 GPIO1 5 GPIO1 4 GPIO1 3 GPIO1 2 GPIO1 1 GPIO1 0 CN10 10 CN10 9 CN10 8 CN10 7 CN10 6 CN10 5 CN10 4 CN10 3 4 GPIO1 0 i GPIO1 6 2 GROT JP10 1 JP10 2 JPi0 3 4 SDAT 1 4 JP10 5 SCL1 10 6 JP10 7 JP10 8 IC10 PCA9672PW b eda GND PCA9672 VDD per ione gt CN10 1 SDA1 0x56h GND SCL1 0x54h GND GND 0x44h PCA9672 8 bit GPIO Bus1 Fig 24 Bus1 GPIO 8 bit Table 5 LED driver address selection AO connected to Hexadecimal 8 bit address NXP 7 bit address Address LSB Address LSB GND 0x44 0100 0100 0x22 010 0010 Voc 0x46 0100 0110 0x23 010 0011 SCL 0x54 0101 0100 Ox2A 010 1010 SDA 0x56 0101 0110 0x2B 010 1011 a 012281 Fig 25 Bus1 GPIO 8 bit section UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 24 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 5 4 Bus two Bus2 5 4 1 The second 12 bus on the Fm Development Board OM13260
45. low connection without blocking the push switches or the LEDs See Figure 61 Figure 62 and Figure 63 3V3 3V3 Tas CN1 1 CN2 1 m CN1 2 55 CN2 2 O0 5 CNI 3 dip 100 _s CN23 101 __ sent 101 S cno 4 102 gt CN1 5 02 5 CN2 5 103 gt 103 gt CN2 6 104s CN1 7 04 gt CN2 7 105 gt CNI 8 105 _s CN2 8 106 _s CNI 9 106 gt CN2 9 107 gt CNI 10 107 _s CN2 10 aaa 012141 Fig 61 Connectors UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 44 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 aaa 012303 Fig 62 Ribbon cables attached to underside of the GPIO target board OM13303 aaa 012304 Fig 63 Ribbon cables attached to the topside of the GPIO target board OM13303 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 45 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 7 Bus buffer demo board OM13398 The Bus Buffer Board OM13398 supplied in the kit provides a method to link both the 12C buses on the Fm Development Board OM13260 by attachment to Port E in place of the wire jumper used earlier see Section 5 6 1 Linking both buses together with a jumper See Figure 64 and Figure 6
46. m Development Board OM13260 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 56 of 61 NXP Semiconductors U M1 0741 Fm development kit OM13320 9 Third party tools Generation inspection and logging of I C bus data is easily achieved with third party development tools from a number of suppliers SB Solutions Inc www i2ctools com and Total Phase www totalphase com SB Solutions supplies a range of tools driven from USB and outputs to 12C and SPI The user interface is very similar to the Fm Development Board GUI and a DLL is provided for custom development These tools are not supplied in the kit and must be purchased directly from the vendor Total Phase supplies two tools called Aardvark host adapter and Beagle bus logger that connect directly to the Fm Development Board OM13260 These tools are not supplied in the kit and must be purchased directly from the vendor aaa 012505 Fig 80 SB Solutions USB to I2C Pro connected to an Fm Development Board daughter card aaa 012316 Fig 81 Aardvark Host Adapier connected to the Fm development board OM13260 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 57 of 61 NXP Semiconductors U M1 0741 Fm dev
47. ment Board OM13260 may also be operated with nothing connected to Port E CN12 The Port E signal pins are arranged to be symmetrical permitting the card to be rotated 180 effectively changing the direction of the signals through the card See Figure 35 and Figure 36 Remark When linked together by wire jumper the pull up resistors on each bus are effectively in parallel The resulting value is therefore one half of the original value Pull up resistors of low value will overload the I C drivers and effectively stop the bus from operating Linking both buses together with a jumper Fig 35 Port E with wire jumper All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 30 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 5 6 2 Linking both buses together with a bus buffer board aaa 012288 Fig 36 Port E with bus buffer card OM13398 installed 5 7 Tester connectors for third party tools Bus1 may be connected to third party test equipment via CN17 Bus2 has a similar and independent connection at CN18 See Figure 37 Figure 38 and Figure 39 Remark Refer to Section 9 Third party tools of this user manual GND gt CN18 10 GND___sen17 10 SSNO 5 jp7 3 ____s CN18 9 MCU SSN 5 on17 9
48. near ground This turns on the green LED D01 Resistor R04 applies positive feedback hysteresis about 150 mV to the comparator shifting the trip point to a slightly lower voltage to stop the circuit from oscillation around the switch point The input IOO is attenuated slightly by a resistor divider R07 and R08 if the resulting voltage is lower than the threshold set by Vi the output of the comparator IC1B switches to near ground This turns on the red LED D01 Resistor R08 applies positive feedback hysteresis about 125 mV to the comparator shifting the trip point to a slightly higher voltage to stop the circuit from oscillation around the switch point LED current is limited by resistors R05 and R09 which are selected to give approximately equal brightness to the green and red LED elements See Figure 56 The operation of the window circuit is shown by applying a ramp waveform see Figure 57 and Figure 58 3V3 R02 10 kQ LMV358MM 5 a VH R03 G R 51k0 Vale a 8 100 R05 1 MQ 330 Q VL R06 10 R07 51 012138 Fig 56 Window comparator Channel 0 shown All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 41 of 61 NXP Semiconductors U M1 0741 Fm development
49. of 61 NXP Semiconductors UM10741 UM10741 Fm development kit OM13320 LPC134X_HVQFN32 IC5G 6 IC5G 7 GND Fig 18 IC5 MCU Port1 oscillator and power supply XTALIN XTALOUT LPC134X HVQFN32 VDDIO EXT 1 VDDMAIN EXT LPC134X HVQFN32 XE1 IC5G 5 12 MHz C8 15 pF 15 pF GND GND 3V3 NX5032GA GND GND aaa 011877 5 3 2 Bus1 pull up resistors The Bus1 is pulled up to either the 3 3 V or 5 V supplies via JP13 Three different value pull up resistors are provided by jumper selection JP11 and JP12 The values of the pull up resistors are shown in Table 3 Separate pull ups are provided for the SCL and SDA signal lines Bus2 has a similar arrangement See Figure 19 and Figure 20 45V 1 1 b d R16 L5 JP12 6 634 Q gt JP12 4 R15 JP13 1 3240 P122 JP13 24 H JP13 3 1 1 kQ RIS 634 t gt 11 4 R12 324 0 2 11 2 R11 C10 100 nF GND 12 BUS 1 PULL UP RESISTOR NETWORK Fig 19 Bus1 pull ups and bus voltage selector JP12 5 lt _ JP12 3 lt _ SCL1 12 1 lt JP11 5 lt JP11 3 lt SDA1 JP11 1 aaa 011878 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1
50. on of Bus1 are on the Fm Development Board OM13260 Fig 68 Bus2 bus buffer VDD A al alle alg sl g o 400 OE gi UX gg SCL VDD A PULL UP GND v N 1 Q Q ao QA TP3 yi i h TP6 r ag d SCL2 SDA2 n JP6 1 JP6 2 GND ENABLE SCLA SDAA HWSON8 PCA9617ATP DO NOT PLACE SND aaa 012144 UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 49 of 61 UM10741 Fm development kit OM13320 NXP Semiconductors 7 2 3 Supply select jumpers The B Side high voltage side of the voltage level translator of each PCA9617A can be either 3 3 V or 5 V as selected by JP1 The A Side low voltage side of the voltage level translator of each PCA9617A can be either 3 3 V or a variable voltage between 1 0 V and 3 2 V as selected by JP2 See Figure 69 SEL VDD B VOLTAGE PEE a a a gt 2 8 SEL VDD A VOLTAGE 5V 5V TN 009 N N CN AES e ng B e S g gt US 7 x thc e 02 22 16 V amp BLU 9 Q1 GND BSH111 FAN2558ADJ GND GND VAR ADJ a iE T VDD A ON ol S LIN VDD A LDO 1 0 V to 3 2 V GND
51. requires the addition of an NXP LPC Xpresso Module not included in the kit to either be the Master or drive the bus controller PCA9665 IC 4 There are two almost identical 12C buses on the Fm Development Board OM13260 called Bus1 and Bus2 These share a ground and power connection but may be operated independently Remark The bus voltage for each 12 maybe different for example 3 3 V for one I C bus 5 V for the other 12C bus Bus2 master LPC Xpresso MCU LPC1343 The LPC Xpresso Module contains an NXP LPC1343 MCU similar to the one on Bus 1 and support circuits called LPC Link See Figure 26 The LPC Xpresso requires firmware that is loaded through either the LPC Link and USB Bridge or JTAG Single Wire Debug SWD connector Remark The LPC Xpresso is not compatible with the NXP GUI and requires the installation of an IDE for code development aaa 012282 Fig 26 Fm development board with LPC Xpresso installed The LPC Link may be powered from the Fm Development Board OM13260 or from a USB Host connected to the LPC Link port There is a possible conflict that the LCP Link 3 3 V supply will compete with the Fm Development Board OM13260 3 3 V supply To avoid this issue the LPC Xpresso Module can provide its own 3 3 V power by removing jumper JP1 on the Fm Development Board OM13260 See Figure 27 12C Bus2 is connected to the MCU PortO via RC edge rate control networks that provide bus
52. rmitted by applicable law even if any remedy fails of its essential purpose Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 12 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors N V NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 60 of 61 NXP Semiconductors UM10741 13 Contents Fm development kit OM13320 Introduction 3 Key 3 I2C bus 3 I2C bus slaves 3 Accessory 3 2C 3 Other 4 Fm development kit quick tour 4 Kit contents 4 Box 5 Supplied PCB assemblies 6 Fm Development Board OM13260 6 GPIO target board OM13303 7 PCA9617A bus buffer demo board OM13398 7 Bridge board OM13398 8 Daughter cards not supplied in the kit 8 First time setup Fm development board kit OM13320 2 ga
53. rs 5 12 Prototype 5 13 LED blinker 9901 6 GPIO target board OM13303 6 1 Theory of 6 2 Circuit description 6 2 1 Window 6 2 2 Push switches 6 2 3 Bias CIrc lt sep RI ERR da edness 6 2 4 GorihectOrs s cake e ek Ra 7 Bus buffer demo board OM13398 7 1 Theory of 7 2 Circuit description 7 2 1 Bus1 bus buffer PCA9617A 7 2 2 Bus2 bus buffer PCA9617A 7 2 3 Supply select 7 2 4 Variable voltage regulator 7 2 5 Connector 8 Bridge board 13399 8 1 Theory of 8 2 Circuit description 8 2 1 Fm development board OM13260 connector 8 2 2 Power supply select JP1 and JP4 8 2 3 9 position connectors CN1 and CN2 8 2 4 Tester connector 4 8 2 5 LED indicators and pull ups 8 3 Example using PCA9632 OM13269 9 Third party 10 Abbreviations 11 References 12 Legal information 12 1 Defiritlornis 2 0 4 125
54. s buffer PCA9617A I2C bus signals from the Fm Development Board OM13260 called SCL1 and SDA1 are applied to the high voltage or B Side of IC1 PCA9617A The required pull up resistors on this section of Bus1 are on the Fm Development Board OM13260 Signals on the low voltage or A Side of IC1 are connected to a selection of pull up resistors selected by either JP5 for SCL or JP3 for SDA and the low voltage or A Side of the second PCA9617A IC3 Loading capacitors C31 for SCL and C51 SDA can be placed on the low voltage section of the bus To accommodate two different footprints IC1 TSSOP8 and IC2 HWSON8 are connected in parallel but only one part is installed Installing JP4 disables the Bus Buffer See Figure 67 User manual Rev 1 1 April 2014 48 of 61 NXP Semiconductors UM10741 Fm development kit OM13320 7 2 2 Bus2 bus buffer PCA9617A I2C bus signals on the low voltage bus are also connected to the A side of the second PCA9617A Bus Buffer device IC3 To accommodate two different footprints IC3 TSSOP8 and IC4 HWSONS are connected in parallel but only one device is installed Installing JP6 disables the bus buffer See Figure 68 I C bus signals from the high voltage or B side of IC3 PCA9617A are passed back to the Fm Development Board OM13260 The required pull up resistors on this secti
55. supply The Fm Development Board OM13260 operates from DC either from the USB Host connector CN5 or an optional external AC DC power adapter not supplied in the kit via connector CN6 See Figure 11 and Figure 12 Selection of the power source is automatic using ORing diodes D1 and D2 The main power on the Fm Development Board OM13260 is 3 3 V from a linear regulator IC1 but some of the circuits are powered directly from the incoming supply which is a nominal 5 V Linear regulator 1 1 uses the PCB bottom layer copper as a heat sink The Fm Development Board OM13260 external DC input is protected against reverse polarity or overvoltage by Zener diode D3 Both input sources are scaled by resistor dividers R1 R2 and R39 R40 and fed to the MCU IC5 Port1 ADC inputs for voltage level monitoring The VBUS from the USB Host is fed to the MCU Port 0 so that the MCU can detect that a USB connection is available Green LED D4 confirms 5 V and Green LED D5 confirms 3 3 V All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 15 of 61 NXP Semiconductors UM10741 Fm development kit OM13320 5V VBUS 02 R2 R4 STPS2L40U R5 10 KQ 10 kQ
56. t kit OM13320 Other features SPI ports One for on card MCU two more for LPC Xpresso Serial Com Port EIA232 with voltage level shifter and connection to the LPC Xpresso LED blinker NXP PCA9901 one wire with on card LED INT Interrupt and RST Reset Bus signal monitor LEDs buffered Logic probe Utility LEDs buffered to monitor signals by user jumper wire connection External DC input 6 V DC maximum Prototype area Uncommitted 8 x 8 100 mil pitch tie points for end user component attachment Test points and ground for probe attachment to major signals Connection of both 12 buses together supplied 2 wire jumper 3 Fm development kit quick tour 3 1 Kit contents Before using the kit for the first time please familiarize yourself with the various components listed in Table 1 See Figure 1 Remark Each PCB assembly is shipped in an anti static bag After the first use these may be discarded to simplify future storage aaa 011939 aaa 011940 a Top layer b Bottom layer Fig 1 Fm development kit UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 4 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 Table 1 development kit contents Components Fm development board OM13260 GPIO target board OM13303 PCA9617A bus buffer demo board
57. the Fm Development Board OM13260 or a GPIO daughter card with a flat ribbon cable supplied in the kit Two connectors are installed one on each end of the board and on opposite sides of the PCB to aid in connection without the cables blocking the buttons or LEDs There are no option jumpers and no adjustments on the GPIO Target Board OM13303 Unlike other PCB assemblies in the Fm Development Kit OM13320 the GPIO Target Board OM13303 has components on both sides of the PCB See Figure 55 aaa 012300 Fig 55 OM13303 GPIO target board PCB assembly back side UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 40 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 6 2 Circuit description 6 2 1 The schematic diagram has multiple sheets For clarification only fragments of the schematic are shown here The full schematic should be downloaded if required The following pages are divided in to several sections covering the window comparator push switches bias circuit and connectors Window comparator Channel 0 is shown channels 1 through 7 are identical The input signal is applied to two comparators ICO1A and ICO1B If the input IOO is higher than the threshold set by and resistor divider R03 and R04 the output of the comparator ICO1A switches to
58. tic should be downloaded if required The following pages are divided in to several sections covering the Bus1 Bus Buffer Bus2 Bus Buffer Supply select jumpers Adjustable Voltage Regulator and Connectors A block diagram will assist understanding See Figure 66 5V ADJUSTABLE J 33v VOLTAGE REGULATOR TOV to 3 2V VCC A VCC B PULL UP RESISTORS Vcc A Vcc A VCC B EE E l l I 1 B BUS1 lt 9617 l i PCA9617A gt BUS2 d voltage I bus I Dc ue ee bou scs aaa 012142 Fig 66 Block diagram for the bus buffer board OM13398 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 47 of 61 NXP Semiconductors U M1 0741 VDD A sl le alle al lg 5 o jy 0 SDA VDD A PULL UP T vox lls w jo GND 4 v v 9 C51 2 wur VDD A 5 5 5 c 5 S GND TP1 TP2 y i pi mi SCL1 SDA1 a gt GND GND SCL1 SCLA SDA1 SDAA TSSOP8 JP4 1 JP4 2 GND ENABLE SCLA SDAA HWSON8 PCA9617ATP DO NOT PLACE GND aaa 012143 Fig 67 Bus1 bus buffer UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved 7 2 1 Fm development kit OM13320 Bus1 bu
59. to s none iD ern 9 Before you begin 9 First time setup of the Fm development board 13260 9 0 132680 jumpers 9 OM13260 Port bypass 10 OM13260 mounting hardware 11 NXP firmware installation 12 NXP GUI installation 12 Fm development board OM13260 13 Theory of operation 13 Circuit 15 Power supply 15 USB 17 B s one Bust iR 17 Bus1 master MCU LPC1343 17 Busi pull up 20 LED driver slave 9955 21 GPIO slave PCA9672 23 Bus two 2 25 Bus2 master LPC MCU LPC1343 25 Bus2 bus master PCA9665 27 2 pull up 5 5 28 Daughter card ports 29 PottE ERI DR 30 Linking both buses together with a jumper 30 Linking both buses together with a bus buffer board esce hkl 31 5 7 Tester connectors for third party tools 5 8 Serial communication port 5 9 SPI ports 5 10 Logic probe 5 11 INT and RST indicato
60. tors U M1 0741 Fm development kit OM13320 3V3 C15 1 14 100 nF L 100 nF GND GND T10UT ea 2 RAIN 3 gt 4 INVALID is FORCEOFF 8 FORCEON GND CL3220CV2 X GND GND SERIAL COMMS mm Fig 40 Bus2 tester connectors aaa 012291 Fig 41 Serial Com section aaa 012292 Fig 42 Serial Com dongle UM10741 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 33 of 61 NXP Semiconductors UM10741 5 9 SPI ports development kit OM13320 Both the Bus1 Master MCU and the Bus2 Master LPC Xpresso Module support SPI communications The Bus1 MCU has one SPI port SPI2 CN16 and the LPC Xpresso has two SPI ports SPIO and SPI1 CN9 CN8 respectively See Figure 43 Figure 44 and Figure 45 Also refer to Section 9 of this user manual for details on using the tester connector for third party tools with the SPI ports NT cN amp s SND 5 CN amp 7 gt CNB 6 f gt CN8 5 gt CN8 4 35 CNB8 3 M CN8 2 8 1 NI cNes SND 5 CN9 7 gt CN9 6 gt CN9 5 gt CN9 4 CN9 3 2 5 CN9 1 SPI DAUGHTER CARD EXPANSION CONNECTORS Fig 43
61. ubject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 13 of 61 NXP Semiconductors U M1 0741 UM10741 Fm development kit OM13320 Each bus has a GPIO 8 bit Slave device PCA9672 IC10 and IC20 and Bus 1 also has an LED Driver 16 channel device PCA9955 IC6 All sixteen outputs are connected to LEDs for visual indication The 8 bit GPIOs require connection of GPIO Target Boards OM13303 supplied in the kit to both indicate the output using eight LEDs and allow user input from eight push switches An NXP LPC1343 Microcontroller MCU serves as both the Bus 1 Master and the USB link The firmware on the MCU can be replaced by the In System Programming ISP mode with data sent over the USB link CN5 Bus 2 has a Parallel to 12 Controller device PCA9665 IC6 which is to be driven by an optional NXP LPC Xpresso module not supplied That module is also an 12 Master and connected to Bus 2 Remark Although Bus 2 has more than one I C Master only one is active at any time The remaining circuitry is to support the 12C devices and provide communications with the PC over a USB link The main operating voltage on the Fm Development Board OM13260 is 3 3 V supplied from a linear regulator IC1 Some circuits and the optional I2C bus pull ups may run from 5 V derived either from the USB host typically a PC or an AC DC power supply not supplied in the kit
62. upply connection CN6 is required to drive the LEDs to the maximum current per channel of 57 mA for a total of approximately 1 A All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 1 April 2014 22 of 61 NXP Semiconductors UM10741 5 3 4 UM10741 Fm development kit OM13320 The recommended AC DC adapter is Digikey PN 62 1132 ND not supplied See Figure 23 aaa 012280 Fig 23 AC DC adapter 6 V 2 A The Slave address is set by JP5 summarized in Table 4 Remark The PCB is marked with hexadecimal 8 bit address data but data sheets and the NXP GUI use the 7 bit address values See Table 4 Table 4 LED driver address selection JP5 connected to Hexadecimal 8 bit address NXP 7 bit address Address MSB LSB Address MSB LSB GND 0xCO 1100 0000 0x60 110 0000 Vec OxDO 1101 0000 0x68 110 1000 GPIO slave PCA9672 The GPIO PCA9672 IC10 is connected to Bus1 and provides eight input output channels at CN10 Jumper JP10 sets the device address to one of four options depending on whether the pin is connected to GND Vcc SCL or SDA Bus2 has a similar arrangement for a second GPIO PCA9672 IC20 See Figure 24 and Figure 25 Remark The PCB is marked with hexadecimal 8 bit address data but data sheets and the NXP GUI use the 7 bit address values This is summarized in Table 5 A

UM10741 Fm+ development kit OM13320

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