IP320A Manual
Contents
1. COMPONENT SIDE OF CARRIER BOARD Ns P1 CONNECTOR 50 PIN CONNECTOR 1004 512 PIN 1 ON CABLE NO MARKINGS FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX EL 5025 551 SCHEMATIC MODEL 5025 551 SIGNAL CABLE SHIELD 19 2 P1 TO 19 AVME9630 9660 mN MODEL 5025 552 CARRIER BOARD 1 0 TERMINATION P3 OR P4 P5 P6 PANEL x gt FEET TOP VIEW STRAIN 50 PIN RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR 1004 534 2002 261 INDICATES PIN 50 1004 512 POLARIZING KEY ME STRAIN RELIEF 1004 534 PIN 1 4501 463A SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 1234 56 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1 1234 5 6 7 B 9101112131415 16 1718 19 20 2122 2324 25 26 27 28 20 30 31 32 33 34 35 36 37 38 39 40 4142 43 4445 46 47 48 49 50 MODEL 5025 552 TERMINATION PANEL SCHEMATIC 770 CR ee ee Pee ee eee ee ae E P12. 5 BOARD Default Hardware Jumper Configuration Analog Input Range Hardware Jumper Configuration Power Supply Hardware Jumper Configuration Control Register Analog Input Data CONNECTORS cie aeann eri x Re PR ete IP Field I O Connector P2 Analog Input Noise and Grounding Considerations External Trigger IP Logic Interface Connector 1 PROGRAMMING INFORMATION ID SPAGE SPACE ADDRESS Control ADC Convert Read ADC PROGRAMMING CONSIDERATIONS Using the Separate ADC Convert amp Read Command Using External Conversion Triggers USE OF CALIBRATION 5 Uncalibrated 2 0 3 0 3 33833000000 OO IO ID Calibrated 10 4 0 THEORY OF
3. 12 ANALOG 5 11 LOGIC POWER 13 2320 1 2 toe eoe 13 5 0 SERVICE AND 14 SERVICE AND REPAIR ASSISTANCE 14 PRELIMINARY SERVICE PROCEDURE 14 WHERE TO GET 14 6 0 8 14 GENERAL 65 14 14 ANAEOG INPUTS 21 ete idee 15 INDUSTRIAL PACK COMPLIANCE 15 bid toe 16 CABLE MODEL 5025 550 16 CABLE MODEL 5025 551 16 TERMINATION PANEL MODEL 5025 552 16 TRANSITION MODULE MODEL TRANS GP 16 Page DRAWINGS Page 4502 043 20 JUMPER LOCATIONS 17 4502 044 IP320A BLOCK 18 4501 435 ANALOG INPUT CONNECTION DIAGRAM 18 4501 434 IP MECHANICAL ASSEMBLY 19 4501 463 CABLE 5025 551 SHIELDED 19 4501 464 TERMINATION PANEL 5025 552 20 4501 465 TRANSITION MODULE TRANS GP 20 IMPORTANT SAFETY CONSIDERATIO
4. HE E 1 C 1 N amp 751 I THE HH m H7 x m 85 1 Ha jl A g g N is Olt Y EH o 9 ol ILL 1 vi N Y FRONT VIEW n 078 E E 198 49 4 6 A lt 10 31 261 9 gt NOTE DIMENSIONS ARE IN INCHES MILLIMETERS TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 465A 20
5. BIN MOUNTING SHOWN HERE AERMINATI N pr DIN EN 50035 32mm L ome EP ACROMAG PART NUMBER 1001046 ui RAIL DIN MOUNTING 3 032 p SHOWN HERE 77 0 fyb DIN EN 50022 35mm TB1 aS 2200002000220 0000 0000000 0 000 E 0 2200 00202220229292220292029292 L E Ore SLOT FOR 315 REMOVAL FROM T RAIL 135 0 TOP VIEW SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 TOLERANCE 40 020 40 5 1 3 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 MODEL 5025 552 TERMINATION PANEL ane 58 5 4501 464A FRONT VIEW A B C D 125 48 49 50 123 48 49 50 123 48 49 50 1253 48 49 50 CONNECTORS MODEL TRANS GP ON RE BOARD MODULE SCHEMATIC a 2 123 48 49 50 123 48 49 50 123 48 49 50 123 48 49 50 CONNECTORS ON FRONT PANEL TOP VIEW A B D i 9 19 233 4 10 e iol 0
6. a EUM EE BEEN ic WR i EEUU UE 2 5 to 2 5 1 25 to 1 25 0 625 to 0 625 Note that the worst case non linearity error is 0 75 LSB the sum of the 72 LSB non linearity of the ADC and the 74 LSB non linearity of the PGA 1 0 6125 CAL3 Calibrated Performance Very accurate calibration of the IP320A can be accomplished by using calibration voltages present on the board The four voltages and the analog ground reference are used to determine the endpoints of a straight line which defines the analog input characteristic The calibration voltages are precisely adjusted at the factory to provide optimum performance as detailed in the following table The following equation 1 is used to correct the actual ADC data i e the uncorrected bit count read from the ADC making Maximum Maximum use of the calibration voltages and range constants Calibration Tolerance Temperature Signal 25 C Volts Drift 9 0 0000 i0002 0 Ideal_Volt_Span 0 0005 2 12250 004 EE M m 7 Cont CALLO cars 0 6125 00002 Worst case temperature drift is the sum of the 15 ppm C drift of the calibration voltage reference plus the 5 ppm 9C drift of the resistors in the voltage divider Volt Gain Ideal Zero CALLO where m represents the actual slope of the transfer characteristic as defined in equation 2 find two p
7. 1 COMPONENT SIDE OF IP MODULE Je xL M2 x 6 PAN HEAD SCREW ASSEMBLY PROCEDURE THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGTHS THE SHORTER LENGTH IS FOR USE WITH AVME 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS NSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE IP MODULE AND INTO HEX S RS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS OGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED NSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM 8 AND TIGHTEN 4 PLACES IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY PIN 5 OF P1 amp P2 CONNECT TO GROUND SHIELD P2 P1 50 1 50 49 49 48 4B 47 47 46 46 45 45 44 44 43 43 42 42 4 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 3e 20 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 15 12 12 11 11 12 10 9 9 8 8 7 7 6 6 5 5 4 4 3 5 2 2 1 1
8. 90mA Typical 210mA Maximum 12 Volts 5 from P1 15 Typical 25mA Maximum 15 Volts 5 from P2 12 Volts 3 596 from P1 or 15 Volts 45 from P2 Note Note 1 c 13mA Typical 25mA Maximum See Note 1 1 The 12 volt power supplies are normally supplied through P1 logic interface connector Optionally jumper selectable on the IP the user may connect external 15 volt supplies through the field I O interface connector P2 ENVIRNOMENTAL Operating Temperature Relative Humidity Storage Temperature Non Isolated Radiated Field Immunity RFI Conducted RF Immunity CRFI Electromagnetic Interference Immunity EMI Electrostatic Discharge Immunity 50 Surge Immunity Electric Fast Transient Immunity EFT 0 to 70 C 40 to 85 C E Version 5 95 non condensing 740 to 125 C Logic and field commons have a direct electrical connection Complies with EN61000 4 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with error less then 0 25 of FS Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with error less then 0 25 of FS No digital upset under the influence of EMI from
9. 0 6kg packed TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 50 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area MIL G 45204 Type Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage or to AVME9630 9660 9668 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type II Grade C Connects to 9630 9660 boards within the card cage via f
10. 100 NI 170 Ld OA 21 5110 330 NO 3dAL NVdS 39NV3 2 2 1 2 z 1 NOLLOSTAS SONILLSS S9NILI3S 1fidNI INANI INANI 20v 27 2 ui iP AlddNS H3MOd HOLIMS HOLIMS 330033 53 Z ONY Lf JO SNId SNOILO313S AlddNS sbunes YOUMS did NOILO313S JONVY 90 1VNV m 020 0 lt 006 gt 1 1 1 1 SZ1Z 0 AQIS LN3NOdWOO 193NNOO LON OQ XINO 3SN AHOLOVJ SI 6 QNV v L SNOILISOd SONILLAS HOLIMS LINV4SSG NMOHS HOLIMS did E o Le ius NOILSOd 440 NI HOLIMS NOILISOd NO NI HOLIMS gt bez HOLIMS did zr _ AOVAYSLNI AOV4AYSLNI 21901 17 SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD FIELD 1 0 a a INTERFACE 52 p CALIBRATION VOLTAGES 2 he RANGE Wu SERIAL LINK MUX AA SELECTION 12 BIT gt DIP a gt LN SWITCH FT Se ADDRESS gt CONTROL LINES DATA BUS CONTROL J LOGIC N EXTERNAL TRIGGER INPUT C
11. This IP module supports both wait states generated by the IP module and Hold states generated by the carrier board SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board Acromag s AVME9630 9668 3U 6U non intelligent VMEbus carrier boards and Acromag s APC8620 series PCI bus carrier boards are supported A wide range of other Acromag IP modules are available to serve your signal conditioning and interface needs The cables and termination panels described in the following paragraphs are also available For optimum performance with the 12 bit IP320 analog input module Acromag recommends the use of the shortest possible length of shielded input cable Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The shielded cable is recommended for optimum performance with precision analog I O applications while the unshielded cable is recommended for digital cables are available in 4 7 or 10 feet lengths Custom lengths 12 feet maximum are available upon request Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 o
12. Typical Temperature Coefficient See specification of calibration voltages Ideal Maximum Programmable Calibration Voltages follow Value Tolerance Temperature 25 C Volts Calib Signal Volts Drift ppm C 0 0002 Auto 0 0000 Zero CAL2 12250 30004 06126 30002 _ Worst case temperature drift is the sum of the 15 ppm C drift of the calibration voltage reference plus the 5 ppm 9C drift of the resistors in the voltage divider Notes 2 Range assumes the programmable gain is equal to one Additional ranges are created with other gains Divide the listed range by the programmable gain to determine the actual input range Input signal ranges may actually fall short of reaching the specified endpoints due to hardware limitations For example if an input may reach zero volts or less a bipolar input range should be selected 3 These ranges can only be achieved with 15 Volt external power supplies The input ranges will be clipped if 12 Volt supplies are used typically to 9 Volt maximum inputs 4 Follow the input connection recommendations of Section 2 because input noise and non ideal grounds can degrade overall system accuracy For critical applications multiple input samples can be averaged to improve performance Accuracy is specified for the software conversion command Use of the external hardware trigger input with software polling may degrade accuracy Accura
13. 4 as required USE OF CALIBRATION SIGNALS Reference signals for analog input calibration have been provided to improve the accuracy over the uncalibrated state The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in precision analog front ends A comparison of the uncalibrated and software calibrated performance is shown to illustrate the importance of the software calibration Uncalibrated Performance The uncalibrated performance is affected by two primary error sources These are the Programmable Gain Amplifier PGA and the Analog to Digital Converter ADC The untrimmed PGA and ADC have the following performance PGA206AU 2259C Linearity Error is 0 005 Maximum i e 1 4 LSB Offset Error RTI is 1mv Typical 2 5mV Maximum Gain Error is 0 0196 typical 0 196 maximum for all gains ADC ADS8508 25 C Linearity Error is 0 5 LSB Maximum Unipolar Zero Error is 5 mV Maximum Bipolar Zero Error is 1 mV Maximum Full Scale Calibration Error is 0 5 of span Maximum SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Table 3 3 Maximum Overall Uncalibrated Error at 25 Max Table 3 4 Recommended Calib Voltages For Input Ranges ADC Offset Rec Low Rec High Input Range Range Error Input Calib Calib Volts Volts LSB Range Range Voltage Voltage Volts Volts VoltcaL Lo VoltCALH Volts Volts 5
14. Convert command or an external trigger input Bit 15 CTRIG in the Control Register can be used to determine if a conversion has been triggered either by software command or external trigger input Bit 14 Data Ready in the Control Register can be used to determine if a conversion has been completed If the Read ADC Data command is executed while the ADC conversion is taking place then the IP320A will institute wait states until the data is available up to 4 5 uS before providing the ADC data and completing the cycle Execution of the read command requires 2 wait states if the ADC conversion completed prior to initiating the read command The execution of this command will reset the CTRIG and Data Ready bits in the Control Register The 12 bits of data are left justified within the 16 bit word The four LSB s will always read as 0 Data format is Straight Binary A Reset will set all bits of this register to 0 MSB LSB D15 gt D4 D03 DO ADC DATA 0000 PROGRAMMING CONSIDERATIONS FOR ACQUIRING ANALOG INPUTS The IP320A provides two different methods of analog input acquisition to give the user maximum flexibility for each application The following sections describe the features of each and how to best use them Using the Separate ADC Convert and Read Commands Use of the separate convert and read commands is a straightforward and accurate way to acquire data This method is useful for most applications SERIES IP320
15. Maximum 12V 12mA Typical 15mA Typical 20mA Maximum 25mA Maximum 142V 8mA Typical 13mA Typical 20mA Maximum 25mA Maximum Finally note that the IP320 and the IP320A may not give the exact same data values when interchanged due to the differences in the hardware However all values will remain within the specified tolerances given in this manual SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or IP with one that is known t
16. A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Programming Example Separate ADC Convert amp Read NOTE For this example it is assumed that the external trigger input is NOT being used to trigger conversions 1 Write to the control register to configure the acquisition mode gain and channel selections 2 Delay to allow for input settling Execute the ADC Convert command 4 Write to the control register to configure the acquisition mode gain and channel selections for the next acquisition if they are different This may be done while the conversion is in progress because the ADC is in the hold mode 5 The ADC conversion takes several microseconds This time can be put to use for other purposes e g calibration of ADC channel data 6 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data 7 Repeat steps 3 6 as required to acquire additional analog input samples Note that the input settling delay does not have to be inserted since writing to the control register to configure for the next acquisition immediately after initiating the previous conversion will allow the input to adequately settle before the next conversion is started The overlapping of these tasks with the ADC conversion cycle is what gives rise to pipelined operation and maximum system throughput Using External Conversion Triggers External hardware
17. AT THESE PINS AS DO NOT CONNECTS CONNECTING THSE PINS MAY DAMAGE THE BOARD Control Register Configuration The control register is software configurable There are no hardware jumpers associated with it Control register bits are defined as logic low at reset and must be programmed to the desired gain acquisition mode and channel configuration before starting ADC analog input acquisition refer to Section 3 for details Analog Input Data Format The analog input data will appear as Straight Binary for all input ranges The following tables indicate the relationship between data format bipolar vs unipolar and the ideal analog input voltage to the module Table 2 3 Unipolar Straight Binary Analog Data Format Analog Input Voltage Unipolar Straight Binary Data For Table 2 3 it is assumed that the analog input range unipolar is O to 10 Volts i e with a programmable gain of 1 The 12 bit straight binary data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are zero and should be ignored in calculations made with the data returned from the IP module SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Table 2 4 Bipolar Straight Binary Analog Data Format Analog Input Voltage Bipolar Straight Binary Data Volts Hex 4 9976 FFFO 4 9951 FFEO 0 0024 8010 0 0000 8000 0 0024 7FFO 4 9976 0010 5 0000 0000 For Table 2 4 it is assumed that the anal
18. Acromag 4 Series IP320A Industrial I O Pack 12 Bit High Density Analog Input Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2005 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 783 A00L000 SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL KEY ANALOG INPUT 8 INDUSTRIAL I O PACK INTERFACE FEATURES SIGNAL INTERFACE INDUSTRIAL I O PACK PREPARATION FOR UNPACKING AND CARD CAGE
19. DE are both 0 differential channels 0 19 and calibration voltages 0 3 may be selected when MODE 1 is 0 and MODE O is 1 single ended channels 0 19 may be selected when MODE 1 is 1 and MODE 0 is 0 single ended channels 20 39 may be selected when both MODE 1 amp MODE 0 are 1 the Auto Zero input is selected regardless of any other bit levels 1 N N a 8 2 23 24 5 26 29 30 52 35 36 1_ 0 0 0 0 1 38 1 1 1 o 39 Auto X X X X X 1 Zero Mode Mode 0 Desired Bit Bit Chan 009 008 ed IER ADC Convert Command Write Base 10H The ADC Convert Command is a write only register will not respond to reads that is used to trigger a conversion The data written to this location should be all ones to reduce digital noise although the write action alone is sufficient to trigger the conversion Note that a write to this register during an A D conversion will have no effect Execution of this command requires 1 wait state D15 D00 FFFF NOTE FFFF means that all bits are programmed as ones Read ADC Data Read Base 20H Use the Read ADC Data command to read the results of the last ADC conversion This command should be used following the ADC
20. NS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series IP320A module is a 12 bit high density single size IP analog input board with the capability to monitor 20 differential or 40 single ended analog input channels The IP320A utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density It offers a variety of features which make it an ideal choice for many industrial and scientific applications as described below Model Operating Temperature Range IP320A 0 to 70 C IP320AE 40 to 85 C KEY ANALOG INPUT FEATURES e High Channel Count Monitors up to 20 differential or 40 single ended analog inputs acquisition mode and channels are selected via a programmable control register Up to four units may be mounted on a carrier board providing up to 80 differential inputs or 160 single ended inputs in a single System slot 12 bit Accuracy Contains an enhanced 12 bit successive approximation Analog to Digital Converter ADC with a 4 5uS c
21. ONTROL IP CONTROL REGISTER SIGNALS ADC DATA REGISTER ANALOG m DIGITAL COMMON COMMON ID PROM CPLD 15V SUPPLIES J1 amp J2 12V SUPPLIES SUPPLY SELECTION IP320A BLOCK DIAGRAM 4502 044 IP320 A SINGLE ENDED VOLTAGE INPUT CONNECTION DIAGRAM d CON SCHOO a SCH01 ee A ES1 1 io N CH39 n CY 6539 A I SENSE EARTH GROUND ANALOG COMMON DIGITAL CONNECTION AT va Y SHIELD COMMON POWER SUPPLY SEE NOTE 2 i mum TYPICAL SEE NOTE 1 1777 B DIFFERENTIAL VOLTAGE INPUT CONNECTION DIAGRAM 18528 CARRIER BOARD EN L ESO H 0 E 1 um 7 4 77 ESI DCHQ1 A CH1 CJ i DCHe1 25 E 77 DCH19 CH19 E l 00919 gt EARTH GROUND ANALOG COMMON DIGITAL CONNECTION AT COMMON POWER SUPPLY SHIELD eae NOTE 2 1 1 ae TYPICAL e SEE NOTE 1 NA gt SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE ROUND LOOPS 2 HERWISE BE FLOATING CHANNELS ALREADY COMMON TO AVOID GROUND LOOPS 450 1 4 amp 55 3 EXTERNAL SU S CAN BE USED BY J CONNECTED TO ANALOG COMMON JMPERING IT IS RECOMMENDED THAT THE SUPPLY COMMONS BE 18 SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD M2 x 6 gt FLAT HEAD SCREW THREADED M2 gt SPACER m
22. SPACE ADDRESS MAP This board is addressable in the Industrial Pack I O space to control the acquisition of analog inputs from the field The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP320A only uses a portion of this space The space address map for the IP320A is shown in Table 3 2 Note the base address for the IP module I O space see your carrier board instructions must be added to the addresses shown to properly access the I O space All accesses are performed on a 16 bit word basis DO D15 SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Table 3 2 IP320A I O Space Address Memory Map Odd Byte EVEN Byte D07 D00 LSB D08 CTRIG Data Not Not Not Not MODE MODE TE EE lee ODD Byte MSB LSB 007 oos pes oos oos pez bo ooo GsEL GSEL Not SEL CH3 CH2 CH1 Bit 15 When read the CTRIG bit indicates whether an ADC conversion has been triggered either by software command or external trigger input If the bit reads high the conversion could be taking place or has been completed CTRIG is cleared by reading the ADC data Writing to this bit position will have no effect Repeated Read ADC Data Bit 14 The Data Ready bit indicates if an ADC convert command has completed and valid data resides in the ADC Data Register If the bit reads high then Not Used valid data awaits in the ADC data re
23. Switching solenoids commutator motors and drill motors Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge and Level 2 4KV enclosure port contact discharge and European Norm EN50082 1 Not required for signal I O per European Norm EN50082 1 Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 SERIES IP320A INDUSTR IAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Radiated Emissions ANALOG INPUTS Meets or exceeds European Norm EN50081 1 for class equipment Shielded cable with connections in shielded enclosure are required to meet compliance Input Channels Field Access 40 Single ended or 20 Input Signal Differential Ended Voltage Non isolated Input Ranges DIP switch selectable Bipolar 5 to 5 Volts Bipolar 10 to 10 Volts Unipolar 0 to 10 Volts Programmable Gains Input Overvoltage Protection Input Input Bias Current Common Mode Rejection Ratio CH to CH Rejection Ratio A D Resolution Data Format left justified No Missing Codes A D Integral Linearity Error System Accuracy See Note 4 Maximum Overall Calibrated Eri Input Ran
24. cted value for input channel 0 16 Repeat steps 12 15 to re measure channel zero s data as desired Calibration Programming Example 2 Assume that the input range is 0 to 1 25 volts Channel 39 is connected single ended and corrected input channel data is desired From Tables 3 4 and 3 5 several calibration parameters can be determined Gain 8 From Table 3 4 VoltcAL 7 1 2250 volts CAL2 From Table 3 4 Voltc AL LO 0 6125 volts CAL3 From Table 3 4 Ideal Volt Span 10 0000 volts From Table 3 5 Ideal Zero 7 0 0000 volts From Table 3 5 The calibration parameters Countc ay jjj and Countca remain to be determined before uncorrected input channel data can be taken and corrected SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 1 To prepare to measure write to the Control Register 00H to setup the CAL3 acquisition mode and PGA gain 8 by writing 00D7H Note that not used bits are set to zero 2 Delay to allow for input settling Execute ADC Convert Command Base 10H 4 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 5 Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as Countcal o 6 To prepare to measure Countca write to the Control Register 00H to setup the CAL2 acquisition mode an
25. cy versus temperature depends on the temperature coefficient of the calibration voltage INDUSTRIAL 1 0 PACK COMPLIANCE This device meets or exceeds all written Industrial I O Pack specifications per ANSI VITA 4 1995 for 8MHz operation Electrical Mechanical Interface Single Size IP Module VO Space IOSEL 16 bit word read of 12 bit left justified ADC data 16 bit read write of control register conversion request write ID Space IDSSELY 8 bit Supports Type 1 32 bytes per IP Consecutive odd byte address Interrupt Space INTSEL Not Used SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Access Times 8MHz Clock ID PROM Read 0 wait states 250ns cycle Control Register Read 0 wait states 250ns cycle Control Register Write 1 wait state 375ns cycle Conversion Request Write 1 wait states 375ns cycle Read ADC Data Note 5 2 wait states 500ns cycle Note 5 The 2 wait states specified assume that the previous conversion has been completed and that data is available to be read If a conversion is in progress the command will institute wait states until the data can be delivered This could take up to 4 5uS 32 wait states maximum APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shi
26. d PGA gain 8 by writing OOD6H Note that not used bits are set to zero 7 Delay to allow for input settling Execute ADC Convert Command Base 10H 9 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word Repeat steps 8 and 9 several times e g 16 and take the average of the ADC results Save this number as 11 Calculate actual slope from equation 2 since all parameters are known e e 10 It is now possible to correct input channel data from any input channel using the same input range i e 0 to 1 25 volts with a PGA gain 8 Repeat steps 1 11 periodically to re measure the calibration parameters Countc A and CountcA as required 12 To prepare to measure channel 39 single ended write to the Control Register Base OOH to setup the single ended input channel 39 acquisition mode and PGA gain 8 by writing 0203 Note that not used bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word This data represents the uncorrected Count Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known Calculate the calibrated value Corrected Count This is the desired corrected value for input channel 39 Repeat steps 12 15 to r
27. dustrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 9668 or APC8620 21 non intelligent carrier boards via a flat ribbon cable Model 5025 550 x or 5025 551 x The A E connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial I O Pack modules Field signals accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG 16 Connections to Acromag non intelligent carrier boards P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 to 100 Shipping Weight 1 25 pounds
28. e measure channel 39 s data as desired 13 14 15 16 Error checking should be performed on the Corrected Count value to make sure that calculated values below 0 or above 4095 are restricted to those end points Note that the software calibration cannot recover signals near the end points of each range which are clipped off due to the uncalibrated hardware e g PGA and ADC The maximum corrected i e calibrated error is summarized in Table 3 6 as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 25 C Typical accuracies are significantly better 12 Table 3 6 Maximum Overall Calibrated Error 25 C Max Error LSB Span 2 1 Input Range Volts ADC Range Volts 4 25 006 8 29007 5 2 18 004 251025 4 21 005 0to 125 8 m 3214055 ___ ______3 1 0 076 P51 0 125 625 1 25 to 1 25 2 5 0 061 4 0 THEORY OF OPERATION This section describes the functionality of the IP320A circuitry Refer to the block diagram of Drawing 4502 044 as you study the following paragraphs ANALOG INPUTS The field interface the carrier board is through connector P2 Field analog inputs are non isolated This means that t
29. ed in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped 52 This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES NOT SHIP STORE NEAR STRONG 00 ELECTROSTATIC ELECTROMAGNETIC MAGNETIG OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD CARD CAGE CONSIDERATIONS pins are shorted together with a shorting clip OUT means the clip has been removed For a detailed drawing refer to 4502 043 Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified Table 2 1 Analog Input Range Selections DIP Switch Settings Desired ADC Input Range VDC Switch Settings ON Switch Settings OFF Required Input Span Volts Required Input Type IMPORTANT Adequate air circulation must be provided to prevent a tem
30. elded Type Flat Ribbon Cable 50 wires female connectors at both ends The cables are available in 4 7 or 10 feet lengths Custom lengths 12 feet maximum are available upon request Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Application Used to connect Model 5025 552 termination panel to carrier board 50 pin field connectors Length Last field of part number designates length in feet 4 7 or 10 feet standard It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For IP Carrier Boards Application To connect field I O signals to the In
31. er 00H to setup the CALO acquisition mode and PGA gain 1 by writing 0014H Note that not used bits are set to zero 7 Delay to allow for input settling 8 Execute ADC Convert Command Base 10H 9 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 10 Repeat steps 8 and 9 several times e g 16 and take the average of the ADC results Save this number as CountcA 11 Calculate m actual slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 10 to 10 volts with a PGA gain 1 Repeat steps 1 11 periodically to re measure the calibration parameters Countc A and CountcA as required 12 To prepare to measure channel 0 differentially write to the Control Register Base OOH to setup the differential input channel 0 acquisition mode and gain 1 by writing 0000H Note that not used bits are set to zero 13 Delay to allow for input settling 14 Execute ADC Convert Command Base 10H 15 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word This data represents the uncorrected Count Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known Calculate the calibrated value Corrected Count This is the desired corre
32. f ambient temperatures change to obtain the best accuracy Note that several readings e g 16 of the calibration parameters should be taken via the ADC and averaged to reduce the measurement uncertainty Calibration Programming Example 1 Assume that the input range is 10 to 10 volts Channel 0 is connected differentially and corrected input channel data is desired From Tables 3 4 amp 3 5 several calibration parameters can be determined Gain 1 From Table 3 4 Voltc AL HI 7 4 9000 volts CALO From Table 3 4 0 0000 volts Auto Zero From Table 3 4 Ideal Volt Span 20 0000 volts From Table 3 5 Ideal Zero 10 0000 volts From Table 3 5 The calibration parameters Countc A and CountcA remain to be determined before uncorrected input channel data can be taken and corrected 1 To prepare to measure Countc write to the Control Register Base 00H to setup the auto zero acquisition mode and PGA gain 1 by writing O300H Note that not used and don t care bits are set to zero 2 Delay to allow for input settling 3 Execute ADC Convert Command 10H 4 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 5 Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as Countca o 6 To prepare to measure Countc aj write to the Control Regist
33. ge PGA ADC Range Volts Gain Volts 0 044 0625 to 0 625 8 12510 125 8 __010 125_ 8 2 5 0 2 5 See Note 2 See Notes 2 amp 3 See Notes 2 amp 3 X1 X2 x4 x8 32 Volts with power applied 35V to 55 Volts unpowered 1000 MO Typical Typical 80dB Typical 60Hz 80dB Typical 60Hz 12 bits Straight Binary No Missing Codes 12 bit ADC 1 2 LSB Maximum The maximum corrected i e calibrated error is summarized in the following table as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 25 C Typical accuracies are significantly better ror 25 C Max Error LSB Span 1 8 2 1 0 051 2 9 0 071 2 5 0 067 100 410 10 to 10 2 5 0 061 3 2 0 078 2 2 0 055 pem 21 0051 a Oto 10 0 to 10 pe s 7 31 0 076 pom ru 5 1 0 125 15 Settling Time 20V step 5 2 5 to 0 0196 of FSR A D Conversion Time 4 5uS Maximum A D Triggers External and Software Maximum Conversion Rate 200KHz Maximum Recommended Conversion Rate 100KHz Maximum Input 0 2 LSB rms
34. gister from the previous conversion Data Ready is cleared by reading the ADC data register Writing to this bit position will have no effect Bits 13 10 Not used if read will return data written to those bit positions Notes Table 3 1 Bits 9 amp 8 Control the input acquisition mode as described in the following table 1 Registers appear in multiple locations in the memory map Acquisition Mode Bit D09 Bit D08 because of simplified address decoding these locations can Differential Input be ignored 19 amp CALO 3 2 The IP will respond to addresses that Not Used with an Single ended Input 1 active IP module acknowledge ACK The board will return CH0 19 0 for all address reads that are not used or reserved Single ended Input 1 CH20 39 This memory map reflects byte accesses using the Big Auto Zero Input Endian byte ordering format Big Endian is the convention used x 2 Auto Zero input is enabled by the mode bits in the Motorola 68000 microprocessor family and is the VMEbus overriding all channel selection bits convention In Big Endian the lower order byte is stored at odd byte addresses The Intel x86 family of microprocessors uses the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such installation of this module on a PC carrier board will require the use of the even address locations to acces
35. he field analog return and logic common have a direct electrical connection Care must be taken to avoid ground loops and excessive common mode voltage see Section 2 for connection recommendations These can cause measurement error and with extreme abuse circuit damage Analog inputs and calibration voltages are selected via CMOS analog multiplexers MUX s A software programmable control register contains gain acquisition mode e g single ended or differential and channel selection information to control the multiplexers Up to 40 single ended inputs can be monitored where each channel s input is individually selected along with a single sense lead for all channels Up to 20 differential inputs can be monitored where each channel s and inputs are individually selected Single ended and differential channels cannot be mixed i e they must all be single ended or differentially wired A Programmable Gain Instrumentation Amplifier PGA takes as input the selected channel s and inputs or and sense and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the control register The output of the PGA feeds the Analog to Digital Converter ADC The A D Converter is a state of the art 12 bit successive approximation converter with a built in Sample and Hold S H circuit The S H goes into the hold mode when a conversion is initiated This maintains the selected channel s vo
36. in assignments of P1 are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 6 Note that the IP320A does not utilize all of the logic signals defined for the P1 connector Logic lines NOT USED used by this model are indicated in BOLD ITALICS Table 2 6 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number GND LR 79 002 6 04 8 D5 9 ___006 70 D09 3 AA 1 Signal is active low 2 Line is reserved for factory programming BOLD ITALIC Logic Lines are NOT USED by this IP Model P1 of the IP module provides the logic interface to the mating connector on the carrier board see Table 2 6 This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly 3 0 PROGRAMMING INFORMATION ID SPACE Read Only 32 odd byte addresses Each IP module contains an identification ID PROM that resides in the ID space per the IP module specification This area of memory c
37. lat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 to 85 C Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packed 12 BIT HIGH DENSITY ANALOG INPUT BOARD SERIES IP320A INDUSTRIAL I O PACK vevo coSv SNOILVOO J43dNnfn SINGNI WOWIXVWN LOA 6 8 OL ATIVOIdAL 0351 38v S3NddNS 21 38 NIM S39NVH lfldNI SHL 53 3 VNN3IX3 61 HLM Q3A3IHOV 38 A TINO NYO SSONVY 3S3HL AVSSVIOG 3A08V 3HL NI NMOHS SV lfldNI 9QV 110 S OL 5 3HL ONILLAS HOLIMS did L10nv43Q SHL Q3ddlHS SI GYVOd8 JHL L 40 V 9 5 3 08V Wvaovid JHL NI NMOHS Sv 53114405 LIOA 21 9NILI3S YSAWAP 1 IHL HLIM Q3ddlHS SI QaivO8 JHL 6895 Let 01 010 SLIOA 61 SLTOA 21 3SN LON OG 793 O3XIN 38 LON GINOHS S3riddns ONY TIVNH3INI 87 1 69 lt Jojodig 02 0101 NI Ino NI 110 zd WNYSLX3 L10 S177 8 o g z 6 v c l G OL S
38. ltage constant until the A D Converter has accurately digitized the input Then it returns to the sample mode to acquire the next channel Once a conversion has been started the control register can be updated for the next channel This allows the input to settle for the next channel while the previous channel is converting which gives rise to the pipelined mode of operation and maximum system throughput SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD A miniature DIP switch on the board control the range selection for the A D Converter 5 to 5 10 to 10 or 0 to 10 Volts as detailed in Section 2 DIP switch selection should be made prior to powering the unit Thus all channels will use the same A D Converter range However the analog input range can vary on an individual channel basis depending on the programmable gain selection The logic interface provides 12 Volt supplies to the analog circuitry The 10 to 10 and 0 to 10 Volt A D Converter ranges will be clipped if these supplies are used typically to 9 Volt maximum inputs The user has the option of providing 15 Volt external supplies to fully utilize input ranges to 10 Volts These supplies are selected via hardware jumpers J1 and J2 as detailed in Section 2 Note that jumper selection should be made prior to powering the unit Further internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts The boa
39. nel configuration before starting ADC analog input acquisition Analog Input Range Hardware Jumper Configuration The ADC input range is programmed via hardware DIP Switch The DIP switch controls the input voltage span and the selection of unipolar or bipolar input ranges The configuration of the DIP switch for the different ranges is shown in table 2 1 A Switch selected as ON would be positioned to the side of the DIP labeled The DIP switch location is shown in Drawing 4502 043 Power Supply Hardware Jumper Configuration The selection of internal or external analog power supplies is accomplished via hardware jumpers J1 and J2 J1 J2 controls the selection of either the internal 12 12 Volt supply sourced from P1 connector or the external 15 15 Volt supply sourced from the P2 connector The configuration of the jumpers for the different supplies is shown in the table 2 2 IN means that the Assuming a gain of 1 These ranges can only be achieved with 15 external power supplies The input ranges will be clipped if 12V supplies are used typically to 9 V maximum inputs Table 2 2 Power Supply Selections Pins of J1 and J2 Power Supply J1J2 J1 J2 Selection 1 amp 2 2 amp 3 12 Volt Internal P1 15 Volt External OUT IN P2 Internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts WARNING J3 IS USED FOR FACTORY CALIBRATION ONLY TRE
40. nputs are applied differentially follow the differential channel labeling for each channel s and input leads Analog Input Noise and Grounding Considerations Differential inputs require two leads and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating it must be referenced to analog common on the IP module and be within the normal input voltage range Differential inputs are the best choice when the input channels are sourced from different locations having slightly different ground references See Drawing 4501 435 for analog input connections for differential and single ended inputs Table 2 5 IP320A Field I O Pin Connections P2 Pin Description Number Pin Description Number SCH22 DCHO2 6 SCH23 DCHO3 8 SCHO4 DCHO4 9 Indicates an Active Low Signal Single ended inputs only require a single lead per channel with a shared sense reference lead for all channels and can be used when a large number of input channels come from the same location e g printed circuit board The channel density doubles when using single ended inputs and this a powerful incentive for their use However caution must be exercised since the single sense lead references all channels to the same common which will induce noise and offset if they are different The IP320A is non i
41. o work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e X Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 624 1541 Fax 248 624 9234 Email solutions acromag com 14 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Physical Configuration Module iui Max Component Height Connectors P1 IP Logic Interface P2 Field Power 5 Volts 5 Single Industrial Pack 3 900 99 0 mm 1 800 in 45 7 mm 0 062 in 1 59 mm 0 314 in 7 97 mm 50 pin female receptacle header AMP 173279 3 or equivalent 50 pin female receptacle header AMP 173279 3 or equivalent
42. og input range bipolar is 5 to 5 Volts i e with a programmable gain of 1 The straight binary 12 bit data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are zero and should be ignored in calculations made with the data returned from the IP module CONNECTORS IP Field I O Connector P2 P2 provides the field I O interface connector for mating IP modules to the carrier board P2 is a 50 pin receptacle female header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 5 and normally correspond to the pin numbers of the front panel field I O interface connector on the carrier board you should verify this for your carrier board In Table 2 5 channel designations are abbreviated to save space For example single ended channel 0 is abbreviated as SCHOO the input for differential channel 0 is abbreviated as DCHO00 Both of these labels are attached to pin 1 but only one applies according to whether the input is single ended or differential i e if your i
43. oints that determine the straight line characteristic of Counter ro the analog front end for a particular range The recommended calibration voltage selection for each range is summarized in the The calibration voltages are used with the auto zero signal to m Gain VoltcAr gp 7 2 Gain The Programmable Gain following table Amplifier Setting Used See Table 3 7 Voltc AL High Calibration Voltage See Table 3 7 VoltcaLLo Low Calibration Voltage See Table 3 7 Actual ADC Data Read With High Calibration Voltage Applied Countcai Lo Actual ADC Data Read With Low Calibration Voltage Applied Ideal Volt Span Ideal ADC Voltage Span See Table 3 8 10 SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Actual Uncorrected ADC Data For Input Being Measured Ideal Zero Ideal ADC Input For Zero See Table 3 8 Count Actual Table 3 5 Ideal Voltage Span and Zero For Input Ranges Ideal Volt Ideal Span Zero Volts Volts Volts 5 to 5 5 to 5 10 0000 5 0000 Input Range 2 5 to 2 5 ae 1 25 to 1 25 1 0 625 to 10 to 10 5 to 5 2 5 to 2 5 1 25 10 1 25 0 0 0 to 1 25 The calibration parameters Countc A pj and for each active input range should be determined at startup and updated periodically e g once an hour or more often i
44. on is Base Add 0 complete and valid Bit 14 data can be read from the ADC Data Register Register Reset All values All values 0 Condition undefined Not Used R W Will not R W IP module respond responds w ACK All Address Space paw reads return 0 13 Wait State Changes IP320 IP320A ADC Convert Reg Write 0 wait states 1 wait state ADC Data Reg 3 wait states min 2 wait states min Read 68 wait states max 36 wait states max Hardware specification changes IP320 IP320A A D Converter ADS774KE ADS8508 Linearity Error 0 5 LSB 0 45 LSB Unipolar Offset 2 LSB 2 05 LSB Bipolar Offset Err 4 LSB 0 41 LSB F S Cal Error 0 25 0 5 Conversion Time 8 5us 4 5us PGA PGA203KP PGA206AU Linearity Error 0 012 0 005 RTI Error 2mV 24mV Gain 2 5mV Gain Error 0 2596 0 196 Input Setting Time 8 5us 10V step 5 2us 20 V step to 0 01 of F S Input Range Via Jumper J3 J4 Via DIP Switch Selection 1 Statistical Maximum values at 25 C Note that the change in the A D Converter has caused the uncalibrated errors to change The offset error has decreased significantly while the gain error increased Combined the overall uncalibrated error has decreased The calibrated tolerances remain the same Power 20 IP320A 45V 270mA Typical 90mA Typical 350mA Maximum 210mA
45. ontains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP320A ID information does not contain any variable e g unique calibration information ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PCI bus The IP320A ID space contents are shown in Table 3 1 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access ID space Execution of an ID space read requires 0 wait states Table 3 1 IP320A ID Space Identification ID PROM Hex Offset From ID PROM Base Address ASCII Character Equivalen Numeric Value Hex Field Description All IP s have AcromagID Code __ 32 IP Model Code Not Used Revision ___ 2 00 Not Used Driver ID Low Byte 13 Not Used Driver 15 0c Total Number of __ _____ a a ___ CRC i9to3F 00 NotUsed Notes Table 3 2 1 The IP model number is represented by a two digit code within the ID space the IP320A model is represented by 32 Hex
46. onversion time e High Speed The recommended maximum system throughput rate is 100KHz Multiple Input Range A Hardware DIP switch allows for selectable ranges for both bipolar and unipolar voltage inputs 5 to 5V 10 to 10V and 0 to 10V Programmable Gain Gains of 1 2 4 and 8 are programmable via the control register e Software Hardware Trigger Input acquisition can be triggered via software or by an external hardware input for synchronization to external events Precision References On board high precision voltage references provide the means for accurate and reliable software calibration of the module SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD INDUSTRIAL PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Four units mounted on a carrier board provide up to 80 differential or 160 single ended channels in a single System slot e LocalID Each IP module has its own 8 bit ID PROM which is accessed via data transfers in the ID Read space 16 bit I O Control register Read Write and A D Conversion Read are performed through 16 bit data transfer cycles in the IP module I O space e High Speed Access times for all data transfer cycles are described in terms of wait states typically O to 3 wait states are required for data transfer see specifications for detailed information Wait Hold State Support
47. perature rise above the maximum operating temperature 134 9 25678 10 to 10 2 5 6 9 1 3 4 7 8 0 to 10 1347 2 5689 The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The board may be configured differently depending on the application All allowable jumper settings are discussed in the following sections Jumper locations are shown in Drawing 4502 043 Power should be removed from the board when configuring hardware jumpers installing IP s cables termination panels and field wiring Refer to Drawing 4501 434 and IP documentation for IP configuration and assembly instructions Default Hardware Jumper Configuration A board shipped from the factory is configured as follows e Analog input range is configured for a 10V bipolar input span i e an ADC input range of 5 to 5 Volts Internal 12 Volt power supplies are used sourced from P1 connector Programmable software control register bits are set at logic low during power up reset The control register should be programmed to the desired gain mode and chan
48. r other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field connections of IP modules A through D for rear exit from the card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to AVME9630 9660 boards via a flat 50 pin ribbon cable within the card cage cable Model 5025 550 X or 5025 551 X IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 98 Me 2000 XPG applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual Visual Basic Borland Builder and others The DLL functions provide a high level interface to the carriers and IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VXWorks SOFTWARE Acromag provides a soft
49. rd contains four precision voltage references and a ground autozero reference for use in calibration These provide considerable flexibility in obtaining accurate calibration for any desired ADC range and gain combination when compared to fixed hardware potentiometers for offset and gain calibration of the ADC and PGA The calibration signals are selected multiplexed into the PGA like any other input channel LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 Not all of the IP logic P1 pin functions are used refer to Table 2 6 P1 also provides 5V and 12V to power the module A Complex Programmable Logic Device CPLD installed on the IP Module provides an interface to the carrier board per ANSI VITA 4 1995 It also produces the control signals for the A D Converter as well as channel and gain selection signals IP320 vs IP320A The IP320A is a drop in replacement upgrade for the IP320 The memory maps are identical and the analog tolerances either improved overall or remained unchanged on the IP320A Due to hardware differences between the two versions there are some slight changes in the operation and specification of the IP320A through they should remain unnoticed by the end user The following tables illustrate the differences between the IP320 and the IP320A Memory Map Changes IP320 IP320A Not Used Data Ready Indicates Control Register if an A D conversi
50. s the lower 8 bit GSEL1 GSELO data while on a VMEbus carrier use of odd addresses locations are required to access the lower 8 bit data The function of each register noted in Table 3 1 will be discussed in the following sections R W Control Register Repeated Control Register W ADC Convert Command Repeated ADC Convert Command R Read ADC Data N Aca o h m o m o A x e als Alo wld N N o o m c e m 5 m S m S MeN Bits 7 amp 6 Control the programmable gain setting as described in the following table Control Register Read Write 00H Bit 5 Not used if read will return data written to the bit The IP320A Control Register reflects and controls analog position input channel data acquisition functions This register must be Bit 4 The SEL HIGH bit acts as the MSB for analog input written read one word D16 at a time Execution of a Control channel selection As such its action is grouped with Register read write requires O 1 wait states At reset all bits that of bits 3 0 see following are set to 0 The function of each bit is described as follows SERIES IP320A INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Bits 3 0 Control the selection of analog input channels per the following table Note that the SEL HIGH bit and MODE bits are also shown to completely define the channel selection When MODE 1 amp MO
51. solated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IP320A input module External Trigger Input The external trigger signal on P2 is an active low input which may be used for synchronizing the ADC conversion of analog inputs from several IP modules to external events The external trigger must be a 5 Volt logic TTL compatible debounced signal referenced to analog common Note that the IP320A provides 125ns of debounce on the external trigger input The conversion is triggered on the falling edge of a normally high signal SERIES IP320A INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD The trigger pulse must be low for a minimum of 250nS to guarantee acquisition The external trigger may remain low for an indefinite period of time However it must return to a high state for a minimum of 250nS prior to a subsequent trigger See Section 3 for programming information IP Logic Interface Connector P1 The p
52. triggers are generated by the user via an external TTL compatible input through the field I O connector see Section 2 make sure that all pertinent voltage and pulse width constraints are met The conversion is initiated on the falling edge of the external trigger signal This type of conversion triggering is useful for synchronizing the ADC conversion of analog inputs e g several IP320A s to external events Precise time intervals between conversions can be achieved with an external timing device Note that external triggers that occur during an A D conversion cycle will be ignored Programming Example External Conversion Trigger NOTE For this example it is assumed that the external trigger input is being used to trigger conversions 1 Write to the control register to setup the acquisition mode gain and channel selections 2 Delay to allow for input settling 3 Poll Bit 15 CTRIG in the control register to determine when an ADC conversion has been triggered this assumes some prior knowledge in the application program that a hardware external trigger will occur for a particular channel s conversion 4 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data The Read ADC Data command will reset the CTRIG bit in the control register to prepare for the next external trigger 5 Repeat steps 3 4 for acquisition of the same input Otherwise repeat steps 1
53. ware product sold separately consisting of board VxWorks software This software Model IPSW API VXW is composed of VxWorks real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9660 9630 APC8620A 21A 8630 35 and ACPC8625 The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI boards IP MODULE QNX SOFTWARE Acromag provides a software product sold separately consisting of board QNX software This software Model IPSW API QNX is composed of QNX real time operating system libraries for all Acromag IP modules and carriers including the 9670 AVME9660 9630 APC8620A 21A 8630 35 and ACPC8625 The software supports X86 PCI bus only and is implemented as library of C functions These functions link with existing user code to make possible simple control of all Acromag IP modules and carriers 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damag
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