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ADA2000 User`s Manual - RTD Embedded Technologies, Inc.

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1. All Inputs Data Bus All Outputs Floating Iccse1 Vcc Supply Current Standby Freq DC CS Vcc All Other Inputs Pins Outputs Open Ow Input Capacitance 10 fe 1 MHz VO Capacitance 20 unmeasured pins Output Capacitance 2 pF returned to GND S A C CHARACTERISTICS 0 C to 70 C 5V 10 GND 0V 40 C to 85 for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE ymbol Parameter ES Om in 9 ee ol le T im Address Hold Time atterAOT o 9 ne wn 119122181217 wo Delay rom tao Dara Detay trom adaress m 3 me aT wma ening Tos f o pos e ne me omi NOTE 1 AC timings measured at 2 0V Vo 0 8V 3 96 intel 82054 A C CHARACTERISTICS Continued WRITE CYCLE Parameter EEES EA in Address Before WAY o o In CSsuweBere WR o lo wA Address Hold Time WAT o o T re Cow WA Pulse with Data Setup Time Betre WAT 120 95 wo Data Hold time AterWAT o 9 209 1 tay CLOCK AND GATE Symbol Parameter m tows High Pulse wath 609 ao tow Pulse width EAT s
2. lines digital input 10 BASE_ADDRESS 768 20 CONTROL_BYTE amp 9 30 OUT BASE_ADDRESS 27 CONTROL_BYTE 40 A_DATA INP BASE_ADDRESS 24 50 B_DATA INP BASE_ADDRESS 25 60 C_DATA INP BASE_ADDRESS 26 lines digital output 10 BASE_ADDRESS 768 20 CONTROL_BYTE amp 80 30 OUT BASE_ADDRESS 24 A_DATA 40 OUT BASE_ADDRESS 25 B_DATA 50 OUT BASE_ADDRESS 26 C_DATA For more information about the operation of the PPI see the data sheet included in Appendix C Programming the Programmable Interval The programmable interval timer PIT can be configured for a variety of timing and counting functions The PIT s versatility is supplemented by the use of header connector P3 for jumpering various 1 O options 3 Jumper Settings describes this connector The PIT consists of three independent 16 bit down counters The counters are initialized for operation in any of six modes by writing data to the appropriate control word for each counter Counter data is then written to or read from each of the counters by accessing three additional internal registers The data is set up a two byte format each byte serially accessible on the data bus The I O locations that control the PIT are listed below from Table 1 2 I PIHFUNCTION as as as a Counter 0 0 te Counter 1 i Counter 2 1 1 0 Control Word 1 1 1 Your specific re
3. 8 usec typ 9 usec max 1 bit typ 40 TTL CMOS compatible 24 buffered 16 unbuffered Relative accuracy 4 Full scale accuracy Non linearity Channel to channel isolation Chip selectable output range Settling time to 0 01 PA ORE A Dl dedos 1 bit max 3 bits max 1 bit max 34 dB typ 0 to 5V jumper selectable to 5V O to 10V jumper selectable to 10V 1 8 usec typ 3 3 max 1 2 bit typ 90 dB typ Miscellaneous I Os Connectors Environmental Size Power Requirements 12V 5V PC bus sourced Ground PC bus sourced Two external interrupt inputs Reset output A 260 mA SAO Cc 30 mA LAA 35mA Three 40 pin box headers one dedicated to analog signals only AII 120 signals exit through one rear panel slot in the PC Operating temperature 2 24 4 4 010 70 Storage 40 to 85 Humidity 0 to 90 non condensing A 3 875 99 With 4 uie itas 10 40 264 mm A 2 APPENDIX CONNECTOR ASSIGNMENTS ASSIGNMENTS Table B 1 Mating External I O Con
4. LIST OF ILLUSTRATIONS EE OO INTRODUCTION This manual shows you how to operate and provides technical data for Real Time Devices 2000 multifunction data acquisition board The ADA2000 features 12 bit high speed multichannel differential or single ended analog to digital conversion and two channels of digital to analog conversion This versatile interface allows your IBM PC XT AT or compatible computer to effectively operate in the real time environment of data acquisition and control to sense and generate both analog and digital signals Figure i 1 shows a typical laboratory setup using a PC for data collection LABORATORY WORKSTATION HARDWARE IBM PC or SOFTWARE Compatible Signal conditioning acquisition data reduction graphics analysis control data storage LABORATORY AUTOMATION Fig i 1 Typical Laboratory Setup The ADA2000 features high resolution 12 bit analog to digital and digital to analog converters digital I O and timer counters that provide flexibility for many applications Its six layer construction including separate power and ground planes enhances board performance and low noise characteristics It plugs directly into any unused expansion slot in the computer All external I O connections including PC bus sourced power are accessible at the rear panel of the computer when the board is installed Several of the ADA2000 s functions can
5. Ta GexReTme 2 2 ww Gate wiath ign o I 59 Gate Win om _ so 39 rs ws GaeSeupTmew OKT s 0 ion Gate Hold Time After soa som Too OwptDeayfomdKl mo 39 m os Output Delay rom Gate 15 10 wc CLK Delay tor Loading o s o s rs ins Gate Delay for Samping 5 so s wo OUTDeayfomModeWde 230 zo CLK Set Up for Count taton 59 4 amp o 49 NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwH May cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 100 tested Ta 25 6 If CLK present at Twc min then Count equals N 2 CLK pulses max equals Count 1 CLK pulse Twc min to max count will be either 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at min Counter will not be triggered at Two max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count value latched at Tc
6. and 44 PLCC 24 Programmable 1 Pins A m Available in EXPRESS m Low Power CHMOS Standard Temperature Range Completely Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82 55 is pin compatible with the NMOS 8255A and 8255A 5 in MODE 0 each group of 12 pins may be programmed in sets of 4 and 8 to be inputs or outputs MODE 1 each group may be progremmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 2C554 is fabricated on Intel s advanced CHMOS lil technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages de EC TIOMAL DATA BUS 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82 55 Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82 55 Table 1 Pin Description n y
7. oo 8 9 Program AOUT2 LSB Program AOUT2 MSB Convert Update AOUT1 AOUT2 C D E or F Clear AOUT1 AOUT2 10 1 ES or ts 18 Counter 0 Counter 1 Counter 2 Control Word Control Word NOTE x don t care setting Note that if you change any DIP switch settings to the CLOSED ON position as described in that chapter you must remove the corresponding buffer from the board Figure 1 4 shows the operation of PPI2 8255 PPI DIGITAL VO DIP SWITCH SHUNTS GROUP A GROUP B GROUP LSB A 4 4 VO CONNECTOR GROUP C MSB OPTIONAL VO BUFFERS amp PULL UP PULL DOWN RESISTORS Fig 1 4 PPI2 Functional Block Diagram Single in line resistor networks can be installed at the factory if ordered as an option or by the user in IC locations RN1 through RN4 on the left side of the board These networks allow the PPI2 digital I O lines to be pulled up or pulled down for certain applications These networks are connected to a voltage source pull up or ground pull down by jumper settings on header connector P13 Figure 1 5 showsa typical pull up resistor application Details on configuring the PPI circuitry are included in Chapter 3 Fig 1 5 Pull Up Resistor Block Diagram Installing the ADA2000 in Your Before installing the ADA2000 in your computer make sure that the base
8. ADA2000 User s Manual Gl Real Time Devices Inc Accessing the Analog World 1509001 and AS9100 Certified ADA2000 User s Manual FU REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 Copyright O 1991 by Real Time Devices Inc All rights reserved Printed in U S A Rev C 9234 TABLE OF CONTENTS Page INTRODUCTION How Use This 1 2 When You Need 1 2 CHAPTER 1 QUICK START GETTING YOUR ADA2000 RUNNING What Comes With Your 2000 1 1 Hardware 1 1 Functions You Can e 1 1 Setting the Base I O 2222 0 1 2 Digital VO PETENS 1 4 Installing ADA2000 in Your Computet c csccsssscsssssesssscsscessscecsscesssssessscsscsecsecenees 1 7 genen Nee 1 8 D mo Disk A e ete eva iaa 1 8 Backing Wp COULD e 1 8 Initializing Your ADAL
9. Figure 22 Minimum and Maximum initial Counts 3 95 Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero in Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex
10. 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A4 Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in Control Word Counter 0 LSB of count Counter 0 MSB of count Counter 0 Control Word Counter 1 LSB of count Counter 1 MSB of count Counter 1 Control Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 00 00 002002 Control Word Counter 0 Counter Word Counter 1 Control Word Counter 2 LSB of count Counter 2 LSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 MS8 of count Counter 1 MSB of count Counter 2 20000 a a a a oa gt NOTE struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be aftected as described in the Mode definitions The new count must follow the programmed count format lf a Counter is programmed to read write two byte counts the following precaution applies A program must not transf
11. 5 DATA FROM PERIPHERAL TO 8255 8255 TO PERIPMERAL DATA FROM 8255 8080 231256 26 Note Any sequence where WA occurs before AND 5 occurs before RD is permissible INTR IBF e MASK STB RD OBF e MASK e ACK WR WRITE TIMING READ TIMING DATA BUS BUS 2 7 IMPEDANCE 231256 27 231256 29 A C Testing inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic O Timing Measurements Are Made At 2 0V For 18 Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification Includes Jig Capacitance 231256 30 3 146 APPENDIX D CONFIGURING THE ADA2000 FOR SIGNAL MATH D 1 Jumper Settings When running SIGNAL MATH you have to change some of the ADA2000 s on board jumpers from their factory set positions Before using SIGNAL MATH on the ADA2000 board check the following jumpers P2 Base address P3 8254 timer counter I O configuration P4 PS amp P7 Interrupts End of Convert Monitor The board layout is shown in Figure D 1 LJ Ll or am or m Fig D 1 ADA2000 Board Layout P2 Base Address SIGNAL MATH assumes that the base address of your 2000 is the factory setting of 300 hex 768 decimal If you change this setting you must run the ADAINST program and reset the base address NOTE When us
12. ADA2000 Board Layout The functions which you can control through hardware Base I O address Analog input channel type Analog input channel voltage range and polarity End of convert monitor Analog output voltage range and polarity Digital hardware and software PIT timer counters hardware and software Interrupts The functions which you can control through software are Analog input channel selection Analog input gain selection Digital software and hardware PIT timer counters software and hardware Board initialization Setting the Base Address Starting with the base I O address BA the ADA2000 uses 28 consecutive address locations in your computer s I O space Table 1 2 lists the I O map for the ADA2000 It is important to recognize that some of your computer s I O address locations will already be occupied by internal I O and other peripherals If your ADA2000 board tries to use I O address locations already in use by another device in your system address contention will result Hence the board will not operate or at best will operate erratically I O address contention is one of the most common problems encountered when adding an interface device to your computer system To avoid this problem a base I O address jumper circuit is provided on the ADA2000 board By changing the position of the jumper on the header connector labeled P2 located just to the right of ce
13. SYSTEM POWER sv Power Supp SS 27 34 DATA BUS Bi directional tri state data bus lines connected to system data bus RESET RESET A high on this input clears the control register and all ports are set to the input mode WRITE CONTROL This input is low during CPU write operations PA7 4 37 40 41 44 PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch il IIA 3 125 intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems its function is that of a general purpose component to interface peripherai equipment to the microcomputer system bus The functional configu ration of the 82 55 is programmed by the system software so that normaily no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82 55 to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control bus
14. Pur Lo s o ourur wur e OUTPUT 1 o o o ourur output OUTPUT o j o 1 meur ourur 9 output Put 1 o 1 o ourur 10 iur OUTPUT 1 o 1 1 meur ourur weur eur i s o o meur weur 2 output o s weur meur 13 ourur INPUT o weur meut 14 eur OUTPUT lala 1 1 meur 15 wer MODE 0 Configurations CONTROL WORD 90 CONTROL WORD 62 2 0 0 0 0 0 D Os 4 0 0 0 CONTROL WORD 1 9 0 By 0 D 0 D 221256 10 3 131 82 55 MODE 0 Configurations Continued CONTROL WORD 44 2 De D BD 0 BB CONTROL wORD 95 0 D 0 0 0 D CONTROL WORD 06 0 04 0 D D 0 D CONTROL WORD 87 0 Ds D 0 0 o 3 132 CONTROL WORD a 5 Don 0 CONTROL WORD 00 D D D 0 0 D 0 D 1 2 68 11 1010 411 CONTROL WORD 610 5 0 0 0 D 5 CONTROL WORD 0 0 0 0 5 0 9 rere 231256 11 intel 82 55 MODE 0 Configurations Continued CONTROL WORD 612 D Os 0 0 0 D 0 CONTROL WORD 913 0 0 D 0 D 0 D Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring
15. The counter status format is shown in Figure 11 Bits 05 through DO contain the counters programmed Mode exactly as written in the last Mode Control Word OUTPUT bit 07 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system 06 Ds 02 Dy Do 07 NULL NOSE D Out Pin is 1 Out Pin is O Null count Count available for reading 05 Counter Programmed Mode See Figure 7 Huw a 71 0 De 1 0 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded nto the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value not reflect the new count just written The operaticn cf Null Count is shown in Figure 12 Command D7 Dg 05 D4 02 Dy Do AAA Description Read back count and status of Counter 0 Read back status of Counter 1 Status latched for Counter 1 111 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 Read back count of Counter 2 Count latched for Counter 2 1 1 Read back count and
16. A D End of Convert EOC Interrupt 11 EXTINT2 and PPI2 INTRA and INTRB 2 3 6 P6 End of Convert EOC Monitor Header Connector 2 3 6 P9 A D Converter Voltage Range Header 22 nenne 3 7 P10 D A Converter Voltage Range Header Connector 1 3 7 P12 Digital Header 4 3 7 Digital I O Buffers Shunts and Resistor 1 2 0 0061 2 00606 3 8 Mode 0 3 9 O AAA 3 9 UA A AAA retten ste 3 9 SE O 3 10 CHAPTER 4 PROGRAMMING YOUR ADA2000 Selecting an Analog Input 2 4 1 AAA O 4 1 Taking an A D Reading ii id atadas 4 1 Controlling the D A Converter 2224 0 nono 4 1 Programming the Programmable Peripheral Interfaces 44 4 1 Programming the Programmable Interval 44000000100 4 3 Hardware Intemipts dile 4 3 A D End of Convert EOC 220000 4 4 EPS nd 4 4 IA lados 44 CHAPTER 5 CALI
17. CWels 158 3 14 158 231244 10 GATE transition should not occur one clock prior to terminal count 1 17 2 nte 82 54 Writing new count while counting does not affect the current counting sequence lf a trigger is ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle in mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 1 similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above repeated indefinitely An initial count of results in square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by
18. It is also very important to note that the ADA2000 interrupt sources are TTL totem pole push pull type outputs they are not open collector Therefore do not attempt to connect one of these interrupts to any other interrupt output The following paragraphs describe the interrupts available on your ADA2000 board 3 4 4 EXTINT1 and INTRA Interrupts Header connector P4 is used to select PPI1 INTRA for connection to one of the computer s interrupt channels IRQ2 through IRQ7 EXTINTI is provided to accommodate an interrupt signal generated external to the ADA2000 and routed onto the board through external I O connector P15 see Table B 4 in Appendix B INTRA labeled 1PC3 on the board is generated by PPII This interrupt is generated during PPI mode 1 or mode 2 operation only One of these two signals can be jumpered to one of the available computer interrupt channels IRQ2 through IRQ7 by first placing a jumper horizontally across the pins of the signal chosen and then placing a second jumper horizontally across the pins of the selected IRQ channel Figure 3 5 shows header connector P4 with jumpers installed so that PPI1 INTRA is connected to IRQ2 P4 EXTINT1 1 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 Fig 3 5 Interrupt Header Connector P4 P5 PIT Output Interrupts Header connector PS shown in Figure 3 6 is used to jumper one of the three PIT outputs OUTO OUT1 or OUT to one of th
19. Os Dy 0 D Do BESSER 0 0 D D Dz D 0 LEPETT 678 IBF RER INTA 231256 21 Figure 16 MODE Combinations 3 138 82C55A Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for cortrol or status The remaining bits ars either inputs or outputs as defined by a Mode command During a read of Port C the state of all the Port C lines except the and STB lines will be placed on the data bus In place of the and STB line states flag status will appear on the data bus in the 2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to GROUP A ONLY MODE 0 OR MODE 1 ONLY gt gt gt O gt gt lt gt change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line programmed as an output inctuc 19 INTR and OBF can be written or an interrupt enable flag can be either set or reset Port C l
20. This pin can be horizontally jumpered to the CKx input on the right side of the connector in place of the XTAL source The ECx signals are brought onto the board through external I O connector P15 see Table B 4 in Appendix B Gate Inputs 5V This input if connected to the GTx input by placing a jumper horizontally between the two pins places the associated timer counter circuit in an enabled state at all times EGx This input can be horizontally jumpered to the GTx input on the right side of the connector to provide an external gate input instead of the 5 volts input The EGx signals are brought onto the board through external 1 O connector P15 see Table B 4 in Appendix B Counter Outputs COx This output can be horizontally jumpered to the corresponding OUT pin on the right side of the connector so that the clock output signal can be routed to external I O connector P15 see Table B 4 in Appendix B COx This output can be horizontally jumpered to the corresponding OUT pin on the right side of the connector to provide the inverse of the clock output signal to external 1 connector P15 see Table B 4 in Appendix B 3 3 CKx This input connects the output of one timer counter to the clock input of the next timer counter CKx is provided for TC1 and TC2 only and is connected to the output of the previous timer counter or TC1 by placing a jumper horizontally between the pins These connections ar
21. max CLK will not be reflected in the count value iatched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count vallue which is one least significant bit EXTENDED TEMPERATURE T4 40 C to 85 C for Extended Temperature Parameter T a Min we ETC _ Gate Delay for Sampling intel 82654 WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS om 231244 15 RECOVERY 231244 16 3 98 intel 82054 CLOCK AND GATE los too 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT 2 4 2 0 20 Dm 04 0 0 45 231244 18 Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Timing measurements are made at 2 0V for a logic 1 and 0 8V for a logic 0 231244 19 150 pF C includes jig capacitance 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint t l 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with ail intel and Most m Control Word Read Back Capability Other MICroproeessore m Direct Bit Set Reset Capability m High Speed Zero Wait State uS Operation with 8 MHz 8086 88 and Capability 1 0 901007108 Available 40
22. 1 O address has been properly selected and all the hardware settings have been configured to support your requirements This chapter explains how to control the base I O address Other hardware settings are set at the factory as listed in Table 1 1 and remain at their factory settings unless you change them The interrupts generated by your ADA2000 are disabled not connected when you receive your board If you intend to use the interrupts they must be configured appropriately before installing the board Information about these and other functions not covered in this chapter is provided in Chapters 2 through 4 Use these chapters as necessary to configure your board before installation To install your ADA2000 follow these step by step procedures 1 TURN OFF THE POWER TO YOUR COMPUTER FIRST Refer to the owner s manual for your computer and remove the top cover 2 Selectan unused expansion slot in which to install your board and remove its corresponding blank bracket from the rear panel of the computer by removing the screw at the top of the bracket 3 Before placing the board into the computer three ribbon cable assemblies must be installed on board connectors P8 P14 and P15 If you have purchased the ADA2000 cable set first install the twisted pair cable analog I O connector P8 Then install the standard cables on P14 and P15 Each cable is a 40 line external I O cable which extends through the connector slot in the rear panel of the c
23. 2 222 2 2 2 4 22 74 16 Pull up Resistor Block 2222 20 1 7 A D Conversion Word 2 2 2 22 2 1 12 ADA2000 Functional Block 2 2 4 4 2 1 EOC Timing 0 04 22 12 2 3 ADA2000 Board 400 3 1 DIP Switch ST u insbe 3 2 PIT VO Header Connector P3 8 3 3 PIT Functional Block Diagram 11 34 Interrupt Header Connector P4 4 2 3 5 Interrupt Header Connector 5 3 5 Interrupt Header Connector P7 44 4400 3 6 Interrupt Header Connector P11 eee eese eee eee ene eee n ette nnn 3 6 EOC Monitor Header Connector 2 24 42212 7 3 6 A D Converter Voltage Range Header Connector P9 3 7 D A Converter Voltage Range Header Connector 10 3 7 Digital I O Header Connector P12 sees ecce eene eese eee 3 8 2 3 8 PPI2 Port A Pull up Pull down Resistor Circuitry 3 10 PPI Mode Definition 440 4 2 ADA2000 Board adi 5 1
24. Any value resistor can be used however for pull up applications resistors of 10 kilohms or higher are recommended Table 3 2 PPI2 Resistor Networks When using resistor networks you must first determine which lines you want to pull up or down and then install the resistor networks according to Table 3 2 The PPI2 port label is stamped on the printed circuit board next to its RN component location for ease in determining the correct resistor network socket After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled 5V on one end and GND for ground on the other end The middle hole is common One three hole pad is located next to each of the four SIP IC sockets Figure 1 14 shows a blowup of the pads for Port A To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the 5V pin For pull downs solder a jumper wire between the common pin middle pin and the GND pin 8 3 NEL ar 9 Fig 3 14 PPI2 Port A Pull up Pull down Resistor 3 10 4 PROGRAMMING YOUR ADA2000 communication with the ADA2000 interface board is done by strobing data to and from the board using the YO reference instructions Most operations involve the transfer of data to or from the components internal re
25. Convert Monitor Jumper P6 0 4 Running ADAINST After the jumpers are set and the ADA2000 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running the ADAINST driver installation program After running the program open ADA2000 EXE from the Open a File menu You will see a screen similar to the screen shown in Figure D 5 below The factory default settings are shown in the illustration Y our settings may or may not match the default settings depending on whether you have made changes to these settings before Base Address The board s base address setting is entered in the upper right block as shown in the diagram The factory setting for all Real Time Devices boards is 300 hex 768 decimal The base address can be entered as a decimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC IT End of Convert Interrupt In this block enter the IRQ channel number which corresponds to your jumper setting on P7 Timer IT Timer Counter Interrupt In this block enter the IRQ channel number which corresponds to your jumper setting on P5 LabTech SW IT LABTECH NOTEBOOK Software Interrupt This sets the software interrupt address where LABTECH NOTEBOOK s labLINX driver is installed The factory setting is 60 This s
26. MHz 8086 88 and frequency 80186 188 Completely TTL Compatible m Handies Inputs from DC to 8 MHz 10 MHz for 82 54 2 Six Programmable Counter Modes Available in EXPRESS Binary or BCD counting Standard Temperature Range Status Read Back Command Extended Temperature Range m Available In 24 DIP and 28 Pin PLCC The Intel 82 54 is high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82054 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82054 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82 54 is fabricated on Intel s advanced CHMOS technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages DATA Dr Op am Bus GATE 0 ys s BUFFER 00 7 231 Dos 2L AD 12 3 5 LJ LI LJ LJ L2 UJ LJ OUT 1 OUTO GND NC OUTI GATE1CLK1 231244 3 PLASTIC LEADED CHIP CARRIER CONTROL COUNTER WORD REGISTER 2 SATE 2 231244 1 Figure 1 82C54 Block Dia
27. Mode 1 Operation When operating a group of lines in mode 1 some of the port C bits are used as handshaking signals Therefore the buffers that are installed at locations U22 and U23 must be removed and switch 53 must have all switches closed to allow for the transmission of these signals in both directions both to and from port C Buffers may still be used for ports A and B input or output with mode 0 operation buffers cannot be used for port A or port B if the mode 1 direction is changed dynamically under software control In this case the appropriate DIP switches must be closed for these ports and the corresponding buffers removed Mode 2 Operation This mode also uses some of the port C bits for handshaking signals In addition port A serves as a bidirectional data bus Therefore the buffers for ports A and C must be removed and replaced by DIP switch shunts Refer to Table 3 1 for the locations of the buffers and shunts for these ports Buffers may still be used for port B Resistor Networks The circuitry also includes provisions for pull up or pull down resistor networks for each of the four ports A B CL and CH however resistors can only be used when the port is configured as an input port The board provides IC locations through to accommodate SIP resistor networks for PPI2 s digital I O and RN4 are 10 pin SIPs and RN2 and RN3 are six pin SIPs Pin 1 is common to all resistors
28. TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 82054 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CW 18 LS6 3 FF FF FF FF FE FO 16 15843 EE CWs18 158 3 158 2 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again 3 94 After writing the Control Word and initial count the counte
29. Type Name and Function PORT A PINS 0 3 Lower nibbie of an 8 bit data output latch buffer and an 8 bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to AD and WA signals RD and WA are ignored otherwise ADDRESS These input signals conjunction RD and WA control the selection of one of the three ports or the control word registers Ay RD WR CS input Operation Read po fof of 1 _ Pora DataBus 1 o PetB DaaBus o o Potc Datasus o ControWord Data Bus Output Operation Write 1 Data us PorA DataBus PorB pi fo 1 0 0 DataBus Porc 1 ot 0 DataBus Control__ X x x x 1 DataBus 3 State tl 1 11 _OmmBur2 sum _ 7 4 PORT PINS 4 7 Upper nibble of 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be d vicad into two a Lit ports uncer tne mode conic Each 4 bit port contains a 4 bit tatch and it can be used tor the control signal outputs and status signal inputs in conjunction with ports and PORT PINS 0 3 Lower nibble of Port C PBo 7 20 22 PORT B PINS 0 7 8 bit data output latch buffer and an 8 24 28 bit data input buffer Was
30. be readily adapted for your specific requirements Through programming and or jumper or switch settings made on the board you can Select the base I O address Choose 8 differential or 16 single ended analog input channels Select the active channel Select the channel gain Select the analog input voltage range and polarity Select the analog output voltage range and polarity Control 40 TTL CMOS compatible digital I O lines Control three 16 bit 8 MHz timer counter circuits the programmable interval timer Monitor the A D conversion using the end of convert EOC signal Generate interrupt signals Many of these functions are set up at the factory based on typical data collection requirements and customer specifications when ordering Therefore you can successfully install and run the ADA2000 with minimal understanding about changing and controlling them On the other hand you may want to understand everything about your board so that you can effectively use each feature With this in mind this manual provides basic information to get the board up and running as well as detailed information for a full understanding of each function Thi nual This manual is designed to help you install and get your ADA2000 running quickly while also including sufficient detail about each board function Begin by reading Chapter 1 in order to use your board as quickly as possible This chapter and the accompanying demonstration software inclu
31. bracket back in place with the screw and put the cover back on your computer Now your board is ready to be connected via the external connectors at the rear of the computer After these connections have been made the board is ready for operation The Software The ADA2000 operates under software control Programming includes the analog input channel selection and gain control of the the A D and D A conversions the programmable peripheral interfaces and PPI2 and the programmable interval timer The analog input channel and gain selections taking an A D reading and controlling the D A converter are covered in this chapter Digital I O control through PPI1 and PPI2 and control of the programmable interval timer are more complex and are described in Chapter 4 Programming Your ADA2000 Regardless of what programming language you use you can write programs that control the ADA2000 board The demonstration disk which accompanies your ADA2000 contains examples in Turbo C Turbo Pascal and BASIC Nearly all modern MS DOS based PC languages have I O reference instructions These are the instructions to control the data transfers to and from the 1 O ports Consult your programming language reference to find these instructions for your favorite language Listed below are the YO reference instructions used by some common languages BASIC TURBO PASCAL TURBO C input INP Port inportb output OUT Port outportb Demo Disk Included with you
32. case of the interrupt signals are disabled Therefore you do not have to do any further set up of the board in order for it to operate in your system as described in Chapter 1 The descriptions in this chapter allow you to change factory settings or to tailor your board to take full advantage of its built in versatility There are a DIP switch and several header connectors which allow you to control various board functions In addition there are buffers three shunt DIP switches and resistor networks associated with one of the programmable peripheral interfaces PPI2 which enhance the capability of this device s digital I O These are shown in the board layout of Figure 3 1 and are presented as follows 1 Analog Input Signal Type DIP Switch P2 Base I O Address Header Connector P3 Programmable Interval Timer PIT I O Header Connector P4 P5 P7 and P11 Interrupt Header Connectors P6 End of Convert EOC Monitor Header Connector P9 A D Converter Voltage Range Header Connector P10 D A Converter Voltage Range Header Connector P12 Digital I O Header Connector Digital I O Buffers Shunts and Resistor Networks HAHET Fig 3 1 ADA2000 Board Layout 3 1 S1 Analog Input Signal DIP Switch DIP switch S1 shown in Figure 3 2 configures the multiplexers for single ended or differential inputs and selects a unipolar or bipolar input voltage range The first three switches on S1 o
33. channels are fixed For the ADA2000 DMA is not used and should be left blank Gain and loss are provided so that you can make adjustments for external gain or loss as described above for the A D parameters For a bipolar output range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D 6 APPENDIX E CONFIGURING THE ADA2000 FOR ATLANTIS Jumper Settings When running ATLANTIS you have to change some of the ADA2000 s on board jumpers from their factory set positions Before using ATLANTIS on the ADA2000 board check the following jumpers P2 Base address P3 8254 umer counter I O configuration P4 PS amp P7 Interrupts P6 End of Convert Monitor The board layout is shown in Figure E 1 aar L2 ace ar jam am m Fig E 1 ADA2000 Board Layout P2 Base Address ATLANTIS assumes that the base address of your ADA2000 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base address to be entered in decimal notation P3 8254 Timer Counter I O Configuration The 8254 must be configured with the six jumpers placed between the pins as shown in Figure E 2 After setting the jumpers verify that each is in the proper location Any r
34. coun ter s The command is written into the Contro Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 A1 11 D Ds Ds 04 02 1 1 count CNT 2 1 Latch count of selected counter s Latch status of selected counter s Select counter 2 Select counter 1 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the intel 82654 count all but the first ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter
35. goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count ot N OUT does not go high until N 1 CLK pulses after the initial count is written lf a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 pulses after the new count of N is written an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 58 4 fe FE 158 3 0 158 3 e EA GATE 188 2 231244 8 The Followi
36. here Note the importance of this setting with respect to the possibility of address contention with other devices in your computer Be sure to examine this possibility if you experience board failure when you first attempt to operate the board in your computer P5 Programmable Interval Timer PIT Header Connector Header connector P3 shown in Figure 3 3 controls the programmable interval timer PIT The PIT contains three independent 16 bit timer counter circuits as described in Chapter 2 Each timer counter has three I O signals associated with it a clock a gate and an output P3 can be configured in a number of ways to provide maximum versatility in applying this device to your particular application Each timer counter is factory set for XTAL clock input 5V gate input and CO output Figure 3 4 shows a block diagram of the PIT For ease in configuring this circuitry the header connector is partitioned into three functional groups TCO TC1 and TC2 which correspond to timer counter 0 timer counter 1 and timer counter 2 respectively These designations also correspond to the manufacturer s designations as shown on the data sheet included in Appendix C Starting from the top of P3 the first group of pins on the right side are labeled CKO GTO and OUTO the three I O signals for TCO The signals on the left side for TCO are labeled XTAL ECO 5V EGO COO and COO this signal has a bar over top of the signal name on the board a
37. in this mode and any port can be configured as an input or an output The outputs are latched gt the inputs are not latched In mode 1 the four ports are grouped into two groups Each group contains one eight bit data port port A or port B and one four bit control data port port C lower or port C upper which is used for control and status of the eight bit port The eight bit data port in each group can be configured as an input or an output Both inputs and outputs are latched In mode 2 port A is an eight bit bidirectional bus and port C isa five bit control port Port B cannot be used in this mode but is available for use in mode 0 or mode 1 while port A is in mode 2 Both inputs and outputs are latched Each PPI is configured by writing a control word to the appropriate I O address location as described in Chapter 4 Programming Your ADA2000 The control word can also be used to individually set or reset the port C bits This feature allows any bit of port C to be set or reset without affecting the other port C bits The data sheet included in Appendix C explains this feature The PPIcan also be used to generate interrupts in mode 1 or mode 2 operation In these modes the interrupt enable INTE mask is used to enable the INTRA and INTRB interrupt signals Note that the INTRB signal for PPI cannot be used since port B of this PPI is always configured as mode 0 output and is reserved for channel selection and gain control Interrupt fu
38. iow to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of PCs input Operations STB Strobe Input A low on this input loads data into the input latch Input Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with Controlled by bit set reset of PC4 3 136 intel 82 55 CONTROL WORO Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 PERIPMERAL Uus DATA FROM 82 55 TO PERIPHERAL 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before a nd 518 occurs before RD is permissible INTR IBF e MASK e STB e RD e MASK e WR 3 137 nte 82 55 MODE 2 AND MODE O INPUT MODE 2 AND MODE 0 OUTPUT CONTROL WORD D 0 0 0 0 Do CONTROL WORD D 0 D Dj D D 0 OO 20 1 INPUT INPUT 0 OUTPUT 0 OUTPUT MODE 2 AND MODE 1 INPUT MODE 2 AND MODE 1 OUTPUT CONTROL WORD CONTROL WORD 0 9
39. n this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a Count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral 1 ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ag Ay connect to the Ao A1 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an intei 8205 for larger sys tems COUNTER 0 COUNTER 1 COUNTER 2 OUT GATE CLK OUT GATE CLK OUT GATE CLK Figure 6 82C54 System Interface ntel 82054 OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format 5 0 1 R 0 Ay Ao 11 D De 05 D4 Programming the 82C54 Counters are progr
40. range ee Offset TRS Full Scale TR6 4 99878 volts 4 99634 volts 0000 0000 0001 1111 1111 1111 Table 5 1 provides a reference for the ideal input voltage for the A D converter for each bit weight in each voltage range This table shows the ideal full scale all ones value in the first line and decrements by one bit weight each line thereafter Note that these values are for 12 bit A D conversions and are not valid when using the converter to perform more rapid eight bit conversions Note that the voltage values in the table are in millivolts Table 5 1 A D Converter Bit Weights umma pee tae iit A D Bit Weight 4095 Full Scale i 9997 6 2048 5000 0 1024 2500 0 512 1250 0 625 00 312 50 156 250 78 125 39 063 19 5313 9 7656 4 8828 2 4414 0 0000 Four trimpots TR1 through TR4 are used to adjust the gain circuitry one for each of the gains 2 4 8 and 16 To calibrate this circuitry apply an input voltage of 39 063 millivolts to the input of channel 1 Next by writing the correct word to the BA 1 I O location set the gain to 2 and adjust trimpot TR1 to obtain the 12 bit A D converter output for your board s voltage range as listed in Table 5 2 Then repeat this procedure for each of the remaining three gain settings adjusting the appropriate trimpot until achieving the correct value listed in the table Table 5 2 A D Converter Readings for Gain
41. set to be monitored through PA7 on P6 EOC signal is low logic 0 during a conversion Figure 2 2 shows the EOC timing diagram Also the three state A D output buffers remain in a high impedance state and therefore data cannot be read While a conversion is in progress any transitions of the digital inputs which control the conversion will be ignored so that the conversion cannot be prematurely terminated or restarted Once the conversion is complete EOC is now high or logic 1 the A D data can be read in two bytes the MSB and the LSB in any order For a 12 bit conversion the data is left justified in a 16 bit word In the case of an eight bit conversion the data is completely contained in the eight bit MSB Refer to Chapter 1 Taking an A D Reading and the demo disk for more information about using the A D converter 2 2 os er AR ws Hr EOC ccc f Data MM JS 2 Fig 2 2 EOC Timing Diagram Dieital to Analog ion Circuit By providing adigital to analog D A conversion capability the ADA2000 interface board can output the digitized data asanalog voltages to be displayed on strip charts oscilloscopes and other such devices The data can be output slow or fast to support specific requirements The D A conversion circuitry receives 12 bit digital words mapped into a right justified two byte data field in its two independent channels and converts them to voltage outputs D A
42. signal be used in a number of ways One way isto use this line to monitor the A D conversion status Setting up the EOC signal to be monitored involves configuring bit 7 of PPI1 port A or port C as an input line and connecting the EOC signal to it This procedure is detailed in Chapter 3 Jumper Settings The EOC signal is factory set to be monitored through 7 on header connector The general algorithm for taking an A D reading is 1 Start a 12 bit conversion by writing to base_address 4 or 6 out base_address 4 0 Note that the value you send is not important The act of writing to this I O location is the key to starting a conversion 2 Delay at least 20 microseconds or monitor PPI1 Port A or C bit 7 for a transition Polling permits the fastest data acquisition 3 Read the least significant bit from base_address 5 or 7 isb inp base_address 5 4 Read the most significant bit from base_address 4 or 6 msb inp base_address 4 5 Combine them into the 12 bit result by shifting the LSB four bits to the right The MSB must also be weighted correctly result msb 16 Isb 16 For a 12 bit conversion the A D data read is left justified in a 16 bit word with the least significant four bits equal to zero as shown in Figure 1 6 Because of this the two bytes of A D data read must be scaled to obtain a valid A D reading Once it is calculated the reading can be correlated to a volta
43. status of Count latched for Counter 1 Counter 1 but not status Read back status of Counter 1 CAUSES Null count 1 THIS ACTION A Write to the control word register 11 B Write to the count register 121 New count is loaded into CE CR gt Null count 1 Null count 0 1 Onty the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 the counter is programmed for two byte counts least significant byte then most significant byte nuil count goes to 1 when the second byte is written Figure 12 Null Count Operation multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads ail but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched statu
44. support a 10 volt range 0 to 10 volts or 5 to 5 volts or across the pins marked 20V to support a 20 volt range 10 to 10 volts The setting of this jumper coupled with the setting of switch 51 4 which selects a unipolar or a bipolar range determines the input voltage range of the A D converter P9 is configured at the factory according to the customer s specifications for the input voltage range The valid settings of P9 and 51 4 are summarized in the table below P9 Fig 3 10 A D Converter Voltage Range Header Connector P9 P10 D A Converter Voltage Range Header Connector Header connectorP10 shown in Figure 3 11 is used to select the output voltage polarity of each of the two D A converter channels and AOUT2 Each channel can be independently configured as a unipolar output or abipolar output To select the polarity for each channel install a jumper vertically across either the unipolar pins or the bipolar pins for the corresponding channel Note that each channel must have one jumper installed in order to function properly The outputs are factory setto match the specified A D input polarity If you reconfigure the board for a different output range than that specified when the board was ordered then you must recalibrate the D A converter for the new range according to the instructions in Chapter 5 AOUTI AOUT2 B Fig 3 11 D A Co
45. switch for those lines has all of its switches set to the OPEN position Then verify that the buffer is installed according to Table 3 1 Finally make sure that the jumper on connector P12 is positioned to correspond with the direction that the buffer is to be configured The following sections describe the conditions for each mode when DIP switch shunts must be used in place of the PPI2 buffers Mode 0 Operation If the direction of a port configured for mode 0 operation is changed dynamically through software all of the switches on the corresponding switch must be set to the CLOSED position and the buffer must be removed for that port This is required because the buffers are hardware configured for a particular direction using a jumper at P12 Therefore their direction cannot be changed through software After closing the DIP switches carefully remove the corresponding buffer from the printed circuit board Locate the PPI2 port that requires a DIP switch shunt in Table 3 1 then note the component labels of both the buffer and the associated DIP switch to verify that all settings are as desired In the event that shunts are required for only one half of port the switches on DIP switch 3 can be closed in groups of four Determine their positions from Table 3 1 then close the appropriate group of switches Only the buffer corresponding to the half of port C that requires shunts must be removed refer to the table for its location
46. the RD input tells the 82 54 that the CPU is reading one of the counters A low on the WR input telis the 82 54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ag 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to detine the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command Bus BUFFER 2 gt 2 z z z 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82054 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched
47. the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability OV TA 40 C to 85 for Extended Temperture syms parameter unte Testconations 9 v input ign eo voe v IC IET Veo 2 BEES Input Leakage Current Vin to OV Note 1 lorL Output Float Leakage Current Vin to OV Note 2 Note 4 IPHL Port Hold Low Leakage Current 300 Vour 1 0V Port A only 2 5 mA lon 100 pA ne 300 Vout 3 0V Ports A 5 C Vour 0 8V Vour 3 0V Te foe Voc 5 5V Vin or GND Port Conditions Open High Open Only With Data Bus High Low CS High Reset Low Pure inputs Low High 3 141 intel 82C55A 25 C Voc GND OV Input aime e Unmeasured pins 1 2 5 NOTE 5 Sampled not 100 tested A C CHARACTERISTICS 0 to 70 C 5V 10 GND OV 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE ressas o m Adress Hold o s wa J m v tao 9 v Cor m cover Time xo ns WRITE CYCLE HM 2 i
48. x positions control the direction of the remaining 16 digital I O lines available on PPI1 These lines can be configured as inputs outputs or in other more complex configurations For example when the control byte bit pattern is 100000000 decimal 128 the ADA2000 is initialized as follows out base_address 3 128 When this value is used to initialize the ADA2000 the eight port C lines of PPI1 will all be configured as outputs You can transfer data to these lines with the command out address 2 data If instead the decimal value 137 1000 1001 is used to initialize the ADA2000 the port C lines will be set up as inputs You can input data from port C with the command data inp base_address 2 Note that port A bit 7 of PPI1 is factory set to monitor the end of convert EOC signal PPI must be programmed so that port A is an input if you are going to monitor the EOC signal through PA7 The control byte must then conform to the general form of 1xx1 00 where the underlined 1 is the data bit which sets up port A as an input A functional description of the PPIs is contained in Chapter 2 Functional Description and hardware configurations are described in Chapter 3 Jumper Settings Information about how you can control the digital I O lines is contained in Chapter 4 Programming Your ADA2000 and is not covered here because of its complexity As mentioned earlier the eight lines of port B on PPI
49. 1 are used to select the analog input channeland gain The four LSBs PB for Port B 0 through PB3 control the channel selection and the four MSBs PB4 through PB7 control the gain selection The bit assignment of this port is MSBs LSBs 7654 3210 PPI Port Base Address 1 gain select channe select 0000 1 0000 channel 1 0001 2x 0001 2 0010 4 0010 0100 8 0011 1000 16 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 15 1111 channel 16 After the ADA2000 is initialized port B register is loaded with the default setting of 0000 0000 This selects channel 1 as the input channel with a gain of 1 To change this value for example to a gain of 2x on channel 16 enter these commands BA 1 hex selects port B 0001 1111 sets gain to 2x and channel to 16 Recall that the board s default channel setting is eight differential channels Therefore only the channel select binary values for channels 1 through 8 apply Channels 9 through 16 are used in the single ended channel mode only Now your board is initialized and ready to operate The following sections describe how to select the analog input channel set the input gain take an A D reading and control the D A converter Mastering these operations will allow you to effectively use your board for data acquisition applications i I 1 After the ADA2000 has been initialized you can sel
50. BRATION PROCEDURES Required E 5 1 ada 5 1 Unipolar CAIDA 5 2 Bipolar TEE 5 2 Gain Circuitry CA 5 3 DA CAD ee 5 3 Unipotar Calibrations 5 3 Bipolar Calibration tds 54 APPENDIX A ADA2000 5 2 222222 2 4 0 700 A 1 APPENDIX B Connector Pin B 1 APPENDIX C Component Data 222222 2 4 2 1 APPENDIX D Configuring the ADA2000 for SIGNAL MATH D 1 APPENDIX E Configuring the ADA2000 for E 1 APPENDIX F Warraufy uices ad veste aea F 1 ii 2 1 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 4 1 5 1 Page Typical Laboratory 5 0 2 0 0 1 1 ADA2000 Board 1 2 Base I O Address Header Connector 2 1 4 8255 PPI Functional Block 4 4 2 22 22 1 1 4 PPI2 Functional Block
51. Calibration Trimpot 10 Volts 0 to 10 Volts TRI 1000 0001 0000 TR2 1000 0010 0000 TR3 1000 0100 0000 TR4 1000 1000 0000 The D A converter can be used in either a unipolar or a bipolar configuration Each has a different calibration procedure Both D A converter channels are factory calibrated for outputs which are set to match the specified A D input polarity If you are verifying unipolar output accuracy follow the unipolar calibration procedure below If you have bipolar outputs follow the bipolar calibration procedure below Unipolar Calibration Two adjustments are necessary to calibrate the D A converter for full scale unipolar operation one for each of the two converter channels This procedure uses trimpots TR8 and TR9 to make the adjustments The full scale adjustmentcalibrates the reference voltage used by the D A converter to compensate for the analog outputs Calibration is accomplished by monitoring the output voltage of each channel at external I O connector P8 and adjusting the appropriate trimpot The analog output its P8 pin assignment and its associated trimpot are Output Trimpot P8 Pin Assignment AOUTI TR9 33 SIGNAL 34 GND AOUT2 TR8 35 SIGNAL 36 GND Program the D A converter to output a full scale voltage by writing XFFF to base address locations BA 8 and BA 9 for AOUT1 and A and B for AOUT2 Use the digital voltmeter to monitor the output voltage present between the appr
52. Converter The D A converter consists of two closely matched 12 bit current output D A converters in one monolithic IC to provide twoanalog output channels available at external I O connector P8 By using dual converters in a single package excellent thermal tracking and monotonicity across the 12 bit range are maintained Both D A converter channels are internally double buffered and can be updated simultaneously to prevent voltage glitches on the outputs Both converters support a 5 or 10 volt unipolar or bipolar output voltage range depending on the board configuration The two converters are identical 12 bit multiplying D A converters each with two pairs of input registers to allow simultaneous updating of both channels A conversion is initiated by first loading data into the first pair of registers This data is contained in two bytes eight bits in the LSB and four bits in the MSB which are written into the registers as described in Chapter 1 Controlling the D A Converter After the inputregisters are loaded an update command written to the D A converter starts the actual conversion process The output of the converter is a current value which accurately represents the 12 bit data word Both channels can be cleared by writing to the appropriate I O address location Output Amplifiers The D A converter s current output from each channel is fed through a high speed precision monolithic operational amplifier where itis converted into a pro
53. Converter See this section in Chapter 1 P ing the P ble Peripheral Interf Each programmable peripheral interface has three eight bit parallel I O ports port A port B and port C which can be configured for a variety of applications PPI1 has 16 lines available at external I O connector P15 for YO use the eight bits of port B 0 7 are used for channel selection and gain control and cannot be used for other functions PPI2 has all 24 lines available at external I O connector P14 The PPI ports can be operated in one of three modes The mode of operation and the signal direction of each port input or output are controlled by an eight bit control word written to an internal register Two bits define the mode selection mode 0 mode 1 or mode 2 Four bits configure the I O direction one bit to control PAO PA7 one bit to control PBO PB7 one bit to control PCO PC3 and one bit to control PC4 PC7 Port C is divided into two four bit fields so that it can provide status and control for ports A and B if desired in your application The control word is defined in Figure 4 1 Each PPI is configured by writing a control word to the PPI s internal control register Upon power up all ports are configured as mode 0 inputs is written to during board initialization so that port B is set up as a mode 0 output to configure it for channel selection and gain control functions Chapter 1 Initializing Your ADA2000 describes this pro
54. Figure 4 Note After the reset is removed the 82 55 can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any 1 structure For instance Group can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis PC PCy PAPA UO CONTROL PA OR 1 0 unii MODE 2 8 A uo ree BIDIRECTIONAL r M CONTROL rts 231256 5 Figure 5 Basic Mode Definitions and Bus Interface CONTROL WORD zu PORT LOWER 1 0 OUTPUT PORT 1 INPUT OUTPUT MODE SELECTION 0 MODE O MODE 1 PORT C UPPER Y INPUT OUTP
55. Jumper Settings details how to change these settings Note that only one jumper should be installed for each channel Whenever the voltage range or polarity is changed the D A converter should be recalibrated as described in Chapter 5 Calibration Procedures Loading the D A Converter Data Each D A channel has two eight bit internal input registers which receive the data for the D A conversion The channels are programmed independently by writing data to these registers The D A converters used on the ADA2000 board have a resolution of 12 bits Two write operations are required to load the 12 bit data field into these registers One register loads the least significant byte of the data field and the other register loads the most significant byte of the data field Each byte contains bits 0 through 7 with bit 0 being the least significant bit and bit 7 being the most significant bit in the byte Data bits DBO through DB7 are loaded into the least significant byte and data bits DB8 through DB11 are loaded into bits O through 3 of the most significant byte The setting of bits 4 through 7 of the most significant byte does not matter since they are not used A sample Turbo Pascal program for generating a channel AOUT1 output is Begin board 300 Write Data for channel AOUT1 Read in a amsb a div 256 alsb a amsb 256 Port Board 8 alsb Port Board 9 amsb Port Board C 0 end The 1 O locations that
56. MODE 1 Port A and Port can be individually defined as input or output in Mode 1 to support a wide variety of strobed applications CONTROL wORO 5 0 D D D 0 D 0 lo 7 X 9 gt 1 WR 0Q PORT STROBED INPUT PORT STROBED OUTPUT CONTROL WORD Dy 0 D D Dz Dz D D BORD INPUT 0 OUTPUT RO PORT ISTROBED OUTPUT PORT STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disabie functions are also available MODE 2 Basic Functional Definitions Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched e The 5 bit control port Port C is used tor control and status for the 8 bit bi directional bus port Port A Bidirectional Bus Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go
57. Programming the PPIs Chapter 4 and demo disk Programmable Inverval Timer Circuitry Modes Software controllable See Programming the PIT Chapter 4 and demo disk Configuration Clock Input 5 MHz Gate Input 5 V Clock Output To P8 See P3 discussion Chapter 3 Disabled See P4 P5 P7 and P11 discussions Chapter 3 and Interrupt Considerations Chapter 4 Interrupts 1 3 Figure 1 2 shows the base address header connector 2 with the jumper installed at the factory set location of 300 hex The jumper must be installed vertically across one of the eight pairs of pins on P2 The hexadecimal base I O address setting corresponding to each pair of pins from left to right is as follows 200 240 280 200 300 340 380 3C0 For example if the base address is changed to 280 hex then for the 28 operations listed in Table 1 2 BA equals 280 Thus to send the channel selection and gain data to port B of PPII its address of BA 1 becomes 281 hex If the factory setting of 300 hex will cause contention in your system position the jumper to the desired base I O address setting Once you have set the base I O address make a note of its value on the table inside the back cover of this manual You will need to know this setting for use in your programs 200 3C0 P2 Fig 1 2 Base Address Connector P2 Digital VO Circuitry Two 8255 programmable per
58. SES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE ADA2000 User Selected Options Base Address hex decimal IRQ Channel Selection A D EOC CHANNEL PIT OUTO IRQ CHANNEL PIT OUT1 IRQ CHANNEL PIT OUT2 IRQ CHANNEL INTRA 1PC3 IRQ CHANNEL PPI2 INTRA 2PC3 IRQ CHANNEL PPI2 INTRB 2PCO IRQ CHANNEL IRQ CHANNEL IRQ CHANNEL A D EOC PPI Bit Assignment
59. UT MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C SIT SET RESET 1 0 RESET BIT SELECT 011 2131415 8 7 DEN This function allows the Programmer to disallow or al
60. When operated in mode 1 or mode 2 certain PPI2 port C lines function as handshaking signals some are outputs while others are inputs Therefore when operated in these modes buffers cannot be used for some ports and DIP switches S2 53 and S4 allow these ports to be shunted These switches are shown in Figure 3 13 which is a blowup of the PPI2 circuitry on the board Fig 3 13 PPI2 Circuitry 3 8 Table 3 1 lists the component location and type of device used for buffering a port configured for mode 0 operation The L and H listed for port refer to the least significant port lower and most significant port upper four bits respectively Also listed in Table 3 1 are the DIP switch shunt locations for each of the ports The numbers listed after DIP switch S3 are the switch numbers of the individual shunts used for the two four bit groups of port For buffered 1 Os the associated DIP switches must be in the OFF or OPEN position and for shunted I Os the associated DIP switches must be in the ON or CLOSED position The corresponding buffer s should be removed from the board for all shunted Table 3 1 PPi2 Buffers and Shunts Table 3 1 2 Butters and Shunts eee Location Buffer Device um rame gt rases ws rase s Poren u To buffer the input or output lines of a port first be certain that the
61. ammed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when A4 Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ag in puts are used to select the Counter to be written into The format of the initial count is determined by the Contro Word used D 02 Do scr sco eco SC Select Counter SC1 SCO SeeaGonere setectcounter2 1 1 Read Back Command See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations EIER Read Write least significant byte only Read Write most significant byte only 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be O to insure compatibility with future Intel products MODE Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 intel 82054 Write Operations The programming procedure for the 82 54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written
62. cedure 4 1 55505093 For oe os To 2a PORT LOWER 1 0 OUTPUT PORTB 1 0 OUTPUT MODE SELECTION 0 MODE O 1 MODE 1 GROUP A PORT C UPPER 1 0 OUTPUT 1 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE Fig 4 1 Mode Definition Format The 1 O locations that control PPI1 and PPI2 are listed below from Table 1 2 a Eunerion as A2 A1 ao mw RRA BES A Port R W 18 toco p R W 19 R W 1A 1 9 1 1B Port B Channel Sel amp Gain Port C Because the PPI can be configured for a wide range of operating modes and programming requirements it is heavily dependent on correctly understanding how to use the proper control byte to configure the PPI for your application The demo disk includes example programs that show how to select the common operating modes Reading the source code is highly recommended The following examples show how to configure PPI2 for the most common operating modes can be similarly configured by using its locations in place of PPI2 s locations except that port B can never be configured as an input HEX Fe RER Port A Port B Port C Control Word
63. contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled for Counting Ele ment It is 16 bit presettable synchronous down counter and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called and CR for Count Register Both are normally referred to as one unit aad called just CR When a new count is written to the Counter the count is stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously and are cleared when the Counter is programmed
64. control the D A converter functions are listed below from Table 1 2 Program AOUT1 LSB Program AOUT1 MSB Program AOUT2 LSB Program AOUT2 MSB Convert Update AOUT1 AOUT2 C D E orF Clear AOUT1 AOUT2 0 0 10 11 12 or 13 The inputregisters for each D A converter are loaded by using the corresponding base address hex values listed above To start a D A conversion a write operation to I O location base address C D E or F select one of these locations must be executed It does not matter what is written the act of writing to one of these four I O locations will initiate a D A conversion in both channels To clear the outputs of both channels simply write to I O location base address 10 11 12 or 13 Again the act of writing to any one of these four locations will clear the outputs the data written is not important Note that these outputs are also cleared every time a hardware system reset occurs Output Voltage Range and Resolution The voltage range and bit weight resolution of the analog outputs depend on the reference IC used and whether the channel is set up for unipolar or bipolar outputs The reference IC can be 5 or 10 volts for both channels depending on the IC type installed on the board Each channel can be individually controlled to have a unipolar or bipolar output depending on the setting of the jumpers on header connector 10 The reference voltage is customer specified when ordering and the output defau
65. d by writing to 1 O location BA 5 or 7 While an eight bit conversion has a lower resolution than the 12 bit conversion itis performed much more rapidly in about 13 microseconds 12 bit conversion takes about 20 microseconds Therefore when speed is essential you use the eight bit conversion capability Controlling the D A Converter The two analog output channels channel AOUT1 and channel AOUT2 can be independently programmed by writing to internal registers of the AD7537 D A converter The outputs can be set to one of four possible output voltage ranges two unipolar and two bipolar These ranges are 0 to 5 volts O to 10 volts 5 volts or 10 volts The range of the full scale output voltage is controlled by the factory installed voltage reference at IC location U15 The voltage range is specified when ordering the board REF 01 provides a 10 volt reference and REF 02 provides a 5 volt reference If after receiving your board you wish to change the voltage reference for the analog outputs you must change the IC in location U15 Replace the IC with PMI REFO2 or equivalent to set up a 5 volt reference or PMI REF 01 to set 10 volt reference The analog output channels can be independently configured for unipolar or bipolar output ranges Jumpers installed header connector P10 select the range desired for each output Both outputs are factory set to the same polarity as that specified for the A D inputs Chapter 3
66. d their corresponding buffers are removed then the I O lines controlled by them are shunted Each of the four ports A B CL or CH is controlled by one DIP switch and buffer The circumstances under which shunts are required in place of the buffers are detailed in Chapter 3 Jumper Settings Resistor networks are also provided to allow any or all of the ports to be pulled up or pulled down These networks can be used only when the associated ports are configured as inputs Resistor network use is explained in Chapter 3 Jumper Settings Programmable Interval Timer PIT The programmable interval timer PIT can be configured for a variety of timing and counting functions This versatile IC contains three independently clocked 16 bit timer counter circuits TCO TC1 and TC2 which operate as down counters These down counters can resolve time increments down to 125 nanoseconds This circuit s most common application is to provide accurate time delays under software control Upon command the PIT can count out a programmed delay and interrupt the PC when it has finished its tasks All three counter outputs are brought out to external I O connector P15 The three 16 bit timer counters are each loaded by two one byte write operations to the appropriate I O location The bytesare latched intoa 16 bit internal count register where they are stored until the count sequence starts The countdown starts when the count register contents are transfer
67. data to or from a specified port in conjunction with strobes or handshaking signals mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals 3 133 CONTROL WORD 14 0 0 0 0 0 D D CONTROL WORD 015 0 0 0 0 0 0 8 8 231256 12 Mode 1 Basic functional Definitions e Two Grouos Group and Group e Each group contains one 8 bit data port and one 4 bit control data port e The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port intel 82 55 Input Control Signal Definition MODE 1 PORT A STB Strobe input A low on this input loads data into the input latch CONTROL WORD 0 D 0 0 Dz D Op ela lt lt 1e A high on this output indicates that the data has 0 OUTPUT been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input IBF Input Buffer Full F F INTR Interrupt Request A high on this output can be used to interrupt the URDU RR CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one udis n and INTE is a It is reset by the falling edge of PODDA RD This procedure allows an input device to re quest service tro
68. dd 1 9 Selecting an Analog Input Channel eeescesessessssssesnsnnesennnonennnnnnnnnnennnnnnnennennesnennenananeennn 1 10 Setting Input sk e 1 11 Taking n A D Reading 1 12 Controlling the D A Converter da 1 13 Loading the D A Converter Data 1 13 Output Voltage Range and Resolution treten trenes 1 14 CHAPTER 2 FUNCTIONAL DESCRIPTION Analog to Digital Conversion Circuitry eese 2 2 soi C E 2 2 CAM CONO ECC i n 2 2 Sample and Hold CU daa 2 2 PAV CONVENED A O AN 2 2 Digital to Analog Conversion CirCuitry cccssscsssssscsssseccceccssesesscscstsceesesessesscssseveceeeeee 2 3 A AN 2 3 A A TA 2 3 Programmable Peripheral Interfaces 2 3 EP ee ida 2 4 xp AO 2 4 Programmable Interval Timer e dae 24 CHAPTER 3 JUMPER SETTINGS S1 Analog Input Signal DIP Switch conca da 32 P2 Base I O Address Header Connector eese eerte tret ellus 3 2 Programmable Interval Timer PIT YO Header 3 2 P4 P5 P7 and P11 Interrupt Header Connectors P4 and PPI1 INTRA eese PS PIT Output Interr pts eiie sees na obo Fo eoe sonipa Race rH aea P7
69. ded with your ADA2000 package will allow you to promptly use your interface To fully understand and control the ADA2000 functions read Chapters 2 through 4 Chapter 5 contains board calibration procedures The chapters and appendixes in this manual are described in detail below Chapter 1 Quick Start Getting Your ADA2000 Running provides the instructions necessary to install the board and use its basic functions The information contained in this chapter does not cover how to change the board setup except for the base I O address Chapter 2 Functional Description provides a block diagram and a functional discussion of the board Chapter 3 Jumper Settings describes each header or jumper circuit on the board and how it is controlled Chapter 4 Programming Your ADA2000 describes how the board can be programmed using the demonstration software Chapter 5 Calibration Procedures provides instructions for board calibration Appendix A ADA2000 Specifications contains a complete listing of board specifications Appendix B Connector Pin Assignments contains the pinouts of the external I O connectors and the mating connectors part numbers Appendix Component Data Sheets contains manufacturers data sheets for major board components Appendix Configuring the ADA2000 for SIGNAL MATH contains information about setting board jumpers and and initializing the board to r
70. dependent However they can be cascaded for countdowns which are longer than 16 bit field can support For example TCO s OUT signal can be connected to TC1 s CK signal and TC1 s OUT signal can be connected to TC2 s CK signal When configured this way the PIT can accommodate extremely long countdowns One of the three timer counter outputs OUT TC1 OUT or TC2 OUT can also be used as a PC interrupt These signals are brought out to board header connector 5 where one and only one can be selected for connection to any one IRQ channel IRQ2 through IRQ7 Chapter 3 Jumper Settings and Chapter 4 Programming Your ADA2000 describe these interrupts in more detail 3 AMD JUMPER SETTINGS This chapter describes the ADA2000 board settings you can control on DIP switches S1 through S4 and various header connectors You can use this chapter to tailor your board s functions to your specific application before installing it in your computer or to change the board s configuration as you leam more about its operation and special features In this chapter you will learn about each setting and how to set switches or install jumpers to achieve the desired operation of your board Before changing any settings you should have a functional knowledge of the circuit you are setting up see Chapter 2 Remember that all of the settings described in this chapter have been factory set or as in the
71. e analog input when the EOC signal is low logic 0 the amplifier holds the input A D Converter The A D converter is a high speed 12 bit conversion IC which performs conversions in approximately 20 microseconds Eight bit conversions can also be performed when speed is more critical than resolution An eight bit conversion takes about 13 microseconds allowing rapid conversions of dynamic analog inputs The converter supports 10 or 20 volt analog input signals however it cannot supporta 20 volt unipolar input range because its supply voltage in the ADA2000 application is only 4 12 volts The analog input voltage ranges supported by the ADA2000 are listed in the specifications in Appendix A Calibration circuitry is included for unipolar and bipolar calibration of the A D converter Calibration procedures are described in Chapter 5 An 8 or 12 bit conversion is initiated by a write operation to the appropriate I O address Once a conversion is begun the conversion status can be monitored by reading the A D converter status STS signal which is output from the A D converter IC and inverted before being made available to other circuitry on the board as the end of convert EOC signal The EOC signal can be monitored by one of two digital input lines on PPI1 PA7 or PC7 Note that if either line is selected as the EOC monitor a jumper must be installed for the selected line on P6 and that line must be configured as an input The EOC signal is factory
72. e computer s interrupt channels IRQ2 through IRQ7 As in the case of P4 two jumpers must be installed to connect a PIT output to an interrupt channel First install a jumper horizontally across the pins of the PIT output selected Then install a second jumper across the pins of the interrupt channel selected Figure 3 6 shows jumpers installed so that OUT is connected to P5 IRQ7 IRQ6 IRQS IRQ4 IRQ3 IRQ2 OUTO OUT1 OUT2 Fig 3 6 Interrupt Header Connector P5 P7 A D End of Convert EOC Interrupt Header connector P7 shown in Figure 3 7 is used to jumper the A D converter s end of convert EOC signal to one of the computer s interrupt channels IRQ2 through IRQ7 The EOC signal is connected to an IRQ channel by installing a single jumper horizontally across the pins of the IRQ channel selected Figure 3 7 shows signal connected to IRQ4 Dl Fig 3 7 Interrupt Header Connector 7 P11 EXTINT2 and 2 INTRA and INTRB Interrupts Header connector P11 is used to select EXTINT2 PPI2 INTRA or PPI2 INTRB for connection to one of the computer s interrupt channels IRQ2 through IRQ7 EXTINT2 is provided to accommodate an interrupt signal generated external to the ADA2000 and routed onto the board through external I O connector P14 see Table B 3 in Appendix B PPD INTRA labeled 2PC3 on the board and PPI2 INTRB labeled 2PCO on the board are generated by PPI2 One of th
73. e the A D converter for unipolar or bipolar operation These affect the offset and full scale performance of the ADA2000 circuitry Both calibration steps are performed using trimpots TR5 and TR6 or TR6 and TR7 Trimpot TR5 or TR7 is used to zero the offset error of the A D converter and trimpot TR6 is used for full scale adjustment In the following procedure use analog input channel 1 and set it for a gain of 1 This is accomplished by writing all zeroes to I O address location BA 1 Be certain that position 4 of switch S1 is set for the desired polarity and the jumper on connector P9 is set for 10V Unipolar Calibration Two adjustments are necessary to calibrate the A D converter for the unipolar voltage range of 0 to 10 volts one for offset and one for full scale To adjust the offset a very low analog input voltage shown under the Offset heading in the following table is connected to the channel 1 input of the multiplexer P8 1 The ground reference of this signal should be connected to 8 2 While continuously displaying 12 bit A D conversions adjust TR7 until the A D data flickers between the two values listed in the table under Offset After the offsetadjustmentis made then TR6is used to adjust the full scale value While the full scale input voltage listed in the table is not the actual full scale voltage for an ideal 0 to 10 volt range it is the maximum voltage at which the A D conversion is guaranteed to be linear Any val
74. e used to cascade the timer counters for longer time delays than are supported by a single timer counter circuit P15 P3 8255 PIT U5 4 O O GTO EGO AO COO Q gt e O EO E BO 5V O ES en EG1 gt we ou CO1 DE cl O Is 2 C GT2 e OUT2 e AA Fig 3 4 PIT Functional Block Diagram 2 P4 PS P7 and P11 Interrupt Header Connectors Header connectors P4 P5 P7 and P11 are used to jumper various signals generated by the ADA2000 circuitry to the PC s interrupt channels The interrupt channels available on the board are IRQ2 through IRQ7 Note that only one interrupt in the computer system can be connected to an interrupt channel at any given time Before attempting to use interrupts you should be familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines These procedures are beyond the scope of this manual but must be understood to effectively use interrupts in you computer system Becareful to avoid contention when selecting the interrupt channels used both with the signals on the ADA2000 as well as with other devices within your computer To avoid contention use the table inside the back cover of this manual to record the interrupt channels you use with the ADA2000 board
75. ect the analog input channel The analog input channel is selected by writing to PPI1 port B mapped at I O location base address 1 The input channel and the input gain can be set individually by setting only the four LSBs channel select or only the four MSBs gain of the eight bit control word sent to PPI1 port B Before you change either the input channel or the gain you MUST preserve the current state of port B Failure to do so will result in changing both the channel select and the gain when you intended to change only one of these two settings The general algorithm for setting the channel changing just the four LSBs of the control word while preserving the four MSBs is 1 10 1 Read the current state of port current state inp base_address 1 2 Preserve the upper four bits since they contain gain data current state current state AND FO 3 Logically OR the current state with the desired channel number minus 1 current state current state OR channel 1 4 Write it back out to port B out address 1 current state A BASIC program to select channel 2 is 100 BASE_ADDRESS 768 110 CHANNEL 2 120 STATUS INP BASE ADDRESS 1 130 STATUS STATUS AND 140 STATUS STATUS OR CHANNEL 1 150 OUT BASE_ADDRESS 1 STATUS Setting the I Gai The gain is set by writing to the upper four bits of PPI1 port B at BA 1 The bit pattern for each of the five gain values
76. een the appropriate P8 signal and ground pins Adjust the appropriate trimpot so that the output voltage is zero volts Next calibrate the full scale voltage output For full scale calibration program the D A converter to output a full scale voltage by writing to base I O address locations BA 8 and BA 9 for AOUTI and BA A and BA B for AOUT 2 Use the digital voltmeter to monitor the output voltage present between the appropriate P8 signal and ground pins Adjust the appropriate trimpot until the voltage equals the full scale voltage in Table 5 4 as measured by the voltmeter Table 5 4 lists the maximum D A bipolar output voltage for each bit weight in a 12 bit conversion for 5 and 10 volt references Note that the voltage values in the table are in millivolts Table 5 4 D A Converter Weights Bipolar Ideal Output Voltage millivolts D A Bit Weight 10_ Volts 4095 full scale output 4997 5 9995 1 2048 0000 0 0000 0 1024 2500 0 5000 0 512 3750 0 7500 0 256 4375 0 8750 0 128 4687 5 9375 0 64 4843 8 9687 5 32 4921 9 9843 8 4960 9 9921 9 4980 5 9960 9 4990 2 9980 5 4995 1 9990 2 4997 6 9995 1 5000 0 10000 0 5 5 APPENDIX ADA2000 SPECIFICATIONS Typical at 25 Interface Analog Inputs A D Converter Counter Timer Digital I O Lines D A Converter Analog Out
77. emaining jumpers must be removed from the P3 header connector 5V 2 XTAL 2 5V EG2 co2 co2 9 9 ZA g IELE vino 715 mo Fig 2 8254 Timer Counter Jumpers P4 P5 amp P7 Interrupts To select an IRQ channel and an interrupt source for ATLANTIS you must install two jumpers on P5 the timer counter output interrupt header Jumpers must be installed across the OUT2 pins and across the pins of your desired IRQ channel Figure E 3 shows OUT2 jumpered to IRQ3 Make sure that no jumpers are installed across the IRQ pins on header connectors P4 and P7 IRQ6 IRQS IRQ4 IRQ3 IRQ2 OUTO OUT2 Fig E 3 End of Convert Interrupt Jumper 7 P6 End of Convert Monitor When running ATLANTIS place a jumper between EOC and PA7 as shown in Figure E 4 P6 Vd 19d Fig E 4 End of Convert Monitor Jumper P6 4 1 APPENDIX F 2 LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective product
78. er control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count e Control Word Counter 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 MSB of count Counter O D 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 1 Control Word Counter 2 LSB of count Counter 0 MSB of count Counter 1 LSB of count Counter 2 of count Counter 0 of count Counter 2 20000 m 2 P In all four examples all counters programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences _ Read Operations lt is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82 54 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the 1 0 inputs the CLK input of the selected Counter must be inhibited b
79. ese three signals can be jumpered to one of the available computer interrupt channels IRQ2 through IRQ7 by first placing a jumper horizontally across the pins of the signal chosen and then placing a second jumper horizontally across the pins of the selected IRQ channel Figure 3 8 shows header connector P11 with jumpers installed so that PPD INTRB is connected to IRQS IRQ7 P11 IRQ6 IRQS IRQ4 IRQ3 IRQ2 2PCO 2PC3 EXTINT2 Fig 3 8 Interrupt Header Connector P11 As described above the A D converter end of convert EOC signal can be used to generate an interrupt If this signal is not used as an interrupt it can be used as a status monitor of the A D conversion process Header connector P6 provides two lines through which the EOC can be monitored PPI1 PA7 or PPI1 PC7 One of these two digital IO lines is selected for EOC monitoring by installing a jumper horizontally across the appropriate pair of pins The digital I O line selected PA7 or PC7 must be configured as a mode 0 input see Chapter 4 Programming Your ADA2000 Figure 3 9 shows P6 with a jumper installed in the factory set position for EOC monitoring through 7 P6 Vd 42d Fig 3 9 EOC Monitor Header Connector P6 3 6 P9 A D Converter Voltage Range Header Connector Header connector P9 shown in Figure 3 10 is used to select the analog input voltage range of the A D converter A jumper is installed vertically across the pins marked 10V to
80. etting be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address DMA D A DMA Channel Channel Select Select External Gain External Gain amp Loss amp Loss A D Unipolar E Select D A Unipolar Bipolar Select Fig D 5 ADAINST EXE Screen D 5 Resolution and number of channels are fixed by the program for your board The DMA channel number block is not valid on the ADA2000 and should be left blank The next two blocks gain and loss are provided so that you can make adjustments for external gain or loss other than the programmable gain settings available on the board If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for loss If you have an external gain factor then you can adjust for this condition Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 For a bipolar input range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D A Parameters Six D A board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of
81. for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there intel 82654 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5 to 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage on any Input GND 2Vto 6 5V posure to absolute maximum rating conditions for Voltage on any Output GND 0 5Vto 0 5V extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C 5 10 GND 0V Ta 40 C to 85 for Extended Temperature Symbol Parameter unts TestConditions Vu mputowvotagg os os w me 20 nl E ae RR PE Output High Voltage 3 0 lon 25 mA 0 4 lon 100 pA v Input Load Current ViN 7 Vcc to OV Output Float Leakage Current SS EXP Voc to 0 0V Voc Supply Current 8MHz 82C54 7 5 PE
82. ge value by scaling it in the case of bipolar inputranges 5 or 10 volts and then multiplying by the appropriate bit weight as shown in the table at the top of the following page MSB LSB DIS 014 013 012 011 DIO 09 08 07 06 05 04 D3 02 DO peo per vee oes pes ose o Fig 1 6 Conversion Word Format 1 12 Input Range Scale Factor Bit Weight 5 volts Subtract 2048 2 4414 mV 10 volts Subtract 2048 4 8828 mV 0 to 10 volts None 2 4414 mV For example if the A D reading is 1024 and the input range used is 5 volts the analog input voltage is calculated as follows 1024 2048 bits 2 4414 mV bit 2 49999 volts For a 10 volt input range the voltage is calculated as follows 1024 2048 bits 4 8828 mV bit 4 99999 volts For a 0 to 10 volt input range no scaling is required and the voltage is calculated as follows 1024 bits 2 4414 mV bit 2 49999 volts The input voltage range and polarity are factory set according to customer specifications when ordering the board If after receiving your board you wish to change the input voltage see Chapter 3 Jumper Settings Whenever the voltage polarity is changed unipolar to bipolar or vice versa the A D converter should be recalibrated as described in Chapter 5 Calibration Procedures Note that eight bit A D conversions can also be performed This is accomplishe
83. gisters However some operations require only that a particular 1 address be written to the data written is irrelevant These I O locations are referenced to the ADA2000 base I O address BA determined by the jumper setting of connector P2 Chapter 1 describes the base I O address considerations and configuration The data collection and support functions controlled through software include the analog input channel selection and gain control of the the A D and D A conversions the programmable peripheral interfaces and PPI2 and the programmable interval timer Because they are integral to the basic operation of the board the analog input channel and gain selections taking an A D reading and controlling the D A converter are covered in Chapter 1 Digital control through and PPI2 and control of the programmable interval timer are more complex and are described in this chapter The demonstration disk which accompanies your ADA2000 contain examples in Turbo C Turbo Pascal and BASIC Nearly all modern MS DOS based PC languages have I O reference instructions These are the instructions to control the data transfers to and from the 1 O ports Consult your programming language reference to find these instructions for your favorite language Selecting an Analog Input Channel See this section in Chapter 1 Setting the I Gai See this section in Chapter 1 Taki A D Readi See this section in Chapter 1 Controlling the D A
84. gram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82054 Pinout September 1989 3 83 Order Number 231244 005 intel 82654 Table 1 Pin Description A AAA on we A connected to system data bus crko 9 10 Clocko CiockimputofCountero ouro 10 12 O Outputo OutputofCountero GATEO 13 1 Gateo GateimputofCountero GND 12 144 Ground Power supply connection our 16 O Outr OutputofCounters GATE1 14 147 1 Gatet GateimputofCountert 15 18 1 Clock 1 ClockinputofCountert GATE2 16 19 1 Gate2 GateinputofCounter2 2 2 our2 17 20 Out2 OutputofCounter2 eke 18 1 Clock Ciockinputot Goumer2 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus Counter 0 Counter 1 Counter 2 Control Word Register Chip Select A low on this input enables the 82 54 to respond to RD and WA signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations SE Write Control This input is low during CPU write Operations Voc Power 5V power supply connection M 1 11 15 25 sired delay After the desired delay the 82 54 will FUNCTIONAL DESCRIPTION inter
85. ines programmed as inputs including ACK and STB lines associated with Port C are not affected by Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82 55 to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION D Dg Ds D3 Dz D Do in Mode 0 Port C transfers data to from the pe _ ripheral device When the 82 55 is programmed to BES function in Modes 1 or 2 Port C generates or ac Paid cepts hand shaking signals with the peripheral de ener vice Reading the contents of Port allows the OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe De 2s Br Ds D2 E ripheral device and change the program flow ac OU ANTEA GROUP A GROUP There is no special instruction to read the status in formation from Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function D4 Dz Dj Do TT 7 NS ANO Sr rn GROUP A GROUP Defined Mode 0 o
86. ing the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 D 3 P3 8254 Timer Counter I O Configuration The 8254 must be configured with the six jumpers placed between the pins as shown in Figure D 2 After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P3 header connector XTAL E 45V o EGO E XTAL 8 21 Fig 0 2 8254 Timer Counter Jumpers P4 PS amp P7 Interrupts To select IRQ channels and interrupt sources for SIGNAL MATH you must install two jumpers on P5 and jumper on P7 First install a jumper on P5 OUT2 and a second jumper across the pair of P5 pins for the IRQ channel you select Then install a jumper on the end of convert interrupt header P7 across the pins of your desired IRQ channel The IRQ selected on P7 must be different from the IRQ set on P5 Figure D 3 shows OUT2 jumpered to IRQ3 and EOC jumpered to IRQ4 Make sure that no jumpers are installed on P4 P5 IRQ7 IRQ6 P7 IRQS IRQ4 IRQ3 IRQ2 OUTO OUT OUT2 Fig D 3 Timer Counter Out amp End of Convert Interrupt Jumpers P5 amp P7 EOC voacoo y Ol P6 End of Convert Monitor When running SIGNAL MATH place a jumper between EOC and 7 as shown in Figure D 4 P6 Vd 194 Fig D 4 End of
87. ipheral interfaces PPIs provide 40 TTL CMOS compatible digital I O lines which can be configured by the user for a wide range of I O functions Each PPI has 24 digital lines as shown in the 8255 block diagram in Figure 1 3 Eight of these lines PPI1 support the board s analog to digital conversion function and are not available for other use The remaining 16 lines from and 24 lines from PPI2 are available to the user PA7 PORTA PORT B PCO PC7 PORT Fig 1 3 8255 PPI Functional Diagram The 24 lines of PPI2 be set as buffered or shunted lines using on board DIP switches to support individual user requirements All 24 lines are factory set as buffered inputs and this is the setting which will be used in this chapter PPI2 U20 and its associated buffer ICs and DIP switches are located on the left hand portion of the board near I O connector P14 The board is shipped with buffer ICs installed and with the switches set to the OPEN OFF position P12 is jumpered so that the I O lines are configured as buffered inputs All of these settings are explained in Chapter 3 1 4 Table 1 2 ADA2000 Map mem LI EE Start 12 bit Conversion Start 8 bit Conversion Read MSB Read LSB 00010 ILL Program AOUT1 LSB Program ADUT1 5 202225 Port Channel Sel amp Gain Port C 0 Control Word 0 o
88. l It makes a low to high transition at the completion ofeach conversion cycle and remains high until another conversionisinitiated The timing of the EOC signal is shown in Figure 2 2 Chapter 2 PPI Interrupts The interrupts generated mode 1 and mode 2 operation can be jumpered to any of the PC interrupt channels IRQ2 through IRQ7 The timing of these interrupts is shown on the PPI data sheet included Appendix The PPI interrupts must be enabled by writing a 1 to the INTE mask bit of the particular PPI as described in the data sheet under Interrupt Control Functions The INTE mask bits are disabled during power up reset and whenever the PPI mode is changed PIT Interrupts One of the OUTO OUTI or OUT2 signals generated by the PIT can be jumpered to a PC interrupt channel using connector P5 When using a PIT OUT signal as an interrupt you must be very careful to ensure that the PC system s programmable interrupt controller PIC is properly configured to ignore interrupts on the selected interrupt channel immediately after power up This is necessary because the PIT must first be initialized to define the desired mode s of operation Prior to initialization the mode count and output of all counters are undefined If the system interrupts are not disabled the counter outputs may cause erratic system behavior 4 4 5 CALIBRATION PROCEDURES This chapter contai
89. lexer is configured for single ended inputs and when they are down the multiplexer is configured for differential inputs Note that these three switches are always set as a group to the same position see S1 Switch Settings Chapter 3 A channel is selected through software control by writing to Port of PPI1 as described in Chapter 1 Gain Control Circuitry The programmable gain control circuitry can provide a gain factor of 1 2 4 8 or 16 The gain selection is made by writing to Port B of PPII as described in Chapter 1 The gain factor is controlled by the setting of four analog switches For a gain of 2 4 8 or 16 this write operation will close one of the four switches for a gain factor of 1 all switches are open Note that programming gain factors other than the five listed here is not recommended Sample and Hold Circuitry A sample and hold S H amplifier is used between the gain control circuitry output and the A D input to ensure that dynamic analog signals are accurately digitized by the A D converter The 001 hold capacitor used in this circuit is apolystyrene type selected for its low dielectric absorption Its low value minimizes the acquisition time 6 microseconds typical and minimizes hold step voltage and droop The sample and hold time and rate are determined by the EOC signal generated by the A D converter and fed back into the S H circuit When the EOC signal is high logic 1 the amplifier samples th
90. low a specific 1 device to interrupt the CPU with out affecting any other device in the interrupt struc ture BIT SET RESET FLAG ME INTE flip flop definition 29125627 BIT SET INTE SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Figure 7 Bit Set Reset Format Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 82 55 Operating Modes Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports Thi ti Mode 0 Basic Input Output This functional con Any port Be wicdtor output figuration provides simple input and output opera tions for each of the three ports No handshaking Outputs are latched is required data is simply written to or read from a Inputs are not latched specified port 16 different Input Output configurations are pos sible in this Mode MODE 0 BASIC INPUT 231256 8 MODE 0 BASIC OUTPUT 231256 9 3 130 intel 82 55 MODE 0 Port Definition GmourB_ doren 99 comen 0 o o o output outeur o output output o o 1 ourur ourur 1 ourur 1 o ourur ourur 2 eur lo o 1 1 output outeur 3 Lo o o ourur weur 4 OUTPUT jo 1 o ourur meur s ourur
91. lt setting for both channels is the same polarity as that specified for the A D converter The possible ranges and their corresponding bit weights are Range Bit Weight 0 to 4 9988 V 1 22 mV 0 to 49 9976 V 2 44 mV 4 9976 to 5 0000 2 44 mV 9 9951 to 10 0000 V 4 88 mV The data written to each pair of D A channel inputregisters represents a 12 bit digital value of the desired output voltage When the output is unipolar a data value of zero corresponds to zero volts and a full scale value all ones corresponds to the positive full scale voltage either 4 9988 volts or 9 9976 volts Intermediate voltage values are determined by multiplying the D A data by the appropriate bit weight 1 22 millivolts or 2 44 millivolts In bipolar operation the direction of the voltage changes from positive to negative as the data value increases data value of zero corresponds to the positive full scale output voltage 5 0000 volts or 10 0000 volts A full scale value all ones corresponds to the negative full scale output voltage 4 9976 volts or 9 9951 volts An algorithm for determining the bipolar output voltage is given by the following equation Analog output voltage FS voltage D A value bit weight where FS voltage is the positive full scale voltage 5 or 10 volts D A value is the digital data converted by the D A converter Bit weight is either 2 44 mV or 4 88 mV The correlation of the D A data values to the output vol
92. m the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of PCs Figure 8 MODE 1 Input FROM PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input 3 134 e Output Control Signal Definition OBF Output Butter Full F F The BF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set by the rising edge of the WR input and reset by input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when is a one is a one and INTE is a one It is reset by the falling edge of WR INTE Controlled by bit set reset of PCs INTE B Controlled by bit set reset of 82 55 CONTROL WORD D 0 0 0 Oy D D D 90000555 1 INPUT 9 OUTPUT MODE 1 PORT B CONTROL WORD D 04 Os 0 D3 0 D Op Te X 231256 15 Figure 10 MODE 1 Output 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82 55 Combinations of
93. nctions are further explained in the data sheet in Appendix C provides 16 digital I O lines at external I O connector P15 see Table B 4 Appendix B The lines available for digital are port A and port C The eight bits of port B are reserved for A D channel selection and gain control and cannot be configured for I O use Ports and C can be configured in any of the three operating modes described above The ADA2000 board provides a header connector which can jumper the A D converter end of convert EOC signal to a PPI1 bit where it can be monitored to provide A D conversion status The EOC signal can be jumpered to either PA7 port A bit 7 or PC7 port C bit 7 The default setting of the jumper is PA7 The port used to monitor the EOC signal must be configured as a mode 0 input port PPI2 PPI2 has some special circuitry on the ADA2000 board which enhances its capabilities All 24 I O lines available from PPI2 can be buffered or shunted as well as pulled up or pulled down These signals are provided at external I O connector P14 see Table B 3 Appendix B The buffer circuitry allows PPI2 to drive long cables with output signals and provides noise immunity for input signals However buffers cannot be used for some ports when operating in modes 1 or 2 or when dynamically changing the port direction through software control On board DIP switches are included to bypass the buffers When these DIP switches are closed an
94. nectors for P8 P14 and P15 Manufacturer Part Number 8 3M 3417 7040 P14 Robinson Nugent IDS C40PK C SR TG P15 Mil C 83503 M83503 7 09 Table B 2 P8 Connector Pin Assignments da pues DIFF SE AIN1 GND AINI AIN9 GND AIN2 AIN2 GND AIN2 AINIO GND AIN3 AIN3 GND AIN3 GND AIN4 AIN4 GND AIN4 AIN12 GND AINS AINS GND AINS AIN13 GND AIN6 AIN6 GND AIN6 AIN14 GND AIN7 AIN7 GND AIN7 AINIS GND AIN8 AIN8 GND AINS AIN16 GND AOUTI GND AOUT2 GND 12 VOLTS GND 12 VOLTS GND Table 3 14 Connector Pin Assignments 2PA6 2PA4 2PA2 2 0 2PC6 2PC4 2PC2 2 0 2 6 2 4 2 2 2 0 12 VOLTS RESET DRV 12 VOLTS GND Table B 4 P15 Connector Pin Assignments e 1PAS 1PA3 IPA1 GND 1PC7 5 GND EXTCLKO CLKOUTO CLKOUTO EXTCLK1 CLKOUT1 CLKOUTI EXTCLK2 CLKOUT2 CLKOUT2 5 VOLTS GND 12 VOLTS 12 VOLTS APPENDIX COMPONENT DATA SHEETS Intel 82 54 Programmable Interval Timer Data Sheet Reprint Intel 82 54 CHMOS PROGRAMMABLE INTERVAL Compatible with all Intel and most Three independent 16 bit counters other microprocessors B Low Power CHMOS High Speed Zero Wait State 10 mA 8 MHz Count Operation with 8
95. ng Conventions Apply All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a contro word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 intel 82 54 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting
96. ns calibration procedures for the A D converter input voltage range the A D converter gain and the D A converter output voltage range The offset and full scale performance of the ADA2000 A D and D A converters are factory calibrated according to the specifications that were given when your order was placed The gain circuitry is also factory calibrated before the board is shipped The following procedure allows you to quickly verify the accuracy of these circuits This procedure should be done approximately every six months whenever inaccurate readings are suspected or whenever the voltage ranges are changed Calibration is performed with a properly configured ADA2000 installed in the PC Apply power to the computer and allow the ADA2000 circuitry to stabilize for 15 minutes Required Eaui The following equipment is required for calibration Precision Voltage Source O to 10 volts Digital Voltmeter 5 1 2 digit 4 Jumper Wire Small Screwdriver for trimpot adjustment Figure 5 1 shows the board layout The trimpots referenced in the following procedures are grouped in the upper center area of the board Fig 5 1 ADA2000 Board Layout A D Calibrati During this procedure connections must be made to some of the analog inputs on external I O connector P8 available at the rear panel of the computer The pin assignments for this connector are given in Table B 2 Appendix B Two adjustments are necessary to completely calibrat
97. nter near the bottom of the board the base I O address setting can be changed to any one of eight locations 1 2 Table 1 1 ADA2000 Board Functions and Settings FUNCTION FACTORY SETTING USER INFORMATION Base I O Address 300 hex 768 decimal To change this setting see Setting the Base VO Address Chapter 1 To select 16 single ended channels see 1 discussion Chapter 3 Analog Input Channel Type 8 differential channels Software controllable See Selecting an Analog Input Channel Chapter 1 and demo disk Analog Input Channel Selection See Setting the Input Gain Chapter 1 and demo disk Analog Input Gain Selection Software controllable To change these settings see 1 and P9 discussions Chapter 3 User specified when ordering Analog Input Voltage Range and Polarity End of Convert Monitor Connected to See P6 discussion Chapter 3 To change these settings see 10 discussion Chapter 3 Analog Output Voltage Range and Polarity Voltage range factory set to same polarity as analog input Digital VO 16 I O Lines from PPI1 Software controllable unbuffered See Programming the 5 Chapter 4 and demo disk 24 I O Lines from PPI2 Buffered inputs software controllable See Digital Circuitry Chapter 1 P12 and digital I O discussions Chapter 3
98. nverter Voltage Range Header Connector P10 Header connector P12 shown in Figure 3 12 controls the direction of the buffered digital I O lines of PPI2 As described in Chapter 2 the 24 PPI2 digital I O lines are grouped into two eight bit groups port A PAO through PA7 and port PBO through PB7 and two four bit groups port C low PCO through and port C high PC4 through PC7 P12 is labeled A B CL port low and CH port C high on the right side to correspond with the PPI s group structure For each group of lines to be buffered a jumper must be installed horizontally to select the direction that the buffer is to be configured output O or input 1 To select the direction of the data at a port with respect to the PPI position the 3 7 jumper horizontally beside the O or the for each buffered port The board is factory set for buffered inputs on all 24 PPI2 digital I O lines If a particular port is shunted by using the port s DIP switch and removing the corresponding buffer the jumper on P12 for that port should be removed Chapter 2 and the section below about shunts buffers and resistor networks further explain the PPI s possible configurations P12 gt 1 O E N O 2 T 1 O E 1 Fig 3 12 Digital VO Header Connector P12 Digital VO Buffers St 1 Resistor ks Fi 3 13 Programmable peripheral interface PPI2 has buffers for the input or output lines when operated in mode 0
99. omputer All three cables run through a single slot where they provide 120 lines of external I O to the board This configuration allows substantial board I O through a single expansion port in your computer Appendix B lists the signal carried on each pin of these connectors To install the cables a Remove the strain relief clamp attached to the ADA2000 bracket located on the right side of the board b Connect the socket connector to board connector for each cable When installing observe the connector keying and press firmly to make sure that each socket connector is fully seated on the board Each cable provided is labeled with the connector s P number for easy identification The cables have strain reliefs one connector and not on the other The connector without the strain relief is to be installed on the board After the cablesare installed on the board position them so that they pass over the flange in the board s bracket c Re attach the clamp to the bracket using the hardware supplied with your ADA2000 securing the ribbon cables in place 4 After checking that the cables are correctly installed on the board orient the board inside the computer so that the cables extend through the rear panel opening and the card edge connector lines up with the expansion slot connector Then press down on the metal bracket tab and the top of the board until the board is firmly seated in the expansion slot connector 5 Secure the
100. opriate P8 signal and ground pins Using Table 5 3 adjust the appropriate trimpot until the voltage equals the full scale voltage in Table 5 3 as measured by the voltmeter Table 5 3 lists the maximum D A unipolar output voltage for each bit weight in 12 bit conversion for 5 and 10 volt references Note that the voltage values in the table are in millivolts Table 5 3 D A Converter Bit Weights Unipolar ae Ideal Output Voltage millivolts D A Bit Weight 0 to 5 Volts 0 to 10 Volts 9997 6 4095 full scale output 4998 8 2048 2500 0 5000 0 1024 1250 0 2500 0 512 625 00 1250 0 256 312 50 625 00 156 250 312 50 78 125 156 250 39 063 78 125 19 5313 39 063 9 7656 19 5313 4 8828 9 7656 2 4414 4 8828 Bipolar Calibration Calibration of the D A outputs when configured for bipolar operation involves both a mid scale adjustment and a full scale adjustment for each output channel The trimpots associated with each adjustment and the analog output P8 pin assignments for measuring the output voltage are Output Mid Scale Full Scale P3 Pin Assignment Trimpot Trimpot AOUTI TR9 TR10 33 SIGNAL 34 GND AOUT2 8 TR11 35 SIGNAL 36 GND Program the D A converter to output a mid scale voltage by writing X800 to base I O address locations 8 and BA 9 for AOUT1 and BA A and BA B for 2 Use the digital voltmeter to monitor the output voltage present betw
101. perate as a group When these are in the UP position the multiplexers are configured for single ended inputs when they are in the DOWN position the multiplexers are configured for differential inputs Note that these three switches must all be set to the same position UP or DOWN for the multiplexers to function properly The remaining switch S1 4 controls the input voltage polarity When this switch is in the UP position the input voltage range is unipolar when it is in the DOWN position the voltage range is bipolar This switch coupled with the voltage range selection set on header connector P9 determines the analog input voltages supported by the A D converter Note that whenever the polarity is changed the A D converter circuitry should be calibrated as described in Chapter 5 The switch settings are clearly labeled on the board to eliminate errors when configuring S1 TYPE POL 4 1 2 3 4 S E DIFF Fig 3 2 Switch 1 P2 Base Address Header Connector Header connector P2 controls the 28 computer 1 O address locations used by the board The base I O address location is set by jumpering one of the eight positions on the P2 header connector The base I O address is factory set to 300 hex 768 decimal with the jumper installed across the pair of pins fifth from the left on the connector The base I O address setting is fully explained in Chapter 1 Base I O Address Setting and is not repeated
102. portional voltage for output on external I O connector P8 This voltage is either aunipolar or bipolar value depending on the configuration of the board Both op amps are contained in one IC package providing excellent slew rate and tracking characteristics Programmable Peripheral Interfaces Two 8255 programmable peripheral interfaces and 2 provide 40 TTL CMOS digital I O lines which be configured in a number of ways to support user requirements Each PPI has 24 digital I O lines These lines are grouped into three eight bit ports port A port B and port C Port C is further subdivided into two four bit ports port C lower PCO PC3 and port C upper PC4 PC7 in certain modes of operation The PPI data sheet is included in Appendix C The is capable of three modes of operation Mode 0 Basic input output Provides simple input and output operations for each port Data is written to or read from a specified port Mode 1 Strobed input output Provides a means for transferring I O data to or from port A or port B in conjunction with strobes or handshaking signals Mode 2 Strobed bidirectional input output Provides a bidirectional means of communicating with another device ona single eight bit bus Handshaking signals are similar to mode 1 This mode applies to port A only 2 3 In mode 0 all four ports A B C lower and C upper are available as I O lines Sixteen configurations are possible
103. put ADA2000 SPECIFICATIONS IBM PC XT AT compatible Jumper selectable base address I O mapped Jumper selectable interrupts 8 differential or 16 single ended inputs switch selectable Input impedance each channel 210 megohms Gains software Selectable 1 2 4 8 or 16 Gain evene 0 5 typ 1 max Input options 10 volt range Option 1 Bipolar 5V Guaranteed Linearity 5V 10 volt range Option 2 Unipolar 0 to 10V Guaranteed Linearity 0 to 9 5V 20 volt range Option 3 Bipolar 10 V Guaranteed uid DE 9 5V Range Jumper selectable Polarity T Pen Switch selectable Settling trente tont 3 usec max Common mode input voltage 10V Overvoltage protection 35 Vdc Erratic readings can occur beyond specified input voltage ranges A Resolution 10 20 volt range Chip selectable conversion speed Option 0 Option 1 Option 2 AA E Sample and hold acquisition time Throughput Three 16 bit 8 MHz down counters Successive approximation 12 bits 2 44 mV bit 12 bits 4 88 mV bit 20 typ 25 max 12 typ 15
104. quirements will determine how the individual timer counters should be configured The data sheet included in Appendix C provides the information required to control the PIT The software included on the demo disk shows example programs for controlling some of the PIT operating modes The signals generated by the OUT pins for any of the counters may be connected to one of the PC s interrupt channels using jumpers installed at connector P5 Refer to the Hardware Interrupts section below for more information on using the OUT signals to generate interrupts Hardware Interrupts Four jumper connectors labeled P4 PS P7 and P11 are provided on the ADA2000 to enable interrupts generated by the A D converter the PIT the PPIs and two external sources to the PC s interrupt channels IRQ2 through IRQ7 Chapter 3 Jumper Settings explains how these header connectors can be configured Before youattempt to use interrupts be sure you are familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines 4 3 A D Converter End of Convert EOC Signal The A D converter EOC signal can be used to generate an interruptto the PC An interrupt will occur through the selected interrupt channel to indicate a conversion is complete approximately 20 microseconds after the conversion is initiated The EOC signal is inverted before being applied to the interrupt channe
105. r ADA2000 is a demo disk which provides programming instructions and example programs for controlling the functions of your interface board This demo disk is divided into directories each of which is named according to the language used to write the programs it contains The files within each directory contain example programs and a documentation file with general information addition your demo disk contains a README DOC file which provides programming information for your board Each example program shows you how to control a particular board function such as selecting an input channel or input gain controlling the A D and D A converters controlling digital data transfers and setting the timer counter circuitry These programs should be used to become familiar with these functions Also included in your ADA2000 package is the ATLANTIS data acquisition software demo disk ATLANTIS is a powerful software package written exclusively for Real Time Devices A D conversion boards More information about this easy to use software is available from Real Time Devices Inc Backing Up Your Disk The demo disk provided with the ADA2000 is a double sided format which can be read by all DOS versions 1 1 and above Before using the software included with your board make a backup copy of the disk You may make as many backups as you need To copy the original to any other DOS formatted disk insert the disk to be copied into drive A of your computer and f
106. r Mode 1 Selection Figure 17b MODE 2 Status Word Format Interrupt Enable Flag Position Alternate Port C Pin Signal Mode INTE B ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 STBA Input Mode 1 or Mode 2 INTE A1 Output Mode 1 or Mode 2 Figure 18 interrupt Enable Flags in Modes 1 and 2 3 140 intel 82 55 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 Cto 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input 2V to 6 5V Voltage any Output GND 0 5V to 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C 5V 10 GND Output Low Voltage Output High Voltage IDAR Darlington Drive Current Ehe Port Hold High Leakage Current IPHLO Port Hold Low Overdrive Current llc Vcc Supply Current Vcc Current Standby NOTES ee 1 Pins A4 CS WR RD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA 350 Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
107. r will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there 1 158 3 13 158 3 FF 0 0 231244 13 20 5 intel 82 54 Signal Low Status or 5 7 Disables Enables counting counting 1 Initiates counting 2 Resets output after next 1 Disables counting Initiates 2 Sets output counting immediately high 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high Disables Enables counting counting Initiates counting Figure 21 Gate Pin Operations Summary COUNT COUNT NENNEN EET NOTE 0 is equivalent to 216 for binary counting and 104 for BCD counting
108. re prototyping solid state relays or optoisolators this can easily be done with an XB40 The expansion cable terminates in a 40 pin wire wrap header connector suitable for installation in standard 0 1 inch spacing perf board material available from most electronic distributors The Hardware The ADA2000 interface board is shown in Figure 1 1 A complete listing of the board specifications is contained in Appendix A The ADA2000 has several features which are user controlled through hardware or software Most of the hardware controllable features are jumper controlled the remaining switch controlled All of the board components are mounted on a 10 4 inch printed circuit board which fits in any unused full size expansion slot in an PC XT AT or compatible computer Three 40 connectors on the board 8 P14 and P15 accommodate all of the board s external I O In operation these connectors are cabled so that all 120 lines are accessible at the rear panel of the computer see the board installation instructions later in this chapter Functions You Can Set To allow the ADA2000 interface board to be adapted to your needs several functions can be set up to perform specific tasks by changing the hardware configuration or through software Table 1 1 lists each function you can control the factory or default setting if applicable and where in this manual you can find information about its settings 1 1 Fig 1 1
109. read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specificaily if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected
110. red in parallel to the down counter The timer counter circuits can be programmed for binary or BCD countdowns 24 A 5 MHz crystal on the ADA2000 be used to clock any timer counter circuit Or the timer counter can be clocked by a source external to the board through external I O connector P15 Rates of dc to 8 MHz can be used to clock the timer counters Each timer counter can be configured for one of six modes of operation These modes are Mode 0 Interrupt on end of count The OUT signal changes from low to high when the countdown is completed Mode 1 Re triggerable one shot A low level pulse triggered by the GT input is output on the OUT pin Mode 2 Rate generator Mode 3 Square wave generator Mode 4 Software triggered strobe Mode 5 Hardware triggered strobe re triggerable The timer counter count modes as well as the count type binary or BCD read write mode and counter timer selection mode are all part of the control word which is written to the PIT control register to initialize the circuit When the PC is powered up the timer counter circuits are not defined until the appropriate control words are written to the circuits to program them for operation Initialization is required only once after a power up reset occurs Detailed information about the PIT including the control word format is given in the data sheet in Appendix C The three timer counter circuits are in
111. rom DOS enter COPY A B or other destination drive specifier 1 8 Initializing Y ADA2000 Before you can operate the ADA2000 it must be initialized This step must be executed every time you start up reset or reboot the computer This sets up to properly communicate with the A D converter circuitry If the board is not initialized it will not respond to the software commands and will probably lock up requiring you to reboot your system As described earlier the ADA2000 uses 28 consecutive address locations in the computer s I O space These address locations start with the base I O address BA and go through 1B hex Table 1 2 provides the ADA2000 I O map defining what function each of the 28 addresses controls Recall that the base I O address is factory set at 300 hex On the demo disk the base I O address is usually stored in the variable board Remember to use the correct base I O address in the demo disk programs or your own programs The demo disk explains how to change the base I O address in the programs The ADA2000 is initialized by simply writing a control byte to the PPI1 control register mapped at the location base address 4 3 hex The control byte must conform to this general form 1 x00x where x don t care This ensures that the eight I O lines making up port B of PPI1 which are used to control the multiplexer and gain circuitry configured as outputs The don t care
112. rupt the CPU Software overhead is minimal and variable length delays can easily be accommodated General Some of the other counter timer functions common The 82 54 is a programmable interval timer counter to microcomputers which can be implemented with designed for use with Intel microcomputer systems the 82C54 are it is a general purpose multi timing element that can be treated as an array of 1 ports in the system Real time clock software e Even counter e Digital one shot The 82054 solves one of the most common prob Programmable rate generator lems any microcomputer system the generation Square wave generator of accurate time delays under software control In Binary rate multiplier stead of setting up timing loops in software the pro e Complex waveform generator grammer configures the 82C54 to match his require e Complex motor controller ments and programs one of the counters tor the de 3 84 82 54 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82054 to the system bus see Figure 3 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 A4 and Ag select one the three counters or the Control Word Regis ter to be read from written into A low on
113. s regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads reiurn un latched count Results Count and status latched for Counter 0 Command ignored status already latched for Counter 1 Figure 13 Read Back Command Example 82 54 5 Ao i 0 Write into Countero jo 0 1 Counters o 1 Write into Counter 2 Write controt word 0 o Read trom Counter o_ LO counters 10 1 Read trom Counter 2 L0 0 1 t 1 No Operation 3 State No Operation 3 State Lo 1 1 No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82 54 CLK PULSE a rising edge then a falling edge that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then
114. s are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 BIDIRECTIONAL DATA BUS 231256 3 Figure 3 82 55 Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions EXTERNAL INTERNAL PORT A DATA IN PIN INTERNAL DATA OUT INTERNAL 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port Bus hold Configuration 3 127 intel 82 55 82 55 OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see
115. s or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPEN
116. s the inverse designation The groups of signals for TC1 and TC2 are identical to TCO except that each has a CK input on the left side of the header connector Note that each signal name on the right side of the connector CK GT and OUT spans a group of two or three pins Each group can have only one jumper installed at any time The following paragraphs describe how these signals can be used in the PIT circuit An x is used in place of 0 1 or 2 in the signal names whenever the application can be applied to any or all of the three timer counter circuits XTAL ECO 5V EGO coo coo CK1 XTAL EC1 5V EG1 CO1 CO1 CK2 0110 OLD 042 145 LINO XTAL EC2 5V EG2 2 2 219 Fig 3 3 VO Header Connector Counter Inputs XTAL This input to all three timer counter circuits is from the 5 MHz crystal oscillator labeled Y 1 located near the center of the board By connecting XTAL to the CKx input on the right side of the connector with a jumper placed horizontally between the pins the 5 MHz clock is applied to the timer counter circuit If required by your application the XTAL frequency can be changed by installing a different crystal oscillator at Note however that the maximum frequency at which the PIT will operate is 8 MHz ECx This input allows an external clock other than the XTAL signal to control the timing of the corresponding timer counter circuit
117. se steps are all that are necessary to use your ADA2000 board This chapter explains how to install your ADA2000 and use its basic functions You will learn how to Change the base 1 O address setting Install the board in your PC Initialize the board Select the analog input channel and gain Take an A D reading Generate analog outputs This chapter allows you to immediately start using the basic functions of your ADA2000 board for data collection applications This chapter does not explain how to control the more intricate board functions such as the programmable interval timer the various digital O configurations or interrupts nor does itexplain how to change hardware controlled settings except for the base I O address The functions not covered here are described in Chapters 2 through 4 What Comes With Your ADA2000 The standard ADA2000 board package includes 1 ADA2000 10 4 inch 264mm interface board 1 ADA2000 demo disk 1 user s manual Additional items such as the ADA2000 cable set order number XK40 2 extender boards or SIGNAL MATH or ATLANTIS application software are available for this board and are included on an as ordered basis signals on your board are made easily accessible with Real Time Devices XB40 extender board and 40 expansion cable The extender board has two 20 pin terminal strips and a prototype area to support any special circuitry you may require to condition the signals For example if you a
118. ses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82 55 control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words trom the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port upper 7 4 Control Group Port B and Port lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82 55 contains three 8 bit ports A and can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to turther enhance the power and flexibility of the 82 55 Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold device
119. software also Writing a new count while counting does not affect the current counting sequence a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts 3 93 OUT will be high for N 1 2 counts and low for 1 2 counts 5844 1 1 GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE
120. supported by the hardware are 0000 gain of 1 0001 gain of 2 0010 gain of 4 0100 gain of 8 1000 gain of 16 It is recommended that no other bit patterns be used when setting the gain The general algorithm for setting the gain is 1 Read the current state of port B current_state inp base_address 1 2 Preserve the lower four bits since they contain channel information current_state current_state AND 0 3 Logically OR the current_state with a bit pattern that activates the desired gain current_state current_state OR gain bit pattern 1x bit pattern 0 2x bit pattern 16 4x bit pattern 32 8x bit pattern 64 16x bit pattern 128 4 Write the current_state back to port B base_address 1 current_state A BASIC program to seta gain of 2 is 100 BASE_ADDRESS 768 110 GAIN 2 120 STATUS INP BASE_ADDRESS 1 130 STATUS STATUS AND amp 140 IF GAIN 1 GOTO 160 150 STATUS STATUS OR GAIN 8 160 OUT BASE_ADDRESS 1 STATUS Taki A D After you have selected an analog input channel and set the gain you can take an A D reading It is important to note that once the gain and channel are set they stay at those settings until you change them that is they are latched You do not have to set the gain or channel every time you take a reading Each time an A D conversion is completed an end of convert EOC signal is generated to signify the end of the conversion This
121. tages is summarized below Analog Output D A Data 0 5 0000 10 0000 5 0000 0 0 9 9976 4 9976 9 9951 2 FUNCTIONAL DESCRIPTION This chapter describes the major functions of the ADA2000 interface board Figure 2 1 shows a block diagram of the board The functions discussed in the following sections are Analog to digital conversion circuitry Digital to analog conversion circuitry Programmable peripheral interface 1 Programmable peripheral interface 2 PPI2 Programmable interval timer PIT circuitry 5 B i spe p Fig 2 1 ADA2000 Functional Block Diagram 2 1 Analog to Digital ion Circuit One of the main functions of the ADA2000 interface board is to provide high speed analog to digital conversion capability for data acquisition The analog to digital A D conversion circuitry receives inputs from eight differential or 16 single ended analog channels selects one active channel and performs an analog to digital conversion of the voltage value read at that channel The conversion throughput rate is typically 38 kHz Multiplexers Two eight bit analog multiplexers are used to connect either one of 16 single ended or one of eight differential analog channels to the gain circuitry The leftmost three switches on DIP switch S1 set up the multiplexer at IC location U9 to receive either single ended or differential inputs When these three switches are up the multip
122. the same count into the counter GATE has no effect on our If new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CWx12 15843 158 3 12 158 2 0 FFEFFLO oir 231244 9 16 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles 1 enables counting 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also
123. ue above this voltage may not be linear and thus may adversely affect calibration After connecting the full scale voltage listed in the table to the channel 1 input adjust TR6 until the data flickers between the two values in the table under Full Scale 0 to 10 volts range Pt Offet TR7 Fu Scale TRG 0000 0000 0001 1111 0011 0011 Bipolar Calibration Whether you are selecting the bipolar input voltage range of S to 5 volts or 10 to 10 volts the following calibration procedure can only be performed with the board configured for a 5 to 5 volt input voltage range This means that the jumper on header connector P9 must be installed across the 10V pins If you are using the 10 to 10 voit range reposition the jumper on P9 across the 20V pins after you perform the calibration procedures below Two adjustments are necessary to calibrate the A D converter for bipolar voltage ranges one for offset and one for full scale To adjust the offset connect the voltage shown under the Offset heading in the table below to the channel 1 input of the multiplexer While continuously displaying 12 bit A D conversions adjust TR5 until the data flickers between the two values listed in the table under Offset Next connect the full scale voltage listed in the table to the channel 1 input and adjust TR6 until the data flickers between the two values in the table under Full Scale Bipolar Calibration 5 to 5 volts or 10 to 10 volts
124. un the SIGNAL MATH acquisition and analysis program Appendix E Configuring the ADA2000 for ATLANTIS contains information about setting board jumpers to run the ATLANTIS data acquisition and real time monitoring program Appendix F Warranty contains board warranty information When You Need Help When you are working with the ADA2000 interface board this manual and the demo software included in your package will provide sufficient information to properly control all of the board s functions If however after carefully reviewing the manual you are unable to obtain proper responses from the board Real Time Devices technical staff is ready to assist you For assistance call 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 Be sure to include your company s name your name your telephone number and a brief description of the problem 1 QUICK START GETTING YOUR ADA2000 RUNNING get started using your ADA2000 interface board you must Select by jumper a base I O address which does not contend with any other peripheral device Install the board into your PC Connect a signal to one of the analog input channels Run the ADA2000 software Unless you have other requirements the
125. y using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel 82 54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when Ay Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ay 11 5 0 RD 1 0 Dg Ds D4 D3 D2 Dy Do sci sco o 5 1 SCO specify counter to be latched Sci SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is
126. z Test ymbo aram M Conditions m Address Stable Before WR o m AddressHoldTimeAtterWRT 20 ns PotsA amp B eee a Hc Toner Do re two Data Hold Time After WA T 30 ns PotAa amp B _ ms Pomo 3 142 intel 82 55 OTHER TIMINGS Units WR 1 to Output Peripheral Data Before R Peripheral Data After RD ACK Pulse Width ST STB Pulse Width tps Per Data Before STB High Per Data After STBHigh ACK 0 to Output 1 to Output Float 1toOBF O 0to OBF 1 Oto 1 1to 0 Oto 0 1to INTR 1 twiT WR OtoINTR 0 Reset Pulse Width 9 et e d zi 38 gt tar Rij 00 see note 2 NOTE 1 INTR T may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum 3 143 inter 82 55 WAVEFORMS MODE 0 BASIC INPUT tro 231256 22 7 MODE 0 BASIC OUTPUT 231256 23 3 144 intel 82 55 WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT 231256 25 3 145 intel 82C55A WAVEFORNS Continued MODE 2 BIDIRECTIONAL DATA FROM 2080 TO 8255

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