An Introduction to
Contents
1. Altium An Introduction to Embedded Intelligence Summary This document provides you with an introduction to the world of Embedded Intelligence and FPGA design It takes a look at the design environment provided by Altium s Innovation Station including essential design concepts and also takes a look at final deployment of a design in the field Guide GU0123 v1 0 May 19 2008 With their ability to operate at high switching frequencies FPGAs have provided an ideal solution for implementing large amounts of high speed digital logic allowing the designer to reduce the size and cost of a product Today these devices have sufficient capacity to implement more than just some of the hardware in a product they can be programmed to implement an entire digital system including the processor peripheral components and the interface logic To do this the engineer needs a design environment that solves the system integration issues where they can capture the hardware design write the embedded software for the processor and implement test and debug both the hardware and software on the target FPGA Altium Designer brings together the required tools and the necessary communications systems Combine this with the Desktop NanoBoard reconfigurable hardware platform the NB2DSK01 and you have a complete FPGA design environment This guide will give you an overview of the key design concepts and the technologies and tools provided2. your product will be deployed in the field Altium provides a range of Deployment NanoBoards that you can either use entirely as an off the shelf solution or that you can customize with your own peripheral boards Alternatively you can go for a fully custom PCB solution The choice of deployment options will be influenced by a range of factors including cost time to market logistics and form and fit constraints Figure 12 Move your product to the field using one of the available Deployment NanoBoard solutions Revision History Date Version No Revision 19 May 2008 Initial release Software hardware documentation and related materials Copyright 2008 Altium Limited All Rights Reserved The material provided with this notice is subject to various forms of national and international intellectual property protection including but not limited to copyright protection You have been granted a non exclusive license to use such material for the purposes stated in the end user license agreement governing its use In no event shall you reverse engineer decompile duplicate distribute create derivative works from or in any way exploit the material licensed to you except as expressly permitted by the governing agreement Failure to abide by such restrictions may result in severe civil and criminal penalties including but not limited to fines and imprisonment Provided however that you are permitted to make one archival copy
3. intuitive streamlined and less prone to error TSES30004 1 REGBRANES a gt WBE INTERCOM WEM BUS US U6 Wishbone Interconnect TSK30004 32 Bit RISC Processor Wishbone Interface fl 7 Y i A i cxp IITTI UAN ANN Current Configuration BDU Inatalled Desug Hardware Inatalled Internal Menory 32 KB TSK30004 CLK CLK I RST RST I RegBarks SchDoc u10 Wishbone Interface UF Configurable Digital 10 CUR FE Pals dima CIR BANKG 0 BANK NUMG 0 ii CUR_VALG1 0 REG NUM 0 j S WE_INTERCON WB_INTERFACE Figure 5 Example bus based systems in Altium Designer OpenBus System based top and Schematic based bottom 4 GU0123 v1 0 May 19 2008 An Introduction to Embedded Intelligence For more information on the concepts and workings of the OpenBus System refer to the document AR0144 Streamlining Processor based FPGA Design with the OpenBus System For a tutorial that looks at taking an existing schematic based FPGA design and converting it to use the OpenBus System refer to the document TU0129 Converting an Existing FPGA Design to the OpenBus System PL FPGA Design for Embedded Developers this video takes a look at how easy Altium Designer makes it for Embedded Software Developers to take control over their hardware platform Custom Logic Quite literally custom logic is logic or intelligence that you cr
4. by this innovative design environment an environment that allows you to quickly and efficiently take your design and turn it from envisioned dream to deployed reality The Altium Innovation Station Take an FPGA design from concept idea to fruition and you will more than likely have an innovative product on your hands The environment needed to capture and develop that design needs to be equally innovative Altium Designer combined with the Desktop NanoBoard delivers just such an environment Referred to as the Altium Innovation Station this pairing of unified electronics design software with a reconfigurable hardware platform provides you with a design environment that places embedded intelligence at the center of the design process Altium Designer and the Desktop NanoBoard work seamlessly together to provide e One unified software hardware design solution e One design data model e One development platform e Complete hardware and software device vendor independence Figure 1 Altium Designer and the Desktop NanoBoard work in harmony to deliver the ultimate Innovation Station e Multiple hardware deployment possibilities With Altium s Innovation Station the low level detail is managed for you leaving you free to focus on embedded intelligence and functionality the source of true and sustainable product differentiation The designs you create are limited only by the extent of your imagination GU0123 v1 0 M
5. design refer to the document AP0103 Processing the Captured FPGA Design iT How do I create an FPGA design this video covers the basics of getting a simple FPGA design up and running PL How do I build an FPGA design this video looks at processing a design and running it on some target hardware PL FPGA Design for Board Level Designers this video takes a look at how you can leverage your existing board level design skills to begin designing FPGA circuits today Mapping Mapping is a method by which your design can be interfaced to the physical pins of the FPGA device in which it is programmed Put another way it is the means by which your design can interact with the outside world By mapping internal digital signals to the device pins your logic is able to communicate to other areas of your product As part of this mapping you would also define analog characteristics of the pins such as IO standards drive strengths and slew rates In Altium Designer this mapping is achieved using ports or port components configurations and constraint files An FPGA design can have multiple defined configurations with each configuration containing the constraint files pin mappings clock constraints place and route constraints required to target a different physical device FPGA Ready Vendor independent Components FPGA Project Constraint File Containing Clock constraints and additional non architecture specific d
6. s Desktop NanoBoard NB2DSK01 is a unique reconfigurable hardware platform that harnesses the power of today s high capacity low cost programmable devices to allow rapid and interactive implementation and debugging of your digital designs The Desktop NanoBoard is designed to be a perfect complement to Altium Designer transforming your desktop into a complete and interactive electronics design laboratory that uses LiveDesign LiveDesign is a unified electronics system design methodology that is based on live engineering inside a programmable physical hardware design space Altium Designer the NanoBoard and LiveDesign provide real time communication and hands on interaction between you and your design during the development process The Desktop NanoBoard gives you the ability to design implement and debug an entire design before deploying that design in the field At the heart of its reconfigurable nature are e Swappable daughter boards enabling you to target a range of different programmable devices allowing you to compare the performance benefits and trade offs of different FPGAs without changing the actual design e Satellite peripheral boards delivering additional hardware resources available to the daughter board FPGA and providing a simple and cost effective method for rapid prototyping of hardware concepts Once implemented on the Desktop NanoBoard your design can then be probed analyzed and debugged interactively us
7. the design Imagine being able to jump inside the physical FPGA device armed with an oscilloscope multimeter and logic analyzer and you ll have some idea of what these instruments can offer as part of a live debugging environment GU0123 v1 0 May 19 2008 7 An Introduction to Embedded Intelligence Custom Instnument Data Inf7 0 Data Ont 0 e Override Figure 9 Monitor and control I O using a custom instrument just one of a variety of virtual instruments for use in an FPGA design COSTOM INS TROMENT Instrument Rack Soft Devices JTAG CORE mAT RDR IT AON ae TAO fs fs Tru er d y Ff y Finis ee y feu Pra ae Pe ea g6 126 160 Each of these various controls reflect the value currently set by the NanoBoard s DIP Switch Use this control to set the value for the Data _Owt signal 0000 1111 and control the LEDs on the NanoBoard during normal operation DAUGHTER BD TEST RESET when lit The input signal Data_In is hooked directly to these controls Embedded software can be debugged in real time once the FPGA design and associated program code have been programmed into the physical FPGA device The debug environment offers the full suite of tools you would expect to see in order to efficiently debug the embedded code These features include BE gt Setting Breakpoints Adding Watches Stepping into and over at both the source cC and instruction asm level Reset
8. Run and Halt code execution Run to cursor An example of using virtual instrumentation in an FPGA design can be found in the base tutorial document TU0116 Getting Started with FPGA Design For a tutorial that looks at using the Custom Instrument component refer to the document TU0135 Adding Custom Instrumentation to an FPGA Design How do I use instruments in my FPGA design this video looks at the use of embedded instruments in an FPGA design the button on the NanoBoard is currently depressed and the hardware override is activated Click this button to toggle the state of the software override TSK30004 Running Pause Continue d Reset a Single Step Example Instrument C TSk30004_SRAM32_TopSCHDOC Devices E tsk3000_istructiontest asm Result BNE Result _BGEZ Result _BGTZ Result _BLEZ Result_BLTZ global START Section text MainsStart Figure 10 Entering an embedded code debug session equ equ equ DataMemoryBase DataMemoryBase DataMemoryBase DataMemoryBase DataMemoryBase DataMemoryBase 0x03 xC gt PRIP 0x14 0x18 0x91 0x92 0x93 0x94 0x95 0x244 0x243 Ox24C 0x250 7 0x254 7 Ox260 0x264 Two test GU0123 v1 0 May 19 2008 An Introduction to Embedded Intelligence then Interactively Test amp Debug using the Desktop NanoBoard Altium
9. ay 19 2008 1 An Introduction to Embedded Intelligence Create the Embedded Intelligence using Altium Designer Altium Designer brings together hardware software and programmable hardware design within a single unified environment This integrated environment provides all the tools necessary to create the embedded intelligence for your product the hardware design itself and the embedded software which is destined to run on any soft processors defined within that design Embedded Intelligence Concepts From the outside an FPGA device does not look particularly interesting seen one seen them all Once programmed however the device comes alive with engineered functionality becoming the heartbeat for the electronic product in which it resides It is this functionality or Embedded Intelligence that we are concerned with when creating an FPGA design The actual content of an FPGA design will depend on the nature of that design the functionality it requires and the end task that it is to perform To effectively develop embedded intelligence there are some essential concepts that you will need to understand Embedded Intelligence Embedded Intelligence is an umbrella term for all elements that are downloaded into the product to give it its functionality This includes the FPGA design itself as well as any embedded program code required by processors within that design The term reflects perfectly the soft na
10. d go to town with the associated embedded code functionality For an introductory tutorial that looks at an FPGA design incorporating a 32 bit processor refer to the document 7U0128 Implementing a 32 bit Processor based Design in an FPGA For an introductory tutorial that explores Embedded Software design in Altium Designer refer to the document TU0122 Getting Started with Embedded Software PL How do I decide which processor to use this video gives a brief overview of the various processors supported by Altium Designer and how to choose the one that is right for your application PL How do I add peripherals and IO to my processor this video looks at using Wishbone to customize the mix of peripherals that you use in your embedded application Hardware Acceleration Hardware acceleration is the concept of enhancing the speed of a design by imparting software processes into hardware Many computational algorithms that are straightforward to code and debug in software are inherently parallel in nature Encryption algorithms image manipulation and signal processing are just some examples To remain as software entities such functions place heavy demands on the processor FPGAs themselves are parallel in nature offering the ability to perform multiple operations simultaneously To move computationally intensive functions from software into hardware and ease the burden of the processor would therefore be considered an evolutional jum
11. e size of the address bus width It main should be large enough to address the parameters of the largest function in the design rotate set_tabs A Address Bus Width E Select the number of spaces after the parameter bus on the schematic Extra space 10 Figure 8 The ASP component interfaces between the code running on the processor and the functions implemented in the FPGA fabric For a tutorial that explores the use of hardware acceleration in an FPGA design refer to the document 7U0130 Getting Started with the C to Hardware Compiler For detailed reference information on the C to Hardware Compiler refer to the document GU0122 C to Hardware Compiler User Manual For information on the ASP component refer to the document CRO177 WB_ASP Configurable Application Specific Processor Debugging Debugging is the act of testing you hardware design and any embedded software running on soft processors therein to obtain the desired correct performance and functionality Debugging is an important element of the overall design strategy and effective debugging can save a lot of time and money when it comes time to deploy your end design in the field In Altium Designer debugging of hardware is provided courtesy of virtual instruments components which are wired into the actual FPGA design but which on programming the physical device offer software based controls for interrogation and control of nodes within
12. eate yourself and add in to your design You would typically add your own custom logic into a design where the functionality required cannot be implemented using the FRGA ready components shipped with Altium Designer In Altium Designer custom logic is implemented using a hierarchical design approach and using any combination of generic logic components C or HDL code VHDL or Verilog In addition provision of a Custom Wishbone Interface component allows you to quickly hook your custom logic into your existing bus based system creating your own Custom Wishbone Peripheral without needing any knowledge of the workings of that bus system L GeneratePulse i Jervecters 2 GO I Gy I Betas 2 DONE fs J Description sc eS pulses when GO I transitions i f Finclude lt stdbhool Wh static bool s_Gerrey yoid GeneratePuisetbooi C_I bool Gi_PULSE Oj Figure 6 Adding custom logic through creation of hierarchical FPGA designs Vendor specific FPGA primitives can also be used to provide the desired functionality but use of such devices limits the portability of the design locking it into a specific device family or in some cases specific physical FPGA device An example of hierarchical FPGA design and the use of custom logic can be found in the base tutorial document TU0116 Getting Started with FPGA Design For a tutorial that explores the use of creating custom logic using C refer to the document 7U0133 D
13. esign constraints Constraint File Containing Place amp Route Constraints for any Spartan 3 implementation Constraint Files Containing Mappings from FPGA Project Ports to pins of XC3S1500 4FG676C on Daughter Board DB30 Source Design Files Schematic OpenBus System HDL Configuration A Xilinx Spartan 3 XC3S1500 4F G676C on Daughter Board DB30 Flow Peripheral Board Constraint File t Video Output VGA_VSYNC qa Interface Mapping Constraint File NB2DSK01 Motherboard Constraint File VGA_HSYNC Interface Mapping Constraint File Q Daughter Board DB30 Xilinx Spartan 3 XC3S1500 4FG676C Desktop NanoBoard NB2DSK01 Daughter Board Constraint File A8 B8 Xilinx Spartan 3 FPGA Example Port to Pin Mapping Figure 4 Targeting a design to a physical device on a daughter board plugged into the Desktop NanoBoard The example mapping illustrates a couple of signals associated with a resource on a peripheral board and their subsequent mapping path to the physical pins of the target device GU0123 v1 0 May 19 2008 3 An Introduction to Embedded Intelligence For more information on the concept of configurations and constraints and their role in design portability refe
14. esigning Custom FPGA Logic using C For more information on the Custom Wishbone Interface component refer to the document CRO187 WB_INTERFACE Custom Wishbone Interface For more details on building your own core component refer to the document 7U0123 Creating a Core Component Lo How do I use VHDL or Verilog in an FPGA design this video looks at how blocks of VHDL or Verilog can be included in an FPGA design PL How do I create and share an FPGA Core this video looks at creating FPGA components that allow you to reuse your FPGA design blocks across multiple projects without exposing your IP GU0123 v1 0 May 19 2008 An Introduction to Embedded Intelligence Soft Processors and their Embedded Software Soft processors are processors that are defined as part of the FPGA design that is programmed into the physical FPGA device rather than physical discrete devices connected to the FPGA or processors that are immersed as part of the physical FPGA s makeup Such processors are typically 32 bit and have simple RISC architectures Embedded software refers to the code the software smarts that gets downloaded to the physical FPGA device and which will run on a soft processor defined within the FPGA design The beauty of using soft processors in FPGA designs is that you are not locked to a physical device You can change processor or modify the code running on it simply by reprogramming the physical FPGA device
15. ing an array of virtual instruments and JTAG based monitoring features As the implementation is performed within a programmable hardware realm you can update the design quickly and many times over without incurring cost or time penalties 3 1 VGA 24 Bit RGB 4 Beas Tce sy tos 4 a A J E 3 cut y gim i H a Fe 3 I ae cig on o y a Ca Sis E ET TIA ue 0 1 C46 10 co 2 yo com e t com on wi Oo 1 5 vi e af PB01 REV 1 03 Audio Video Peripheral Board PBO3 REV 1 03 USB IrDA Ethernet Peripheral Bo ard T NA Altium NanoBoard F Bafi g UN Da Bits Ria S ADER B AE Figure 11 Altium s Desktop NanoBoard NB2DSK01 For detailed information on the NB2DSKO01 refer to the document TR0143 Technical Reference Manual for Altium s Desktop NanoBoard NB2DSK07 For information on communications between the Desktop NanoBoard and the PC refer to the document AR0130 PC to NanoBoard Communications For information on the range of supported daughter and peripheral boards available for the Desktop NanoBoard and additional documentation specific to each go to www altium com nanoboard resources GU0123 v1 0 May 19 2008 9 An Introduction to Embedded Intelligence and Ultimately Deploy to the Field Once you have your FPGA design and associated embedded software for any processors running bug free on a Desktop NanoBoard it is time to consider how that design
16. of said materials for back up purposes only which archival copy may be accessed and used only in the event that the Original copy of the materials is inoperable Altium Altium Designer Board Insight DXP Innovation Station LiveDesign NanoBoard NanoTalk OpenBus P CAD SimCode Situs TASKING and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed v8 0 31 3 08 10 GU0123 v1 0 May 19 2008
17. p for the design In Altium Designer hardware acceleration is facilitated using the C to Hardware Compiler CHC which takes standard untimed ISO C source code and produces a synthesizable hardware file RTL Upon synthesis this RTL description is translated into an 6 GU0123 v1 0 May 19 2008 An Introduction to Embedded Intelligence electronic circuit that implements the function required A soft processor in the FPGA design accesses these hardware functions through use of an Application Specific Processor ASP GPIO VIDEO LA ut K 0 s MULTIMASTER_1 P F part ji i it ae i O 1 Qe aenn BO Fuocessar Configure ASP WB_ASP Properties ASP ASP Options Symbols In Hardware Q Processor MCU Global Yariable Allocate in Hardware l bt656_settings Use the following options to enable or disable costab v acceleration You can do this at either the FPGA or imgbuf the processor code level sintab v BC TFT The Generate ASP option controls whether any FPGA tft 7 logic is generated Disable this option to globally EG O disable the ASP and not generate any FPGA logic The Use ASP from Software option controls whether the code running on the processor will call the ASP or not Disable this option to disable the use of the ASP while retaining the ASP logic in the FPGA Generate 4SP Use ASP from Software Parameter Bus Options Function Implement in Hardw Export to Software init Select th
18. r to the article AR0124 Design Portability Configurations and Constraints For more detailed information on the Desktop NanoBoard NB2DSKO01 constraint system including auto configuration refer to the application note AP0154 Understanding the Desktop NanoBoard NB2DSK0O1 Constraint System For a tutorial that looks at how signal integrity can be used to determine optimum slew and drive settings for specific pins of an FPGA device refer to the document 7U0126 Checking Signal Integrity on an FPGA Design PL How do I target and constrain an FPGA design this video covers creation of a configuration that targets your FPGA design to run on a specific device i How do I setup FPGA IO this video looks at setting up your FPGA IO to interface to the outside world Bus based System A bus based system is the term used to describe a method of connecting functional building blocks of logic into an overall system using generic buses In this way you can quickly assemble a system that incorporates a diverse range of functionality and that will meet the needs of your intended application In Altium Designer such a system is built using the Wishbone bus interconnect and can be implemented as a high level abstract OpenBus System document or at the low level using Wishbone compliant components placed on schematic sheets OpenBus Systems are the favored approach as they provide an environment in which to build your system that is highly
19. tion Phase placing and wiring the ingredient logic for the design and ensuring that it is free of electrical and drafting errors e Configuration Phase targeting the design to the physical device into which it is to be programmed see the next section Mapping e Processing Phase the job of turning the design from captured source files into a programming file that can be downloaded to the targeted device In Altium Designer the design is created and managed within an FPGA project In terms of design capture a variety of FPGA ready and vendor independent components are supplied for use in your FPGA designs When it comes to processing the design Altium Designer RAMSE provides a central interface from where the design can be Figure 2 FPGA ready components vendor independent building compiled synthesized built using the appropriate and blocks that enable designs to be created quickly and retargeted to alternate physical devices installed Vendor tools and dowloaded into the device 2 GU0123 v1 0 May 19 2008 An Introduction to Embedded Intelligence c Spartans 40351 500 4F S676C Reset Figure 3 Processing of an FPGA design within Altium Designer literally at the click of a button For an introductory tutorial that covers the basics of FPGA design using the Altium Innovation Station refer to the document TU0116 Getting Started with FPGA Design For information on processing an FPGA
20. ture of a design who s intelligence is embedded into a high capacity programmable device By moving functionality out of the physical domain and into the soft you are able to create the device intelligence needed to generated sustainable differentiation of your end product in the market place The following are just some of the key benefits of soft design e The IP that you program into the system is better protected than physical IP as the source isn t shipped with the product e Soft design can happen before and after the hardware platform is designed e Soft design can continue after the product is manufactured and deployed to the end customer This includes aesthetics implemented in the soft design e Soft design provides the basis for an ecosystem which connects your customer to you via your products PT How do I choose an FPGA device this video looks at how to find the best suited FPGA to host your design iT Building a complete Embedded FPGA application from scratch this video takes a look at just how quickly you can create a complex design such as a video capture application using Altium Designer FPGA Design This is the hardware design itself which will be programmed within the physical device It will contain all of the logic and TSKS000A 32 Hit RISC Processor connectivity and typically feature a processor system There are three important phases to consider when creating your FPGA design e Capture amp Verifica
21. with a modified hardware design or updated embedded code leading to true field upgradeable hardware and software In Altium Designer a wide range of 32 bit soft processors are supported for use within your FPGA designs The associated software code is created and managed within an Embedded Software project TSK3S0004 32 Bit RISC Processor ff initialize registers IO ADR O 25 0 ALE for i 0 i lt NUM BANKS i 10 DAT_I S1 0 IGL GHD i 10_DaT_Of3l o Ej main c int main ivoid uint32_t regBank reqNum regVal Mint3sZ t i j wbh_interface_set_change_reg_bank Base_REGBANKES i for j 0 j lt BANK_SIZE wh_interface_set_reg Base_REGBANKS j i BANK_SIZE j a 4 a E a d IO WE Current Configuration Installed ff read user input while 1 ff activate the selected register bank Debug Hardware Installed Intemal Hemoxy 32 EB regBank wb_interface_get_user_sel_bank Base_USER_IO wh _ interface _set_change reg bank Base REGBANKS regBank ff retrieve the selected register s value TSES0004 CLE CLE regNum wb_interface_get_user_sel_reg Base_USER_I0 RST _ EST _I req al wbh_interface_get_reg Base_REGBANKS regNum ff display the register value wbh_interface_set_ display reg_val Base_USER_IO regVal ff add sall delay for i 0 i lt 20 i nopi return 0 Figure 7 Add a 32 bit soft processor to your design an
Download Pdf Manuals
Related Search