SMT381 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. L 4 3 1 Mux with Dual Output Fanout Buff MER MMBX Clock Div 8 External Trigger External Trigger Input MMBX LVPECL Buffer FPGA SMT338 VP Figure 2 Clock tree of the SMT381 The main clock tree of the SMT381 consists of two clock sources to achieve the DAC s full range of input frequencies DC 500MH z The first clock source is a MICREL clock synthesizer which has a range from 50MHz to 950MHz This source s disadvantage however is that it has a jittery output and thus the clock is not that stable Its advantage however is that it can attain a wide range of frequencies especially the lower frequencies The output clock is LVPECL The second clock source is a Voltage Controlled Oscillator VCO with a phase lock loop This combination has a very stable output However a limited frequency range can be attained by this combination 800M Hz 600M Hz This is achieved by taking a 600M Hz 1200MHz VCO and dividing the output by 2 The output clock must also be scaled to LVPECL Alternatively the user can provide the module with an external LVPECL clock or an external RF clock The user can select between any of these input clocks Page 11 of 31 The selected clock then drives the DAC and is also distributed to the base board for data synchronization purposes On the FPGA of the base board a PLL synchronizes the clock with2. 22 Teles Clock dac 381vyv4 task EE 24 7 1 4 Clock dac 381v4 div4 task 25 OS 25 Ee 25 GEN AR TIBI E 25 8 Physical Proper TE 26 Bd Mechanical interlace a de ee UU N DO M EUH 26 S2 Ice sersan EE EE late 26 9 SLV e E 27 TON ER 28 11 1 Description of the COS DES nada eco tr dede den an de an 28 11 1 1 The Reset Register Write Add 000 eneve 28 11 1 2 Temperature Registers Read Add 0x020 0x021 0x028 0x029 28 11 1 3 DAC Clock Source Registers Write Add Ox801 29 11 1 4 Clock Synthesizer Setup Register Write Add 80 0 29 11 1 5 PLL Setup Registers Write Add 0x802 0 809 30 11 1 6 Data Source Selection Write Add Ox80E 30 11 1 7 DAC Setup Registers Write Add 0x900 0x905 31 Table of Figures Figure 1 block diagram Of the SMT38 gen 9 Figure 2 Clock tree of the SMT38 gn 11 Figure 3 Option 1 for the SMT381 analog output stage 12 Figure 4 Option 2 for the SMT381
3. Length 106 68 mm Height 21mm Maximum SMT381 36 71grams SMT381 VP 94 30 grams SMT381 VP including fittings 97 40 grams Table 5 SMT381 VP Dimensions 8 2 Electrical Interface The following voltages are required by the SMT381 and must be supplied over the daughter card power connector Current Voltage Required D45VO IN 500 mA D 12V0_IN 250 mA D 12VO IN 250 mA Table 6 SMT381 Power Supply Voltages User Manual SMT381 Last Edited 12 06 2007 10 43 00 The following table lists the internal SMT381 voltages that are derived from the voltages that are provided over the daughter card power connector Table 7 Internal Power Supply Voltages 9 Safety This module presents no hazard to the user when in normal use 10 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot 11 Appendix 11 1 Description of the registers 11 1 1 The Reset Register Write Add 0x000 The reset register is used to reset the firmware and some of the components of the SMT381 Writing a T will put
4. CC CE CO EE Imm era WM esenca IT eleng ED ET TT CC EL mere SSS gt RM Ree IT gt IC DestertsdsTenmner u 8 1 E OX029 Reserved 0x029 DaughterCardDiodeTempReg Jac modste specie pac moane Specie CE o reena oO CET Ten TT Imm sss eg MES Rei Imm seen ue esi MN Rei mam suamque or era Imam eem Rest BER Rer 0x809 Smt381Pll RfN Reg2 0x809 Reserved mm mess 1 BER Reet m eg MM ere Imp mes Immp mes 1 BD Ree nM Data source sorection EL ET TT MERI ere Imam om Immr Table 4 registers memory map 7 1 3 Clock dac 381v4 task This task generates the clock that is used to send the samples to the DAC It implements a Delay Locked Loop The task has 1 input channel and 1 output channel User Manual SMT381 Page 24 of 31 Last Edited 12 06 2007 10 43 00 Input 0 Used to reset the task Output 0 Bit 0 the clock used to send data to the DAC Bit 1 the clock used to send data to the DAC divided by two Bit 2 the clock used to send data to the DAC divided by four Bit 3 the clock used to send data to the DAC divided by eight Bit 4 the locked signal of the DCM used in this task The Diamond clock domain generated by this task should be used to clock task DAC3881 7 1 4 Clock dac 381v4 div4 task This task generates a Di
5. analog output stage 13 Figure 5 Combined analogue output circuit 13 Figure 6 Waveform Memory Time View Capture 1000Msps VCO 125MHz E E 14 Figure 7 Measurements of Capture 1000Msps VCO 125MHz analogue output 15 Figure 8 Waveform Memory FFT 1000Msps VCO 125MHz analogue output Beet E 15 Figure 9 Waveform Memory FFT 1000Msps VCO 125MHz analogue output ORATOR ators 16 Figure 10 Waveform Memory FFT 600Msps VCO 75MHz analogue output NT e 16 Figure 11 Waveform Memory FFT 600Msps VCO 75MHz analogue output CAO EE 17 Figure 12 Connector Location on 9141 361 18 Figure 13 Test point locations on the SMT381 20 Figure 14 example block diagram ss 21 Figure 15 Setup Packet UFUCLUEPe i ose roe tnrba Azaro zeg Seege 22 Figure 16 Packet Structure Defined Commands 22 Figure 17 Reset Register Write Only 28 Figure 18 Temperature Registers Read Only 29 Figure 19 Clock Source Selection Table Write Only 29 Figure 20 PLL Setup Registers Write Only pana ni dhi 30 Nene KREE 31 Figure 22 DAC Setup Registers Write
6. latches All digital functions on the module are controlled by the FPGA of the base board 4 2 Main analogue features The main analogue characteristics of the SMT381 are listed in the following table Analogue outputs Data Format Analogue current External sampling clock inputs The clock frequency is divided by 2 on the SMT381 for a DDR clock for the DAC LVPECL Clock Signal format LVPECL DR DAC performance Single tone at 1dBFS 800MSa s DC to 400MHz From DAC datasheet Spurious Free Dynamic Range SFDR 20MHz 75dBc Spurious Free Dynamic Range SFDR 300MHz 58dBc Cross talk 4 tone test each tone at 15dBFS centred at 67dBc 276MHz Table 1 main analogue features 4 3 Clock structure There are two integrated clock generators on the module The user can either use these clocks or provide the module with an external clock input via MMBX connectors The following figure shows the SMT881 clock tree User Manual SMT381 Page 10 of 31 Last Edited 12 06 2007 10 43 00 External Clocks i Clk Synth 50MHz VCO 600MHz T 950MHz 1200MHz ExtRF tt li LVPECL ME i Clock Clock CkSynh d Ges Input i i i Input i MES MMBX i v Voltage Controlled Oscillator ECL ECL Comp Reciever arator Driver Comparator TEE 3 div 2 gt e dl Lk 2
7. the data being sent by using the supplied clock and looping that same clock to the DAC and back This technique synchronizes the clock to the data is being sent out on base board side even further with the clock used in the DAC Synchronization issues become a bigger factor as the clock frequencies get bigger All the clock control is done on the base board in firmware on the FPGA 4 4 Analogue output Two options are hardwired into the design The options are shown below with a figure of each Option 1 Single ended AC coupled output with Macom TP 101 transformer Output Connector vov Figure 3 Option 1 for the SMT381 analog output stage Option 2 Differential DC coupled output with and channels going to separate connectors Output Connector Output Connector R2 2 R2 it d Figure 4 Option 2 for the SMT381 analog output stage Combined circuit The two combined 0 ohm TP101 0 ohm Figure 5 Combined analogue output circuit Depending on whether an AC or DC coupled version is ordered the board will be assembled accordingly to either give the AC or DC coupled circuit shown above For more information consult the Fujitsu MB86064 DAC datasheet 4 5 SLB The SMT381 connects to a base module SMT338 VP SMT398 VP SMT368 via the SLB connector Refer to the SLB specification document for more information 5 Performance 5 1 Waveform Memory In the following captures the
8. 03 External ECL Clock SC On board VCO 0x0005 On board Clock Synthesizer 0x0006 External RF Clock 0x0007 External RF Clock Figure 19 Clock Source Selection Table Write Only 11 1 4 Clock Synthesizer Setup Register Write Add 0x800 This register sets up the frequency of the clock synthesizer on the SMT381 Any write operation to this register will trigger the clock synthesizer interface control logic to initialize the clock synthesizer with its new value For a detailed description of the configurable bits in the Clock Synthesizer register please refer to the Clock Synthesizer section under Firmware Building Blocks at the end of this document Page 29 of 31 Last Edited 12 06 2007 10 43 00 11 15 PLL Setup Registers Write Add 0x802 0x809 These registers set up the frequency of the PLL circuit on the SMT381 There are two sets of registers one set for setting up the IF side of the PLL and the other set for setting up the RF side of the PLL The IF side is unconnected while the RF side is connected to a 600 1200 MHz VCO circuit which is divided by two before entering the DAC at a frequency of 300 600MHz All registers must be initialized and only when writing to the final register will both the IF and RF side be configured to their new values Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Smt381Pll RfR Reg1 Smt381Pll RfR Reg1 Smt381Pll RfR Reg2 Smt381Pll RfR Re
9. 38 VP 2 1 Referenced Documents 2 2 Applicable Documents 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations 3 2 Definitions 4 Functional Description 4 1 Block Diagram The following diagram represents the architecture of the SMT381 daughter module Base module SLB connector Control Control Y Low jitter SEET local ME oscillator aie m E e External clock Channel Channel B Figure 1 block diagram of the SMT381 The SMT381 is a daughter board that plugs onto a base board The base board sends the digital samples for the DAC and control data for the on board clocks and the DAC via the SLB connector There are two DAC cores present in the MB86064 Thus two channels are available for outputs The outputs of the DAC are differential currents which are converted to a voltage by the analogue output stage RF Transformer There are three sources for the sampling clock of the DAC e the on board VCO e the on board Clock synthesizer e the external clock can be provided as an LVPECL clock or as an RF clock two separate inputs The sampled data can either be supplied to the DAC cores externally via its LVDS data bus or internally from the Waveform Memory Module The data may be routed to the DAC cores through a number of paths The most direct path routes data straight from the LVDS input buffers to the DAC core input
10. Only 31 1 Introduction The SMT381 is a single width expansion daughter module capable of converting two external digital inputs at 1Gsps with a resolution of 14 bits A Fujitsu dual channel DAC MB86064 performs the digital to analogue conversion The SMT381 plugs onto a base board which provides an FPGA to interface to the DAC and control the SMT381 Base board currently available with the SMT381 are e SMT338 VP e SMT368A 1 1 Module Features The main features of the SMT381 are listed underneath e Dual channel DAC e 1 GSPS conversion frequency e 14 bit data resolution e Custom Clock and Trigger inputs via external connectors e Internal Waveform generator e Standard Sundance comport and SHB interfaces for easy interconnection to Sundance products via base module 1 2 Possible applications The SMT381 can be used for the following applications this non exhaustive list should be taken as an example e Broadband cable modem head end systems e 3G Radio transceivers e High data rate point to point radios e Medical imaging systems e Spectrum analyzers 1 Note that when the SMT381 is coupled with the SMT338 VP sampling rate of 1Gsps is only achievable when using the internal memory of the DAC Limitations in the Virtex2pro architecture limit the frequency to 840Msps with the parallel interface of the DAC 2 Related Documents Sundance LVDS Bus SLB specifications Fujitsu MB86064 DAC datasheet SMT368 SMT3
11. Unit Module Description 1Gsps dual channel 14bits DAC Unit Module Number SMT381 Document Issue Number Original Author Jean Philippe Arnaud User Manual for SMI381 Sundance Multiprocessor Technology Ltd Chiltern House VVaterside Chesham Bucks HP5 1PS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2006 Certificate Number FM 55022 Revision History 10 New New document 0 0000 0612007 ES Table of Contents 1 BENE OCC GEO E 6 LL ee ER Feat r s ann cn 6 1 2 POS app Te E 6 2 Rented DOCUMENTS n add e od E 7 2 1 Referenced Documents vasaqomeiecesasasnctaasemaaueneswadensdasedanuseeseiaesesiasace 7 22 Appi ae ana dint ans en ee ad en un 7 3 Acronyms Abbreviations and Definitions cccccssscsssccsscccssccssccsssccsscccssceess 8 3 1 Acronyms and Abbreviations cccccccccsscsrsosrsesrpesccesccesccesccesacessosrsesrpesspasssascoascs 8 TU EE 8 4 Fanctional TICS CLI GION eege 9 4L Poek PIV AC RR m 9 42 Manandlopu EE 10 GE TO ee ee 10 d OS A OUR E a DENEN Utd 12 CT E eem 14 5 BOT EEN 14 LO MO a dtp ri Dosis SN bU DNE 14 6 eet 18 DI COM 2 DEE 18 GC Te Emm 19 7 SUPPO l AaCc E 21 re SIV EE 21 ll SSNDESSICOBLUPOD E 22 11 2 655 5
12. amond clock domain running at one eighth the sampling frequency of the DAC It receives the clock from its input channel which should be connected to task clock dac 381v4 7 1 5 DAC381 task This task interfaces to the DAC It receives the samples for the DAC on its input channels and sends them to the LVDS interface of the DAC This task interfaces to the two DDR 14 bits LVDS ports of the DAC It runs at half the sampling frequency of the DAC samples for channel A Input 1 samples for channel B Input 2 Bit 0 reset the task when T Input channels 0 and 1 carry two samples at a time on the 32 lower bits of their data bus Bits 15 to 0 first sample Bits 31 to 16 second sample 7 1 6 Sine task This task generates the samples of a sine wave 7 1 7 Duplicate task This task duplicates on two output channels the data coming on its input channel 8 Physical Properties 8 1 Mechanical Interface The depth of the SMT381 combined with a base board is about 21 mm If the SMT381 18 mated with a PCI carrier two PCI slots will be required for the Module Carrier combination If the SMT381 is mated with a cPCI carrier the Module Carrier will require two cPCI slots The following table lists the dimensions for the SMT381 and the SMT881 coupled with a SMT338 VP SMT381 VP Width 63 5 mm Module Dimensions Only Length 106 68 mm SMT381 Height 21mm Maximum Width 63 5 mm Module Dimensions SMT381 VP
13. are the following address The data is sent on the output channel 0 Figure 16 Packet Structure Defined Commands User Manual SMT381 Page 22 of 31 Last Edited 12 06 2007 10 43 00 Example 1 Sending Ox1001FFFF to the task will Write to Address 0x001 Data FFFF Example 2 Sending 0x2801xxxx to the task will request a Read from Address 0x801 The data will be written to the output channel 0 7 1 2 2 Registers addresses The following figure shows the memory map for registers Detailed description of the registers is provided in appendix mn Il enn CECR EE OR Rees EC Rene ERR nu OT ERR mur TT ERR nus TT ERR Reece IT GER rasen IT SC EE CE TT WEB missense 0008 reer MEC MED SmeseiPn inet o0 mr MER SmeseiPn inne 1 0008 reer EE hour Posi bo seem Pe rea WO MEI sm Pn esa M Renee ME zum ee g BM MUR smesei Ciko B nor TT MU Smeseicioexsoureeseect OM T B Rees O S S SOSO MM eera Linen TT ME era B Rene ME mes o Rene TT reer MER era EC ET TT User Manual SMT381 Page 23 of 31 Last Edited 12 06 2007 10 43 00 ER EE eleng LIRE nene SS gt EC ET TT Inm era ASC roms WM eleng EC esenca IT
14. ean Cn NI zl 4 Cn poimi OD D 0 Figure 7 Measurements of Capture 1000Msps VCO 125MHz analogue output E J4 E 1 TDS2024 MATH1 10 dB 25 MHz Figure 8 Waveform Memory FFT 1000Msps VCO 125MHz analogue output Channel A 1 ui AU Figure 9 Waveform Memory FFT 1000Msps VCO 125MHz analogue output Channel B 5 T 1 TDS2024 MATH1 10 dB 25 MHz Figure 10 Waveform Memory FFT 600Msps VCO 75MHz analogue output ChannelA User Manual SMT381 Page 16 of 31 Last Edited 12 06 2007 10 43 00 qp Ll 1 TD352024 MATH1 10 dB 25 MHz Figure 11 Waveform Memory FFT 600Msps VCO 75MHz analogue output ChannelB 6 Footprint 6 1 Components location The following diagram indicates the location of all the important connectors and components on the SMT381 Rev 1 PCB AI ap Re eee e 2 Bee gc ee t Un ron eee d r zi 23 zo ToT n must mi am Fa si Ta re es j n La Se u uL LI Sie z uu rh v1 ip OR CH nu L al TER PEPE REIT ETE i p N f FILI ER em TPE ar Z f fork 1 i Fir Fi deri i MASSE PT Tere ay 5 GL S v T Li i Fi S lt H 1 1 if SU rr Figure 12 Connector Location on SMT381 Diagram Pcb Descript
15. g2 Smt381Pll RON Regl Smt381Pll RON Regl Smt381Pll R N Reg2 Smt381Pll R N Reg2 Figure 20 PLL Setup Registers Write Only For a detailed description of the configurable bits in the PLL registers please refer to the PLL Configuration section under Firmware Building Blocks at the end of this document 11 1 6 Data Source Selection Write Add OxSOE This register selects between four data sources Ox1 Ox80E Not Used 6 4 Channel B selection 2 0 Channel A selection What follows applies for Channel A and B Register Channel Data Source Value 0x0 Look Up Table A Fixed sine period is stored into a block of ROM as 32 samples SHB to DPRAM In this mode 32 samples per channel are loaded via SHB to be played back continuously and sent to the DAC Ox Ox Ox 5 6 SHB to DAC Samples coming the SHBs are routed directly to the DAC A 256 word 32 bits FIFO connects the SHB interface to the DAC 7 BEC RSL to DAC Samples coming out of the User Manual SMT381 Page 30 of 31 Last Edited 12 06 2007 10 43 00 RSL interface are routed to the DAC This is the fastest way A 64 word 64 bits each FIFO converts the data into the right format Figure 21 Data Source Selection When using the Memory available inside the DAC any source can be selected It will not affect the DAC It is recommended to keep the selected source into reset 11 1 7 DAC Setup Registers Write Add 0x900 0x905 T
16. hese registers configure the internal functionality of the DAC on the SMT381 There are six registers 4 data registers an address register and setup register The address and setup registers must be set up before the data registers Once the data registers are written to the data address and setup information contained in all the registers will be transferred to the DAC over a serial interface an mem moe wem ne ma s 0x902 Smt381DacData LSB Smt381DacData LSB 0x903 Smt381DacData Smt381DacData 0x904 Smt381DacData Smt381DacData 0x905 Smt381DacData MSB Smt381DacData MSB Figure 22 DAC Setup Registers Write Only
17. int TP5 Daughter Card Connector test point TP6 Daughter Card Connector test point TP7 1V8 test point TP8 3V3 IN test point TP9 ECL 5V test point TP10 3V3 test point TP11 ECL 5V2 test point TP12 Analog 3V3 TP13 VCO 12V TP14 VCO 5V TP15 VCO Clock positive TP16 VCO Clock negative 7 Support Packages The SMT381 can be coupled with several base modules Example applications are provided for each base module The examples are developed with 3L Diamond DSP and FPGA design tool Source code for the software and firmware tasks is provided The tasks can be re used by users to implement their own applications The following sections describe the examples provided for each one of the base boards available with the SMT381 7 1 SMT368A The FPGA uses a Look Up Table to generate a sine wave that is then played out by the DAC The sampling frequency and other parameters of the SMT381 are controlled via software The example uses a DSP module to run the software tasks The base module is a SMT368A In the example the FPGA sends the samples for a sine wave to the DAC The DSP is used to configure and control the SMT381 and its base module The diagram shows the tasks used in the example and their interconnection The task in yellow runs on the DSP of the SMT395 the tasks in blue run on the FPGA of the base module Control channel Data channel a T Analog sig
18. ion Notes Ref RefDes A J11 External Trigger B Channel LVPECL Signal Positive on inside of connector Negative on outside of connector External Trigger A Channel LVPECL Signal Positive on inside of connector Negative on outside of connector Analog Signal Signal on inside of connector GND on outside of connector For DC Coupling only differential signal split over both connectors Analog Signal Signal on inside of connector GND on outside of connector For AC Coupling single ended and pos side of DC coupling differential Analog Signal Signal on inside of connector GND on outside of connector For DC Coupling only differential signal split over both connectors Analog Signal Signal on inside of connector GND on outside of connector For AC Coupling single ended and pos side of DC coupling differential connector Used for verification of the clock going to the DAC H J5 External RF clock input External Analog input Clock to DAC Clock on inside of connector DGND on the outside of connector I JA External ECL clock input External ECL input Clock to DAC Positive on inside of connector negative on the outside of connector Table 2 Table of Connector Locations on SMT381 Diagram Pcb Description Notes Ref RefDes J J8 FPGA 1 MSP JTAG FPGA MSP430 on SMT338 VP JTAG Chain Only Connector routed down to SMT338 VP Use for easy access without having to remove the SMT381 Fujitsu DAC DAC Requires hea
19. nals DSP tasks FPGA tasks Figure 14 example block diagram The samples generated by task sine are duplicated by task duplicate Each channel is sent to task DAC381 which sends the samples to the DAC Task registers_381 implements the registers used to control the firmware and the SMT381 daughter board Task SMT381Control is a software task which configures the registers to control the SMT381 and the application Task clock_dac_381v4 manages the clocks used to generate the samples in the FPGA and to send them to the DAC More details about each task are provided in the following section 7 1 1 SMT381Control task This software task allows controlling the SMT381 daughter module The task uses a GUI running on the host to select the sampling frequency of the DAC the source of the clock and other advanced parameters 7 1 2 Registers_381 task This task implements the registers used to control the SMT381 daughter board and the firmware The task has 1 input channel and 2 output channels Input 0 Used to read or write the registers Output 0 Carries the content of the register that is been read Output 1 Carries information used to control the firmware 7 1 2 1 Protocol The registers are accessed by writing to input channel 0 The data written to input channel 0 follow the following protocol to read and write the registers Command Address Data Figure 15 Setup Packet Structure The commands
20. t sink with air flow cooling in a system setup M A Com By default the SMT381 analog input is AC coupled Transformer through a twisted pair balum transformer differential to single ended It is possible to change this configuration to DC coupled by taking out the transformer and inserting some resistors on the board Com By default the SMT381 analog input is AC coupled Transformer through a twisted pair balum transformer differential to single ended It is possible to change this configuration to DC coupled by taking out the transformer and inserting some resistors on the board N VCOI UMC 600 1200MHz VCO System Clock for the DAC VCO Requires heat sink with air flow cooling in a system setup U31 Clock Synthesizer 50 Test Clock for DAC The range of this clock is wider 950MHz than the operating range of the DAC Table 3 Table of Component Locations on SMT381 6 2 Test points The following diagram shows all the Test points present on the board TPN TRE TF3 e ZSNvULe Ug UP Ki LC Tin l x L WNAF c CT O wpe biam kenn t ml d ER OC he ke S Te i E e TSNUHL 9 Sigg DD SN Ki ares ke Bue Z TPL P15 TP1B TP14 TP8 TP rpg 14 TP12 Figure 13 Test point locations on the SMT381 TP1 External Clock positive TP2 External Clock negative TP3 Daughter Card Connector test point TP4 Daughter Card Connector test po
21. the selected block in the reset state Writing a 0 will release the reset Figure 17 Reset Register Write Only Reset command Bit 0 firmware reset Bit 1 DAC Reset 11 1 2 Temperature Registers Read Add 0x020 0x021 0x028 0x029 There are four temperature registers Each register 1s 16 bits long When the bit value of the register is converted to a decimal number that number is the temperature in degrees Celsius Read Request Format User Manual SMT381 Last Edited 12 06 2007 10 43 00 0x021 Smt338DiodeTempReg 2 0x028 DaughterCardAirTempReg 3 0x029 DaughterCardDiodeTempReg 4 1 SMT338 VP Air Temperature on Top of PCB 2 SMT338 VP FPGA temperature on Bottom of PCB 3 SMT381 Air Temperature on Bottom of PCB 4 SMT381 ADC temperature on Top of PCB Read Response Format Ox2 SMT338 VP Air Temperature Ox2 SMT338 VP Diode Temperature Ox2 SMT381 Air Temperature Ox2 SMT381 Diode Temperature Figure 18 Temperature Registers Read Only 11 1 8 DAC Clock Source Registers Write Add Ox801 The A and B channels of the DAC can receive a clock from the on board VCO the on board clock synthesizer or from an external clock RF or ECL The following table shows the different combinations for setting up the SMT881 clock tree Register A Channel Clock Source B Channel Clock Source Value 0000 On board VCO 0x0001 On board Clock Synthesizer 0x0002 External ECL Clock 0x00
22. waveform memory is set up for a cyclic run of 8 samples per channel and a sinus wave programmed into the memory One complete cycle of the wave is loaded into the memory resulting in a waveform being generated at 1 8 of the sample frequency The DAC sample frequency is double that of the clock supplied to the DAC So for eg if a 500MHz clock is given to the DAC with the waveform memory initialized as described above the DAC sample frequency will be 1000MHz and the generated wave will be 125MHz 1000MHz divided by 8 Led a i 2 ei i i I d 1 gt i r H 3 Xf OS i d Be CH1 50 mv 3 nef el TD S O24 CH 50 mv 3 Figure 6 Waveform Memory Time View Capture 1000Msps VCO 125MHz analogue output J TD52024 Data Waveforms CH 1 J TDS2024 Data vVaveforms CH 2 Automatic Measurement Method Value 24 07M Value 25 31M Measurement requency os Pulse Width 01001 O700n eg Pulse Width 9700n 9900n se Time m p 3 eg Overshoot 12 987m Jo 0 0000 r4 r4 ES II pem p po f Peak to Peak E e Wm emm A 3m V bw emm gt Minimum 78 000m 8 000m 1 4406m 24 D5u 08 77u 6650m 5 086m 6 349m urstyvidth 9 990 0 070 eriod D Un 0600n nergy 5 831p 9 348p Energy 4 371p 5 811p ACRMS 5 067m 6 349m RMS 5 264m 6 589m lt lt lt ycle M
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