User Manual - TTC Upgrade
Contents
1. n 21 24 Board conH9uratiol e dde andas EVER ERE Eo PERSE NE EN sos EEA A sai aca PU VERE ETUU 21 2 5 Fibre cable connechons ssa Danas uniu 22 2 6 Output signal amplitude information cccccccccsssssssssscccccssssssssscccccccccssssssssccccsscesssssssscccsssssssssssscccsssseess 22 21a Froptpanel LEDS sea 23 2 8 Improvements made on the production version V3 ecce eee eee eee ee eee eese eese e ss sss eee eeeeeeessssssne 23 2 8 1 DAML ESRB OTTO CCS OR NTC ais ah ore adc terete oN calcite ois hak i Lio 23 Registers lunii 24 De HR RA 24 RF TTC COMMON SOIDWAFO ciini v EE EHE E RA nna 27 Sd J lkOdUCUOH cootra ER EET OO NEN en sm INE NI e S 27 3 L1 HW EVON e DE die cerei tes ten RR adus otio eu a eU t A a ea OL o assi 27 3 1 2 SW EVA OTe P T EE T LE ET 27 3 2e Test DEOSEOIBS aiuta el e e cane Deve pu CN era P anes eee E OH ori OR d es eU ne ii DM HM 27 Sida ANG User MDTA m 27 1 INTRODUCTION The RF2TTC RF to TTC VMEbus Interface Card is an interface card between the optical receiver modules receiving timing signals coming from the SR4 building in Echenevex and the TTC electronics within the experiments j af E Rego if E Me A 1 aa Tae ii t EE pl LARA ul a i lll I Va aN AAA rare p2. 1 to this bit forces the resynchronization of the DLL This bit always reads as a 0 ORBIN DELAY25 x Offset Used Size Access Name oro pes om e po Description These registers control the configuration of the Delay25 chips for the orbit input signals Finely adjusting the delay of the orbit inputs allows centralising the orbit pulse with the rising edge of the corresponding bunch clock to ensure a good synchronisation of the 2 signals For details about the read protocol see above Bit definition see BC_DELAY x register ORBOUT DELAY25 x Name Offset Used Size Access ORBOUT DELAY25 GCR 0x7D054 8 bits RW ORBOUT DELAY25 ORBmain 0x7D048 ORBOUT DELAY25 ORB2 0x7D044 ORBOUT DELAY25 ORBI 0x7D040 Description These registers control the configuration of the Delay25 chips for the orbit output signals This adjustment is to allow the experiments fine tuning the orbit for its use in their trigger electronics For details about the read protocol see above Bit definition see BC DELAY x register TTCrx registers Name Offset Size Access TTCrx pointer to the register 0x7E000 TTCrx pointer to the data 0x7E004 Description These are the two registers used to read and write all the internal registers of the TTCrx used to receive the BST message see TTCrx user manual Only one register requires to be accessed for the purpose of receiving the BST message the control register internal address 0x03 Its value should
3. mermo wo p k EO CO w Tmoswewdemee eme e fu DeLavas REG HO wow R owevrpuavsGER wb 8 e ORBOUT_DHLAYISORBman foros 8 JN omovrpuAvs ONE og 8 ew oroo oars oms woe 8 ew o vmmpuavxso wb CR ew vw oR wb CO ew ommo OR wom e uv pemanen wb 8 jew wcpuavs dcm wb CO jew BC DELAYS ow O CO jew wcpuavxsacG O CO w CE O COR jew nr wes que mota mc fu Ro www mom quo q mai mem quo q MANIAC mom ju J A mM A 3 RF2TTC COMMON SOFTWARE 3 1 2 3 3 INTRODUCTION Even though the RF2TTC performs the same task in each of the four LHC experiments it will be operated in H W and S W environments that are specific to the respective experiment Therefore the common S W is limited to the lowest level which consists of some diagnostic programs and a user library This S W is implemented in the rf2ttc package and can be found in CERN CVS repository at http isscvs cern ch cgi bin viewcvs all cgi rf2ttc cvsroot rf2ttc For direct access from Unix use e g setenv CVSROOT kserver isscvs cern ch local reps rf2ttc 3 1 1 H W Environment In the ATLAS and ALICE experiments the RF2TTC is controlled by a VMEbus SBC from Concurrent Technologies either a VP110 or a VP315 CMS uses a PCI VMEbus link from CAEN and LHCb a USB VMEbus link from the same manufacturer In all four experiments the crate that houses the RF2TTC should be VME64X compatible as otherwise it is not possible use geographica
4. ORB2 output of the RF Rx D ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics ECL AC coupled signal Experiments electronics 2 6 OUTPUT SIGNAL AMPLITUDE INFORMATION The typical outputs ECL amplitude that we have after 2m of cables on 50O0hm terminated ends are o BC 670mV amplitude o POSITIVE ORBIT 1 1V o NEGATIVE ORBIT 570mV These values have been set to fit the various needs of all the users but could need to be adjusted for a special need ex increase the negative orbit amplitude It is possible to increase or decrease all these amplitudes just by changing the value of one resistor per output Please contact Stephane DETRAZ or Sophie BARON 1f you want to do 1t 2 1 FRONT PANEL LEDS Description LED BCI LOCK Displays the state of the QPLL chip connected to the selected BC signal ON locked OFF not locked BC2 LOCK Displays the state of the QPLL chip connected to the selected BC signal ON locked OFF not locked BCREF LOCK Displays the state of the QPLL chip connected to the selected BC signal ON locked OFF not locked BCmain LOCK Displays the state of the QPLL chip connected to the selected BC signal ON locked OFF not locked ORBI OK Monitors the presence of
5. be OxB3 instead of 0x93 its default value The 1 added on bit 5 allows enabling the Dout bus of the TTCrx which contains the broadcast data and hence the Machine Mode Register access protocol The TTCrx chip needs to be ready ie the optical fibre needs to deliver a correct encoded 40M Hz clock in order to access the internal registers The way to access the TTCrx registers is described in the TTCrx manual p30 2C pointer register and the I2C data register The IC pointer register is five bits wide and contains the address of the internal register as defined in Table 3 page 16 When reading the I2C_data register the content of the TTCrx register being addressed by the pointer register is transferred Conversely writing a byte to the I2ZC_data register in fact writes to the TTCrx register addressed by the RC pointer register Hence each I2C access is performed in two steps 1 Write the register number in the IC pointer register 2 Read or write the IC data register According to the I2C bus specification each device on the bus is addressed by a 7 bit wide I2C device address Each TTCrx chip occupies two consecutive positions in the 7 bit I2C address space Hence it is possible to address 64 devices in the system The 7 bit I2C address is derived from the content of the ID I2C lt 5 0 gt base address register in the following way I2C access register name Resulting 7 bit I2C address I2C pointer ID I2C 5 0 2 I2C data I
6. comparator in a range from 1 25 V to 1 25 V The threshold is linked to the value of the register by the formula Threshold 1 25 value 2 5 255 TTCrx_ status Name Offset Size Access Description This register reflects the status of the on board TTCrx chip Bit definitions Description Value TTCrx not ready TTCrx ready the BST message is correctly decoded at least a 40MHz clock is sent over the optical fibre connected to the TTCrx BST Machine Mode Name Offset Size Access BST Machine Mode OxTFAC Description This register holds the LHC machine mode as decoded from the BST messages received by the TTCrx Each number here in hexadecimal corresponds to one machine mode as transmitted by the BST Value Description Po em fl a a BEAM_NO_BEAM_DEF Name Offset Size Access BEAM NO BEAM DEF 0x7FA7C Description This register controls the operation of the RF2TTC in automatic mode Each bit controls one machine mode A bit that is set to O causes the RF2TTC to use the NOBEAM SELECT registers for BC and orbit to be active when the machine is in the mode that corresponds to that bit If a bit is set to 1 the RF2TTC applies the settings in the BC and orbit BEAM SELECT registers for as long as the machine is in the respective mode Bit MODE Description Default Name Filling l BEAMMODE when automatic mode is DEI activated DN ELM NEN WORKING MODE Name Offset Si
7. three counters that generate the internal orbits 1 2 and Main One bit per counter Same definition than the ORB INT ENABLE register PERIOD COUNTER RE 0x7FA48 Reset the counters that measure the SET period of the orbit pulses 1 2 and Main At the same time the period FIFOs are cleared One bit per counter Same definition than the PERIOD COUNTER ENABLE register ORB COUNTER RESET Ox7FA44 Reset the orbit pulse counters 1 2 and Main Description A reset is triggered by writing a 1 to the address of the respective register The 3 bits of the counter reset register can reset the counters of ORBI ORB2 and or ORBmain by writing various patterns Bit number Related orbit Counter mode Orbit 1 No effect reset l Orbit 2 No effect 2 Main orbit No effect DELAY25_REG TTCrx_REG Name Offset Size Access DELAY25 REG 0x7D200 8 bits R TTCrx REG 0x7E200 Description These registers are required to read values from the TTC and Delay25 registers described below Due to delays introduced by the I2C bus it is not possible to read these registers directly Instead a sequence of three steps is required 1 Read a dummy data word from the address of the TTC or Delay25 register that 1s to be read out 2 Wait for at least 2 ms 3 Read the data value from the DELAY25 REG or TTCrx REG FIFO contents of the read access to delay25 and TTCrx chips If multiple registers are to be read one can group the dummy reads ste
8. C1 input BCx QPLL MODE Name Offset Size Access rot RN Description These registers define the QPLL locking mode Value Description NE Re lock only after a reset Re lock automatically if the lock gets lost BCx DAC Name Offset Size Access BCI DAC Ox7FBEC 8 bits R W BC2 DAC Ox7FBBC BCref DAC 0x7FB9C Description These registers define the threshold of the input comparator for the respective BC input channel in a range from 1 25V to 1 25V The threshold is linked to the value of the register by the formula Threshold 1 25 value 2 5 255 BCx_QPLL_STATUS Name Offset Size Access Description These registers contain the status of the QPLLs of the BC channels Bit 1 indicates that the QPLL detected an error and bit 0 indicates the locking status Bit 1 Description QPLL has error Bit 0 Description NEN QPLL not locked QPLL locked ORBx MAN SELECT ORBx BEAM SELECT amp ORBx NOBEAM SELECT Name Offset Size ORB2 BEAM SELECT ORB2 NOBEAM SELECT ORBmain MAN SELECT 2 bits ORBmain BEAM SELECT ORBmain NOBEAM SELECT Description These registers select the sources of the orbit outputs Only one set of registers is active at any time The ORBx MAN SELECT registers are active when the RF2TTC is operating in manual mode If the card is in automatic mode and the beam is on the orbit outputs are controlled by the ORBx BEAM SELECT registers The ORBx NOBEAM SELECT registers control th
9. Class VME Function RF2TTC 2 PH ESS 16 05 2007 Modified 16 05 2007 USER MANUAL RF2TTC V3 User Manual V2 1 RF to TTC VMEbus Interface Card and S W Summary This document describes the functionality of the RF2TTC card as well as the generic S W that has been developed for it Document Revision 2 o 12 03 07 the CR CSR space has been transposed to the User Space o 16 05 07 geographical address modified information on orbit period counter results initialisation procedure section 2 7 1 last firmware version output signals amplitude adjustments section 2 6 etc Prepared by Checked by Approved by Sophie Baron PH ESS Markus Joos PH ESS for information Tel Fax E Mail you can contact Sophie Baron 41 22 7677339 41 22 7678925 sophie baron cern ch 41 22 7672364 41 22 7678925 markus joos cern ch Stephane Detraz 41 22 7679702 41 22 7678925 Stephane detraz cern ch Table of Contents I 2 3 INFO CHORE A 3 RF2FIC HardW re ias OSSO ada aa 5 Zils Standards and power SUP PLIES asas escala Pi ite on nu toO iiti 5 9 55 VINEE TCU HET REID I OE I UT 5 Zub REEE NES UM ra ooo oan en tuat dedissent hti ated ac ae aee iM ca 5 2 2 24 Board Identification read only registers rer a cas seu YER ERR EE EUER EX RR ARE S casseedeeausverssassoedesanveeese y 225 Jourd conftisuratton TePISIGES Soros veins esie abies ie itp veg uit ahi ab moran a ee 7 2 3 Calibration procedures er
10. D_I2C lt 5 0 gt 2 1 Table 12 I2C address calculation The registers accessible via I2C are the following I2C reg address Register name Default decimal content After reset Config 1 00011010 Config 2 10000100 0 8 o 9 18 MasterModeB lt 1 0 gt I2C ID 00000000 ENENP dd Bits lt 23 16 gt 00000000 2 3 2 4 Example of registers read and write via VME access Read control register I2C address 3 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x3 register I2C address 2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 3 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x00000003 Write Fine Delay Register I2C address I l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 register I2C address 2 VME WRITE AM 0x09 RegOFFSET 0xE004 offset of the data register 0x0000YOURDATA Read fine delay register I2C address 1 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 3 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x000XYOURDATA with X 0 if the fIFO is not empty X 1 if you are reading the last word stored in a FIFO Successively read fine delay registers 1 and 2 I2C address 1 and 2 4 VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 5 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 6 VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x2 7 VME READ AM 0x09 RegOFFS
11. ET 0xE000 the Data read has no meaning 8 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0000Y OURDATA 9 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0001 YOURDATA CALIBRATION PROCEDURES For a proper functioning of the RF2TTC in its environment a number of coarse and fine grained pulse delay and stretch registers have to be tuned by the user A description of this procedure will follow once if that been analyzed to what extent the RF2TTC can perform FPGA based auto calibrations BOARD CONFIGURATION Element Description LSB rotary switch TBD MSB rotary switch TBD 2 9 FIBRE CABLE CONNECTIONS Connector name BST BC INPUTS BCI BC INPUTS BC2 BC INPUTS BC REF ORB INPUTS ORBI ORB INPUTS ORB2 BC OUTPUTS BCI BC OUTPUTS BC2 BC OUTPUTS BC REF BC OUTPUTS BCmain ORB OUTPUTS ORBI ORB OUTPUTS ORB2 ORB OUTPUTS ORBmain To be connected to TTC encoded signal One of the BST optical fibres two are normally available one per ring The optical power level should be between 5dBm and 25dBm ECL AC coupled signal Should be connected to the BC1 output of the RF Rx D ECL AC coupled signal Should be connected to the BC2 output of the RF Rx D ECL AC coupled signal Should be connected to the BCref output ofthe RF Rx D ECL AC coupled signal Should be connected to the ORBI output of the RF Rx D ECL AC coupled signal Should be connected to the
12. controlled by VME accesses A solution was provided to ensure the board initialisation after power up sys reset or reconfiguration without using a crate processor This initialisation ensures that e All the delay25 chips are enabled i e transmit the signals present at their inputs 0x40 is written in all of their delay registers e Allthe DACs are configured correctly to allow latching the input orbits if any set to OxAA e The TTCrx chips is configured to transmit the BST message to the FPGA control register is set to OxFF e All the signals are set to INTERNAL by default 2 9 REGISTERS SUMMARY Name Offset Size bits Access C eme qu BC2 MAN SELECT 0x7FBCC memso uma que BC2 NOBEAM SELECT 0x7FBC4 peme wma CO CO orm CO CU COST moss CO CU Name Offset Size bits Access ORBI PERIOD FIFO STATUS ORBI PERIOD FIFO RD ORB2 MAN SELECT R ORB2 BEAM SELECT R ORB2 NOBEAM SELECT R ORB2 COARSE DELAY R ORB2 INT PERIOD SET ORB2 INT PERIOD COUNTER ot COUNTER ORB2 PERIOD FIFO STATUS ORB2 PERIOD FIFO RD ORB2 DAC 0x7FAFC 8 ORBmain NOBEAM SELECT ORBmain INT PERIOD SET W ORBmain INT PERIOD COUNTER ni COUNTER ORBmain PERIOD RD ORBmain PERIOD FIFO STATUS ORBmain PERIOD FIFO RD BST Machine Mode BEAM NO BEAM DEF W _ Offset Size bits Access Name WORKING MODE omas poo que o om NrENAmE erc um PERIOD COUNTERENAME eau um owmwrmsr O qme pu PeRioD_CouNTER RESET wma p po om course ota pr
13. crate reconfiguration Table 1 VMEbus resources of the RF2TTC All the registers of the board are accessible using 0x09 AM A32 D32 The board address is the geographical address of the module if the manual rotary switches are set to 0x00 The address used to access the user space is hence defined as follows o A31 A28 A27 A24 A23 A20 SW 7 0 0x00 pO GEOG ADD SW 7 0 20x00 00 0 SW2 3 0 MSB SWI 7 4 LSB 2 2 1 Reset registers Register Offset Purpose Access BSET Board Set Register assignment Description This register is declared in the VME64x as a User defined Bset register It 1s used here to define partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Value Write Read place Delay25 chips in reset Delay25 chips in reset mode mode place QPLL chips in reset mode QPLL chips in reset mode 2 place TTCrx chips in reset TTCrx chips in reset mode mode place board in reset mode Board in reset mode BCLEAR User defined BCLEAR Register assignment Description This register is declared in the VME64x as a User defined Bclear register It is used here to remove partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Value Write Read remove Delay25 chips from Delay25 chips in reset mode reset mode 1 remove QPLL chips from reset QPLL chips in reset mode mode 2 remove TTCrx chips from reset TTCrx chips
14. e orbit outputs when the RF2TTC is in automatic mode and the beam absent The MAN SELECT and NO BEAM registers are set to INTERNAL by default The BEAM register to EXTERNAL Bit definition for ORBI and ORB2 registers Value Description L9 1 Output follows the respective orbit input EXTERNAL Output from internal BC synchronized orbit generator Bit definition for ORBmain registers Value Description Output follows the orbit 1 input Output from internal BCmain synchronized orbit generator Output follows the orbit 2 input ORBx_POLARITY Name Offset Size Access ORBI POLARITY 0x7FB60 l bit R W ORB2 POLARITY 0x7FB20 ORBmain POLARITY Ox7FAEO Description If set this bit inverts the polarity of the orbit output with respect to the orbit input 1 e the orbit output is negative active ORBx_COARSE_DELAY Name Offset Size Access ORBI COARSE DELAY 0x7FB5C 12 bits R W ORB2 COARSE DELAY 0x7FBIC ORBmain COARSE DELAY 0x7FADC Description This register allows the orbit output signal to be shifted by multiples of 25 ns with respect to the input If set to 0 the output 1s shifted by the minimum intrinsic delay induced by the board itself Values above OxDEB 3563 are illegal because they would result in a shift longer than the LHC orbit period 88 93 us ORBx LENGTH Name Offset Size Access ORBI LENGTH 0x7FB58 ORB2 LENGTH Ox7FBIS ORBmain LENGTH Ox7FADS Description This register allows the o
15. in reset mode mode remove Board from reset mode Board in reset mode 2 2 2 Board Identification read only registers Register Address Value Access MANUFACTURER ID 0x00000 0x00080030 CERN BOARD ID 0x00004 0x0000016B REVISION ID 0x00008 Hardware version R nal Prototype 0x2 Production 0x3 ul PROGRAM ID 0x0000C Firmware date number R m Last 08052007 08 May 2007 m 2 2 3 Board configuration registers BCx MAN SELECT BCx BEAM SELECT amp BCx NOBEAM SELECT Name Offset Size Access PMNS REIN BC NOBEAM SELECT BC2 NOBEAM SELECT Description These registers select the sources of the BC outputs Only one set of registers is active at any time The BCx MAN SELECT registers are active when the RF2TTC is operating in manual mode If the card is in automatic mode and the beam is on the BC outputs are controlled by the BCx BEAM SELECT registers The BCx NOBEAM SELECT registers control the BC outputs when the RF2TTC is in automatic mode and the beam absent The MAN SELECT and the NO BEAM registers are set to INTERNAL by default and the BEAM register to EXTERNAL Bit definition for BC1 BC2 and BCref registers Value Description 0 Output taken from internal 40 078MHz clock INTERNAL Output follows the respective BC input EXTERNAL Bit definition for BCmain registers Value Description 00 Output taken from internal 40 078MHz clock NN Output follows BCref input Output follows BC2 input Output follows B
16. l addressing 3 1 2 S W Environment On the low end ATLAS and ALICE will use the vme rcc driver developed by ATLAS to communicate with the RF2TTC CMS and LHCb will use S W packages provided by CAEN for the respective interface The common S W will be programmed in a way that it is compatible with any of these bus access packages At the top end each experiment has to develop appropriate secondary libraries and applications to interface the RF2TTC to their respective control systems The development of the interface to the DIP server is also up to the experiments TEST PROGRAMS Currently there exists one program that comes in three flavours rf2ttcscope atlice for ATLAS and ALICE rf2ttsscope cms and rf2ttcscope lhcb This interactive application can be used to read decode and write any register of the RF2TTC in a hopefully intuitive way If a users feels that some functionality is lacking he is welcome to contact the developer M Joos It is e g possible to extend rf2ttcscope by additional command line parameters such that certain tests can be executed from scripts A tcltk graphical user interface rf2ttc tcl is also available for test purpose It has been written for SBCs from Concurrent Technologies VP110 and VP315 THE USER LIBRARY This library consists of a common source file that implements the access to the registers of the RF2TTC in a generic way and a number of files to implement glue layers to the VMEbus access libra
17. m TT n o l f cA Im E NNI TEET i a TITLET HHT re Do P a Dm W oats The timing signals treated by the RF2TTC are the three 40 078MHz Bunch Clocks BC1 BC2 and BCref and the two orbit signals Orbl and Orb2 necessary to drive the 2 beam lines of the LHC The RF2TTC module converts them into ECL signals drivers B02_CLOCK BC2 lock Lvos2EcL BGret CLOCK PECL2NIM CONVERSION TRANSISTORS RF2TTC BOARD BLOCK DIAGRAM V1 7 10 11 2006 Coarse Delay Stretch Delay Coarse Delay M Steton Delay INTERNAL a M Coarse VME BUS I pro is Delay Sie teh Deisy INTERNAL CLOCK RF2TTC module diagram The three Bunch Clocks represented on the top part of the above diagram are all treated in the following way A comparator with an adjustable threshold fi
18. ow when the timing signals are stable and can be used In deed neither the Bunch Clocks nor the Orbit signals are fully guaranteed out of the physics modes flat top of the LHC energy curve It is thus advised to use internal signals when the machine mode indicates that there 1s no beam All the adjustments are done using VME registers Many status registers are available as well as special configurations for stand alone or debugging work This document contains a description of all accessible registers of the RF2TTC card as well as description of the generic S W that has been developed for this card At the end of this document some basic examples of configuration procedures are proposed 2 RF2TTC HARDWARE 2 1 STANDARDS AND POWER SUPPLIES The RF2TTC board is a VME64x 6U board It requires the following power supplies e 3V3 2 5A e 5V 0 3A e 12V 1 4A Total power 26W 2 2 VMEBUS INTERFACE The VMEbus interface of the RF2TTC cards is implemented in its FPGA and based on the VME interface developed by Peter Lichard for the TRT TTC board ATLAS It provides 2 types of VMEbus addressable resources as described in Table 1 Resource VMEbus access mode Description Control and status A32 D32 with A19 0 and AM code These are the registers that control the registers behaviour of a RF2TTC card and provide information about its current status A32 D32 with A19 1 and AM code The access to the EPROM is reserved for in 0x09
19. p 1 and data reads step 3 such that they are only separated by one 2 ms delay This pipelining however works for up to 256 read requests BC DELAY25 x Name Offset Used Size Access BC DELAY25 GCR 0x7D014 8 bits RW BC DELAY25 BCmain 0x 7D00c BC DELAY25 BCref 0x7D008 BC DELAY25 BC2 0x7D004 BC DELAY25 BC 0x7D000 Description These registers control the configuration of the Delay25 chips for the BC signals These chips ensure the BC signal to be shifted by steps of 0 5ns with a jitter lower than 19ps rms For details about the read protocol see above Bit definition from Delay25 manual The bit allocation of each channel control register is as given in the following table Bits Del lt 5 0 gt control the delay for each channel and the Enable bit enables the channel output Upon a reset bit Enable and bits Del lt 5 0 gt are cleared Control registers CRO to CR4 bit allocation B7 B6 B5 B4 B3 B2 B1 BO The general control register GCR controls the operation of the Delay Locked Loop DLL and allows to reset the DLL or the ASIC via the I2C interface The bit allocation for this register is given in Table 4 General Control Register GCR bit allocation The ASIC can operate with for different clock frequencies 32 40 64 and 80 MHz For this application the M lt 0 gt and M lt 1 gt bits must be set to 0 40MHz IDLL bit IDLL is used to force the resynchronization of the DLL without resetting the chip Writing a
20. rbit pulse to be stretched in steps of 25 ns If set to 0 the width of the orbit pulse is stretched by 75 ns The largest pulse width with all 8 bits set to 1 1s 6 4 us The original width of the internally generated orbit pulse is 75ns ORBx INT PERIOD SET Name Offset Size Access ORBI INT PERIOD SET 0x7FB54 12 bits R W ORB2 INT PERIOD SET 0x7FBI4 ORBmain INT PERIOD SET 0x7FAD4 Description This register allows setting the period of the internally generated orbit signal in units of 25 ns The default value is OXDEC which corresponds to 3564 bunch clocks between two orbits ORBx_INT_PERIOD_COUNTER Name Offset Size Access ORBI INT PERIOD COUNTER 0x7FB50 ORB2 INT PERIOD COUNTER Ox7FBIO ORBmain INT PERIOD COUNTER Ox7FADO Description This register is provided for debugging purposes It holds the value of the BC counter that is used to generate the internal orbit signal This can be reset by the ORB INT RESET register ORBx COUNTER Name Offset Size Access ORBI COUNTER 0x7FB4C 32 bits R ORB2 COUNTER 0x7FBOC ORBmain COUNTER 0x7FACC Description This register holds the number of orbit pulses that have been received since the counter was reset enabled At an orbit period of 89 us this counter will overflow after approximately 106 hours and will be reset ORBx_PERIOD_RD Name Offset Size Access a E ORB2 PERIOD RD Ox7FBOS ORBmain PERIOD RD Ox7FACS Description This register holds the time in uni
21. ries from ATLAS and CAEN respectively
22. rst converts the input signal into a PECL signal before being multiplexed with an internal 40 078MHz clock in case of absence of the Bunch Clock on the front panel The signal is then shifted by an adjustable delay with 0 5ns precision before being cleaned by a QPLL and transmitted on the front panel via an ECL 50 Ohm coaxial cable driver with an AC coupled output A global multiplexer allows selection between the three Bunch Clocks and the internal clock to generate a fourth Bunch Clock output called Main BC which can also be delayed The two orbit signals middle and bottom right parts of the diagram are first converted using the same adjustable comparator stage as for the Bunch Clocks They are then lengthened to more than 25ns finely delayed with 0 5ns steps before going into an FPGA grey block of the diagram where they are synchronized to their corresponding clock multiplexed with an internal orbit and coarse delayed Their length and polarity can be adjusted and they are then again finely delayed before being transmitted by the ECL drivers A global multiplexer also allows selection between the two orbits and an internal one synchronized to the Main Bunch Clock This orbit signal is called Main Orbit and can as well be finely delayed before being transmitted The BST Beam Synchronous Timing optical signal on the bottom left part of the diagram is received decoded and analyzed to recover the machine mode This mode is useful to kn
23. the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold ORB2 OK Monitors the presence of the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold BEAM Monitors if the current machine mode corresponds to a BEAM mode or a NO BEAM mode ON BEAM OFF NO BEAM BST ready Monitors the state of the TTCrx in charge of receiving and transmitting the BST message to the FPGA ON TTCrx ready received frame is consistent and can be decoded OFF no consistent BST message BERR Flashes when the RF2TTC generates a BERR Not implemented yet Flashes if the RF2TTC has replied to a VMEbus cycle 2 8 IMPROVEMENTS MADE ON THE PRODUCTION VERSION V3 2 8 1 Initialisation procedure The state of the Delay25 chips after a power up was not satisfactory as the outputs were all disabled The same for the TTCrx which does not allow by default the transmission of the broadcast words Finally the DAC in charge of the threshold adjustments are set to 1 25V by default after power up Hence the Delay25 TTCrx and DAC chips need to be initialised first and it requires using some internal protocols I2C or other
24. ts of 25 ns BC ticks that has elapsed between the last two orbit output pulses The number of steps given is always 1 more than the real number of steps between 2 orbits ORBx_PERIOD_FIFO_STATUS Name Offset Size Access ORBI PERIOD FIFO STATUS 0x7FB44 ORB2 PERIOD FIFO STATUS 0x7FB04 ORBmain PERIOD FIFO STATUS 0x7FAC4 Description This register holds the status of the FIFO that contains the most recent 256 orbit periods of the respective orbit output channel Bit definitions Value Description Fifo not empty Fifo empty Fifo not full Fifo full ORBx_PERIOD_FIFO_RD Name Offset Size Access ORBI PERIOD FIFO RD 0x7FB40 16 bits R ORB2 PERIOD FIFO RD 0x7FB00 ORBmain PERIOD FIFO RD 0x7FACO Description These registers provide access to three 256 word deep FIFOs which contam the most recent 256 orbit periods of the respective orbit output channel in bits 0 13 Reading the last period stored in the FIFO or from an empty FIFO results in reading a 1 in bit 14 FIFO empty For the moment it is not possible to read these FIFOs with a constant address block transfer When the FIFO has been filled the first read value is not significant because the counter does not begin with an orbit pulse but with an enable or a reset command ORBx_DAC Name Offset Size Access ORBI DAC Ox7FB3C 8 bits R W ORB2 DAC Ox7FAFC Description These registers allow setting the threshold voltage of the orbit input
25. ze Access Description The bits in this register control the operational modes of the outputs of the RF2TTC Each bit corresponds to one signal Bit number Related output Bit Selected mode value os wmm Automatic TE Ta s O ama ni ORB O ama ee ee ORB_INT_ENABLE Name Offset Size Access Description This register controls the status of the BC counters that generate the internal orbit pulses Bit number Related orbit Bit value Counter mode Orbit 1 counts BC ticks D Disabled Orbit 2 counts BC2 ticks 3 Disabled Main orbit counts BCmain E Disabled ticks ORB_COUNTER_ENABLE Name Offset Size Access ORB COUNTER ENABLE Ox7FA68 Description This register controls the status of the orbit pulse counters Once a channel has been enabled the registers ORBx COUNTER count the orbit pulses of that channel Bit number Related orbit Bit value Counter mode ro eee LL Eta Po ET Emm PERIOD COUNTER ENABLE Name Offset Size Access PERIOD COUNTER ENABLE Ox7FA64 Description This register controls the status of the orbit period counters Once a channel has been enabled the FIFOs and ORBx PERIOD FIFO RD start measuring and storing the duration of orbit signals Bit number Related orbit Counter mode Orbit 1 Disabled Enabled 1 Orbit 2 Disabled 2 Main orbit Disabled Counter RESET registers Offset Access Function ORB INT RESET 0x7FA4C W Reset the
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