FPGA Based Design & Implementation of Embedded System for Tilt
Contents
1. C altera 70 quartus DEe2 EPCS16 1C6FB812 00000000 LI LI Cl t Page_O G amp Hierarchy D Files aP Dosign Units CI CI CI CI Status x dife Auto Detect Cake Add File CH Add Device Ge PRASAD G Tak ABSTRACTMOW Micr Figure 11 Active Serial programming mode 6 Design Of Hardware 6 1 Analogue to Digital Converter The system uses simple 0809 It converts analogue o p of level sensor to 8 bit digital value This digital value is fed to the DE2 board through expansion header slot The decimal equivalent digital output value D for a given analogue input voltage Vin can be calculated from the relationship D Vin Vref 256 Ik mnp Figure 12 ADC 0808 0809 6 2 Expansion Header The DE2 Board provides two 40 pin expansion headers GPIO 0 GPIO 1 Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins are brought out to two 40 pin expansion connectors 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages Vol 2 No 3 July 2011 OIJoAT 344 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 JP1 GPIO 0 2 D protect2. Figure 15 IC 555 as Astable Multivibrator ote ck input CPD 07 END GROWS ADA coat PUT KAL yin al GND GAOS HD CCH CP GND Pea i cpl Gadu 40 PIN EXPANSION GHD kiza aol Wee 34 TAD Wee 33 GAD Woo 33 Guo Woo 33 GHD Woo 33 GHD Wie 33 Figure 16 Interfacing diagram of system Vol 2 No 3 July 2011 OIJoAT LCD MODULE LoD _ DAT AO LoD DAT AL LOD _DATALZ LoD DAT ALS LoD_DAT AL LCD DATAISI LOD_DAT AG LOD CATAL 346 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 7 Simulation Results using MODELSIM For design of controller we have used modelsim for simulation Test value 1 VALUE 00000111 S_ UNITS 30 S_TENS 30 S THOUSANDS 37 gl wave Jefadi lL Fide Edt Yaa Ad Forest Took Window OS TTEA eA feo et MD a E FE bles me oy are Be oe alaaa af TT eT Test value ai TIT iHd Ha MAI i maaa Test value 2 VALUE 00100101 S UNITS 30 S_TENS 33 S THOUSANDS 37 Fie Ed Wiew Add Feet Teele Winda Us Se RAD ae SSR ee ST mme a det decked i liek iif p OPS ADAE ie aaa LNT gigi m Dest Wahie 2 1 Hinton hepr wahe chard EA gt UNITS 30 i T S_TENS 33 S THOUSAND 337 H aa La La Ka Ka harara EETA KA ba i I 1 oe la ot cial Paro ELE E ana S000 000 S000 50 Ore E RC JI 1599459051 ns te G00046 5 ns Hoger 30 ms
3. software you can specify options to customize your work environment For example you can Vol 2 No 3 July 2011 OIJoAT 336 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 choose a preferred look and feel for the Quartus II user interface You can customize the display of messages You can create and customize toolbars and show and hide toolbars and the status bar You can also specify that the current project and files should reopen at startup 3 Proposed System Figure shows the schematic block diagram of tilt measurement system In order to use the DE2 board the user has to be familiar with the Quartus II software which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry To design the controller VHDL is use because VHDL is a standard technology vendor independent language and is therefore portable and reusable DE Boar Figure 2 The Proposed System 3 1 Sensor The Tilt is a static measurement where gravity is the acceleration being measured Therefore to achieve the highest degree resolution of a tilt measurement a low g high sensitivity accelerometer is required Sensor arrangement is used to sense the surface deformation or change in the position of object on which the tilt meter is mounted with respect to its reference position We are using gravity based resistive sensor When tilt occurs resistance of the potentiometer change
4. PIN J LCD Data o LCD _DATA 1 PIN Ja LCD Data 1 LCD DATAP PIN HI LCD Data 2 LCD DATA PIN _H2 LCD Data 3 LCD DATA PIN J LCD Data 4 LCD DATAI5 PIN JS LCD Data 5 icD_ RV PIN KA LCD ReadVvrite Select 0 Write 1 Read PIN KA LCD Command Data Select 0 Command 1 Data PIN LA LCD Power ON OFF PIN KA LCD Back Light ON OFF 5 3 Loading VHDL Program in FPGA The Programmer allows us to program or configure all Altera devices supported by the Quartus II software with files generated by the Compiler The Assembler module of the Quartus II Compiler generates programming files that the Programmer can use to program or configure a device with Altera programming hardware The Programmer has four programming modes e In Passive Serial programming mode e In JTAG programming mode e In In Socket programming mode e In Active Serial programming mode Vol 2 No 3 July 2011 OIJoAT 343 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 To demonstrate the designed we have used ASP mode X Quartus li Chain1 cdf La File Edit View Project Assignments Processing Tools Window Help D m ex W als Hardware Setup USB Blaster USB 0 Mode fa TAG Progress ox j Enable real time ISP to allow background programming for MAX Il devices i Ly Compilation Hierarchy pel Start File Device Checksum Usercoa de se ee Verify es Examine
5. are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design It depicts the layout of the board and indicates the location of the connectors and key components The DE2 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects uss XSGA Ethernet ji Staster USE USB Mic Une Lime Video Video 1Ov 100M RS 232 Dut hag 2 r ls rut In Port 1 SV DC Power Supply x ty Connector t t t t f t t amp W F 2 Mrz Oscillator a j A BA 5 24 bit Apdo CODEC p PS Por TY Decoder NTSC PAL XSGA 10 b8 DAC Power yen Expansion Header 2 P72 a with Vollage Protection USB Hos Slave 1 Controler Expansion Meader 11 JPt with Vollage Protector Altera USG Blaster Ethernet 10 100M Controller Controler choset Alhora EPCS14 Configurstoe Dewce a Altera 90nm Cyclone li RUNPROG Swatch FPGA with 35K LEs for JTAGIAS Modes 16 Connector LCD 1812 Module SD Card Conne IrDA Transceiver A Green LEDs SEG Display Module 18 Red LEDs SMA Ext Cik 18 Toggle Seitches 4 Push button Seviches SOMnz Oscilistor SMbyte SORAM 51 Kbyie SRAM 6 4Mbyte Flash Memory upgradable to 4Mbyte Figure 1 Block Diagram of DE2 Board 2 2 Altera Quartus I The Quartus II development software provides a complete design environment for system on a programmable chip SOPC design When working with the Quartus II
6. AB Dlr v mr me hh gt S wD ee Sa ee b DE2_CLOCK vhd d Compilation Report Flow Th DE2_CLOCK vwf d Simulation Report Simula ga Pin Planner eB Assignment Editor ll EP2C35F672C6 J DE2 CLOCK RA WR EEG ri A PEA i YA z s z Fite a s A a A E3 a Warning Found logic contention at time 0 ps on bus node DE2 CLOCK DATA_BUS 5 result E 2 Info Option to preserve fewer signal transitions to reduce memory requirements is enabled 4 Info Simulation partitioned into 1 sub simulations 4 Info Simulation coverage is 0 74 3 4 Info Number of transitions in simulation is 198 fl 42 Info Quartus II Simulator was successful 0 errors 8 warnings s TT uw b j System Processing Extra Info Info Warning Critical Warning Error Suppressed s Message 0 of 38 Tl P Location For Hel ress F1 ana Idle Figure 10 Pin Assignments in Quartus II Vol 2 No 3 July 2011 OIJoAT 342 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 5 2 Utilized pins of FPGA Cyclone II EP2C35 Table 1 Pin utilized for Expansion Header GPIO oOo PIN D25 GPIO Connection Of0 GPIO_O 1 PIN J22 GPIO Connection O 1 Table2 Pin utilized for the clock input CLOCK 27 PIN_D13 27 MHz clock input CLOCK 50 PIN M2 50 MHz clock input EXT CLOCK PIN P26 External SMA clock input Table 3 Pin utilized for LCD LCD DATA O
7. Deta 2 Vol 2 No 3 July 2011 OIJoAT 347 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 Test value 3 VALUE 01110001 S_UNITS 31 S_TENS 31 S_THOUSANDS 33 wine delaull gt EE E3 ie Edit View Add Format Tock Winde Oe S 6 a SAR tes og RAT E i gt EELE uf DAREM Test Value 3 ADONAI ae ae gt UNITS 31 gt TENS 31 gt THOUSANDS 33 8 Conclusions This paper demonstrate the Embedded controller for tilt measurement where an external sensor is used for tilt measurement The sensor has 5 outputs and gives the tilt in digital angle format Being a 5 bit output device it can measure tilt to an accuracy of 360 245 11 25 degrees each bit indicates a 11 25 degrees approximate tilt from the reference tilt To further elucidate the point let us take an example the output 00110 indicates a tilt of 6 11 25 67 25 degree tilt from the reference tilt This measured tilt will be given to the Altera DE2 Board and the tilt would be displayed on the LCD The LCD data pins as present on the board are used the expansion slot 1 is used as the slot to take input from the tilt meter sensor The VHDL code that will be burnt inside the Cyclone chip would convert this value into a proper tilt value and then produce the output accordingly The output produced out of this conversion would be shown on the LCD screen The LCD operates on a 27 states 11 state are u
8. International Journal of Advancements in Technology http ijict org ISSN 0976 4860 FPGA Based Design amp Implementation of Embedded System for Tilt Measurement Mr A R M Khan S M Gulhane S L Badjate Department of Electronics Department of Electronics Department of Electronics amp Telecommunication Jawaharlal amp Telecommunication Jawaharlal amp Telecommunication Darda Institute of Engg amp Darda Institute of Engg amp S B Jain Institute of Technology Yavatmal Technology Yavatmal Technology Management and Research Nagpur Corresponding author mr atharravishkhan rediffmail com Abstract Measurement of tilt is having a very much importance in the applications such as railway track monitoring mining aviation tunneling bridge and dam monitoring system etc The tilt is measured in terms of degrees and is made with respect to the original tilt of the surface on which the meter is kept This paper proposes an embedded tilt measurement system which uses a level sensor A D converter Altera DE2 board and a controller designed in FPGA using VHDL with the help of QUARTUS II software The proposed model of the tilt measurement system would measure the tilt based on an initial calibration and the Reference tilt set at the beginning Here we have an output tilt which is available in degrees and it changes as per the input changes The controller designed using VHDL would sense the changes in the inputs which is the change in the t
9. amp Cyclone ll EP2C35F672C6 S B Legal Notice Simulation mode Timing tm pbg DE2 CLOCK 136 136 BEB Flow Summary SREB Flow Settings z aoa Simulator Bee SREB Summary BEB Settings AB Simulation Waveforms el SD Simulation Coverage E amp E IN Usage ye Messages Interval Start End 1 71 ns 2 57 ns 3 42 ns 428ns 5 a 1 gt ka r x ay Warning Found logic contention at time 0 ps on bus node DE2 CLOCK DATA BUS 5 result E A Info T to preserve fewer AmE transitions to reduce memory requirements is enabled io a Figure 9 Simulation in Quartus II 5 Synthesis of VHDL code 5 1 Pin Assignments Assignments are used to control a variety of different functions of the Quartus II software and are an important part of an efficient and effective design When used in conjunction with a solid design foundation assignments can help us successfully compile our design Assignments are logic functions we assign to a physical resource on the device or compilation resources we assign to logic functions Making assignments allows us to specify various options and settings for the logic in the design including location I O standard timing logic option parameter simulation and pin assignments F Quartus I D project DE2_CLOC m7 File Edit View Project Assignments Processing Tools Window Help gt lt ae ae ee c EEE vll K
10. g flow can be well explained with flowcharts as given above in figure 5 4 1 Internal Clock Utilization The DE2 board includes two oscillators that produce 27 MHz and 50 MHz clock signals The board also includes an SMA connector which can be used to connect an external clock source to the board The schematic of the clock circuitry is shown in figure 6 V_VCC33 2 EXT CLOCK Figure 6 Schematic diagram of the clock circuit 4 2 Generation of 400Hz clock In the design of the controller 50 Mz of crystal is utilize to generate the 400 Hz clock for the LCD display and the calculation are as follows SOMHz clock 400Hz clock 1 25 000 Hence 1 25 000 OF424 Hex cycles S0MHz clock 1 cycle of 400Hz Of clock LO T DCO T II 1 25 000 cycles of SOMHe clock a 1I cycle of 400He chock Figure 7 Generation of 400 MHz Clock Vol 2 No 3 July 2011 OIJoAT 340 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 4 3 Creation of Design File The Compiler is a set of modules that transform design files in a project into output files for device programming and simulation We can use the Compiler to run a full compilation or we can run the individual modules separately A full compilation processes a design with Analysis amp Synthesis the Fitter and the Assembler and the Classic or Time Quest Timing Analyzer and allows you to optionally process the design with the Design Assistan
11. h as display RAM character generator and liquid crystal driver required for driving a dot matrix liquid crystal display are internally provided on one chip a minimal system can be interfaced with this controller driver The HD44780U character generator ROM is extended to generate 208 5 x 8 dot character fonts and 32 5 x 10 dot character fonts for a total of 240 different character fonts The low power supply 2 7V to 5 5V of the HD44780U is suitable for any portable battery driven product requiring low power dissipation START DATE BUS TRISTATED DATA BUS DATA BUS VALUE IF EVENT OCCUR AT VE EDGE OF 50 MHZ CONVERT 50 MHZ CLOCK IN TO 4Q0HZ CLOCK FOR PROPER LCD OPERATION USING 20 BIT COUNTERT READ INPUT TILT SETUP A STATE MACHINE FORLCD OPERATION AND TO CALCULATE INPUT TILT INITIALISE THE STATE MACHINE SET COMMAND MODE OF LCD FOR PROPER RESET OF LCD USE 3 RESET STATES ON RESET AND SET THE 400 HZ CLOCK TO START PROCEDURE CONVERT INPUT SEIT VALUES TO ASCII FOR DISPLAY ON LCD FUNCTION BYTE TO INTEGER CONVERT THE INPUT INTO ASCII VALUE WRITE FROM CHARI TO CHAR 16 AGAIN CONTINUE READING NEAT TILT VALUE Figure 5 Flowchart demonstrating design of controller Vol 2 No 3 July 2011 OIJoAT 339 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 4 Designing of Controller using VHDL Controller is designed in FPGA using VHDL The programmin
12. ilt measured as 8 bit values measured by level sensor and fed to DE2 board via A D converter Accordingly the tilt will be displayed using LCD module on Altera DE2 Board The proposed system can be calibrated to get the specified precision in calculating the tilt The system is able to calibrate the tilt up to required precision The model will be scalable so that the input and output ranges could be easily changed as per the situation demands Keywords A D converter LCD module VHDL Cyclone II EP2C35F72C6 FPGA Altera Quartus II ModelSim 1 Introduction System is used to capture and calibrate the small changes in the level of the surface on which it is mounted with respect to its initial position The tilt or deflection of the system at its initial position is called as reference tilt and is always considered as 0 degree The designed system is a multipurpose embedded system for the measurement of tilt based on CYCLONE II FPGA It has very much application in the field of aviation robotics dam monitoring system bridge monitoring system etc This system mainly consists following parts level sensor Simple A D converter Altera DE 2 Board Here a gravity based resistive sensor using a multi turn potentiometer pot is use to serve the purpose of capturing the inclination of surface The output of a sensor is a voltage i e an analogue value which is dependent on the level or position of the surface on which it is mounted If there is cha
13. ion resistors and diodes i y not shown for other ports pads sp Figure 13 Schematic diagram of the expansion header In the tilt measurement system proposed here uses GPIO 0 to give the 8 bit output of ADC to FPGA The connection diagram is as shown in following figure The figure shows the protection circuitry for only 8 of the pins on header GPIO 0 but this circuitry is included for all 72 data pins 6 3 Regulator using IC 7805 The LM7805 IC of three terminal regulators is available with several fixed output voltages making them useful in a wide range of applications One of these is local on card regulation eliminating the distribution problems associated with single point regulation The voltages available allow these regulators to be used in logic systems instrumentation Hi Fi and other solid state electronic equipment Although designed primarily as fixed voltage regulators these devices can be used with external components to obtain adjustable voltages and currents GNO Figure 14 Regulator IC 7805 6 4 Design of clock generator using IC 555 IC 555 can be designed as Astable Multivibrator to give o p frequency of 25 KHz as follows Since we require 50 duty cycle Vol 2 No 3 July 2011 OIJoAT 345 GND International Journal of Advancements in Technology http ijict org ISSN 0976 4860 145 149 IK RC RC 2910 5 220K IRG et C Q 01F R So Ra Rb 2910 DOP 06 R 2 SKonm
14. mitted to hardware the Simulator can significantly shorten the time it takes to transform our initial design concept into working silicon Depending on the type of information we need we can perform a functional simulation to test the logical operation of our design or we can perform a timing simulation to test both the logical operation and the worst case timing for the design in the target device We are using the Quartus II Simulator to simulate any design in a project We can simulate a full design or any part of a design 4 5 Node Finder The Node Finder is a search tool that allows us to find and use any node name in a compiled Quartus II project We can search for specific node names or types of node names using custom or Altera provided filters and other search criteria We can limit the node name search to specific design entities or you can search the entire project Vol 2 No 3 July 2011 OIJoAT 341 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 Quartus I D project DE2_CLOCK DE2_CLOCK Simulation Report Simulation Waveforms File Edit View Project Assignments Processing Tools Window Help x Joao wal Ma IK 7 ee S YAI e S woe DE2_CLOCK vhd Compilation Report Flow Summary TAY DEZ_CLOCK wut amp Simulation Report Simulation Wave Simulation Report Entity C C C CidiCiWLo GCC Cree Simulation Waveforms
15. nge or deflection in the level of surface the output of the sensor will vary depending on the amount of variation in the level of surface Output of the level sensor is fed to the simple A D converter which is used to convert the analogue value into corresponding 8 bit value 1 e the Vol 2 No 3 July 2011 OIJoAT 335 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 digital data This digital data corresponds to the amount of the changes in the level of surface which will be dependent on the o p of the sensor analogue value fed to it The O P of the A D converter is fed to the DE2 board via an expansion header slot provided on it through an IDE connector There is provision of two expansion headers on DE2 board as GPIO O GPIO 1 Of which the expansion header GPIO O is used The o p of an A D converter is given to the first eight I O pins of the expansion header slot a controller designed in CYCLONE II FPGA chip provided on DE2 board with the help of VHDL and Quartus II takes values available on expansion header slot and converts these values to the required format The controller will display these values on the display provided on DE2 board in required format as e g TILT 019 00 DEG This system is capable of displaying the tilt in the range of 0 to 255 degrees 2 Tools Used 2 1 Altera DE2 Board Figure gives the block diagram of the DE2 board To provide maximum flexibility for the user all connections
16. rpose clocking with clock synthesis and phase shifting as well as external outputs for high speed differential I O support M4K memory blocks are true dual port memory blocks with 4K bits of memory plus parity 4 608 bits These blocks provide dedicated true dual port simple dual port or single port memory up to 36 bits wide at up to 260 MHz These blocks are arranged in columns across the device in between certain LABs Embedoed AA oT iol ies MISA Blocks MWAGA Blois Figure 3 FPGA Cyclone II EP2C35 Each Cyclone II device I O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery of the device Each IOE contains a bidirectional I O buffer and three registers for registering input output and output enable signals 3 3 LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which is called HD44780 A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure os ji Pat ka SESE os S ales x 16 DODrTCTGIT LODO LoD ete Figure 4 Schematic diagram of the LCD module Vol 2 No 3 July 2011 OIJoAT 338 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 The HD44780U dot matrix liquid crystal display controller and driver LSI displays alphanumeric Japanese kana characters and symbols Since all the functions suc
17. s According to this the output voltage changes which is given to A to D converter which coverts analog value to digital value and then it is given to expansion header We choose a multi turn for more power better resolution linearity and stability than a single turn 3 2 Field Programmable Gate Array FPGA Cyclone II devices contain a two dimensional row and column based architecture to implement custom logic Column and row interconnects of varying speeds provide signal interconnects between logic array blocks LABs embedded memory blocks and embedded multipliers The logic array consists of LABs with 16 logic elements LEs in each LAB An LE is a small unit of logic providing efficient implementation of user logic functions LABs are grouped into rows and columns across the device Cyclone II devices range in density from 4 608 to 68 416 LEs Cyclone II devices provide a global clock network and up to four Vol 2 No 3 July 2011 OIJoAT 337 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 phase locked loops PLLs The global clock network consists of up to 16global clock lines that drive throughout the entire device The global clock network can provide clocks for all resources within the device such as input output elements IOEs LEs embedded multipliers and embedded memory blocks The global clock lines can also be used for other high fan out signals Cyclone H PLLs provide general pu
18. sed for initialization and the other 16 states write a single line output on the LCD in the form of ASCII HEX characters Vol 2 No 3 July 2011 OIJoAT 348 International Journal of Advancements in Technology http ijict org ISSN 0976 4860 References 1 J Bhasker VHDL PRIMER Third Edition Pearson Education Pte Ltd Pub Co 2003 2 Douglas L Perry VHDL Programming by Examples Fourth Edition Tata Mc Graw Hill 2002 3 Kenneth Ayala The 8051 microcontroller Architecture amp programming amp Applications Second Edition Penram 4 Kamal Embedded Systems Architecture Programming and Design Publisher Mcgraw Hill Science engineering math 5 FPGA based Implementation of Digital Logic Design using Altera DE2 Board Zeyad Assi Obaid Nasri Sulaiman and M N Hamidon IJCSNS International Journal of Computer Science and Network Security VOL 9 No 8 July 2009 6 Implementing an IC Master Bus Controller in a FPGA for Maxim DS3232 April 2008 Enoch Hwang 7 Altera DE2 Development and Education Board DE2 Package or available online at http www altera com 8 Altera DE2 Development and Education Board user manual Version 1 42 2006 http www altera com Vol 2 No 3 July 2011 OIJoAT 349
19. t the EDA Netlist Writer and the Compiler Database Interface By default the Compiler performs a timing driven compilation File Edit e Project ignment rocessing lool nade Hel D a B UW AA Project Navigator ax Entity a gt Compilation Hierarchy Select the family and device you want to target for compilation Show in Available device lis Family Cyclone Ii Target device Package Ar w C Auto device selected by the Fitter Fin count Any Specific device selected in Available devices list Speed grade Any Core voltage 1 2V IV Show advanced devices wa Available devices Name z Memor Embed PLL 2 4 ByHierarchy J B Files J aP Design Units J EP2C20F484C7 EP2C20F484C8 Status ax EP2C20F 48418 RENIE EP2C200240C8 Module Progress Time S EP2C35F 48406 EP2C35F 48407 EP2C35F 484C8 33216 33840 0 2 EP2C35F 48418 33216 83840 0 amp Quartus I fi 33216 i d Information COR si 29 o gt A Documentation g System Processing A Extra Info A Info A waning A Critical Warming A Error A Suppressed 7 4 Message tl fi ocation Idle For Hel ress F1 Figure 8 Creation of Design File 4 4 Simulation in Quartus IT The Quartus II Simulator is a tool for testing and debugging the logical operation and internal timing of our design Because the Simulator allows us to verify our project before the project is actually com
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