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V1742 & VX1742 User Manual

1. 51 5 46 SCRATCH OXEE20 eU EHE YER 51 5 47 SOFTWARE RESET 0XEF24 W 52 5 48 SOFTWARE CLEAR 0 28 W 2 1 2 2 2 0000044000000060000080000000000000000000000000000 52 5 49 FLASH ENABLE 2 52 5 50 FLASH DATA 52 5 51 CONFIGURATION RELOAD OXEF34 52 6 INSTALLATION 53 6 1 POWERON SEQUENCE A EE O E 53 60 2 POWER ON STATUS aasan der ate eda tee 53 63 FIRMWARE UPGRADE E E E E R 53 NPO Filename Number of pages Page 00103 09 1742 06 V1742_REV6 DOC 54 CAEN Tools for Discover PRELIMINARY Document type Title Revision date Revision Users Manual Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 LIST OF FIGURES FIG 1 1 MOD 1742 BLOCK DIAGRAM eceeeseesseeesseeenceeesneeesceceneceaeecsneeesaeeesaeessaeecsaeeesaeecsaeeeeaeecsaeessaeeeeaeeeeates 9 FIG 2 1 MOD V 1742 FRONT PANEL
2. 11 FIG 2 2 MCX CONNECTOR shana ayau 12 FIG 2 3 AMP CLK IN OUT CONNECTOR n 12 FIG 2 4 PROGRAMMABLE IN OUT CONNECTOR 13 PIG 2 5 EC OPTICAL CONNECTOR Em 13 FIG 2 6 ROTARY AND DIP SWITCHES LOCATION 15 FIG 3 1 ANAEOGINPUT DIAGRAM eene eee deeper eMe qvae pese dee cash 17 32 INPUT BIKGRAM I alana akha qasay 18 FIG 3 3 TRO LOGIC BLOCK DIAGRAM 19 FIG 3 4 CLOCK DISTRIBUTION DIAGRAM 022 2 00 0000 20 FIG 3 5 SAMPLED WAVEFORM AND NOISE HISTOGRAM BEFORE CELL OFFSET CORRECTION 21 FIG 3 6 SAMPLED WAVEFORM AND NOISE HISTOGRAM AFTER CELL OFFSET CORRECTION 21 FIG 3 7 SAMPLED WAVEFORM AND NOISE HISTOGRAM AFTER INDEX SAMPLING CORRECTION 22 FIG 3 8 SAMPLED TRO SIGNAL IN GRO AND BEFORE TIME 23 FIG 3 9 SAMPLED TRO SIGNAL IN GRO AND AFTER TIME CORRECTION nennen nnne 23 Fic 3 10 INL TIME PROFILE OF DRS CHIPS 0 AND BEFORE TIME CORRECTION 24 Fic 3 11 INL TI
3. Bit Function 31 0 write access to this register causes software reset see 8 5 47 reload of Configuration ROM parameters and a PLL reconfiguration NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 52 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 6 Installation The Mod V1742 fits into all GU VME crates VX1742 versions require VME64X compliant crates Use only crates with forced cooling air flow Turn the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion removal A CAUTION USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEAT MAY DAMAGE THE MODULE CAUTION ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 6 1 Power ON sequence To power ON the board follow this procedure 1 insertthe V1742 board into the crate 2 power up the crate 6 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration see 3 10 6 3 Firmware upgrade CAEN provides a firmware upgrade tool see 4 that can be used with either VME or optical link paths Download the software package applicati
4. PORE 14 2 7 TECHNICAL SPECIFICATIONS TABLE 2 2 0 201 2 0 0 0000 uqusqa 16 3 FUNCTIONAL DESCRIPTION 17 Sele JANAEOGINPUT STAGE iei ves bx Pe 17 32 DOMINO RING SAMPLING asul FEE RE ER de sea bae ea y e YR E Rus 17 33 XSTR ANDIRLDINPUTS suu u 18 34 CLOCKDISTRIBUTION eoi tete creen rue ce tol ee pete 19 3 4 1 Multi board synchroniz ti n ise i ie i a i a cds aoa et 20 3 92 DATA 21 3 5 1 offset CONTE CTION kanan a fecti hiss sapa E TURIS Yee 21 3 5 2 Index sampling COTFeCHOR eitis eerte hem rr teat et 22 3 5 3 Time COFFOCHON Say RSS 23 3 6 EVENT STRUCTU RE LL sondage sane ta eve 25 3 6 1 Memory PULL Management ARAM 26 3 7 TRIGGER MANAGEMENT u ee E 27 3 7 1 Trigger distriDUlloh
5. 42 5 13 MEMORY CALIBRATION TABLES DATA 0X1NDJO 42 5 14 GROUP N TR THRESHOLD OXIND4 R W nnne 42 5 15 GROUP TR DC OFFSET OXI NDC R W 2 24 1040200001411000000000000000000000000000000 43 5 16 GROUP CONFIGURATION REGISTER 0X8000 44 5 17 GROUP CONFIGURATION BIT SET 0X8004 45 5 18 GROUP CONFIGURATION CLEAR 0 8008 W 45 5 19 BUFFER ORGANIZATION 0 800 R W a 45 5 20 CUSTOM SIZE 0 6020 R W Pm 45 5 21 INITIAL TEST WAVE VALUE 0X807C 45 NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 4 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT 1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 22 SAMPLING FREQUENCY 0X80D38 46 5 23 ACQUISITION CONTROL 0X8 100 46 5 24 ACQUISITION STATUS 0 8104 R enne nnns seen nennt 46 5 25 SOFTWARE TRIGGER 0X8108 W eei a erase 47 5 26 TRIGGER SOURCE ENABLE MASK 0X810C 47 5 27 FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 R W
6. 47 5 28 POST TRIGGER SETTING 0 8114 47 5 29 FRONT PANEL I O DATA 0 8118 48 5 30 FRONT PANEL I O CONTROL 0X81 R W 48 5 31 GROUP ENABLE MASK 0X8120 R W 48 5 32 ROC FPGA FIRMWARE REVISION 0X8124 R a 49 5 33 EVENT STORED 0X812C BR 49 5 34 SET MONITOR DAC 0x8138 49 5 35 BOARD 0 8140 49 5 36 MONITOR MODE 0X8144 R NW 49 5 37 EVENT SIZE 0 814 49 5 38 VME CONTROL OXBF00 RAW 50 5 39 VME STATUS 0 04 2 1 00 50 5 40 12 R W 50 5 41 MCST BASE ADDRESS AND CONTROL OXEFOC 51 5 42 RELOCATION ADDRESS OXEF10 51 5 43 INTERRUPT STATUS ID OXEF14 R W 51 5 44 INTERRUPT EVENT NUMBER OXEF1 8 2 4 411 400 51 5 45 BLT EVENT NUMBER
7. nnt ees Sie 28 36 FRONT PANEL 28 3 9 TEST PATTERN GENERATOR c ccccssssceesssseeesssneeeessseeeeseseeeesesaeecssaeeessseeeessaeseseeeseseueeesseeeeeseceeeeseneeees 29 3 10 RESET CLEAR AND DEFAULT CONFIGURATION 29 3 10 d Global Reset cese 29 3102 Memory Resele aeaa ukana a a uwa E uh Qa 29 3 10 3 Timer as s aS Qa a a un 30 NPO Filename Number of pages Page 00103 09 1742 06 V1742_REV6 DOC 54 3 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision Users Manual Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 11 VIMEBUS INTERPAGE nasa 30 SALES Addressing capabilitieg 30 3 11 1 1 Base addtes8 oem stein n BERI OR I xe nadie 30 3 11 1 2 CR CSB addte53 n E E 30 3 11 1 3 Address relOCatiOD u n L mer ebd seb eia ire ie sands 31 3 12 DATA TRANSFER CAPABILITIES EAR e CREER ER SEC AREE 31 3 13 EVENTS READOUT eres eec cette 31 3 13 1 Sequential readout i isi oe tp i tro ee et 31 3 13 1 1 SINGLE
8. 0x00 checksum_lengthO 0x20 constant2 OxF010 0x83 constant1 OxF014 0x84 constantO OxF018 Ox01 c_code OxFO1C 0x43 r_code OxF020 0x52 oui2 OxF024 0x00 oui OxF028 0x40 oui0 2 OxE6 vers OxF030 V1742 VX1742 0x70 board2 OxF034 V1742 0x00 VX1742 0x01 board1 OxF038 0 06 board0 OxFO3C 0 revis3 OxF040 0 00 revis2 OxF044 0 00 revis1 OxF048 0 00 revisO OxFO4C 0 01 sernum1 OxF080 0 00 sernumO OxF084 0x16 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout 5 3 Group n Channel Threshold 0x1n80 r w Bit Function 31 0 reserved 5 4 Group n Status 0x1n88 r Bit Function 9 Mezzanine PCB rev 121 0 0 B DRS Chips Busy 7 Group Odd PLL Lock 6 Group Even PLL Lock 5 reserved 4 Group Odd Enable 3 Group Even Enable 2 SPI Bus Busy 1 Busy 0 SPI ready 1 Memory empty 0 Memory full NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 40 Tools f or Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 5 5 6 5 7 5 8 5 9 Daughter board FW revision 0x1n8C Bit Function 31 16 Revision
9. BOARD ID 8 A24 A32 D32 R W X X MULTICAST BASE ADDRESS amp CONTROL OxEFOC A24 A32 D32 R W X RELOCATION ADDRESS OxEF10 A24 A32 D32 R W X INTERRUPT STATUS ID OxEF14 A24 A32 D32 RW X INTERRUPT EVENT NUMBER OxEF18 A24 A32 D32 R W X X BLT EVENT NUMBER OxEF1C A24 A32 D32 R W X X SCRATCH OxEF20 A24 A32 D32 R W X X SW RESET OxEF24 A24 A32 D32 W SW CLEAR OxEF28 A24 A32 D32 W FLASH ENABLE OxEF2C A24 A32 D32 X FLASH DATA A24 A32 D32 R W X CONFIGURATION RELOAD OxEF34 A24 A32 D32 CONFIGURATION ROM OxF000 OxF3FC A24 A32 D32 5 2 Configuration ROM 0xF000 0xF084 The following registers contain some module s information they are D32 accessible read only manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 39 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 Table 5 2 ROM Address Map for the Model V1742 Description Address Content checksum 000 OxA4 checksum_length2 0 004 0x00 checksum_lengthi OxF008
10. Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 TABLE OF CONTENTS 1 GENERAL DESCRIPTION 8 LI OVERVIEW I E n DI 8 12 BEOCK DIAGRAM nien rete 9 2 TECHNICAL SPECIFICA TIONS 10 2 1 PACKAGING AND COMPLIANCY ccsccccsssssceessseceessseeecsseecessneeecssaeeecsuaeeeeseaeeesesueeecseaeeeeseseeesssneeesseaeeess 10 2 2 POWER REQUIREMENTS 10 223 11 2 4 EXTERNAL CONNECTORS aus a Se COR 12 2 4 1 INPUT CORRE CLOTS eiie Rau aaah 12 2 4 2 CONTROL COMME CLOTS sisi 12 2 4 3 ADC REFERENCE CLOCK 12 2 4 4 Digital I O ConneCtO 13 2 4 5 Optical LINK COnnector u a na tee qaa 13 2 5 OTHER FRONT PANEL COMPONENTS a 14 2 5 1 DA RR P 14 2 0 INTERNAL COMPONENTS
11. 0x5C16 write 0x5C16 at address Ox12D4 or 0x13D4 Negative signal on TRn V 0 200mV TRO DC Offset 0x8000 write 0x8000 at address Ox 10DC or Ox11DC TRO Threshold 0x613E write 0x613E at address Ox 10D4 or 0x11D4 TRI DC Offset 0x8000 write 0x8000 at address 12DC Ox13DC TR1 Threshold 0x613E write Ox613E at address 0x12D4 or Ox 13D4 Bipolar signal on TRn TRO DC Offset 0x8000 write 0x8000 at address 0x10DC or Ox11DC TRO Threshold 0x6666 write 0x6666 at address 0x10D4 or Ox11D4 TRI DC Offset 0x8000 write 0x8000 at address 0x12DC Ox13DC TRI Threshold 0x6666 write 0x6666 at address 0x 12D4 or 0x13D4 TTL on TRn or Positive signal on TRn V 0 22V TRO DC Offset 0xA800 write 0xA800 at address Ox10DC or Ox11DC TRO Threshold 0x6666 write 0x6666 at address Ox 10D4 or Ox11D4 TR1 DC Offset 0xA800 write 0xA800 at address Ox12DC or 0x13DC TR1 Threshold 0x6666 write 0x6666 at address Ox 12D4 or Ox13D4 Positive on TRn V 0 2V TRO DC Offset 0x91A7 write 0x91A7 at address 0x10DC or Ox11DC TRO Threshold 0x6666 write 0x6666 at address OX10D4 or Ox11D4 TRI DC Offset 0x91A7 write 0x91A7 at address Ox12DC 0x13DC TRI Threshold 0x6666 write 0x6666 at address 0x 12D4 or 0x13D4 Mezzanine PCB Rev 0 NIM signal on TRn TRO DC Offset 0x1000 write 0x1000 at address 0x10DC or Ox11DC NPO Filename Number of pages Page 001
12. 8 Trigger Time Tag records the Trigger arrival time each bin has a 8 5ns width 3 6 1 Memory FULL management Bits of Acquisition Control register see 5 23 allows to select Memory FULL management mode NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 26 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 7 NPO TRG IN In Normal Mode the board becomes full whenever all buffers are full otherwise Always one buffer free mode it is possible to always keep one buffer free board becomes full whenever N 1buffers are full with N nr of blocks In Normal Mode the board waits until one buffer is filled since FULL status is exited whether the trigger is overlapped or not The board exits FULL status at the moment which the last datum from the last channel participating to the event is read In Always one buffer free mode one buffer cannot be used therefore it is NOT POSSIBLE with this mode to set Buffer Code to 0000 see 5 19 but this allows to eliminate dead time when FULL status is exited Trigger management Signal digitization can be triggered basically in two ways Common trigger a trigger produced via software via VME or Optical Link or sent via front panel TRG IN signal NIM TTL signal on LEMO connector 50 Ohm impedance
13. PECL LVPECL CML Zdiff 100 Ohm Mechanical specifications AMP 3 102203 4 connector CLK_OUT Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 100 Ohm Mechanical specifications AMP 3 102203 4 connector Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 12 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 4 4 Digital connectors m Fig 2 4 Programmable IN OUT Connector Function N 16 programmable differential LVDS signals Zdiff_in 110 Ohm Four Independent signal group 0 3 4 7 8 11 12 15 In Out direction control Lowest couple 0 highest couple not connected See also 3 8 Mechanical specifications 3M 7634 5002 34 pin Header Connector 2 4 5 Optical LINK connector LINK TX red wrap RX black wrap Fig 2 5 LC Optical Connector Mechanical specifications LC type connector to be used with Multimode 62 5 125um cable with LC connectors on both sides see also 3 14 CAEN provides optical fiber cables with a duplex connector on the A2818 side and two simplex connectors on the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher Electrical specifications Optical link for data readout and slow control with
14. order to handle TRn positive signals larger than 2V WARNING Before writing this register it is necessary to check that the SPI Bus Busy flag in the Status Register 5 4 is set to 0 otherwise the process of writing will not give error messages out but it will not run properly 5 16 Group Configuration Register 0x8000 r w Bit Function Select monitor signal from daughter board 0000 no signal 31 28 0001 all fast trigger 0010 accepted fast trigger 0011 busy 27 13 reserved MUST ALWAYS BE SET TO 0 TRn Trigger Enable when this bit is 1 TRn signal is used as local trigger 0 TRn Local Trigger disabled Default 12 TRn Local Trigger enabled Signal TRn Readout Enable when this bit is 1 signal TRn is present in data readout 0 Signal TRn Readout disabled Default 1 Signal TRn Readout enabled 10 9 reserved MUST ALWAYS BE SET TO 0 8 Individual Trigger must 1 7 reserved MUST ALWAYS BE SET TO 0 TR Trigger polarity 6 0 Rising Edge Default 1 Falling Edge 5 reserved MUST ALWAYS BE SET TO 0 4 reserved MUST ALWAYS BE SET TO 1 Test Mode when this bit is 1 the ADC samples are replaced by a 3 sawtooth generated by the FPGA 0 2 Normal mode data from the DRS4 and ADC Default 12 Test Mode emulated data from the sawtooth generator 2 0 reserved MUST ALWAYS BE SET TO 0 12 11 NPO Filename Number of
15. After trigger analog samples are digitized by external ADC 12 bit 110us Analog inputs only 181us Analog inputs TRO TR1 inputs sampling clock generation supports two operating modes PLL mode internal reference 50 MHz local oscillator PLL mode external reference on CLK Jitter lt 100ppm Freq 50 MHz CLK IN AMP Modu ll AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available on request Jitter lt 100ppm TRG_IN LEMO 50 Ohm NIM TTL S IN 50 Ohm NIM TTL 1 Altera Cyclone EP3C16 for 161 channels 128 event ch 1024 samples per event Multi Event Buffer with independent read and write access Common Trigger TRG External signal Software from VME or Optical Link Fast local trigger Fast local trigger TRO and TR1 with individual programmable analog threshold CAEN proprietary protocol up to 80 MB s transfer rate Daisy chainable it is possible to connect up to 8 32 ADC modules to single Optical Link Controller Mod A2818 A3818 Allows data alignment and consistency across multiple V1742 modules allows the synchronization to a common clock source S IN ensures start acquisition times alignment Firmware can be upgraded via VME Optical Link VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast CyclesTransfer rate 60MB s MBLT64 100MB s 2eVME 160MB s 2eSST Sequential and random access to th
16. DC offset is adjustable via 16bit DAC 1V range on each channel and allows tot sample either bipolar Vin 0 5V or unipolar full positive Vin 0 1V or negative Vin 0 1V analog input swing without losing dynamic resolution The analog input signals are continuously sampled into the DRS4s in a circular analog memory buffer 1024 cells default sampling frequency is 5GS s 2 5GS s and 1GS s frequencies can be also programmed As a trigger signal arrives all analog memory buffers are frozen and subsequently digitized with a 12bit resolution into a digital memory buffer The digital memory 128 events deep for each channel where 1 event 1024x12bit allows to store subsequent events even if the readout is not yet started Moreover since the digital memory buffers work like FIFOs the readout activity from VME or Optical Link does not affect write operations of subsequent events A common board trigger can be provided via VME or Optical Link or by TRG IN input Two special fast analog trigger inputs TRO and TR1 TTL NIM levels compatible can be used as lo latency external trigger signals These special inputs can be also sampled into the DRS4s analog memory buffers for applications where high resolution timing and time analysis with a common reference signal like a trigger or system clock is required During analog to digital conversion process the V1742 cannot handles other triggers this is called Dead Time Dead time will be
17. In this case all the channels in a board share the same trigger e Low latency trigger a logic level fed directly into the DRS4 via the front panel TRn signals In this case one TRn signal triggers two groups TRO for Groups 0 and 1 TR1 for Groups 2 and 3 As a trigger signal arrives the analog buffers related to that trigger are frozen and then digitized with a 12bit resolution ADC into the digital memory buffer During analog to digital conversion process the V1742 cannot handles other triggers this Dead Time is larger if also TRO and or TR1 input channels are sampled together with the analog inputs see S3 3 The TRO TR1 are actually analog inputs but they are also TTL NIM compatible order to use them as low latency external trigger signals it is necessary to set properly the Configuration Register Local TRn Trigger Enable bit see 3 3 Once the acquisition is triggered in one of the ways described above digitization takes place as described in 3 2 Mezzanines Mother Board Memory TRG OUT 5 Buffers m Acquisition Logic B x8 8 8 Digital Enable Mask Thresholds TRO TR1 VME Local Bus Interface Interface Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742_REV6 DOC 54 27 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06
18. V1742 REV6 DOC 54 10 CAEN PRELIMINARY Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 3 Front Panel Mod V1742 X 1 lt lt lt y 32 CH 12 BIT 5 GS s DIGITIZER Fig 2 1 Mod V1742 front panel Number of pages Page NPO Filename 54 11 00103 09 1742 06 V1742_REV6 DOC Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 4 NPO External connectors 2 4 1 INPUT connectors CH0 Fig 2 2 MCX connector Function Analog input single ended Zin 50 Ohm TR 1 0 Fast TRG input Zin 50 Ohm Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER Suggested plug MCX 50 2 16 type Suggested cable RG174 type 2 4 2 CONTROL connectors Function e TRG OUT Local trigger output NIM TTL on Rt 50 Ohm e TRG IN External trigger input NIM TTL Zin 50 Ohm e SYNC SAMPLE START S IN Sample front panel input NIM TTL Zin 50 Ohm e 5 DAC output 1Vpp on Rt 50 Ohm Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors GND CLK Fig 2 3 AMP CLK IN OUT Connector CLK_IN Function CLK IN External clock Reference input AC coupled diff LVDS ECL
19. an external via front panel signal or an internal via local oscillator source selection is performed via dip switch SW1 see 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway REF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details available on http www analog com Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 19 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 Fig 3 4 Clock distribution diagram 3 4 1 Multi board synchronization To be implemented NPO Filename Number of pages Page 00103 09 1742 06 V1742_REV6 DOC 54 20 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 5 Data correction ADC counts ADC counts 3 5 1 Three types of data correction are required in order to compensate for unavoidable construction differences in the DRS4 chips All boards are factory calibrated during production test and correction parameters are saved on board see 6 3 Application software provided by CAEN r
20. integral non linearity INL time profile of DRS chips before and after correction 3500 T T T wave tr 970 notimecorr txt wave tr gr1 notimecorrtxt 3000 4 2500 2000 f ADC counts 1500 1000 500 Samples Fig 3 8 Sampled TRO signal in GRO and before time correction 3500 T T T wave tr 970 timecorrtxt wave tr gr1 3000 2500 2000 ADC counts 1500 1000 500 0 200 400 600 800 1000 Samples Fig 3 9 Sampled TRO signal in GRO and GR1 after time correction NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 23 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 08 T T T T TimelNL_5GHz_chip0 txt TimelNL_ 5GHz_chip1_txt Noise 0 200 400 600 800 1000 Samples Fig 3 10 INL time profile of DRS chips 0 and 1 before time correction ResidualTimelNL 5GHz chip tx ResidualTimelNL 5GHz 0 04 lt 0 02 1 r 0 02 1 0 04 3 1 i 1 1 1 0 200 400 600 800 1000 Samples Fig 3 11 INL time profile of DRS chips 0 and 1 after time correction NPO Fi
21. s therefore it is possible to connect up to eight V1742 s to a single Optical Link Controller for more information see www caen it path Products Front End PCI PCIe Optical Controller The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 allows to enable the module to broadcast an interrupt request on the Optical Link the enabled Optical Link Controllers propagate the interrupt on the PCI bus as a request from the Optical Link is sensed VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having higher priority anyway it is better to avoid accessing the board via VME and Optical Link simultaneously Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 33 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 32 2 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 4 Software tools NPO CONET2 Optical Link Fig 4 1 Block diagram of the software layers CAEN provides drivers for both the physical communication channels the proprietary CONET Optical Link managed by the A2818 PCI card or A3818 PCle cards and the VME bus accessed by the V1718 and V2718 bridges refer to the related User Manuals a set of C
22. 0 panel output signals TRG OUT CLKOUT enabled 1 12 panel output signals TRG OUT CLKOUT enabled in high impedance 0 0 TRG CLK are NIM I O Levels 1 TRG CLK TTL Levels Bits 5 2 are meaningful for General Purpose use only 15 7 6 5 31 Group Enable Mask 0x8120 Bit Function 3 0 Group 3 disabled 1 Group enabled 2 0 Group 2 disabled 1 Group 2 enabled 1 0 Group 1 disabled 1 Group 1 enabled 0 0 Group 0 disabled 1 Group 0 enabled Enabled groups provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 48 Tools for Discovery Document type Title User s Manual MUT 5 3 2 Bit Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer PRELIMINARY Revision date Revision 06 02 2012 6 ROC FPGA Firmware Revision 0x8124 r Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 5 33 Event Stored 0 812 Bit Function 31 0 This register contains the number of
23. 00 A24 A32 D32 RW X X Group CONFIGURATION BIT SET 0x8004 A24 A32 D32 W X X Group CONFIGURATION BIT CLEAR 0x8008 A24 A32 D32 W X X BUFFER ORGANIZATION 0x800C A24 A32 D32 RW X X CUSTOM SIZE 0x8020 A24 A32 D32 RW X X INITIAL TEST WAVE 0x807C A24 A32 D32 R W X X SAMPLING FREQUENCY 0x80D8 A24 A32 D32 RW X X ACQUISITION CONTROL 0x8100 A24 A32 D32 X X ACQUISITION STATUS 0x8104 A24 A32 032 X X SW TRIGGER 0x8108 A24 A32 D32 W TRIGGER SOURCE ENABLE MASK 0x810C A24 A32 D32 RW X X FRONT PANEL TRIGGER OUT ENABLE MASK 0x8110 A24 A32 D32 RW X X POST TRIGGER SETTING 0x8114 A24 A32 D32 RW X X FRONT PANEL I O DATA 0x8118 A24 A32 D32 RW X X FRONT PANEL I O CONTROL 0 811 A24 A32 D32 RW X X Group ENABLE MASK 0x8120 A24 A32 D32 X X NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 38 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 REGISTER NAME ADDRESS ASIZE DSIZE MODE S_RES CLR ROC FPGA FIRMWARE REVISION 0x8124 A24 A32 D32 EVENT STORED 0x812C A24 A32 D32 X X X SET MONITOR DAC 0x8138 A24 A32 D32 R W X X BOARD INFO 0x8140 A24 A32 D32 MONITOR MODE 0x8144 A24 A32 D32 X X EVENT SIZE 0 814 A24 A32 D32 X X X VME CONTROL OxEFOO A24 A32 D32 R W X VME STATUS 0 04 A24 A32 D32
24. 02 2012 6 Fig 3 14 Block diagram of Trigger management 3 7 1 Trigger distribution 3 8 NPO The OR of all the enabled trigger sources after being synchronized with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG_OUT connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal Front Panel l Os The V1742 is provided with 16 programmable general purpose LVDS I O signals Signals can be programmed via VME see 5 29 and 5 30 Default configuration is Table 3 1 Front Panel I Os default setting Nr Direction Description 0 out Group 0 Trigger Request 1 out Group 1 Trigger Request 2 out Group 2 Trigger Request 3 out Group 3 Trigger Request 4 E 5 6 7 8 Memory Full 9 out Event Data Ready 10 out Channels Trigger 11 out RUN Status 12 in Trigger Time Tag Reset active low 13 in Memory Clear active low 14 RES
25. 020 r w Bit Function 00 1024 sample ch 01 520 sample ch 10 256 sample ch 11 136 sample ch This register must not be written while acquisition is running 1 0 5 21 Initial test wave value 0x807C Bit Function 11 0 Test wave start value NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 45 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 22 Sampling Frequency 0x80D8 Bit Function 1 0 00 5 GS s 01 2 5 GS s 10 1 GS s 11 reserved use This register must not be written while acquisition is running 5 23 Acquisition Control 0x8100 r w Bit Function 5 0 Normal Mode default board becomes full whenever all buffers are full 1 Always keep one buffer free board becomes full wnenever N 1 buffers are full N 1024 4 reserved 3 0 COUNT ACCEPTED TRIGGERS 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 3 5 2 0 Acquisition STOP 1 Acquisition RUN allows to RUN STOP Acquisition 1 0 reserved Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset see 3 10 2 is automatically performed When bi
26. 03 09 V 1742x MUTx 06 V1742 REV6 DOC 54 43 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 TRO Threshold 0x717D write 0x717D at address 0x10D4 or Ox11D4 TRI DC Offset 0x1000 write 0x1000 at address 0x12DC Ox13DC TRI Threshold 0x717D write 0x717D at address 0x12D4 or 0x13D4 Negative signal on TRn V 0 400mV TRO DC Offset 0x1000 write 0x1000 at address 0x10DC or Ox11DC TRO Threshold 0x6E72 write 0x6E72 at address Ox 10D4 or Ox11D4 TRI DC Offset 0x1000 write 0x1000 at address 12DC or Ox13DC TRI Threshold 0x6E72 write 0 6 72 at address 0x12D4 or 0x13D4 Bipolar signal on TRn TRO DC Offset 0x1000 write 0x1000 at address Ox 10DC or Ox11DC TRO Threshold 0x6C80 write 0x6C80 at address 0x10D4 or 0x11D4 TRI DC Offset 0x1000 write 0x1000 at address 12DC Ox13DC TRI Threshold 2 0x6C80 write 0x6C80 at address Ox12D4 or Ox13D4 TTL on TRn or Positive signal on TRn V 0 22V TRO DC Offset 0x4000 write 0x4000 at address 0x10DC or Ox11DC TRO Threshold 0x7158 write 0x7158 at address 0x10D4 or Ox11D4 TRI DC Offset 0x4000 write 0x4000 at address 0x12DC Ox13DC TRI Threshold 0x7158 write 0x7158 at address Ox 12D4 or 0x13D4 On boards with Mezzanines PCB Rev 1 it is suggested to use an external attenuator in
27. 9 V1742x MUTx 06 V1742_REV6 DOC 54 6 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 TABLE LI MOD Vil 742 VERSIONS sizes ctis voee FREE RR E te pado REPE 9 TABLE 2 1 MODEL 1742 POWER REQUIREMENT S esee een 10 TABLE 2 2 FRONT PANEL LEDS 14 TABLE 2 3 V1742 TECHNICAL SPECIFICATIONS 1 12 00 00000000000000 16 TABLE 3 1 FRONT PANEL I OS DEFAULT SETTING racirea uea EEE AE A E EETA E 28 TABLE 5 1 ADDRESS MAP FOR THE MODEL 172 38 TABLE 5 2 ROM ADDRESS MAP FOR THE MODEL 1742 00 1 00000000000000000000000000 40 NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 7 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 1 General description 1 1 NPO Overview The Mod V1742 is a VME board housing two 16 1Channels 12bit 5GS s Switched Capacitor Digitizer sections based on DRS4 Domino Ring Sampler chip with 1 Vpp input dynamic range on single ended MCX coaxial connectors A VME64X mechanics version Mod VX1742 is also available The
28. AAA 128 event ch 6U VME64 V1742B WV1742XAAAAA 1024 event ch 6U VME64 VX1742 WVX1742BXAAA 128 event ch 6U VME64X VX1742B WVX1742XAAAA 1024 event ch 6U VME64X 1 2 Block Diagram FRONT PANEL fff p s BUFFERS z 0 SE vv SEE FIT o5 4 lt o C 5 E ROC FPGA Readout control VME interface control Optical link control i Trigger control External interface control Fig 1 1 Mod V1742 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename 00103 09 V1742x MUTx 06 V1742_REV6 DOC Number of pages Page 54 9 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 Technical specifications 2 1 Packaging and Compliancy The module is housed in a 6U high 1U wide VME unit The board hosts the VME P1 and P2 connectors and fits into both VME VME64 standard and V430 backplanes VX1742 versions fit into VME64X compliant crates In all cases only well ventilated crates must be used 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1742 power requirements 5 V 5 5 12 V 200 12 V 300 Filename Number of pages Page 00103 09 V 1742x MUTx 06
29. BERR signal during BLT32 cycles in order to end the cycle avoiding filler readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below READOUT DATA 0 BUFFERS 1 2 3 Group size 1024 bytes BERR enabled BLT size 16384 bytes N 4 Fig 3 20 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGN64 bit in the VME Control register see S 5 34 MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are multiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals DS and DTACK to complete a data cycle Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 32 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 13 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1742 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CB
30. D32 I ukun R 32 3 13 1 2 BLOCK TRANSFER D32 D64 26 VME u a ee TO ORE HYS PORTO ha re reds 32 3 13 1 3 CHAINED BLOCK TRANSFER D32 D 64 33 2213 2 33 3 14 OPTICAL LINK 5 33 4 SORT WARE TOOLS CER 34 5 VME INTERFACE usasqa 38 5 1 REGISTERS ADDRESS 38 5 2 CONFIGURATION ROM 0 000 0 084 R a 39 5 3 GROUP N CHANNEL THRESHOLD 0 1980 40 54 GROUP N STATUS OXINGS8 ced 40 5 5 DAUGHTER BOARD FW REVISION OXIN8C ener nennen 41 5 6 GROUP N BUFFER OCCUPANCY 0XIN94 41 57 GROUP N CHANNEL DC OFFSET OX1N98 R W a 41 5 8 GROUP N ADC CONFIGURATION 0X1N9C R MW a 41 5 9 DRS4 TEMPERATURE 41 5 10 CHANNEL N DAC SEL 0X1NA4 42 5 11 GROUP N CHANNEL TRIGGER MASK OXINAS 42 5 12 MEMORY CALIBRATION TABLES ENABLE 8 410 0000 00
31. ERVED 15 RESERVED Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 28 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 9 Test pattern generator The FPGA can emulate the ADC and write into memory a sawtooth signal for test purposes It can be enabled via Group Configuration register see 0 The following figure shows the test waveforms for even and odd groups respectively Even channel test wave 4800 4095 4000 3200 2400 1600 800 0 0 800 1600 2400 3200 4000 4800 Odd channel test wave 4800 4095 4000 3200 2400 1600 800 0 800 1600 2400 3200 4000 4800 Fig 3 15 FPGA test waveform Since an event is made up of up to 1024 samples the test event samples only a portion of the sawtooth the start point of the sampling can be programmed via Initial Test Wave Value register see 5 21 for example if this register is set to OXOFF then the channels in the even groups sample the ramp between 255 and 1278 the channels in the odd groups instead sample the complementary value therefore between 3840 and 2817 3 10 Reset Clear and Default Configuration 3 10 1 Global Reset Global Reset is performed at Power ON of the module or via a VME RESET SYS RES see 5 47 It allows to clear the data off the Output Buffer the event counter and perfor
32. Function This register defines the maximum number of events that can be transferred in a 7 0 Block Transfer Cycle after which the board asserts the Bus Error to stop the transfer Allowed setting is between 0 meaning no limit and 255 5 46 Scratch 0xEF20 r w Bit Function 31 0 Scratch to be used to write read words for VME test purposes NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 51 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 47 Software Reset 0xEF24 w Bit Function A write access to this register causes a board reset the acquisition 31 0 16 stopped all the registers are set to the default settings and all data are cleared 5 48 Software Clear OxEF28 w Bit 31 0 Function A write access to this register causes a data clear the registers setting is not modified 5 49 Flash Enable OxEF2C r w Bit 0 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool Function 5 50 Flash Data OxEF30 r w Bit Function 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 5 51 Configuration Reload OxEF34 w
33. LT is based on the passing of a token between the boards it is necessary to verify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or las via MCST Base Address and Control Register see 5 41 A common Base Address is then defined via the same register when a BLT cycle is executed at the address CBLT Base 0x0000 OxOFFC the first board starts to transfer its data driving DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If the size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point where the previous cycle has ended 3 13 2 Event Polling 3 14 NPO A read access to Event Size register see 5 36 allows polling the number of 32 bit words composing the next event to be read this permits to perform a properly sized according to the Event Size information BLT readout from the Memory Event Buffer Optical Link The board houses a daisy chainable Optical Link communication path which uses optical fiber cables as physical transmission line able to transfer data at 80 MB
34. ME PROFILE OF DRS CHIPS 0 AND AFTER TIME CORRECTION a 24 E1G 3 125 BVENTEEORMAT 25 FIG 3 13 GROUP DATA FORMAT Sun 26 FIG 3 14 BLOCK DIAGRAM OF TRIGGER MANAGEMENT 28 FIG 3 15 FPGA TEST 29 3 16 A24 ADDRESSING 30 PIG 3207 A32 ADDRESSING uya aaa a A sk ista eerie ead 30 FIG 3 18 CR CSR ADDRESSING was N Ove deese ede dva Nea eee RE a pis 31 FIG 3 19 SOFTWARE RELOCATION OF BASE ADDRESS teer 31 FIG 3 20 EXAMPLE OF BLT 2 42 2 0004000 32 FIG 4 1 BLOCK DIAGRAM OF THE SOFTWARE LAYERS 34 4 2 WAVEDUMP OUTPUT WAVYEBFORMS uuu nsn aus 35 4 3 CAENSCOPE OSCILLOSCOPE iaeaea i a iaeiei 35 FIG 4 4 CAENUPGRADER GRAPHICAL USER INTERFACE enne nnne neret nnne 36 FIG 4 5 DPP CONTROL SOFTWARE GRAPHICAL USER INTERFACE AND ENERGY PLOT 37 LIST OF TABLES NPO Filename Number of pages Page 00103 0
35. S s Switched Capacitor Digitizer 06 02 2012 6 easy steps to upload different firmware versions on CAEN boards to upgrade the VME digitizers PLL to get board information and to manage the firmware license CAENUpgrader requires the installation of 2 CAEN libraries CAENComm CAENVMELib and Java SE6 or later CAENComm allows CAENUpgrader to access target boards via USB or via CAEN proprietary CONET optical link CAEN Upgrader GUI Upgrade CAEN Front End Hardware CAEN Electronic Instrumentation z SIC 58 Bridge Upgrade Available actions Connection Type Config Options o Standard Page Upgrade Firmware USB Backup Page Board Model UNK number LJ B Skip Verity VME Base Address Upgrade Firmware binary file cvUpgrade Ready Fig 4 4 CAENUpgrader Graphical User Interface DPP Control Software is an application that manages the acquisition in the digitizers which have DPP firmware installed on it The program is made of different parts there is a GUI whose purpose is to set all the parameters for the DPP and for the acquisition the GUI generates a textual configuration file that contains all the parameters This file is read by the Acquisition Engine DPPrunner which is a C console application that programs the digitizer according to the parameters starts the acquisition and manage the data readout The data that can be waveforms time stamps energies o
36. Technical Information Manual Revision n 6 06 February 2012 MOD V1742 32 2 CH 12 BIT 5 GS s DIGITIZER MANUAL REV 6 NPO 00103 09 V1742x MUTx 06 CAEN will repair replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards CAEN
37. and LabView libraries demo applications and utilities Windows and Linux are both supported The available software is the following CAENComm library contains the basic functions for access to hardware the aim of this library is to provide a unique interface to the higher layers regardless the type of physical communication channel Note for VME access CAENcomm is based on CAEN s VME bridges V1718 USB to VME and V2718 PCI PCle to VME In the case of third part bridges or SBCs the user must provide the functions contained in the CAENcomm library for the relevant platform The CAENComm requires the CAENVMELib library to be installed even in the cases where the VME is not used CAENDigitizer is a library of functions designed specifically for the digitizer family and it supports also the boards running special DPP Digital Pulse Processing firmware The purpose of this library is to allow the user to open the digitizer program it and manage the data acquisition in an easy way with few lines of code the user can make a simple readout program without the necessity to know the details of the registers and the event data format The CAENDigitizer library implements a common interface to the higher software layers masking the details of the physical channel and its protocol thus making the libraries and applications that rely on the CAENDigitizer independent from the physical layer The library is based on the CAENComm library that manages the com
38. ation Data will erase the module s calibration pattern 5 13 Memory Calibration Tables Data 0 1 00 Bit Function 7 0 Data to be serialized or read from Memory Tables calibration This register allows to access the memory location where calibration data are stored see 3 5 CAUTION before writing this register it is necessary to verify that SPI Bus Busy Flag in the Status register 5 4 is 0 and in any case its use is reserved to experienced Users since a wrong value written in the Memory Calibration Data will erase the module s calibration pattern 5 14 Group n TR Threshold 0x1nD4 Bit Function 15 0 Threshold The threshold on TRn for local trigger generation can be set by a programmable 16bit DAC One TRn signal is common to two groups therefore for example write access to either 0x10D4 or 0x11D4 leads to the same setting for TRO input For TRn Threshold setting example see the paragraph below NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 42 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 A WARNING Before writing this register it is necessary to check that the SPI Bus Busy flag in the Status Register S 5 4 is set to 0 otherwise the process of writing will not give error messages out bu
39. d either on the leading or the trailing edge depending on Configuration register setting see 5 16 Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 18 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 4 NPO lt Tebit GROUP 1 GROUP 0 DIGITAL FPGA MEMORY BUFFER TRO Input DRS4 Y ADC 12bit COMP eu 16bit Fig 3 3 TRO logic block diagram Clock Distribution The module V1742 features a PLL for clock synthesis with a selectable internal or external reference clock source Multi board synchronization can be done by driving a clock on CLOCK IN input allowing all DRS4s to run synchronously with this external reference All analog inputs will be sampled at the same time without time drift allows high resolution timing and time analysis across multiple V1742 The module clock is provided by OSC CLK and REF CLK OSC CLK is a fixed 50MHz clock provided by an on board oscillator it handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure below REF CLK handles trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either
40. date Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2010 is 0xA6120103 Group n Buffer Occupancy 0x1n94 r Bit Function 10 0 Occupied buffers 0 1024 Group n Channel DC offset 0x1n98 r w Bit Function 19 16 Channel index from 0x0 to 0x7 only one DAC ch or OxF all DAC ch 15 0 DAC Data The input DC offset can be adjusted group per group and channel per channel by means of a programmable 16bit DAC there is a DAC serving each group 8 channels Default value 0x8F00 about for input bipolar signals The channel index field bits 19 16 is used only in write access In read access channel index must be set on CH DAC SEL register see Channel DAC Select register For example in order to set the DAC Value 0x6C00 for channel 15 channel 7 of group 1 a write access to address 0x1198 with value 0x76C00 must be performed In order to readout the channel 15 DAC Value a write access to address 0 11 4 with value 0x7 must be performed and then a read access to address 0x1198 A WARNING Before writing this register it is necessary to check that the SPI Bus Busy flag in the Status Register 5 4 is set to 0 otherwise the process of writing will no
41. e CPU 1 BERR Enabled the module is enabled either to generate a Bus error to 3 0 Optical Link interrupt disabled 1 Optical Link interrupt enabled 2 0 Interrupt level 0 interrupt disabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only In RORA mode interrupt status can be removed by accessing VME Control register see 5 38 and disabling the active interrupt level In ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level gt 0 via VME Control register VME Status OxEF04 Bit Function 3 0 VME FIFO not empty 1 VME FIFO empty 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register read out 1 reserved 0 No Data Ready 0 y 1 Event Ready Board ID 0xEF08 r w Bit Function 4 0 GEO VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of
42. e data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access Libraries C and LabView Demos and Software tools for Windows and Linux NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 1742 REV6 DOC 54 16 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 Functional description 3 1 3 2 NPO Analog input stage Input dynamic is 1Vpp on single ended MCX coaxial connectors Zin 50 Ohm A 16bit DAC allows to add up to 1V DC offset in order to preserve the full dynamic range also with uni polar positive or negative input signal The input bandwidth ranges from DC to 500 MHz Input Dynamic Range 1 Vpp Ww MOX 1 50 Positive Unipolar Input AW WW z DAC FSR DRS4 12 bit 0 50 AAA Vref F PG A 0 16 bi it Negative Unipolar DAC 0 1 50 50 DAC FSR 2 Fig 3 1 Analog input diagram Domino Ring Sampling The analog input signals are continuously sampled into the DRS4s Domino Ring Sampler which consists of an on chip inverter chain domino wave circuit generating a maximum 5GS s sampling frequency 2 5GS s and 1GS s frequencies can be also programmed see 5 21 No external sampling clock is
43. ecovers automatically the calibration parameters and runs them in order to correct the stored data events Cell offset correction Unavoidable construction differences between the analog memory cells see 3 1 require an amplitude calibration algorithm The following images show the sampled waveform and noise histogram before and after correction 25 2200 2150 2100 2050 2000 histo_ch0_nocorrection txt wave_ch0_nocorrection txt 20 WII 15 Occurrence 1950 200 400 600 800 1000 2000 2050 2100 2150 Samples ADC counts Fig 3 5 Sampled waveform and noise histogram before cell offset correction 300 2200 2150 2050 2000 2100 F 1 histo ch offsetcorrection txt wave ch offsetcorrectionibx 250 200 8 5 100 F L 1950 NPO 00103 09 1742 06 1000 1950 2000 2050 2100 2150 2200 200 400 600 800 ADC counts Samples Fig 3 6 Sampled waveform and noise histogram after cell offset correction Filename Number of pages Page V1742_REV6 DOC 54 21 CAEN Tools for Discovery Document type Title User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Ca
44. eted the relevant memory buffer becomes free and ready to be written again old data are lost After the last word in an event the first word Header of the subsequent event is readout It is not possible to readout an event partially Filename Number of pages Page 1 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 3 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 NPO 3 13 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in 3 5 We suggest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event 3 13 1 2 BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register see 5 45 Event Size 4 Group Size 16 bytes Group Size depends on Custom Size setting see 5 20 and whether TRn signals are stored in the event or not Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable
45. events currently stored in the Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 5 34 Set Monitor DAC 0x8138 r w Bit Function 31 0 reserved 5 35 Board Info 0x8140 Bit Function 15 8 Memory size Mbyte Group 7 0 Board Type 0x06 5 36 5 37 NPO 00103 09 V 1742x MUTx 06 Monitor Mode 0x8144 r w Bit Function 31 0 reserved Event Size 0x814C r Bit Function 31 0 Nr of 32 bit words in the next event Filename V1742 REV6 DOC Number of pages Page 54 49 Tools for Discovery Document type PRELIMINARY Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 38 5 39 5 40 NPO VME Control Bit Function 7 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 6 0 RELOC Disabled is selected via Rotary Switch see 2 6 1 RELOC Enabled BA is selected via RELOC register see 5 42 0 ALIGN64 Disabled 5 4 ALIGN64 Enabled see 3 13 1 2 inquires the module 4 74 finish a block transfer or during the empty buffer read out in D32 0 BERR Not Enabled the module sends a DTACK signal until th
46. he following format example of Group 0 31 29 28 27 26 25 24 23 22 21 20 19 8 17 16 15 14 3 12 11 10 9 8 7 16 5 4 13 2 1 010 START INDEX CELL 10 0 EREQ 0 0 0JTR SIZE CH 0 7 S0 CH2 LO S0 CH1 S0 CHO S0 CH5 LO S0 CH4 S0 CH3 S0 CH2 HI S0 CH7 S0 CH6 S0 CH5 HI S1 CH2 LO S1 CH1 S1 CHO S1 CH5 LO S1 CH4 S1 CH3 S1 CH2 HI S1 CH7 S1 CH6 S1 CH5 HI S N 1 CH7 S N 1 CH6 S N 1 CH5 HI S2 TR00 LO S1 TROO S0 TR00 S5 TR00 LO S4 TR00 S3 TROO S2 TROO HI S7 TROO S6 TROO S5 TROO HI S N 1 TROO S N 2 TROO S N 3 TROO HI 31 30 TRIGGER TIME Fig 3 13 Group Data Format In the Group Event Description Word yellow in the figure above the following fields are shown Bit 29 20 Start Index Cell of DRS4 related to this event Bit 17 16 sampling frequency 00 5GS s 01 2 5GS s 10 1GS s 1 used _ Bit 12 tr 0 signal not present in readout 1 TRn signal present in readout Bit 11 0 Size related to channel 0 7 number of 32 bit words when each channel has 1024 samples Size Ch 0 7 is 0xC00 If readout of TRn is disabled data related to such channel light blue in figure above are not present in the event if readout of TRn is enabled data size related to such channel is Size TRn Size Ch 0 7
47. imum value for the post trigger is Ox3FF Number of pages Page NPO Filename 54 47 00103 09 V 1742x MUTx 06 V1742 REV6 DOC Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 NOTE This setting is valid from Firmware revision 0 3 on For previous revisions the register is over 7 bits and the maximum value for the post trigger is 0x7F 5 29 Front Panel I O Data 0x8118 r w Bit Function 15 0 Front Panel I O Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outputs 5 30 Front Panel I O Control 0x811C r w Bit Function 0 I O Normal operations TRG OUT signals outside trigger presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see 5 26 12 Test Mode TRG OUT is logic level set via bit 14 14 12 TRG OUT Test Mode set to 1 0 TRG OUT Test Mode set to 0 13 8 reserved 00 General Purpose 01 Programmed 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field 5 0 LVDS I O 15 12 are inputs 1 LVDS I O 15 12 are outputs 4 0 LVDS I O 11 8 are inputs 1 LVDS 11 8 are outputs 3 0 LVDS I O 7 4 are inputs 1 LVDS I O 7 4 are outputs 2 0 LVDS 3 0 are inputs 1 LVDS 3 0 are outputs
48. increased if also TRO and or TR1 channels are sampled in the acquisition of the analog inputs The module V1742 features a PLL for clock synthesis with a selectable internal or external reference clock source Multi board synchronization can be done by driving a clock on CLOCK IN input allowing all DRS4s to run synchronously with this external reference All analog inputs will be sampled at the same time without time drift allows high resolution timing and time analysis across multiple V1742 The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer D32 32 64 bit Block Transfer BLT MBLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The board houses a daisy chainable Optical Link able to transfer data at 80 MB s thus it is possible to connect up to 8 ADC boards 256 16 ADC channels to a single Optical Link Controller Mod A2818 Optical Link and VME access are internally arbitrated Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 Table 1 1 Mod V1742 versions Model Code SRAM Memory Form factor V1742 WV1742BXA
49. ister allows to overwrite the rotary switches settings its setting is enabled via VME Control Register see 5 34 The used addresses are 31 24 23 1615 0 OFFSET A32 software ADER H ADER L relocation 31 2423 1615 0 OFFSET A24 software lt ADERL relocation Fig 3 19 Software relocation of base address Data transfer capabilities The board supports D32 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST Events readout 3 13 1 Sequential readout The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0x0000 0x0FFC The events are readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is compl
50. itch Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 14 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 32 2 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 elk WT I GE E 1 8 1 en qer ed Hi 1 Fig 2 6 Rotary and dip switches location NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 15 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 7 Technical specifications table Table 2 3 Mod V1742 technical specifications 1 unit wide VME module 32 channels MCX 50 Ohm Single ended Input range 1 Vpp Bandwidth gt 500MHz Programmable DAC for Offset Adjust x ch adjustment range 1V Programmable 5 2 5 or 1GS s MCX 50 Ohm fast local trigger TRO for ch0 15 TR1 for ch16 31 and high resolution timing reference Based on DRS4 chip Switched capacitor ADC 1024 storage cells per channels simultaneously sampled at 5 2 5 195 5 selectable on all channels
51. lename Number of pages Page 00103 09 1742 06 V1742_REV6 DOC 54 24 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 32 2 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 6 Event structure An event is structured as follows Header four 32 bit words Data variable size and format The event can be readout either via VME or Optical Link data format is 32 bit word 31 30 29 28 27 26 25 2423 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87654 3 2 1 o 1 o0 1 0 TOTAL EVENT SIZE LWORDS BOARDID GR MASK EVENT COUNTER EVENT TIME TAG GROUP 1 EVENT DESCRIPTION WORD GROUP 1 CHANNEL DATA n GROUP 1 TRIGGER TIME GROUP 3 EVENT DESCRIPTION WORD e a GROUP 3 CHANNEL DATA tc GROUP 3 TRIGGER TIME Fig 3 12 Event Format The Header is composed by four words namely Size of the event number of 32 bit words Board ID GEO 16 bit pattern latched on the LVDS as one trigger arrives Group Mask 1 Groups participating to event ex GR2 and GR3 participating Gr Mask OxC this information must be used by the software to acknowledge what Group the samples are coming from the first event contains the samples from the Group with the lowest n
52. ms a FPGAs global reset which restores the FPGAs to the default configuration It initializes all counters to their initial state and clears all detected error conditions 3 10 2 gt Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a write access to Software Clear Register see 5 48 or with a pulse sent to the front panel Memory Clear input see 3 8 NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 29 2015 for Discovery PRELIMINARY type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 10 3 Timer Reset The Timer Reset allows to initialize the timer which allows to tag an event The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input see 3 8 3 11 VMEBus interface The module is provided with a fully compliant VME64 VME64X interface see 1 1 whose main features are EUROCARD 9U Format 1 1 and J2 P2 with either 160 pins 5 rows or 96 rows connectors A24 A32 and CR CSR address modes 032 BLT MBLT 2eVME 2eSST data modes write capability CBLT data transfers RORA interrupter Configuration ROM 3 11 1 Addressing capabilities 3 11 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four r
53. munication at low level read and write access CAENVMELib and CAENComm libraries must be already installed on the host PC before installing the CAENDigitizer however both CAENVMELib and CAENComm libraries are completely transparent to the user WaveDump is a Console application that allows to program the digitizer according to a text configuration file that contains a list of parameters and instructions to start the acquisition read the data display the readout and trigger rate apply some post processing such as FFT and amplitude histogram save data to a file and also plot Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742_REV6 DOC 54 34 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 the waveforms using the external plotting tool gnuplot available on internet for free This program is quite basic and has no graphics but it is an excellent example of C code that demonstrates the use of libraries and methods for an efficient readout and data analysis NOTE WaveDump does not work with digitizers running DPP firmware The users who intend to write the software on their own are suggested to start with this demo and modify it according to their needs For more details please see the WaveDump User Manual and Quick Start Guide Doc nr UM2091 GD2084 Fig 4 2 WaveDump outpu
54. on notes and user manual available at www caen it website path Products FrontEnd VME Digitizer V1742 then follow the instructions for installation and usage NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 53 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 WARNING in case of programming failures the board can store two firmware versions called STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the JP2 jumper see 2 6 which can be placed either on the STD position left or in the BKP position right Please contact CAEN at support frontend caen it for instructions in order to restore the backup image Once the board is successfully powered with backup firmware the standard firmware image can be reprogrammed NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 54
55. otary switches see 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range 0 000000 lt gt 0 000 24 mode 31 24 23 1615 0 sw4 Sws Fig 3 16 24 addressing 0x00000000 lt 0xFFFF0000 A32 mode 31 24 23 1615 0 OFFSET n I SW2 5 3 SW4 5 5 Fig 3 17 32 addressing Base Address of the module is selected through four switches see 2 6 then it is validated only with either a Power ON cycle or a System Reset see 3 10 3 11 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23 19 of CR CSR space indicating the slot number in the crate the recognized Address Modifier for this cycle is 2F This feature is implemented only on versions with 160pin connectors NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 30 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 12 3 13 NPO 31 2423 19118 1615 0 GEO OFFSET Fig 3 18 CR CSR addressing 3 11 1 3 Address relocation Relocation Address register see 5 42 allows to set via software the board Base Address valid values 0 Such reg
56. pacitor Digitizer 3 5 2 Index sampling correction Revision date 06 02 2012 PRELIMINARY Revision 6 It has been observed a fixed pattern noise introduced by the DRS4 over the last samples 30 samples in a waveform therefore the index sampling correction is necessary this correction actually reduces this noise thus anytime the best accuracy is 2200 wave_ch0_oft amp indsampcorr txt 2150 2100 ADC counts 2050 2000 1950 0 200 400 600 800 1000 Samples Fig 3 7 Sampled waveform and noise histogram after index sampling correction NPO Filename 00103 09 V 1742x MUTx 06 V1742 REV6 DOC Occurrence 350 300 F 250 F 200 150 100 F required the last 30 samples should be rejected histo ch0 off amp indsampcorr txt 1950 2000 2050 counts 2100 2150 Number of pages Page 54 22 2200 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 3 5 3 Time correction The sampling sequence is handled by the DRS4 through 1024 physical delay lines the unavoidable construction differences between such delay lines must be compensated through a time calibration The following figures show the fast trigger signal TRO sampled by the DRS chip related to Group 0 and 1 and the
57. pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 44 ols for Discovery PRELIMINARY Ne type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 There are three ways to write the content of the Configuration Register Normal Write at address 0x8000 the content of the register is fully overwritten by the new data Bit Set Mode at address 0x8004 writing 1 in one bit will set that bit writing 0 leaves the bit unchanged Bit Clear Mode at address 0x8008 writing 1 in one bit will clear that bit writing 0 leaves the bit unchanged The use of the Bit Set Clear modes are recommended when concurrent processes can access the register this prevents a process to operate on the content of the register while another process has already changed it The read access to the Control Register can be done at 0x8000 address 5 17 Group Configuration Bit Set 0x8004 w Bit Function 31 0 Bits set to 1 means that the corresponding bits in the Group Configuration register are set to 1 5 18 Group Configuration Bit Clear 0x8008 w Bit Function 31 0 Bits set to 1 means that the corresponding bits in the Group i Configuration register are set to 0 5 19 Buffer Organization 0x800C r w Bit 31 0 Function reserved always set to 0 5 20 Custom Size 0x8
58. patible TRO is common to group 0 ch 7 0 and 1 ch 15 8 TR1 to group 2 ch 23 16 and 3 ch 31 24 TRn signals can be used as external triggers see 3 7 Moreover they can be also sampled into the DRS4s analog memory buffers for applications where high resolution timing and time analysis with a common reference signal like a trigger or system clock is required this is achieved through the Configuration Register Signal TRn Readout Enable bit setting see 5 16 allows to store TRO input with samples coming from group 0 and 1 and TR1 with those from group 2 and 3 In order to be sampled the TRn signals must be compatible with the DRS4 chips input dynamics 1V therefore on V1742 mezzanine 0 PCB the TRn signals are attenuated by a factor 3 on V1742 mezzanine Rev 1 PCB the TRn signals are attenuated by a factor 2 therefore if TRn signals larger than 2V are going to be sampled an external attenuator shall be used To properly handle bipolar signals and also unipolar positive or negative signal a 16 bit DAC allow you to add a DC offset to TRn offset value can be programmed via Group n TR DC Offset register see 5 15 When the TRn signals are used as trigger they are processed by an internal comparator whose threshold can be programmed via Group n TRn Threshold register see 5 14 as the threshold is exceeded the FPGA triggers the DRS4 s and samples digitizing takes place The trigger signals can be sense
59. r other quantities of interest can be saved to output files or plotted using gnuplot as an external plotting tool exactly like in WaveDump NOTE so far DPP Control Software is developed for Mod x724 and Mod x720 digitizer series CAEN Electronic Instrumentation Settings Mode Channel Channel 0 7 8 Basic Advanced General Settings Channel Enabled Copy Settings DC Offset 4012 InputDigital Gain gt Decimation gt Pulse Polarity POSITIVE v Trigger and Timing Filter Energy Filter DPP PHA Control Software x IE onuplot graph Energy Histogram Decay Time Threshold Rise Time Smoothing Factor Flat Top Delay b ED Baseline Mean Holdoff Trapezoid Peaking Delay RT Discrimination Window Peak Mean B Enabled Width Baseline Holdoff Peak Holdoff 4000 ADC channels 8165 49 7022 17 NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742_REV6 DOC 54 36 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 Fig 4 5 DPP Control Software Graphical User Interface and Energy plot NPO Filename Number of pages Page 00103 09 V1742x MUTx 06 V1742 REV6 DOC 54 37 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Man
60. required This signal opens write switches in all 9 sampling channels where the differential input signals are sampled 1024 sampling capacitance cells per channel After being started the domino wave runs continuously in a circular fashion after the end of the ring samples are over written until decoupled from the write switches by a trigger signal which freezes the currently stored signal in the sampling capacitance cells Subsequently the cells are multiplexed into the 12 bit ADCs whose output are stored by the FPGA into the Digital Memory Buffer and ready for readout in the shape of events data A 16bit DAC allow to add up to 1V DC offset in order to preserve the full dynamic range also with uni polar positive or negative input signals Filename Number of pages Page 17 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 x 16bit 8 DRS4 i l DIGITAL Analog Input G FPGA MEMORY BUFFER TRn Input 3 3 NPO 16bit Fig 3 2 Input diagram Detailed documentation of the DRS4 is available at http drs web psi ch TRO and TR1 Inputs The module features two fast trigger inputs TRO and TR1 with extended level amplitude TTL NIM com
61. t 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected 5 24 Acquisition Status 0x8104 r Bit Function 8 Board ready for acquisition PLL and ADCs are synchronized correctly 0 not ready 1 ready This bit should be checked after software reset to ensure that the board will enter immediately run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur 7 PLL Status Flag see 2 5 1 0 PLL loss of lock 1 2 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see 5 39 6 PLL Bypass mode see 2 5 1 0 No bypass mode 1 Bypass mode 5 Clock source see 2 6 0 Internal 1 External 4 EVENT FULL it is set to 1 as the maximum nr of events to be read is reached 3 EVENT READY it is set to 1 as at least one event is available to NPO 00103 09 V 1742x MUTx 06 Filename Number of pages Page V1742 REV6 DOC 54 46 PRELIMINARY Tools for Discovery Revision date Revision Document type Title User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 readout 0 RUN off RUN on 1 0 reserved 5 25 Software Trigger 0x8108 w Bit Function 31 0 A write access to this location generates a trigger
62. t give error messages out but it will not run properly Group n ADC Configuration 0x1n9C r w Bit 31 0 Function reserved DRS4 temperature 0x1nA0 7 0 DRS4 temperature from 0 C to 127 C Bit Function Filename Number of pages Page 1 00103 09 V1742x MUTx 06 V1742_REV6 DOC 54 4 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 10 Channel n DAC SEL 0x1nA4 r w Bit Function 3 0 DAC Channel index for readout from 0x0 to 0x7 For example in order to read the channel 15 DAC Value a write access to address 0x11A4 with value 0x7 channel 15 is channel 7 of group 1 must be performed and then a read access to address 0x1198 5 11 Group n Channel Trigger Mask 0x1nA8 r w Bit 31 0 Function reserved 5 12 Memory Calibration Tables Enable 0x1nCC Bit Function 0 1 Memory Calibration Tables ENABLED 0 Memory Calibration Tables DISABLED This register allows to access the memory location where calibration data are stored see S 3 5 CAUTION before writing this register it is necessary to verify that SPI Bus Busy Flag in the Status register S 5 4 is 0 and in any case its use is reserved to experienced Users since a wrong value written in the Memory Calibr
63. t it will not run properly 5 15 Group n TR DC offset 0x1nDC Bit Function 15 0 DC Offset The TRn signal offset can be set by a programmable 16bit DAC One TRn signal is common to two groups therefore for example write access to either 0x10DC or 0x11DC leads to the same setting for TRO input If you are sending bipolar or negative signal to TRn you have to set the TRn Offset to 0x1000 default setting if you are sending positive signal to TRn you have to set the TRn Offset to 0x4000 TRn setting examples trigger level on half voltage swing Mezzanine PCB Rev 1 ECL signal on TRn TRO DC Offset 0x55A0 write 0x55A0 at address 0x10DC or Ox11DC TRO Threshold 0x6666 write 0x6666 at address 0x10D4 or Ox11D4 DC Offset 0x55A0 write 0 55 0 at address Ox 12DC or Ox 13DC TR1 Threshold 0x6666 write 0x6666 at address 0x12D4 or Ox13D4 NIM signal on TRn TRO DC Offset 0x8000 write 0x8000 at address 0x10DC or Ox11DC TRO Threshold 0x51C6 write 0x51C6 at address 0x10D4 or 0x11D4 TRI DC Offset 0x8000 write 0x8000 at address 12DC 0x13DC TR1 Threshold 0x51C6 write 0x51C6 at address 0x12D4 or Ox 13D4 Negative signal on TRn V 0 400mV TRO DC Offset 0x8000 write 0x8000 at address 0x10DC or Ox11DC TRO Threshold 0x5C16 write 0x5C16 at address 0x10D4 or 0x11D4 TRI DC Offset 0x8000 write 0x8000 at address 0x12DC Ox13DC TRI Threshold
64. t waveforms CAENScope is a fully graphical program that implements a simple oscilloscope it allows to see the waveforms set the trigger thresholds change the scales of time and amplitude perform simple mathematical operations between the channels save data to file and other operations CAENscope is provided as an executable file the source codes are not distributed NOTE CAENScope does not work with digitizers running DPP firmware and it is not compliant with x742 digitizer family For more details please see the CAENScope Quick Start Guide GD2484 Toots jor Discovery Tne ti 9 a7 t O CAEN Q e s r3 acini RECORD o Max butters was file format me mmm Ca Com uen 2 usn AsCH w x Folder AUTO TRIG RISING EDGE Fig 4 3 CAENScope tab CAENUpgrader is a software composed of command line tools together with a Java Graphical User Interface for Windows and Linux OS CAENUpgrader allows in few NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 35 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5G
65. the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 50 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 41 Base Address and Control 0xEF0C Bit Function Allows to set up the board for daisy chaining 00 disabled board 9 8 01 last board 10 first board 11 intermediate These bits contain the most significant bits of the MCST CBLT 7 0 address of the module set via VME i e the address used in MCST CBLT operations 5 42 Relocation Address OxEF10 r w Bit Function These bits contains the A31 A16 bits of the address of the module 15 0 it can be set via VME for a relocation of the Base Address of the module 5 43 Interrupt Status ID OxEF14 r w Bit Function 31 0 This register contains the STATUS ID that the module places on the VME data bus during the Interrupt Acknowledge cycle 5 44 Interrupt Event Number 0xEF18 r w Bit Function 9 0 INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events gt INTERRUPT EVENT NUMBER 5 45 BLT Event Number 0xEF1C r w Bit
66. transfer rate up to 80MB s TX RX daisy chainable NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742 REV6 DOC 54 13 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 2 5 Other front panel components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Colour Function DTACK green VME read write access to the board CLK_IN green External clock enabled NIM green Standard selection for CLK I O TRG OUT TRG IN S IN TTL green Standard selection for CLK I O TRG OUT TRG IN S IN LINK green yellow Network present Data transfer activity PLL green The PLL is locked to the reference clock PLL_BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL_LOCK LED is turned off RUN green RUN bit set see 5 24 TRG green Trigger accepted DRDY green Event data depending on acquisition mode are present in the Output Buffer BUSY red All the buffers are full OUT_LVDS green Signal group OUT direction enabled 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Set the VME base address of the module SW3 CLOCK SOURCE Type Dip Switch Function Not Used SW1 FW Type Dip Sw
67. ual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 5 VME Interface The following sections will describe in detail the board s VME accessible registers content Registers whose name begins with Group n are referred to channel groups with index in the address going from 0 to 3 each group is composed by eight subsequent channels A N B bit fields that are not described in the register bit map are reserved and must not be over written by the User 5 1 Registers address map Table 5 1 Address Map for the Model V1742 REGISTER NAME ADDRESS ASIZE DSIZE MODE H_RES S_RES CLR EVENT READOUT BUFFER 0x0000 0x0FFC A24 A32 A64D32 X X X Group n Channel THRESHOLD 0x1n80 A24 A32 D32 R W X X Group n STATUS 0x1n88 A24 A32 D32 X X Daughter board FW revision Ox1n8C A24 A32 032 R Group n BUFFER OCCUPANCY Ox1n94 A24 A32 D32 X X X Group n Channel DC offset 0x1n98 A24 A32 D32 R W X X Group n DAC SEL 4 24 2 032 R W X X DRS4 n Temperature Ox1nAO A24 A32 D32 R X X Group n CHANNEL TRIGGER ENABLE MASK Ox1nA8 A24 A32 D32 RW X X Memory Calibration Tables ENABLE OxinCC A24 A32 D32 R W X X Memory Calibration Tables DATA Ox1nDO A24 A32 D32 X X Group n TR THRESHOLD 0 1 4 A24 A32 D32 R W X X Group n TR DC offset Ox1nDC A24 A32 032 R W X X Group CONFIGURATION 0x80
68. umber Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see 5 20 Trigger Time Tag It is a 32 bit counter 31 bit count 1 overflow bit which is reset either as acquisition starts or via front panel Reset signal see 3 10 and is incremented at each sampling clock hit It is the trigger time reference Each group is composed by 8 analog channels group 0 channel 0 7 group 1 channel 8 15 etc and by the special channel TRn such signal is common to two groups it can be used as Local Trigger or digitized and stored with the data for high resolution timing analysis between the ADC channels and the TRn itself NPO Filename Number of pages Page 00103 09 V 1742x MUTx 06 V1742_REV6 DOC 54 25 Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 06 02 2012 6 TRO can trigger Group 0 and Group 1 and can be stored with data from Group 0 therefore the stored waveform will be labelled as 00 and with data from Group 1 therefore the stored waveform will be labelled as 01 TR1 can trigger Group 2 and Group 3 and can be stored with data from Group 2 therefore the stored waveform will be labelled as Tr12 and with data from Group 3 therefore the stored waveform will be labelled as Tr13 The part of an event related to each group has t
69. via software 5 26 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 0 reserved EXTERNAL TRIGGER ENABLE bit30 enables the board to accept the TRG_IN SW TRG ENABLE bit 31 enables the board to accept software trigger see 5 25 5 27 Front Panel Trigger Out Enable Mask 0x8110 Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 4 reserved 3 0 Group 3 trigger disabled 1 Group 3 trigger enabled 2 0 Group 2 trigger disabled 1 Group 2 trigger enabled 1 0 Group 1 trigger disabled 1 Group 1 trigger enabled 0 0 Group 0 trigger disabled 1 Group 0 trigger enabled This register bits 3 0 enable the groups to generate a trigger as the relevant TRn signal TRO for group 0 1 and TR1 for group 2 3 exceeds the set threshold see 5 12 EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG_OUT SW TRIGGER ENABLE bit 31 enables the board to broadcast a software trigger see 5 25 5 28 Post Trigger Setting 0x8114 r w Bit Function 9 0 Size of the post trigger window The register value sets the size of the post trigger window expressed in steps of about 8 5ns the max

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V1742 &amp; VX1742 User Manual

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V1742 & VX1742 User Manual