Home

User Manual

1. If you are designing a daughter board either DNSEAM NS or DINARI please see the relevant spec for the daughter board outline and mounting hole locations Reference designs with OrCAD schematics and PADS layout files are provided on request If you are designing a chassis for this board we provide top layer Gerber and DXF files by request Since these are the controlling documents for the board layout we recommend you design your chassis based on them We also provide the baseplate layout including all of the positions and sizes of the mounting holes Contact support dinigroup com to request these files v 2012 11 03 Page 57 The Dini Group DNV7F1A User Manual 3 25 POWER This section discusses the power requirements of the DNV7F1A 3 25 1 Power Headers There are two power headers on this board the 24 pin ATX header and the 6 pin PCI Express Graphics power header They are both in the north west corner of the board Both should be connected when the board is in use Any off the shelf ATX power supply rated for 300W or greater on the 12V rail is suitable for powering the DNV7F1A Please use a supply with single 12V rails Among many other vendors most Corsair branded supplies have this feature An appropriate ATX supply is shipped with each board 3 25 2 Estimating Power Draw Most of the power draw for the DNV7F1A comes from either the daughter boards or the user FPGA and is therefore application de
2. U0 1 CCUK A CONF i CONFIG CCLK A ccu DONE o Atti 0 19 DONE CONFIG PROGRAM j 21 FPGA TEMP PA EONFIECINIT A Mer PROGRAM B 0 0 FGA TE CFG FOCFGEVS INIT_BO DXN_O CFGBVS 0 _ AB2I CFG F0 GNDADC CONFIG M2 ALL AMO VREFP 0 LCFG FO CND LL AGO M20 0 T 10 M00 ve o 287 FPGA XADC VP R1850 MTO _0 2 1000pF _ R1851 VNO 50 yeceatt_o S 3 o Y21 VCCADC JTAG TC Y2 UL GNDADC JTAE TDO THE rck o E GNDADC 9 JTAG TDLA Tio IMS o 5 R10 JTAG 41 8y CPU we m T009 M10 veco 0 Ci203 1193 d 2 2uF 6 3V 20 CER 4TuF 6 3V 20 TANT 70mOhm XC7V2000TFHG1761_0 You can also read back the voltages on these pins the FPGA temperature and the VCCINT and VCCAUX voltages using IMPACT and the JTAG chain or by instantiating the XADC block in your design See Xilinx 7 Series FPGAs XADC User Guide UG480 for details on using XADC functionality within your design 3 29 LED REFERENCE LIST There are a lot of LEDs on the board This list describes them In general you can search for the text in the Meaning column or for the reference designator in the schematic to gain more knowledge about what makes them turn on and off REF DES COLOR
3. DII peo ux m i4 is Better hope you have DITE TERM in the receiving pina CKOUT2 G0 cFPGAD ice out SHIRE REOR 2 4 m vcc 01 z cus pd Hen Tw Bw son BES PLL Loss Indicator i 4 47 SYNTH INC GO 20 em R232 SYNTH DEC 18 m roy i SYNTH LoL 60 EU SYNTH LOL Gor SYNTH ALL nese mE X EKCENRGD A a LN SR Silkscreen Go 10L ne Hx za a ne Hir x 1 9mA he HE L 8 JP12 sua Iestall jumper for DE Coupling CGNIRORSE 4 rr ar OND vods c vyo ES iC Gop 5 QF NS0P600X800XS0 37N con sua 1x GD sua MAYEEGND EGHTHOR SE 2 nt Cik Gon Install jumper for si peration of 215126 input The synthesizer used is a high performance low jitter high precision clock generator chip the 515326 To change the clock frequency you can use the EMU software aloj x Y 0 000 rca 936A 0 000 _save tent Auto Scroll F Welcome to Enut RUTOCONNECT 7 9099989 Ethernet NoT FOUND CONNECTED TO BOARD 0211 DNU7 K10 1008025 Ethernet The clocks GO
4. Group Logic Emulation ASIC Verification Algorithm Acceleration User Manual DNV 7F1A DNV7F1A User Manual DOCUMENT PATH I work out 2012 11 02 DNV7F1A_manual_rev03 docx LAST SAVED BY Ivan Yulaev LAST SAVE DATE 2012 11 03 The Dini Group DNV7F1A User Manual Contents 1 INTRODUCTION 5 1 1 AUDIENCE AA 5 1 2 CONVENTIONS AA 5 1 3 RESOURCES TREES 5 2 QUICK START 8 2 1 STEPS TO FOLLOW 3 HARDWARE 18 3 1 OVERVIEW 3 2 VIRTEX 7 FPGA 3 3 CLOCK RESOURCES 3 4 NMB Bus 3 5 240 PIN 72 DIMM DDR3 CONNECTORS 3 6 DAUGHTER CARD CONNECTORS E ENNA 3 7 FPGA CONFIGURATION 3 8 3 9 3 10 3 11 USER LEDS 3 12 SPI FLASH 3 13 dide 3 14 USER CLOCK OUTPUTS 3 15 USER ASSORTED I O 3 16 USER SATA TT 48 3 17 USER SFP 3 18 GTX EXPANSION DNSEAM NS 3 19 USER PCI EXPRESS 3 20 USER USB 3 0 E E VE RA OE IE d Ta D VAR E o Ho 53 3 21 USER GTX SMAs 3 22 3 23 3 24 3 25 3 26 3 27 3 28 3 29 LED REFERENCE LIST 3 30 TESTPOINT REFERENCE LIST cineri reato adr mite rrt to pk lene ee E rere erg a
5. gt revision 3 5232 serial Cable DB9 to IDC cable O USB Stick containing user support package L USB Stick containing FPGA bit files and a shell script v 2012 11 03 Page 8 The Dini Group DNV7F1A User Manual O Packing foam Power supply PCI Express cable host adapter 2 1 2 Before power Take ESD precautions whenever handling board Place the board clear desk with static control padding You can use the silver colored bag the board comes wrapped in as a static control surface Make sure you neutralize the static in your fingers with the surface before every time you contact the board 2 1 3 Connect a system to host PC interface At least one host PC facing interface should be connected to allow the user to interact with the DNV7F1A These interfaces are described in this section GA PCle 6 5 5 2 1 3 1 Install the PCI Express adapter board in PCI Express slot optional During the course of your project if you intend to control the board using PCI Express then you should complete this step v 2012 11 03 Page 9 The Dini Group DNV7F1A User Manual The board fits into any 8x or 16x PCI Express slot Make sure the computer is powered off when you install the board into it There are two x4 cable connectors on the board You should use only the bottom one with the DNV7F1A because th
6. please see the relevant section further on in this chapter Any clock signal going into the FPGA must be terminated to function correctly This includes all in board clock resources For differential clocks it is usually sufficient to enable the DIFF TERM attribute on the IBUFDS element used for the clock input Make sure you enable DIFF TERM for all of the relevant clocks in your design 3 3 2 Global Networks The global clocks are high accuracy low jitter programmable synthesizers connected to user FPGA MRCC pins There is no set function for these clock networks They may be used to clock logic or any on board interface although in general dedicated clock sources are provided for all high speed interfaces 114 285 MHz 114 285 MHz 114 285 MHz Frequency Frequency Frequency _ Synthesizer GO lt Synthesizer G1 Synthesizer G2 Si5326 lt 515326 lop 4 515326 J J SMA SMA SMA 3 3 3 Clocks GO G1 G2 The clocks GO G1 and G2 are from a synthesizer that can produce any frequency from 2KHz to 700MHz with a 5Oppm tolerance or better They also have the option of being used with either a differential or single ended off board signal generator v 2012 11 03 Page 22 CLK Multiplier G0 PETIT E LVDS GND 5 EALA A CUI oF PGK 425 CUK L i panos ES Fase emg
7. 112 This allows the DNV7F1A to be used to prototype PCI Express IP The PCle interfaces comply with the PCI Express Cabling Specification and are compatible with Molex iPASS PCle cables other vendors are available v 2012 11 03 Page 51 The Dini Group DNV7F1A User Manual Each cable connection can be configured as an upstream or a downstream device changing between the two requires either adding or removing the optocoupler devices and adding removing the optocoupler bypass resistors The clock direction must also be changed once again by moving around SMD resistors By default both ports are configured as downstream connections If you know ahead of time what orientation you need contact the factory and we can make sure the board ships configured correctly Otherwise you ll need to find someone proficient in soldering SMD components to help you with this Each PCle interface has an associated REFCLK On the DNV7F1A a PLL jitter attenuator is used to filter the clock going to the FPGA There is an on board 100MHz clock source which is used to drive both the PLL and the cable REFCLK connection when the board is configured as an upstream device When the board is configured as a downstream device the PCle cable clock is connected to the PLL and thereby drives the FPGA The sideband signals are connected through optoisolators when the board is configured as a downstream device As a side effect all of the sideband signals have thei
8. 3 3V tolerant Only signal levels between GND and 1 8V should be applied to these headers v 2012 11 03 Page 47 The Dini Group DNV7F1A User Manual Silkscreen 1 8V Mictor Debug 59 2 Do Nor Connect 2 tae 4 MICTOR DEBUG MICTOR DEBUG CK WICTOR i 3 MTOR DEBUG 8 rom D Fig NWIETOR DEBUS T7 x LAV25 WICTORCDEBUE T V 10 12 WICTOR DESUG TS j IOUS Ti DOS 12 Maa WICTOR DESUG T V 12 Ha meron Dese IO19N Ti Dos 12 AWT MICTOR DESUS TE 13 4 u IO L19P T1712 AWS MICTCR DESUE IS i 15 18 yp WETOR DESUS ST AU28 TENTHINCH W 7 18 20 WMICTOR DEBUG Z2 3 LAV28 ENTHINCECIO UZ yu 1 20 22 WICTORCDEBUG 7 OLAN TI SROC 12 ates MICTOR DEBUG CRT zi 2 S IO L12P TI MRCC 12 AU27 TENTHINCH 10 05 24 26 WICTOR DEBUG Z5 12 PALE 25 2 8 ID I MRC PE E MRI LAP27 TENTANCH OW a 30 32 WICTOR DESUG 27 n L AR28 TENTHINCH 10 08 V 2 34 WICTORCDEBUG 2 B i H ai LAP28 WICTOR DESUG 2I 36 38 WICTOR DESUG S Wema DERE cz 3700 po 38 H Al 44 x LAP25 WICTORCDEBUC M an weri E AR25 MICTOR DEBUG 25 GND GND em AN GND GND H AN28 MICTOR DESUG 27 787004 2 n DEBUG Za CON
9. CPU executes in place address OxF60000 of the SPI device In this case the SPI device is an ATMEL data flash The data flash contains code that initializes DRAM and loads the last 512KB of memory from the data flash into DRAM The last 512KB of flash contains a u boot bootloader image When u boot runs it reads a set of environment variables off the flash It runs the u boot command defined by the bootcmd variable That command will copy the entire contents of the data flash image from address of the data flash to address 0x2000000 of DRAM At address in the data flash is a compressed linux binary image u boot uncompresses the image and jumps to it U boot can pass a single string of information to the linux image called the boot arguments The value of these boot arguments can be modified using u boot environment variables Linux boots setting up all the devices including NAND flash The NAND flash shows up as four MTD block devices representing four different regions in the NAND flash As the last step of booting it mounts a JFFS2 file system from one device specified in the boot arguments Before starting a shell for the user linux will run a shell script on the filesystem called startup sh This script loads the software that Dini Group wrote that controls the FPGAs and other functions of the board This program is called DiniCmos and runs in the background You don t need to worry about it See the Emu Manual pdf do
10. D Fi ga ded 64 4 66 41 EMU HOST SOFTWARE 66 v 2012 11 03 Page 3 The Dini Group DNV7F1A User Manual 4 2 4 3 4 4 4 5 5 REFERENCE DESIGN WRITING YOUR OWN SOFTWARE Dean doeet ode dete eee de e VA eade ea re duda 72 How EMULIB WORKS MARVEL ENVIRONMENT MORE INFORMATION 5 1 NMB SPACE MAANA 81 5 2 el Iu ce aaier veaa kaza aaae Aae eta PE 82 6 nn 83 6 1 GENERAL PROCEDURE 7 ORDERING r 84 7 1 PARTNUMBER Ya Ia seta tial te AAA aaa a WA 7 2 How ORDER 7 3 BOARD OPTIONS 74 COMPLIANCE INFORMATION 8 TATA IETT 85 v 2012 11 03 Page4 The Dini Group DNV7F1A User Manual 1 INTRODUCTION Welcome to the DNV7F1A FPGA based ASIC Prototyping Platform This manual will assist in setting up using and understanding the hardware aspects of this product 1 1 Audience This product is marketed and sold to engineers who are familiar with circuit board design physically probing AC waveforms programming FPGAs wiring HDL code reading device data sheets reading C source code and writing softwa
11. G1 and G2 can also be set to distribute a signal from an external source Note that the Si5326 cannot accept input frequencies lower than 2kHz For very low input frequencies you may consider using the user FPGA SMA inputs described in section 3 3 4 3 3 4 User FPGA SMA inputs There is a single pair of AC coupled SMAs connected to an MRCC clock input pair on the user FPGA v 2012 11 03 Page 23 The Dini Group DNV7F1A User Manual 93222 gets level translated and muxed within CFPG to the outside world uu has no purpose other OSC SATA FS0 1 than vo provide CUCTO QCONFIG AR Sock Engen OSC SATA FSI 18 CEPGA User FPGA Osc SATA DECREASE IO 0 VRN 15 IO LTP TO ADOP 15 IO LIN TO ADON 15 IO L2P TO ADSP 15 IO L2N TO 15 IO L3F TO DOS ADIP 15 IO L2N TO DOS ADIN 15 IO L4P TO 15 IO LAN TO 15 IO L5P TO ADSP 15 IO L5N TO ADSN 15 IO L6P TO 15 IO LEN TO VREF 15 IO L7P T1 2 15 IO L7N Tf ADZN 15 IO LEP T1 AD 0P 15 IO LEN T1 AD10ON 15 IO 19 Tt DOS AD3P 15 IO L9N TT DOS AD3IN 15 IO LIOP TT ADTIP 15 IO L10N T1 ADTIN 15 IO L 1P T1 SRCC 15 IO L1IN Tf SRCC 15 IO L12P T1 MRCC 15 IO L12N MRCC 15 IO L13P T2 MRCC 15 IO L12N T2 MRCC 15 IO L14P T2 SRCC 15 IO L14N T2 SRCC 15 IO L15N T2 DOS ADV 15 IO L16P T2 A28 15 IO LI7P T2 A26 15 IO L17N TZ A25 15 IO L18P T2 A24 15 IO L18N TZ A23 15 IO L19P T3 A22 15 AOA TT There is n
12. I O interface that is required or to design their own Three DDR3 sockets red rectangles are on the board to provide bulk memory for use in the FPGA You can use standard off the shelf laptop memory SODIMM or you can use one of the many memory technology DIMMs that the Dini Group provides Getting data on and off the board is accomplished through the Marvell CPU It provides USB Ethernet PCI Express interfaces It connected to the user FPGAs through the NMB interface which provides an easy to use 20 30MB link to the user FPGA A high speed PCI Express only NMB solution is also available if greater bandwidth is required up to 380MB s Contact Dini Group support for more information The standard NMB interface inside the FPGA and on the host PC is v 2012 11 03 Page 19 The Dini Group DNV7F1A User Manual very simple because all of the software and hardware between has already been designed proven and optimized 3 2 Virtex 7 FPGA The Virtex 7 FPGA provides the latest features largest sizes and fastest speeds from Xilinx 3 2 1 Stuffing Options Below there is a table that describes the major differences between the available FPGAs Only FPGAs that Xilinx sells in the 1761 FF FFG FH FHG packages are compatible with this board FPGA Flip flops Equivalent All Board 25x18 Memory Grades ASIC Gates Features multipliers bits VX330T 1 2 3 408 000 14 1M 1 120 27M V585T 1 2 3 728 400 4 2M 1 260 28 6M VX485
13. MEANING DS1 GREEN reserved DS2 RED MV78200 Core Voltage Failure DS3 RED MV78200 uncore voltage failure DS4 GREEN MV78200 SATA1 activity DS5 RED MV78200 software reset asserted DS6 GREEN MV78200 SATAO activity DS7 RED Firmware not configured DS8 RED 2 8V supply failure DS9 RED POR reset asserted DS10 GREEN Configuration FPGA Status DS11 RED Front panel logic reset asserted DS12 GREEN Configuration FPGA Status DS13 RED Device USB overcurrent DS14 GREEN Configuration FPGA Status DS15 RED User FPGA Core voltage failure DS16 RED 5 0V failure from ATX supply v 2012 11 03 Page 62 DNV7F1A User Manual The Dini Group DS17 RED MV78200 NAND flash busy DS18 GREEN Configuration FPGA Status DS19 RED Configuration FPGA core voltage failure DS20 RED 2 5V clock power failture DS21 GREEN Configuration FPGA Status DS22 RED Configuration FPGA Status DS23 GREEN MV78200 to configuration FPGA link active DS24 RED G2 synthesizer loss of lock DS25 RED G1 synthesizer loss of lock DS26 RED GO synthesizer loss of lock DS27 RED MV78200 lost connection to configuration FPGA DS28 RED MGTAVCC Configuration FPGA failure DS29 RED MGTAVTT configuration FPGA failure DS30 RED 1 8V power failure DS31 RED DIMM power failure DS32 BLUE Configuration FPGA DONE configured DS33 RED MV78200 V1 failure DS34 RE
14. Vivado software However it has been modified The modifications allow the use of dual rank DIMMs and also set some parameters automatically such as RAS and CAS latencies and total DIMM density Some of the signals that are connected between the SODIMM connector and the FPGA are not used by MIG These include the SODIMM NC no connect pins the upper two address pins and the EVENTn pin If you want to use MIG you should use the HDL files produced by MIG and use the UCF file provided by Dini Group removing the unused signals v 2012 11 03 Page 27 The Dini Group DNV7F1A User Manual 3 5 2 IO Standards The DIMM interface is voltage selectable When using DDR3 memory it is suggested to use the 1 5V IO voltage When using this voltage signals to the SODIMM should be of the IO Standard SSTL15 T DCI DIFF_SSTL15 SSTL15 or LVCMOS15 The necessary board features to make SSTL work properly are provided See the sample UCF files provided with the MainRef example design for details See Xilinx UG586 for exact guidelines on which signaling standards should be used for which pins The pin is also voltage selectable It will be the same voltage as the rest of the DIMM There are some LED signals on the FPGA that are connected to the DIMM bank The IOSTANDARD attribute of these signals must be changed to match the voltage of the DIMM The IIC signals SDA and SCL are fixed at 1 8V and should use a 1 8V standard 3 5 3 Voltage S
15. in each section Please see the Virtex 6 user guide BUFR for the behavior of these modules DCM IDDR IDELAY ISERDES MMCM ODDR ODELAY OSERDES Core These words refer interchangeably to HDL code IP Verilog VHDL Design DCI Digitally controlled impedance It refers to the ability of the FPGA to output optimally terminated signals DIFF TERM Attribute that can be set on differential inputs to differentially end terminate them DLL Delay locked loop PLL Phase locked loop MMCM something something clock manager These words are incorrectly used interchangeably in this guide Usually means double data rate meaning that a signal s value is significant on both rising and falling edges of a clock Sometimes this guide also uses DDR to refer to DRAM just to add confusion DRIVE attribute This refers to the ability of the FPGA to produce a variety of output Drive strength impedaces on its 1 0 v 2012 11 03 Page 85 The Dini Group DNV7F1A User Manual FPGAQ These words are used interchangeably to refer to the controller FPGA on Config FPGA the DNV7F1A which is not generally available for user designs NMB Bridge Spartan GND This refers to both a net on the DNV7F1A and to the absolute potential of Ground that net at any given time When an absolute voltage is given in this manual it should be interpreted as a voltage relative to this net IOSTANDARD attribute This is an attribute of the 1 0 buffer primitive
16. interact with the mounted filesystem v 2012 11 03 Page 38 The Dini Group DNV7F1A User Manual 3 8 4 DEV Bus NAND The root file system of the Linux installation is contained on the NAND Flash device connected to the Marvell s device bus The NAND is 256MB in size with the first 100MB already assigned to the Linux installation This memory space can be used for storing a few configuration bitfiles or other data 3 8 5 USB The Marvell device natively provides a USB host and peripheral device The two media devices are managed by Linux You are not expected to interact directly with the host ports Instead when a device is detected Linux automatically mounts the devices as storage devices with filesystems They can then be interacted with as a file based device v 2012 11 03 Page 39 The Dini Group DNV7F1A User Manual 4e vio faa 72 2 So N ai N gt gt The single host interface is intended to be used as a connection to a host PC that will be used with the provided EMU software You are expected to use the EMU controller library to interact with this device 3 8 6 Bus Temperature Sensors The temperature sensors for the user FPGAs for the Marvell processor and for the config FPGA are connected to the Marvell s two wire serial interface The installed software will poll these IIC interfaces and measure the temperature of the FPGAs If the FPGAs are not within a specified te
17. is more complicated 12 Type this command reboot It is important that you use the reboot command and do not simply power cycle the board If you power cycle the board then the SPI flash may not get written completely due to write buffering 4 5 More Information The Emu manual has more and possibly more up to date information on the MV78200 environment and how to perform firmware upgrades on your board You can find it online at http www dinigroup com product data DNV7F1A files Emu Manual pdf v 2012 11 03 Page 80 The Dini Group DNV7F1A User Manual 5 REFERENCE DESIGN FPGA reference code is provided in the Customer Support Package at FPGA Reference Designs boards dn0247 dnv7f1a MainRef A very large portion of the design is contained in generic HDL modules which can be found in FPGA Reference Designs common Much of this generic Verilog HDL code can be very useful in writing custom designs 5 1 NMB Space Map The upper 8 bits of the NMB address select the FPGA Ox00 FPGA A which is the only user FPGA on this board This is true for all NMB designs it is not specific to the MainRef example design The MainRef sample design implements the following memory spaces The underscore is to make the 64 bit addresses easier to read and should be omitted when entering addresses into software 0x00010000 00000000 BLOCKRAM 0x00020000 00000000 DRAM 0x00040000 00000000 INTERCON TEST CONTROLS 0x00080000 00000000 REGISTERS Th
18. matching guidelines in UG586 to determine what matching to expect Length reports are available by request 3 5 5 Clocking Clocking of the DIMM interface is accomplished by using the dedicated Si598 oscillator connected to the user FPGA bank 38 This clock should be used as the SYSCLK by the MIG core The dedicated DIMM oscillator provides a 200Mhz clock to the user FPGA it can also be re programmed to provide almost any frequency between 10 and 800MHz 3 6 Daughter Card Connectors The primary means of interfacing between the FPGA and external I O interfaces are through the three DINAR1 GPIO expansion connectors These are three high speed high density connectors on the top side of the board containing 150 single ended signals each 72 differential v 2012 11 03 Page 29 The Dini Group DNV7F1A User Manual This section will mainly cover the DNV7F1A specific features of these connectors For a general connector spec please see the DINARI Interface Specification available on the product USB media 3 6 1 1 O Electrical Each DINARI 1 banks connects to an FPGA bank The DINARI connectors fit into a single SLR column so the entire interface can be clocked using a BUFMR f ex when implementing a 64 bit wide memory interface The DINARI spec is followed completely by the DNV7F1A board Note that under no circumstances should any signal above 1 8V be driven into the DINARI header This includes 3 3V signals Voltage translation must be u
19. mnt ram o size 32M 7 Type the following command cd mnt ram 8 Get the update files from the Dini group website Put these files on the board If you have the board connected to an internet enabled network you can use the wget command wget http dinigroup com marvellfiles u boot db78200 MP bin wget http dinigroup com marvellfiles update uboot wget http dinigroup com marvellfiles uImage If you do not have access to the internet then you will need to use some other method to transfer files to the board You can use a USB key a network mount or any other Linux trick you know 9 Type this command chmod 500 update uboot 10 Type this command update uboot 11 Type this command diff new contents bin u boot db78200 MP bin v 2012 11 03 Page 79 The Dini Group DNV7F1A User Manual The file new contents bin contains the current contents of the SPI flash This command is to make sure that the update was written successfully to the SPI flash If this diff fails shows the files are different then something went wrong with the update and you should notturn off your board If you turn off the board at this time the board will never boot again and you will have to send it back to the factory for re programming 12 Was the diff clean If not then stop here 13 Type this command cat ulmage dev partition spi This command updates the Linux kernel If this command fails the recovery procedure is still possible but
20. pdf file Advanced users only may read the following section but typically should not attempt any of these procedures without contacting support dinigroup com first 4 4 9 1 Installing a kernel update To get the current version of the Linux kernel you can check the boot messages for this line Booting image at 02000000 Image Name Linux 2 6 22 18 Created 2010 04 02 1 27 51 UTC Image Type ARM Linux Kernel Image uncompressed Data Size 2840632 Bytes 2 7 MB Load Address 00008000 Entry Point 00008000 Verifying Checksum OK Check the Created date 1 Connect the serial terminal to the board 2 Power on the board You should see u boot boot messages in the terminal At some point u boot should print Hit any key to stop autoboot 3 At this step press any key You will then recieve a u boot prompt like this gt gt 3 Type this u boot command protect off 1 0 63 U boot will print this Un Protect Flash Sectors 0 63 in Bank 1 4 boot into linux by typing this u boot command boot v 2012 11 03 Page 76 The Dini Group DNV7F1A User Manual 5 Once linux is done booting you will receive a command prompt like this sh 6 Type the following command mount t tmpfs tmpfs mnt ram o size 32M 7 Type the following command cd mnt ram 8 Get the update files from the Dini Group website Put these files on the board If you have the board connected to an internet enabled network you can use the wget co
21. provided called Emu The Emu program is provided in source and as binaries on the user support package See the Emu User Manual for additional information on installing and using the Emu software The rest of this guide will assume you are using a Windows computer however you can also use v 2012 11 03 Page 12 The Dini Group DNV7F1A User Manual Linux If you are using Linux the instructions may be slightly different although the Emu program is cross platform and should operate in the same way irrespective of the host PC OS If you are using PCI Express then you need to install a PCI Express driver This can be done in Windows using the device manager The driver files are provided in the support package Host Software emu Drivers windows pci Windows should detect the Dini Group board when it is attached to the system and prompt you to help it locate a driver just have it find a driver in this location If you are using USB then you will need to install a USB driver Linux does not require a USB driver This can be done in Windows using the device manager The driver files are provided in the support package Host Software emu Drivers windows usb Ethernet does not require a driver 2 1 8 Selecting a board Run the provided emu program located in the user support package here Host Software emu App out gui win32 exe This window will appear v 2012 11 03 Page 13 The Dini Group DNV7F1A User Ma
22. provided software EMU to push data to the board over USB Ethernet and PCI Express then you are required to interface to NMB in your FPGA design v 2012 11 03 Page 25 The Dini Group DNV7F1A User Manual 3 4 1 Protocol You are expected to know nothing about the protocol of NMB and only interface to it using the provided HDL interface wrapper in your FPGA on one end and in the EMU C code on the other end This short section describes the implementation of the interface recommend you skip this protocol section It is useless to know anything here The NMB interface is a physically point to point connection from each FPGA to the configuration FPGA The point to point connection consists of 40 signal wires which are used as 20 LVDS pairs These pairs are further divided into 10 signals in each direction with 1 clock signals 1 control signal and 8 data signals The clock frequency of the interface is 1GHz 500 MHz clock with DDR capture The theoretical throughput is therefore 1GB sec in both directions simultaneously The protocol supports four channels demand mode bursts interrupts link detection some FIFO flags and more The data to from the FPGA is stored in buffers in the DRAM of the Marvell processor 3 4 2 User Interface An HDL module is provided in the support package here FPGA_Rererence_designs common NMB nmb_user_interface v See Documentation Manual Dini Buses User FPGA Design Manual pdf and Documentation Manual PC
23. set to another frequency via the Emu software HPCLK Clock Network Source Oscillator 200MHz Default LVDS Output 42 5V LDO dimm R1184 1183 Note that output enable pin pin 2 is ACTIVE HIGH S 4 7K ke 9 88 22 DMMCKOE GND Si 598FCA00012806 Vh 0 75 Vad 3 3 7 GTX Transceiver Reference Clocks All of the GTX interfaces have some form of REFCLK allocated for them by the DNV7F1A Usually this consists of either a selectable frequency oscillator the choices are usually relevant for the interface bit rate or an externally provided clock source f ex for the PCle downstream interface The REFCLK implementations are interface specific and are described in the relevant sections of this chapter 3 3 8 From the DINARI Interfaces The DINAR1 interface designates pairs for clocking the interface Please see the section that describes the DINAR1 interfaces 3 3 9 NMB The NMB interface includes one clock signal running at 50 or 100MHz This clock is free running and is not configurable It is received by the FPGA from the configuration FPGA 3 3 10 Generating clocks from FPGAs Clocks may be generated in an FPGA using a CMT PLL or other logic That means you can do all of your frequency generation in the FPGA if so desired 3 4 NMB Bus The NMB bus is the primary means you will use to get high quantities of data on and off the board If you want to use the
24. to control the board directly from a computer over USB then you should complete this step v 2012 11 03 Page 10 The Dini Group DNV7F1A User Manual Connect a USB cable from the host computer to the USB type B connector on the board If the board is plugged into PCI Express the computer that connects to the board with USB does not necessarily need to be the same computer 2 1 3 4 Connect MV78200 RS232 1 4 The MV78200 processor may be accessed via 5232 If you are using the board without a chassis interface with the header circled above otherwise use the top header on the front of the chassis The RS232 port provides a root shell within the Linux environment running on the CPU this may be used via DiniCMOS to configure FPGAs set clocks etc See the DiniCMOS documentation part of the Emu manual for more details In general this interface is not recommended for new users it is recommended to use of the Emu compatible interfaces listed earlier in this section 2 1 3 5 Connect FPGA JTAG This is just a JTAG connection to the user FPGA See section 3 23 This is if you want to configure the FPGA directly and talk to it over JTAG f ex for debugging with Chipscope 2 1 4 Connect power cables The DNV7F1A requires an ATX power header an EPS 8 pin CPU power and a PCle Graphics power cable to be attached to power the board These should all come from the same power supply It is recommended that the power supply use a s
25. to convert an 8 bit L VCMOS bus to the USB 1 1 2 0 differential pair CPU 33v USB Sideband and PHY SAAV 181 Rio 5 R203 OR al ULPI ttg has Vih min DL EBOLA Vih 49 80 U0 Sc usa G OE 1 ga USB G R307 33R US3 REFCEK 2 eK Hr usa G VDDIS 2 vec H 35 BLANK C217 G DATAT 34 3 T DATAZ 5 ir OSCCC2SOKS20KI20 AN Ts Ed CBA TSE Soars 3i DATA 2 USSG Rins 1K USB G vaus ERE parar veus Kuba q veus 5 319255 ou Use G DM Ee para 5 05876 0 USB G NT ID tt 1 J TT 39 DiR USE G RESETE 24 USB G RBIAS 22 USB CLKOUT RUIA WA USE G 12 RESETS RBIAS 470F CLKOUT CIROUT onto CC pin please 17 7 DNI 0 28 2 ahr R308 cates 1K Di from VEAT The USB 3 0 port is circled in red in the photo below v 2012 11 03 Page 53 The Dini Group DNV7F1A User Manual 3 21 USER GTX SMAs Three GTX channels each comprised of Rx Tx diff pairs are connected to SMA coaxial connectors on the board These have no specific intended function and can be connected to a wide variety of sourc
26. unreliable phase output 3 6 10 How to make a daughter card It is recommended that you start with one of the Dini Group daughter cards as a design template The ORCAD schematic and layout files are all provided on the Dini Group website for several daughter cards The DINAR1 OBS is a good starting point for a new daughter card design Please make sure to read and understand the DINARI spec before designing a daughter board 3 7 FPGA CONFIGURATION 3 7 1 SelectMAP High speed select map configuration is controlled by the ConfigFPGA and Marvell CPU FPGAs can be configured over Ethernet USB PCle from USB Flash Drives external SATA hard drives from onboard NAND Flash on the Marvell Processor and more See the EMU Manual for more information on these Configuration methods v 2012 11 03 Page 34 The Dini Group DNV7F1A User Manual 3 7 2 JTAG A standard JTAG header is provided to which a Xilinx Platform USB JTAG cable or other JTAG cable can be connected All seven FPGAs are on a single JTAG chain and can be configured using the Xilinx Impact software This JTAG port can also be used for JTAG based FPGA debug 3 8 Marvell CPU The clock networks off board 1 0 and configuration is controlled by a Marvell ARM CPU This section describes the hardware attached to the Marvell processor For information about programming the Marvell and the software running on the Marvell see the software section of this manual and the Emu User Man
27. 03 Page 43 The Dini Group DNV7F1A User Manual Please use the below pins on the user FPGA for this interface 3 11 USER LEDS Pin Function U0 AM38 RS232 RX fpga input 8 RS232 TX fpga output The user FPGA has 8 LEDs connected to it The GPIO pins for the LEDs drive a n channel FET so driving the output high will turn on the relevant LED LVCMOS levels should be used v 2012 11 03 Page 44 The Dini Group DNV7F1A User Manual If you pulse a signal to them then they will be varying levels of brightness They are sort of yellow in color 3 12 SPI FLASH The user FPGA has attached to it a SPI flash chip SPLAD 18 338 saca 18 SPLA Sn 16 0 DIR n ER SNTARVCHTTASISOTZSS y Hra KAA 16 C382 FNF 33 SPLA 18 v 2012 11 03 Page 45 The Dini Group DNV7F1A User Manual The chip used is Micron M25P128 with 128Mbits of storage space The interface is SPI The SPI signals on the FPGA are 1 8V and are translated up to 3 3V When calculating timing for this interface please be sure to account for the delay added by the SN74AVCH1T45 level translators 3 13 EEPROM There is an EEPROM connected to the user FPGA The purpose of this memory is to store information about
28. 3 Page 50 The Dini Group DNV7F1A User Manual Each connector has on it eight transceivers lanes RX and TX 16 SelectlO signals 4 REFCLK signals and over 50W of power on 3 3V 12V and 1 8V rails The daughter board is expected to supply the REFCLK signals to the main board there are four pairs dedicated to this on the DNSEAM NS interface The DNSEAM NS daughter boards mount to the bottom of the board and attach to the baseplate which sits between the main board and the daughter board The photo below shows the location of the two DNSEAM NS connectors as seen from the bottom of the board although in this case the baseplate is not attached if the baseplate were in this photo the rest of the board would not be visible only the DNSEAM NS connectors would be visible through their apertures in the baseplate ee ee ee ee A detailed electrical and mechanical spec including the connector pin out signaling levels routing rules mechanical requirements and connector part numbers is provided for the DNSEAM_NS interface please find it on your board support package If you are designing a custom DNSEAM_NS card it must comply with the DNSEAM_NS spec We provide design reviews for DNSEAM NS expansion boards inquire please send requests to support dinigroup com 3 19 USER PCI EXPRESS The user FPGA has two 4 lane PCI Express cable connections attached to GTX tiles 113 and
29. 7 Scripting with EMU The command line version of EMU uses stdin and stdout for input and output and so it is possible to write scripts that interact with it In this way you potentially can use the board without ever having to write any software of your own If you run the program with the c switch then EMU processes commands from stdin instead of presenting the text menu Run EMU with the h script for a list of available commands The parameters for each command are identical to what EMU would expect if the same command was run from the text menu Experiment with each command from the text menu to learn how to put it into a script v 2012 11 03 Page 71 The Dini Group DNV7F1A User Manual 4 1 8 Emu the Marvell Linux environment The command line version of EMU is also installed on the Linux system that is installed on the Marvell CPU This allows EMU commands to be issued to the board using the RS232 terminal or over a telnet session to the board The command is emu mv 4 2 Writing your own software To write your own software it is recommended that you start by attempting to compile the existing gui or command line version of Emu There is Emu software manual that describes the process in the support package Host Software emu Documents 4 3 How EmuLib works The Emu program and EMULIB communicate to the board through a tall stack of software linking the host PC to the Marvell processor the Marvell processor to the F
30. D DIMM V failure DS35 RED 3 3V clock power failure DS36 RED 3 3V clock power failure DS37 RED 2 5V clock power failure DS38 RED 2 7V power failure DS39 RED 1 3V power failure DS40 RED MGTVccaux power failure user FPGA DS41 RED power failure user FPGA DS42 RED power failure user FPGA DS43 RED Vccaux power failure user FPGA DS44 RED 3 3V power failure DS45 RED 2 5V power failure DS46 RED Vccaux jo Power failure DS47 YELLOW User FPGA LED user defined DS48 YELLOW User FPGA LED user defined DS49 YELLOW User FPGA LED user defined DS50 YELLOW User FPGA LED user defined DS51 RED 3 3V clock power failure DS52 RED 3 3V clock power failure DS53 BLUE User FPGA DONE configured DS54 YELLOW User FPGA LED user defined DS55 YELLOW User FPGA LED user defined DS56 RED MGTAycc power failure user FPGA DS57 RED power failure user FPGA v 2012 11 03 Page 63 The Dini Group DNV7F1A User Manual DS58 YELLOW User FPGA LED user defined DS59 YELLOW User FPGA LED user defined DS77 RED reserved DS78 GREEN ATX power OK DS79 GREEN 12V power present 3 30 TEST POINT REFERENCE LIST There are a lot of test points on the board This list describes them The reference designator in the left hand column appears on the circuit board and can be searched for in the schematic The net names in the PIN columns are schematic net names which can also be sear
31. GA Source Synchronous interfaces are the preferred way of clocking a high speed interface across the DINAR1 connection 2onnector Virtex 7 FPGA Matched Length BUFO Optional 3 6 8 3 Source synchronous outputs You can repeat this setup in the opposite direction as long as the hold time on the device on the DINARI card is zero or negative Source Synchronous interfaces are the preferred way of clocking a high speed interface across the DINAR1 connection v 2012 11 03 Page 32 The Dini Group DNV7F1A User Manual Connector 3 6 8 4 Skewed Clocks The 1 0 on the FPGA can be used on either rising or falling edges of a clock so it is easy to invert the clock on the FPGA device so that it operates 180 degrees out of phase with the daughter card Or you can invert the clock as you output it to the daughter card The maximum frequency of the interface when using this method is effectively reduced by half Daughter Card FPGA Connector v 2012 11 03 Page 33 The Dini Group DNV7F1A User Manual 3 6 9 Incorrect Clocking Methods The following are methods that don t work 3 6 9 1 Hold time violation The following diagram shows a method that potentially violates hold time on the device on the DINARI card Daughter 3 6 9 2 PLL cascade When using PLLs in the FPGA make sure that there is not another PLL anywhere in the feedback loop of the PLL or it will result in an
32. ISE Vivado These are software programs provided by Xilinx Bitgen iMpact XST CoreGen MIG LOC constraint This is a constraint type that controls which physical pin on the FPGA device an I O will be mapped to Megabyte Usually 1 000 000 bytes but sometimes 1 048 576 bytes Kilobyte Usually 1 000 bytes but sometimes 1 024 bytes Mega b its divided by seconds Mega T ransfers per second These are used interchangeably with MHz to avoid any possible confusion when dealing with DDR interfaces MHz 1 000 000 divided by seconds Mu Multiplexer MV78200 The on board processor manufactured by Marvell Marvell Processor CPU MCU uP These interchangeably refer to a physical wire on the printed circuit board A net on the circuit board is all points that are electrically shorted together NMB These interchangeably refer to the 40 signal bus between each FPGA and Main Bus the configuration FPGA This word can mean any one of the following An interface that is more than one signal wide An interface that has more than two endpoints An interface PCIE PCI Express RGMII This is an interface specification used for Ethernet physical interface SGMII devices RocketIO In this guide these all refer interchangeably to the 10Gbps high speed GTP serial transceivers available on Virtex 7 devices GTX MGT v 2012 11 03 Page 86 The Dini Group DNV7F1A User Manual RS232 This could refer to one of the follo
33. N pi LA ENTHINCH 27 p AK24 TENTHINCH 05 Silkscreen 1 8V GPIO IO L24N T3 12 1G 25 VRP 12 41 8V CPU 41 8V CPU Fi 12 gt TENTHINCH VCC ki C18 cna ci207 H VEEC 12 tuF 100uF 3 12 iE 2x 7 voco 12 SS CER A XCTV2000TFHG1761 0 ES En a a d TENTHINCH IO 16 TENTHINCHCIO 17 N 59859 558NVNSSSzSOS WA 3 16 USER SATA The user FPGA has four SATA connectors attached to a single GTX quad tile 111 Two of the connectors have the host pinout for attaching to a downstream device like a SATA hard drive and two have the device pinout for attaching to a host system like a computer mainboard There is a dedicated oscillator connected to an appropriate REFCLK input The frequency select pins of the oscillator are connected to the FPGA so that the user can select an appropriate REFCLK frequency for SATA or SATA II or even SATA III v 2012 11 03 Page 48 The Dini Group DNV7F1A User Manual SATA NEED 150 or 300 MHZ REFCLK 3 17 USER SFP The user FPGA attaches to four connectors they occupy GTZ tile 117 This connector may be used for Fibrechannel 1 and 10 gigabit Ethernet and SAS applications via an adapter The line rate is limited by what the user FPGA supports 1 speed grade devices cannot operate the GTX xcvrs at 10Gbps v 2012 11 03 Page 49
34. P56 DIMM NC4 TP57 DIMM NC5 TP58 DIMM NC6 TP59 DIMM NC7 TP60 DIMM NC8 v 2012 11 03 Page 65 The Dini Group DNV7F1A User Manual 4 Software Using the board requires configuring FPGAs setting board controls such as clock frequency settings and transferring data on and off board For these purposes software has been provided The best place to find details about the Emu software and programming API is in the Emu Manual pdf which can be found in the user package under Host software Emu Documents Emu manual pdf 4 1 Emu host software In the user support package under Host software Emu App there is a program called EMU It can be used on Windows or Linux PCs This program allows you to control the board EMU 101 File Board FPGA Clocks Temps Data Test Help Auto Update Board Interface Refresh DNO200_DNV6F6PCIE 1003019 Ethernet CLOCKS co 100 005 Synthesizer Gl 100 003 Synthesizer G2 200 013 Synthesizer USER_L 0 000 FPGA A SRC USER_R 259 799 FPGA SRC 312 519 312 MHZ Ry Clear Save Text Full Screen Auto Scroll Welcome to Emut Comment i4 Update me EMU SOFTWARE The window shown above the is the main window of EMU Page 66 v 2012 11 03 The Dini Group DNV7F1A User Manual on 1 8 9 compiled 24 2010 Initializing aeeooooooooooooe EMU TEXT BASED UTILITY Compiled May 24 2616 Version 1 6 9 SELECTED BOARD NONE Wa a
35. PGA I Os and the FPGA 1 05 to your HDL Host PC Virtex 6 FPGA Marvell CPU Config FPGA nmb target interface Some Software Linux DMA Some HDL Ethernet EM driver m Engine Some HDL USB DMA Express driver Engine PCI Express aid Virtex 6 FPGA nmb_target_interface Clocks Some HDL DNV6FGPCIE If you want to implement your own software that uses EmuLib to talk to the board from the host PC side you are expected to understand and use the interface provided by the file diniboard h See the software Emu User Manual for details found in the user package On the FPGA side you are expected to understand and use the interface provided by the file nmb user interface v also found in the user package See documentation here Documentation Manual Dini Buses User FPGA Design Manual pdf The layers of software and hardware in between should operate transparently For no particular reason details are given here v 2012 11 03 Page 72 The Dini Group DNV7F1A User Manual 1 Your C code calls nmb_write function in the diniboard h interface 2 The emulib library determines which of the three interfaces the board is connected on Let s assume ethernet 3 The emulib library creates a packet of data with a header and the data you supplied 4 Emulib sends the packet to a special port at the ip address of the board 5 On the board a program called DiniCmos is listening to that very same port It takes the data in the p
36. Software is able to set these control signals in order to configure the clocks per the user s inputs 3 9 9 Clock MUX The config FPGA serves as one stage of multiplexers for the clocking network On the schematic you may see that clocks GO G1 and G2 come from the config FPGA The config FPGA drives out clock signals coming from the user FPGAs on the TO_SPARTAN wires depending on software settings 3 9 10 Configuring the FPGAs The configuration FPGA is connected to the selectmap configuration bus of the six user FPGAs It uses this bus to configure and read back the configuration data of the user FPGAs 3 9 11 Marvel to NMB Bridge The NMB interface connects each user FPGA to the config FPGA The data that goes to and from the FPGA winds up in the Marvell CPU s DRAM Since the config FPGA has a PCI Express link to the Marvell Processor it is able to directly manipulate memory in the Marvell s DRAM The config FPGA has a DMA controller inside of it that pushes data directly from the FPGAs to the Marvell DRAM This is entirely abstracted away via the NMB interface the user logic should simply implement the NMB engine and the user software should deal with either the Emu board control software or the AETEST library For details about the function of DMA controller see the PCle DMA ConfigFPGA design User Manual PDF document 3 10 RS232 There is a pair of signals RX and TX for RS232 Serial communication to the FPGAs v 2012 11
37. T 1 2 3 607 200 3 5M 2 800 37M VX690T 1 2 3 866 400 4 99M 3 600 52 9M V2000T 2 443 200 46 5M Each V2000T FPGA can emulate approximately 14 1 million ASIC gates reasonably however this is only an estimate It is strongly recommended that you synthesize your actual ASIC design mapping to FPGA technology to get an accurate FPGA utilization estimate 3 2 2 Speed Grades Xilinx FPGAs usually come in three speed grades There is no rule of thumb to estimate which speed grade you will need to run your design at your target frequency You will only know this once you have run a synthesis with FPGA place and route targeting the actual FPGA device that you will be using The transceivers are limited to 6 6Gbps for the 1 speed grades 10 3125Gbps for the 2 speed grades and 12 5Gbps for the 3 speed grades Verify your transceiver performance requirements before selecting your FPGA Notably to run 10Gbps Ethernet and PCle GEN3 2 speed grade or faster parts must be used 3 2 3 Upgrades If you would like to install smaller slower FPGAs when you order the board and later upgrade FPGAs to larger parts this is possible however you should request this before ordering the board because there are risks involved in attempting to add FPGAs to an existing board Costs associated with the upgrade should be negotiated with Dini Group sales v 2012 11 03 Page 20 The Dini Group DNV7F1A User Manual 3 2 4 Small FPGAs Some FPGA types notabling the V
38. The Dini Group DNV7F1A User Manual Sideband signals are also attached to the user FPGA Each has a dedicated set of sideband lines including the FC interface Voltage translation is provided as necessary The sideband signals are attached to FPGA bank 13 please see the GTX SIDEBAND page in the schematic for the sideband signal to FPGA pin mapping An oscillator is provided for REFCLK generation The oscillator can operate at four different frequencies 100MHz 125Mhz 150MHz 156 25MHz 125MHz can be used for both 1GbE and 10GbE The oscillator pads are compatible with standard 5x7mm 6 pin SMD oscillators If you require different frequencies contact the factory Please see the GTX SFP page of the schematic for a drawing of the SFPs GTX tile 117 and the SFP support circuitry NOTE POLARITY IS SWAPPED ON THE FOLLOWING NETS SFP1 MGT SFP1 RXp MGT SFP1 RXn SFP3 MGT SFP3 RXp MGT SFP3 RXn SFP4 MGT SFP4 RXp MGT SFP4 RXn MGT_SFP4_TXp MGT_SFP4_TXn The SFP connectors and cages are shown below 3 18 GTX Expansion DNSEAM NS The DNV7F1A features two DNSEAM NS GTX expansion connectors These are high performance mezzanine connectors for breaking out GTX transceivers to commonly used connectors types Available DNSEAM NS expansion cards include SFP SATA Infiniband and Samtec BullsEye Please inquire to sales dinigroup com for card availability or if you require a particular high speed serial interface v 2012 11 0
39. X330T and VX485T do not support some of the on board interfaces The interfaces that are not available in these smaller parts are 1 PCle connection 2 2 DINARI 2 3 Mictor and 0 1 header 4 User FPGA SATA connections device and host 3 2 5 Safe Handling of FPGAs There are three easy ways to break the FPGAs 1 Static electricity Make sure you keep the board on a static controlled surface and that you neutralize your body with that surface before handling the board Especially sensitive are the FPGA I Os These are exposed on the daughter card headers and other connectors 2 High Voltage The FPGA I O can only withstand voltages between GND and the VCCO power supply When interfacing the board to some external 1 0 make sure your I O signals are driven at levels that do not exceed VCCO If you do not know what VCCO is then you probably should not be interfacing the board to some external I O Note that the maximum allowable VCCO on Virtex 7 is 1 8V If you are interfacing with a 3 3V device then you will need voltage translators 3 Board warp If the board undergoes mechanical stress the FPGA pins balls can separate from the PCB and result in non connected signals The most common mechanical stress occurs when installing and removing connectors Make sure that when installing a connector you are supporting the connector from the opposite side so that board warp does not absorb the force of the insertion The board baseplate and
40. a aa aa aa aa aa aa HAKI Main Menu 9800000000000 Board Menu FPGA Menu Clocks Temps Menu Data Menu Test Menu Map Quit Enter selection There is also a command line version of EMU 4 1 1 Selecting a board To connect to a board using the EMU program make sure the board is connected to the computer either over Ethernet USB or PCI Express If the board is connected to Ethernet make sure the network supports DHCP or else you may not be able to connect to the board If DHCP is not available see the Emu_Manual pdf document for more information on setting up a static IP address When using USB on Windows a USB driver must be installed before the EMU program can detect the board The Windows USB driver is located here Host_Software emu Drivers win32_usb The driver can be installed using Device Manager Note that Linux does not require a USB driver When using PCI Express on Windows a PCI Express driver must be installed before the EMU program can detect the board The Windows PCI Express driver is located here Host_Software emu Drivers win32_pci The driver can be installed using Device Manager When using PCI Express on Linux a driver is required The Linux PCI Express driver is located here Host Software emu Drivers linux86 pci There is also provided a shell script that will load the kernel module and create suitable device nodes on the file system You must have root privileges to run this shell script v 2012 11 03 P
41. acket and drops it in the DRAM of the marvel 6 Over PCI Express the DiniCmos program sets some registers in the DMA controller in the configuration FPGA 7 The data is transferred to the configuration FPGA and then over the appropriate NMB link to the target FPGA 4 4 Marvel Environment The Marvell CPU is running a complete Linux operating system Most standard Linux applications and utilities are already installed You are able to program the Marvell processor with your own code so that the board can operate as a stand alone device without the need for a host computer in production environments 4 4 1 Linux Provided The Linux kernel on the board is version 2 6 22 18 as of this writing There is no particular name for the distribution on the board however many of the common Linux utilities are provided by busybox 4 4 2 Operating from the shell terminal You can get a linux shell terminal by using telnet to access the board The board will register its host name with the dhcp server if the dhcp server supports dns The host name of the board is DNV7F1A Xxxxxxx where xxxxxxx is the 7 digit serial number of the board The serial number can be found on the serial number sticker near the user FPGA specifically next to the user FPGA LEDs The host name of the board can also be found by connecting to the Marvell RS232 terminal and typing hostname at the prompt To do this without knowing the hostname and connecting to the board ove
42. age 67 The Dini Group DNV7F1A User Manual In Emu from the Board menu select Board gt Select Board A drop down menu will appear allowing you to select which board you wish to control and over which interface If you have multiple boards connected to the system you can only control one at a time using each instance of the Emu program After you have selected the board the main window will update to show a picture of the board you are using Selection Requested 1 31 xl Select Board 9 1 53 Ethernet Note that it may take about a minute from the time a board is powered on until when it becomes selectable from the EMU window This is the time it takes the Marvell CPU to boot into Linux 4 1 2 Configuring FPGAs To configure an FPGA you can select the option FPGA Configure FPGA from the menu bar Or you can click on the photo of the board near one of the FPGA labels and select configure FPGA from the pop up window The program will ask for the path to the bit file that you wish to use When the FPGA is done being configured a blue dot will appear next to any FPGA that has been configured The dot will stay blue until you clear the FPGA Also note that a blue LED will light on the board itself You can clear an FPGA by clicking on it and selecting clear from the pop up window 4 1 3 Clocks There are 3 global clock networks on the board that have user controllable settings Each of those clocks has its frequency continu
43. ally monitored and displayed on the main EMU window on the right side of the board photo The Auto Update check box controls if EMU monitors the board for changes or whether it only updates the screen when the user does an action To change the settings of the clocks you can click on the text displaying that clock s frequency A pop up window will display options for the clock Each clock may have different options and all options may not be available for all clocks For example clocks GO G1 and G2 can be set to a user specified frequency but USER Land USER R can not v 2012 11 03 Page 68 The Dini Group DNV7F1A User Manual 4 1 4 Sending data to and from the FPGA The EMU program can also be used to transfer data to and from the FPGAs The name of the interface on the FPGA that can be accessed from EMU is called NMB The NMB interface can be thought of as an address space The EMU program can read and write to addresses on that space Select NMB Advanced from the Data menu There are also several other NMB options to play with including a memory space browser and file transfer functions In order to transfer data to your FPGA your design must implement an NMB endpoint The code necessary to implement an NMB endpoint is provided in the user package at FPGA Reference designs common nmb For help in understanding this endpoint read the document here Documentation Manual Dini Buses User FPGA Design Manual pdf The main ref r
44. an integrated network controller if one is used such as the MAC address You are of course free to use this memory however you d like ceu EEPROM 256K Network Device Info Storage R1332 R1325 47K 4 7K 1 8V_CPU U86 PRON2 SCL adt H TOE PROM2 R428 DNI 4 7K TOE PROM2 SDA WA 2 R427 NI 7K ji A a R435 YAA VOE 2 Wi ie VCC GND AT24C256CI8 SOIC i 47K 05 Q fno Lo m o 3 14 USER CLOCK OUTPUTS The user FPGA has a pair of SMAs that may be used for clock output Also there is no reason that these SMAs could not be used as a clock output Note that since the clock is AC coupled a step clock or very low frequency constant clock may not propagate to the output The clock frequency should be about 1MHz or faster User FPGA CONN LIGHTHORSE SASFS46 P25X1 53 USERFPGAD C1205 Wa CLK SMA USERFPGApc CLK SMA USERFPGAn oe CLK SMA USERFPGANC v 2012 11 03 Page 46 The Dini Group DNV7F1A User Manual DNV7FIA 3 15 USER ASSORTED I O The user FPGA has a 0 1 header and a mictor attached to bank 12 There is no specific function for these connections they can be used for general signals 1 0 and or debug The powering these interfaces on bank 12 is 1 8V Note that these headers are connected directly to the FPGA pins they are NOT
45. board DDR3 UDIMM 16GB Max SATA Il honi EXPRESS DNV7F1 Cable GENT Qodeilla s Life Coach 7 2000 800 pins Block Diagram vin The board contains one Xilinx Virtex 7 FPGAs in the FF1761 package There are 5 different Xilinx part numbers that come in this package the VX330T VX485T V585T VX690T and V2000T All 5 of these are compatible with this board in any speed grade although the 10Gbps interfaces can only be used with 2 speed grades and faster The Virtex 6 ConfigFPGA is not intended for your use so you should think of it as more of a controller bus switch monitor v 2012 11 03 Page 18 The Dini Group DNV7F1A User Manual Note that two different diagrams exist the VX330T VX485T diagram shows some functionality lost due to the reduced pin count of the smaller devices The 330 485 diagram is re printed below DDR3 UDIMM 16GB Virtex 7 Ethernet 7VX330T 7VX485T FFG1761 DDR 2 IDELAY Refcik sc 54 Virtex 6 DDR3 Config FPGA DNV7F1 Wodallla s Life Coach 3307 485T 700 pins Block Diagram connect to other systems or off board 1 0 there three daughtercard connectors provided In the block diagram these appear as yellow rectangles The user is expected to buy a daughter card that contains the
46. casionally error conditions may occur and the interface may return error codes There is no defined way to distinguish these error codes from real data The error codes are as follows ERROR CODE MEANING OxDEADBEEO DEADBEE1 Read request to the configFPGA timed out OxDEADBEE2 DEADBEE3 Read request to the user design BARs 1 2 4 timed out OxDEADBEE4_DEADBEE4 Read request to configFPGA while the config interface is in reset The config interface may be in reset because the config clock Spartan FPGA gt PCle FPGA is not being properly received or the BARO register for resetting the config interface is set high or the DMA engines are being cleared OxDEADBEE5_DEADBEES Read request to user space while the user interface is in reset The config interface may be in reset because the BARO register for resetting the user interface is set high or the DMA engines are being cleared 3 5 240 pin 72 bit DIMM DDR3 Connectors For memory expansion the DNV7F1A has a single 240 pin 72 bit DDR3 DIMM connector This connector supports UDIMMs up to 8GB at the time of printing If you require another type of memory not DDR3 please contact Dini Group We may have or be able to manufacture a custom DIMM to your requirements 3 5 1 Memory Interface Generator The provided reference design uses a memory controller that is based on the memory controller that is produced by the Memory Interface Generator MIG part of the Xilinx
47. ched for in the schematic TESTPOINT PIN 1 PIN 2 1 VBATT_D2 GND PCIE_CPU_CPERSTn_FPGA TP2 RST_PEXOn_CPU b TP3 1 0 CPU GND TP4 12V GND TPS 1 1V CPU GND TP6 12V GND TP7 SATA_USB_TP TPS 0 9V_VTT_M GND TP9 PEX TP TP10 43 3V GND TP11 2 5V GND TP12 3 3V_ATX TP13 Ge0_TSTP TP14 DEV_READY TP15 GND TP16 minus12 0V_ATX TP17 DEV_BURST TP18 RST PORn TP19 RST_CPUn GND TP20 1 8V_CPU GND TP21 5 0V TP22 minux5 0V 5 0VSB_ATX TP26 GND TP27 2 5V_CLK_LDO TP28 5 0V_ATX v 2012 11 03 Page 64 The Dini Group DNV7F1A User Manual TP29 1 0V_MGTAVCC_Q TP30 GND TP31 43 3V PCIE GND TP32 1 2V_MGTAVTT_Q GND TP33 GND TP34 DIMM VCCO TP35 1 0 MGTAVCC 0 TP36 1 2 MGTAVIT 0 TP37 GND TP38 1 8V_VCCAUX GND TP39 1 8 GND TP40 42 5V 100 LOCAL 2 GND TP41 1 2V_MGTAVTT_1 GND TP42 2 0V GND TP43 43 3V PCIE1_PWR GND TP44 1 0 MGTAVCC 2 GND TP45 GND TP46 GND TP47 1 0 MGTAVCC 1 TP48 1 0 VCCINT A TP49 2 5 LDO LOCAL TP50 GND TP51 43 3V 2 PWR GND TP52 41 3V GND TP53 CFG VP Or GND TP54 FPGA XADC VPr FPGA VNr TP55 DIMM NC3 T
48. cument for additional information about u boot kernel and the root filesystem There is a chapter in there called The Marvell Processor that is really good 4 4 7 Compiling U boot Like the kernel compiling u boot requires a virtual machine or cross compile platform It is not recommended that you do this Instead submit your change request to Dini Group so that we can mainline your changes See the Emu Manual pdf for additional information 4 4 8 Creating the Root File system There is no root file system build process Instead we maintain a golden image in the form of a tar file containing the contents of the root file system on the Marvell Changes have to be made to the tar file manually 4 4 9 Update the software and firmware When updates are made to the root file system or to the host software or drivers an email is sent out to the emu update mailing list To subscribe to this mailing list send an email to emu update 9 dinigroup com with Subscribe in the subject line The latest software package is always available at v 2012 11 03 Page 75 The Dini Group DNV7F1A User Manual http www dinigroup com files web packs emu zi The following sections give instructions on advanced update techniques for updating the various pieces of the firmware running on the board Typically the Root File System RFS is the only firmware piece that users will ever update For the best instructions on doing a firmware update see the Emu Manual
49. e Config FPGA The configuration FPGA loads itself off of an on board SPI flash The contents of this flash are programmed by the MV78200 and updated automatically as part of the firmware upgrade procedure Thus the user should never have to do anything manually to program the configuration FPGA 3 9 3 RS232 The config FPGA passes through the user s RS232 signals to the RS232 buffer This is completely transparent to the user the configuration FPGA is simply acting as a voltage translator Please reference section 3 10 for details on user FPGA pinout for this interface 3 9 4 Count Clocks All of the boards global clocks are connected to the config FPGA The config FPGA measures the frequency so that software can report it 3 9 5 JTAG The config FPGA has a dedicated JTAG chain and connector that can be used with the IMPACT program from Xilinx This interface has no purpose v 2012 11 03 Page 42 The Dini Group DNV7F1A User Manual 3 9 6 Device Bus The config FPGA has a device bus interface connected between it and the Marvell CPU In this way the CPU can access the config FPGA as a memory mapped device This interface serves no purpose on this board 3 9 7 Blink LEDs The config FPGA is connected to 6 green LEDs It blinks these LEDs incessantly The LEDs have no purpose or meaning 3 9 8 Controlling Clocks The control signals for the global clock synthesizer chips and the multiplexer chips are connected to the config FPGA
50. e DNV7F1A PCI Express interfaces only support 1x or 4x PCI Express links The top connector on the PCI Express cable adapter card is for use with 8x links Connect one end of the provided PCI Express cable to the bottom connector of the adapter card and the other end of the cable to the DNV7F1A The correct connector is labeled PCIE Marvell for use with the Emu software For general purpose applications use this connection If you require higher throughput and lower latency on the link you way connect the PCle cable to the Configuration FPGA PCle port and use the PCIEDIRECT interface through Emu See the Emu manual for details on selecting the interface from the host software 2 1 3 2 Connect Ethernet Cable This step is optional During the course of your project if you intend to use Ethernet to control the board then you should complete this section Have a computer network In order to be able to access the board over the network the network must support DHCP Otherwise the board will fail to have a usable IP address Connect the RJ45 connector on the DNV7F1A to your network If DHCP is not available a static IP address can be assigned to the board See the Emu User Manual for more information Traffic must be allowed on certain ports in order for the Emu Software to communicate with the board See the Emu User Manual for more information 2 1 3 3 Connect USB Cable This step is optional During the course of your project if you intend
51. e REGISTERS space looks roughly like this 0x08 NMB REG IDCODE Always reads 0x05000211 0x10 NMB REG DESIGNTYPE NMB DESIGNTYPE NO 0x00000000 NMB DESIGNTYPE MISC 0x34560000 NMB DESIGNTYPE MAINREF 0 34561111 NMB DESIGNTYPE LVDSABC 0 34562222 NMB DESIGNTYPE LVDSCBA 0 34563333 NMB DESIGNTYPE FASTINTERCON 0x34564444 0x18 NMB REG SODIMMSIZE 0x20 NMB REG SODIMMEEPROM 0x60 NMB REG LVDSINTERCONBANKS 0x68 NMB REG SINGLEINTERCONBANKS 0x70 NMB REG SPIFLASH 0x78 NMB REG RS232 0x80 NMB REG PULLUPS 0x88 NMB REG VRP PULLDOWNS v 2012 11 03 Page 81 The Dini Group DNV7F1A User Manual 0x90 NMB REG MISC PULLUPS 0x98 NMB REG MISC PULLDOWNS NMB REG SPD SCL OxA8 NMB REG SPD SDA OxBO NMB REG SINGLEFAST TYPE 0x100 NMB REG STATUS 0x108 NMB REG TXRESET 0x110 NMB REG ROCKETIO RXRESET 0x118 NMB 0582 PHY ID 0x800 REG CLKSTART 5 2 Compiling The MainRef design builds in the Xilinx ISE software Scripts for building it are found at FPGA Reference Designs boards dn2047 dnv7f1a MainRef buildxst There are many many Verilog macro defines that control how the design compiles These are found at the top of the main Verilog file FPGA Reference Design boards dn0247 dnv7f1a MainRef source fpga v v 2012 11 03 Page 82 The Dini Group DNV7F1A User Manual 6 TROUBLESHOOTING General tips for troubleshooting are presented here If in doub
52. eference design provided is here FPGA Reference designs Fpga programming files user fpga main ref Correctly implements an NMB endpoint You can load these test files into one or more FPGAs and use EMU s NMB functions to send data to the reference design 4 1 5 Hardware Tests To detect hardware failures the EMU program is capable of testing the board If you want to run a complete hardware test of the board select the board in emu From the Test Menu select Selected Tests This window will appear v 2012 11 03 Page 69 The Dini Group DNV7F1A User Manual OneShot Custom Settings xl FACTORY TESTS single header test rocketio factory test FIELD TESTS temperature test clock field test nmb blockram test dram test single intercon test rocketio field test single intercon Fast lvds intercon test nmb spi flash test TEST OPTIONS Pause Error Iv Automated Mode Iv Set Clocks Repetitions 1 All of the check boxes are tests on the board that be run independently The items in the Factory Tests area all require specialized test fixture hardware to pass so they will be of limited use to users for testing the board The tests in the field tests area can all pass without special test fixtures Note that the DRAM Test requires that there is a DDR3 DIMM any density installed in the DIMM slot on the board If it is not installed the test will fail B
53. efore running the test may ask for the path to the bit files used to program the FPGAs A directory with an appropriate structure is provided on the user package in this location FPGA Reference Designs Programming Files After the test s complete the program will print out a message like this ONESHOT rocketio field test PASSED FE HEE EE EE E ONESHOT CUSTOM TEST COMPLETE rocketio field test PASS v 2012 11 03 Page 70 The Dini Group DNV7F1A User Manual ceres eee mese E CUSTOM TEST REP 1 1 PASSED DNO200 DN2076K10 1003019 5 26 2089 Comment i5 Update me EMU SOFTWARE If the test stops or fails you may need to hit the key to regain control of the EMU program 4 1 6 Command Line version The EMU program compiles into two versions The GUI version and the command line version Both versions can run in Windows or in Linux in CUST_CD DN 6F6PCIE Hi 1 6 9 compiled 24 2010 Initializing WAHAHA HAHAHAHA EMU TEXT BASED UTILITY Compiled May 24 2010 Version 1 6 9 SELECTED BOARD NONE IEEE aa aa aa aa aa aa HAKI Main Menu Ka Aa Aa aa aa aa aa aa aa Board Menu FPGA Menu Clocks Temps Menu Data Menu Test Menu Map Guit Enter selection The menu options in the command line version and in the GUI version are identical The command line version lends itself well to scripting 4 1
54. election Off the shelf DDR3 DRAM always uses 1 5V core power and IO signaling levels If you are using DRAM then you would never need to change the voltage output of the DRAM interfaces However when using alternate memory modules from Dini Group or when designing your own daughter cards you may need to supply a different voltage to the DIMM and to the attached pins of the FPGA The DIMM uses its own power regulator for DIMM Vcc and FPGA on the DIMM banks The voltage on this regulator is selectable through a jumper Position 1 2 set the DIMM voltage to 1 8V position 2 3 sets it to 1 5V and no jumper sets the DIMM voltage to 1 35V The voltage change must be performed without power applied to the board Changing the voltage while the board is powered may damage the V7F1A After performing the voltage change please make sure to probe the DIMM voltage test point to make sure it is set as expected The location of the test point and the meaning of the two available positions is drawn below v 2012 11 03 Page 28 The Dini Group DNV7F1A User Manual 3 5 4 Daughter cards Since the pins that connect to the DIMM interface on the Virtex 7 FPGA are not dedicated it is possible to develop custom daughter cards that plug into the DIMM connector The signals on the DnV7F1A circuit board are routed as 40 or 50 ohm impedance Almost every signal connecting to the DIMM is length matched including the feedback clock please see the length
55. es The SYS RESET button does not cause the power supplies to power down or the power up sequence to be repeated Here is a photo showing the location of the SYS RESET button v 2012 11 03 Page 60 The Dini Group DNV7F1A User Manual 3 27 4 User Reset There is another reset button on the board called the USER RESET button It is located as shown below This button has nothing to do with the power monitors or power All it does is assert the USER RESETn signal to the FPGA FPGA USER RESETn A active low connected to user FPGA pin AH35 It can and should be used as a general purpose logic reset in the user FPGA design The USER RESETn signal to the FPGA is also automatically asserted by the configuration FPGA while it is configuring FPGAs After an FPGA is configured the config FPGA will de assert the USER RESETn signal For this reason it is useful for the purpose of resetting your logic Additionally software can assert this signal The Emu software does so when the FPGA gt Reset menu option is chosen 3 28 XADC Each Virtex 7 FPGA has an internal block called the XADC The system monitor is enabled on the DNV7F1A although the internal source should be used for this block The VP and VN analog inputs of the FPGA are connected to a low pass filter and a through hole test point v 2012 11 03 Page 61 The Dini Group DNV7F1A User Manual WO de de WAA
56. es and their connection to the user FPGA on the DNV7F1A To obtain a better understanding of the interfaces especially if you want to design a custom daughter board please see the relevant specifications on the product CD Daughtercards Specifications v 2012 11 03 Page 6 The Dini Group DNV7F1A User Manual 1 3 6 Device Datasheet Library There is a PDF datasheet provided for every part used on the board It is in the user support package see Documentation Datasheets 1 3 7 Xilinx Questions about the use of Virtex 7 FPGAs or Vivado that aren t specific to the DNV7F1A should be directed to Xilinx 1 3 8 EMAIL AND Telephone Technical support Email support dinigroup com for the best and quickest connection to an actual Engineer that will be able to directly answer your questions Phone support is also available Pacific Standard Time from 9AM to 5PM from Monday through Friday excluding USA federal holidays Support is available in English Support for boards purchased through distributors can additionally be provided by the distributor Distributors are listed in the ordering information section Telephone USA 858 454 3419 v 2012 11 03 Page 7 The Dini Group DNV7F1A User Manual 2 Quick Start Guide This section will walk through an example session using the board 2 1 Stepsto Follow 2 1 1 Examine Contents of Box The box containing the product should have come with the following units O DNV7F1A board green
57. es capable of communicating via high speed serial connections For example Xilinx HW AFX SMA SATA can be used to convert a single GTX channel to a SATA connection Note that the SMA RX connections are AC coupled while the TX connections are not An AC coupling capacitor can be inserted onto the TX lines if this is necessary for your application see the GTX SMA schematic page p 21 to identify the capacitor part designators The SMA connectors for the GTX transceivers are circled in the following image Note that the transceivers are labeled channel direction polarity in the board silkscreen This isn t visible in the photo but you should be able to use the marking on your board to determine how to hook up this interface v 2012 11 03 Page 54 The Dini Group DNV7F1A User Manual 3 22 ENCRYPTION The Virtex 7 FPGA allows the use of encrypted bit files You would want to encrypt a bit file if you want some person to pay you for the use of your IP or to not steal it and reverse engineer it In order to support encryption we have provided the necessary battery on the board This battery supplies voltage to the VBATT pin of the FPGA even when the board is off It also provides power to the VBAT pin of the real time clock on the board The above photo shows where one might install a battery on the DNV7F1A The DNV7F1A comes with a battery installed that will last for quite some time Use an LR44 or SR44 battery An SR44 battery to
58. ingle rail for these connections If your power supply does not feature a single 12V rail do not connect the PCle graphics power header No performance degradation will be experienced in this configuration v 2012 11 03 Page 11 The Dini Group DNV7F1A User Manual 2 1 5 Power on the board If you are using the board in a chassis simply flip the switch on the front panel Otherwise install a jumper in header J21 positions 9 10 pictured below and then turn on the power supply E cba T fe The board has self boot process that takes 30 to 45 seconds 2 1 6 Using a USB pen drive to control the board The board is provided with a USB pen drive that has on it a Linux shell script startup sh If you plug the USB stick into the board then the board will automatically run the shell script The shell script on the provided pen drive will cause the FPGAs to load with the reference design bit files You can tell that the bit files are loading because after each FPGA configures a blue LED will appear on the board A USB pen drive left connected to the board will execute each time the board is powered on allowing the user to customize clock settings FPGA load files and other features without the need for host control or software intervention 2 1 7 Host Software Whether the board is connected to a computer using USB MV78200 PCI Express or Ethernet the board is controlled using a program that Dini Group has
59. ith the system however the main purpose of the console is to receive kernel debugging messages so it is recommended that you instead use a telnet terminal as this shell will be much less chatty In order to interact with the boot loader or see output from the boot process you must use the RS232 console you cannot use telnet for these purposes 3 8 2 PCI Express The Marvell device natively contains a PCI Express device The PCI express pins of the Marvell processor are connected directly to an iPass cable connector on the DNV7F1A board The provided PCle cable and adapter card can be used to connect to a host PC v 2012 11 03 Page 37 The Dini Group DNV7F1A User Manual The device appears as three 1MB memory regions to the host machine You are expected to use the Emu software and drivers source code provided to interface with PCI Express There is no description available of the function of DNV7F1A as a PCI Express device For faster and lower latency PCle accesses to the user FPGA memory space use the Configuration FPGA PCle interface See section 3 9 1 for details 3 8 3 SATA The Marvell device contains natively two SATA host ports In the pre installed software these ports are managed by Linux and you are not intended to directly interact with SATA hardware Instead when a device is installed it is automatically mounted as a storage device with a filesystem From that point you should use Linux scripts and programs to
60. l DINARI signals are length matched in accordance with the DINARI spec They are routed as 500 loosely coupled traces The signal lengths are about 300mm on the DNV7F1A v 2012 11 03 Page 30 The Dini Group DNV7F1A User Manual 3 6 6 Physical Spec See DINARI spec section 3 3 6 7 Insertion and removal Due to the small dimensions of the very high speed DINARI connector system the pins on the plug and receptacle of the DINARI connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the DINARI line up BEFORE applying pressure to mate the connectors Place it down flat then press down gently Mating can be started from either end Locate and match the connector s A1 position marking triangle for both the Plug and Receptacle Markings are located on the long side of the housing Rough alignment is required prior to connector mating as misalignment of gt 0 8mm could damage connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the plug housing with the Small alignment key of the receptacle housing and the large alignment slot with the large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by feel and
61. le DMA ConfigFPGA design User Manual pdf for details on implementing the NMB FPGA module More or less the nmb_user_interface v provides a simple Address Dataln DataOut type interface You should think of the interface as a memory space On the C side of the NMB there are simple functions like emu_nmb_read address buffer size that can be used to view this memory space The code for this is found in the support package here Host_Software emu App out_release release Software emu App source EMULIB diniboard h See Documentation Manual Emu_Manual pdf for details on the Host side of NMB communication 3 4 3 Memory Spaces For additional information read the Emu Manual sections on NMB Documentation Manual Emu_Manual pdf The memory space is 64 bit Each address represents a single byte NMB uses byte addressing however the data is required to be read and written in blocks of 32 bits Addresses supplied to the interface must be divisible by 4 Therefore the bottom 2 bits of the address space are unused and always zero v 2012 11 03 Page 26 The Dini Group DNV7F1A User Manual Additionally since there are no chip selects on the NMB bus it is necessary to pre allocate address ranges for devices on the bus On this board there is only one device the NMB address ranges that it responds to on the bus is given here Target Starting Address End Address FPGA A 0 00000000 00000000 OxOOFFFFFF FFFFFFFF 3 4 4 Error Conditions Oc
62. lerates heat better but they have similar capacity and lifetimes These batteries should impress a voltage of 1 5V nominal Do not use batteries with a nominal voltage higher than this applying a voltage in excess of 1 9V will damage the board In order to change the battery without the loss of the encryption key you can apply a voltage of 1 5V to TP1 and then replace the battery Make sure to re install the plastic battery tray when replacing the battery 3 23 JTAG The FPGA JTAG chain of the Virtex 7 FPGAs is available for your use It isn t used by any other circuit on the board It connects right up to a header that the Xilinx programmer cable connects to The v 2012 11 03 Page 55 The Dini Group DNV7F1A User Manual Xilinx Impact software or other JTAG software can be used JTAG based debug programs such as Xilinx Chipscope can also be used The configuration FPGA is not attached to the same chain as the user FPGAs 3 24 MECHANICAL The following diagram illustrates the mechanical dimensions of the DNV7F1A v 2012 11 03 Page 56 The Dini Group DNV7F1A User Manual mum 0 mart m 22 sm 501 247 0000 Rev 10 d B 502 0247 0000 DN VIF 1A pom Te Lo dile he Mode la UA x a 55 TS 55 2 5
63. mmand wget http dinigroup com marvellfiles ulmage If you do not have access to the internet then you will need to use some other method to transfer files to the board You can use a USB key a network mount or any other linux trick you know 9 Type this command cat ulmage gt dev partition spi This command updates the Linux kernel If this command fails the recovery procedure is still possible but is more complicated 10 Type this command reboot It is important that you use the reboot command and do not simply power cycle the board If you power cycle the board then the SPI flash may not get written completely due to write buffering 4 4 9 2 Installing an RFS root file system update This procedure will result in the loss of user data on the Linux file system Back up your data To check the version number of your root file system you can type this Linux command cat root image date 1 Connect the serial terminal to the board 2 Power on the board You should see u boot boot messages in the terminal At some point u boot should print v 2012 11 03 Page 77 The Dini Group DNV7F1A User Manual Hit any key to stop autoboot 3 At this step press any key You will then receive a u boot prompt like this gt gt 3 At the type this command spi boot recoveryfs 5 Once Linux is done booting you will receive a command prompt like this sh 6 At the command prompt type this Linux command
64. mperature range the software will automatically clear the overheated FPGA both to alert the user to the problem and to prevent damage to the FPGAs 3 8 7 ICE There is an interface for running a hardware debugger on the Marvell processor It is not expected that anyone will use this interface and no header is factory installed so details are omitted here v 2012 11 03 Page 40 The Dini Group DNV7F1A User Manual 3 8 8 SDRAM The Marvell environment has 1GB of DRAM managed by Linux 3 8 9 SPI Bus Flash The linux kernel and uboot bootloader are contained on a SPI flash device The marvell boots by running instructions from address of the SPI flash device There is a 4 pin SPI programming header attached to this SPI flash Typically it is unnecessary for the user to access this header do not attempt to program the Marvell SPI flash unless directed to do so by a support engineer 3 8 10 Ethernet The Marvell Processor natively contains three gigabit Ethernet ports Only one of these three ports are enabled The Ethernet port is managed by Linux You are expected to use standard Linux programming APIs to access these ports from the Marvell side of the link and to write your own software for the host side of the link The provided Emu software can be used to communicate with the board over Ethernet and you can use the communication framework provided to interact with the board from your own application The MV78200 linux terminal i
65. nual 515 File Board FPGA Clocks Temps Data Test Help Auto Update Board Interface Refresh No board selected interface selected No Board Selected Clear Saye Text FullScreen Auto Scroll M Welcome to Emut DISCONNECTED From the Board menu choose select board If you are connected to the board over PCI Express USB and Ethernet simultaneously then there will be three options in the pull down menu Each interface is treated like a separate board From the pull down menu you can see the serial number of each board The serial number in this menu should match the serial number located on a sticker near DIMM D of your board Once you have selected a board your window should look like this v 2012 11 03 Page 14 The Dini Group DNV7F1A User Manual l xl EMU File Board FPGA Clocks Temps Data Test Custom Help Auto Update Refresh Board Interface 00211 DN2076K10 1008025 Ethernet CLOCKS co 99 999 Synthesizer Gl 139 9 Synthesizer G2 199 999 Synthesizer USER_L 0 002 FPGA F SRC USER_R 0 000 FPGA C SRC USER T 0 000 FPGA A SRC Welcome to Emut RUTOCONNECT DN8211 DN2876K18 9898989 Ethernet RUTOCONNECT NOT FOUND CONNECTED TO BOARD 090211 DN2876K10 1668625 Ethernet 2 1 9 Configure an FPGA You can configure an FPGA by clicking on the image of it in EMU and selecting configure from the pop up window There are some example bit files that
66. o defined purpose for this input Given that it is on an MRCC pair it is possible that it would be useful for sending a clock into the user FPGA CONN SMA LIGHTHORSE_SASF548 F26 xt 5555555585 do c gt 8 Gt xueg 4 X9331A 5 3 8 5 pry 2 a 5 N o 1 3 3 5 DDR3 DELAY Clock This clock source provides the user FPGA with by default a 200MHz reference clock The Dini Group reference designs use this clock as a calibration frequency for IODELAY elements The user may use this clock for any purpose in their designs The frequency of this clock may be reset through the Emu software as DDR3 IODELAY 42 5V 100 LOCAL Calibration OSC LVDS 200MHz Default R519 R523 4 7K C CLK CIK DORI DELAY p osc pora EE NC 1 OSC DDR3 DELAY Ni 2 5 100 LOCAL OSC DDR3 DELAY p2p5v FB13 3 51598 5 8 439 424 BLM18AG102SN1 R525 Si 588FCA000126DG 0 tuF 10uF b 700mOhm DC 1000 Ohm 100 425 100uF 4 OSC DDR3 DELAY p2p5v dam 20 R502 0 51R v 2012 11 03 Page 24 HAAS The Dini Group DNV7F1A User Manual 3 3 6 DDR3 Reference Clock The DDR3 DIMM interface has a dedicated oscillator clock source used for providing the SYSCLK necessary for the Xilinx MIG core to function This oscillator operates at 200MHz by default but may be
67. pendent By design the maximum power the DNV7F1A is allowed to dissipate is 400W from the 12V rail and 7 5W from the 5 0V rail This assumes a very very aggressive design in the user FPGA dissipating about 100W all transceivers being used and daughter boards utilizing the maximum power allowable by their specifications With the user FPGA de configured and no daughter boards installed the auxiliary circuitry on the board will draw well under 100W Thus adding your daughter board high speed serial transceiver and user FPGA power to 100W should provide a reasonable ceiling for the total system power dissipation All of these numbers ignore the efficiency of the ATX power supply 3 26 HEAT 3 26 1 Total thermal performance The FPGA heat sinks that come installed on the board are each capable of dissipating one Watt for every 0 4 degrees in Celsius that the FPGA under it raises above the ambient temperature For example if you are using the board in a room at 25 degrees and you configure one of the FPGAs with a design that uses 50 Watts the core temperature of the FPGA will rise by 20 degrees for a total temperature of 45 degrees Note that ambient air near the board temperature measurements must be taken at full power v 2012 11 03 Page 58 The Dini Group DNV7F1A User Manual You can use the Xpower tool in Xilinx to determine how much power your FPGA design uses The amount of power that your FPGA uses may limit the maximum ambient
68. port 118 with the supplied adapter Terminal settings are 19200bps no parity no flow control Power cycle the board and watch for text on this terminal If no text is seen stop now and send email to support dinigroup com with the findings 7 If text is seen wait a minute for linux to boot Eventually it will print out something like DiniCmos Version 2011 07 26 DN0247_DNV7F1A 1201001 DiniCmos is now ready for host connections Pressing enter will then give a linux prompt If this stage is not reached stop now and send email to support dinigroup com with the findings Include all of the text that came out of the serial port that did not result in a successful linux boot v 2012 11 03 Page 83 The Dini Group DNV7F1A User Manual 7 ORDERING INFORMATION 7 1 Part Number All orders should reference the product as DNV7F1A 7 2 Howto Order Send email to sales dinigroup com for all sales inquiries North American sales are handled directly by the main Dini Group office in La Jolla CA Dini Group also has sales representation all over the world Include your geographic location in your sales inquiry so we may direct your request to the appropriate sales office Alternately you may visit our sales page to find your regional rep http www dinigroup com new sales php 7 3 Board Options The number type speed grade and position of FPGAs must be specified DRAM options must be requested specifically Chassis req
69. r a network follow the instructions in the next paragraph You can also access a terminal using the RS232 connector located near the lower right corner of the board labeled Marvell Serial This connector is a standard computer serial port The2x5 connector can be connected to with the provided IDC to DB9 adapter cable The terminal settings are v 2012 11 03 Page 73 The Dini Group DNV7F1A User Manual Baud 19200 Data Bits 8 Parity None Stop Bits 1 Flow Control OFF Emulation VT200 The RS232 output is also the system console so you will also see system messages on your terminal in addition to the shell output If this bothers you you can use telnet instead To do this follow the instructions in the previous paragraph 4 4 3 Running EMU in the terminal You can run EMU from the linux terminal From here you can configure FPGAs set clocks and send data to and from FPGAs The command is emu mv Using the program is identical to using the command line version on the EMU program on the host You should connect to the board by ip address at address 127 0 0 1 which happens automatically when mv is run If you really want you can also control other boards from this board over Ethernet 4 4 4 Compiling code on the Marvell The compiler GCC and standard C headers and libraries are installed on the board You can compile standard C and programs that run in user space For more information see the Marvell Proce
70. r logic inverted when going through the isolator i e driving high into one side of the isolator will cause the other side to go low So when configured as a downstream device make sure to invert the sideband signals in your FPGA logic The below table describes relevant device stuffing for each PCI Express interface when configured as either an upstream or a downstream device Interface Configuration Installed 0 for resistors Not Installed PCle 1 Upstream R489 R484 R491 R486 R485 R490 U93 U94 R1366 R1369 R1364 R1360 R1394 PCle 1 Downstream R485 R490 U93 U94 R489 R484 R491 R486 R1366 R1369 R1364 R1360 R1394 PCle 2 Upstream R571 R566 R573 R568 R567 R572 U107 U106 R1462 R1448 R1451 R1446 R1444 PCle 2 Downstream R567 R572 U107 U106 R571 R566 R573 R568 R1462 R1448 R1451 R1446 R1444 The PCle ports are circled in the below drawing v 2012 11 03 Page 52 The Dini Group 3 20 USER USB 3 0 The DNV7F1A has a single USB 3 0 port type B on the front panel The SuperSpeed Rx Tx lines connected to an FPGA GTX transceiver while the USB full speed high speed lines are handled through a discrete PHY chip DNV7F1A User Manual The superspeed lines connect to FPGA GTX tile 114 The user is expected to implement their own USB 3 0 IP for these lines The high speed lines are connected as sideband signals to SelectlO bank 13 USB3317 PHY is used
71. ram test IV dram test n single intercon test Iv rocketio field test JW single intercon Fast IV lvds intercon test JV nmb spi flash test IV TEST OPTIONS Pause On M Automated Mode Iv Set Clocks Iv Repetitions 1 The tests that you can run now are the temperature test clock test blockram test intercon test lvds test and flash test Let s skip the DRAM test and the factory tests for now After you hit the v 2012 11 03 Page 16 Comment i2 Add EMU SOFTWARE Comment i3 Update EMU SOFTWARE The Dini Group DNV7F1A User Manual OK button the program will ask you to locate the bit file directory This is where the test FPGA load files are stored Select this folder in the user support package FPGA Reference designs Programming Files After each test runs the Emu window will print PASS or FAIL and at the end of testing a summary will be presented with the results of each test that was run Note that the factory tests require specialized hardware and therefore cannot be run in the field The DRAM test requires that DDR3 SODIMM memory units are installed in the available SODIMM slots with the slots set for the correct voltage level If these conditions are not met then the test will fail v 2012 11 03 Page 17 The Dini Group DNV7F1A User Manual 3 Hardware This section describes the board hardware 3 1 Overview Below is a block diagram of the
72. re The provided support material all assumes that the user already has these skills 1 2 Conventions Computer input or output p http links to web pages 1 3 Resources The following list includes the resources that you are expected to make use of 1 3 1 Website The product page for this product is on the internet here http www dinigroup com DNV7F1A html This page contains Block Diagram of the board Marketing Product description List of supported features Latest Errata Latest software and firmware update package Latest version of this document v 2012 11 03 Page 5 The Dini Group DNV7F1A User Manual 1 3 2 Product Package The board comes with a USB memory stick with files on it On the root directory there is a file called Support Package Contents pdf that describes the contents and the directory structure This package contains the software installed on the board as well as the software that should be installed on your host computer 1 3 3 Reference Design The product package contains a set of FPGA designs written in Verilog HDL that produce working configuration files for the FPGAs on the DNV7F1A Project files and batch script files that use Xilinx Vivado to build the designs are also provided These example files can be used to quickly create working bit files for the FPGAs The reference design implements every feature on the board including DDR3 memory Rocket I O and othe
73. rs You are free to adopt any of the device controllers used in this reference design For most customers the most interesting part of the reference design will probably be the UCF file which contains a list of all the usable signals connected to the FPGA and the correct IOSTANDARD attribute to use with each 1 3 4 Schematics and Netlist This user manual does not list specifications for all of the devices connected to the FPGAs and so to correctly use them you will have to refer to the device datasheet and the schematic The schematic is provided in PDF format If you need machine readable format you can use the provided ASCII netlist of the board The ASCII netlist contains only nets on the DNV7F1A that are connected to usable I O on the FPGA 1 3 5 Other Relevant Documentation The principal form of control and communication with the DNV7F1A system is via the Emu software tools This manual will discuss the use of Emu in performing basic operations on the board such as FPGA configuration clock setting and data transfer For a more detailed overview of the Emu software please see the Emu manual at this URL http www dinigroup com product data DNV7F1A files Emu Manual pdf Two of the primary board interfaces the DINARI general purpose 1 0 interface and the DNSEAM NS high speed serial breakout are proprietary to Dini Group These are intended to be used for breakout from the DNV7F1A main board This manual will describe the interfac
74. s accessible via ssh v 2012 11 03 Page 41 The Dini Group DNV7F1A User Manual 3 8 11 Multi CPU The Marvell Processor has two CPUs The first CPUO is used by the Linux operating system Since the Linux kernel running on the MV78200 does not support symmetric multi processing the second CPU CPU1 must be operated in un hosted mode in its own area of DRAM without accessing devices I O must be accomplished through CPUO under Linux The use of PCI Express and the DMA engine in the configuration FPGA is possible Interrupts may also be used by CPU1 The second CPU is disabled by default 3 9 Config FPGA The second FPGA on the board the config FPGA FPGA Q is not really intended for the user It is a cleanup FPGA that controls all the clock circuits on the board configures the other FPGAs and multiplexes the NMB bus from the Marvell CPU to the user FPGAs You don t need to know anything about it or how it works You are encouraged to skip this section 3 9 1 PCI Express The config FPGA is connected to the Marvell processor through a PCI Express interface The config FPGA is a PCI Express endpoint and the Marvell acts as a root port The configuration FPGA has its own PCle cable interface independent from the one described just prior It is accessible from the host system via the AETEST software amp library This interface is less user friendly than Emu but is much faster for FPGA memory space accesses 3 9 2 Configuring th
75. se after power is applied as required by the device datasheet with the minimum pulse width specified in the datasheet 3 Prevent the user from using the board if any power supply is malfunctioning and to indicate the malfunctioning power supply with status LEDs 4 Allow the user a way to reset the board to a repeatable state without having to power the board down and back up v 2012 11 03 Page 59 The Dini Group DNV7F1A User Manual 3 27 1 Power Sequencing The power supplies are allowed to supply voltage in a particular order This is controlled by the requirements of the multi rail devices on the board 3 27 2 Power supply failure detection There is a comparator circuit on the board to detect when any of the voltages on the board falls below some minimum voltage If this happens the result is like holding down the SYS RESET button A red LED comes on and the board won t work at all Typically many LEDs will come on one for the supply that has failed and one for each supply after the sequenced supply If you give us a list of the red FAULT LEDs that are illuminated we can use this to determine which power supply has failed Often power supply failures are caused by a blown fuse which can often be fixed in the field and not require a time consuming RMA 3 27 3 Reset Button The SYS RESET button asserts the same signal that the power fail circuit does It resets the entire board similar to what a power off then power on cycle do
76. sed for these applications 3 6 2 Power The DNV7F1A can supply up to 500mA of power per DINARI 1 0 bank The voltage regulators can be set to supply 1 8V or 1 2V power to the daughter board By default as shipped 1 2V power is provided removing the VADJ jumpers along the north edge of the board sets the on board supplies to 1 8V In accordance to the interface spec the daughter board should supply the necessary Vcco voltage to the main board however if you make a mistake on your daughter board using the mainboard regulators may be useful 3 6 3 I O Header Mechanical The main board uses the Samtec SEAF 20 05 0 S 10 2 A K TR connector The daughter board uses the Samtec SEAM 20 07 0 S 10 2 A K TR connector The V7F1A is the main board side of the interface The mating card is called the daughter board For daughter board mechanical specifications including information on what mounting points are provided on the mother board please see the DINARI spec 3 6 4 Clock Pins DINARI clock pins are connected to MRCC SRCC pins on the main board On bank 1 of the DINARI interface 1000 differential termination is provided across the P and N pins on the MRCC pins This is so that a differential clock can be inserted into these clock pairs even when a 1 0 voltage other than 1 8V is used Xilinx FPGAs require 1 8V for DIFF TERM Keep this in mind of these pins are used for something other than LVDS inputs 3 6 5 Net Lengths Al
77. sh root recover sh 7 The recovery process takes about 10 minutes plus longer for the 180MB download from dinigroup com Wait patiently 8 When the recovery script is complete Type this at the shell prompt Reboot Do not power off the card without typing reboot or halt and waiting until the kernel totally shuts down The sync command can also help Otherwise the NAND Flash may become corrupt due to write buffering in linux 4 4 9 3 Installing a U boot update A failure during this process will cause the board to be un recoverable Please consult Dini Group before starting this process There is normally no reason for the user to use this procedure To check your current version of u boot you can check the boot messages for this line The compile date of mv main c is May 14 2010 1 Connect the serial terminal to the board 2 Power on the board You should see u boot boot messages in the terminal At some point u boot should print Hit any key to stop autoboot 3 At this step press any key You will then receive a u boot prompt like this gt gt v 2012 11 03 Page 78 The Dini Group DNV7F1A User Manual 3 Type this u boot command protect off 1 0 63 U boot will print this Un Protect Flash Sectors 0 63 in Bank 1 4 boot into Linux by typing this u boot command boot 5 Once Linux is done booting you will receive a command prompt like this sh 6 Type the following command mount t tmpfs tmpfs
78. ssor section in the Emu Manual pdf 4 4 5 Kernel Space If you want to run code on the Marvell Processor in kernel space the complete kernel code is required The kernel code is not installed on the board so compiling kernel mode code for the board cannot be done on the board For this you will need a build environment Likewise to modify the kernel itself also requires a separate build environment We can provide a VMWare virtual machine with a cross compiler installed that is capable of building the kernel and kernel modules Alternatively a cross compile platform can be set up See the Emu Manual pdf for additional information on building the kernel and the uboot boot loader When modifying the kernel you should maintain your code as diff files because if and when Dini Group modifies the kernel we will not provide you with a change list and you will have to re port your changes to the new kernel source Alternately you can develop the kernel changes you require and provide the change list to Dini Group and we will mainline your changes Note that you may not need to make kernel modifications at all We have provided a device located at dev mem v 2012 11 03 Page 74 The Dini Group DNV7F1A User Manual That gives user mode programs read write access to the CPUO memory space If the only thing you need to do is access protected kernel memory we recommend you just use this method 4 4 6 Boot Sequence When the board powers on the
79. stiffeners should be left installed to help reduce flex on the V7F1A system 3 3 Clock Resources The board provides many clocking resources for general use The sources and speeds of these clocks are designed to be as flexible as possible to accommodate a wide range of applications 3 3 1 Clock pins on the FPGA Xilinx Virtex 7 parts have removed the notion of global clock pins The two types of clock capable on the part excluding the GTX transceiver reference clocks are MRCC and SRCC pins The difference between the pins mostly apply to phase sensitive applications such as clocking a source synchronous interface or applications demanding the use of higher performance regional buffers BUFMR or BUFR rather than global clock resource BUFG v 2012 11 03 Page 21 The Dini Group DNV7F1A User Manual Either MRCC or SRCC pins may be used to route to a BUFG or to a clock management tile CMT Either type of pin may be used to clock regional clock resources i e a bank associated with the bank into which the clock is connected MRCC pins have the ability to clock as many as three clock regions using BUFMRs this Is useful when designing fast wide source synchronous interfaces i e a DDR3 SODIMM interface or similar The DNV7F1A s user FPGA is pinned out to maximize the amount of clocking resources available to the user and ensure flexibility across all board level interfaces For more details on how to clock a particular interface
80. t send an inquiry to support dinigroup com before attempting anything that may damage the board 6 1 General Procedure If a board is not functioning properly follow this general procedure for troubleshooting 1 Disconnect all peripherals cables daughtercards and anything else that can be disconnected 2 Visually inspect the board for damage burn marks physical damage etc 3 Using a Multimeter probe all power testpoints for GND shorts Use the TEST POINT REFERENCE LIST in this manual to locate power test points DO NOT POWER ON THE BOARD IF ANY POWER RAIL IS SHORTED TO GND If any shorts are present stop now and send email to support dinigroup com with the findings 4 Plug power back in to all 3 power connectors and power on the board Look for RED LEDs that indicate things are broken Note that the clock LOL loss of lock LEDs will be on until linux finishes booting about 30 seconds and this is normal If any RED LEDs are on stop now and send email to support dinigroup com with the Led reference designators noted The board will not boot if any power fault LEDs are lit 5 OPTIONAL Use a multimeter to probe each testpoint checked in step 3 only this time check that the voltage is correct BE VERY CAREFUL NOT TO SHORT ANYTHING WITH YOUR MULTIMETER PROBES If any voltage rails do not match their nominal value stop now and send email to support dinigroup com with the findings 6 Connect to the Marvell serial
81. temperature that your board can operate in The FPGA is not guaranteed to function properly at core temperatures above 85 degrees C 3 26 2 FANS The fans that are sitting on top of the heat sink are plugged into the board for power They have a tachometer The frequency of operation in revolutions per minute can be read from the EMU host software The fan uses a 4 pin PWM fan header which allows the configuration FPGA to control the fan speed With the fan unit included with the DNV7F1A system this should occur transparently with no user interaction required If your fans start to make a grinding noise the bearings have worn out and they need to be replaced We will send you new ones 3 26 3 Temperature Sensors The user FPGA has a temperature sensor attached to it to measure the temperature of the FPGA core die temperature Since correct operation of the FPGA is not guaranteed by Xilinx when the core temperature goes above 85C degrees we helpfully reset the FPGA for you when the temperature hits 85C This also prevents the temperature from increasing further and reaching the point at which permanent damage can result This behavior can be changed if you want but you ll have to email support dinigroup com and ask us how 3 27 RESET There is a board wide reset circuit called SYS RESET Its purpose is as follows 1 Cause power supplies to come up in a particular order 2 Cause each device on the board to get a reset pul
82. tension of Xilinx ISE constraint files It stands for Universal Constraint File These are all special purpose 1 pins on the Virtex 6 FPGA For each section that mentions one of these pins you are expected to know the purpose and usage of each These refer to reference documents produced by Xilinx v 2012 11 03 Page 87
83. ual v 2012 11 03 Page 35 The Dini Group DNV7F1A User Manual SMA 24 0 Confi GA PCI Express USER R JTAG lc NMB4 gt P rr Cable P T FONE FF1156 gt GEN 2 25 5 MHz Third Party debug connector 101001000 o Frequency 3 Synthesizer Go 85326 USB 2E 35700 MHz 20 E 3x gt Gi synthesizer 4lanes 85326 99326 Pu e PCle GEN1 2 Frequency ymhesizer 95326 I PCI Express Cable GEN 1 The primary purpose of the Marvell processor is to pump data from a host interface PCI Express Gigabit Ethernet SATA Flash or USB to and from the user s design in the FPGA Additionally these host interfaces can also be used to control the settings of the board s resources like clock synthesizers FPGA configuration and logic resets The software that comes pre loaded on the Marvel processor is running the Linux operating system For this section it is assumed that you have a working understanding of Linux 3 8 1 RS232 The console output of Linux is directed to an RS232 port In order to connect a terminal to this port you will need to set the terminal settings to 19200 baud 8bit no parity no flow control 1 stop bit v 2012 11 03 Page 36 The Dini Group DNV7F1A User Manual The Linux console is connected to a shell so you can interact w
84. uests must be discussed Many daughtercards are available see www dinigroup com for more information Contact sales dinigroup com to discuss available board options or for recommendations for your application 7 4 Compliance Information 7 4 1 EMISSIONS CERTIFICATIONS We are willing to obtain an FCC CE or other certification for volume production Inquire at sales dinigroup com 7 4 2 ROHS The board is ROHS compliant We can obtain a certification if necessary for volume production 7 4 3 PCI SIG The board passes our internal PCI Express compliance test If you need the board added to the PCI SIG integrator s list for some reason this may be done upon special request v 2012 11 03 Page 84 The Dini Group DNV7F1A User Manual 8 Glossary You can expect this manual marketing materials diagrams emails and source code from Dini Group to contain a lot of shorthand and imprecise phraseology To ensure consistency and precision here is a list of terms and words that we use throughout our documentation bit file All of these words interchangeably refer to the file containing the data for Load file the SRAM configuration bits for the FPGA This file is generated by the Configuration file Xilinx bitgen program Bitstream Hex file rarely BUFG Each of these are primitive HDL modules available in the Virtex 6 FPGA It BUFH is assumed that the reader is familiar with the behavior and use of any BUFIO primitives mentioned
85. when the receptacle keys start into the plug slots push down on one end and then move force forward until the receptacle cover flange bottoms on the front face of the plug Like mating a connector pair can be unmated by pulling them straight apart However it requires less effort to un mate if the force is originated from one of the slot key ends of the assembly Reverse procedure from mating Mating or un mating of the connector by rolling in a direction perpendicular to alignment slots keys may cause damage to the terminal contacts and is not recommended 3 6 8 Clocking Methods A wide variety of clocking topologies were considered when designing the DINAR1 interface There should be at least one clocking method possible that will meet your needs A list of reasonable clocking methods are listed and diagramed below 3 6 8 1 Manual phase alignment You can use a PLL inside the FPGA to manually align the phase of a clock that you send from the FPGA to a DINARI daughter card v 2012 11 03 Page 31 The Dini Group DNV7F1A User Manual 3 6 8 2 Source Synchronous inputs Since the signals to the daughter card are length matched you can rely on a tight timing relationship between the clock and data that you send from the daughtercard to the FPGA Since the FPGA has a zero hold time input sending a clock from the DINARI card whose rising edges are aligned with the data transitions on your data lines will result in reliable communication with the FP
86. wing Serial Port The serial port on a computer The connector on the DNV7F1A that is intended to connecting to a computer s serial port SEAM These refer to three connectors attached to FPGAs A C and D These Serial Daughtercard connectors carry high speed serial signals from the Virtex 6 FPGAs SEAM refers to the name of the Samtec brand connector series that were selected for this board SFP Small form factor pluggable module This refers to the socket attached to FGPA F that is intended for Gigabit Ethernet SMA These are little gold colored screw in coax connectors that are on the board in various places These all refer interchangeably to the DIMM connector attached to the user FPGA on the DNV7F1A Source Synchronous This refers to a clocking strategy that involves introducing a controlled amount of clock skew to devices with respect to each other don t know what it stands for Serial something interface maybe It is the protocol used for the serial Flash on this board SSTL These are all signaling standards They each require certain voltage levels LVDS and termination schemes LVCMOS HCSL HSTL CML LVTTL LVDS EXT System Synchronous A clocking strategy where each device receives a low skew clock In this guide often use this word as shorthand for using one of the provided global clock networks used this as shorthand for the set of place and route constraints that you input into ISE It refers to the ucf file ex
87. you can use in the support package located at FPGA reference designs Programming Files dn0247 dnv7f1a user fpga MAINTEST Be sure to choose bit files that are compiled for the correct type of FPGA that you have installed on the board as indicated by the folders they are stored in For example for a XC7V2000T part make sure to select from the V2000T sub directory of MAINTEST After the FPGA successfully configures a blue dot will appear next to any configured FPGA Comment i1 Update EMU SOFTWARE Page 15 v 2012 11 03 The Dini Group DNV7F1A User Manual 2 1 10 Setting board controls and options The primary board settings that you will need to modify are the clock settings There are three clocks on the board that have modifiable options Let s change the clock frequency of GO just for kicks In the EMU window click on the right side where it says CLOCKS GO A pop up menu will allow you to change the frequency of clock GO You can also change the frequency using the Clocks Temps menu in the menu bar The clock frequency of the four main clocks are periodically measured and displayed on the screen kscreen clipping of clock setup gt 2 1 11 Hardware Verification Test To run the hardware test from the Test menu select selected tests OneShot Custom Settings xl FACTORY TESTS single header test rocketio factory test FIELD TESTS temperature test IV clock Field test V nmb block

User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents