presentation - Pumpkin, Inc.
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1. TxByteCount 0 setup for Tx of string TxBitCount 0 y NE CCRI TAR SWUART TX BITTIME start 1 bit time from now GERS C TE and go void OSDisableHook void CCTL2 amp DOT b c Timer A2 interrupt calls OSTimer e No need to disable interrupts globally when Timer A1 is easily controlled via CCIE bit e 1200bps timing accuracy is more important than absolute accuracy of 10ms system tick timer OSTimer Therefore SWUART Tx XmtBit was located in the highest possible remaining timer slot available and OSTimer below it Slide 25 Advanced Technical Conference Part IV cont d PUMPKIN www pumpkininc com How to pass information up to the overlying application without requiring the disabling of interrupts One solution is to employ a single bit as a binary semaphore which is tested and cleared in the background with protection and if originally found to be set signal another background process if statusBits gt SWUARTStrSent 1 CCTLI g eOCIBS statusBits gt SWUARTStrSent 0 CCTLl CCIE OSSignalBinSem BINSEM XMITDONE P e In this example Timer AT interrupts are disabled for only 3 instructions Slide 26 Advanced Technical Conference www pumpkininc com Part IV cont d The receiver posed a greater challenge Higher bit rate requires higher interrupt priority to ensure timely processi2. transmitter it s unnecessary to disable global interrupts when re enabling transmit interrupts it s atomic Therefore we ve removed all interrupt latency unsigned char putcharTxO unsigned char data unsigned char getcharRxO unsigned char dataP if txOCount lt TX0 BUFF SIZE i if rxOCount txOBuff txOlnP data dataP rxOBuff rx0OutP if txOInP gt TXO_BUFF_SIZE 1 if rxOOutP gt RXO_BUFF_SIZE 1 txOInP 0 rx0OutP 0 tx0Count rx0Count IE1 UTXIEO return TRUE return TRUE else else return FALSE return FALSE Slide 21 Advanced Technical Conference INCORPORATED Part Ill cont d www pumpkininc com e When compared to this interrupt based UART approach a non interrupt based approach has the following characteristics On the Tx side a new character cannot be sent until the TXEPT flag is set At very high speeds e g 115 200bps this may be more efficient e smaller code size and quicker outputs But at low speeds e g 9 600bps looping to poll this bit prevents any other background code from executing On the Rx side the faster the baud rate the more often the receiver must be polled to avoid overrun errors Even a low baud rate requires tat the application poll within a critical period or errors will return e Not using interrupts requires the use of polling Polling is inefficient because it consumes CPU cycles that could otherwise be spent on other thi
3. ATC 2006 Slide 33 N ti O ce INCORPORATED www pumpkininc com This presentation is available online in Microsoft PowerPoint and Adobe Acrobat formats at www pumpkininc com content doc press Pumpkin MSP430ATC2006 ppt and www pumpkininc com content doc press Pumpkin MSP430ATC206 pdf Slide 34 Advanced T clinical Conference suggested Reading www pumpkininc com 1 MSP430x15x MSP430x16x MSP430x161x Mixed Signal Microcontroller Texas Instruments Datasheet SLAS368D October 2002 2 MSP430x1xx Family User s Guide Revision F Texas Instruments SLAUOA9F 2006 3 Salvo User Manual Pumpkin Inc 2003 Slide 35 Advanced T clinical Conference PUMPKIN Appendix www pumpkininc com e Speaker information Dr Kalman is Pumpkin s president and chief technology architect He entered the embedded programming world in the mid 1980 s After co founding Euphonix Inc the pioneering Silicon Valley high tech pro audio company he founded Pumpkin to explore the feasibility of applying high level programming paradigms to severely memory constrained embedded architectures He holds two United States patents and is a consulting professor at Stanford University e Acknowledgements Pumpkin s Salvo and CubeSat Kit customers whose real world experience with our products helps us improve and innovate e Salvo CubeSat Kit and CubeSat information More information on Pumpkin s Salvo RTO
4. H watch for overruns when updating count rxOBuff rx0InP RXBUFO H take char from UART receiver and place in buffer if rxOInP gt RXO BUFF SIZE 1 H wrap input ptr if necessary rxOInP 0 rxOCount Slide 18 Advanced T clinical Conference Part Ill cont d www pumpkininc com Dequeueing a single incoming byte from an Rx buffer unsigned char getcharRx0 unsigned char dataP if rxOCount II if there s any char in the buffer dataP rxOBuff rxOOutP Il get it if rxOOutP gt RXO_BUFF_SIZE 1 H wrap the output ptr if necessary rx0OutP 0 _DINT general case see note on slide 21 rxOCount HA update count a shared global variable _EINT return TRUE else return FALSE Slide 19 Advanced T clinical Conference Part Ill cont d e With two UARTs each with dedicated Tx and Rx ISRs and mainline code maximum interrupt latency is only 2 3 2 3 10 instructions This is good for the UARTs and the system as a whole www pumpkininc com e Can be optimized by observing that increments and decrements of 16 bit int sized count variables on the MSP430 are atomic and do not require disabling of interrupts This drops the latency down to only 2 2 4 instructions in put charTxn Slide 20 Advanced Technical Conference Part Ill cont d www pumpkininc com e Further optimization is possible on the MSP430 In the
5. I ASO kaale EC taremitreceies others T2 IAG see hote d ADC 1 400 121 FG lhaskable OFFEEh T see Motes d A2 Tima A3 Tac RO CC IPRS feral OFFECH zem Hoe 2 TSEC Al and TACERE Tim er A3 CC IPs TAIRG Marable OFFESH 5 ze Motes 1 21 PIIRGO PIIEGT EES EES CES et SR ose ore Pe IRS FIRST DACIE DIFG DAc12 1IFG DMan Io DMAT IFS DMAZIFG ses Mots 1 2 MSP430F 169 Interrupt Vector Table Slide 10 Advanced Technical Conference Annual Part Il cont d www pumpkininc com Interrupt acceptance on the MSP430 1 Any currently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 6 The SR is cleared This terminates any low power mode Because the GIE bit is cleared further interrupts are disabled 7 The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Slide 11 Advanced Technical Conference Interrupt driven MSP430 IN UART Routines warn pumpne com SRST URXEX URXEIE URXWIE SYNC 0 URXIFGx FE PE OE Em e SS wn e oe R
6. S and Pumpkin s CubeSat Kit can be found at http www pumpkininc com and http www cubesatkit com respectively Copyright notice 2006 Pumpkin Inc All rights reserved Pumpkin and the Pumpkin logo Salvo and the Salvo logo The RTOS that runs in tiny places CubeSat Kit CubeSat Kit Bus and the CubeSat Kit logo are all trademarks of Pumpkin Inc All other trademarks and logos are the property of their respective owners No endorsements of or by third parties listed are implied All specifications subject to change without notice First presented at the TI MSP430 Advanced Technical Conference in Dallas Texas on November 7 9 2006 Advanced T chnical Conference Slide 36
7. XERR RXWAKE Receiver Shift Register Ei 8 i I 0 SSH 1 SSELO SP CHAR A URXD L J UCLKI oo Baud Rate Generator SCH 7 I J Dese He Prescaler Divider UE Rx I I SMCLK 11 Modulster UxMCTL UTXD t SP CHAR i I i l A TraremitShift Register Q 1 smo oh GP 0 m TXWAKE Transmit Buffer UxTXBUF Ka UTXIFG I SYNC CKPH CKPL SWRST UTXEX TXEPT sm 1 UCLK UCLKI Clock Phase and Polarity gt Slide 12 Advanced T clinical Conference Part Ill cont d www pumpkininc com e Simplified overview of UART s Tx interrupt system Interrupts are enabled via a single bit UTXIEn in lEn An interrupt is generated when the outgoing character has left the Transmit Buffer for the Transmit Shift Register thus freeing the Transmit Buffer for another character Single buffered For efficient use of the UART we ll fill a buffer with characters and have the Tx ISR automatically send the characters out until the buffer is empty The buffer will be filled from background code e g somewhere in a main loop and it will be emptied via foreground code the Tx ISR Slide 13 Advanced Technical Conference Part Ill cont d www pumpkininc com Initialization UARTO Tx amp Rx unsigned int txOCount txOInP txOOutP rxOCount rxOInP rx0OutP char txOBuff TXO BUFF SIZE rxoBuff RXO BUFF SIZE void OpenUSARTO unsigned int UCTL UTCTL unsigned
8. be short and fast Should affect the rest of the system as little as possible Require a balance between doing very little thereby leaving the background code with lots of processing and doing a lot and leaving the background code with nothing to do Applications that use interrupts should Disable interrupts as little as possible Respond to interrupts as quickly as possible e CPU Architectures can help by Assisting interrupt handling via dedicated instructions Vectoring interrupt sources Providing configurable interrupt priorities ndividual control of interrupt enables Slide 7 Advanced T chnical Conference Part cont d www pumpkininc com Why must global variables be protected Assume a 32 bit global variable var32 on a 16 bit machine An ISR writes to the variable if non zero Mainline code records the variable and then resets it to zero for the next round Code to store a 32 bit variable on a 16 bit machine PC var32 sample Ox131E 924200020402 MOV W A sample amp var32 0x1324 924202020602 MOV W A sample 2 A var32 2 Code to clear a 32 bit variable on a 16 bit machine PC var32 0 0x5332 82430402 MOV W 0 amp var32 0x5336 82430602 MOV W 0 A var32 2 Since it takes two instructions to zero var32 consider the case when var32 is 0x0801F3CE In two instructions var32 will go from 0x0801F3CE to 0x08010000 to 0x00000000 If an interrupt occurs jus
9. e outgoing byte from the Tx buffer void ISRTxO void interrupt UARTOTX VECTOR sendcharTx0 void sendcharTxO void TXBUFO txOBuff txOOutP 4 send char out UART transmitter if txOOutP gt TXO_BUFF_SIZE 1 wrap output ptr if necessary txOOutP 0 txOCount update count if txOCount 0 if that was the last one disable further interrupts IE1 amp UTXIEO Slide 16 Advanced T clinical Conference Part Ill cont d www pumpkininc com This code satisfies our requirements for the ISR and overlying code because The code is relatively small Interrupts are disabled for a very short time 3 instructions _DINT 32C2 DINT IE2 UTXIE1 F2D020000100 BIS B 0x20 amp 1 tx1Count 92534A04 ADD W 1 amp txlCount _EINT 32D2 EINT The system overhead is quite good characters can be enqueued into the buffer as fast as possible with no delays and then they are removed from the buffer at the baud rate Time spent within the ISR is quite short mainly buffer management Only shared global variable needing protection is count Slide 17 Advanced Technical Conference INCORPORATED Part Ill cont d PUMPKIN Enqueueing a single incoming byte into the Rx buffer www pumpkininc com void ISRRxO void interrupt UARTORX VECTOR rcvcharRx0 void rcvcharRxO void if rxOCount lt RXO_BUFF_SIZE
10. errupt handling performance Slide 4 Ai l av Advanced Technical Conference Aen NU Part I cont d www pumpkininc com e When an interrupt occurs Interrupts are typically disabled prevents unwanted nesting The PC and certain registers e g STATUS are saved on the Stack The PC changes to the starting address of the ISR The ISR is executed to completion The saved registers are restored from the stack interrupt are re enabled and program execution resumes where it left off in non interrupt code e A non standard return from interrupt may be required when e g The processor is in a low power mode Exception handling is required An RTOS is used to schedule tasks Slide 5 Advanced Technical Conference Part cont d www pumpkininc com e Interrupts preempt normal code execution Interrupt code runs in the foreground Normal e g main code runs in the background Interrupts can be enabled and disabled Globally ndividually on a per peripheral basis Non Maskable Interrupt NMI e The occurrence of each interrupt is unpredictable When an interrupt occurs Where an interrupt occurs Interrupts are associated with a variety of on chip and off chip peripherals Timers SCI A D amp D A NMI change on pin Slide 6 Advanced Technical Conference Part cont d www pumpkininc com e Well written ISRs Should
11. g a critical section www pumpkininc com Disabling interrupts in a critical section prevents corruption of the RTOS global variables e g task control blocks when RTOS services that act on these variables are called from within ISRs Slide 29 Advanced Technical Conference Part V cont d www pumpkininc com How the RTOS controls interrupts during critical sections may be critical to the performance of your application f interrupts are disabled globally in critical sections you ll need to characterize how long they are disabled Too long a period and your peripheral performance may be limited f interrupts are disabled on a per peripheral basis in critical sections the RTOS impact on interrupts is limited to the particular peripherals In some RTOSes it is possible to avoid the need to disable interrupts in a critical section by using a simple semaphore based approach to pass information from the ISR level up to the background level and into the RTOS Slide 30 Advanced T chnical Conference Additional Interrupt Topics www pumpkininc com e Interrupt related runtime problems can be exceptionally hard to debug Common interrupt related errors include Failing to protect global variables sometimes due to feature creep Forgetting to actually include the ISR in the application No linker error Not testing or validating thoroughly The window in which some interrupt related e
12. int URCTL_UMCTL unsigned int BR1 BRO P30UT amp BIT5 P3DIR amp BIT5 P3SEL BIT5 II pin inits P3OUT BIT4 P3DIR BIT4 P3SEL BIT4 H rxOCount 0 rxOInP 0 rx0OutP 0 H buffer inits txOCount 0 txOInP 0 txOOutP 0 H UCTLO UCTL_UTCTL amp 0OxFF00 gt gt 8 SWRST H module init as per Tl s instructions UTCTLO UCTL UTCTL amp Ox00FF gt gt 0 H URCTLO URCTL UMCTL amp OxFF00 gt gt 8 H UMCTLO URCTL_UMCTL A Ox00FF gt gt 0 H UBR10 BR1_BRO amp OxFFOO gt gt 8 H UBROO BR1_BRO amp Ox00FF gt gt 0 H ME1 UTXEO URXEO enable Tx and Rx modules UCTLO amp SWRST II finish init IE1 URXIEO enable Rx ints Slide 14 Advanced T clinical Conference Part Ill cont d www pumpkininc com Enqueueing a single outgoing byte into a Tx buffer unsigned char putcharTxO unsigned char data if txOCount lt TX0 BUFF SIZE II if there s any room in the buffer txOBuff tx0InP data put it in there if txOInP gt TXO_BUFF_SIZE 1 H wrap the input ptr if necessary txOInP 0 _DINT general case see note on slide 21 txOCount H update count a shared global variable IE1 UTXIEO H force an interrupt now that data is ready to be sent EINT return TRUE else return FALSE Slide 15 Advanced T clinical Conference Part Ill cont d www pumpkininc com Dequeueing a singl
13. ng Higher processing rate also requires HEXTAL as MCLK Approach was similar to transmitter a FSM was employed to sample incoming bits once start bit falling edge was detected via capture mode hardware e Some interleaving of ISR processing was used to avoid excessively long execution in any particular state of the FSM Need to pass information from ISR complete received char to background process just like transmitter Slide 27 Advanced Technical Conference Part IV cont d www pumpkininc com Review Transmitter Interrupt driven At adequate priority Related interrupt control does not affect any other interrupts Highly responsive system because driving background process launches immediately upon end of transmission no polling Receiver Interrupt driven At higher priority due to higher bit rate Related interrupt control does not affect any other interrupts Highly responsive system because driving background process launches immediately upon end of transmission no polling Slide 28 Advanced Technical Conference Impact of RTOS on Interrupts e An RTOS performs context switches based on predefined behavior e g time slicing event driven task scheduling etc Normal operation involves register saves and restores manipulation of the stack and changes to global variables For all of these reasons an RTOS must typically disable interrupts durin
14. ngs Slide 22 Advanced Technical Conference Bit banged Tx Rx UART PUMPKIN using MSP430 s Timer A seis pumpleninc com e Existing MSP430 application using USARTO Tx Rx 9600 SPI and I2C USART1 Tx Rx 9600 DMA ADC P1 P2 etc Needed a 4800bps receiver and 1200bps transmitter Incoming and outgoing packets vary in length e Solution Dedicate Timer AO to 4800bps receiver and Timer A1 to 1200bps transmitter Move OSTimer 100Hz from Timer AO to Timer A2 Note Timer AO is on one interrupt vector and Timer A1 amp Timer A2 are on another Slide 23 Advanced Technical Conference Part IV cont d www pumpkininc com ISR for 1200bps bit banged transmitter void Timer A1 void __interrupt TIMERA1_VECTOR switch TAIV case 2 CCR1 SWUART TX BITTIME every 833us SWUART Tx XmtBit break case 4 CCR2 TIMERA2 RELOAD H every 10ms OSTimer break case 10 H probably should check for overflow default while 1 H error check should NOT get here break e SWUART Tx XmtBit is a state machine to output a null terminated string by bit banging an output port It sets a single bit flag when done Slide 24 Advanced Technical Conference Part IV cont d www pumpkininc com Instead of disabling interrupts globally when dealing with the 1200bps transmitter or the RTOS individual control is used void CSK SWUART Tx XmtStr void
15. rrors can occur can be as small as a single instruction Stack overflow Overlooking errata or peculiarities e g MSP430 s DMA Running out of CPU horsepower to execute the ISR fast enough Thinking that you can detect a bad time for interrupts from inside the ISR by checking a flag set in the background and thereby avoid corrupting a background process Trying to outsmart the compiler Slide 31 Advanced Technical Conference Summary By coding efficiently you can run multiple peripherals at high speeds on the MSP430 Polling is to be avoided use interrupts to deal with each peripheral only when attention is required www pumpkininc com e Allocate processes to peripherals based on existing fixed interrupt priorities Certain peripherals e g DMA can tolerate substantial latency Use GIE when it s shown to be most efficient and the application can tolerate it Otherwise control individual IE bits to minimize system interrupt latency e An interrupt based approach eases the handling of asynchronous events Slide 32 Advanced Technical Conference i G Ke e P ud ym 2 E m ger LE s 3 LR cube SE com wec Kit T4 Cid xi mpg xiL K kr Je en A 4 mm 2 D 2A TE T ge s RE my n zi d CT E Ze CM dE y x PUMPKIN www pumpkininc com Live Demo Q amp A Session Thank you for attending this Pumpkin seminar at the
16. t after PC20x5332 var32 will be 0x0000xxxx after var32 0 That may be all your application needs to crash badly Slide 8 Advanced Technical Conference Interrupts on the MSP430 www pumpkininc com MSP430 has 16 Interrupt vectors Some vectors have sub vectors e g Timer_A1 s TAIV Similar parts may have different vector tables Interrupts have fixed priority Once in the ISR interrupts are disabled They can be automatically re enabled on exit via RETI MSP430 compilers automatically add RETI to the end of declared ISR code A single stack is used for all register saves etc Therefore limited in depth only by available RAM Global Interrupt bit GIE in the Status Register SR R2 Individual peripherals usually have Module Enable Bit Module Interrupt Enable Bit IE Module Interrupt Flag IF Slide 9 Advanced Technical Conference Part Il cont d www pumpkininc com INTERRUPT SOURCE INTERRUPT FLAG SYSTEM IHTERRUPT MORD 4007 BSS PRIORITY Power up 15 highest Edema Reset Wachdog Aash m em cen RO Phi HEC see Motes d I Nonjmaskable Oscillator Fait OFIAS free Motes 1 42 Nonjmastable OFFACh Flash m em ory assess vclapon PACU WAG ses Motes d Nonimastable Tim er E ze Mote 5 TECCRO CCIFG Whos le 12 zem Hoe 21 TECCHR1 TECCRE Tim er E ses Monte 5 CCIRSs TEI RS hazlsble FFFeh zem Motes 1 21 GAG Ge Wgd mer TE EE seen ET uaa same sees 9 USS ATO trarem it UTx
17. www pumpkininc com Maximizing Runtime Performance in Peripheral Rich MSP430 Applications Andrew E Kalman Ph D Slide 1 7 Introduction PUMPKIN www pumpkininc com e Andrew E Kalman President and CTO Pumpkin Inc Author of Creator of the KA i9 L KIT o 20 years of embedded systems design and programming experience Contact aek pumpkininc com Slide 2 Advanced T clinical Conference Outline Overview Seminar Goals Part Interrupts Explained Part Il Interrupts on the MSP430 Part Ill A Basic Example Interrupt driven MSP430 UART Routines Part IV A Complex Example Bit banged Tx Rx UART using MSPA30 s Timer A Part V Impact of RTOS on Interrupts Part VI Additional Interrupt Topics Part VII Summary Advanced Technical Conference www pumpkininc com Slide 3 PUMPKIN INCORPORATED Interrupts Explained www pumpkininc com e Interrupts provide a means of changing the Program Counter PC and hence which code is executed by the CPU based on internal or external events e Interrupt code is executed from nterrupt Service Routines ISRs ISRs are vectored e Interrupts have often priorities associated with them e Interrupts can be nested e Servicing an interrupt can be thought of as a context switch e ISRs can normally call code anywhere in program memory e Instruction sets and architectures often have specific features to improve int
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