Interfacing the DSP560xx/DSP563xx Families to the Crystal CS4226
Contents
1. 3 1 3 1 OVERVIEW OF SERIAL COMMUNICATIONS 3 3 3 2 PROGRAMMING THE SSI FOR IPS 3 4 3 3 PROGRAMMING THE SAI FOR 125 3 5 3 4 SERIAL BIT CLOCK AND FRAME SYNC GENERATION 3 6 INTERFACE EXAMPLES 4 1 4 1 CDB4226 EVALUATION BOARD TO DSP56009EVM AND DSP56302EVNMU s ns arietes RE OE Eos ente 4 3 4 2 JUMPER AND SWITCH SETTINGS 4 3 4 3 SOFTWARE CONFIGURATION 4 4 4 4 HEADER PIN CONNEGTIONS secar uRRR sans 4 8 REFERENCE 1 5 1 5 1 REFERENCES rates eee eg ur Prid 5 3 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Freescale Semiconductor Inc LIST OF FIGURES DSP56302 CS4226 Pin Connections Bit Clock Frame Sync and Data Signals for Stereo Data in 2S Format eras vee cece a a ees S acr e eid rte ESSIO Control Register A CRA Located SPEEEB5 s eau ub EA RR ERR DR E ESSIO Control Register B CRB Located at X FFFFB6 e HE SAI Receive Control Status Register RCS2. 4 3 SOFTWARE 4 4 HEADER PIN CONNECTIONS Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Examples CDB4226 Evaluation Board to DSP56009EVM and DSP56302EVM 41 0 4226 EVALUATION BOARD TO DSP56009EVM AND DSP56302EVM This section illustrates the interface topics with development boards provided by and Crystal Semiconductor 42 JUMPER AND SWITCH SETTINGS The Crystal CDB4226 Evaluation Board provides seven shared analog inputs any three active at once six discrete analog outputs optical and coaxial S PDIF receive and transmit and serial interfaces through DSP and auxiliary ports The CDB4226 can be configured to act as a slave device to the DSP with a combination of switch jumper and control byte settings The switch and jumper settings are given in Table 4 1 and Table 4 2 Please refer to the Crystal CDB4226 Product Information document for details on these settings Table 4 1 Jumper Settings on CDB4226 Jumper s Position XT SEL XTAL HDRI 7 AIN RX SEL RX2 for optical S PDIF input open for coaxial S PDIF input Table 4 2 Switch Settings on CDB4226 SWI SW2 1 Off 2 Off Off 3 Off Off 4 On On 5 On Off 6 On Crystal 4226 Multichannel Codec Interface For More Information On This Product Go
3. Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Considerations Analog and Digital Input Output 2 3 ANALOG AND DIGITAL INPUT OUTPUT The 54226 handles audio information with both analog and digital Input Output I O It can support up to three simultaneous analog input channels or one digital input channel The carrier format of the resulting data either directly from the digital input or after A D conversion of the analog channels can be configured to be Inter Integrated Circuit Sound 25 PS is an industry standard format for the transfer of Pulse Code Modulation PCM digital audio and will be discussed in the next section Encoded multichannel digital bitstreams such as AC 3 or MPEG can be input through a coaxial interface or optical S PDIF from a LaserDisc or DVD player The CS4226 can be programmed to notify the user of the presence of certain bitstreams since it has built in detection of AC 3 and MPEG These bitstreams are passed to the DSP which decodes them into discrete linear PCM channels and performs any desired processing The PCM bitstreams are passed back to the CS4226 and can be converted to analog or output digitally via coaxial interface or optical S PDIF ESP 2 4 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 3 COMMUNICATIONS PROTOCOL For More Information On This P
4. Interface Examples Software Configuration The DSP control registers are initialized and set into Master mode with a pass through program which takes data in from the ESSI receive pin and returns immediately to the ESSI transmit pin An example of pass through code written specifically for the DSP56302EVM is shown in Example 4 2 with the control register initializations shown in bold The pass through program is a simple example illustrating how the control registers are updated any program can incorporate the code in bold to initialize the control registers The code can be downloaded and run on the DSP using the EVM56302 Debugger from Domain Technologies Inc Example 4 2 DSP56302EVM Pass Through Code KKK ckck ckck ckck ck ck ckck ck ck ck ck ckck ck ck ck ck ck ck KKK KKK ck ck ckck ck ck KKK KKK KKK KKK 4226PASS ASM Multi channel pass thru for the DSP56302EVM using the Crystal CS4226 Codec Based on DSP303EVM passthru code modified by Mathew Abraham July 1997 KKK KKK KKK KKK KK KKK KKK KK ck ck ck ck ck ckck ck ck ck ck KKK KKK ck ck ckck ck ck ck ck ck KKK KKK KKK KKK nolist include ioequ asm include intequ asm include vectors asm list RRR f fff f I I d Buffer for talking to the CS4226 org x 0 RX BUFF BASE equ RX data 1 2 ds RX data 3 4 ds TX BUF
5. Located at dto Dantes RS bowed SAI Transmit Control Status Register TCS Located at X FFE4 sd ico gor rz oet o al cabida PLL Control Register PCTL Located at OEREEED S cent Ns qure RACE UR THES Kod a E E Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com 2 3 3 3 vi Freescale Semiconductor Inc Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Table 4 1 Table 4 2 Table 4 3 Table 4 4 Freescale Semiconductor Inc LIST OF TABLES Jumper Settings on 0 4226 4 3 Switch Settings on CDB4226 4 3 CDB4226 DSP56302bVM Header Connections 4 8 CDB4226 to DSP56009EVM Header Connections 4 8 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc viii Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Example 4 1 Example 4 2 Freescale Semiconductor Inc LIST OF EXAMPLES Batch File To Initialize CDB4226 DSP56302EVM Pass Through Code Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Crystal 42
6. or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applicati
7. 25 format and its implementation on the SAI and SSI will be discussed to help facilitate the interface examples in the next section A timing diagram of stereo data in 125 format is shown in Figure 3 1 Serial Bit Clock Frame Sync Left Word Right Word Clock Frame Frame Serial Data LSB of last MSB of Left LSB of Left MSB of LSB of Right Right Word Word Word Right Word Word Figure 3 1 Bit Clock Frame Sync and Data Signals for Stereo Data in IS Format Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Communications Protocol Programming the SSI for I2S The 125 format requires a bit clock a frame clock and a data line For stereo data each frame cycle must contain a left word and a right word The left word is aligned with the low level and the right word with the high level of a frame cycle The number of bits per word varies depending on the number of bit clock periods contained within one frame pulse As shown in Figure 3 1 the words are aligned in such a way that the first bit of a left or right word occurs one bit clock cycle after the onset of the frame p
8. 26 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 1 INTRODUCTION For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction 1 1 INTRODUCTION Beh cR e ete ae Ag c d ne tne 1 3 1 2 SCOP Es tp s cede wee dees ERR LE a aus 1 3 1 3 THE DSP56XXX IN SURROUND SOUND bes eie EORR 1 3 1 4 THE 542261 SURROUND SOUND APPLICATIONS 1 4 1 2 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction Introduction 1 4 INTRODUCTION A common application of DSP560xx and DSP563xx Digital Signal Processors DSPs is professional and consumer level audio processing These DSPs are a popular choice in products ranging from recording studio effects processors to home theater surround sound decoders 1 2 SCOPE This article focuses primarily on the DSP56xxx as a surround sound decoder and on the accompanying hardware a surround sound application requires 1 3 THE DSP56XXX IN SURROUND SOUND APPLICATIONS Minimally digital surround sound processing requires three components surround encoded source material a software based or hardware based decoding solution and multiple Digital To Analog D A converters to supply the analog mul
9. F BASE equ TX data 12 ds TX data 3 4 ds RX PTR ds TX PTR ds org p 100 START main movep 740014 x M_PCTL movep 012421 x M_BCR ori 3 mr movec 0 sp move 0 omr move 40 r6 move 1 m6 jsr ada init loop 1 jset 2 x M_SSISRO jclr 2 x M_SSISRO move x RX_BUFF_BASE a move x RX_BUFF_BASE 1 b jsr process stereo movea x TX BUFF BASE moveb x TX_BUFF_BASE 1 jmp loop 1 process stereo nop nop nop rts include ada init asm echo end data time slot 1 2 for RX ISR data time slot 3 4 for RX ISR data time slot 1 2 for TX ISR data time slot 3 4 for TX ISR Pointer for rx buffer Pointer for tx buffer PLL 24 576 20 1 7 1 64 512 MHz 64 512MHz 1344 48kHz Set up one ext wait state for all AAR areas mask interrupts clear hardware stack pointer operating mode 0 initialise stack pointer linear addressing initialize codec wait for frame sync to pass wait for frame sync receive left receive right any audio processing happens here transmit left transmit right any audio processing happens here Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Examples Software Configuration Example 4 2 DSP56302EVM Pass Through Code Continued ROR f ff fff ff fff f f fff f fff ADA INIT ASM Includ
10. Freescale Semiconductor Inc Freescale Semiconductor Interfacing the DSP560xx DSP563xx Families to the Crystal CS4226 Multichannel Codec by Mathew Abraham Freescale Semiconductor Inc 2004 All rights reserved Ma 2 f 1 For More Information On This semiconductor to www freescale Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447
11. RRR fff p 2 5 d 2 dd SSIO_ISR ASM Ver 2 0 Example program to handle interrupts through the 56302 ESSIO to move audio through the CS4226 Copyright MOTOROLA 1995 1996 1997 H Semiconductor Products Sector Digital Signal Processing Division upon entry R6 must be the stack pointer corrupts j R6 P History 4 6 14 June 1996 RLR LJD ver 1 0 22 July 1997 MTA Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Examples Software Configuration Example 4 2 DSP56302EVM Pass Through Code Continued RRR ROR I OR P f fff f the actual interrupt service routines ISRs follow GERE OK KD ok Kee e eie eec oen SSI TRANSMIT ISR Kk kk kk kk kk kk kk kk kk kk kk Sk I I AG x G x 551 txe isr bclr Ssi tx isr move move move move nop movep move move move rti 4 x M_SSISRO r0 x r6 m0 x r6 1 m0 x TX PTR rO x r0 x M_TX00 rO x TX x r6 m0 x r6 r0 Read SSISR to clear exception flag explicitly clears underrun flag Save r0 to the stack Save m0 to the stack Modulus 2 buffer Load the pointer to the tx
12. buffer SSI transfer data register Update tx buffer pointer Restore m0 Restore r0 p kkkkkkkkkkxkkkkxkxkkx x SST TRANSMIT LAST SLOT ISR ssi_txls_isr move move move move rti qp ook KR kk KKK KKK SST receive ssi_rxe_isr belr ssi_rx_isr move move move move nop movep move move move Td 0 r6 TX_BUFF_BASE r0 rO x TX n x r6 r0 5 x M_SSISRO 0 16 m0 x r6 1 m0 x RX PTR rO x M r0 rO x RX n x r6 m0 x r6 r0 PRR KKK KKK ERK KKK SST receive last ssi_rxls_isr move move move move rti 0 r6 n BUFF BASE r0 rO x RX x r6 r0 Save r0 to the stack Reset pointer Reset tx buffer pointer just in case it was corrupted Restore r0 ISR RRR XX kk kk k kk ck k ck ck Read SSISR to clear exception flag explicitly clears overrun flag Save r0 to the stack Save m0 to the stack Modulo 2 buffer Load the pointer to the rx buffer Read out received data to buffer Update rx buffer pointer Restore m0 Restore r0 Slot ISR x XxxxX ook ok kk RR KK ee eek Save r0 to the stack Reset rx buffer pointer just in case it was corrupted Update rx buffer pointer Restore r0 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Examples Hea
13. conductor Inc Communications Protocol Serial Bit Clock and Frame Sync Generation the operating specs of the part The resulting DSP core clock frequency is shown in Equation 3 5 Please refer to the appropriate DSP Family Manual for further details on programming the PLL X MF 1 DSP Core Clock Equation 3 5 PD 1 x 2PF For example if the external crystal 24 576 MHz MF 20 PD 7 and DF 0 then 24 576 x 20 1 DSP Core Clock D 7 1 2 64 512MHz Equation 3 6 MFIO MF9 MF7 MF6 MF5 4 2 MFO 23 22 21 20 19 18 17 16 15 14 13 12 PD3 PD2 PDI PDO COD PEN PSTP XTLD XTLR DF2 DFO Figure 3 6 PLL Control Register PCTL Located at X FFFFFD Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Communications Protocol Serial Bit Clock and Frame Sync Generation 3 8 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 4 INTERFACE EXAMPLES For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Examples 4 1 4 2 4 3 4 4 4 2 CDB4226 EVALUATION BOARD TO DSP56009EVM AND DSBP56302EVM 4 3 JUMPER AND SWITCH 5 5
14. der Pin Connections 4 4 HEADER PIN CONNECTIONS Interfacing the Crystal CDB4226 Evaluation Board to a Evaluation Module requires connecting the two boards with jumper wires that carry clock and data signals Both boards have a header block to make pin to pin connections to external devices See Figure 2 1 on page 2 3 for an example of the necessary connections between the DSP56302EVM and the CDB4226 These connections are also listed in Table 4 3 Connections to the DSP56009EVM are listed in Table 4 4 These examples illustrate how the Crystal CS4226 multichannel codec can be interfaced to DSPs to implement surround sound decoding Table 4 3 CDB4226 DSP56302EVM Header Connections DSP on CDB4226 J7 ESSIO on DSP56302EVM SCLK 7 SCKO 2 LRCK 5 5 2 12 SDOUT 3 SRDO 8 SDIN1 17 6 SDIN2 15 SC00 4 SDIN3 13 SCO1 10 Header pin number Table 4 4 CDB4226 to DSP56009EVM Header Connections DSP on CDB4226 J5 on DSP56009EVM SCLK 7 SCKT 15 LRCK 5 WST 13 SDOUT 3 SDIO 9 SDIN1 17 SDOO0 17 SDIN2 15 SDO1 19 SDIN3 13 SDO2 21 Header pin number Se 4 8 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 5 REFERENCE MATERIAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Referenc
15. e Material 5 1 5 2 REFERENCES 4 bench eee teehee a qai ined Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reference Material References 51 REFERENCES For additional information consult the following documents from and Crystal Semiconductor DSP56000 Digital Signal Processor Family Manual DSP56009 Digital Signal Processor User s Manual DSP56009EVM User s Manual DSP56300 Digital Signal Processor Family Manual DSP56302 Digital Signal Processor User s Manual DSP56302EVM User s Manual Crystal CS4226 Preliminary Product Information Crystal CDB4226 Preliminary Product Information For a complete list of accessible DSP documents visit the website reached at the following address http www f r eescal e dsp com documentation The example code presented in this application report is available via the website reached at the following address http www f r eescal e dsp com documentation appnotes Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reference Material References 5 4 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com
16. e for 4226PASS ASM to initialize the CS4226 Copyright c MOTOROLA 1997 Semiconductor Products Sector H Digital Signal Processing Division H History P 14 June 1996 RLR LJD ver 1 0 22 July 1997 RRR k k k k k k 132 60 org p ada init Set up control words for ESSIO movep 0000 x M_PCRC movep 18180d x M_CRAO movep ff 341c x M_CRBO movep 003F x M_PCRC reset delay for codec do 1000 _delay_loop rep 65 nop _delay_loop movep 000C x M_IPRP andi CLB 1 jset Jerr jset CLB bset do jset init loopB rts SFC mr 3 x M SSISRO 3 x M SSISRO 3 x M SSISRO 18 x RX BUFF BASE 18 x TX BUFF BASE 4 init loopB 2 x M SSISRO 2 x M SSISRO turn off ESSIO port PM 13 SCLK 64 2 W F 2 304MHz 24 2 48kHz network synchronous mode all transmitters enabled frame clocked on falling edge turn on ESSIO WL 24 bits 1 ms delay 512MHz 13 1 2 2 304MHz assuming 64 512MHz VCO set interrupt priority level for ESSIO to 3 enable interrupts wait wait wait loop until until until until set wait wait until until rx frame rx frame rx frame CLB set tx frame tx frame bit bit bit bit bit
17. milar communication protocols in mind configuration is a trivial issue Detailed connection circuitry including capacitors and pull up resistors will not be discussed here Please refer to each part s respective data sheet for assistance in designing appropriate interface circuitry 2 2 COMMUNICATION PINS The Crystal CS4226 codec is able to communicate with the DSP560xx or DSP563xx families via a serial interface Depending on which DSP chip derivative is used the serial interface may be a Synchronous Serial Interface SSI or a Serial Audio Interface SAI The DSP563xx derivatives use an Enhanced SSI ESSI that includes up to three transmitters which can be programmed to transmit three stereo channels or six total channels The ESSI facilitates the implementation of surround sound decoding because six channels can be transmitted in parallel removing the need for multiplexing the outputs Refer to Figure 2 1 for signal connections between the DSP56302 ESSI and the CS4226 codec DSP56302 CS4226 master slave Coaxial S PDIF Receive Transmit SCKO SCLK RXI Au M Digital audio bitstream 5 2 W LRCK 2 4 M Optical S PDIF Receive Transmit N SDOUTI ii SRDO 3 STDO SDINI AIN Analog in 5 00 We SDIN2 2o Analogo SC01 W SDIN3 Figure 2 1 DSP56302 54226 Pin Connections Crystal 4226 Multichannel Codec Interface For More
18. nterface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Communications Protocol Programming the SAI for I S 11 10 9 8 7 6 5 4 3 2 1 0 PSR PM7 PM6 PM5 4 PM3 PM2 PMI PMO 23 22 21 20 19 18 17 16 15 14 13 12 SSCI WL2 WLI WLO ALC DC4 DC3 DC2 DC1 DCO CKP FSP FSR FSL1 FSLO SHFD SCKD SCD2 SCD1 SCDO OF1 OFO 23 22 21 20 19 18 17 16 15 14 13 12 REIE TEIE RLIE TLIE RIE TIE RE TEO 2 MOD SYN Figure 3 3 ESSI Control Register B CRB Located at X FFFFB6 defines the functionality of the port FSL 1 0 Bits 7 8 defines the shape of the frame pulse FSR Bit 9 chooses word alignment FSP Bit 10 defines the frame sync polarity CKP Bit 11 defines the bit clock polarity SYN Bit 12 chooses between asynchronous synchronous transmit and receive and MOD Bit 13 chooses Normal mode or Network mode To conform to S standards the frame pulse should be one word long The first word bit should lag the frame pulse by one serial clock as shown in Figure 3 1 The frame sync and bit clock should clock in data on the falling edge choose synchronous mode for simplicity and for stereo data choose Network mode to allow for two words per frame 3 3 PROGRAMMING THE SAI FOR 25 The SAI port is more readily configurable for handling 125 than is the SSI port I
19. ons intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS INTRODUCTION 2423 3 xeu ree nes 1 1 1 1 INTRODUCTION Eades ER FOE ade 1 3 1 2 Or Ble eae Pe Oc se 1 3 1 3 THE DSP56XXX IN SURROUND SOUND APPLICATIONS uc Gada denen ate E debt at 1 3 1 4 THE 54226 IN SURROUND SOUND APPLICATIONS 1 4 INTERFACE CONSIDERATIONS 2 1 2 1 INTERFACE CONSIDERATIONS 2 3 2 2 COMMUNICATION PINS zr ov ketene QERERRERIM 2 3 2 3 ANALOG AND DIGITAL INPUT OUTPUT 2 4 COMMUNICATIONS PROTOCOL
20. r home theater applications A common scenario is to use the S PDIF receiver on the CS4226 to pass an encoded audio bitstream to the DSP The DSP will decode the bitstream into its constituent channels and perform any desired post processing For Dolby Digital or DTS bitstreams the output of the decoder is typically six channels of digital audio more commonly referred to as 5 1 channels The six channel D A converters on the 54226 can convert the six individual data streams into six analog outputs This solution replaces a multiple chip A D and D A configuration with a single chip for surround sound applications ESP 1 4 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 2 INTERFACE CONSIDERATIONS For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Considerations 2 1 2 2 2 9 2 2 INTERFACE CONSIDERATIONS COMMUNICATION ANALOG AND DIGITAL INPUT OUTPUT Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Considerations Interface Considerations 2 1 INTERFACE CONSIDERATIONS The DSP56000 family and the Crystal 54226 can be interfaced without glue logic Because these parts are designed with si
21. roduct Go to www freescale com Freescale Semiconductor Inc Communications Protocol 3 1 3 2 3 3 3 4 3 2 OVERVIEW OF SERIAL COMMUNICATIONS 3 3 PROGRAMMING THE SSI FOR 9 3 4 PROGRAMMING THE SAI FOR 129 3 5 SERIAL BIT CLOCK AND FRAME SYNC GENERATION 3 6 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Communications Protocol Overview of Serial Communications 3 1 OVERVIEW OF SERIAL COMMUNICATIONS derivatives of the DSP560xx and DSP563xx families use either SSI or SAI for serial communications The SSI is a full duplex serial port for communicating with a variety of peripheral devices such as codecs microprocessors or other DSPs The port is fully programmable allowing the user to choose the number of bits per word the protocol the clock and the transmit receive synchronization The ESSI is available on the DSP563xx derivatives and provides three transmitters as compared to one transmitter on the standard SSI The SAI port is used in many of the audio based derivatives of the DSP560xx family and is an important subset of the SSI port The SAI supports by default many popular audio data formats such as PS developed by Philips Compact Disk Protocol CDP from Sony and Matsushita Electronic Corporation MEC protocol making it ideal for audio applications The 1
22. t defaults to two words per frame which simplifies much of the configuration The Baud Rate Control BRC register the Receive Control Status RCS register and the Transmit Control Status TCS register dictate the behavior of the SAI port The BRC register determines the serial bit clock rate similar to the PM 7 0 bits in the ESSI CRA The Receive and Transmit Control registers shown in Figure 3 4 and Figure 3 5 are identical in defining the data format Bits 4 and 5 determine the word Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Communications Protocol Serial Bit Clock and Frame Sync Generation length Bit7 chooses the frame sync polarity and Bit 8 chooses the bit clock polarity Bit 9 defines the word alignment 11 10 9 8 7 6 5 4 3 2 1 0 RXIE RDWT RREL RCKP RLRS RDIR RWLI RWLO RMST RIEN ROEN 23 22 21 20 19 18 17 16 15 14 13 12 RRDF RLDF RXIL Figure 3 4 SAI Receive Control Status Register RCS Located at X FFE1 11 10 9 8 T 6 5 4 3 2 1 0 TDWE TREL TLRS TDIR TWLI TWLO TMST T2EN TIEN TOEN 23 22 21 20 19 18 17 16 15 14 13 12 Figure 3 5 SAI Transmit Control Status Register TCS Located at X FFE4 3 4 SERIAL BIT CLOCK AND FRAME SYNC GENERATION An important step in correctly implementing I5 is defining the appropriate bi
23. t clock and frame sync frequencies In this discussion the DSP is the master device and therefore supplies the necessary clocks to the CS4226 codec The codec uses the frame sync clock as its Analog to Digital A D sampling frequency and uses the bit clock to synchronize communication with the DSP In order to choose a 44 1 kHz or a 48 KHz sampling frequency F for the codec careful consideration must be given to the generation of these clocks in the DSP Once an F is chosen say 48 kHz the Phase Lock Loop PLL on the DSP must be programmed to provide an exact multiple of the chosen frequency In the example given in Equation 3 3 and Equation 3 4 the PLL was programmed to create a DSP core frequency of 64 512 MEZ which is exactly 1344 48 KHz The DSP56302 PLL Control Register PCTL can be configured to provide almost any desired serial clock frequency by adjusting the DSP core clock frequency This is accomplished by modifying the external crystal frequency F with multiply and divide bits in the PCTL shown in Figure 3 6 MF 11 0 Bits 0 11 applies a multiplication factor to and PD 3 0 Bits 20 23 and DF 2 0 Bits 12 14 are predivider factor and divider factor bits respectively Care must be taken to ensure that at any step the multiplication or division factors do not set the VCO frequency outside 3 6 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semi
24. tichannel output Source material that has digitally encoded surround sound can be in the form of LaserDiscs or Digital Versatile Disks DVDs which typically contain Dolby Pro Logic Dolby Digital or Digital Feeder System DTS encoded soundtracks Decoding this material in real time from a bit stream to multichannel digital audio requires a hardware based solution such as the DSP56009 or DSP56362 The final component in surround sound processing converts the multichannel digital audio to multichannel analog audio Traditionally the surround sound process employed multiple mono or stereo D A converters to provide the number of analog outputs needed Replacing these multiple codecs with a single integrated multichannel codec such as the C 4226 from Crystal Semiconductor Inc would simplify the design as well as reduce cost Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction The CS4226 in Surround Sound Applications 1 4 THE CS4226 IN SURROUND SOUND APPLICATIONS The CS4226 contains one stereo Analog to Digital A D converter one mono A D converter and six D A converters on a single chip All converters have 20 bit resolution and programmable input gain and output attenuation The CS4226 will also accept and transmit Sony Phillips Digital Interface S PDIF digital data signals These features make this particular codec attractive fo
25. to www freescale com Freescale Semiconductor Inc Interface Examples Software Configuration 4 3 SOFTWARE CONFIGURATION The Crystal CDB4226 requires certain control registers to be initialized to operate in the desired mode A DOS executable provided by Crystal called WRSPI EXE uses a host computer to initialize the control bytes The batch file listing shown in Example 4 1 gives the necessary commands to set up the CDB4226 as the slave device using 125 data format Please refer to the Crystal CS4226 Product Information document to customize the initialization of these control bytes Example 4 1 Batch File To Initialize CDB4226 rem RSTSPI EXE sends a soft reset to the CDB4226 rstspi rem Begin initialization rem Clock Mode Byte PLL driven by coaxial S PDIF in XT 256Fs CLKOUT 256Fs wrspi 01 04 p00 rem Converter Control Byte wrspi 02 00 rem DAC Control Byte wrspi 03 00 rem Output Attenuator Bytes no attenuation wrspi 04 00 wrspi 05 00 wrspi 06 00 wrspi 07 00 wrspi 08 00 wrspi 09 00 rem ADC Control Byte S PDIF input to SDOUTI wrspi 0b 40 rem Input Control Byte wrspi 0c 00 rem DSP Port Mode Byte 125 data falling edge DSP is slave 64 bit clocks Fs period wrspi 0e ec rem Auxiliary Port Mode Byte wrspi 0f 00 rem Auxiliary Port Control Byte wrspi 10 00 4 4 Crystal 4226 Multichannel Codec Interface For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
26. ulse frame pulse 1 2 frame period The SSI and the SAI ports can be configured to handle the PS carrier format essentially by programming their respective control registers The important portions of the control registers that pertain to 175 are discussed below Refer to the respective parts user s manual to correctly program the remaining bits in the control words 3 2 PROGRAMMING THE SSI FOR 125 The SSI port is more flexible than the SAI port and thus requires more programming to define a particular data format such as 125 The example used in this section will focus on the DSP56302 ESSI port which has two control registers Control Register A CRA and Control Register B CRB shown in Figure 3 2 and Figure 3 3 These registers define how the SSI handles data CRA defines the timing of the necessary signals PM 7 0 Bits 0 7 defines the serial bit clock rate DC 4 0 Bits 12 16 gives the number of time slots or words per frame and 2 0 Bits 19 21 defines the number of bits per word The following equations show how these bits define the clocking signals DSPCoreClock Serial Bit Clock 3x PM 1 Equation 3 1 SerialBitClock Frame Sync Clock WLx DC 1 Equation 3 2 For example if the DSP Core Clock 64 512 MHz PM 13 WL 24 and DC 1 64 512MHz Serial Bit Clock SX 2 304MHz Equation 3 3 2 304MHz Frame Sync Clock BAx 1 1 48 000kHz Equation 3 4 3 4 Crystal 4226 Multichannel Codec I
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