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SoC Reference Kit User Manual

1. Ethernet Traffic Generator SmartBits To PC Serial Port 48V Power Supply Figure 5 RF Traffic Test Configuration September 2005 9 SoC Reference Kit User Manual 3 USING THE REFERENCE KIT SOFTWARE 31 Terminal Setup Windows HyperTerminal is the suggested interface for setting up the host PC and SoC Reference Board Section 2 2 details how to configure HyperTerminal However any VT100 terminal will work with the following setup e Baud rate 115200 8 bit data no parity bit 1 stop bit and no flow control e VI100 emulation must be chosen as terminal emulation type e Do not send line ends with line feeds e Donotecho locally typed characters 3 1 1 SoC Main Menu Once your PC has been setup the SoC software defaults to the SoC Main Menu Navigate through the submenus to setup the SoC Reference Board On your keyboard type the number corresponding to the submenu you want to access At any stage during setup you can return to a previous submenu hitting the ESC key or return to the Main Menu by hitting ESC a few times consecutively Each submenu is described below a SoC HyperTerminal Unlicensed Max File Edit View Call Transfer Help Main Menu 1 System Configuration 2 RF Board Configuration 3 ARM Subsystem Tests 4 802 16 PHY Tests 9 Traffic Application 6 gt Upgrade 1 Save and Restore Config Command ESC Exit Connected 0 00
2. 0 1 11 Modulation QPSK er voss ay cons esee 1100 Full Duplex T APG Enabl ss i a cess orai ween er Vctcxo Setting x OxFFF 0x7fFf h AGC 1 AGC Atten Value 9 63dB 0 1 Bandwidth S ffinj sui 99297 Mhz BY Start delay 0xa0 1 TK Stop N LA RM UBLGU cons comm eran woes s nn 3 0x50 he R starb deldU cvv pews TR_SWITCH 1 IZQ DAC ADC Int Ext Internal q I Q DAC Output Control BB 0x1559 r IZQ DAC Output Control RF 0x199d s BER Resolution x10 6 Command ESC Exit lt gt Connected 0 01 55 Auto detect 115200 8 N 1 Station Type Choose the station type of the board for the traffic tests In Master mode the board initiates the PHY traffic In Slave mode the Slave board will listen for the Master board and then sync to the Master before it can transmit uplink data RF BASEBAND Setup the board to allow RF or Baseband traffic In Baseband mode the RF Board is not initialized and AGC and Automatic Frequency Control AFC are not operational FDD TDD For an RF system define
3. Data Bus 7 LocaBusData 118 GND 119 MD12 Data Bus Local Bus Data 120 MD13 Data Bus Local Bus Data 121 MDM Data Bus Local Bus Data 122 GND 123 MD15 Data Bus Local Bus Data 124 MD16 Data Bus Local Bus Data 1 September 2005 Table 15 J 3 Pinout Debugger Connector continued Pin 55 BSName SS Description BS Description LocalB Bus Data 0 125 126 127 128 129 130 131 132 133 134 135 156 137 138 139 140 141 142 143 144 MD17 GND MD18 MD19 MD20 GND MD21 MD22 MD23 GND MD24 MD25 MD26 GND MD27 MD28 MD29 GND MD30 MD31 Data Bus Data Bus Data Bus Data Bus Data Bus DataBus Data Bus 2 0004 Data Bus SoC Reference Kit User Manual Local Bus Data Local Bus Data Local Bus Data Local Bus Data Local Bus Data Local Bus Data Local Bus Data ___ Local Bus Data Local Bus Data Bus Data gt Local Bus Data DataBus tocalBusbata Local Bus Data 146 GND 147 50 CAS SDRAM Column Address Select 148 5 RAS _ SDRAM Row Address Select 149 SD_WE SDRAM Write Enable 150 GND 151 CSDA Data 152 CSCL m Clock 153 SPICLK SPI CLK 154 GND 155 SPIDATAOUT SPI Data Out 156 SPI_ C50 SPI Chip Select 157 ARM GPIO2 BE ARM General Purpose Input Ou
4. disabled enabled enabled enabled 1 enabled 3 4 LEDs ARM GPIO 0 24 and ARC_GPIO 0 3 are routed to LEDs to aid testing and development with the SoC Reference Board Table 6 LED Routings ARM GPIOO ARM GPIO1 ARM GPIO2 ARM GPIO3 ARM GPIO4 ARM GPIO5 ARM GPIO6 ARM GPIO7 ARM GPIO8 ARM GPIO9 ARM GPIO15 ARM GPIO16 ARM GPIO17 ARM GPIO18 ARM GPIO19 ARM GPIO20 ARM GPIO21 ARM GPIO22 ARM GPIO23 ARM GPIO24 ARM GPIO10 ARM GPIO11 ARM GPIO12 ARM GPIO13 ARM GPIO14 ARC GPIOO ARC GPIO1 ARC GPIO2 ARC GPIO3 A 6 September 2005 SoC Reference Kit User Manual 35 DIP Switches DIP switches on the SoC Reference Board allow for ARM GPIO level settings and PLL settings For all DIP switches setting the position to OFF causes logic level HIGH while setting the position to ON causes logic level LOW DIP switch settings for PLLs assume a REFCLK frequency of 20MHz Table 7 DIP Switch Default Settings Signal Default Setting DIPSW Signal Default Setting ARM GPIO8 ARM GPIO16 ARM GPIO9 ARM GPIO17 ARM GPIO10 PLL1 SPEEDO ARM GPIO11 PLL1 SPEEDI ARM GPIOI _ kr PLL2 SPEEDO ARM GPIO13 PLL2 SPEEDI ARM GPIO14 PLL3 SPEED ARM GPIO15 Not Used Table 8 DIP Switch PLL Frequencies pu Multiplier PLL1Frequency ARM 140MHz 160MHz default 180MHz 200MHz i s Multiplier PLL2 Frequency ARC 140MHz 160MHz de
5. Description 0 0 0 0 0 0 ARM GPIO12 GND ARM GPIO13 ARM GPIO14 ARM GPIO15 GND ARM GPIO16 ARM GPIO17 ARM GPIO18 GND ARM GPIO19 ARM GPIO20 ARM GPIO21 GND ARM GPIO22 ARM GPIO23 ARM GPIO24 GND SPARE SPARE SPARE GND AGC CTRLO AGC CTRL2 GND AGC CTRL3 AGC_CTRL4 5 GND AGC STRB SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General P urpose Input Output ARM General P urpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Bus A 20 September 2005 SoC Reference Kit User Manual Table 16 J 14 Pinout Debugger Connector continued Pin Description O 00 0000 0 SPARE GND SPARE SPARE SPARE GND SPARE
6. VX A N 199 C233 245 287 C289 304 C323 341 C344 C603 55 56 70 73 MCNC 0402 22PF 50V 5 04025A220J AT2A AVX COG C217 CAP MCNC 0402 0 022UF 16V5 0402 223 AT2A AVX X7R C74 C85 CAP MCNC 0402 47PF 5 50V 04025 470 COG C219 0402 0 047UF 16V 80 20 0402YG473ZA 405 CAP MCNC 0402 56PF 5 50V 040254560 AT2A COG C401 CAP MCNC 0402 68PF 5 50V 040254680 COG C404 CAP MCNC 0402 82PF 5 50V 040254820 COG C213 214 TANT SMD 10 20V 20 NTC T105M20 NIC COMPONENTS 1 C218 CAP MCNC 0402 0 033UF 04022 333 AT2A AVX 10V5 X7R C402 403 CAP MONO 6 8PF 0402 25V COG 650L6R8BT 257 C202 TANT SMD 22UF 16V 20 F931C226MC NICHICON C40 41 TANT SMD D 47UF 10V 10 PCT47 10DK NEMCO C215 CAP TANT SMD D 100UF 10V 10 TPSD107K010R0065 C45 C602 CAP TANT SMD E 100UF 16V 10 TPSE107K016R0100 1812 1000PF 2KV X7R 10 1812GC102KA11A C22 C30 31 C35 1812 0 01UF 60 OV X7R 10 1812CC103KAT2A 1 C24 CAP SMD C 68UF 6 3V 20 ROHS NOJC686M006RWJ AVX PB FREE 1 L8 FERRITE BEAD 1206 3A BLM31P1215G MURATA 120R 100M A 32 September 2005 SoC Reference Kit User Manual Reference Description Part ParNumber Ql Reference L21 L25 26 L28 29 L33 38 1127 71 12 RECEPTACLE CONN 1X3PIN 2MM 0 126 HSMT TMM 103 01 G S SM SAMTEC 3 5 8 9 CONN 1X2PIN 2MM 0 126 SMT TMM 102 01 G S SM SAMTE
7. J23 RF Connector J16 SED Q S3 Reset J19 MultiTrace J1 MultilCE J20 External Processor Switch S2 DIP Switch To PC Serial 48V Power Port Supply Figure 3 SoC Reference Board 5 September 2005 SoC Reference Kit User Manual 2 1 Host PC Requirement A host PC is required to change the default SoC Reference Kit software configuration and to initiate tests To communicate with SoC you must have a computer system that meets the following hardware and software requirements e 1 available standard hardware serial port DB9 operating system that provides a standard RS 232 terminal program for the available hardware serial port e g Microsoft Windows HyperTerminal 2 2 How To Configure HyperTerminal The procedure for configuring HyperTerminal on a Windows based PC is detailed below 1 Select File Properties from the main menu to display the Serial Properties screen Serial Hyper Terminal HAK Displays the properties of the current session 2 The Serial Properties screen defaults to the Connect To tab Under the Connect Using dropdown menu select an available COM port then click Configure to configure this port S
8. 5 2 4 HosStPGO here aar 6 22 How To Configure Hyper Terminal ti tec tee eee re ea ee 6 2 3 Anstalling Heatsink and Powering UP cou onibus a ameet Io Rape vac aevo ids 8 2 4 Setting Up SoC Reference Boards for a Traffic 8 24 1 eet ene 8 242 8 3 Using the Reference Kit nennen naar nnns 10 22 TEMNA o mmm 10 SOC MANE 10 312 System Gonliguralor MOL SSE 11 3 1 9 RF Board Goniiguration 22222 Icom ee co n 12 3 1 4 ARM Subsystem Tests 14 3 1 5 802 16 PHY Tests 16 3 1 6 ass uu St rede FUR t 17 SLT Upgrade M nU RU 18 3 1 8 Save and Restore Configurations 19 Appendix 1 Definitions and A 1 Appendix 2 Reference Board Functional A 2 Appendix 2 Some PORT A 15 Appendix 4 Reference Board Bill of Materials A 32 Appendix 5 Reference Board 5 A 37 Sept
9. 5 00 Command ESC Exit DEMO performing init GPIO TRANS MGR INIT ENET MGR INIT BER 107 6 BER init success DEMO Loading and Messaging ARC image Demo Success ARC was loaded Using Internal IQ adc dacs Setting to 3 5 Mhz Setting TCR to 1559 Loading preamble for RFI BOARD Successful Demo Success Preamble loaded Demo Setting VCTXO to 7ff ARC Change State to Demo Success ARC Demo Config PHY Demo Config Success ARC Demo Start PHY Demo Start Success DEMO begin traffic Connected 0 17 06 Auto detect 115200 8 N 1 When Running and Connected on Master soc HyperTerminal Unlicensed Joes Edt View Cal Transfer Heb Du DB Traffic Statistics Station Type Master Ethernet 0 Ethernet Rx Ethernet Rx Errors HY AT loce rrr PHY 1 NOMEN RS 3 Instant BER x10 6 0 Total BER x10 6 0 Hit ESC to exit Connected 0 24 44 Auto detect 115200 8 N 1 3 1 7 Upgrade Menu SoC Reference Kit User Manual When Running on Slave SoC HyperTerminal Unlicensed Jog Edt Cal Transfer Heb D 25 085 Traffic Statistics Station Type Slave Link is UP RS 73 Instant BER x10 6 0 Total BER x10 6 0 Hit ESC to exit ted 0 30 27 Auto detect 115200 8 N 1 The Upgrade Menu has three 3 operations as
10. PHY Clock Generated by programmable Direct Digital Synthesis DDS Analog Devices AD9834 e Reference Board VCTCXO can be bypassed by a jumper when RF Boards are used 1 2 6 Output e Transmit Tx Analog Output 10mA outputs requiring 75ohm termination resistor Differential outputs e Receive Rx Analog Input 0 5VPP inputs 0 55V common mode differential inputs 1 2Kohm impedance e Digital to Analog Converter DAC Outputs 10 bit DAC outputs for option of using external DACs Outputs provided on 38 pin Mictors for logic analyzer access e Digital Analog to Digital Converter ADC Inputs 10 bit ADC inputs for option of using external ADC nputs provided on 38 pin Mictors for logic analyzer access 3 September 2005 SoC Reference Kit User Manual 1 2 7 Baseband and RF Interface Connector e Connector Samtec TOLC 125 02 F Q LC e Supported Boards Baseband Adapter Board SiGe SE7351L AK1 SiGe SE7351L AK2 SiGe SE7351L AK3 SiGe SE7351L AK4 SiGe SE7351L AK5 SiGe SE7351L AK6 1 2 8 External Processor Interface Connector e Connector 152 pin Mictor Receptacle e External Processor Board GDA Technologies MPC8560 Mezzanine Card 1 2 9 Debugger Board Interface Connector e Connectors One 1 Samtec SOLC 130 02 S LC and One 1 Samtec SOLC 150 02 S LC e Interfaces to Debugger Board 1 2 10 RS232 Connector Connector Micro D Sub 9 Pin 1 2
11. SiGe BD2 16 3 5GHz RF chipset gt TX 3500 3600 MHz gt RX 3400 3500 MHz gt 3 5 MHz bandwidth RF Eval Board F2 H FDD SS SiGe 802 16 3 5GHz RF chipset TX 3400 3500 MHz gt RX 3500 3600 MHz gt 3 5 MHz bandwidth One board installed at a time Figure 2 Relationships between Hardware and Software SoC Reference Kit September 2005 SoC Reference Kit User Manual 1 2 2 Power Supply e Power Requirements 15W Max standalone or 25W Max with external processor board e Input 48VDC e Connector 5 5mm OD 2 5mm ID Center Positive DC Connector e Power Reset Voltage supervisor resets processor when rails drop below 20 nominal value e Power Sequencing Voltage rails are sequence to requirements of processor 1 2 3 Processor One 1 Fujitsu MB87M3400 WiMAX SoC 1 2 4 Upper Media Access Control UMAC Processor Peripherals e Processor ARM 926 internal to SoC e Memory Synchronous Dynamic Random Access Memory SDRAM 128Mb 4Mx32 Micron MT48LC8M32LF F5 10 Flash 4Mb e Ethernet Physical Layer PHY AMD 79C874 e General Purpose Input Output GPIO Light Emitting Diode LED status LED status indicators for each 24 GPIOs for software development Dual In line Package DIP switch pull down for 10 GPIOs for software development 1 2 5 Clocks e Clock Source 20MHz Voltage Controlled Temperature Compensated Oscillator VCTCXO 10ppm control 4 5ppm stability e Front End FE
12. debugger running on the host PC 6 4 ARC Debugger The ARC debug signals are routed to a 200 pin Samtec SOLC connector J3 The Debug Connector Board is required to connect to J3 and bring the ARC debug signals to a DB 25 connector suitable for interfacing to a PC parallel port 6 5 Debug Connectors The Debug Connectors are two 2 Samtec SOLC connectors 200 pin and 120 on the bottom of the SoC Reference Board J3 and J14 Most of the digital signals that are useful for troubleshooting are routed to these connectors The Debug Connector Board makes these signals available on 38 pin MICTOR connectors suitable for connecting to a logic analyzer It also serves double duty as an ARC debugger board 6 6 SoC PHY Subsystem Physical Layer Functionality for SoC includes e Mandatory Functionality Frequency Range 2 11 GHz 256 point FFT 192 data carriers 8 pilot carriers 200 active carriers Forward Error Correction FEC Concatenated Reed Solomon Viterbi Mapping BPSK QPSK 16 QAM with coding rates 1 2 3 4 Channel Quality Measurements A 10 September 2005 SoC Reference Kit User Manual e Optional Functionality 64 QAM with coding rates 2 3 3 4 Reed Solomon Bypass BPSK Subchannels e Special Functions Alternate syncs Manufacturing Functions 6 7 PHY Interface PHY interface signals are described in Section 7 below PHY amp Q outputs are inter
13. 35 MA24 Address Bus gt 36 25 EE 2001 0001 37 650 LBSZ0 ChipSelet LocalBusBurstSze 38 GND 39 ICSI 18571 _ 000 Bus BurstSize _ 40 CS2 1852 Chip Select Local Bus BurstSize 41 CS3 Chip Select 42 GND A 15 September 2005 SoC Reference Kit User Manual Table 15 J 3 Pinout Debugger Connector continued Pin s5 BS Description Local Bus Ready Mode Local Bus Chip Select Local Bus Byte Enable JCS4 LBRDYMD 55 118 CS 45 WEO BEO 46 GND 47 BE1 48 49 ME3 BE3 50 GND 51 TXDO 52 TXD1 53 TXD2 54 GND 55 TXD3 56 MIL TXCLK 57 TXEN 58 GND 59 TXER 60 RXCLK 61 RXDV 62 GND 63 RXER 64 COL 65 CRS 66 GND 67 RXDO 68 RXDI 69 RXD2 70 GND 71 RXD3 72 73 MDC 74 GND 75 SPARE 76 SPARE 7 ARM GPIOO 78 GND 79 ARM GPIO1 80 SD CKE 81 TXDI Chip Select Chip Select SDRAM Write Enable SDRAM Write Enable SDRAM Write Enable SDRAM Write Enable Ethernet Tx Data Bus Ethernet Tx Data Bus Ethernet Tx Data Bus Ethernet Tx Data Bus Ethernet Tx Clock Local Bus Byte Enable Local Bus Byte Enable
14. TECHNOLOGY IC 1 24V 5 30V ADJUSTABLE LM285M NATIONAL REGULATOR 1 U10 ICDRIVER RX DUAL 5016 ADM3202ARN ANALOG DEVICES exeever m BET raten UT IC DDS 50MHZTSSO0P20 AD9834BRU ANALOG DEVICES 014 018 030 IC R R HISPD SOT 23 5 AD8051ART ANALOG DEVICES 2 U24U27 IC OPAMP DIFFERENTIAL AD8132 AD8132ARM ANALOG DEVICES IC ZERO DELAY BUFFER 50108 23055 1 CYPRESS 2 2031 IC SINGLE SCHMITT TRIGGER INV MC74VHC1G14DFT2 ON SEMI U6 U8 U15 U19 20 IC OCTAL BUFFER DRIVER W 3 SN74LVC244APWR TEXAS STATE OUTPUTS INSTRUMENTS U32 IC ZERO DELAY BUFFER 23025 CYPRESS PROGRAMMABLE LOW V HIGH BANDWIDTH BUS SN74CB3Q3257PWR TEXAS INSTRUMENTS TEMP SENSOR 12C 9 BIT SIGN LM77CIMX 3 NATIONAL U21 22 AUSTIN LYNX PROGRAMMABLE 005 0 TYCO POWER MODULE NON ISOLATED U3 FUJITSU AIRMAN 802 16 CHIP MB87M3400 FUJITSU T CNVRTR DC DC 48V TO 12V PKB4713PINB ERICSSON 121 R31R36 37 R39 44 0402 OR 5 1 16W RM04J 000 CAL CHIP R46 47 R119 120 R 123 125 R128 129 R 136 138 R140 R142 145 R 153 157 R160 163 R169 R171 R173 R175 176 R194 R218 R222 R225 226 R 232 233 R235 R239 R241 R243 R245 R247 R249 R255 256 R261 R265 R271 272 R291 R295 R297 R299 306 R316 R320 R323 R330 R 333 336 R 378 384 R 399 R404 405 R419 441 R460 R500 R502 R523 524 R529 R540 R543 R198 R258 R450 R452 RES 0402 1000HM 0 062W 196 RMOAF1000CT CAL CHIP R454 R4
15. at 1OMHz input 59dBc A 14 September 2005 SoC Reference Kit User Manual APPENDIX 3 CONNECTOR PINOUTS Table 15 J 3 Pinout Debugger Connector Pin 55 BSName SSDescripion BS Description 1 GND 222 2 3 00 LBA00 Address Bus LocalBusAddress 4 MAO1 Address Bus Local Bus Address 5 Address Bus Local Bus Address 6 GND 7 Address Bus Local Bus Address 8 4 Address Bus Local Bus Address 9 MAO5 Address Bus Local Bus Address 10 GND dL 11 LBAO6 Address Bus gt Bus Address 12 000000 LocalBus Address 13 LBAO8 AddessBus gt LocalBus Address 14 GND 15 LBAO9 Address Bus LocalBusAddress 16 MA10 LBA10 Address Bus LocalBusAddres 17 Address Bus LocalBusAddress 18 GND eee 19 MAI2 1 12 AddessBus gt Bus Address 20 MAI3 A Ass Bus Local Bus Address 21 AddessBus gt LocalBus Address 22 GND 23 MAIS LBAIS AddessBus gt LocalBus Address 24 16 Heus AMS Bus LocalBus Address 25 MAI AddressBus 00000 26 GND 27 18 AddressBus gt fo 28 MAI9 JARED 29 20 Address 3 MA21 Address 32 22 ess 33 MA23
16. described below a soc HyperTerminal Unlicensed Jod File Edit View Call Transfer Help De 83 DA Upgrade a Upgrade KMODEM b Erase Flas c Version Information Command ESC Exit _ Connected 1 57 45 Auto detect 115200 8 N 1 a Upgrade XMODEM Load a new version of the SoC software into the Flash chip using HyperTerminal When the PC displays the HyperTerminal main menu select Transfer Send File Refer to Section 2 2 for details on how to configure HyperTerminal September 2005 SoC Reference Kit User Manual Ensure XMODEM 1K is selected as the transfer protocol then locate the bin file i e Pre SoC Ref 1 x bin Choose the bin file to begin Modem transfer When the transfer is complete the firmware begins to update the contents of the Flash chip Wait until the Upgrade Menu screen reappears with a confirmation that the upgrade was successful To run the newly upgraded software you must reboot the system EA SoC HyperTerminal Unlicensed Job File Edit View Call Transfer Help Command ESC Exit Starting Recieve Maximum image size is 512 KB cancel session type ctrl x ctrl x CCC gt Connected 1 58 31 Auto detect 115200 8 N 1 b Erase Flash This option is provided for advanced Flash chip programming purposes Caution selecting this option completely erases the contents of the Flash chip This is not recomm
17. frequency range between 3 401 750 to 3 500 000KHz in 250KHz increments e g Fc 3 401 750 250n where n 0 393 e MHz BW TDD radios Center frequency range between 3 403 500 to 3 500 000KHz in 250KHz increments e g Fc 3 403 500 250n where n 0 386 e MHz BW HD FDD SS Slave radios Tx center frequency range between 3 403 500 to 3 500 000KHz in 250KHz increments e g Fc 3 403 500 250n where n 0 386 Rx center frequency range between 3 503 500 to 3 600 000KHz in 250KHz increments e g Fc 3 503 500 250n where n 0 386 7MHz BW HD FDD BS Master radios Tx center frequency range between 3 503 500 to 3 600 000KHz in 250KHz increments e g Fc 3 503 500 250n where n 0 386 Rx center frequency range between 3 403 500 to 3 500 000KHz in 250KHz increments e g Fc 3 3403 500 250n where nz0 386 Transmit Power Attenuation 0 95 dB Control Tx power by attenuating the maximum possible Tx power by the given amount of attenuation Values range between 0 to 95 dB of effective attenuation 13 September 2005 SoC Reference Kit User Manual The next four 4 items under the RF Board Configuration Menu display current read only values for the four attenuators on the RF Board f 20dB attenuator pin g Tx fe Agc Gain 0 35 5dB steps h Tx age gain 0 50 1dB steps i Tx mixer gain 0 6 12 18 dB j Show Registers Display the read only RF Board Registers Menu The RF Board is not automatically progr
18. the duplexing mode as either FDD or TDD In FDD mode Rx and Tx frequencies differ while in TDD mode they are the same Rx and Tx frequencies are set under the RF Board Configuration Menu see Section 3 1 3 Modulation Change the modulation scheme Choose from BPSK QPSK QAM16 and QAM64 Ethernet Configure the Ethernet PHY to Auto Negotiate 100BT half Duplex 100BT full Duplex 10BT half Duplex or 10BT full Duplex AFC Enable Enable or disable the Automatic Frequency Control AFC This feature is only applicable to Slave mode and cannot be enabled in Master mode Refer to VCTCXO Setting below to understand AFC requirements for system configuration VCTCXO Setting 0x0 0xFFF Fine tune the RF Center Frequency This is critical for data transfer on an RF system i e does not affect data transfer on a Baseband system The VCTCXO Setting is the binary value of the VCTCXO adjustment which is written to a 12 bit DAC that controls voltage at the control pin of the oscillator AFC on the Slave board must be disabled in order for the VCTCXO value to take effect To fine tune the frequency write the value of OX7FF to DAC on both Master and Slave boaras The ideal value for Ox7FF differs for each board due to its unique electrical characteristics Determine the ideal value using lab equipment i e a frequency counter and spectrum analyzer to ensure the RF Center Frequency is closely matched on Master and Slave AGC Enable Enable or dis
19. 0 bit DACs Similarly analog data is converted to digital by the PHY using a pair of 10 bit A 13 September 2005 SoC Reference Kit User Manual ADOs Two 2 ADC DACs are required for Quadrature Amplitude Modulation QAM to provide two streams of data and Q ADC DAC sampling rates support the maximum data bandwidth of the system and oversampling requirements of the PHY The maximum supported bandwidth is 20MHz with a sampling clock of 46MSPS ADC DAC controls the inputs for registers such as output enable data format 2 s complement or binary and power down Registers are controlled by the PHY and are accessible by the ARM via ARC DAC requires an external reference of 1 1V This is implemented on the SoC Reference Board by D9 and a resistor divider The ADC input range is 0 25V 0 85V This is equivalent to a 0 6Vpp 1 2Vpp differential signal with a common mode voltage of 0 55V Table 14 ADC and DAC Specifications ADC Specifications DAC Specifications Resolution 10 Bits Resolution 10 Bits Data Throughput 100MS S Data Format Two s complement and binary SNR Signal to Noise Ratio at 10MHz input 56dBFS min e Atan output frequency of 110MHz 8 is 60DBc SINAD Signal to Noise and Distortion at 10MHz Atan output frequency of 110MHz 4 is 48DBc input 54dBFS ENOB Effective Number of Bits at 10MHz input 8 7 bits SFDR Spurious Free Dynamic Range at 10 2 60dBc THD Total Harmonic Distortion
20. 11 ARM Debug Connector e Connector 2x10 0 1 shrouded male header e Debugger ARM Multi Ice 1 2 12 ARM Embedded Test Module ETM Connector e Connector 38 pin MICTOR Receptacle ARM Multi Trace e Supported Mode Multiplexed half clock mode 13 SoC Baseband Board Specifications The SoC Baseband Board and the SoC Reference Board interface via the baseband and RF interface connector e Connector Samtec TOLC 125 02 F Q LC e Channel BW 3 5MHz and 7MHz baseband filters selectable by shunt jumper e Rx Inputs amp Q single ended inputs on MCX cables e Tx Outputs I amp single ended outputs on MCX cables Power Supply 5VDC powered by the SoC Reference Board via the power cable 14 SoC Debugger Board Specifications The SoC Debugger Board and the SoC Reference Board interface via the debugger connector e Connectors One 1 Samtec TOLC 130 02 S Q LC and One 1 Samtec TOLC 150 02 S Q LC e ARC Debugger DB25 female connector attached at the Personal Computer PC parallel port e Logic analyzer Interface Five 5 38 Pin MICTOR receptacles and ARM external memory interface Serial Peripheral Interface SPI IC Automatic Gain Control AGC RF control 4 September 2005 SoC Reference Kit User Manual 2 QUICK START GUIDE Refer to Figure 3 to identify the components of the SoC Reference Board that are required for host PC requirements Section 2 1 and Heatsink installation Section 2 3
21. 39 Auto detect 115200 8 N 1 1 System Configuration Setup the SoC Reference Board system configuration Examples of system configurations include Baseband or RF operation mode TDD or FDD operation and Modulation type 2 HF Board Configuration Manipulate the RF Board and its registers from this submenu ARM Subsystem Tests Access useful memory and tests for the ARM subsystem 802 16 PHY Tests lnteract with 802 16 PHY Peak the values for each register and configure registers using the poke command Traffic Application Start traffic between the Master and the Slave Upgrade Upgrade firmware using the XModem protocol Erase the contents of Flash under this menu and retrieve firmware version information see also Section 3 1 7 b 7 Save and Restore Config Save customized configurations for the SoC Reference Board that are maintained on reboot Factory default settings are also available from this menu 10 September 2005 SoC Reference Kit User Manual 3 1 2 System Configuration Menu Use the System Configuration Menu to change default settings for the SoC Reference Board Develop custom configurations for Baseband RF TDD FDD and Modulation Each submenu is described below soc HyperTerminal Unlicensed Job File Edit View Call Transfer Help i System Configuration d SIBIDOU asas coos essen cous coon aster b RF BASEBAND
22. 56 R533 R55 R80R89R209R212 RES 0402 1 0KOHM 0 062W 1 RMOAF1001CT CAL CHIP R227 229 R 236 237 R 262 263 R286 R329 R 397 398 R408 410 R451 R453 R455 R457 R466 R476 R601 602 R8 R18 R25 27 R 32 34 RES 0402 10 0KOHM 0 062W 196 04 1002 CAL CHIP R48 R65 66 R87 R118 R 127 R131 R147 R223 R 324 R331 R411 412 R415 418 R442 443 R458 R477 478 R495 499 R503 504 R544 545 A 34 September 2005 o 25 D 25 eT un D 5 Qty Part Number 2 R215 R407 RES 0402 1MOHM 0 062W 1 RMO4F 1004CT CAL CHIP 1 R200 RES 1 16W 1 1 1 0402 CR05 1101F T 1 CAL CHIP CAL CHIP CAL CHIP CAL CHIP RES 0402 1 21KOHM 0 062W 1 RMO4F1211CT RES 0402 12 1 0 062W 1 RMO4F1212CT R149 RES 0402 13K7 0 062W 1 RMO4F 1372CT 89 14 R16 R84 86 RES 0402 150 OHM 0 062W 1 RMOAF 1500CT R90 98 R 102 113 R 116 R224 R254 R264 R274 277 R402 403 R481 CAL CHIP CAL CHIP CAL CHIP CAL CHIP CAL CHIP CAL CHIP CAL CHIP PANASONIC CAL CHIP CAL CHIP RMOAFSEQICT AMOAFSELOCT RMOAF DICT AMOAFERSICT 08 RHOF IOROCT R5 6 R19 R29 30 R51 RES 0402 33 20HM 0 062W 1 RM04F33R2CT R 53 54 R 56 62 R 69 70 R72 79 R81 82 R100 R114 115 R 130 R 133 134 R152 R164 168 R 177 192 RMONFISDICT CALCHP RMO4F1821CT CALCHI 3 RMO4F2000CT CALCHP RMO4F2002CT CALCHI RMO4F2431CT CALCHP 3 RMO4F27AICT CALCHI RMO4F3320CT CALCHP RMO4F3321CT CALCHP R
23. 93 SDRAM Write Enable 94 MDIO Data Bus 95 GND 96 MD09 Data Bus 97 SDRAM Write Enable 98 MD08 Data Bus 99 GND 100 MD07 Data Bus 101 WE2 SDRAM Write Enable 102 MD06 Data Bus 103 SPARE 104 MD05 Data Bus _105 SDRAM Write Enable 106 MD04 Data Bus 107 GND 108 MD03 Data Bus 109 SPARE 110 MD02 Data Bus 111 GND 112 MDOI Data Bus 113 SPARE 114 MD00 Data Bus 115 55 EB ES Chip S elect 116 GND 117 SPARE 118 SPARE 119 MA15 Address Bus 120 GND 121 MA14 Address Bus 122 MD31 Data Bus 123 MA13 Address Bus 124 MD30 Data Bus 125 12 Address Bus 126 MD29 Data Bus 127 11 Address Bus A 28 Local Bus Address September 2005 SoC Reference Kit User Manual Table 18 J 20 Pinout PowerPC Board Connector continued m Sum Meme SS Description BS Description Data Bus Local Bus Data Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Address Bus Data Bus Local Bus Data A 29 September 2005 SoC Reference Kit User Manual Table 19 J 4 Pinout Serial Connector Pin Name Description gt N A TX RS232 RX RS232 N A GND N A N A N A N A 3V3 3V3 ARM
24. APPENDICES September 2005 SoC Reference Kit User Manual APPENDIX 1 DEFINITIONS AND ACRONYMS ADC AFC AGC AHB APB BER BS BWA CODERAM DAC DDS DIP DMA DSI ETM FDD FE GPIO HD TX UART UMAC VCTCXO Analog to Digital Converter Automatic Frequency Control Automatic Gain Control Advanced High Performance Bus Advanced Peripheral Bus Bit Error Rate Base Station Broadband Wireless Access Code Random Access Memory Digital to Analog Converter Direct Digital Synthesis Dual In line Package Direct Memory Access Direct Slave Interface Embedded Test Module Frequency Division Duplexing Front End General Purpose Input Output High Density Integrated Circuit Institute of Electrical Electronic Engineers Intermediate Frequency Load Store Light Emitting Diode Media Access Control Personal Computer Physical Layer Phase Locked Loop Radio Frequency Receiver Sensitivity Signal Strength Real Time Operating System Receive Synchronous Dynamic Random Access Memory System on Chip Serial Peripheral Interface Subscriber Station Time Division Duplexing Transmit Universal Asynchronous Receiver Transmitter Upper Media Access Control Voltage Controlled Temperature Compensated Oscillator September 2005 SoC Reference Kit User Manual Appendix 2 Reference Board Functional Description 1 INTRODUCTION The SoC Reference Board consists of the following modules 802 16 SOC e 20 MHz VC
25. ARE 53 SPARE 24 SPARE 55 SPARE 56 SPARE 57 SPARE 58 SPARE 59 SPARE 60 SPARE 61 SPARE gt 62 SPARE 20 63 ARCEXTIRQL _ 64 SPARE 65 SPICLK 66 SPARE Jooo 67 GND 68 BS SYNCIN 69 spicso _ 70 71 ARC EXT IRQQ n em 1 gt 13 SPIDATAOUT 14 BRDY 2 75 SPARE 6 GND 77 RE 8 6010 _____ ____ 79 ENABLE __ 80 CS2 81 SPARE 82 ARM GPIO5 83 EXT RESET 04 MD15 ARC General Purpose Input O Frame Timer Interrupt Output Base Station Synchronization Output ARC External Interrupt SPICLK Base Station Synchronization Input SPI Chip Select ARC External Interrupt Spi Data Output Local Bus Ready Mode Read Enable Local Bus Read Write PHY RF Circuitry Enable Chip Select Local Bus Burst Size ARM General Purpose Input Output External Reset Data Bus Local Bus Data 2 September 2005 SoC Reference Kit User Manual Table 18 J 20 Pinout PowerPC Board Connector 2 Local Bus Burst Size Pin SSName BSName_ Ss Description PS Description CS1 Chip Select Data Bus 07 ARM 4 ARM General Purpose Input Output 88 MD13 Data Bus 89 50 Chip Select 90 0 Data Bus 91 ARM GPIO23 ARM General Purpose Input Output 92 MDII Data Bus
26. C EN TOP SHROUD TERMINAL STRIP 151 110 01 5 0 SAMTECH CONN COMMERCIAL MICRO D 83611 9006 MOLEX PLUG J2 CONN RJ 45S W CONDUCT 155 P 3 8 1 REGAL GASKET ELECTRONICS 1 16 CONNRFMCKPCBICKGGS G2MCK SOO TT ITINN HUBER amp SUHNER VE EE COM S0PNSOL sorcas oe SAMTEC TERMINAL SMT av WSRIWSPMWEOS fes ooo X2 CRYSTAL 25M 50 PPM 40C PM 2MM 25 0000MHZ D A TO485C VCTCXO 20MHZ SMD 3 4 0PPM SBTO16DDVY20 000M SANGSHIN Hz 1 06 X LEDRECTRDSMD SML LX1206IC LUMEX D1 D3 0605 LD1 48 LED GREEN 0603 SML LX0603GW TR LUMEX H7 12 STANDOFF FLARE MOUNTED 6 KFB3 632 8ET ken 32 0 250 SDRAM 128MBIT VFBGA 90 MT48LC4M32LFB5 10 MICRON IT IC 10 BIT 80 MPSP DUAL D A AD9218BST 80 ANALOG DEVICES CONVERTER IC 10 BIT 125 MSPS DUAL DAC AD9763AST ANALOG DEVICES 1 041 IC DAC 12 BIT SOIC 8 TLV5616ID TEXAS INSTRUMENTS IC VOLTLTG SPRVOLTSR 5VOLT ADM708TAR ANALOG DEVICES SOIC8 U37 IC POWER SEQUENCING ISL6123 INTERSIL CONTROLLER IC FLASH MEMORY W P0 MT28F 320 3BS 11ET MICRON SOFTWARE LOAD 2 U33 U600 IC VOLT 1 25 MHZ LT1765 LT1765ES8 LINEAR TECHNOLOGY U4 U34 IC VOLT REG 5 0VOLT 0 8A LDO LM1117IMPX 5 0 NATIONAL A 33 September 2005 SoC Reference Kit User Manual Qty Reference Description Part Number Manufacturer 1 1026 ICVOLTAGEREG 1 8VOLT0 8A LM1117MPX 1 8 NATIONAL U36 IC VOLT INVOLT 5VOLT 50723 6 LTC1983ES6 5 LINEAR
27. DRAM tests a d are for the external SDRAM chip interfaced with the ARM subsystem e Code Random Access Memory CODERAM tests e h verify the RAM memory contained in the ARC subsystem This memory module is where the ARC executable is loaded and executes 14 September 2005 SoC Reference Kit User Manual e Load Store LD ST tests i l verify the load store RAM memory contained in the ARC subsystem This memory module is where the interface between ARC and ARM occurs e FLASH tests m p are geared to the external FLASH chip interfaced with the ARM subsystem FLASH tests do not erase the software image SoC HyperTerminal Unlicensed Jod File Edit View Cal Transfer Help ARM Memory Tests SDRAM Stuck Address SDRAM Rolling Bit SDRAM Alternating Data SDRAM Odd Address CODERAM Stuck Address CODERRM Rolling Bit CODERAM Alternating Data CODERRM Odd Address LD ST RAM Stuck Address LD ST RAM Rolling Bit LD ST RAM Alternating Data LD ST RAM Odd Address Flash ID Register Test Flash Stuck Address Flash Rolling Bit Flash Alternating Data Command ESC Exit TOD Be Kew 20 90 17 0 Connected 0 05 19 Auto detect 115200 8 N 1 b Direct Memory Access DMA Test the general DMA of SoC in Descriptor or Simple mode SoC HyperTerminal Unlicensed Jotg File Edit View Call Transfer Help ARM DHA Tests a DMA Descriptor b DMA Simple C
28. FUJITSU SoC Reference Kit User Manual vi a i Fujitsu Microelectronics America Inc Corporate Headquarters 1250 East Arques Avenue M S 333 Sunnyvale California 94088 7470 Tel 800 866 8608 Fax 408 737 5999 E mail inquiryQfma fujitsu com Web Site www fma fujitsu com 2005 All rights reserved PN 5720 6104 Rev 1 1 SoC Reference Kit User Manual TABLE OF CONTENTS 1 1 VI Reference NEON 1 1 2 SoC Reference Board 1 PA CCL UNO DR 1 1 2 2 IPOWOI OUDDIV ur 3 1 2 3 JE FOCCSSON 3 1 2 4 Upper Media Access Control UMAC Processor Peripherals 3 VES OS 3 265 erai 3 1 2 7 Baseband and RF Interface Connector 4 1 2 8 External Processor Interface Connector sse 4 1 2 9 Debugger Board Interface Connector srera e a a N 4 1 2 10 232 01 6 4 1 2 11 ARM Debug 4 1 2 12 ARM Embedded Test Module ETM 4 1 3 SoC Baseband Board eaa 4 1 4 SoC Debugger Board Specifications aaa a a a a 4 2 Quick start GE
29. G 5v 45V ANALOG LDO JOHLNOD OOXLOA Tx Rx l amp Q X analog signals TN Debugger Connector J14 Debugger Connector J3 Debug Board SS AGG RF 1 Note There will be two variants of the CONTROL ARM GPIO SOC Evaluation board a Subscriber LOGIC ARMIRQs1 Station SS variant and a Base Station 1 BS variant Components that are only required on one variant will be ic ic ogic ic ARC DEBUG designated as SS variant or BS nalyzer nalyzer DB25 amp 1284 variant Figure A 1 SoC Reference Board Block Diagram A 2 September 2005 SoC Reference Kit User Manual 2 POWER SUPPLY The SoC Reference Board requires a 48VDC input voltage 1A when configured as an SS When configured as a BS the current requirement is 1 5A The input voltage range can be 37VDC to 60VDC The 48V power supply can be connected to the SoC Reference Board via a 2 5mm ID 5 5mm OD DC power jack barrel connector J6 Inner pin is positive Diode protection against polarity reversal is provided The 48V power supply feeds an isolated 48V to 12V power module This power module feeds DC to DC converters to generate the following voltages 1 8VDC Q24A SOC core voltage e 3 3VDC 0 5A 6A SoC 1 0 voltage and digital components 0 5A Provides power to PowerPC Board in BS configuration 6A e 6VDC 1 5A Analog components on SoC Reference Board RF circuitry on
30. Local Bus Byte Enable Ethernet Enable for Tx Data Bus Ethernet Rx Clock Ethernet Rx Data Valid Ethernet Collision Ethernet Carrier Sense Ethernet Rx Data Bus Ethernet Rx Data Bus Ethernet Rx Data Bus Ethernet Rx Data Bus Ethernet Management Data Input Output Ethernet Management Data Clock ARM General Purpose Input Output SDRAM Clock Enable UART Serial Tx Data ARM General Purpose Input Output A 16 September 2005 SoC Reference Kit User Manual Table 15 J 3 Pinout Debugger Connector continued Pin SSName BSName 55 Description BS Description 82 63 RXDI 1 UART Serial Rx Data 84 SD CLK SDRAM Clock 1389 2 Powerupreset __ ___________ 86 GND 87 SPARE 88 GND 89 SPARE 90 GND 91 SPARE 92 3V3 93 SPRE 94 GND 95 SPARE 96 3V3 97 3V3 98 3V3 99 3V3 100 3V3 101 GND 103 MD00 Data Bus Local Bus Data 104 MDOI Data Bus Local Bus Data 105 MDO2 LBD02 DataBus LocalBus Data gt 106 G N D RARE NERE SE EEE NN NE EE 107 MD03 Data Bus Local Bus Data 108 MD04 8004 DataBus 10 485 gt 109 MDO5 j Data Bus 1 1004850488 amp 111 MD06 DUVO _ DataBus LocalBusDaa 112 MD07 Data Bus Local Bus Data a 113 MD08 18008 Data Bus LocalBus Data gt 114 GND LA 115 MD09 Data Bus Local Bus Data 116 MD10 L Data Bus Local Bus Data
31. M Simple Debugger a Poke b Peek Command ESC Exit Connected 0 11 32 Auto detect 115200 8 N 1 3 1 5 802 16 PHY Tests Menu The PHY Test Menu allows read and write access to the PHY registers When writing to the PHY registers the software default value to the registers is overwritten By having PHY register access the user can experiment with different PHY settings The PHY Test Menu has three 3 options that are used to interface the ARM to the PHY registers For the PHY register memory map listing see the MB87M3400 data sheet EA soc HyperTerminal Unlicensed BAX File Edit View Call Transfer Help Dls E 802 16 PHY Tests a Poke b Peek c gt Phy Test Tone Command ESC Exit lt gt Connected 0 13 32 Auto detect 115200 8 N 1 a Poke Manipulate the PHY control registers You are prompted to provide a PHY register address and the desired value of that register in Hexadecimal b Peek Read the contents of a PHY register You are prompted to enter a PHY register address in Hexadecimal in order to display the contents of the register c Phy Test Tone Generate a sinusoidal signal Turn the test tone utility on off and manipulate the phase size and tone of the test tone CER Terminal Unlicensed Jn Ed Yew Gal Transfer o os n PHY Test Tone Menu ja Test Tone OFF b Phase Control Frequency Step Size d Fre
32. MO4F3652CT CALCHI RMO4F3921CT CALCHP RMO4F4320CT CALCHI RMOAFATSICI CALCHP R117R406R534 535 RES 0402 499 OHM 0 062W 1 RMO4F4990CT CAL CHIP RMOFISSICT CALCHI RMO4F4992CT C R 195 197 R 199 R 202 205 R219 221 R251 252 ON SEMI gt gt lt R268 270 R273 R280 R 282 285 R 339 366 R 368 377 R538 14 R4 R35 838 845 R49 899 RES 0402 49 90HM 0 062W 1 RMO4F49R CAL CHIP R139 R141 R266 R278 R 386 389 1 50 210 211 R216 RES 0402 75 00HM 0 062W 1 RMO4F 75ROCT CAL CHIP 217 R327 RES 0603 4K75 196 3EKF4751 PANASONIC R52 R63 64 RES ARRAY ISOLATED 33RX12 5 PRN1102433R 0 CMD R28 R267 RES ARRAY BUSSED 10KX155 PRN111161002 CMD 2 D5 D601 DIODE STKY RECT 2A 60V MBRS260T3 A 35 September 2005 SoC Reference Kit User Manual Part Number Manufacturer DIODE ULTRAFAST RECT 200V 3A MURS320T3 ON SEMI 1 D10 DIODE ZENER 6 2V 200MW MM3Z6V2T1 ON SEMI 500323 SLVU2 8 8 EPD DIODE ARRAY SLVU2 8 8 TB E PROTEK D4 D600 DIODE SW HISPD 100V 0 24 50723 MMBD914LT1 MOTOROLA 0103011 MOSFET PWR N CH 100V 6 9A IRF7420 INT RECTIFIER SOIC 8 Q2 Q4 5 Q8 9 MOSFET PWR N CH 20V 7 0A IRF7401 INT RECTIFIER SOIC 8 5 SWNOPBRAPCBMOUNT KTIIPZSM SWITCH HALF PITCH DIP 97 085 GRAYHILL XFORMER SINGLE 10 100BTX 16110 5050 2 HALO SOIC 06 7 010 012 TRANS NPN 3904 1A 50123 MMBT3904 FAIRCHILD 5 1 2 1 A 36 September 2005 SoC Reference Kit User Manual APPENDIX 5 REFERENCE B
33. NTRST GND ARM TDI GND ARM TMS GND ARM TCK GND ARM RTCK GND ARM TDO GND PRESET GND DBGRQ GND DBGACK GND A 30 September 2005 SoC Reference Kit User Manual Table 21 19 Pinout ARM MultiTRACE Connector Pin Name Description gt N A N A N A N A GND TRACECLK DBGRQ DBGACK PRESET N A ARM_TDO 3V3 ARM_RTCK 3V3 ARM_TCK TRACEPKT7 ARM TMS TRACEPKT6 ARM TDI TRACEPKT5 ARM NTRST TRACEPKT4 GND TRACEPKT3 GND TRACEPKT2 GND TRACEPKT1 GND TRACEPKTO GND TRACESYNC GND PIPESTAT2 GND 5 1 GND PIPESTATO ARM Pipeline Status lt Ww Ne 31 September 2005 SoC Reference Kit User Manual APPENDIX 4 REFERENCE BOARD BILL OF MATERIALS BOM Qty Reference Description ParNumber Manufacturer CAP ELEC SMD 33UF 100V PANASONIC AV AVX C4 14 C21 C25 C 32 34 CAP CERAMIC 1210 10UF 10V X5R 1210ZD106KAT2A AVX 57 60 C64 65 C 75 84 C86 96 C205 206 C210 C413 C415 416 C 420 427 1 C207 CAP MONO 0402 25V 2 6501100 COG 2 C97 C209 CAP MONO 0402 100PF 50V 5 04025 101 2 COG C27 C44 C66 69 C601 CAP MONO 0402 1000PF 50V 5 04025 102 2 XTR 12 C26 C61 63 98 99 C216 CAP CER 16V 0 01UF 16V 10 0402Y C103KAT2A 220 222 C232 C412 XTR 0402 1 3 15 20 C28 29 C42 CAP CER 10V 0 10 10 0402 X5R 0402ZD104KAT2A C101 145 C148 200 C203 204 C212 C223 231
34. OARD SCHEMATICS Schematics of the SoC Reference Board and the RF Boards are included on the SoC Reference Kit CD Rom in PDF format A 37 September 2005
35. Radio Board e 8 5VDC 1 5A Tx power amp on Radio Board e 5VDC 0 1A Analog components on SoC Reference Board The 1 8V core and 3 3V I O rails are generated by Point of Load POL modules The 6 0V and 8 5V rails are generated by LT1765 DC to DC converters As RF circuitry is sensitive to power supply noise the power supply rails for the Radio Board are kept separate from power supply rails for the SoC Reference Board The 6 0V rail is partitioned into the 6 0VRF rail which feeds the Radio Board and the 6 0VA rail which feeds analog components on the SoC The 8 5V power supply rail only feeds the Tx power amp on the Radio Board The SoC requires that power supplies be sequenced as follows 1 8V core gt 3 3V I O gt 1 8V analog on power up The Intersil ISL6123 provides this sequencing On power up it will sequentially turn on load switches that are gating these power supply rails 3 DIGITAL ENGINE 31 Clocks A 20 MHz VCTCXO is the main clock source for SoC Reference Board It outputs a sinusoidal signal and feeds the RF LO intermediate Frequency IF LO on the RF Board and digital Phase Locked Loops PLLs on the SoC The SoC s PLLs generate the following clocks e 160MHz ARM subsystem Clock REFCLK1 8 e 160MHz ARC subsystem Clock REFCLK2 8 100MHz PHY subsystem Clock REFCLK3 5 e 40 MHz DDS Synthesis Clock ARCCLK A All of the above clocks are shown with default rates However each clock can be set to d
36. SPARE SPARE GND 5V 3V3 5V 3V3 5V 3V3 GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE SPARE GND SPARE SPARE 21 September 2005 SoC Reference Kit User Manual Table 16 14 Pinout Debugger Connector continued Pin Description __ 0 0 0 0 000 0 88 89 90 91 92 93 94 95 SPARE GND SPARE TX_EN RX EN GND TR SW LD ILD GND CTRL6 CTRL7 SPARE GND SPARE SPARE SPARE GND SPARE AGC STRB SED CLK GND SED DATA SED FS SPARE SPARE BS SYNC IN BS SYNC OUT FT INT SPARE SPARE AGC CTRL8 AGC CTRL9 Tx Enable Rx Enable TX Rx Switch Automatic Gain Control Bus Automatic Gain Control Bus Automatic Gain Control Strobe Symbol Error Display Clock Symbol Error Display Data Symbol Error Display Frame Synchronization Base Station Synchronization Input Base Station Synchronization Output Frame Timer Interrupt Output Automatic Gain Control Bus Automatic Gain Control Bus A 22 September 2005 SoC Reference Kit User Man
37. TCXO and DDS for generation of all system clocks e Memory components Flash and SDRAM e Debug development connectors ARM MultilCE ARM MultiTRACE ARC Debugger RS232 serial port e Ethernet PHY and connector e PowerPC connector for half duplex BS testing e HF Board connector for connecting a RF deck such as the Radio Board e LEDs and DIP Switches for aiding software development system integration e External high speed I amp Q ADC and DAG e Reset supervisory and push button With the Radio Board the SoC Reference Board implements an 802 16 SS In the BS build configuration the SoC Reference Board can interface to a GDA MPC8560 PowerPC board to implement a half duplex BS 802 16 SoC Reference Board Main Eval Board DC PWR RJ45 Ethernet PHY CONNECTOR Ka Reset Push 2 Button OR and Supervisory 4 gt ARMICE 20MHz VCTCXO Buffer PLL2 PLL3 gt Rs232 PowerPC 48 5VPA Evaluation Memory amp External Device TOEN VCTXCO CONTROL 802 16 SOC 4 Interface EMB DDS CLK Tx 18 Q Data LBCLK amp FEEDBACK Rx amp Q Data 6V ANALOG Sampling Clock Sampling Clock Tx Analog ARM 6V RF Rx Analog 5V ANALOG 3 3V I O ARC GPIO amp IRQs 3 3V for PowerPC LEDs 1 8V CORE pil PLL 46V ANALOG O 1 8V 1 8VANALOG Tx Rx CONFIG LDO 2x8 POLE DIPSW 46V ANALO
38. able the Automatic Gain Control AGC of the receiver AGC Atten Value Specify a desired level of constant attenuation to control the Rx signal This setting is used when AGC is disabled but a specific amount of attenuation is desired Bandwidth Setting Choose between the 3 5 MHz and 7 0 MHz data bandwidth 11 September 2005 SoC Reference Kit User Manual Refer to Figure 6 for items k I and o below k TXStart Delay Time between when Tx is enabled and data is actually transmitted Maintain the default setting of 0x25 TX Stop Delay Time delay between the end of Tx and when the system returns to the Tx enable low setting Maintain the default setting of 0x25 m TX RX Delay Time delay between a Tx enable low setting and an Rx enable high setting Maintain the default setting of 0x50 n RX Start Delay Time delay between an Rx enable high setting and data being received Maintain the default setting of 0x0 o TR Switch Delay Time delay between Tx enable high and TR SWITCH high Maintain the default setting of OxO p DAC ADC Int Ext Maintain the default setting of internal as the external DAC and ADC are not connected to the output and can only be used to capture data 10 DAC Output Control BB DAC output amplitude adjustment setting for baseband configuration r DAC Output Control RF DAC output amplitude adjustment setting for RF configuration s Bit Error Rate BER Resolution Ratio
39. ammed with a modified register value If you need to program the RF do this after you manually modify each register value SoC HyperTerminal Unlicensed MEN File Edit View Call Transfer Help RF Board Registers Read Only REGO value 0x006120a0 b RE61 value 0x00066181 c REG2 value 0x00002282 d RE63 value 0x00025f03 e RE64 value 0x00006186 f REG C value 0x00050004 g REG PD value 0x00000005 Command ESC Exit _ lt gt Connected 0 02 53 Auto detect 115200 8 N 1 a Set REGO Value Modify the SYSO register of the RF chip b Set REG1 Value Modify the SYS1 register of the RF chip c Set REG2 Value Modify the SYS2 register of the RF chip d Set REG3 Value Modify the SYS3 register of the RF chip e Set REG4 Value Modify the SYS4 register of the RF chip f Set REG C Value Modify the SYS C register of the RF chip g Set REG PD Value Modify the SYS PD register of the RF chip 3 1 4 ARM Subsystem Tests Menu The Arm Subsystem Tests Menu lists six 6 specific sets of tests for ARM as described below lt EA soc HyperTerminal Unlicensed File Edit View Transfer Help ARM Subsystem Tests a gt Memory b gt e gt Timers amp WDT f gt Debugging Command ESC Exit _ Connected 0 04 34 Auto detect 115200 8 N 1 a Memory Internal and external memory tests for ARM as follows e S
40. ble 17 J 23 Pinout RF Board Connector continued Pin Description O 00 0 Voltage for power amp Switched by TX EN A 25 September 2005 SoC Reference Kit User Manual Table 18 J 20 Pinout PowerPC Board Connector ARM GPIO24 SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE ARM GPIO22 SPARE SPARE PPC LSYNC IN SPARE GND SPARE PPC LSYNC OUT SPARE GND ARM GPIO6 SPARE CSCL GND CSDA SPARE ARM GPIO2 GND SPARE LB CLK ARC GPIOO GND ARC GPIO1 SS Description BS Description ARM General Purpose Input O utput ARM General Purpose Input O utput PowerPC Local Bus Synchronization Input PowerPC Local Bus Synchronization Output ARM General Purpose Input O utput ARM General Purpose Input O utput Local Bus Clock ARC General Purpose Input O utput ARC General Purpose Input O utput A 26 September 2005 SoC Reference Kit User Manual Table 18 J 20 Pinout PowerPC Board Connector continued Pin SSName BSName SS Description BS Description 42 SPARE 43 44 45 FTINT 1 46 SPARE gt 47 BS SYNC OUT PEEEa ases _ 20 48 SPARE 49 SPARE 50 SPARE 21 SPARE 52 SP
41. ch Output ARM 11 N A Not Used N A ARM 12 N A Not Used N A ARM GPIO13 N A Not Used N A ARM GPIO14 N A Not Used N A ARM 15 N A Not Used N A ARM GPIO16 N A Not Used N A ARM_GPIO17 N A Not Used N A ARM 18 N A Not Used N A ARM GPIO19 N A Not Used N A ARM GPIO20 N A NotUsed N A ARM GPIO21 PD SE7051L Power down for SE7051L Output ARM GPIO22 SIGE LE SE7051L Microwire Latch Enable Output ARM GPIO23 ATT 20 Tx Power amp 20 dB Attenuation Output ARM GPIO24 Table 3 Interrupt Assignment IRQX Device Description 0 ARM EXT 1800 FT INTfromSoC 1 1801 Flash Read Write Not Used Not Used Not Used SDRAM Read Write Not Used Spare SDRAM chip select A 5 September 2005 SoC Reference Kit User Manual Table 5 Configuration Pins Description SS mode BS mode CMODE Disables ARM subsystem when high Used for BS mode 0 ARM Enabled 1 ARM Disabled BOOT 1 0 Selects 8 16 or 32 bit boot device 01 16 bit 00 PLL1 SPEED 1 0 Selects ARM subsystem PLL clock freq 140 160 180 01 160MHz 00 N A or 200MHz PLL2 SPEED L 0 Selects ARC subsystem PLL clock freq 140 160 180 or 200MHz PLES SPEED Selects PHY subsystem PLL clock freq 60 or 100 MHz PLL1_S ARM PLL enable PLL2_S ARC PLL enable PLL3 5 PHY PLL enable 01 160MHz 01 160 2 100 2 1 100 2
42. ember 2005 SoC Reference Kit User Manual 1l OVERVIEW The System on Chip SoC Reference Kit is designed for Institute of Electrical Electronic Engineers IEEE 802 16 2004 WIMAX product developers for evaluation of WiMAX solutions from Fujitsu The SoC Reference Kit includes the necessary software and hardware components to achieve a cost effective fixed Broadband Wireless Access BWA system solution for e Low cost subscriber stations SS e Enterprise SS and e Base stations BS The Fujitsu 802 16 platform enables a BWA platform for SS or BS It includes e Compliance with IEEE 802 16 2004 standard specification e Media Access Control MAC portability to different Real Time Operating System RTOS e MAC security sublayer for SS authentication and data encryption e Multiple service class support to differentiate service quality e Dynamic service management to activate the service class when needed 1 1 Reference Kit Content The SoC Reference Kit consists of a combination of hardware and software components The three 3 main components are the e SoC Reference Board with the 802 16 WiMAX SoC Integrated Circuit IC core processor e Software package to run the SoC and the Reference Board and e Software package to install the SoC Reference Kit as a half duplex WiMAX SS Figure 1 shows the hardware components included in the SoC Reference Kit while Figure 2 illustrates the relationships between hardware and software c
43. ended as the firmware will be lost SoC HyperTerminal Unlicensed Job File Edit View Call Transfer Help WARNING This will cause all contents in flash to be erased including this program Erase flash Do you want to erase the entire flash memory y n Connected 1 59 26 Auto detect 115200 8 N 1 c Version Information Display version information for the SoC Reference Board software EA soc HyperTerminal Unlicensed Job File Edit View Call Transfer Help De 83 08 Version 1 3 Build Date Jul 20 2005 13 46 09 Uptime 0 2 28 80 Press SPACE to continue lt gt Connected 2 00 09 Auto detect 115200 8 N 1 3 1 8 Save and Restore Configurations Menu The Save and Restore Configurations Menu has three 3 options as described below SoC HyperTerminal Unlicensed Job File Edit View Call Transfer Help DF 83 05 Save And Restore Config a Restore Config Defaults b Reload Last Saved Config c Save Config Command ESC Exit Auto detect 115200 8 N 1 a Restore Config Defaults Rollback the configuration parameters to factory default settings b Reload Last Saved Config Load the last saved configuration parameters into the system c Save Config Once you are satisfied with the configuration settings save them on the Flash chip for future access 19 September 2005 SoC Reference Kit User Manual
44. erial Properties Country region Emer the area code without the long distance prefix Ares code Phone numb Connect using Conhgure September 2005 SoC Reference Kit User Manual 3 he Com Properties screen shows the Port Settings tab Configure the port settings as shown below then click OK to confirm and return to the Serial Properties screen COMS Properties Pot Stings Bits per second 4 Data 3 Nene Stop bes 1 Flow contol None Dataults 4 Inthe Serial Properties screen select the Settings tab and configure it as shown below Serial Properties Connect To Function arrow and keys act 8 Temunal keys 7 Windows keys Backspace key sends Crk Space Emulation WT 1G Terminal Setup Taket terrm ID BEackserall bulter hrs sound whan connecting disconnecting 5 Return to the main HyperTerminal window Select Call Call to initiate communication with the SoC Reference Board Serial HyperTerminal View B Transfer Hep Wat for a Cal Conne cts t remote system September 2005 SoC Reference Kit User Manual 2 3 Installing Heatsink and Powering Up The procedure for installing Heatsink and powering up the SoC Reference Board is given below Figure 3 identifies the components mentioned in this procedure 1 Remove the clear pla
45. fault 180MHz 200MHz PLL3 Multiplier PLL3 Frequency PHY ON 3 60MHz OFF 5 100MHz default Table 9 umper Settings 17 RF Board FE AGC routing 1 2 ARM 6 4 routed to FE AGC 2 3 AGC_CTRL 6 8 routed to FE AGC default J5 ARM BYPASSYNC control Mustbe installed for MultilCE to work 8 19 only present 20MHz Clock J 8 installed RF board drives clock on Rev D J 9 installed On board VCTCXO drives clock Either 8 9 to be installed not both If no RF board is installed J 9 must be installed for SoC to boot September 2005 SoC Reference Kit User Manual 3 6 Memory Devices SDRAM 128Mb of SDRAM is configured as 4M x 32b SDRAM is used for program execution and data storage The SDRAM clock is 80MHz generated by the ARM subsystem s 160MHz clock ARMCLK 2 The footprint is compatible with 256Mb and 512Mb devices The SDRAM device is Micron P N MT48LC4M32LFB5 10IT Flash The 32Mb of flash memory is configured as 2M x 16b Flash memory is used for the boot loader and program images for the ARM and ARC subsystems The footprint is compatible with 64Mb and 128Mb devices The Flash device is Micron P N MT28F320J3BS 1 1 ET Signal VPEN ARM GPIOO is used for write protection 4 RS 232 INTERFACE An RS 232 Interface connects to a terminal port to provide a menu driven user interface for SoC configuration Universal Asynchronous Receiver Transmitter UART in the ARM s
46. ic generation see also Section 3 1 6 2 4 2 RF Traffic Procedure 1 Configure two 2 SoC Reference Boards as shown in Figure 5 2 Install an RF board on each of the SoC Reference Boards 3 Access 60db of RF attenuation rated to at least 3 6GHz Then use adapters to couple the attenuation between the two RF Boards to prevent damage 8 September 2005 SoC Reference Kit User Manual 4 Make sure that the shunt at J8 is installed and the shunts at J11 and J9 are removed 5 From the SoC Main Menu Section 3 1 1 select 5 Traffic Application a Run Traffic to start traffic generation see also Section 3 1 6 J5 RXQ J23 RF Connector Q J20 External Processor J16 SED 419 J1 MultilCE BEGG UNNE 51 0 Switch S3 Reset S2 DIP Switch Ethernet Traffic Generator SmartBits To PC Serial Port 48V Power Supply J20 External Processor 423 RF Connector J16 SED O J19 MultiTrace J1 MultilCE ST DIP S
47. ifferent rates as follows e ARM clock 140 160 180 or 200 MHz e ARC clock 140 160 180 or 200 MHz e PHY clock 60 or 100 MHz and e DDS clock 40 80 or 160 MHz A 3 September 2005 SoC Reference Kit User Manual The VCTCXO frequency is centered on 20 MHz and is adjustable 10ppm by the AFC function in the SoC The AFC adjusts the VCTCXO frequency such that errors in the receive data from the access point are minimized The front end clock for PHY subsystem is required to be variable to implement variable bandwidth This is also used as the sampling clock for amp Q ADC and DAC The front end clock is generated by a Direct Digital Synthesis DDS device U7 AD9834 Table 1 shows the bandwidths supported by the SoC Reference Board Each bandwidth has different filtering requirements in Baseband IF RF domain The Radio Board only supports a bandwidth of either 3 5 or 7 0 MHz depending on the build configuration SAW filter Table 1 Supported Bandwidths Front End Clock 1 5 MHz 3 440 MHz 3 0 MHz 6 880 MHz 5 5 MHz 12 640 MHz 1 75 MHz 4 000 MHz 3 5 MHz 8 000 MHz 7 0 MHz 16 000 MHz 10 0 MHz 23 040 MHz 14 0 MHz 32 000 MHz 20 0 MHz 46 080 MHz 3 2 Reset and Power Management Power management is controlled by a voltage monitoring supervisor which holds the SoC at reset until the 3 3V I O and 1 8V core supplies are up If the 3 3V I O falls below 88 or the 1 8V supply falls below 95 the voltage monitoring su
48. nally routed to on chip high speed ADC and DAC These signals are also available in digital format for interfacing to external ADC and DAC 6 8 Symbol Error Display SED SED allows monitoring of PHY parameters for the purpose of debugging Debugging is not limited to PHY testing but also RF testing in the field Some parameters can be monitored without a software interface while others require a software interface to read registered values The SED output is a 3 wire SPI interface designed to support a 12 bit serial DAC such as Texas Instruments TLV5616 On the SoC Reference Board SED interfaces with TLV5616 The output of TLV5616 is available on an MCX connector J16 7 RF AND ANALOG 71 RF Circuit Interface Signals The RF circuit signals interface with the SoC on the Radio Board Table 13 RF Circuit Interface Signals Type Direction CTRL 9 0 Automatic Gain Control bus to control the Rx signal level on the Radio Board AGC STRB ILD LD Digital Input TX EN RX EN TR SW RF ENABLE RF ENABLE Signal to allow external processor to enable the PHY RF interface when operating in BS mode TX DETECT Analog Input RX PWR DETECT Analog Input ATX OUT Analog Output 0 00 Analog Output ARX I IN 4 Analog Input High speed 10 bit ADC differential analog input pair 11 September 2005 SoC Reference Kit User Manual Table 13 RF Circuit Interface Signals continued Signal Description T
49. nected to the power down pin of the RF chip This pin should be off for normal operation of the RF Board Rf chip PM bit Manipulate the PM bit of the SYSO register of the RF chip Set Center Freq KHz Setup the RF center frequency When the system is configured for TDD mode you are prompted for a single center frequency that will be used for both Tx and Rx In FDD mode you are prompted to enter a Tx frequency and an Rx frequency Refer to Section 3 1 2 c Enter all frequencies in KHz Tx and Rx frequencies must be reversed between Slave and Master for proper operation It is important to ensure that the RF Board is capable of FDD mode operation before attempting this configuration In FDD mode Tx and Rx frequencies must be separated by 1MHz and the frequency channels must be 1MHz apart The possible ranges of frequencies are e 3 5MHz BW TDD radios Center frequency range between 3 401 750 to 3 500 000KHz in 250KHz increments e g Fc 3 401 750 250n where n 0 393 3 5MHz BW HD FDD SS Slave radios Tx center frequency range between 3 401 750 to 3 500 000KHz in 250KHz increments e g Fc 3 401 750 250n where n 0 393 Rx center frequency range between 3 501 750 to 3 600 000KHz in 250KHz increments e g 3 501 750 250n where 0 393 e 3 5MHz BW HD FDD BS Master radios Tx center frequency range between 3 501 750 to 3 600 000KHz in 250KHz increments e g 3 501 750 250n where 0 393 Rx center
50. of incorrect bits to the correct bits The BER Resolution conveys the accuracy of the BER For example a 10 3 ratio reflects a BER out of 1000 bits and a 10 9 ratio reflects a BER rate out of 1 billion bits 4 WL J LL gt 4 x Rx Delay I I I gt e gt e txStartDelay txStopDelay gt trSwDelay Figure 6 Tx and Rx Start Stop Delay 3 1 3 RF Board Configuration Menu Use the RF Board Configuration Menu to configure the RF Board Each submenu is detailed below soc HyperTerminal Unlicensed Jod File Edit View Call Transfer Help De 95 08 RF Board Configuration a Program with Default Settings B Power down exse esas eves ooo HT chip PM cess cess orii ees th Set Center Freq kHz 9500000 e Transmit Power Attenuation 0 95 dB 10 dB f 20dB attenuator 1 10 Tx FE AGC Gain 8 35 5dB 10 h Tx AGC gain 0 58 1dB 0 1 Ix mixer gain 0 6 12 18 dB 12 j Show Registers Command ESC Exit _ lt gt Connected 0 02 17 Auto detect 115200 8 N 1 12 September 2005 SoC Reference Kit User Manual Program with Default Settings Program the RF Board to factory default settings The contents of the registers will reflect these default settings Power down pin Control the digital line con
51. ommand ESC Exit Connected 0 08 03 Auto detect 115200 8 N 1 c GPlO Test the input output functionality of the pins 4 11 of the ARM subsystem soc HyperTerminal Unlicensed Jod File Edit View Call Transfer Help ARM GPIO Tests a GPIO Output b GPIO Input Command ESC Exit Connected 0 08 22 Auto detect 115200 8 N 1 d Read the temperature C of the SoC chip as measured by the on chip sensor SoC HyperTerminal Unlicensed Jod File Edit View Call Transfer Help ARM I2C Tests 12 Command ESC Exit Connected 0 09 23 Auto detect 115200 8 N 1 15 September 2005 SoC Reference Kit User Manual e Timers amp WDT Verify that Timers 1 2 3 and the Watchdog Timer WDT are working Testing the Timers and WDT does not reset the SoC Reference Board EA soc HyperTerminal Unlicensed ab File Edit View Call Transfer Help Dg 83 Df EF ARM Timer Tests Timer 1 Timer 2 Timer 3 WOT Timed Command ESC Exit _ coco Connected 0 03 41 Auto detect 115200 8 N 1 f Debugging Access two 2 ways to probe the ARM subsystem Poke allows you to set a 32 bit value at a specific address location Peek allows you to see the contents of a memory location SoC HyperTerminal Unlicensed BAX Fie Edit View Call Transfer Help Dar 83 05 AR
52. omponents of the SoC Reference Kit The SoC Reference Board has a high density connector that can be attached to either a Baseband Adaptor Board or an Radio Frequency RF Evaluation Board from SiGe Semiconductor Use two 2 SoC Reference Kits to create a simple point to point network or purchase additional SoC Reference Kits to expand to a point to multipoint network Additional RF boards can be purchased to evaluate other RF configurations e g duplex mode or channel bandwidth The software included in the SoC Reference Kit allows the user to customize operational configurations 12 SoC Reference Board Specifications 1 2 1 General e Duplexing Half Duplex Frequency Division Duplexing HD FDD or Time Division Duplexing TDD e Channel BW 1 75 to 20MHz e Wire Interface Ethernet 10 100BT e Radio Interface Baseband 3 5GHz Band e Operating Temperature Range 40 C to 85 C 1 September 2005 serial Port Cable One software image _ running at a time SoC Demo Test Software WiMAX System Demo Software SoC Reference Kit User Manual Figure 1 Hardware SoC Reference Kit high density connectors Fower Supply amp Cable Set Cl connector Baseband Adaptor Board gt Wi LAN gt 35 10 MHz bandwidth RF Eval Board T1 TDD gt SiGe 802 16 3 5GHz RF chipset gt 3400 3500 MHz 3500 3600 gt 35 MHz bandwidth RF Eval Board F1 H FDD BS gt
53. pervisor will reset the SoC SoC can be reset manually by pressing push button 53 or by the voltage monitoring supervisor After SoC is resent the ARM subsystem boots up and holds ARC and PHY in reset mode ARM then loads the ARC software into the on chip ARC code memory and releases it from reset mode When ARC boots up it releases the PHY from reset mode 3 3 Digital Engine e Interfaces to flash memory 16 bit data bus and SDRAM memory 32 bit data bus e Interfaces to ARC core through internal Advanced High Performance Bus AHB bus e Mllinterface to Ethernet Transceiver A4M79C874VI e HS 232 terminal interface to provide user interface to SoC Reference Board configuration e Configures PLL synthesizers and Tx power settings on RF board e Configures sampling clock frequency synthesizer AD9834 DDS through SPI port A 4 September 2005 SoC Reference Kit User Manual Table 2 ARM I O Pin Assignment Signal Description Type Location Comments VPEN Flash Program Enable Output ARM GPIOO RESET Ethernet Transceiver Reset Output ARM GPIOI RF MEM WP RF EEPROM Write Protect Output ARM GPIO2 N A Not Used N A ARM FE AGC2 FE Tx Attenuation Output ARM GPIO4 FE AGCI FE Tx Attenuation Output ARM GPIO5 FE AGCO FE Tx Attenuation Output ARM_GPIO6 SIGE_DATA SE7051L Microwire Data Output ARM_GPIO9 SIGE_CLK SE7051L Microwire Clock Output ARM_GPIO10 ANT A B SW Antenna A B Swit
54. plexer 035 SN74CB3Q3257 is required to properly interface these signals to the SE7351L The external multiplexer is controlled by a TR SW signal In Tx mode GPIOs are routed to the FE AGC signals of SE7351L while in Rx mode AGC signals are routed to SE7351L 74 Power Monitoring Monitor the power of the ADC radio receiver and transmitter The voltage range for power monitoring is set internally in SoC at 0 825V 2 475V This range can be overridden by driving the ADC2_VRH and ADC2 VRL pins of the SoC A 12 September 2005 SoC Reference Kit User Manual SoC pins for power monitoring are RX POWER DETECT and TX POWER DECTECT These are exposed at the RF Board connector J23 The Radio Board has an AD8318 HF logarithmic power detector for Tx power detection It is connected to the TX POWER DETECT pin of the SoC 75 AFC AFC is implemented by tuning 2OMHz VCTCXO by 10 ppm SoC has a 12 bit AFC DAC for interfacing to the VCTCXO adjustment signal DAC output comes out at VCTCXO_CNTL The AFC DAC voltage range is set to 0 5V 2 5V at pins ADC2 VRH ADC2_VRL to match Temex DVT4564A tuning voltage requirement of 1 5V 1 0 for adjustment of 10 ppm 7 6 RF Power Control and Monitoring Tx power is controlled by the RF chipset through the Microwire interface and through the FE AGC 2 0 and ATT20 signals ARM 4 6 ARM GPIO24 This is controlled by the ARM subsystem The Radio Board has an AD8318 powe
55. quency Control Command FSC Fxitl 16 September 2005 SoC Reference Kit User Manual 3 1 6 Traffic Application Menu The Traffic Application Menu has only one option Run Traffic soc HyperTerminal Unlicensed Job File Edit View Call Transfer Help Traffic Application a Run Traffic Command ESC Exit lt gt Connected 0 16 14 Auto detect 115200 8 N 1 a Run Traffic Start the Traffic application In Master mode Run Traffic commands SoC to transmit the Ethernet packets received at the RJ45 jack out through the PHY In Slave mode with no Master connected Run Traffic does not transfer data because the Slave is dependant on the Master Board to start the traffic process If a Master and Slave are both used in either a Baseband or RF setup the Slave will immediately sync to the signal transmitted from the Master to establish bi directional traffic between the Slave and the Master Boards see Section 3 1 2 a Run Traffic also provides some statistics such as number of Ethernet packets received transmitted and the number of PHY frames received transmitted Receiver Sensitivity Signal Strength RSSI and BER are also displayed on the screen The screenshots below show the traffic startup sequence for each type of Master Slave configuration 17 September 2005 Traffic Startup Sequence 151 soc HyperTerminal Unlicensed Job Ele Edit View Call Transfer Help
56. r monitoring device for monitoring Tx power The RF signal is converted to a voltage that represents the power in dBm Power control for the Radio Board is user settable for up to 30 dBm This device is connected to the TX PWR DETECT signal of SoC which is connected to an on chip 10 bit ADC ADC is read by the ARM subsystem through the APB bus 1 7 RF Chipset Configuration The ARM subsystem is responsible for writing configuration data to the SE7051L chip on the Radio Board in order to set the IF and RF frequencies and Tx power The signals required for the Radio Board configuration are SIGE DATA SE7051L configuration data e SIGE CLOCK Clock for sending SE7051L configuration data e SIGE LE Latch enable for updating SE7051L with configuration data e FE AGC 2 0 SE7351L Tx power setting e ATT20 Tx power amp 2098 attenuation 7 8 RF Amplifier Control LD LD Lock detection signals that indicate when the RF PLLs are locked LD LOW while LD HIGH The LD signal is active when the IF and RF PLLs on the Radio Board are locked Both the LD and LD signals must be locked for the TX EN RX EN and SW signals to operate TX EN Enables the transmit amplifier and the transmit paths for the SE7351L and SE7051L on the Radio Board RX EN Enables the receive paths for the SE7351L and SE7051L on the Radio Board amp Q High Speed ADC DAC Digital data transmitted from the PHY is converted to analog using a pair of 1
57. rnet isolation transformer This secondary transformer interfaces to the Ethernet transceiver The Ethernet transceiver supports a MAC interface for 10 100Base T operation and interfaces to the MAC module of the SoC s ARM subsystem via the MII interface LED Status indicators are provided on the PCB for the following e Transmit LD36 e Receive LD35 e Link LD37 e Duplex 1039 e Collision LD34 e 100BT 1033 e 10 LD38 A SEMTECH diode array for ESD and Latch up protection is on the primary side of the isolation transformer 61 PC bus The bus consists CSDA and CSCL signal Pull up resistors are present on both these lines on the SoC Reference Board These signals are present on the RF board connector J23 to allow for storing of radio calibration data ARM GPIO2 RF_MEM_WP is used as a write protect for this device An LM77 temperature sensor is placed on the bus to allow testing of this interface 6 2 ARC Subsystem The ARC subsystem is intended to handle lower layer MAC functions ARC interfaces to either the ARM subsystem in SS mode or to an external processor e g PowerPC in BS mode ARC also interfaces to the 802 16 PHY and provides the only access to PHY from elsewhere in the system The ARC subsystem operates at a default 160MHz but can also operate at 140 180 and 200MHz Features of ARC include e ARC 4 RISC Core Harvard Architecture e DES AES CCM HCS and CRC 32 hardware blocks e Ex
58. stic cover from the back of Heatsink to expose the adhesive 2 Adhere SoC U3 to the corresponding flat square surface on the Reference Board the red circle in the adjacent photo 3 Connect J4 to a serial terminal e g 115200 Band 8 bits no start bit 1 stop bit using the serial cable included in the SoC Reference Kit Plug in the 48V power supply into a wall outlet 100 240 Vac 1 25A 50 60Hz Connect the barrel connector from the 48V power supply to the SoC Reference Board J10 The LEDs light up on Reference Board and HyperTerminal display the following Initializing ARM Subsystenm Memory Controller 0719 interrupt Controller 0C Syste Tiner sed Systen lt found gt 2 4 Setting Up SoC Reference Boards for a Traffic Test Depending on if you install a Baseband Board or an RF Board on the SoC Reference Board you can generate Baseband or FF traffic tests The procedures for each are given below 2 4 1 Baseband Traffic Procedure 1 Configure two 2 SoC Reference Boards as shown in Figure 4 2 Install a Baseband Board on each of the SoC Reference Boards Connect the Tx Rx I Q ports of the Baseband Boards with the MCX cables provided in your SoC Reference Kit refer to Figure 1 Make sure that the shunts at J11 and J9 are installed and the shunt at J8 is removed 5 From the SoC Main Menu Section 3 1 1 select 5 Traffic Application Run Traffic to start traff
59. tended Instructions for DEC AES CCM HCS and CRC 32 64KB Load Store Memory 32 CODERAM 16KB Scratch Pad RAM e 6 Input Interrupts Lines e 15 GPIOs e Two 2 Timers e AHB Bus Interface for downloading to CODERAM and data transfer to from LD ST memory e DSI Bus Interface for External PowerPC processor or any other processor for BS functions e PHY Interface extended through the peripheral I F e JI AG Debug Interface A 9 September 2005 SoC Reference Kit User Manual Table 11 1 0 Assignments Siga GPIO Description __ PPC IRQO ARC GPIOO PowerPC Interrupt when operating as BS PPCIRQI GPIO1 PowerPC Interrupt when operating as BS PPC IRQ2 ARC GPIO2 PowerPC Interrupt when operating as BS CMODE ARC GPIO3 Indicates to ARC if configured as BS or SS Table 12 Interrupt Assignments PPC PA23 ARC_EXT_IRQO PPC PA24 EXT 1 1 63 ARM Multi ICE and ARM MultiTrace Ports The ARM Multi ICE port enables you to debug software running on the ARM processor This port requires a Multi ICE Interface unit with a 20 pin JTAG connector and debug software on the host PC The ARM MultiTrace port works in conjunction with ARM Multi ICE to provide RealTrace functionality The Multi ICE connector plugs on to the MultiTrace debugger A data port width of 8 bits has been implemented on the SoC The MultiTrace port must be run at half clock speed This is configurable in the Multi Trace enabled
60. tput 158 GND 159 SPI_CS1 SPI Chip Select 160 ARM GPIO3 i ARM General Purpose Input Output 161 ARM EXT IRQO ARM External Interrupt 000 162 GND 163 ARM EXT IRQ1 164 EXT IRQO ARM External Interrupt ARC External Interrupt A 18 September 2005 SoC Reference Kit User Manual Table 15 J 3 Pinout Debugger Connector continued Pin SSName BSName 55 Description BS Description EXT 1401 ARC External Interrupt GND GPIOO ARC GPIO1 ARC GPIO2 GND ARC GPIO3 LB CLK ARM GPIO4 GND ARM GPIO5 ARM GPIO6 ARM GPIO7 GND ARM GPIO8 ARM GPIO9 ARM GPIO10 GND ARM GPIO11 ARC TDI SPARE GND ARC TMS ARC TCK CLK DDS GND ARC TDO 3V3 ARC 551 GND SPARE 3V3 3V3 3V3 3V3 3V3 ARC General Purpose Input Output ARC General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General P urpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARM General Purpose Input Output ARC Debugger Data In ARC Debugger Mode Select ARC Debugger Clock Clock for DDS synthesis ARC Debugger Data Out ARM Debugger Port Reset A 19 SoC Reference Kit User Manual Table 16 J 14 Pinout Debugger Connector Pin
61. ual Table 17 J 23 Pinout RF Board Connector Pin Name Description 0 20MHZ RFCLK 20 MHz oscillator for RF frequency synthesizers ARM GPIO11 ARM 10 ARM GPIO23 ARM GPIO22 SPIDATAIN ARM GPIO21 ARM GPIO20 ARM 19 ARM 11 AGC CTRL5 AGC 14 CTRL3 AGC CTRL2 AGC CTRLO ARM GPIO18 ARM GPIO17 ARM GPIO16 LD TR SW AGND AGND ARM GPIO15 ARM GPIO14 ARM GPIO13 ARM GPIO12 RX ARM 10 ARM GPIO9 ARM 8 ARM GPIO7 Multiplexed Automatic Gain Control FE AGCO Transmitter Power Control for SE7351L Front End Multiplexed Automatic Gain Control FE Transmitter Power Control for SE7351L Front End Multiplexed Automatic Gain Control FE AGC2 Transmitter Power Control for SE7351L Front End AGC CTRL9 ARM GPIO24 TX PWR DETECT TX EN RX EN DGND A 23 September 2005 SoC Reference Kit User Manual Table 17 J 23 Pinout RF Board Connector continued Pin Description S 0 ARM GPIO2 ARM General Purpose Input Output AGND AGND 8V5 8V5 8V5 8V5 VCTCXO CNTL LD AGND AGND ARX I IN ARX I IN AGND 6V 6V AGND ARX Q IN ARX Q IN AGND 6V 6V 6V 6V 6V AGND OUT ATX 0014 AGND Q 0014 ATX Q OUT AGND CSDA CSCL 6V 6V A 24 September 2005 SoC Reference Kit User Manual Ta
62. ubsystem is connected to a RS 232 transceiver to provide a RS 232 port The RS 232 port connector is a 9 pin Micro D Sub connector Molex P N 83611 9006 Micro D Sub to standard Dsub cables suitable for interfacing to a PC are available from Molex in 18 36 and 72 lengths 83421 9039 83421 9040 83421 9041 The RS 232 port connector pins are as follows 1 Not Used 6 Not Used 2 Transmit 7 Not Used 3 Receive 8 Not Used 4 Not Used 9 Not Used 5 Ground 5 POWERPC CONNECTOR The PowerPC connector J20 is used in BS mode to interface to a PowerPC board Power is provided to the PowerPC Board from 3 3V rail The interface is designed for a GDA MPC8560 PowerPC board The connector interfaces with the MPC8560 local bus data and address signals to the Direct Slave Interface DSI of SoC as well as IRQ signals and GPIOs Table 10 PowerPC Connector Signals 8560 Signal SoC Signal 15 31 LB A 16 0 LD 0 31 LB D 31 0P LWE 0 3 LB BE 3 0 LGPL 0 2 LBSIZE 0 2 ILCS1 CS LGPL4 LB RDY LGPL3 LB W RD IIR Q 0 2 ARC GPIO 0 2 23 ARC EXT 1800 PA24 EXT 1801 A Big Endian to Little Endian interface requires the bus order to be reversed for these signals i e LD 31 LB D 0 LD 0 gt LB DPI A 8 September 2005 SoC Reference Kit User Manual 6 ETHERNET TRANSCEIVER Ethernet signals come into the SoC Reference Board through the 8 pin RJ45 and go through an Ethe
63. witch S3 Reset S2 DIP Switch RF Coax Cable Spectrum Analyzer T Adapter ee RF Coax Cable E RX EN JXK RF m Q TX EN Ethernet Traffic Generator SmartBits To PC Serial Port 48V Power Supply RX EN a TX EN SiGe Evaluation Board SiGe Evaluation Board FLD 48 J9 0 0 416 SED O S3 Reset J20 External Processor J19 MultiTrace J1 MultilCE J14 bottom Debug Connector S1 DIP Switch S2 DIP Switch Ethernet Traffic Generator SmartBits To PC Serial Port 48V Power Supply 423 RF Connector IFLD J20 External Processor J8 J9 oo 5 J16 SED O S3 Reset J19 MultiTrace J1 MultilCE J14 bottom Debug Connector ST DIP Switch S2 DIP Switch
64. ype Direction Q OUT Analog Output High speed 10 bit DAC differential analog output pair Current output ARX Analog Input ARX Q IN 4 Analog Input ADC DAC CLK Digital Output BS SYNC OUT Digital Output BS SYNC IN Digital Input FT INT SED CLK SED DATA Data for SED SED FS Frame Synchronization for SED DTX I OUT 9 0 DTX 0 OUT 9 0 DRX I IN 9 0 DRX Q IN 9 0 Digital Input Digital inputs for interfacing to external ADC 7 2 RF Analog Interface Due to differences in common mode voltage requirements between the SoC and the SE7051L a level shifting circuit is required on the receive path On the SoC Reference Board Rev D this is implemented by differential op amps U24 and U27 The SoC has common mode voltage requirement of 0 55V Since the output of the SoC DAC is in current mode a resistor network is required on the Radio Board to provide a voltage level with the appropriate common mode voltage This circuit needs to be physically close to the SE7051L modulator chip to minimize noise coupling The SE7051L input requirements are 75 mVrms differential nominal and 13V 1 6V common mode 73 FE AGC 2 0 Multiplexing FE AGC 2 0 on SE7351L serves two functions x mode Transmit path attenuation at RF frequency Hx mode Receive path attenuation at RF frequency SoC is required to use AGC lines to control Rx attenuation As a result the AGC lines cannot be used for Tx attenuation An external multi

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