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1. elecout check if a value is available for each axis and store that value in a shared variable if so if ADC121FG ADC12IFG4 ADC12IFGA x_val ADC12MEM4 if ADC12IFG ADC12IFG5 ADC12IFG5 y val ADC12MEM5 j if ADC121FG amp ADC12IFG6 ADC12IFG6 2 val ADC12MEM6 Page 51 ADC12IFG RST reset the interrupt register and return return Page 52 2C h Created on Jun 18 2012 Author Josh Fromm This file contains the function declarations and constants needed for the the BioSleeve s I2C module to properly interact with the on board IMU y Hifndef DC H define 12 _ _ initialize the 12C controller void 12C_init void wait until 2 bus is ready for further data transfer void ACK_check void write a value to an IMU register void IMU_write int reg int data read a value from an IMU register signed int IMU_read int reg Page 53 DEFINE Value used to set 2 to master mode DEFINE DC 1 5 0 10 value used to set 2 clock source to SMCLK DEFINE DC 100KHZ baud divider needed to get I2C to run at 100KHz DEFINE IMU_ADDR 0 68 fixed address of IMU unit DEFINE DC PORTS 0X6 bits for ports used for I2C interface DEFINE I2C CTL1 TRANS MODE 0X10 bit select for transmit mode
2. Event 2 00 00 changed define 1200 0x0300 Event 3 12 00 changed RTCCTL23 Control Bits Page 196 define RTCCALF1 0x0200 RTC Calibration Frequency Bit 1 define RTCCALFO 0x0100 RTC Calibration Frequency Bit 0 define RTCCALS 0x0080 RTC Calibration Sign define Reserved 0 0040 define RTCCAL5 0x0020 RTC Calibration Bit 5 define RTCCAL4 0x0010 RTC Calibration Bit 4 define RTCCAL3 0x0008 RTC Calibration Bit 3 define RTCCAL2 0x0004 RTC Calibration Bit 2 ttdefine RTCCAL1 0x0002 RTC Calibration Bit 1 ttdefine RTCCALO 0x0001 RTC Calibration Bit O RTCCTL23 Control Bits ttdefine RTCCALS L 0x0080 RTC Calibration Sign ttdefine Reserved 0x0040 define RTCCAL5_L 0020 RTC Calibration Bit 5 define RTCCAL4_L 0x0010 RTC Calibration Bit 4 define RTCCAL3_L 0 0008 RTC Calibration Bit 3 define RTCCAL2_L 0x0004 RTC Calibration Bit 2 define RTCCAL1_L 0x0002 RTC Calibration Bit 1 define RTCCALO_L 0x0001 RTC Calibration Bit O RTCCTL23 Control Bits define RTCCALF1_H 0x0002 RTC Calibration Frequency Bit 1 define RTCCALFO_H 0x0001 RTC Calibration Frequency Bit Page 197 define Reserved 0x0040 define RTCCALF_0 0x0000 RTC Calibration Frequency No Output define RTCCALF_1 0x01
3. 1 TimerO B7 Capture Compare 1 SFR 16BIT TBOCCR2 TimerO B7 Capture Compare 2 SFR 16BIT TBOCCR3 TimerO B7 Capture Compare 3 SFR 16 TimerO B7 Capture Compare 4 SFR 16BIT TBOCCR5 TimerO B7 Capture Compare 5 SFR 16BIT TBOCCR6 TimerO B7 Capture Compare 6 SFR 16 TimerO B7 Expansion Register O SFR 16BIT TBOIV TimerO B7 Interrupt Vector Word Legacy Type Definitions for TimerB define TBCTL TBOCTL TimerO B7 Control ttdefine TBCCTLO TBOCCTLO TimerO B7 Capture Compare Control 0 ttdefine TBCCTL1 TBOCCTL1 TimerO B7 Capture Compare Control 1 ttdefine TBCCTL2 2 TimerO B7 Capture Compare Control 2 ttdefine TBCCTL3 TBOCCTL3 TimerO B7 Capture Compare Control 3 ttdefine TBCCTLA TBOCCTLA TimerO B7 Capture Compare Control 4 define TBCCTL5 5 TimerO B7 Capture Compare Control 5 define TBCCTL6 TBOCCTL6 TimerO B7 Capture Compare Control 6 define TBR TBOR TimerO B7 ttdefine TBCCRO TBOCCRO TimerO B7 Capture Compare 0 ttdefine TBCCR1 TBOCCR1 TimerO B7 Capture Compare 1 ttdefine TBCCR2 TBOCCR2 TimerO B7 Capture Compare 2 Page 223 define TBCCR3 define TBCCR4 define 5 define 6 define TBEXO define TBIV define TIMERB1_VECTOR define TIMERBO_VECTOR TBOCCR3 TimerO B7 Capture Compare 3 TBOCCRA T
4. ADC12 Data Format ADC12 Resolution Bit 0 ADC12 Resolution Bit 1 ADC12 Temperature Sensor Off ADC12 predivider 0 1 1 4 ADC12CTL2 Control Bits define ADC12REFBURST_L 0x0001 ADC12 Reference Burst define ADC12REFOUT_L 0x0002 ADC12 Reference Out define ADC12SR_L 0x0004 ADC12 Sampling Rate define ADC12DF_L 0 0008 ADC12 Data Format define ADC12RESO_L 0 0010 ADC12 Resolution Bit 0 Hdefine ADC12RES1_L 0x0020 ADC12 Resolution Bit 1 Hdefine ADC12TCOFF_L 0x0080 ADC12 Temperature Sensor Off ADC12CTL2 Control Bits Hdefine ADC12PDIV H 0x0001 ADC12 predivider 0 1 1 4 define ADC12RES 0 0 0000 ADC12 Resolution 8 Bit define ADC12RES_1 0 0010 ADC12 Resolution 10 Bit define ADC12RES_2 0x0020 ADC12 Resolution 12 Bit define ADC12RES_3 0x0030 ADC12 Resolution reserved ADC12MCTLx Control Bits define ADC12INCHO 0x0001 ADC12 Input Channel Select Bit 0 define ADC12INCH1 0x0002 ADC12 Input Channel Select Bit 1 define ADC12INCH2 0x0004 ADC12 Input Channel Select Bit 2 define ADC12INCH3 0x0008 ADC12 Input Channel Select Bit 3 define ADC12SREFO 0 0010 ADC12 Select Reference Bit O define ADC12SREF1 0x0020 ADC12 Select Reference Bit 1 Page 87 define ADC12SREF2 define ADC12EOS define ADC12INCH_0 define
5. Comp B Int Ref 1 Select 4 29 32 Comp Int Ref 1 Select 5 30 32 Comp Int Ref 1 Select 6 31 32 Comp B Int Ref 1 Select 7 32 32 Comp Reference voltage level 0 None Comp Reference voltage level 1 1 5V Comp Reference voltage level 2 2 0V Comp Reference voltage level 3 2 5V Comp B Disable Input Buffer of Port Register 0 Comp B Disable Input Buffer of Port Register 1 Comp B Disable Input Buffer of Port Register 2 Comp B Disable Input Buffer of Port Register 3 Comp B Disable Input Buffer of Port Register 4 define 5 0x0020 Comp B Disable Input Buffer of Port Register 5 define CBPD6 0x0040 Comp B Disable Input Buffer of Port Register 6 define CBPD7 0x0080 Comp B Disable Input Buffer of Port Register 7 define CBPD8 0x0100 Comp B Disable Input Buffer of Port Register 8 define CBPD9 0 0200 Comp B Disable Input Buffer of Port Register 9 define CBPD10 0x0400 Comp B Disable Input Buffer of Port Register 10 define CBPD11 0x0800 Comp B Disable Input Buffer of Port Register 11 define CBPD12 0x1000 Comp B Disable Input Buffer of Port Register 12 define CBPD13 0x2000 Comp B Disable Input Buffer of Port Register 13 define CBPD14 0x4000 Comp B Disable Input Buffer of Port Register 14 define CBPD15 0x8000
6. 0x0000 RTC Prescale Timer 1 Interrupt Interval 2 RTC Prescale Timer 1 Interrupt Interval 4 RTC Prescale Timer 1 Interrupt Interval 8 RTC Prescale Timer 1 Interrupt Interval 16 RTC Prescale Timer 1 Interrupt Interval 32 RTC Prescale Timer 1 Interrupt Interval 64 RTC Prescale Timer 1 Interrupt Interval 128 RTC Prescale Timer 1 Interrupt Interval 256 RTC Prescale Timer 1 Interrupt Interval 2 RTC Prescale Timer 1 Interrupt Interval 4 RTC Prescale Timer 1 Interrupt Interval 8 RTC Prescale Timer 1 Interrupt Interval 16 RTC Prescale Timer 1 Interrupt Interval 32 RTC Prescale Timer 1 Interrupt Interval 64 RTC Prescale Timer 1 Interrupt Interval 128 RTC Prescale Timer 1 Interrupt Interval 256 No Interrupt pending 0x0002 RTC ready RTCRDYIFG define RTCIV_RTCTEVIFG 0x0004 interval timer RTCTEVIFG define RTCIV_RTCAIFG 0x0006 user alarm RTCAIFG define RTCIV_RTOPSIFG 0x0008 RTC prescaler 0 RTOPSIFG define RTCIV RT1PSIFG 0x000A RTC prescaler 1 RT1PSIFG define RTCIV RTCOFIFG 0x000C RTC Oscillator fault Legacy Definitions define RTC_NONE 0x0000 No Interrupt pending define RTC_RTCRDYIFG 0 0002 ready RTCRDYIFG define RTCTEVIFG 0x0004 RTC interval timer RTCTEVIFG define RTCAIFG 0x0006 RT
7. Comp Pos Channel Input Enable 0x0100 Comp Neg Channel Input Select 0 0x0200 Comp B Neg Channel Input Select 1 0x0400 Comp Neg Channel Input Select 2 0x0800 Comp Neg Channel Input Select 3 0x1000 Comp B 0x2000 Comp B 0x4000 Comp B 0x8000 Comp Neg Channel Input Enable CBCTLO Control Bits define CBIPSELO L define CBIPSEL1 define CBIPSEL2 1 define CBIPSEL3 define RESERVED define RESERVED define RESERVED define CBIPEN 1 define RESERVED define RESERVED define RESERVED CBCTLO Control Bits Page 97 0x0001 Comp B Pos Channel Input Select 0 0x0002 Comp B Pos Channel Input Select 1 0x0004 Comp B Pos Channel Input Select 2 0x0008 Comp B Pos Channel Input Select 3 0x0010 Comp B 0x0020 Comp B 0x0040 Comp B 0x0080 Comp B Pos Channel Input Enable 0x1000 Comp B 0x2000 Comp B 0x4000 Comp B define RESERVED 0x0010 Comp define RESERVED 0x0020 Comp B define RESERVED 0x0040 Comp B define CBIMSELO H 0x0001 Comp B Neg Channel Input Select 0 define CBIMSEL1 H 0x0002 Comp Neg Channel Input Select 1 define CBIMSEL2 H 0x0004 Comp B Neg Channel Input Select 2 define CBIMSEL3 H 0x0008 Comp B Neg
8. define BAKDIS 0x0008 Disable backup supply switching BAKCTL Control Bits define LOCKBAK_L 0x0001 Lock backup sub system define BAKSW_L 0x0002 Manual switch to battery backup supply define BAKADC_L 0x0004 Battery backup supply to ADC define BAKDIS_L 0x0008 Disable backup supply switching BAKCTL Control Bits BAKCHCTL Control Bits Page 94 define CHEN 0x0001 Charger enable define CHCO 0x0002 Charger charge current Bit 0 define CHC1 0x0004 Charger charge current Bit 1 define CHVO 0x0010 Charger end voltage Bit 0 define CHV1 0x0020 Charger end voltage Bit 1 BAKCHCTL Control Bits define CHEN_L 0x0001 Charger enable define CHCO_L 0x0002 Charger charge current Bit 0 define CHC1_L 0x0004 Charger charge current Bit 1 define CHVO_L 0x0010 Charger end voltage Bit O define CHV1_L 0x0020 Charger end voltage Bit 1 BAKCHCTL Control Bits define CHPWD 0x6900 Charger write password JERKER EEEE EEE EEEE E EEEE EAE RR EE RR Comparator B KERE PEREA E E EEEE EE EE E EEE REE EES E ER define MSP430 HAS COMPB__ Definition to show that Module is available define MSP430_BASEADDRESS_COMPB__ 0x08C0 SFR_16BIT CBCTLO Comparator Control Register 0 Page 95 SFR 8 1 SFR_8BIT CBCTLO_H SFR_16BIT CBCTL1
9. define DMA4TSEL_21 21 0x0001u DMA channel 4 transfer select 21 USCIA1 transmit Hdefine DMA4TSEL_22 22 0x0001u DMA channel 4 transfer select 22 USCIB1 receive Hdefine DMA4TSEL_23 23 0x0001u DMA channel 4 transfer select 23 USCIB1 transmit define DMA4TSEL_24 24 0x0001u DMA channel 4 transfer select 24 ADC12IFGx define DMA4TSEL_25 25 0x0001u DMA channel 4 transfer select 25 DAC12 OIFG define DMA4TSEL_26 26 0x0001u DMA channel 4 transfer select 26 DAC12 1 define DMA4TSEL__RES27 27 0x0001u DMA channel 4 transfer select 27 Reserved define DMA4TSEL__RES28 28 0x0001u DMA channel 4 transfer select 28 Reserved define DMA4TSEL_29 29 0x0001u DMA channel 4 transfer select 29 Multiplier ready define DMA4TSEL_30 30 0x0001u DMA channel 4 transfer select 30 previous DMA channel DMA3IFG define DMA4TSEL_31 31 0x0001u DMA channel 4 transfer select 31 ext Trigger DMAEO define DMASTSEL 0 0 0x0100u DMA channel 5 transfer select 0 REQ sw si Page 131 define DMASTSEL_1 TAOCCRO IFG define DMASTSEL 2 TAOCCR2 IFG Hdefine DMASTSEL_3 TA1CCRO IFG Hdefine DMASTSEL 4 TA1CCR2 IFG define DMASTSEL 5 TA2CCRO IFG define DMASTSEL 6 TA2CCR2 IFG define DMASTSEL 7 TBOCCRO IFG define DMASTSEL 8 TBOCCR2 IFG define DMASTSEL 9 define DMASTSEL 10 define DMASTSEL
10. define OP1 321 0x0040 Bit width of operand 1 0 16Bit 1 32Bit define OP2 32 0x0080 Bit width of operand 2 0 16Bit 1 32Bit Page 155 MPY32CTLO Control Bits ttdefine RESERVED 0x0002 Reserved define MPYDLYWRTEN_H 0x0001 Delayed write enable define MPYDLY32_H 0x0002 Delayed write mode define MPYM_0 0x0000 Multiplier mode MPY define MPYM_1 0x0010 Multiplier mode MPYS define MPYM_2 0x0020 Multiplier mode MAC define MPYM_3 0x0030 Multiplier mode MACS define MPYM__MPY 0x0000 Multiplier mode MPY define MPYM__MPYS 0x0010 Multiplier mode MPYS define MPYM__MAC 0x0020 Multiplier mode MAC define MPYM__MACS 0x0030 Multiplier mode MACS EROE RARE E ER DIGITAL I O 1 2 Pull up Pull down Resistors JO A AICA KA JOE RACE ER E E ET Hdefine MSP430 HAS PORT1_R__ Definition to show that Module is available define MSP430 BASEADDRESS PORT1 0 0200 define MSP430 HAS PORT2_R__ Definition to show that Module is available define MSP430 BASEADDRESS PORT2 0 0200 define MSP430 HAS Definition to show that Module is available tidefine MSP430 BASEADDRESS PORTA 0 0200 Page 156 SFR_16BIT PAIN SFR_8BIT PAIN_L SFR_8BIT PAIN_H SFR_16BIT PAOUT SFR_8BIT PAOUT_L SFR_8BIT PAOUT_H SFR_16BIT PADIR SFR_8BIT PADI
11. ADC12 Control 0 ADC12 Control O ADC12 Control 1 ADC12 Control 1 ADC12 Control 1 ADC12 Control 2 ADC12 Control 2 ADC12 Control 2 ADC12 Interrupt Flag ADC12 Interrupt Flag ADC12 Interrupt Flag ADC12 Interrupt Enable ADC12 Interrupt Enable ADC12 Interrupt Enable ADC12 Interrupt Vector Word ADC12 Interrupt Vector Word ADC12 Interrupt Vector Word SFR_16BIT ADC12MEMO SFR_8BIT ADC12MEMO_L SFR_8BIT ADC12MEMO_H SFR_16BIT ADC12MEM1 SFR_8BIT ADC12MEM1_L SFR_8BIT ADC12MEM1_H SFR_16BIT ADC12MEM2 SFR_8BIT ADC12MEM2_L SFR_8BIT ADC12MEM2_H SFR_16BIT ADC12MEM3 SFR_8BIT ADC12MEM3_L SFR_8BIT ADC12MEM3_H SFR 16BIT ADC12MEMA SFR 8BIT ADC12MEMA 1 SFR 8BIT ADC12MEMA SFR 16BIT ADC12MEM5 SFR 8BIT ADC12MEMS 1 SFR 8BIT ADC12MEMS Hl SFR_16BIT ADC12MEM6 SFR_8BIT ADC12MEM6_L SFR_8BIT ADC12MEM6_H SFR_16BIT ADC12MEM7 SFR_8BIT ADC12MEM7_L Page 77 ADC12 Conversion Memory 0 ADC12 Conversion Memory 0 ADC12 Conversion Memory 0 ADC12 Conversion Memory 1 ADC12 Conversion Memory 1 ADC12 Conversion Memory 1 ADC12 Conversion Memory 2 ADC12 Conversion Memory 2 ADC12 Conversion Memory 2 ADC12 Conversion Memory 3 ADC12 Conversion Memory 3 ADC12 Conversion Memory 3 ADC12 Conversion Memory 4 ADC12 Conversion
12. DCO RSEL 7 UCSCTL2 Control Bits define FLLNO 0x0001 FLL Multipier Bit O define FLLN1 0x0002 FLL Multipier Bit 1 Page 233 define FLLN2 define FLLN3 define FLLN4 define FLLN5 define FLLN6 define FLLN7 define FLLN8 define FLLN9 define RESERVED define RESERVED define FLLDO define FLLD1 define FLLD2 define RESERVED 0 0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0 0200 FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit 0x0400 RESERVED 0 0800 RESERVED 0x1000 0x2000 0x4000 Loop Divider Bit Loop Divider Bit Loop Divider Bit 0 8000 RESERVED UCSCTL2 Control Bits define FLLNO_L define FLLN1_L define FLLN2_L define FLLN3_L define FLLN4_L define FLLN5_L define FLLN6_L define FLLN7_L Page 234 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit FLL Multipier Bit 277 377 4 5 6 7 8 9 0 1 1 0 157 224 4 5 6 7 define RESERVED define RESERVED
13. DMA Channel 5 Control DMA Channel 5 Control Channel 5 Source Address DMA Channel 5 Source Address Channel 5 Destination Address DMA Channel 5 Destination Address DMA Channel 5 Transfer Size DMA channel 0 transfer select bit 0 DMA channel 0 transfer select bit 1 DMA channel 0 transfer select bit 2 DMA channel 0 transfer select bit 3 DMA channel 0 transfer select bit 4 DMA channel 1 transfer select bit 0 DMA channel 1 transfer select bit 1 DMA channel 1 transfer select bit 2 define DMA1TSEL3 define DMA1TSEL4 DMACTLO Control Bits define DMAOTSELO_L define DMAOTSEL1_L define DMAOTSEL2_L define DMAOTSEL3_L define DMAOTSEL4_L DMACTLO Control Bits define DMA1TSELO_H define DMA1TSEL1_H define DMA1TSEL2_H define DMA1TSEL3_H define DMA1TSEL4_H 0x0800 0x1000 0 0001 0 0002 0 0004 0 0008 0x0010 0 0001 0 0002 0 0004 0x0008 0x0010 DMACTLO1 Control Bits define DMA2TSELO define DMA2TSEL1 define DMA2TSEL2 define DMA2TSEL3 define DMA2TSEL4 define DMA3TSELO Page 115 0x0001 0x0002 0x0004 0x0008 0 0010 0x0100 DMA channel 1 transfer select bit 3 DMA channel 1 transfer select bit 4 DMA channel 0 transfer select bit 0 DMA channel 0 transfer select bit 1 DMA channel 0 transfer
14. Hdefine DMAOTSEL 17 transmit Hdefine DMAOTSEL 18 receive Hdefine DMAOTSEL 19 transmit Hdefine DMAOTSEL 20 receive Hdefine DMAOTSEL 21 transmit Hdefine DMAOTSEL 22 receive Page 122 6 0x0001u DMA channel O transfer select 6 Timer2 7 0x0001u DMA channel 0 transfer select 7 TimerBO 8 0x0001u channel transfer select 8 TimerBO 9 0x0001u DMA channel 0 transfer select 9 Reserved 10 0x0001u 11 0x0001u 12 0x0001u 13 0x0001u 14 0x0001u 15 0x0001u 16 0x0001u 17 0x0001u 18 0x0001u 19 0x0001u 20 0x0001u 21 0x0001u 22 0x0001u DMA channel 0 transfer select 10 DMA channel 0 transfer select 11 DMA channel 0 transfer select 12 DMA channel 0 transfer select 13 DMA channel 0 transfer select 14 DMA channel 0 transfer select 15 DMA channel 0 transfer select 16 DMA channel 0 transfer select 17 DMA channel 0 transfer select 18 DMA channel 0 transfer select 19 DMA channel 0 transfer select 20 DMA channel 0 transfer select 21 DMA channel 0 transfer select 22 Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO USCIBO USCIBO USCIA1 USCIA1 USCIB1 define DMAOTSEL_23 23 0x0001u DMA channel 0 transfer select 23 USCIB1 transmit define DMAOTSEL_24 24 0x0001u DMA channel 0 transfer select 24
15. PMM Control 1 SFR_16BIT SVSMHCTL SVS and SVM high side control register SFR_8BIT SVSMHCTL_L SVS and SVM high side control register Page 173 SFR_8BIT SVSMHCTL_H SVS and SVM high side control register SFR_16BIT SVSMLCTL SVS and SVM low side control register SFR_8BIT SVSMLCTL_L SVS and SVM low side control register SFR_8BIT SVSMLCTL_H SVS and SVM low side control register SFR_16BIT SVSMIO SVSIN and SVSOUT control register SFR_8BIT SVSMIO_L SVSIN SVSOUT control register SFR_8BIT SVSMIO_H SVSIN and SVSOUT control register SFR_16BIT PMMIFG PMM Interrupt Flag SFR_8BIT PMMIFG_L PMM Interrupt Flag SFR_8BIT PMMIFG_H PMM Interrupt Flag SFR_16BIT PMMRIE and RESET Interrupt Enable SFR_8BIT PMMRIE_L PMM and RESET Interrupt Enable SFR_8BIT PMMRIE_H and RESET Interrupt Enable SFR_16BIT PMSCTLO PMM Power Mode 5 Control Register 0 SFR_8BIT PM5CTLO_L PMM Power Mode 5 Control Register 0 SFR_8BIT PM5CTLO_H PMM Power Mode 5 Control Register 0 define PMMPW 0 500 PMM Register Write Password define PMMPW_H 0xA5 PMM Register Write Password for high word access Control Bits define PMMCOREVO 0x0001 Core Voltage Bit O Hdefine PMMCOREV1 0x0002 Core Voltage Bit 1 Page 174 define PMMSWBOR 0 0004 define PMMSWPOR 0
16. define SYSNMIIES 0 0002 edge select define SYSRSTUP 0x0004 RESET Pin pull down up select define SYSRSTRE 0x0008 RESET Pin Resistor enable define 5 5 1 0x0001 select define SYSNMIIES_L 0x0002 NMI edge select define SYSRSTUP_L 0x0004 RESET Pin pull down up select define SYSRSTRE_L 0x0008 RESET Pin Resistor enable FERRATE E EEE RATE ER HR EE ERE SYS System Module EE E e define MSP430 HAS 5 5 Definition to show that Module is available define MSP430 BASEADDRESS SYS 0x0180 SFR 16BIT SYSCTL System control SFR 8BIT SYSCTL L System control SFR 8BIT SYSCTL H System control SFR 16BIT SYSBSLC Boot strap configuration area SFR 8BIT SYSBSLC L Boot strap configuration area Page 205 SFR_8BIT SYSBSLC_H SFR 16 5 5 SFR 8 5 5 1 SFR_8BIT SYSJMBC_H SFR_16BIT SYSJMBIO SFR_8BIT SYSJMBIO_L SFR_8BIT SYSJMBIO_H SFR_16BIT SYSJMBI1 SFR_8BIT SYSJMBI1_L SFR_8BIT SYSJMBI1_H SFR_16BIT SYSJMBOO SFR_8BIT SYSJMBOO_L SFR_8BIT SYSJMBOO_H SFR 16BIT SYSJMBO1 SFR 8BIT SYSJMBO1 1 SFR 8 5 5 01 SFR 16BIT SYSBERRIV SFR S8BIT SYSBERRIV 1 SFR 8BIT SYSBERRIV SFR 16BIT SYSUNIV SFR 8BIT SYSUNIV 1 SFR 8BIT SYSUNIV SFR 16BIT SYSSNIV Page 206 Boot strap configuration area JTAG mailbox contro
17. ADC12 Conversion Memory 13 ADC12 Conversion Memory 13 ADC12 Conversion Memory 14 ADC12 Conversion Memory 14 ADC12 Conversion Memory 14 ADC12 Conversion Memory 15 ADC12 Conversion Memory 15 SFR_8BIT ADC12MEM15_H ADC12 Conversion Memory 15 define ADC12MEM _ ADC12MEM ADC12 Conversion Memory Hifdef ASM HEADER Hdefine ADC12MEM ADC12MEMO ADC12 Conversion Memory for assembler Helse define ADC12MEM int amp ADC12MEMO ADC12 Conversion Memory for endif SFR_8BIT ADC12MCTLO ADC12 Memory Control 0 SFR_8BIT ADC12MCTL1 ADC12 Memory Control 1 SFR_8BIT ADC12MCTL2 ADC12 Memory Control 2 SFR_8BIT ADC12MCTL3 ADC12 Memory Control 3 SFR_8BIT ADC12MCTL4 ADC12 Memory Control 4 SFR_8BIT ADC12MCTLS ADC12 Memory Control 5 SFR 8BIT ADC12MCTL6 ADC12 Memory Control 6 SFR 8BIT ADC12MCTL7 ADC12 Memory Control 7 SFR 8BIT ADC12MCTLS ADC12 Memory Control 8 SFR 8BIT ADC12MCTLS ADC12 Memory Control 9 SFR 8BIT ADC12MCTL10 ADC12 Memory Control 10 SFR 8BIT ADC12MCTL11 ADC12 Memory Control 11 SFR 8BIT ADC12MCTL12 ADC12 Memory Control 12 SFR 8BIT ADC12MCTL13 ADC12 Memory Control 13 SFR 8BIT ADC12MCTL14 ADC12 Memory Control 14 SFR 8BIT ADC12MCTL15 ADC12 Memory Control 15 Page 79 define ADC12MCTL_ Hifdef ASM HEADER ttdefine ADC12
18. Comp B Disable Input Buffer of Port Register 15 define CBPDO_L 0x0001 B Disable Input Buffer of Port Register 0 define CBPD1_L 0x0002 B Disable Input Buffer of Port Register 1 define CBPD2_L 0x0004 Comp B Disable Input Buffer of Port Register 2 define CBPD3_L 0x0008 Comp B Disable Input Buffer of Port Register 3 define CBPD4_L 0x0010 Comp B Disable Input Buffer of Port Register A define CBPD5_L 0x0020 Disable Input Buffer of Port Register 5 define CBPD6_L 0 0040 Comp Disable Input Buffer of Port Register 6 define CBPD7_L 0x0080 Comp B Disable Input Buffer of Port Register 7 define CBPD8_H 0x0001 Comp B Disable Input Buffer of Port Register 8 define CBPD9_H 0x0002 B Disable Input Buffer of Port Register 9 define CBPD10_H 0x0004 Comp B Disable Input Buffer of Port Register 10 Page 107 define 11 H define 12 H define CBPD13 H define 14 H define 15 H 0 0008 0 0010 0 0020 0 0040 0x0080 CBINT Control Bits define CBIFG define CBIIFG define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define CBIE define CBIIE define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED Page
19. define DMA2TSEL__USCIA1RX receive define DMA2TSEL__USCIA1TX transmit define DMA2TSEL__USCIB1RX receive define DMA2TSEL__USCIB1TX transmit Page 139 9 0x0001u channel 2 transfer select 9 Reserved 10 0x0001u channel 2 transfer select 10 Reserved 11 0x0001u DMA channel 2 transfer select 11 Reserved 12 0x0001u DMA channel 2 transfer select 12 Reserved 13 0x0001u DMA channel 2 transfer select 13 Reserved 14 0x0001u DMA channel 2 transfer select 14 Reserved 15 0x0001u DMA channel 2 transfer select 15 Reserved 16 0x0001u DMA channel 2 transfer select 16 USCIAO 17 0x0001u DMA channel 2 transfer select 17 USCIAO 18 0x0001u DMA channel 2 transfer select 18 USCIBO 19 0x0001u DMA channel 2 transfer select 19 USCIBO 20 0x0001u DMA channel 2 transfer select 20 USCIA1 21 0x0001u DMA channel 2 transfer select 21 USCIA1 22 0x0001u DMA channel 2 transfer select 22 USCIB1 23 0x0001u DMA channel 2 transfer select 23 USCIB1 define DMA2TSEL__ADC12IFG 24 0x0001u DMA channel 2 transfer select 24 ADC121FGx define DMA2TSEL RES25 25 0x0001u DMA channel 2 transfer select 25 Reserved si define DMA2TSEL__RES26 26 0x0001u DMA channel 2 transfer select 26 Reserved define DMA2TSEL__RES27 27 0x0001u channel 2 transfer select 27 Reserved Hdefine DMA2TSEL__RES28
20. 0 0200 0 0400 0 0800 0 1000 0 2000 0 4000 0x8000 CBCTL2 Control Bits define CBREFOO_L define CBREFO1_L define CBREFO2_L define CBREFO3_L Page 102 0x0001 0x0002 0x0004 0x0008 Comp B Reference 0 Resistor Select Bit Comp Reference 0 Resistor Select Bit Comp Reference 0 Resistor Select Bit Comp Reference 0 Resistor Select Bit Comp Reference 0 Resistor Select Bit Comp B Reference select Comp B Reference Source Bit 0 Comp B Reference Source Bit 1 Comp Reference 1 Resistor Select Bit Comp Reference 1 Resistor Select Bit Comp Reference 1 Resistor Select Bit Comp B Reference 1 Resistor Select Bit Comp Reference 1 Resistor Select Bit 0 1 2 3 4 0 1 2 3 4 Comp B Reference voltage level Bit 0 Comp B Reference voltage level Bit 1 Comp B Reference Accuracy Comp B Reference 0 Resistor Select Bit Comp B Reference 0 Resistor Select Bit Comp B Reference 0 Resistor Select Bit Comp B Reference 0 Resistor Select Bit 0 1 2 3 define CBREFO4_L define CBRSEL_L define CBRSO_L define CBRS1_L CBCTL2 Control Bits define CBREF10_H define CBREF11_H define CBREF12_H define CBREF13_H define CBREF14_H define CBREFLO_H define CBREFL1_H define CBR
21. ADC12 Conversion Start Address 2 Page 85 define ADC12CSTARTADD_3 define ADC12CSTARTADD_4 define ADC12CSTARTADD_5 define ADC12CSTARTADD_6 define ADC12CSTARTADD_7 define ADC12CSTARTADD 8 define ADC12CSTARTADD 9 define ADC12CSTARTADD 10 define ADC12CSTARTADD 11 define ADC12CSTARTADD 12 define ADC12CSTARTADD 13 define ADC12CSTARTADD 14 define ADC12CSTARTADD 15 ADC12CTL2 Control Bits define ADC12REFBURST 0 0001 define ADC12REFOUT 0 0002 define ADC12SR 0 0004 define ADC12DF 0 0008 define ADC12RESO 0x0010 define ADC12RES1 0 0020 define ADC12TCOFF 0x0080 Hdefine ADC12PDIV 0x0100 Page 86 3 0x1000u 4 0x1000u 5 0x1000u 6 0x1000u 7 0x1000u 8 0x1000u 9 0x1000u ADC12 Conversion Start Address ADC12 Conversion Start Address ADC12 Conversion Start Address ADC12 Conversion Start Address ADC12 Conversion Start Address ADC12 Conversion Start Address ADC12 Conversion Start Address 3 7 4 5 6 7 8 9 10 0x1000u ADC12 Conversion Start Address 10 11 0x1000u ADC12 Conversion Start Address 11 12 0x1000u ADC12 Conversion Start Address 12 13 0x1000u ADC12 Conversion Start Address 13 14 0x1000u ADC12 Conversion Start Address 14 15 0x1000u ADC12 Conversion Start Address 15 ADC12 Reference Burst ADC12 Reference Out ADC12 Sampling Rate
22. DEFINE START_BIT OX2 bit corresponding to sending a start signal DEFINE STOP_BIT bit corresponding to sending to a stop signal DEFINE FREE_I2C 0X10 status bit indicating if 2 is busy DEFINE DC CTL1 MODE bit used to select receive mode DEFINE NACK_BIT OX8 bit corresponding to sending NACK signal Hendif DC H Page 54 2C c Created on Jun 18 2012 Author Josh Fromm This file contains the functions needed for the BioSleeve board to interact with the on board IMU through I2C interface Table of contents 1 126 init void When called the DC init function sets up the registers needed for the 2 interface to function properly 2 check void When called the check function checks the status registers of the I2C module and holds until the I2C is ready for another transmit or receive 3 IMU write reg data The IMU write function writes the passed data to tothe passed register of the on board IMU 4 IMU read reg The IMU read function reads the data stored in the passed register of the on board IMU and returns that value Page 55 include lt msp430f5335 h gt Hinclude I2C h The I2C init function takes no inputs and has no return value The function initializes the 26 module of the CPU by setting up the associated registers void 12C_init void UCBOCTLO M
23. IRDA Transmit Pulse Length 3 define UCIRTXPL2 0 10 IRDA Transmit Pulse Length 2 define UCIRTXPL1 0 08 IRDA Transmit Pulse Length 1 define UCIRTXPLO 0 04 IRDA Transmit Pulse Length O define UCIRTXCLK 0 02 IRDA Transmit Pulse Clock Select define UCIREN 0 01 IRDA Encoder Decoder enable UCAXIRRCTL Control Bits define UCIRRXFL5 0 80 IRDA Receive Filter Length 5 define UCIRRXFL4 0 40 IRDA Receive Filter Length 4 define UCIRRXFL3 0 20 IRDA Receive Filter Length 3 define UCIRRXFL2 0 10 IRDA Receive Filter Length 2 define UCIRRXFL1 0 08 IRDA Receive Filter Length 1 define UCIRRXFLO 0 04 IRDA Receive Filter Length 0 define UCIRRXPL 0 02 IRDA Receive Input Polarity define UCIRRXFE 0 01 IRDA Receive Filter enable UCAXABCTL Control Bits Page 261 define res 0x80 reserved define res 0x40 reserved define UCDELIM1 0 20 Break Sync Delimiter 1 define UCDELIMO 0 10 Break Sync Delimiter 0 define UCSTOE 0 08 Sync Field Timeout error define UCBTOE 0 04 define res 0 02 reserved define UCABDEN 0 01 Auto Baud Rate detect enable UCBxI2COA Control Bits define UCGCEN 0x8000 12 General Call enable define UCOA9 0x0200 12C Own Address 9 define UCOA8 0x0100 12 Own
24. JTAG Mail Box input Interrupt Enable define JMBOUTIE_L 0x0080 JTAG Mail Box output Interrupt Enable define Reserved 0 0004 SFR_16BIT SFRIFG1 Interrupt Flag 1 SFR_8BIT SFRIFG1_L Interrupt Flag 1 Page 203 SFR_8BIT SFRIFG1_H Interrupt Flag 1 SFRIFG1 Control Bits Hdefine WDTIFG 0x0001 WDT Interrupt Flag define OFIFG 0x0002 Osc Fault Flag define Reserved 0x0004 define VMAIFG 0x0008 Vacant Memory Interrupt Flag define NMIIFG 0x0010 NMI Interrupt Flag define Reserved 0 0020 define JMBINIFG 0x0040 JTAG Box input Interrupt Flag define JMBOUTIFG 0x0080 Mail Box output Interrupt Flag define WDTIFG_L 0x0001 WDT Interrupt Flag define OFIFG_L 0x0002 Osc Fault Flag define Reserved 0x0004 define VMAIFG_L 0x0008 Vacant Memory Interrupt Flag define NMIIFG_L 0x0010 NMI Interrupt Flag define Reserved 0x0020 define JMBINIFG_L 0x0040 JTAG Mail Box input Interrupt Flag define JMBOUTIFG_L 0x0080 Mail Box output Interrupt Flag define Reserved 0x0004 define Reserved 0x0020 SFR_16BIT SFRRPCR RESET Pin Control Register Page 204 SFR_8BIT SFRRPCR_L RESET Pin Control Register SFR_8BIT SFRRPCR_H RESET Pin Control Register SFRRPCR Control Bits define 5 5 0x0001 select
25. SYS Incoming JTAG Mailbox 0 Flag auto clear disalbe define JMBCLR1OFF L 0x0080 SYS Incoming JTAG Mailbox 1 Flag auto clear disalbe ttdefine RESERVED 0 0100 SYS Reserved ttdefine RESERVED 0x0200 SYS Reserved ttdefine RESERVED 0x0400 SYS Reserved ttdefine RESERVED 0x0800 SYS Reserved define RESERVED 0 1000 SYS Reserved ttdefine RESERVED 0 2000 SYS Reserved define RESERVED 0 4000 SYS Reserved ttdefine RESERVED Ox8000 SYS Reserved SYSJMBC Control Bits Page 212 ttdefine RESERVED 0x0020 SYS Reserved ttdefine RESERVED 0 0100 SYS Reserved ttdefine RESERVED 0x0200 SYS Reserved ttdefine RESERVED 0x0400 SYS Reserved define RESERVED Ox0800 SYS Reserved define RESERVED 0 1000 SYS Reserved ttdefine RESERVED 0x2000 SYS Reserved ttdefine RESERVED 0 4000 SYS Reserved define RESERVED Ox8000 SYS Reserved SYSUNIV Definitions define SYSUNIV_NONE 0x0000 No Interrupt pending define SYSUNIV_NMIIFG 0x0002 SYSUNIV NMIIFG define SYSUNIV_OFIFG 0x0004 SYSUNIV Osc Fail OFIFG define SYSUNIV_ACCVIFG 0x0006 SYSUNIV Access Violation ACCVIFG define SYSUNIV_BUSIFG 0x0008 SYSUNIV Bus Error SYSBERRIV Definitions define SYSBERRIV_NONE 0x0000 No
26. define UCBOIE UCBOICTL L USCI BO Interrupt Enable Register define UCBOIFG UCBOICTL USCI BO Interrupt Flags Register SFR_16BIT UCBOIV USCI Interrupt Vector Register UCAXCTLO UART Mode Control Bits define UCPEN 0 80 Async Mode Parity enable define UCPAR 0 40 Async Mode Parity 0 odd 1 even define UCMSB 0 20 Async Mode MSB first O LSB 1 MSB define UC7BIT 0 10 Async Mode Data Bits 0 8 bits 1 7 bits define UCSPB 0 08 Async Mode Stop Bits 1 two define UCMODE1 0 04 Async Mode USCI Mode 1 define UCMODEO 0 02 Async Mode USCI Mode 0 define UCSYNC 0 01 Sync Mode O UART Mode 1 SPI Mode Page 256 UCxxCTLO SPI Mode Control Bits define UCCKPH 0 80 define UCCKPL 0 40 define UCMST 0 08 UCBxCTLO 2 Control Bits define UCA10 0 80 define UCSLA10 0x40 define UCMM 0x20 define res define UCMODE_0 define UCMODE_1 0x02 define UCMODE 2 0x04 define UCMODE 3 0 06 Sync Mode Clock Phase Sync Mode Clock Polarity Sync Mode Master Select 10 bit Address Mode 10 bit Slave Address Mode Multi Master Environment 0 10 reserved Sync Mode USCI Mode 0 Sync Mode USCI Mode 1 Sync Mode USCI Mode 2 Sync Mode USCI Mode 3 UCAXCTL1 UART Mode Cont
27. define UCNACKIFG 0x0020 NAK Condition interrupt Flag define UCALIFG 0x0010 Arbitration Lost interrupt Flag define UCSTPIFG 0x0008 STOP Condition interrupt Flag define UCSTTIFG 0x0004 START Condition interrupt Flag define UCTXIFG 0x0002 USCI Transmit Interrupt Flag define UCRXIFG 0x0001 05 Receive Interrupt Flag USCI Definitions define 05 0x0000 No Interrupt pending define USCI_UCRXIFG 0 0002 USCI UCRXIFG define USCI_UCTXIFG 0x0004 USCI UCTXIFG define USCI_12C_UCALIFG 0x0002 USCI I2C Mode UCALIFG define USCI I2C UCNACKIFG 0 0004 USCI DC Mode UCNACKIFG define USCI I2C UCSTTIFG 0x0006 USCI I2C Mode UCSTTIFG define USCI I2C UCSTPIFG 0x0008 USCI 12C Mode UCSTPIFG define USCI I2C UCRXIFG 0 000 USCI I2C Mode UCRXIFG Page 265 define USCI_I2C_UCTXIFG USCI 12C Mode UCTXIFG EE E E E E USCI A1 OR kee define MSP430 HAS USCI 1 Definition to show that Module is available define 5 430 BASEADDRESS USCI A1 0x0600 SFR 16BIT UCA1CTLWO USCI A1 Control Word Register O SFR 8BIT UCA1CTLWO 1 USCI A1 Control Word Register O SFR 8BIT UCA1CTLWO USCI A1 Control Word Register O define UCA1CTL1 UCA1CTLWO L USCI A1 Control Register 1 define UCA1CTLO UCA1CTLWO USCI A1 Control Register 0
28. 0 define P3IV_P3IFG1 0x0004 P3IV P3IFG 1 define P3IFG2 0x0006 P3IV P3IFG 2 define P3IFG3 0x0008 P3IV P3IFG 3 define P3IV P3IFGA 0x000A P3IV P3IFG 4 define P3IFG5 0x000C P3IV P3IFG 5 define P3IV P3IFG6 P3IV P3IFG 6 define P3IFG7 0x0010 P3IV P3IFG 7 define PAIN Port 4 Input define PAOUT PBOUT H Port 4 Output define PADIR PBDIR Port 4 Direction define PAREN PBREN Port 4 Resistor Enable define PADS PBDS Port 4 Resistor Drive Strenght define PASEL PBSEL Port 4 Selection define PAIES PBIES H Port 4 Interrupt Edge Select define PAIE PBIE Port 4 Interrupt Enable Page 162 define P4IFG PBIFG Port 4 Interrupt Flag Definitions for PAIV define NONE 0x0000 No Interrupt pending define PAIFGO 0x0002 PAIV P4IFG O define PAIV PAIFG1 0x0004 PAIV PAIFG 1 define PAIFG2 0x0006 PAIV PAIFG 2 define P4IV PAIFG3 0x0008 PAIV PAIFG 3 define PAIFGA 0x000A PAIV P4IFG 4 define PAIV PAIFGS 0x000C PAIV PAIFG 5 define PAIV PAIFG6 PAIFG 6 define PAIV PAIFG7 0x0010 PAIV PAIFG 7 RE DIGITAL I O Port5 6 Pull up Pull down Resisto
29. 0x0020 Smart Write enable 0x0040 Enable bit for Flash write 0x0080 Enable bit for Flash segment write FCTL1 Control Bits ttdefine RESERVED 0x0001 Reserved ttdefine RESERVED 0x0008 Reserved ttdefine RESERVED 0x0010 Reserved FCTL3 Control Bits define BUSY 0x0001 Flash busy 1 define KEYV 0x0002 Flash Key violation flag define ACCVIFG 0x0004 Flash Access violation flag define WAIT 0x0008 Wait flag for segment write define LOCK 0x0010 Lock bit 1 Flash is locked read only define EMEX 0x0020 Flash Emergency Exit define LOCKA 0x0040 Segment Lock bit read 1 Segment is locked read only ttdefine RESERVED 0x0080 Reserved FCTL3 Control Bits define BUSY_L 0x0001 Flash busy 1 define KEYV_L 0x0002 Flash Key violation flag define ACCVIFG_L 0x0004 Flash Access violation flag define WAIT_L 0x0008 Wait flag for segment write define LOCK_L 0x0010 Lock bit 1 Flash is locked read only define EMEX_L 0x0020 Flash Emergency Exit define LOCKA_L 0x0040 Segment A Lock bit read 1 Segment is locked read only Page 149 ttdefine RESERVED 0x0080 Reserved FCTL3 Control Bits ttdefine RESERVED 0x0080 Reserved Control Bits define VPE 0x0001 Voltage Changed durin
30. OxFFE6 LDO Power Management event define LDO_PWR_ISR func ISR_VECTOR func int51 OxFFE6 LDO Power Management event CCE V2 Style Hendif Page 277 Hifdef ASM HEADER Begin defines for assembler define TIMERO A1 VECTOR int52 OxFFE8 _ 5 1 4 else define TIMERO_A1_VECTOR 52 1u OxFFE8 Timer0_A5 CC1 4 TA define TIMERO A1 ISR func ISR_VECTOR func int52 OxFFE8 TimerO A5 CC1 4 TA CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine TIMERO AO VECTOR int53 Timer0_A5 CCO else define TIMER0_A0_VECTOR 53 1u Timer0_A5 CCO define TIMERO_AO_ISR func ISR_VECTOR func int53 OxFFEA Timer0_A5 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine ADC12 VECTOR int54 OxFFEC ADC else define ADC12_VECTOR 54 1u OxFFEC ADC define ADC12_ISR func ISR_VECTOR func int54 OxFFEC ADC CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define USCI BO VECTOR 1 55 OxFFEE USCI Receive Transmit Helse define 05 VECTOR 55 1u OxFFEE USCI BO Receive Transmit Page 278 define USCI_BO_ISR func ISR_VECTOR func int55 OxFFEE USCI BO Receive Transmit CCE V2 Style Hendif Hifdef__ASM_HEA
31. Prescale Timer 1 Interrupt Interval Bit 1 define RT1IPO 0x0004 Prescale Timer 1 Interrupt Interval Bit 0 define RT1PSIE 0x0002 Prescale Timer 1 Interrupt Enable Flag define RT1PSIFG 0x0001 Prescale Timer 1 Interrupt Flag RTCPS1CTL Control Bits define Reserved 0x0080 define Reserved 0x0040 define Reserved 0x0020 define RT1IP2_L 0x0010 Prescale Timer 1 Interrupt Interval Bit 2 define RT1IP1_L 0x0008 RTC Prescale Timer 1 Interrupt Interval 1 define RT1IPO_L 0x0004 Prescale Timer 1 Interrupt Interval Bit 0 define RT1PSIE_L 0x0002 RTC Prescale Timer 1 Interrupt Enable Flag define RT1PSIFG_L 0x0001 RTC Prescale Timer 1 Interrupt Flag RTCPS1CTL Control Bits define Reserved 0x0080 Page 200 define Reserved define Reserved define RT1IP 0 define RT1IP_1 define RT1IP_2 define RT1IP_3 define RT1IP_4 define RT1IP 5 define RT1IP_6 define RT1IP_7 define RT1IP__2 define RT1IP__4 define RT1IP__8 define RT1IP__16 define RT1IP__32 define RT1IP__64 define RT1IP__128 define RT1IP__256 RTC Definitions define RTCIV_NONE define RTCIV_RTCRDYIFG Page 201 0x0040 0x0020 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0 001 0 0000 0 0004 0 0008 0x000C 0x0010 0x0014 0x0018 0 001
32. SFR_8BIT CBCTL1_L SFR_8BIT CBCTL1_H SFR_16BIT CBCTL2 SFR_8BIT CBCTL2_L SFR_8BIT CBCTL2_H SFR_16BIT CBCTL3 SFR_8BIT CBCTL3_L SFR_8BIT CBCTL3_H SFR_16BIT CBINT SFR_8BIT CBINT_L SFR_8BIT CBINT_H SFR_16BIT CBIV CBCTLO Control Bits Hdefine CBIPSELO Hdefine CBIPSEL1 Hdefine CBIPSEL2 Hdefine CBIPSEL3 define RESERVED define RESERVED define RESERVED Page 96 Comparator B Control Register 0 Comparator B Control Register 0 Comparator B Control Register 1 Comparator B Control Register 1 Comparator B Control Register 1 Comparator B Control Register 2 Comparator B Control Register 2 Comparator B Control Register 2 Comparator B Control Register 3 Comparator B Control Register 3 Comparator B Control Register 3 Comparator B Interrupt Register Comparator B Interrupt Register Comparator B Interrupt Register Comparator B Interrupt Vector Word 0x0001 0x0002 0x0004 0x0008 Comp Pos Channel Input Select 0 Comp B Pos Channel Input Select 1 Comp B Pos Channel Input Select 2 Comp B Pos Channel Input Select 3 0x0010 Comp B 0x0020 Comp B 0x0040 Comp B define CBIPEN define CBIMSELO define CBIMSEL1 define CBIMSEL2 define CBIMSEL3 define RESERVED define RESERVED define RESERVED define CBIMEN 0x0080
33. ball yv check for a collision with the player ball if X pos ball x 2 pos ball y 2 lt ball rad 2 H if a collision occurs delete all balls on the field and reset the score balls pointballs score 0 Page 63 return return The pointmove function updates the position of all green balls on the field and checks for collisions def pointmove global pointballs global x_pos global y_pos global x_max global x_min global y_max global y_min global pointball_rad global score iterate through all green balls for pointball in pointballs check if a green ball reached a boundary If so reverse the partial velocity to cause green ball to bounce off of the boundary if pointball x gt x_max or pointball x lt x_min pointball xv pointball xv if pointball y gt y max or pointball y lt y min pointball yv pointball yv update the green ball s position by its velocity Page 64 pointball x pointball x pointball xv pointball y pointball y pointball yv check if the green ball has collided with the player ball if x_pos pointball x 2 y_pos pointball y 2 lt 2 pointball_rad 2 if so delete the green ball and increment score by 1 pointballs remove pointball score 1 return The update_ball function takes an x value and y value as input and moves the player ball by the passed values in each direction If the player ball is at a bound
34. define DMASTSEL__RES13 di define DMASTSEL RES14 Si Page 145 1 0x0100u DMA channel 5 transfer select 1 TimerO A 2 0x0100u DMA channel 5 transfer select 2 TimerO A 3 0x0100u DMA channel 5 transfer select 3 Timer1 A 4 0x0100u DMA channel 5 transfer select 4 Timer1 5 0x0100u channel 5 transfer select 5 Timer2 6 0x0100u DMA channel 5 transfer select 6 Timer2 A 7 0x0100u DMA channel 5 transfer select 7 TimerBO 8 0x0100u DMA channel 5 transfer select 8 TimerBO 9 0x0100u DMA channel 5 transfer select 9 Reserved 10 0x0100u DMA channel 5 transfer select 10 Reserved 11 0x0100u DMA channel 5 transfer select 11 Reserved 12 0x0100u DMA channel 5 transfer select 12 Reserved 13 0x0100u DMA channel 5 transfer select 13 Reserved 14 0x0100u DMA channel 5 transfer select 14 Reserved define DMASTSEL RES15 15 0x0100u DMA channel 5 transfer select 15 Reserved define DMASTSEL USCIAORX 16 0x0100u DMA channel 5 transfer select 16 USCIAO receive define DMASTSEL USCIAOTX 17 0x0100u channel 5 transfer select 17 USCIAO transmit define DMASTSEL USCIBORX 18 0 0100 DMA channel 5 transfer select 18 USCIBO receive define DMASTSEL USCIBOTX 19 0x0100u channel 5 transfer select 19 USCIBO transmit define DMASTSEL USCIA1RX 20 0x0100u DMA channel 5 transfer sele
35. define RESERVED Page 211 0x0100 SYS Reserved 0 0200 SYS Reserved 0 0400 SYS Reserved 0x0800 SYS Reserved 0x1000 SYS Reserved 0 2000 SYS Reserved 0 0040 SYS BSLMemeory disabled 0 0080 SYS BSL Memory protection enabled 0x0001 SYS Incoming JTAG Mailbox O Flag 0 0002 SYS Incoming JTAG Mailbox 1 Flag 0x0004 SYS Outgoing JTAG Mailbox O Flag 0x0008 SYS Outgoing JTAG Mailbox 1 Flag 0x0010 SYS JMB 16 32 Bit Mode 0 0020 SYS Reserved 0x0040 SYS Incoming JTAG Mailbox 0 Flag auto clear 0x0080 SYS Incoming JTAG Mailbox 1 Flag auto clear 0x0100 SYS Reserved 0x0200 SYS Reserved 0x0400 SYS Reserved 0x0800 SYS Reserved 0x1000 SYS Reserved ttdefine RESERVED 0 2000 SYS Reserved ttdefine RESERVED 0x4000 SYS Reserved ttdefine RESERVED 0x8000 SYS Reserved SYSJMBC Control Bits define JMBINOFG_L 0x0001 SYS Incoming JTAG Mailbox O Flag define JMBIN1FG_L 0x0002 SYS Incoming JTAG Mailbox 1 Flag define JMBOUTOFG_L 0x0004 SYS Outgoing JTAG Mailbox O Flag define IMBOUT1FG_L 0x0008 SYS Outgoing JTAG Mailbox 1 Flag define JMBMODE 0 0010 SYS JMB 16 32 Bit Mode ttdefine RESERVED 0x0020 SYS Reserved define JMBCLROOFF_L 0x0040
36. 0x0008 MODOSC Clock Request Enable define RESERVED 0x0010 RESERVED define RESERVED 0x0020 RESERVED define RESERVED 0x0040 RESERVED define RESERVED 0 0080 RESERVED define RESERVED 0 0100 RESERVED define RESERVED 0 0200 RESERVED define RESERVED 0 0400 RESERVED Page 252 define RESERVED 0x0800 RESERVED define RESERVED 0 1000 RESERVED define RESERVED 0 2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0 8000 RESERVED UCSCTL8 Control Bits etine X define RESERVED 0x0010 RESERVED etine X define RESERVED 0x0020 RESERVED define RESERVED 0x0040 RESERVED define RESERVED 0x0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0x2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED 0x8000 RESERVED DOO ICE TE ER sa USCI AO SETA E AL M LE define MSP430 HAS USCI Definition to show that Module is available Page 253 define 5 430 BASEADDRESS USCI AO 0x05C0 SFR_16BIT UCAOCTLWO USCI 0 Control Word Register 0 SFR_8BIT UCAOC
37. 181 define SVMLVLRIFG 0x0004 5 low side Voltage Level Reached interrupt flag define SVSMHDLYIFG 0x0010 5 5 and SVM high side Delay expired interrupt flag vi define SVMHIFG 0x0020 5 high side interrupt flag define SVMHVLRIFG 0x0040 SVM high side Voltage Level Reached interrupt flag define PMMBORIFG 0x0100 Software BOR interrupt flag define PMMRSTIFG 0x0200 RESET pin interrupt flag define PMMPORIFG 0x0400 Software POR interrupt flag define SVSHIFG 0x1000 SVS low side interrupt flag define SVSLIFG 0x2000 SVS high side interrupt flag define PMMLPMSIFG 0x8000 LPMS indication Flag PMMIFG Control Bits define SVSMLDLYIFG_L 0x0001 5 5 and SVM low side Delay expired interrupt flag define SVMLIFG_L 0x0002 SVM low side interrupt flag define SVMLVLRIFG_L 0x0004 SVM low side Voltage Level Reached interrupt flag define SVSMHDLYIFG_L 0x0010 5 5 and SVM high side Delay expired interrupt flag define SVMHIFG_L 0x0020 5 high side interrupt flag define SVMHVLRIFG 0x0040 SVM high side Voltage Level Reached interrupt flag PMMIFG Control Bits Page 182 define PMMBORIFG H 0x0001 Software BOR interrupt flag define PMMRSTIFG_H 0x0002 PMM RESET pin interrupt flag ttdefine PMMPORIFG H 0x0004 PMM Software POR interrupt flag d
38. 28 0x0001u DMA channel 2 transfer select 28 Reserved define DMA2TSEL__MPY 29 0x0001u DMA channel 2 transfer select 29 Multiplier ready define DMA2TSEL__DMA1IFG 30 0x0001u DMA channel 2 transfer select 30 previous channel define DMA2TSEL DMAEO 31 0x0001u DMA channel 2 transfer select 31 ext Trigger DMAEO define DMA3TSEL DMA REQ 0 0x0100u DMA channel 3 transfer select 0 DMA_REQ sw define DMA3TSEL TAOCCRO 1 0x0100u DMA channel 3 transfer select 1 TimerO A TAOCCRO IFG define DMA3TSEL TAOCCR2 2 0x0100u channel 3 transfer select 2 TimerO TAOCCR2 IFG define DMA3TSEL TA1CCRO 3 0x0100u DMA channel 3 transfer select 3 Timer1 A TA1CCRO IFG define DMA3TSEL TA1CCR2 4 0x0100u DMA channel 3 transfer select 4 Timer1_A TA1CCR2 IFG define DMA3TSEL TA2CCRO 5 0x0100u DMA channel 3 transfer select 5 Timer2_A TA2CCRO IFG Page 140 define DMA3TSEL__TA2CCR2 TA2CCR2 IFG define DMA3TSEL__TBOCCRO TBOCCRO IFG define DMA3TSEL__TBOCCR2 TBOCCR2 IFG define DMA3TSEL RES9 define DMA3TSEL__RES10 define DMA3TSEL__RES11 define DMA3TSEL__RES12 define DMA3TSEL__RES13 di define DMA3TSEL__RES14 define DMA3TSEL__RES15 define DMA3TSEL__USCIAORX receive define DMA3TSEL__USCIAOTX transmit define DMA3TSEL__US
39. BSL Protection Size 0 define SYSBSLSIZE1 L 0x0002 SYS BSL Protection Size 1 define SYSBSLR 1 0x0004 SYS RAM assigned to BSL define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED SYSBSLC Control Bits define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED Page 210 Ox0008 SYS Reserved 0 0010 SYS Reserved 0x0020 SYS Reserved 0x0040 SYS Reserved 0 0080 SYS Reserved 0 0100 SYS Reserved 0x0200 SYS Reserved 0x0400 SYS Reserved Ox0800 SYS Reserved 0 1000 SYS Reserved 0 2000 SYS Reserved Ox0008 SYS Reserved 0 0010 SYS Reserved 0x0020 SYS Reserved 0x0040 SYS Reserved Ox0080 SYS Reserved define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define SYSBSLOFF_H define SYSBSLPE_H SYSJMBC Control Bits define JMBINOFG define JMBIN1FG define JMBOUTOFG define JMBOUT1FG define JMBMODE define RESERVED define JMBCLROOFF disalbe define JMBCLR1OFF disalbe define RESERVED define RESERVED define RESERVED define RESERVED
40. SFR_8BIT PUCTL_H PU Control register SFR_16BIT LDOPWRCTL LDO Power control register SFR_8BIT LDOPWRCTL_L LDO Power control register SFR_8BIT LDOPWRCTL_H LDO Power control register Hdefine LDOKEY 0x9628 LDO Control Register key Hdefine LDOKEYID LDOKEYPID Legacy Definiton Page 185 PUCTL Control Bits define PUOUTO 0x0001 PU PU Output Signal Bit 0 define PUOUT1 0x0002 PU PU Output Signal Bit 1 define PUINO 0x0004 PU PUO DP Input Data define PUIN1 0x0008 PU PU1 DM Input Data define PUOPE 0x0020 PU Port Output Enable define PUIPE 0x0100 PU PHY Single Ended Input enable PUCTL Control Bits define PUOUTO_L 0x0001 PU PU Output Signal Bit O define PUOUT1_L 0x0002 PU PU Output Signal Bit 1 define PUINO L 0x0004 PU PUO DP Input Data define PUIN1 L 0x0008 PU PU1 DM Input Data ttdefine PUOPE L 0x0020 PU Port Output Enable PUCTL Control Bits ttdefine PUIPE H 0x0001 PU PHY Single Ended Input enable define PUDIR 0x0020 Legacy Definiton ttdefine PSEIEN 0x0100 Legacy Definiton LDOPWRCTL Control Bits ttdefine LDOOVLIFG 0x0001 PU LDOO Overload Interrupt Flag Page 186 define LDOONIFG 0 0002 define LDOOFFIFG 0 0004 define LDOBGVBV 0 0008 define OVLAOFF 0 0020 define LDOOVLIE
41. define DMASTSEL1_H 0x0002 DMA channel 5 transfer select bit 1 define DMASTSEL2_H 0x0004 DMA channel 5 transfer select bit 2 define DMASTSEL3_H 0x0008 DMA channel 5 transfer select bit 3 define DMASTSEL4_H 0x0010 DMA channel 5 transfer select bit 4 DMACTL4 Control Bits define ENNMI 0x0001 Enable NMI interruption of DMA define ROUNDROBIN 0x0002 DMA channel priorities Page 117 define DMARMWDIS 0x0004 Inhibited DMA transfers during read modify write CPU operations DMACTLA Control Bits define ENNMI_L 0x0001 Enable NMI interruption define ROUNDROBIN_L 0x0002 Round Robin DMA channel priorities define DMARMWDIS_L 0x0004 Inhibited DMA transfers during read modify write CPU operations DMACTL4 Control Bits DMAXCTL Control Bits define DMAREQ 0x0001 Initiate DMA transfer with DMATSEL define DMAABORT 0x0002 DMA transfer aborted by NMI define DMAIE 0x0004 DMA interrupt enable define DMAIFG 0x0008 DMA interrupt flag define DMAEN 0x0010 DMA enable define DMALEVEL 0x0020 DMA level sensitive trigger select define DMASRCBYTE 0x0040 DMA source byte define DMADSTBYTE 0x0080 DMA destination byte define DMASRCINCRO 0x0100 source increment bit 0 define DMASRCINCR1 0 0200 source increment bit 1
42. define RESERVED 0x0400 0x0800 0 8000 UCSCTL2 Control Bits define FLLN8_H define FLLN9_H define RESERVED define RESERVED define FLLDO_H define FLLD1_H define FLLD2_H define RESERVED define FLLD_0 define FLLD_1 define FLLD_2 define FLLD_3 define FLLD_4 define FLLD_5 define FLLD_6 define FLLD_7 define FLLD_ 1 define FLLD 2 Page 235 0x0001 0x0002 0x0400 0 0800 0 0010 0 0020 0 0040 0 8000 0 0000 0 1000 0 2000 0 3000 0 4000 0 5000 0 6000 0x7000 0x0000 0 1000 RESERVED RESERVED RESERVED FLL Multipier Bit 8 FLL Multipier Bit 9 RESERVED RESERVED Loop Divider Bit 0 Loop Divider Bit 1 Loop Divider Bit 1 RESERVED Multiply Selected Loop Freq 1 Multiply Selected Loop Freq 2 Multiply Selected Loop Freq 4 Multiply Selected Loop Freq 8 Multiply Selected Loop Freq 16 Multiply Selected Loop Freq 32 Multiply Selected Loop Freq 32 Multiply Selected Loop Freq 32 Multiply Selected Loop Freq By 1 Multiply Selected Loop Freq By 2 define FLLD_ 4 define FLLD 8 Hdefine FLLD 16 Hdefine FLLD 32 0x2000 0x3000 0x4000 0x5000 UCSCTL3 Control Bits define FLLREFDIVO define FLLREFDIV1 define FLLREFDIV2 define RESERVED define SE
43. 0 DMA channel 2 transfer select bit 1 DMA channel 2 transfer select bit 2 DMA channel 2 transfer select bit 3 DMA channel 2 transfer select bit 4 DMA channel 3 transfer select bit 0 channel 3 transfer select bit 1 DMA channel 3 transfer select bit 2 DMA channel 3 transfer select bit 3 DMA channel 3 transfer select bit 4 DMA channel 4 transfer select bit 0 DMA channel 4 transfer select bit 1 DMA channel 4 transfer select bit 2 DMA channel 4 transfer select bit 3 define DMA4TSEL4 0x0010 DMA channel 4 transfer select bit 4 define DMASTSELO 0 0100 DMA channel 5 transfer select bit 0 define DMASTSEL1 0 0200 DMA channel 5 transfer select bit 1 define DMASTSEL2 0x0400 DMA channel 5 transfer select bit 2 define DMASTSEL3 0x0800 DMA channel 5 transfer select bit 3 define DMASTSEL4 0x1000 DMA channel 5 transfer select bit 4 DMACTLO Control Bits define DMA4TSELO_L 0x0001 DMA channel 4 transfer select bit O define DMA4TSEL1_L 0x0002 DMA channel 4 transfer select bit 1 Hdefine DMA4TSEL2_L 0x0004 DMA channel 4 transfer select bit 2 Hdefine DMA4TSEL3_L 0x0008 DMA channel 4 transfer select bit 3 define DMA4TSEL4_L 0x0010 DMA channel 4 transfer select bit 4 DMACTLO Control Bits define DMASTSELO_H 0x0001 DMA channel 5 transfer select bit 0
44. 0 1 2 3 4 5 6 7 8 9 define ADC12SHT1_10 10 0x1000u ADC12 Sample Hold 1 Select Bit 10 define ADC12SHT1_11 11 0x1000u ADC12 Sample Hold 1 Select Bit 11 define ADC12SHT1_12 12 0x1000u ADC12 Sample Hold 1 Select Bit 12 define ADC12SHT1_13 13 0x1000u ADC12 Sample Hold 1 Select Bit 13 define ADC12SHT1_14 14 0x1000u ADC12 Sample Hold 1 Select Bit 14 define ADC12SHT1_15 15 0x1000u ADC12 Sample Hold 1 Select Bit 15 ADC12CTL1 Control Bits define ADC12BUSY 0x0001 ADC12 Busy define ADC12CONSEQO 0x0002 ADC12 Conversion Sequence Select Bit define ADC12CONSEQ1 0x0004 12 Conversion Sequence Select Bit 1 define ADC12SSELO 0x0008 ADC12 Clock Source Select Bit 0 define ADC12SSEL1 0x0010 ADC12 Clock Source Select Bit 1 define ADC12DIVO 0x0020 ADC12 Clock Divider Select Bit 0 define ADC12DIV1 0x0040 ADC12 Clock Divider Select Bit 1 define ADC12DIV2 0x0080 12 Clock Divider Select Bit 2 define ADC121SSH 0x0100 ADC12 Invert Sample Hold Signal define ADC12SHP 0 0200 ADC12 Sample Hold Pulse Mode define ADC12SHSO 0x0400 ADC12 Sample Hold Source Bit O define ADC12SHS1 0x0800 ADC12 Sample Hold Source Bit 1 define ADC12CSTARTADDO 0x1000 ADC12 Conversion Start Address Bit O define ADC12CSTARTADD1 0x2000 ADC12 Conversio
45. 0008 define PMMREGOFF 0 0010 define PMMHPMRE 0x0080 Control Bits define PMMCOREVO L 0 0001 define 1 0 0002 define PMMSWBOR_L 0x0004 define PMMSWPOR_L 0 0008 define PMMREGOFF_L 0 0010 define PMMHPMRE_L 0x0080 PMMCTLO Control Bits define PMMCOREV_0 0 0000 define PMMCOREV 1 0x0001 define PMMCOREV_2 0 0002 define PMMCOREV 3 0 0003 PMMCTL1 Control Bits define PMMREFMD 0x0001 define PMMCMDO 0x0010 Page 175 PMM Software BOR PMM Software POR PMM Turn Regulator off PMM Global High Power Module Request Enable PMM Core Voltage Bit 0 PMM Core Voltage Bit 1 PMM Software BOR PMM Software POR PMM Turn Regulator off PMM Global High Power Module Request Enable PMM Core Voltage 0 1 35 PMM Core Voltage 1 1 55V PMM Core Voltage 2 1 75V PMM Core Voltage 3 1 85V PMM Reference Mode PMM Voltage Regulator Current Mode Bit O define PMMCMD1 0 0020 Voltage Regulator Current Mode Bit 1 PMMCTL1 Control Bits define PMMREFMD_L 0x0001 PMM Reference Mode define PMMCMDO_L 0x0010 Voltage Regulator Current Mode Bit 0 define L 0x0020 Voltage Regulator Current Mode Bit 1 PMMCTL1 Control Bits SVSMHCTL Control Bits define SVSMHRR
46. 0x0020 SYS Dedicated JTAG pins enabled 0x0040 SYS Reserved 0x0080 SYS Reserved 0x0100 SYS Reserved 0x0200 SYS Reserved 0x0400 SYS Reserved 0x0800 SYS Reserved 0x1000 SYS Reserved 0x2000 SYS Reserved 0x4000 SYS Reserved 0x8000 SYS Reserved SYSCTL Control Bits define SYSRIVECT_L 0x0001 SYS RAM based interrupt vectors ttdefine RESERVED 0x0002 SYS Reserved define SYSPMMPE_L 0x0004 SYS PMM access protect ttdefine RESERVED 0 0008 SYS Reserved define SYSBSLIND_L 0x0010 SYS TCK RST indication detected define SYSJTAGPIN_L 0x0020 SYS Dedicated JTAG pins enabled define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED SYSCTL Control Bits define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED Page 208 0x0040 SYS Reserved 0 0080 SYS Reserved 0 0100 SYS Reserved 0x0200 SYS Reserved 0x0400 SYS Reserved Ox0800 SYS Reserved 0 1000 SYS Reserved 0x2000 SYS Reserved 0 4000 SYS Reserved Ox8000 SYS Reserved 0x0002 SYS Reserved Ox0008
47. 0x0400 define RESERVED 0x0800 define RESERVED 1000 define RESERVED 0 2000 define RESERVED 0 4000 define RESERVED 0 8000 UCSCTL1 Control Bits define RESERVED 0 0002 Page 232 RESERVED RESERVED RESERVED Disable Modulation RESERVED RESERVED RESERVED DCO Freq Range Select Bit 0 DCO Freq Range Select Bit 1 DCO Freq Range Select Bit 2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED define RESERVED 0 0004 RESERVED define RESERVED 0 0008 RESERVED define RESERVED 0x0080 RESERVED define RESERVED 0 0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0 0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0 1000 RESERVED define RESERVED 0 2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0 8000 RESERVED define DCORSEL_0 0x0000 DCO RSEL 0 define DCORSEL_1 0x0010 DCO RSEL 1 define DCORSEL_2 0x0020 DCO RSEL 2 define DCORSEL_3 0x0030 DCO RSEL 3 define DCORSEL_4 0x0040 DCO RSEL 4 define DCORSEL 5 0x0050 DCO RSEL 5 ttdefine DCORSEL 6 0x0060 DCO RSEL 6 ttdefine DCORSEL 7 0x0070
48. 108 0x0001 0x0002 Comp B Disable Input Buffer of Port Register Comp B Disable Input Buffer of Port Register Comp B Disable Input Buffer of Port Register Comp B Disable Input Buffer of Port Register Comp B Disable Input Buffer of Port Register Comp B Interrupt Flag Comp B Interrupt Flag Inverted Polarity 0x0100 0x0200 0x0004 Comp 0x0008 Comp 0x0010 Comp 0x0020 Comp 0x0040 Comp 0x0080 Comp 0x0400 Comp 0x0800 Comp 0x1000 Comp 0x2000 Comp 0x4000 Comp 0x8000 Comp Comp B Interrupt Enable Comp B Interrupt Enable Inverted Polarity 11 12 13 14 15 Control Bits define CBIFG_L 0x0001 Comp Interrupt Flag define CBIIFG_L 0x0002 Comp Interrupt Flag Inverted Polarity define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED CBINT Control Bits define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define CBIE_H Page 109 0x0004 Comp 0x0008 Comp 0x0010 Comp 0x0020 Comp 0x00
49. 11 Hdefine DMASTSEL 12 define DMASTSEL 13 define DMASTSEL 14 define DMASTSEL 15 define DMASTSEL 16 receive define DMASTSEL 17 transmit Page 132 1 0x0100u 2 0x0100u 3 0x0100u 4 0x0100u 5 0x0100u 6 0x0100u 7 0x0100u 8 0x0100u 9 0x0100u 10 0x0100u 11 0x0100u 12 0x0100u 13 0x0100u 14 0x0100u 15 0x0100u 16 0x0100u 17 0x0100u DMA channel 5 transfer select 1 TimerO A DMA channel 5 transfer select 2 TimerO A DMA channel 5 transfer select 3 Timer1_A DMA channel 5 transfer select 4 Timer1_A DMA channel 5 transfer select 5 Timer2_A DMA channel 5 transfer select 6 Timer2_A DMA channel 5 transfer select 7 TimerBO DMA channel 5 transfer select 8 TimerBO DMA channel 5 transfer select 9 Reserved DMA channel 5 transfer select 10 DMA channel 5 transfer select 11 DMA channel 5 transfer select 12 DMA channel 5 transfer select 13 DMA channel 5 transfer select 14 DMA channel 5 transfer select 15 DMA channel 5 transfer select 16 DMA channel 5 transfer select 17 Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO define DMASTSEL_18 18 0x0100u DMA channel 5 transfer select 18 USCIBO receive define DMASTSEL_19 19 0x0100u DMA channel 5 transfer select 19 USCIBO transmit define DMASTSEL_20 20 0x0100u DMA chan
50. 2 define UCSA1 0x0002 1 2 Slave Address 1 define UCSA0 0x0001 12 Slave Address 0 Page 263 UCBxI2CSA Control Bits define UCSA7 L 0x0080 I2C Slave Address 7 define UCSA6_L 0x0040 12C Slave Address 6 define UCSA5 1 0x0020 12C Slave Address 5 define UCSA4_L 0x0010 12C Slave Address 4 define UCSA3_L 0x0008 12 Slave Address 3 define UCSA2_L 0x0004 12 Slave Address 2 define UCSA1_L 0x0002 12 Slave Address 1 define UCSAO_L 0x0001 12 Slave Address 0 UCBxI2CSA Control Bits define UCSA9_H 0x0002 12C Slave Address 9 define UCSA8_H 0x0001 12C Slave Address 8 UCAXIE Control Bits define UCTXIE 0x0002 05 Transmit Interrupt Enable define UCRXIE 0x0001 USCI Receive Interrupt Enable UCBXIE Control Bits define UCNACKIE 0x0020 Condition interrupt enable define UCALIE 0x0010 Arbitration Lost interrupt enable define UCSTPIE 0x0008 5 Condition interrupt enable define UCSTTIE 0x0004 START Condition interrupt enable Page 264 define UCTXIE 0x0002 05 Transmit Interrupt Enable define UCRXIE 0x0001 USCI Receive Interrupt Enable UCAxIFG Control Bits define UCTXIFG 0x0002 05 Transmit Interrupt Flag define UCRXIFG 0x0001 05 Receive Interrupt Flag UCBxIFG Control Bits
51. 6 is the system s charging LED It quite simply turns on when the battery is charging If the system is plugged in and the LED is not on then the battery is fully charged Component 7 is the system s power switch 8 Component 8 is the system s calibration and reset button When playing Ball Blasters Infinity the user may find that the accelerometer glove is not properly centered If this Page 4 is the case the user can press component 8 to trigger a recalibration sequence During this period which is displayed on the LED display the user should hold the accelerometer glove in the position that the user desires to be the zero position when the glove is in the zero position the blue ball in Ball Blasters Infinity will not move If the system experiences an unknown error the user is recommended to press the recalibration button as it also resets the CPU 9 Component 9 is the system s rechargeable battery Should the battery ever wear out it can be easily replaced by the user by simply plugging a new battery to the onboard jack 10 Component 10 is the system s accelerometer glove The glove is used to control the blue ball in Ball Blasters Infinity It is recommended that the user put the glove on his her index finger with the blue wires facing upwards when the user s finger is parallel to the ground When this is done tilting the user s finger upwards will cause the blue ball to move up tilting downwards will cause the bl
52. ADC12IFGx define DMAOTSEL 25 25 0x0001u DMA channel 0 transfer select 25 DAC12 OIFG si define DMAOTSEL_26 26 0x0001u channel 0 transfer select 26 DAC12 1IFG define DMAOTSEL RES27 27 0x0001u channel 0 transfer select 27 Reserved define DMAOTSEL__RES28 28 0x0001u DMA channel O transfer select 28 Reserved define DMAOTSEL_29 29 0x0001u DMA channel 0 transfer select 29 Multiplier ready define DMAOTSEL_30 30 0x0001u DMA channel 0 transfer select 30 previous DMA channel DMASIFG define DMAOTSEL_31 31 0x0001u DMA channel 0 transfer select 31 ext Trigger DMAEO define DMA1TSEL 0 0 0x0100u DMA channel 1 transfer select 0 REQ sw A define DMA1TSEL_1 1 0x0100u channel 1 transfer select 1 TimerO A TAOCCRO IFG define DMA1TSEL 2 2 0x0100u TA0CCR2 IFG define DMA1TSEL_3 3 0x0100u TA1CCRO IFG define DMA1TSEL 4 4 0x0100u TA1CCR2 IFG Page 123 DMA channel 1 transfer select 2 DMA channel 1 transfer select 3 DMA channel 1 transfer select 4 TimerO A Timer1 Timer1 A define DMA1TSEL 5 TA2CCRO IFG define DMA1TSEL 6 TA2CCR2 IFG define DMA1TSEL 7 TBOCCRO IFG define DMA1TSEL 8 TBOCCR2 IFG define DMA1TSEL 9 define DMA1TSEL 10 define DMA1TSEL 11 define DMA1TSEL 12 define DMA1TSEL 13 define DMA1TSEL 14 define DMA1TSEL 15 define
53. ADC12INCH_1 define ADC12INCH_2 define ADC12INCH_3 define ADC12INCH_4 define ADC12INCH_5 define ADC12INCH_6 define ADC12INCH_7 define ADC12INCH_8 define ADC12INCH_9 define ADC12INCH_10 define ADC12INCH_11 define ADC12INCH_12 define ADC12INCH_13 define ADC12INCH_14 define ADC12INCH_15 define ADC12SREF_0 define ADC12SREF_1 define ADC12SREF_2 define ADC12SREF_3 Page 88 0x0040 0x0080 0x0000 0 0001 0 0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D OxOOOE 0x000F 0 0x10u 1 0x10u 2 0x10u 3 0x10u ADC12 Select Reference Bit 2 ADC12 End of Sequence ADC12 Input Channel 0 ADC12 Input Channel 1 ADC12 Input Channel 2 ADC12 Input Channel 3 ADC12 Input Channel 4 ADC12 Input Channel 5 ADC12 Input Channel 6 ADC12 Input Channel 7 ADC12 Input Channel 8 ADC12 Input Channel 9 ADC12 Input Channel 10 ADC12 Input Channel 11 ADC12 Input Channel 12 ADC12 Input Channel 13 ADC12 Input Channel 14 ADC12 Input Channel 15 ADC12 Select Reference 0 ADC12 Select Reference 1 ADC12 Select Reference 2 ADC12 Select Reference 3 define ADC12SREF_4 4 0x10u ADC12 Select Reference 4 define ADC12SREF_5 5 0x10u ADC12 Select Reference 5 define ADC12SREF_6 6 0x10u ADC12 Sele
54. Address 8 define UCOA7 0x0080 12 Own Address 7 define UCOA6 0x0040 12 Own Address 6 define UCOAS 0x0020 12C Own Address 5 define UCOA4 0x0010 12C Own Address 4 define UCOA3 0x0008 1 2 Own Address 3 define UCOA2 0x0004 12 Own Address 2 define UCOA1 0x0002 12C Own Address 1 define UCOAO 0x0001 12 Own Address 0 UCBxI2COA Control Bits Hdefine UCOA7 L 0x0080 12C Own Address 7 Page 262 define UCOA6 L 0x0040 1 2 Own Address 6 define UCOA5_L 0x0020 1 2 Own Address 5 Hdefine UCOA4_L 0x0010 12 Own Address 4 Hdefine UCOA3 L 0x0008 12C Own Address 3 Hdefine UCOA2 L 0x0004 12C Own Address 2 Hdefine UCOA1 L 0x0002 1 2 Own Address 1 Hdefine UCOAO L 0x0001 12 Own Address 0 UCBxI2COA Control Bits Hdefine UCGCEN H 0x0080 1 2 General Call enable define UCOA9 H 0x0002 12 Own Address 9 Hdefine UCOA8 H 0x0001 12 Own Address 8 UCBxI2CSA Control Bits define UCSA9 0 0200 12C Slave Address 9 define UCSA8 0x0100 12C Slave Address 8 UCSA7 0 0080 12 Slave Address 7 UCSA6 0x0040 12 Slave Address 6 define 0 5 5 0x0020 12C Slave Address 5 UCSA4 0x0010 12C Slave Address 4 define UCSA3 0x0008 12 Slave Address 3 define UCSA2 0x0004 12 Slave Address
55. CBREFO 11 define CBREFO 12 define CBREFO 13 define CBREFO_14 define CBREFO 15 define CBREFO 16 define CBREFO 17 define CBREFO 18 define CBREFO 19 define CBREFO 20 define CBREFO 21 define CBREFO 22 define CBREFO 23 define CBREFO_24 define CBREFO_25 define CBREFO_26 define CBREFO_27 define CBREFO_28 define CBREFO_29 define CBREFO_30 define CBREFO_31 Page 104 0x0009 0x000A 0x000B 0x000C 0x000D OxOOOE 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0 001 0x001F Comp Int Ref 0 Select 1 10 32 Comp Int Comp Int Comp Comp Comp Comp Comp Comp B Int B Int B Int B Int B Int B Int Comp B Int Comp B Int Comp B Int Comp B Int Comp B Int Comp B Int Comp B Int Comp B Int Comp Comp Comp Comp B Int B Int B Int B Int Comp B Int Comp B Int Ref 0 Select 2 11 32 Ref 0 Select 3 12 32 Ref 0 Select 4 13 32 Ref 0 Select 5 14 32 Ref 0 Select 6 15 32 Ref 0 Select 7 16 32 Ref 0 Select 0 17 32 Ref 0 Select 1 18 32 Ref 0 Select 2 19 32 Ref 0 Select 3 20 32 Ref 0 Select 4 21 32 Ref 0 Select 5 22 32 Ref 0 Select 6 23 32 Ref 0 S
56. Channel Input Select 3 define RESERVED 0x1000 Comp B define RESERVED 0x2000 Comp B define RESERVED 0x4000 Comp B define CBIMEN H 0x0080 Comp B Neg Channel Input Enable define CBIPSEL 0 0x0000 V terminal Input Select Channel 0 define CBIPSEL_1 0x0001 Comp B V terminal Input Select Channel 1 define CBIPSEL_2 0x0002 V terminal Input Select Channel 2 define CBIPSEL_3 0x0003 Comp B V terminal Input Select Channel 3 define CBIPSEL_4 0x0004 Comp V terminal Input Select Channel 4 define CBIPSEL_5 0x0005 Comp V terminal Input Select Channel 5 define CBIPSEL_6 0x0006 Comp V terminal Input Select Channel 6 define CBIPSEL 7 0x0007 Comp B V terminal Input Select Channel 7 define CBIPSEL 8 0x0008 Comp B V terminal Input Select Channel 8 define CBIPSEL 9 0x0009 Comp B V terminal Input Select Channel 9 define CBIPSEL 10 0x000A Comp V terminal Input Select Channel 10 define CBIPSEL 11 0x000B Comp B V terminal Input Select Channel 11 Page 98 define CBIPSEL_12 define CBIPSEL_13 define CBIPSEL_14 define CBIPSEL_15 define CBIMSEL_0 define CBIMSEL_1 define CBIMSEL_2 define CBIMSEL_3 define CBIMSEL_4 define CBIMSEL_5 define CBIMSEL_6 define CBIMSEL_7 define CBIMSEL_8 define CBIMSEL_9 define CBIMSEL_10
57. DMA1TSEL 16 receive define DMA1TSEL 17 transmit define DMA1TSEL_18 define DMA1TSEL_19 transmit define DMA1TSEL_20 receive define DMA1TSEL 21 transmit Page 124 5 0x0100u DMA channel 1 transfer select 5 6 0x0100u DMA channel 1 transfer select 6 7 0x0100u DMA channel 1 transfer select 7 8 0x0100u DMA channel 1 transfer select 8 9 0x0100u DMA channel 1 transfer select 9 10 0x0100u 11 0x0100u 12 0x0100u 13 0x0100u 14 0x0100u 15 0x0100u 16 0x0100u 17 0x0100u 18 0x0100u 19 0x0100u 20 0x0100u 21 0x0100u DMA channel 1 transfer select 10 DMA channel 1 transfer select 11 DMA channel 1 transfer select 12 channel 1 transfer select 13 DMA channel 1 transfer select 14 DMA channel 1 transfer select 15 DMA channel 1 transfer select 16 DMA channel 1 transfer select 17 DMA channel 1 transfer select 18 DMA channel 1 transfer select 19 DMA channel 1 transfer select 20 DMA channel 1 transfer select 21 Timer2_A Timer2_A TimerBO TimerBO Reserved Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO USCIBO USCIBO USCIA1 USCIA1 define DMA1TSEL_22 22 0x0100u DMA channel 1 transfer select 22 USCIB1 receive define DMA1TSEL_23 23 0x0100u DMA channel 1 transfer select 2
58. EEEE E E E E ET define MSP430 HAS RTC B Definition to show that Module is available define _MSP430_BASEADDRESS_RTC_B__ SFR_16BIT RTCCTLO1 Real Timer Control 0 1 SFR_8BIT RTCCTLO1_L Real Timer Control 0 1 SFR_8BIT RTCCTLO1_H Real Timer Control 0 1 SFR_16BIT RTCCTL23 Real Timer Control 2 3 SFR_8BIT RTCCTL23_L Real Timer Control 2 3 SFR_8BIT RTCCTL23_H Real Timer Control 2 3 SFR_16BIT RTCPSOCTL Real Timer Prescale Timer Control SFR_8BIT RTCPSOCTL_L Real Timer Prescale Timer 0 Control SFR_8BIT RTCPSOCTL_H Real Timer Prescale Timer O Control SFR_16BIT RTCPS1CTL Real Timer Prescale Timer 1 Control SFR_8BIT RTCPS1CTL_L Real Timer Prescale Timer 1 Control SFR 8BIT RTCPS1CTL Real Timer Prescale Timer 1 Control SFR 16BIT RTCPS Real Timer Prescale Timer Control SFR 8BIT RTCPS 1 Real Timer Prescale Timer Control SFR 8BIT RTCPS H Real Timer Prescale Timer Control SFR 16BIT RTCIV Real Time Clock Interrupt Vector SFR 16BIT RTCTIMO Real Time Clock Time 0 Page 192 SFR_8BIT RTCTIMO_L SFR_8BIT RTCTIMO_H SFR_16BIT RTCTIM1 SFR_8BIT RTCTIM1_L SFR_8BIT RTCTIM1_H SFR_16BIT RTCDATE SFR_8BIT RTCDATE_L SFR_8BIT RTCDATE_H SFR_16BIT RTCYEAR SFR_8BIT RTCYEAR_L SFR_8BIT RTCYEAR_H SFR_16BIT RTCAMINHR Real Time Clock Time 0 Real Time Clock Time 0 Rea
59. Edge Select Port 2 Interrupt Enable PAIFG_H 0x0000 0x0002 0 0004 0 0006 0x0008 0x000A 0x000C OxOOOE 0x0010 Port 2 Interrupt Flag No Interrupt pending P2IV P2IFG O P2IV P2IFG 1 P2IV P2IFG 2 P2IV P2IFG 3 P2IV P2IFG 4 P2IV P2IFG 5 P2IV P2IFG 6 P2IV P2IFG 7 rb DIGITAL I O Port3 4 Pull up Pull down Resistors i define MSP430 HAS Definition to show that Module is available define__MSP430_BASEADDRESS_PORT3_R__ 0x0220 define _MSP430_HAS_PORT4_R__ Definition to show that Module is available define _MSP430_BASEADDRESS_PORT4_R__ 0x0220 Hdefine MSP430_HAS Definition to show that Module is available tidefine _MSP430_BASEADDRESS_PORTB_R__ 0x0220 SFR_16BIT PBIN SFR_8BIT PBIN_L SFR_8BIT PBIN_H SFR_16BIT PBOUT SFR_8BIT PBOUT_L SFR_8BIT PBOUT_H SFR_16BIT PBDIR SFR_8BIT PBDIR_L SFR_8BIT PBDIR_H SFR_16BIT PBREN SFR_8BIT PBREN_L SFR_8BIT PBREN_H Page 160 Port Input Port B Input Port B Input Port B Output Port B Output Port B Output Port B Direction Port B Direction Port B Direction Port Resistor Enable Port Resistor Enable Port B Resistor Enable SFR_16BIT PBDS SFR_8BIT PBDS_L SFR_
60. Interrupt pending define SYSBERRIV_USB 0x0002 SYSBERRIV USB Waitstate Error SYSSNIV Definitions define SYSSNIV_NONE 0x0000 No Interrupt pending define SYSSNIV_SVMLIFG 0x0002 SYSSNIV SVMLIFG Page 213 define SYSSNIV_SVMHIFG 0x0004 SYSSNIV SVMHIFG define SYSSNIV_DLYLIFG 0x0006 SYSSNIV DLYLIFG define SYSSNIV_DLYHIFG 0x0008 5 55 DLYHIFG define SYSSNIV_VMAIFG 0x000A 5 55 VMAIFG define SYSSNIV_JMBINIFG 0x000C SYSSNIV JMBINIFG define SYSSNIV JMBOUTIFG 0 000 SYSSNIV JMBOUTIFG define SYSSNIV_VLRLIFG 0x0010 SYSSNIV VLRLIFG define SYSSNIV_VLRHIFG 0x0012 SYSSNIV VLRHIFG SYSRSTIV Definitions define SYSRSTIV_NONE 0x0000 No Interrupt pending define SYSRSTIV_BOR 0 0002 SYSRSTIV BOR define SYSRSTIV_RSTNMI 0x0004 SYSRSTIV RST NMI define SYSRSTIV_DOBOR 0x0006 SYSRSTIV Do BOR define SYSRSTIV_LPM5WU 0x0008 SYSRSTIV Port LPM5 Wake Up define SYSRSTIV SECYV 0x000A SYSRSTIV Security violation define SYSRSTIV SVSL SYSRSTIV SVSL define SYSRSTIV_SVSH SYSRSTIV SVSH define SYSRSTIV SVML OVP 0x0010 SYSRSTIV SVML OVP define SYSRSTIV SVMH OVP 0x0012 SYSRSTIV SVMH_OVP define SYSRSTIV_DOPOR 0x0014 SYSRSTIV Do POR define SYSRSTIV WDTTO 0x0016 SYSRSTIV WDT
61. Memory 4 ADC12 Conversion Memory 4 ADC12 Conversion Memory 5 ADC12 Conversion Memory 5 ADC12 Conversion Memory 5 ADC12 Conversion Memory 6 ADC12 Conversion Memory 6 ADC12 Conversion Memory 6 ADC12 Conversion Memory 7 ADC12 Conversion Memory 7 SFR_8BIT ADC12MEM7_H SFR_16BIT ADC12MEM8 SFR_8BIT ADC12MEMB8_L SFR_8BIT ADC12MEM8_H SFR_16BIT ADC12MEM9 SFR_8BIT ADC12MEM9_L SFR_8BIT ADC12MEM9_H SFR_16BIT ADC12MEM10 SFR_8BIT ADC12MEM10_L SFR_8BIT ADC12MEM10_H SFR_16BIT ADC12MEM11 SFR_8BIT ADC12MEM11_L SFR_8BIT ADC12MEM11_H SFR_16BIT ADC12MEM12 SFR_8BIT ADC12MEM12_L SFR_8BIT ADC12MEM12_H SFR 16BIT ADC12MEM13 SFR 8BIT ADC12MEM13 1 SFR 8BIT ADC12MEM13 H SFR 16BIT ADC12MEM14 SFR 8BIT ADC12MEM14 1 SFR 8BIT ADC12MEM14 SFR 16BIT ADC12MEM 15 SFR 8BIT ADC12MEM15 1 Page 78 ADC12 Conversion Memory 7 ADC12 Conversion Memory 8 ADC12 Conversion Memory 8 ADC12 Conversion Memory 8 ADC12 Conversion Memory 9 ADC12 Conversion Memory 9 ADC12 Conversion Memory 9 ADC12 Conversion Memory 10 ADC12 Conversion Memory 10 ADC12 Conversion Memory 10 ADC12 Conversion Memory 11 ADC12 Conversion Memory 11 ADC12 Conversion Memory 11 ADC12 Conversion Memory 12 ADC12 Conversion Memory 12 ADC12 Conversion Memory 12 ADC12 Conversion Memory 13
62. PORT_7_ADC set adc pins of port 7 to ADC mode Page 43 return The calibrate function uses a series of readings from the accelerometer to compute an average position This average position is then stored for future comparisons to determime offsets from the base position During the calibration process this function outputs an incrementing loading bar to the system s LED display calibrate has no inputs and does not return anything void calibrate void int x_count 0 counter used to determine how many valid x readings occured int y_count 0 counter used to determine how many valid y readings occured int z_count 0 counter used to determine how many valid z readings occured int j variable used for iteration int led_var 0 variable used for changing output of display iteratively uncalibrated UNCALIBRATED set uncalibrated variable to indicate system is not calibrated ADC12CTLO ADC12SC trigger an ADC read _BIS_SR GIE Page 44 run series conversions add all read values to the base variables after each iteration do a display wait and update the display to indicate remaining time for j 0 j lt NUM_P9_LEDS j Page 45 led_var 0x1 lt lt add another bar to the display P9OUT led var output the value ADC12CTLO ADC12SC set up the next analog to digital conversion _B
63. SVS and SVM low side Reset Release Voltage Level 3 SVS and SVM low side Reset Release Voltage Level 4 SVS and SVM low side Reset Release Voltage Level 5 SVS and SVM low side Reset Release Voltage Level 6 SVS and SVM low side Reset Release Voltage Level 7 SVS low side Reset Release Voltage Level 0 SVS low side Reset Release Voltage Level 1 SVS low side Reset Release Voltage Level 2 define SVSLRVL_3 0x0300 SVS low side Reset Release Voltage Level 3 SVSMIO Control Bits define SVMLOE 0x0008 5 low side output enable define SVMLVLROE 0x0010 5 low side voltage level reached output enable define SVMOUTPOL 0x0020 SVMOUT pin polarity ttdefine SVMHOE 0x0800 SVM high side output enable ttdefine SVMHVLROE 0x1000 SVM high side voltage level reached output enable SVSMIO Control Bits define SVMLOE_L 0x0008 SVM low side output enable define SVMLVLROE_L 0x0010 SVM low side voltage level reached output enable define SVMOUTPOL L 0x0020 SVMOUT pin polarity SVSMIO Control Bits define SVMHOE H 0x0008 SVM high side output enable define SVMHVLROE H 0x0010 SVM high side voltage level reached output enable PMMIFG Control Bits define SVSMLDLYIFG 0x0001 SVS and SVM low side Delay expired interrupt flag define SVMLIFG 0x0002 SVM low side interrupt flag Page
64. SYS Reserved 0x0040 SYS Reserved Ox0080 SYS Reserved 0 0100 SYS Reserved define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED 0x0200 SYS Reserved 0x0400 SYS Reserved 0x0800 SYS Reserved 0x1000 SYS Reserved 0x2000 SYS Reserved 0x4000 SYS Reserved 0 8000 SYS Reserved SYSBSLC Control Bits define SYSBSLSIZEO 0x0001 SYS BSL Protection Size 0 define SYSBSLSIZE1 0x0002 SYS BSL Protection Size 1 define SYSBSLR 0x0004 SYS RAM assigned to BSL define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define SYSBSLOFF Page 209 0 0008 SYS Reserved 0x0010 SYS Reserved 0 0020 SYS Reserved 0 0040 SYS Reserved Ox0080 SYS Reserved 0x0100 SYS Reserved 0 0200 SYS Reserved 0 0400 SYS Reserved 0x0800 SYS Reserved 0 1000 SYS Reserved 0x2000 SYS Reserved 0x4000 SYS BSL Memeory disabled define SYSBSLPE 0x8000 SYS BSL Memory protection enabled SYSBSLC Control Bits define SYSBSLSIZEO_L 0 0001 SYS
65. Sequence Select 0 define ADC12CONSEQ 1 1 2u ADC12 Conversion Sequence Select 1 define ADC12CONSEQ_2 2 2u ADC12 Conversion Sequence Select 2 Page 84 define ADC12CONSEQ_3 3 2u ADC12 Conversion Sequence Select 3 define ADC12SSEL_0 0 8u ADC12 Clock Source Select 0 define ADC12SSEL_1 1 8u ADC12 Clock Source Select 1 define ADC12SSEL_2 2 8u ADC12 Clock Source Select 2 define ADC12SSEL_3 3 8u ADC12 Clock Source Select 3 define ADC12DIV_0 0 0x20u ADC12 Clock Divider Select O define ADC12DIV_1 1 0x20u ADC12 Clock Divider Select 1 define ADC12DIV_2 2 0x20u ADC12 Clock Divider Select 2 define ADC12DIV_3 3 0x20u ADC12 Clock Divider Select 3 define ADC12DIV_4 4 0x20u 12 Clock Divider Select 4 define ADC12DIV_5 5 0x20u ADC12 Clock Divider Select 5 define ADC12DIV_6 6 0x20u ADC12 Clock Divider Select 6 define ADC12DIV_7 7 0x20u ADC12 Clock Divider Select 7 define ADC12SHS_0 0 0x400u ADC12 Sample Hold Source 0 define ADC12SHS_1 1 0x400u ADC12 Sample Hold Source 1 define ADC12SHS_2 2 0x400u ADC12 Sample Hold Source 2 define ADC12SHS_3 3 0x400u ADC12 Sample Hold Source 3 define ADC12CSTARTADD_O 0 0 1000 ADC12 Conversion Start Address O define ADC12CSTARTADD 1 1 0x1000u ADC12 Conversion Start Address 1 define ADC12CSTARTADD 2 2 0x1000u
66. data output data to write to IMU ACK_check UCBOTXBUF STOP_BIT send stop bit return write is finished The IMU_read function takes an integer register value as input and returns Page 57 the value stored in the IMU register corresponding to the input number read cycle is carried out as specified in the IMU data sheet The required steps are set transmit mode gt send a start bit gt wait for acknowledge gt send register value gt wait for acknowledge gt set to receive mode gt send another start bit gt wait for acknowledge gt read value gt send NACK signal gt send stop bit The value red is then returned signed int IMU_read int reg signed int read_data variable containing data read from IMU UCBOCTL1 12C_CTL1_TRANS_MODE set to transmit mode UCBOCTL1 START_BIT send start bit ACK_check UCBOTXBUF reg output register value to read from UCBOCTL1 amp I2C CTL1 REC MODE set I2C to receive mode UCBOCTL1 START_BIT send another start bit ACK_check read_data UCBORXBUF load value read from IMU UCBOCTL1 NACK_BIT send NACK signal to IMU UCBOCTL1 STOP send stop signal to IMU return read_data return the read value Page 58 BallBlasters py Created on Jun 11 2012 Author Josh Fromm This file contains the code and functions u
67. define CBIMSEL_11 define CBIMSEL_12 define CBIMSEL_13 define CBIMSEL_14 define CBIMSEL_15 CBCTL1 Control Bits define Page 99 0 0000 OxOOOE OxOOOF 0x0000 0x0100 0x0200 0x0300 0x0400 0x0500 0x0600 0x0700 0x0800 0x0900 00 0 0000 0 0 00 0 0 00 0 0001 Comp V terminal Input Select Channel 12 Comp V terminal Input Select Channel 13 Comp V terminal Input Select Channel 14 Comp B V terminal Input Select Channel 15 Comp V Terminal Input Select Channel 0 Comp B V Terminal Input Select Channel 1 Comp B V Terminal Input Select Channel 2 Comp V Terminal Input Select Channel 3 Comp V Terminal Input Select Channel 4 Comp B V Terminal Input Select Channel 5 Comp B V Terminal Input Select Channel 6 Comp B V Terminal Input Select Channel 7 Comp B V terminal Input Select Channel 8 Comp B V terminal Input Select Channel 9 Comp B V terminal Input Select Channel 10 Comp B V terminal Input Select Channel 11 Comp B V terminal Input Select Channel 12 Comp B V terminal Input Select Channel 13 Comp B V terminal Input Select Channel 14 Comp B V terminal Input Select Channel 15 Comp B Output define CBOUTPO
68. define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0x2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED 0x8000 RESERVED UCSCTL3 Control Bits define RESERVED 0x0008 RESERVED define RESERVED 0x0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED Page 237 define RESERVED 0 1000 RESERVED define RESERVED 0x2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0x8000 RESERVED define FLLREFDIV_0 0x0000 Reference Divider f LFCLK 1 define FLLREFDIV_1 0x0001 Reference Divider f LFCLK 2 define FLLREFDIV_2 0x0002 Reference Divider f LFCLK A define FLLREFDIV_3 0x0003 Reference Divider f LFCLK 8 define FLLREFDIV 4 0x0004 Reference Divider f LFCLK 12 Hdefine FLLREFDIV 5 0x0005 Reference Divider f LFCLK 16 define FLLREFDIV 6 0x0006 Reference Divider f LFCLK 16 Hdefine FLLREFDIV 7 0x0007 Reference Divider f LFCLK 16 Hdefine FLLREFDIV 1 0x0000 Reference Divider f LFCLK 1 Hdefine FLLREFDIV 2 0x0001 Reference Di
69. h Created on Jun 7 2012 Author Josh Fromm This file contains the constants needed to run the functions that facilitate ADC readings for the BioSleeve system Hifndef ADC_H_ define ADC_H_ DEFINE THRESHOLD 4 constant used to determine minimum distance from base before accelerometer tilt triggers output DEFINE MIN_THRESHOLD 20 accelerometer reads below this value are probably errors DEFINE MAX_THRESHOLD 240 accelerometer reads above this value are probably errors DEFINE CALIBRATED 0 indicates accelerometer is uncalibrated DEFINE UNCALIBRATED 1 indicates accelerometer is calibrated DEFINE ADC SEQ 0X2 sets adc reads to perform a sequence of reads DEFINE EIGHT_BIT_STAND configures adc to be in standard 8 bit mode DEFINE ADC_BITS 0X7F bits corresponding to used ADC memory registers Page 38 HDEFINE ELEC adc port used for electrode 0 DEFINE ELEC_1 0X1 adc port used for electrode 1 DEFINE ELEC_2 0 2 adc port used for electrode 2 DEFINE ELEC_3 0X3 adc port used for electrode 3 DEFINE X AXIS 0X5 adc port used for accelerometer x axis DEFINE Y_AXIS 0X7 adc port used for accelerometer y axis DEFINE Z_AXIS ONSE adc port used for accelerometer z axis end of seq bit DEFINE PORT_6_ADC OXFF pins used on port 6 DEFINE PORT_7_ADC OXFO pins used on port 7 DEFINE NUM P9 LEDS 0X
70. select bit 2 DMA channel 0 transfer select bit 3 DMA channel 0 transfer select bit 4 DMA channel 1 transfer select bit 0 DMA channel 1 transfer select bit 1 DMA channel 1 transfer select bit 2 DMA channel 1 transfer select bit 3 DMA channel 1 transfer select bit 4 DMA channel 2 transfer select bit 0 DMA channel 2 transfer select bit 1 DMA channel 2 transfer select bit 2 DMA channel 2 transfer select bit 3 DMA channel 2 transfer select bit 4 DMA channel transfer select bit 0 define DMA3TSEL1 define DMA3TSEL2 define DMA3TSEL3 define DMA3TSEL4 0x0200 0x0400 0x0800 0x1000 DMACTLO1 Control Bits define DMA2TSELO_L define DMA2TSEL1_L define DMA2TSEL2_L define DMA2TSEL3_L define DMA2TSEL4 L 0x0001 0x0002 0x0004 0x0008 0x0010 DMACTLO1 Control Bits define DMA3TSELO_H define DMA3TSEL1_H define DMA3TSEL2_H define DMA3TSEL3_H define DMA3TSEL4_H DMACTLO Control Bits define DMA4TSELO define DMA4TSEL1 define DMA4TSEL2 define DMA4TSEL3 Page 116 0x0001 0x0002 0x0004 0x0008 0x0010 0x0001 0x0002 0x0004 0x0008 channel transfer select bit 1 channel transfer select bit 2 channel transfer select bit 3 channel transfer select bit 4 DMA channel 2 transfer select bit
71. to send and receive data to from the client running Ball Blasters Infinity Ball Blasters Infinity Client This block runs the game and receives data from the BioSleeve board Page 8 Hardware Manual This section addresses each block of hardware in detail The system s memory map follows Due to the design of the MSP processor all blocks of memory are used in the BioSleeve system except vacant of course MSP430F5335 Memory Mapping EES3 Josh Fromm Peripheral Mapping Reserved for system extension 000008 256 B OOOFFh OOFEFh BioSleeve MSP430 Memory Mapping 4B DES Start address of descriptor 4 KB DOFF7h Peripherals DOFFFh 001000h EF Bootstrap loader memory 2 KB lee Se 01C00h BEEGOR DEE ZER Main interrupt vector 80B qun 220 KB FFFFFh System Memory Mapping The following image shows the layout of the board with exact model numbers for each component Page 9 Reset Switch JTAG Header 9999999 tr 0 0 MAX809 m Power Jacks E O o Charging LED e m lt 555 E Battery Jack SUR MAX1927R e E 9 9 toni ni BioSleeve Detailed Board Layout WiFly RN 131C LED Display E ITG 3200 IMU d 331 Amplifiers Wifi Adhoc Jumper Wifi Stat
72. 0 define UCBRS_1 define UCBRS_2 define UCBRS_3 define UCBRS_4 define UCBRS_5 define UCBRS_6 define UCBRS_7 0x00 0x02 0x04 0x06 0x08 UCAXSTAT Control Bits define UCLISTEN define UCFE define UCOE define UCPE define UCBRK define UCRXERR define UCADDR define UCBUSY define UCIDLE 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x02 UCBXSTAT Control Bits define UCSCLLOW Page 260 0x40 USCI First Stage Modulation F USCI Second Stage Modulation 0 USCI Second Stage Modulation 1 USCI Second Stage Modulation 2 USCI Second Stage Modulation 3 USCI Second Stage Modulation 4 USCI Second Stage Modulation 5 USCI Second Stage Modulation 6 USCI Second Stage Modulation 7 USCI Listen mode USCI Frame Error Flag USCI Overrun Error Flag USCI Parity Error Flag USCI Break received USCI RX Error Flag USCI Address received Flag USCI Busy Flag USCI Idle line detected Flag SCL low define UCGC 0 20 General Call address received Flag define UCBBUSY 0 10 Bus Busy Flag UCAXIRTCTL Control Bits define UCIRTXPL5 0 80 IRDA Transmit Pulse Length 5 define UCIRTXPL4 0 40 IRDA Transmit Pulse Length 4 define UCIRTXPL3 0 20
73. 0 0100 define LDOONIE 0 0200 define LDOOFFIE 0x0400 define LDOOEN 0x0800 LDOPWRCTL Control Bits define LDOOVLIFG_L 0x0001 define LDOONIFG_L 0 0002 define LDOOFFIFG_L 0 0004 define LDOBGVBV_L 0 0008 define OVLAOFF_L 0 0020 LDOPWRCTL Control Bits define LDOOVLIE_H 0x0001 define LDOONIE_H 0x0002 define LDOOFFIE_H 0x0004 define LDOOEN_H 0x0008 define VUOVLIFG 0x0001 Page 187 PU LDOI Coming ON Interrupt Flag PU LDOI Going OFF Interrupt Flag PU LDO Bandgap and LDOI valid PU LDO overload auto off enable PU Overload indication Interrupt Enable PU LDOI Coming ON Interrupt Enable PU LDOI Going OFF Interrupt Enable PU LDO Enable 3 3V PU LDOO Overload Interrupt Flag PU LDOI Coming ON Interrupt Flag PU LDOI Going OFF Interrupt Flag PU LDO Bandgap and LDOI valid PU LDO overload auto off enable PU Overload indication Interrupt Enable PU LDOI Coming ON Interrupt Enable PU LDOI Going OFF Interrupt Enable PU LDO Enable 3 3V PU Legacy Definiton LDOO Overload Interrupt Flag define VBONIFG 0x0002 PU Legacy Definiton LDOI Coming ON Interrupt Flag define VBOFFIFG 0x0004 PU Legacy Definiton LDOI Going OFF Interrupt Flag define VUOVLIE 0x0100 PU Legacy Definiton Overload i
74. 00 RTC Calibration Frequency 512 Hz define RTCCALF 2 0x0200 RTC Calibration Frequency 256 Hz define RTCCALF_3 0x0300 RTC Calibration Frequency 1 Hz RTCPSOCTL Control Bits define Reserved 0x0080 define Reserved 0x0040 define Reserved 0x0020 define RTOIP2 0x0010 RTC Prescale Timer 0 Interrupt Interval Bit 2 define RTOIP1 0x0008 Timer 0 Interrupt Interval Bit 1 define RTOIPO 0x0004 Prescale Timer 0 Interrupt Interval Bit 0 define RTOPSIE 0x0002 Prescale Timer 0 Interrupt Enable Flag define RTOPSIFG 0x0001 Prescale Timer 0 Interrupt Flag RTCPSOCTL Control Bits define Reserved 0x0080 define Reserved 0x0040 define Reserved 0x0020 define RTOIP2_L 0x0010 RTC Prescale Timer 0 Interrupt Interval 2 define RTOIP1_L 0x0008 RTC Prescale Timer Interrupt Interval Bit 1 define RTOIPO_L 0x0004 RTC Prescale Timer Interrupt Interval Bit O Page 198 define RTOPSIE_L define RTOPSIFG_L 0x0002 0x0001 RTCPSOCTL Control Bits define Reserved define Reserved define Reserved define RTOIP_O define RTOIP_1 define RTOIP_2 define RTOIP_3 define RTOIP_4 define RTOIP_5 define RTOIP_6 define RTOIP_7 define 2 define RTOIP 4 define 8 define 16 define 32 def
75. 001u 7 0x0001u 0 0x0001u 1 0x0001u 2 0x0001u 3 0x0001u 4 0x0001u 5 0x0001u 6 0x0001u 7 0x0001u 0x0000 0x0002 0x0004 TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion TimerO B7 Input divider expansion No Interrupt pending TBCCR1 CCIFG TBCCR2 CCIFG Reserved Reserved Reserved 1 2 3 8 5 6 7 8 AJ ER 3 8 5 6 7 8 define TBOIV 6 0x000C W Reserved define TBOIV_TBOIFG TBIFG OR ek EE ERE EE EEE UNIFIED CLOCK SYSTEM SERE OE E EEE E RO TE RE e TE EC E E OR e EEE EEE define _ MSP430_HAS_UCS _ Definition to show that Module is available define __MSP430_BASEADDRESS_UCS__ 0x0160 SFR_16BIT UCSCTLO UCS Control Register 0 SFR_8BIT UCSCTLO_L UCS Control Register 0 SFR_8BIT UCSCTLO_H UCS Co
76. 1 Hdefine DMA4TSEL_12 Hdefine DMA4TSEL_13 Hdefine DMA4TSEL_14 Hdefine DMA4TSEL_15 define DMA4TSEL_16 receive define DMA4TSEL_17 transmit define DMA4TSEL_18 receive Page 130 2 0x0001u 3 0x0001u 4 0x0001u 5 0x0001u 6 0x0001u 7 0x0001u 8 0x0001u 9 0x0001u 10 0x0001u 11 0x0001u 12 0x0001u 13 0x0001u 14 0x0001u 15 0x0001u 16 0x0001u 17 0x0001u 18 0x0001u DMA channel 4 transfer select 2 TimerO A DMA channel 4 transfer select 3 Timer1_A DMA channel 4 transfer select 4 DMA channel 4 transfer select 5 Timer2_A DMA channel 4 transfer select 6 Timer2_A DMA channel 4 transfer select 7 0 DMA channel 4 transfer select 8 0 DMA channel 4 transfer select 9 Reserved DMA channel 4 transfer select 10 DMA channel 4 transfer select 11 DMA channel 4 transfer select 12 DMA channel 4 transfer select 13 DMA channel 4 transfer select 14 DMA channel 4 transfer select 15 DMA channel 4 transfer select 16 DMA channel 4 transfer select 17 DMA channel 4 transfer select 18 Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO USCIBO define DMA4TSEL_19 19 0x0001u DMA channel 4 transfer select 19 USCIBO transmit Hdefine DMA4TSEL_20 20 0x0001u DMA channel 4 transfer select 20 USCIA1 receive
77. 1 receive define DMA2TSEL_23 23 0x0001u DMA channel 2 transfer select 23 USCIB1 transmit define DMA2TSEL_24 24 0x0001u DMA channel 2 transfer select 24 ADC12IFGx define DMA2TSEL_25 25 0x0001u channel 2 transfer select 25 DAC12 OIFG define DMA2TSEL_26 26 0x0001u channel 2 transfer select 26 DAC12 1IFG define DMA2TSEL__RES27 27 0x0001u DMA channel 2 transfer select 27 Reserved define DMA52SEL__RES28 28 0x0001u DMA channel 2 transfer select 28 Reserved define DMA2TSEL_29 29 0x0001u DMA channel 2 transfer select 29 Multiplier ready define DMA2TSEL_30 30 0x0001u DMA channel 2 transfer select 30 previous channel define DMA2TSEL_31 31 0x0001u DMA channel 2 transfer select 31 ext Trigger DMAEO define DMA3TSEL 0 0 0x0100u DMA channel 3 transfer select 0 REQ sw define DMA3TSEL_1 1 0x0100u DMA channel 3 transfer select 1 TimerO TAOCCRO IFG define DMA3TSEL_2 2 0x0100u DMA channel 3 transfer select 2 TimerO A TAOCCR2 IFG Page 127 Hdefine DMA3TSEL_3 TA1CCRO IFG define DMA3TSEL_4 TA1CCR2 IFG Hdefine DMA3TSEL_5 TA2CCRO IFG Hdefine DMA3TSEL_6 TA2CCR2 IFG Hdefine DMA3TSEL_7 TBOCCRO IFG Hdefine DMA3TSEL_8 TBOCCR2 IFG define DMA3TSEL 9 define DMA3TSEL 10 ttdefine DMA3TSEL 11 ttdefine DMA3TSEL 12 define DMA3TSEL 1
78. 12 Enable Conversion define ADC12TOVIE 1 0x0004 ADC12 Timer Overflow interrupt enable define ADC12OVIE L 0x0008 ADC12 Overflow interrupt enable define ADC120N 1 0x0010 ADC12 On enable define ADC12REFON 1 0x0020 ADC12 Reference on define ADC12REF2 DN 1 0x0040 ADC12 Ref 0 1 5V 1 2 5V define ADC12MSC 1 0x0080 ADC12 Multiple SampleConversion ADC12CTLO Control Bits ttdefine ADC12SHTOO H 0x0001 ADC12 Sample Hold O Select Bit O ttdefine ADC12SHTO1 H 0x0002 ADC12 Sample Hold O Select Bit 1 ttdefine ADC12SHTO2 H 0x0004 ADC12 Sample Hold 0 Select Bit 2 ttdefine ADC12SHTO3 H 0x0008 ADC12 Sample Hold O Select Bit 3 ttdefine ADC12SHT10 H 0x0010 ADC12 Sample Hold 1 Select Bit O define ADC12SHT11 H 0x0020 ADC12 Sample Hold 1 Select Bit 1 ttdefine ADC12SHT12 H 0x0040 ADC12 Sample Hold 1 Select Bit 2 ttdefine ADC12SHT13 H 0x0080 ADC12 Sample Hold 1 Select Bit 3 define ADC12SHTO 0 0 0x100u ADC12 Sample Hold 0 Select Bit O ttdefine ADC12SHTO 1 1 0x100u ADC12 Sample Hold 0 Select Bit 1 define ADC12SHTO 2 2 0x100u ADC12 Sample Hold O Select Bit 2 Page 81 define ADC12SHTO_3 define ADC12SHTO_4 define ADC12SHTO_5 define ADC12SHTO_6 define ADC12SHTO_7 define ADC12SHTO_8 define ADC12SHTO_9 define ADC12SHTO_10 define ADC12SHTO_11 define ADC12SHTO_12 define ADC12SHTO_1
79. 22 initialize all ports to reduce power consumption P1DIR ALL PINS P1OUT ALL PINS OUT P2DIR ALL PINS P2OUT ALL PINS OUT P3DIR ALL PINS P3OUT ALL PINS OUT P4DIR ALL PINS P4OUT P4 DIR P5DIR ALL PINS PSOUT ALL PINS OUT P6DIR ALL PINS P6OUT ALL PINS OUT P7DIR ALL PINS P7OUT ALL PINS OUT P8DIR ALL PINS P8OUT ALL PINS OUT P9DIR ALL PINS P9OUT ALL PINS OUT set master clock and SMCLK to be 2 15Mhz UCSCTLO UCSCTLO INIT reset clock system UCSCTL1 UCSCTL1 INIT set frequency range UCSCTL2 UCSCTL2_INIT select specific frequency Page 23 UCSCTL3 UCSCTL3_INIT set reference clock UCSCTL4 UCSCTL4_INIT set system clock sources UCSCTL5 UCSCTL5_INIT set clock dividers UCSCTL6 UCSCTL6 INIT set special clock settings UCSCTL7 UCSCTL7_INIT set fault notifications UCSCTL8 UCSCTL8_INIT set special clock requests _enable_interrupt initialize all system software UART_init display_init adc_init calibrate calibrate the accelerometer chillin loop and keep resetting the adc interrupts for only call update position every once in a while if counter 0 update_position Page 24 prepare for another adc cycle ADC12CTLO ADC12SC _BIS_SR GIE counter 1 increment counter keeping track of when to update position c
80. 3 SFR 8BIT FCTL3 L FLASH Control 3 SFR 8BIT FCTL3 H FLASH Control 3 SFR 16BIT FCTLA FLASH Control 4 SFR 8BIT FCTL4 1 FLASH Control 4 SFR 8BIT FCTL4 FLASH Control 4 define FRPW 0 9600 Flash password returned by read define FWPW 500 Flash password for write define FXPW 0x3300 for use with XOR instruction Page 147 define FRKEY define FWKEY define FXKEY FCTL1 Control Bits define RESERVED define ERASE define MERAS define RESERVED define RESERVED define SWRT define WRT define BLKWRT FCTL1 Control Bits define RESERVED define ERASE_L define MERAS_L define RESERVED define RESERVED define SWRT_L define WRT_L define BLKWRT_L Page 148 0 9600 legacy definition Flash key returned by read 500 legacy definition Flash key for write 0x3300 legacy definition for use with instruction 0x0001 Reserved 0x0002 Enable bit for Flash segment erase 0x0004 Enable bit for Flash mass erase 0x0008 Reserved 0x0010 Reserved 0x0020 Smart Write enable 0x0040 Enable bit for Flash write 0x0080 Enable bit for Flash segment write 0x0001 Reserved 0x0002 Enable bit for Flash segment erase 0x0004 Enable bit for Flash mass erase 0x0008 Reserved 0x0010 Reserved
81. 3 define ADC12SHTO 14 define ADC12SHTO 15 define ADC12SHT1 0 define ADC12SHT1 1 define ADC12SHT1 2 define ADC12SHT1 3 define ADC12SHT1 4 define ADC12SHT1 5 define ADC12SHT1 6 define ADC12SHT1 7 define ADC12SHT1 8 define ADC12SHT1 9 Page 82 3 0x100u 4 0x100u 5 0x100u 6 0x100u 7 0x100u 8 0x100u 9 0x100u 10 0x100u 11 0x100u 12 0x100u 13 0x100u 14 0x100u 15 0x100u 0 0x1000u 1 0x1000u 2 0x1000u 3 0x1000u 4 0x1000u 5 0x1000u 6 0x1000u 7 0x1000u 8 0x1000u 9 0x1000u ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit 3 4 5 6 7 8 9 10 11 12 13 14 15
82. 3 USCIB1 transmit define DMA1TSEL_24 24 0x0100u DMA channel 1 transfer select 24 ADC12IFGx define DMA1TSEL_25 25 0x0100u DMA channel 1 transfer select 25 DAC12 OIFG define DMA1TSEL_26 26 0x0100u DMA channel 1 transfer select 26 DAC12 1IFG define DMA1TSEL__RES27 27 0x0100u channel 1 transfer select 27 Reserved define DMA1TSEL__RES28 28 0x0100u channel 1 transfer select 28 Reserved define DMA1TSEL_29 29 0x0100u DMA channel 1 transfer select 29 Multiplier ready define DMA1TSEL_30 30 0x0100u DMA channel 1 transfer select 30 previous DMA channel DMAOIFG define DMA1TSEL_31 31 0x0100u DMA channel 1 transfer select 31 ext Trigger define DMA2TSEL 0 0 0x0001u DMA channel 2 transfer select 0 REQ sw define DMA2TSEL_1 1 0x0001u DMA channel 2 transfer select 1 TimerO A TAOCCRO IFG define DMA2TSEL_2 2 0x0001u channel 2 transfer select 2 TimerO A TAOCCR2 IFG define DMA2TSEL_3 3 0x0001u channel 2 transfer select 3 Timer1_A TA1CCRO IFG Page 125 define DMA2TSEL 4 TA1CCR2 IFG define DMA2TSEL 5 TA2CCRO IFG define DMA2TSEL_6 TA2CCR2 IFG define DMA2TSEL 7 TBOCCRO IFG define DMA2TSEL 8 TBOCCR2 IFG define DMA2TSEL 9 ttdefine DMA2TSEL 10 ttdefine DMA2TSEL 11 ttdefine DMA2TSEL 12 ttdefine DMA2TSEL 13 ttdefine DMA2TSEL 1
83. 3 ttdefine DMA3TSEL 14 ttdefine DMA3TSEL 15 Hdefine DMA3TSEL 16 receive Hdefine DMA3TSEL 17 transmit Hdefine DMA3TSEL 18 receive Hdefine DMA3TSEL 19 transmit Page 128 3 0x0100u 4 0x0100u 5 0x0100u 6 0x0100u 7 0x0100u 8 0x0100u 9 0x0100u 10 0x0100u 11 0x0100u 12 0x0100u 13 0x0100u 14 0x0100u 15 0x0100u 16 0x0100u 17 0x0100u 18 0 0100 19 0 0100 channel 3 transfer select 3 channel 3 transfer select 4 channel 3 transfer select 5 2 DMA channel 3 transfer select 6 Timer2_A DMA channel 3 transfer select 7 TimerBO channel transfer select 8 0 DMA channel 3 transfer select 9 Reserved channel transfer select 10 DMA channel 3 transfer select 11 DMA channel 3 transfer select 12 DMA channel 3 transfer select 13 DMA channel 3 transfer select 14 DMA channel 3 transfer select 15 DMA channel 3 transfer select 16 DMA channel 3 transfer select 17 DMA channel 3 transfer select 18 DMA channel 3 transfer select 19 Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO USCIBO USCIBO define DMA3TSEL_20 20 0x0100u DMA channel 3 transfer select 20 USCIA1 receive define DMA3TSEL_21 21 0x0100u DMA channel 3 tran
84. 4 define DMA2TSEL 15 Hdefine DMA2TSEL 16 receive Hdefine DMA2TSEL 17 transmit Hdefine DMA2TSEL 18 receive Hdefine DMA2TSEL 19 transmit Hdefine DMA2TSEL 20 receive Page 126 4 0x0001u 5 0x0001u 6 0x0001u 7 0x0001u 8 0x0001u 9 0x0001u 10 0x0001u 11 0x0001u 12 0x0001u 13 0x0001u 14 0x0001u 15 0x0001u 16 0x0001u 17 0x0001u 18 0x0001u 19 0x0001u 20 0x0001u DMA channel 2 transfer select 4 Timer1_A DMA channel 2 transfer select 5 Timer2_A DMA channel 2 transfer select 6 Timer2_A DMA channel 2 transfer select 7 0 DMA channel 2 transfer select 8 0 DMA channel 2 transfer select 9 Reserved DMA channel 2 transfer select 10 DMA channel 2 transfer select 11 DMA channel 2 transfer select 12 DMA channel 2 transfer select 13 DMA channel 2 transfer select 14 DMA channel 2 transfer select 15 DMA channel 2 transfer select 16 DMA channel 2 transfer select 17 DMA channel 2 transfer select 18 DMA channel 2 transfer select 19 DMA channel 2 transfer select 20 Reserved Reserved Reserved Reserved Reserved Reserved USCIAO USCIAO USCIBO USCIBO USCIA1 define DMA2TSEL_21 21 0x0001u DMA channel 2 transfer select 21 USCIA1 transmit define DMA2TSEL_22 22 0x0001u DMA channel 2 transfer select 22 USCIB
85. 40 Comp 0x0080 Comp p X omp 0x0400 Comp 0x0800 Comp x omp 0x1000 Comp x omp 0x2000 Comp 0x4000 Comp 0x8000 Comp 0x0004 Comp 0x0008 Comp 0x0010 Comp 0x0020 Comp 0x0040 Comp 0x0080 Comp 0 0001 Interrupt Enable define CBIIE H define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED CBIV Definitions define CBIV_NONE define CBIV_CBIFG define CBIV_CBIIFG 0x0002 Comp 0x0400 Comp 0x0800 Comp 0x1000 Comp 0x2000 Comp 0x4000 Comp 0x8000 Comp Interrupt Enable Inverted Polarity 0x0000 Interrupt pending 0x0002 CBIFG 0x0004 CBIIFG FERA EE E E ER CRC Module RARE EEE EE REA EE define __MSP430_HAS_CRC__ Definition to show that Module is available define __MSP430_BASEADDRESS_CRC__ 0x0150 SFR_16BIT CRCDI SFR_8BIT CRCDI_L SFR_8BIT CRCDI_H SFR_16BIT CRCDIRB SFR_8BIT CRCDIRB_L Page 110 CRC Data In Register CRC Data In Register CRC Data In Register CRC data in reverse byte Register CRC d
86. 46 OxFFDC USCI A1 Receive Transmit CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine PORT1 VECTOR int47 OxFFDE Port 1 else define PORT1_VECTOR 47 1u OxFFDE Port 1 define PORT1_ISR func ISR_VECTOR func int47 OxFFDE Port 1 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine TIMER1 A1 VECTOR int48 OxFFEO 1 2 TA1 Helse define TIMER1_A1 VECTOR 48 lu Timer1_A3 CC1 2 1 Page 276 define TIMER1 A1 ISR func ISR_VECTOR func int48 OxFFEO Timer1 1 2 TA1 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define TIMER1 0 VECTOR int49 OxFFE2 Timer1_A3 CCO else define TIMER1 AO VECTOR 49 1u OxFFE2 Timer1_A3 CCO define TIMER1 AO ISR func ISR VECTOR func int49 OxFFE2 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define VECTOR int50 4 DMA else define DMA_VECTOR 50 1u OxFFE4 DMA define DMA_ISR func ISR_VECTOR func int50 OxFFE4 CCE V2 Style endif Hifdef__ASM_HEADER__ Begin defines for assembler define LDO_PWR_VECTOR int51 OxFFE6 LDO Power Management event else define LDO_PWR_VECTOR 51 lu
87. 7 Group 0 individually define SHR_1 1 0x2000u TimerO B7 Group 1 3 groups 1 2 3 4 5 6 define SHR_2 2 0x2000u TimerO B7 Group 2 2 groups 1 3 4 6 define SHR_3 3 0x2000u TimerO B7 Group 3 1 group all define TBCLGRP 0 0 0x2000u TimerO B7 Group 0 individually define TBCLGRP 1 1 0x2000u TimerO B7 Group 1 3 groups 1 2 3 4 5 6 define TBCLGRP 2 2 0x2000u TimerO B7 Group 2 2 groups 1 3 4 6 define TBCLGRP 3 3 0x2000u TimerO B7 Group 3 1 group all Hdefine TBSSEL TACLK 0 0x100u TimerO B7 clock source select O TACLK define TBSSEL ACLK 1 0x100u TimerO B7 clock source select 1 ACLK Hdefine TBSSEL__SMCLK 2 0x100u TimerO B7 clock source select 2 SMCLK define TBSSEL__INCLK 3 0x100u TimerO B7 clock source select 3 INCLK define CNTL__16 0 0x0800u Counter lenght 16 bit define CNTL__12 1 0x0800u Counter lenght 12 bit define 10 2 0x0800u Counter lenght 10 bit define CNTL__8 3 0x0800u Counter lenght 8 bit Page 225 Additional Timer Control Register bits are defined Timer A TBxCCTLx Control Bits define CLLD1 0x0400 Compare latch load source 1 define CLLDO 0x0200 Compare latch load source 0 define SLSHR1 0x0400 Compare latch load source 1 define SLSHRO 0 0200 Compare latch load source 0 define
88. 8 UCS Control Register 8 UCS Control Register 8 RESERVED RESERVED RESERVED Modulation Bit Counter Bit Modulation Bit Counter Bit Modulation Bit Counter Bit Modulation Bit Counter Bit Modulation Bit Counter Bit DCO TAP Bit 0 0 1 2 3 4 define 1 0x0200 define DCO2 0x0400 define DCO3 0 0800 define DCO4 0 1000 define RESERVED 0x2000 define RESERVED 0x4000 define RESERVED 0x8000 UCSCTLO Control Bits DCO TAP Bit 1 DCO TAP Bit 2 DCO TAP Bit 3 DCO TAP Bit 4 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Modulation Bit Counter 0 Modulation Bit Counter Bit 1 Modulation Bit Counter Bit 2 Modulation Bit Counter Bit 3 Modulation Bit Counter Bit 4 RESERVED RESERVED RESERVED define RESERVED 0x0001 define RESERVED 0x0002 define RESERVED 0x0004 define MODO L 0x0008 define 1 0x0010 define MOD2 1 0x0020 define MOD3 1 0x0040 define MODA L 0x0080 define RESERVED 0x2000 define RESERVED 0 4000 define RESERVED 0 8000 UCSCTLO Control Bits define RESERVED 0x0001 define RESERVED 0x0002 Page 230 RESERVED RESERVED define RESERVED 0x0004 RESERVED defin
89. 8 number of leds used on port 9 DEFINE P4_LED_LOW 0X8 bit for the lower bar on port 4 DEFINE P4 LED HIGH 0X10 bit for the higher bar on port 4 DEFINE PAUSE_DUR 0X4 number of wait cycles at end of calibration HDEFINE NUM ELEC 0X4 number of electrodes RAIL NOISE 255 common incorrect reading from electrodes DEFINE CONV VAL 25 value used to convert electrode reading into bar values DEFINE LOW TRIG 9 indicates low port 4 led should be lit HDEFINE P4 HIGH TRIG 10 indicates high port 4 led should be lit DEFINE INT RST value used to reset adc interrupt register sets up adc registers needed void adc init void calculates base values for accelerometer Page 39 void calibrate void determines if accelerometer is shifted and outputs strings to wifi void update_position void Hendif ADC_H_ Page 40 adc c Created on Jun 7 2012 Author Josh Fromm This file contains the code needed for the BioSleeve system to interact with all components requiring an analog to digital conversion namely the system s electrodes and accelerometer The file also contains some code for interacting with the display during a calibration procedure Table of Contents 1 adc init void sets up the registers needed for analog to digital V conversions to run Both the electrodes of the system a
90. 8BIT PBDS_H SFR_16BIT PBSEL SFR_8BIT PBSEL_L SFR_8BIT PBSEL_H SFR_16BIT PBIES SFR_8BIT PBIES_L SFR_8BIT PBIES_H SFR_16BIT PBIE SFR_8BIT PBIE_L SFR_8BIT PBIE_H SFR_16BIT PBIFG SFR_8BIT PBIFG_L SFR_8BIT PBIFG_H SFR_16BIT P3IV SFR 16BIT P4IV define P3IN define define P3DIR define P3REN define P3DS Page 161 Port B Resistor Drive Strenght Port Resistor Drive Strenght Port B Resistor Drive Strenght Port B Selection Port B Selection Port B Selection Port B Interrupt Edge Select Port B Interrupt Edge Select Port B Interrupt Edge Select Port B Interrupt Enable Port B Interrupt Enable Port B Interrupt Enable Port B Interrupt Flag Port B Interrupt Flag Port B Interrupt Flag Port 3 Interrupt Vector Word Port 4 Interrupt Vector Word 1 Port 3 Input PBOUT_L Port 3 Output PBDIR L Port 3 Direction PBREN 1 Port 3 Resistor Enable PBDS 1 Port 3 Resistor Drive Strenght define P3SEL PBSEL_L Port 3 Selection define P3IES PBIES L Port 3 Interrupt Edge Select define Port Interrupt Enable define P3IFG PBIFG L Port 3 Interrupt Flag Definitions for define P3IV_NONE 0x0000 No Interrupt pending define P3IFGO 0x0002
91. AIV_NONE define DMAIV_DMAOIFG define DMAIV_DMA1IFG define DMAIV_DMA2IFG define DMAIV_DMA3IFG define DMAIV_DMA4IFG define DMAIV_DMASIFG define DMAOTSEL_0 define DMAOTSEL_1 TAOCCRO IFG define DMAOTSEL_2 TAOCCR2 IFG define DMAOTSEL_3 TA1CCRO IFG define DMAOTSEL_4 TA1CCR2 IFG define DMAOTSEL_5 TA2CCRO IFG Page 121 5 0x1000u 6 0x1000u 7 0x1000u 0x0000 0x0002 0 0004 0 0006 0x0008 0x000A 0x000C 0 0x0001u 1 0x0001u 2 0x0001u 3 0x0001u 4 0x0001u 5 0x0001u DMA transfer mode 5 Repeated Block transfer DMA transfer mode 6 Repeated Burst Block DMA transfer mode 7 Repeated Burst Block No Interrupt pending DMAOIFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG DMASIFG channel 0 transfer select 0 DMA channel 0 transfer select 1 DMA channel 0 transfer select 2 DMA channel 0 transfer select 3 DMA channel 0 transfer select 4 DMA channel 0 transfer select 5 REQ sw TimerO A TimerO A 1 1 Timer2 A define DMAOTSEL 6 TA2CCR2 IFG Hdefine DMAOTSEL_7 TBOCCRO IFG define DMAOTSEL_8 TBOCCR2 IFG ttdefine DMAOTSEL 9 ttdefine DMAOTSEL 10 ttdefine DMAOTSEL 11 ttdefine DMAOTSEL 12 define DMAOTSEL 13 ttdefine DMAOTSEL 14 define DMAOTSEL 15 Hdefine DMAOTSEL 16 receive
92. ASTER_INIT set to SPI mode with CPU as master UCBOCTL1 126 CTL1 SMCLK SMCLK as USCI clock source UCBOBRO DC 100KHZ set baud rate to give desired data transfer UCBOBR1 0x0 UCBOI2CSA IMU_ADDR set slave address to the IMU P2SEL 12C_PORTS set 2 ports to be 2 mode return The ACK_check function simply holds until an acknowledge is received from the slave being interacted with and continues to hold until the 2 bus is free for further data transmission void ACK_check void while UCBOCTL1 amp START_BIT 1 0 wait for first ack while UCBOSTAT amp FREE_12C 0 wait until bus is free Page 56 return The IMU_write function takes an integer register value and an integer data value as input and writes the data value to the passed register of the IMU This is accomplished by following the general transmission protocol specified by the IMU namely Set transmit mode gt send start bit gt wait for acknowledge gt send register address gt wait for acknowledge gt send data to write gt wait for acknowledge gt send stop bit after this procedure is carried out the function returns void IMU_write int reg int data UCBOCTL1 12C_CTL1_TRANS_MODE set to transmit mode UCBOCTL1 START_BIT send start bit ACK_check UCBOTXBUF reg output register value to write to ACK_check UCBOTXBUF
93. BOCCR2 8 0x0001u DMA channel 4 transfer select 8 TimerBO TBOCCR2 IFG Hdefine DMA4TSEL__RES9 9 0x0001u DMA channel 4 transfer select 9 Reserved define DMA4TSEL__RES10 10 0x0001u channel 4 transfer select 10 Reserved di define DMA4TSEL__RES11 11 0x0001u DMA channel 4 transfer select 11 Reserved define DMA4TSEL__RES12 12 0x0001u DMA channel 4 transfer select 12 Reserved define DMA4TSEL RES13 13 0x0001u channel 4 transfer select 13 Reserved define DMA4TSEL__RES14 14 0x0001u DMA channel 4 transfer select 14 Reserved define DMA4TSEL RES15 15 0x0001u channel 4 transfer select 15 Reserved define DMA4TSEL__ define DMA4TSEL__ transmit Page 143 USCIAORX 16 0x0001u channel 4 transfer select 16 USCIAO USCIAOTX 17 0x0001u channel 4 transfer select 17 USCIAO define DMA4TSEL__USCIBORX 18 0 0001 DMA channel 4 transfer select 18 USCIBO receive define DMA4TSEL__USCIBOTX 19 0x0001u channel 4 transfer select 19 USCIBO transmit define DMA4TSEL_ USCIA1RX 20 0x0001u channel 4 transfer select 20 USCIA1 receive define DMA4TSEL__USCIA1TX 21 0 0001 DMA channel 4 transfer select 21 USCIA1 transmit define DMA4TSEL__USCIB1RX 22 0 0001 DMA channel 4 transfer select 22 USCIB1 receive define DMA4TSEL__
94. C user alarm RTCAIFG define RTOPSIFG 0x0008 RTC prescaler 0 RTOPSIFG define RT1PSIFG 0x000A prescaler 1 RT1PSIFG ttdefine RTCOFIFG 0x000C RTC Oscillator fault JERLER EEEE EEE SERA Jo EH EE IOROIOKCKIOROIORORICIOIOIOIORGIOR REEL ES EEE AE SFR Special Function Register Module TR EROE ERE EARL EA AEE ER define MSP430 HAS SFR Definition to show that Module is available define MSP430 BASEADDRESS SFR 0x0100 SFR 16BIT SFRIE1 Interrupt Enable 1 SFR 8BIT SFRIE1 1 Interrupt Enable 1 SFR 8BIT SFRIE1 Interrupt Enable 1 Page 202 SFRIE1 Control Bits define WDTIE 0x0001 WDT Interrupt Enable define OFIE 0x0002 Osc Fault Enable define Reserved 0 0004 define VMAIE 0x0008 Vacant Memory Interrupt Enable define NMIIE 0x0010 NMI Interrupt Enable define ACCVIE 0x0020 Flash Access Violation Interrupt Enable define JMBINIE 0x0040 JTAG Mail Box input Interrupt Enable define JMBOUTIE 0x0080 JTAG Mail Box output Interrupt Enable define WDTIE_L 0x0001 WDT Interrupt Enable define OFIE_L 0x0002 Osc Fault Enable define Reserved 0 0004 define VMAIE L 0x0008 Vacant Memory Interrupt Enable Hdefine NMIIE L 0x0010 NMI Interrupt Enable define ACCVIE_L 0x0020 Flash Access Violation Interrupt Enable define JMBINIE_L 0x0040
95. C121E11 H define ADC121E12 H define ADC121E13 H define ADC121E14 H define ADC121E15 define ADC121FGO define ADC12IFG1 define ADC12IFG2 define ADC121FG3 define ADC12IFGA define ADC121FG5 define ADC12IFG6 define ADC121FG7 Page 90 0 0004 0x0008 0 0010 0 0020 0 0040 0x0080 0 0001 0 0002 0 0004 0x0008 0 0010 0 0020 0 0040 0x0080 0 0001 0 0002 0 0004 0 0008 0 0010 0 0020 0 0040 0x0080 ADC12 Memory 2 ADC12 Memory 3 ADC12 Memory 4 ADC12 Memory 5 ADC12 Memory 6 ADC12 Memory 7 ADC12 Memory 8 ADC12 Memory 9 ADC12 Memory 10 ADC12 Memory 11 ADC12 Memory 12 ADC12 Memory 13 ADC12 Memory 14 ADC12 Memory 15 Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable ADC12 Memory 0 ADC12 Memory 1 ADC12 Memory 2 ADC12 Memory 3 ADC12 Memory 4 ADC12 Memory 5 ADC12 Memory 6 ADC12 Memory 7 Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag define ADC12IFG8 define ADC121FG9 define ADC121FG10 define ADC12IFG11 d
96. CIBORX receive define DMA3TSEL__USCIBOTX transmit define DMA3TSEL__USCIA1RX receive Page 141 6 0x0100u DMA channel 3 transfer select 6 Timer2_A 7 0x0100u DMA channel 3 transfer select 7 TimerBO 8 0x0100u DMA channel 3 transfer select 8 TimerBO 9 0x0100u DMA channel 3 transfer select 9 Reserved 10 0x0100u DMA channel 3 transfer select 10 Reserved 11 0x0100u DMA channel 3 transfer select 11 Reserved 12 0x0100u DMA channel 3 transfer select 12 Reserved 13 0x0100u DMA channel 3 transfer select 13 Reserved 14 0x0100u DMA channel 3 transfer select 14 Reserved 15 0x0100u DMA channel 3 transfer select 15 Reserved 16 0x0100u channel transfer select 16 USCIAO 17 0x0100u DMA channel 3 transfer select 17 USCIAO 18 0x0100u DMA channel 3 transfer select 18 USCIBO 19 0x0100u DMA channel 3 transfer select 19 USCIBO 20 0x0100u DMA channel 3 transfer select 20 USCIA1 define DMA3TSEL__USCIA1TX 21 0 0100 DMA channel 3 transfer select 21 USCIA1 transmit define DMA3TSEL__USCIB1RX 22 0 0100 DMA channel 3 transfer select 22 USCIB1 receive define DMA3TSEL__USCIB1TX 23 0x0100u channel 3 transfer select 23 USCIB1 transmit define DMA3TSEL__ADC12IFG 24 0x0100u DMA channel 3 transfer select 24 ADC121FGx define DMA3TSEL RES25 25 0x0100u DMA channel 3 tra
97. D Page 249 define RESERVED 0 0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0 0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0 2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED Ox8000 RESERVED UCSCTL7 Control Bits define DCOFFG_L 0x0001 DCO Fault Flag define XT1LFOFFG_L 0x0002 XT1 Low Frequency Oscillator Fault Flag define L 0x0004 High Frequency Oscillator 1 Fault Flag define XT2OFFG L 0x0008 High Frequency Oscillator 2 Fault Flag define RESERVED 0x0010 RESERVED define RESERVED 0x0020 RESERVED define RESERVED 0x0040 RESERVED define RESERVED 0x0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED Page 250 define RESERVED 0 2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0x8000 RESERVED UCSCTL7 Control Bits etine define RESERVED 0x0010 RESERVED etine X define RESERVED 0x0020 RESERVED etine X define RESERVED 0x0040 RESERVED eti
98. DER__ Begin defines for assembler define USCI AO VECTOR int56 OxFFFO USCI AO Receive Transmit Helse define USCI_AO_VECTOR 56 1u OxFFFO USCI AO Receive Transmit define USCI_AO_ISR func ISR_VECTOR func int56 OxFFFO USCI AO Receive Transmit CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler ttdefine WDT VECTOR int57 OxFFF2 Watchdog Timer Helse define WDT_VECTOR 57 OxFFF2 Watchdog Timer define WDT_ISR func ISR VECTOR func int57 OxFFF2 Watchdog Timer CCE V2 Style Hendif Hifdef__ASM_HEADER__ Begin defines for assembler define TIMERO_B1_VECTOR int58 OxFFF4 TimerO B7 1 6 TB Helse Hdefine TIMERO B1 VECTOR 58 1u OxFFF4 TimerO B7 CC1 6 TB define TIMERO B1 ISR func ISR VECTOR func int58 OxFFF4 TimerO B7 CC1 6 TB CCE V2 Style endif Hifdef ASM HEADER Begin defines for assembler define TIMERO_BO_VECTOR int59 OxFFF6 Timer0_B7 CCO Page 279 Helse define TIMERO BO VECTOR 59 1 OxFFF6 TimerO B7 CCO define TIMERO BO ISR func ISR VECTOR func int59 OxFFF6 TimerO B7 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define COMP B VECTOR int60 OxFFF8 Comparator else define COMP_B_VECTOR 60 1u OxFFF8 Comparator define COMP_B_ISR func IS
99. DEX_7 TOASIV Definitions define TAOIV_NONE define TAOIV_TAOCCR1 define TAOIV_TAOCCR2 define TAOIV_TAOCCR3 define TAOIV_TAOCCR4 define TAOIV_5 define 6 define TAOIV_TAOIFG Page 219 0x0001 0x0002 0x0004 0 000 0x000C 0 0x0001u 1 0x0001u 2 0x0001u 3 0x0001u 4 0x0001u 5 0x0001u 6 0x0001u 7 0x0001u 0x0000 0x0002 0x0004 0x0006 0x0008 OxOOOE Timer A Input divider expansion Bit Timer A Input divider expansion Bit Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion Timer A Input divider expansion No Interrupt pending TAOCCR1 CCIFG TAOCCR2 CCIFG TAOCCR3 CCIFG TAOCCRA CCIFG Reserved Reserved TAOIFG 0 Timer A Input divider expansion Bit 1 2 1 2 ty 1321 4 5 6 t 7 OE E EE Timer1 id define MSP430 HAS T1A3 Definition to show that Module is available define _ MSP430_BASEADDRESS_T1A3__ 0x0380 SFR_16BIT TA1CTL Timer1_A3 Control SFR_16BIT TA1CCTLO Timer1 Capture Compare Control 0 SFR_16BIT TA1CCTL1 Timer1_A3 Capture Compare Control 1 SFR
100. EE RIE JER Interrupt Vectors offset from OxFF80 EE EE EERE RARE ER EA ed pragma diag_suppress 1107 define VECTOR_NAME name name _ptr define EMIT_PRAGMA x Page 273 _Pragma x define CREATE_VECTOR name void const VECTOR_NAME name void long amp name define PLACE_VECTOR vector section EMIT_PRAGMA DATA_SECTION vector section define PLACE_INTERRUPT func EMIT_PRAGMA CODE_SECTION func text _isr define ISR VECTOR func offset CREATE VECTOR func N PLACE VECTOR VECTOR_NAME func offset PLACE INTERRUPT func Hifdef ASM HEADER Begin defines for assembler define PORT4 int37 OxFFCA Port 4 else define PORT4_VECTOR 37 1u OxFFCA Port 4 define PORT4_ISR func ISR_VECTOR func int37 OxFFCA Port 4 CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine PORT3 VECTOR int38 OxFFCC Port 3 else define PORT3_VECTOR 38 1u OxFFCC Port 3 define PORT3_ISR func ISR VECTOR func int38 OxFFCC Port 3 CCE V2 Style endif Hifdef ASM HEADER Begin defines for assembler define TIMER2 1 VECTOR int39 0 5 1 4 Page 274 Helse define TIMER2_A1 VECTOR 39 1u OxFFCE TimerO 5 CC1 4 TA define TIMER2 A1 ISR func ISR_VECTOR func int39 OxFFCE TimerO A5 CC1 4 TA CCE V2 Style
101. EFACC_H define CBREFO_0 define CBREFO 1 define CBREFO 2 define CBREFO_3 define CBREFO_4 define CBREFO_5 define CBREFO_6 define CBREFO_7 define CBREFO_8 Page 103 0x0010 0x0020 0 0040 0x0080 0 0001 0 0002 0 0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 Comp Reference Resistor Select Bit 4 Reference 1 Resistor Select Bit Reference 1 Resistor Select Bit Reference 1 Resistor Select Bit Comp Reference 1 Resistor Select Bit Comp B Reference 1 Resistor Select Bit Comp B Reference select Comp B Reference Source Bit 0 Comp B Reference Source Bit 1 0 1 2 3 4 Comp B Reference voltage level Bit 0 Comp B Reference voltage level Bit 1 Comp B Reference Accuracy Comp Comp Comp Comp Comp Comp Comp Comp Comp B Int B Int B Int B Int B Int B Int B Int B Int B Int Ref 0 Select 0 Ref 0 Select 1 Ref 0 Select 2 Ref 0 Select 3 Ref 0 Select 4 Ref 0 Select 5 Ref 0 Select 6 Ref 0 Select 7 Ref 0 Select 0 1 32 2 32 3 32 4 32 5 32 6 32 7 32 8 32 9 32 define CBREFO 9 define CBREFO 10 define
102. ESERVED 0x8000 Comp CBCTL1 Control Bits define CBPWRMDO_H 0x0001 Comp Power Mode Bit 0 define CBPWRMD1_H 0x0002 Comp B Power Mode Bit 1 define 0x0004 enable define CBMRVL H 0x0008 Level define CBMRVS_H 0x0010 Comp B Output selects between VREFO or VREF1 define RESERVED 0x2000 Comp B define RESERVED 0x4000 Comp B define RESERVED 0x8000 Comp B define CBFDLY_0 0x0000 Comp Filter delay 0 450ns define CBFDLY_1 0x0040 Comp B Filter delay 1 900ns define CBFDLY_2 0x0080 Comp Filter delay 2 1800ns define CBFDLY_3 B Filter delay 3 3600ns define CBPWRMD_0 0x0000 Comp B Power Mode High speed define CBPWRMD 1 0x0100 Comp B Power Mode 1 Normal define CBPWRMD 2 0x0200 Comp B Power Mode 2 Ultra Low define CBPWRMD 3 0x0300 Comp B Power Mode 3 Reserved Page 101 CBCTL2 Control Bits define CBREF00 define CBREFO1 define CBREFO2 define CBREF03 define CBREF04 define CBRSEL define CBRSO define CBRS1 define CBREF10 define CBREF11 define CBREF12 define CBREF13 define CBREF14 define CBREFLO define CBREFL1 define CBREFACC 0 0001 0 0002 0 0004 0x0008 0 0010 0 0020 0 0040 0x0080 0 0100
103. Each of the bars on the LED display is controlled by a different I O pin of the CPU Eight of the bars are controlled by port 9 all port 9 pins are used on the display and the last two are controlled by the pins P4 3 and P4 4 The display has two distinct functions The first is to show the time remaining for a calibration sequence It does this by showing a loading bar that moves across the display over the course of several seconds When the calibration is finished the display pauses momentarily with all bars lit before returning to its normal functioning During normal system operation the display is fed a magnitude form of the data read from the electrode array by the CPU Due to the refresh rate on the display being quite high and the electrodes having extreme variation in signal the displaying of electrode signals is often not very luminous The CPU interacts with the display by setting all of port 9 and the relevant portion of port 4 to 1 0 mode with direction set to output The LED corresponding to each pin can then be set by changing the output signal on the pin Electrode Array The system incorporates an array of 9 EasyTrode brand silver chloride electrodes for measuring muscle activity of the user The electrodes are separated into groups of two and fed into INA331 operational amplifiers with a gain of 100 The odd electrode is used as a reference and is not amplified After amplification the differential signal is fed to an ADC12 pin on
104. FR 16BIT PEDIR SFR 8 1 Page 167 Port E Input Port E Input Port E Input Port E Output Port E Output Port E Output Port E Direction Port E Direction SFR_8BIT PEDIR_H SFR_16BIT PEREN SFR_8BIT PEREN_L SFR_8BIT PEREN_H SFR_16BIT PEDS SFR_8BIT PEDS_L SFR_8BIT PEDS_H SFR_16BIT PESEL SFR_8BIT PESEL_L SFR_8BIT PESEL_H define P9IN define POOUT define P9DIR define POREN define P9DS define POSEL Port E Direction Port E Resistor Enable Port E Resistor Enable Port E Resistor Enable Port E Resistor Drive Strenght Port E Resistor Drive Strenght Port E Resistor Drive Strenght Port E Selection Port E Selection Port E Selection L Port 9 Input PEOUT L Port 9 Output PEDIR Port 9 Direction PEREN L Port 9 Resistor Enable PEDS 1 Port 9 Resistor Drive Strenght PESEL 1 Port 9 Selection A EEUU EET EUER DIGITAL I O Port Pull up Pull down Resistors Ke define MSP430 HAS PORTJ Definition to show that Module is available Page 168 define _MSP430_BASEADDRESS_PORTJ_R__ 0x0320 SFR_16BIT PJIN Port J Input SFR SBIT PJIN 1 Port J Input SFR SBIT PJIN Port J Input SFR 16BIT PJOUT Port J Output SFR SBIT PJOUT 1 Po
105. Hendif Hifdef 5 HEADER Begin defines for assembler Hdefine TIMER2 AO VECTOR int40 OxFFDO Timer0_A5 CCO else define 2 0 40 1 OxFFDO Timer0_A5 define TIMER2 AO ISR func ISR_VECTOR func int40 OxFFDO TimerO 5 CCE V2 Style Hendif Hifdef __ASM_HEADER__ Begin defines for assembler Hdefine RTC_VECTOR int42 OxFFD4 RTC Helse define RTC_VECTOR 42 lu OxFFD4 RTC define RTC_ISR func ISR_VECTOR func int42 OxFFD4 RTC CCE V2 Style endif Hifdef ASM HEADER Begin defines for assembler define PORT2_VECTOR int44 OxFFD8 Port 2 else define PORT2_VECTOR 44 1u OxFFD8 Port 2 define PORT2_ISR func ISR VECTOR func int44 OxFFD8 Port 2 CCE V2 Style Hendif Page 275 Hifdef ASM HEADER Begin defines for assembler define USCI 1 VECTOR int45 OxFFDA USCI B1 Receive Transmit Helse define USCI_B1_VECTOR 45 1u OxFFDA USCI 1 Receive Transmit define USCI_B1_ISR func ISR VECTOR func int45 OxFFDA USCI B1 Receive Transmit CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define USCI A1 VECTOR int46 OxFFDC USCI 1 Receive Transmit Helse define USCI 1 VECTOR 46 1u OxFFDC USCI 1 Receive Transmit define USCI_A1_ISR func ISR VECTOR func int
106. IS_SR GIE display_wait perform a wait cycle if x_val gt MIN_THRESHOLD amp x_val lt MAX_THRESHOLD check if the x read is valid x_base x_val if so increment base and counter x_count 1 if y_val gt MIN_THRESHOLD amp y_val lt MAX_THRESHOLD check if y read is valid y_base y_val if so increment base and counter y_count 1 if z val gt MIN THRESHOLD amp z val lt MAX THRESHOLD check if z read is valid 2 base z_val if so increment base and counter z_count 1 z_base z_base z_count take the average of the bases y_base y_base y_count x_base x_base x_count P4 LED LOW finish loading display display_wait P4_LED_HIGH for j 0 j lt PAUSE DUR j pause before clearing display display_wait clear_display uncalibrated CALIBRATED indicate that the accelerometer is calibrated return the update_position function determines if the accelerometer is sufficiently shifted from its base position to warrant sending a character via wifi The function accomplishes this by comparing the reading from the accelerometer with the calculated base position for the axis in question plus a threshold Page 46 value If the read value is above or below the thresholds a character is sent Because the system currently uses a two dimensional implement
107. L define CBF define CBIES define CBSHORT define CBEX define CBFDLYO define CBFDLY1 define CBPWRMDO define CBPWRMD1 define CBON define define CBMRVS define RESERVED define RESERVED define RESERVED 0x0002 B Output Polarity 0x0004 Comp Enable Output Filter 0x0008 Comp B Interrupt Edge Select 0x0010 Comp B Input Short 0x0020 Comp Exchange Inputs 0x0040 Comp B Filter delay Bit O 0x0080 Comp B Filter delay Bit 1 0x0100 Comp Power Mode Bit 0 0 0200 Comp Power Mode Bit 1 0x0400 Comp B enable 0x0800 CBMRV Level 0x1000 Output selects between VREFO or VREF1 0x2000 Comp B 0x4000 Comp B 0x8000 Comp B CBCTL1 Control Bits define 1 define CBOUTPOL_L define 1 define CBIES 1 define CBSHORT_L define CBEX_L define CBFDLYO_L Page 100 0x0001 Output 0x0002 Comp B Output Polarity 0x0004 Enable Output Filter 0x0008 Comp B Interrupt Edge Select 0x0010 Comp B Input Short 0x0020 Comp B Exchange Inputs 0x0040 Comp B Filter delay Bit O define CBFDLY1_L 0x0080 Comp B Filter delay Bit 1 define RESERVED 0x2000 Comp define RESERVED 0x4000 Comp define R
108. LO 0x0001 5 5 SVM high side Reset Release Voltage Level Bit 0 define SVSMHRRL1 0x0002 5 5 and SVM high side Reset Release Voltage Level Bit 1 define SVSMHRRL2 0x0004 5 5 SVM high side Reset Release Voltage Level Bit 2 define SVSMHDLYST 0x0008 SVS and SVM high side delay status define SVSHMD 0x0010 SVS high side mode define SVSMHEVM 0x0040 SVS and SVM high side event mask define SVSMHACE 0x0080 SVS and SVM high side auto control enable define SVSHRVLO 0x0100 SVS high side reset voltage level Bit O define SVSHRVL1 0 0200 SVS high side reset voltage level Bit 1 define SVSHE 0x0400 SVS high side enable define SVSHFP 0x0800 SVS high side full performace mode define SVMHOVPE 0x1000 5 high side over voltage enable Page 176 define SVMHE 0x4000 5 high side enable define SVMHFP 0x8000 5 high side full performace mode SVSMHCTL Control Bits define SVSMHRRLO_L 0x0001 5 5 and SVM high side Reset Release Voltage Level Bit 0 define SVSMHRRL1_L 0x0002 SVS and SVM high side Reset Release Voltage Level Bit 1 define SVSMHRRL2_L 0x0004 SVS and SVM high side Reset Release Voltage Level Bit 2 define SVSMHDLYST L 0x0008 SVS and SVM high side delay status ttdefine SVSHMD L 0x0010 SVS high side mode ttdefine SVSMHEVM L 0x0040 SVS a
109. LREFO define SELREF1 define SELREF2 define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0 0080 0 0100 0 0200 0 0400 0 0800 0 1000 0 2000 0 4000 0 8000 UCSCTL3 Control Bits Page 236 Multiply Selected Loop Freq By 4 Multiply Selected Loop Freq By 8 Multiply Selected Loop Freq By 16 Multiply Selected Loop Freq By 32 Reference Divider Bit 0 Reference Divider Bit 1 Reference Divider Bit 2 RESERVED FLL Reference Clock Select Bit 0 FLL Reference Clock Select Bit 1 FLL Reference Clock Select Bit 2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED define FLLREFDIVO_L 0 0001 Reference Divider Bit O define FLLREFDIV1_L 0x0002 Reference Divider Bit 1 define FLLREFDIV2_L 0x0004 Reference Divider Bit 2 define RESERVED 0x0008 RESERVED Hdefine SELREFO L 0x0010 FLL Reference Clock Select Bit O Hdefine SELREF1 L 0x0020 FLL Reference Clock Select Bit 1 define SELREF2 L 0x0040 FLL Reference Clock Select Bit 2 define RESERVED 0x0080 RESERVED
110. Level Bit 1 define SVSMLRRL2_L 0x0004 SVS and SVM low side Reset Release Voltage Level Bit 2 define SVSMLDLYST_L 0x0008 5 5 and SVM low side delay status define SVSLMD_L 0x0010 SVS low side mode define SVSMLEVM_L 0x0040 SVS and SVM low side event mask define SVSMLACE_L 0x0080 SVS and SVM low side auto control enable SVSMLCTL Control Bits define SVSLRVLO_H 0x0001 SVS low side reset voltage level Bit O Page 179 define SVSLRVL1_H define SVSLE_H define SVSLFP_H define SVMLOVPE_H define SVMLE_H define SVMLFP_H define SVSMLRRL_O Si define SVSMLRRL_1 yi define SVSMLRRL 2 i define SVSMLRRL 3 define SVSMLRRL_4 define SVSMLRRL_5 define SVSMLRRL_6 define SVSMLRRL_7 E define SVSLRVL 0 define SVSLRVL 1 define SVSLRVL 2 Page 180 0x0002 0x0004 0x0008 0x0010 0x0040 0x0080 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0000 0x0100 0x0200 SVS low side reset voltage level Bit 1 SVS low side enable SVS low side full performace mode SVM low side over voltage enable SVM low side enable SVM low side full performace mode SVS and SVM low side Reset Release Voltage Level O SVS and SVM low side Reset Release Voltage Level 1 SVS and SVM low side Reset Release Voltage Level 2
111. MCLK Source Divider 3 define DIVS_4 0x0040 5 Source Divider 4 define DIVS_5 0x0050 SMCLK Source Divider 5 define DIVS_6 0x0060 5 Source Divider 6 define DIVS_7 0x0070 SMCLK Source Divider 7 define DIVS_ 1 0x0000 5 Source Divider f SMCLK 1 define DIVS_ 2 0x0010 5 Source Divider f SMCLK 2 define DIVS_ 4 0x0020 5 Source Divider f SMCLK 4 define DIVS_ 8 0x0030 5 Source Divider f SMCLK 8 define DIVS_ 16 0x0040 5 Source Divider f SMCLK 16 define DIVS__32 0 0050 SMCLK Source Divider f SMCLK 32 Page 245 define 0 define DIVA 1 define DIVA_2 define DIVA_3 define DIVA_4 define DIVA_5 define DIVA_6 define DIVA_7 define DIVA__1 define 2 define DIVA 4 define DIVA_ 8 define DIVA 16 define DIVA 32 define DIVPA 0 define 1 define 2 define DIVPA 3 define DIVPA 4 define DIVPA 5 define DIVPA 6 define DIVPA 7 Page 246 0x0000 0x0100 0x0200 0x0300 0x0400 0x0500 0x0600 0x0700 0x0000 0x0100 0x0200 0x0300 0x0400 0x0500 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 ACLK Source Divider 0 ACLK Source Divider 1 ACLK Source Divider 2 ACLK Source Divider 3 ACLK Source Divider 4 ACLK Source Divider 5 ACLK Source D
112. MCTL Helse define ADC12MCTL Hendif ADC12MCTL ADC12 Memory Control ADC12MCTLO ADC12 Memory Control for assembler char ADC12CTLO Control Bits ttdefine ADC12SC ttdefine ADC12ENC define ADC12TOVIE define ADC12OVIE define ADC120N ttdefine ADC12REFON define ADC12REF2 DN ttdefine ADC12MSC define ADC12SHTOO define ADC12SHTO1 ttdefine ADC12SHTO2 define ADC12SHTO3 define ADC12SHT10 ttdefine ADC12SHT11 ttdefine ADC12SHT12 define ADC12SHT13 Page 80 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 amp ADC12MCTLO ADC12 Memory Control for C ADC12 Start Conversion ADC12 Enable Conversion ADC12 Timer Overflow interrupt enable ADC12 Overflow interrupt enable ADC12 On enable ADC12 Reference on ADC12 Ref 0 1 5V 1 2 5V ADC12 Multiple SampleConversion ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 0 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit ADC12 Sample Hold 1 Select Bit 0 1 224 3 0 1 2 3 ADC12CTLO Control Bits define ADC12SC_L 0x0001 ADC12 Start Conversion define ADC12bENC 1 0x0002 ADC
113. MSP430F5335 BioSleeve Prototype Manual and System Information Josh Fromm California Institute of Technology 1200 E California Blvd MC 104 44 Pasadena CA 91125 Page 1 Index 1 Basic System Description Page 3 2 User Manual Page 4 3 System Hardware Overview Page 7 4 Hardware Manual Page 9 5 Software Manual Page 14 6 System Code Page 21 Page 2 Basic System Description The system is a motion and muscle movement detection device that transmits data over wifi In its current implementation the data measured by the system is used to play the game Ball Blasters Infinity Figure 1 Birds eye image of BioSleeve system with numbered components Page 3 User Manual Each of the numbered components in figure 1 are needed for the user to properly interact with BioSleeve system and will be addressed individually 1 The four LEDs labeled 1 indicate the status of the system s wifi module The user determine if a connection has been properly established by checking that the third LED from the left is on not blinking The fourth LED from the left blinks whenever a data transfer occurs via the wifi module This allows the user to easily check to see if data is being transmitted The first two LEDs are less useful for normal use of the system 2 The component labeled 2 is the system s electrode array For proper use the user should peel the electrodes off of the attached plastic and s
114. M_4 Page 244 0x0008 0x0080 0 0001 0 0002 0x0004 0x0800 0 0010 0 0020 0 0040 0 8000 0 0000 0 0001 0 0002 0 0003 0 0004 SMCLK Divider Bit 0 SMCLK Divider Bit 1 SMCLK Divider Bit 2 RESERVED RESERVED RESERVED RESERVED RESERVED ACLK Divider Bit 0 ACLK Divider Bit 1 ACLK Divider Bit 2 RESERVED ACLK from Pin Divider Bit 0 ACLK from Pin Divider Bit 1 ACLK from Pin Divider Bit 2 RESERVED MCLK Source Divider 0 MCLK Source Divider 1 MCLK Source Divider 2 MCLK Source Divider 3 MCLK Source Divider 4 define DIVM_5 0x0005 MCLK Source Divider 5 define DIVM_6 0x0006 MCLK Source Divider 6 define DIVM_7 0x0007 Source Divider 7 define 1 0x0000 MCLK Source Divider f MCLK 1 define DIVM 2 0x0001 Source Divider f MCLK 2 define DIVM 4 0x0002 Source Divider f MCLK 4 define DIVM 8 0x0003 Source Divider f MCLK 8 define DIVM__16 0x0004 Source Divider f MCLK 16 define DIVM__32 0x0005 MCLK Source Divider f MCLK 32 define DIVS_0 0x0000 5 Source Divider 0 define DIVS_1 0x0010 5 Source Divider 1 define DIVS_2 0x0020 5 Source Divider 2 define DIVS_3 0x0030 S
115. O TBOCCRO IFG define DMAOTSEL__TBOCCR2 TBOCCR2 IFG define DMAOTSEL__RES9 define DMAOTSEL__RES10 define DMAOTSEL__RES11 define DMAOTSEL__RES12 define DMAOTSEL__RES13 di define DMAOTSEL RES14 n Page 134 1 0x0001u DMA channel 0 transfer select 1 TimerO A 2 0x0001u DMA channel 0 transfer select 2 TimerO A 3 0x0001u DMA channel 0 transfer select 3 Timer1 A 4 0x0001u DMA channel O transfer select 4 Timer1 5 0x0001u DMA channel 0 transfer select 5 Timer2 A 6 0x0001u channel 0 transfer select 6 Timer2 7 0x0001u DMA channel 0 transfer select 7 TimerBO 8 0x0001u DMA channel 0 transfer select 8 TimerBO 9 0x0001u channel O transfer select 9 Reserved 10 0x0001u DMA channel 0 transfer select 10 Reserved 11 0x0001u DMA channel 0 transfer select 11 Reserved 12 0x0001u DMA channel 0 transfer select 12 Reserved 13 0x0001u DMA channel 0 transfer select 13 Reserved 14 0x0001u channel 0 transfer select 14 Reserved define DMAOTSEL RES15 15 0x0001u DMA channel 0 transfer select 15 Reserved define DMAOTSEL USCIAORX 16 0x0001u DMA channel 0 transfer select 16 USCIAO receive define DMAOTSEL USCIAOTX 17 0x0001u channel 0 transfer select 17 USCIAO transmit define DMAOTSEL USCIBORX 18 0 0001 DMA channel O transfer sel
116. OD_7 define CCIS_0 define CCIS_1 define CCIS_2 define CCIS_3 define CM_0 define CM_1 define CM_2 define CM_3 Page 218 0x0020 Output mode 0 0x0010 interrupt enable 0x0008 Capture input signal read 0x0004 0x0002 PWM Output signal if output mode 0 Capture compare overflow flag 0x0001 interrupt flag 0 0x20u 1 0x20u 2 0x20u 3 0x20u 4 0x20u 5 0x20u 6 0x20u 7 0x20u 0 0x1000u 1 0x1000u 2 0x1000u 3 0x1000u 0 0x4000u 1 0x4000u 2 0x4000u 3 0x4000u PWM output mode 0 output only PWM output mode 1 set PWM output mode 2 PWM toggle reset PWM output mode 3 PWM set reset PWM output mode 4 toggle PWM output mode 5 Reset PWM output mode 6 PWM toggle set PWM output mode 7 PWM reset set Capture input select 0 Capture input select 1 Capture input select 2 GND Capture input select 3 Vcc Capture mode 0 disabled Capture mode 1 pos edge Capture mode 1 neg edge Capture mode 1 both edges Control Bits define TAIDEXO define TAIDEX1 define TAIDEX2 define TAIDEX_0 define TAIDEX_1 define TAIDEX_2 define TAIDEX_3 define TAIDEX_4 define TAIDEX_5 define TAIDEX_6 define TAI
117. OIFG define DMA1TSEL__DMAEO 31 0x0100u DMA channel 1 transfer select 31 ext Trigger DMAEO define DMA2TSEL DMA REQ 0 0 0001 DMA channel 2 transfer select 0 DMA_REQ sw define DMA2TSEL TAOCCRO 1 0x0001u DMA channel 2 transfer select 1 TimerO A TAOCCRO IFG define DMA2TSEL TAOCCR2 2 0x0001u TAOCCR2 IFG define DMA2TSEL TA1CCRO 3 0x0001u TA1CCRO IFG define DMA2TSEL TA1CCR2 4 0 00014 TA1CCR2 IFG define DMA2TSEL TA2CCRO 5 0x0001u TA2CCRO IFG define DMA2TSEL TA2CCR2 6 0 00014 TA2CCR2 IFG define DMA2TSEL TBOCCRO 7 0x0001u TBOCCRO IFG define DMA2TSEL TBOCCR2 8 0x0001u TBOCCR2 IFG Page 138 DMA channel 2 transfer select 2 DMA channel 2 transfer select 3 DMA channel 2 transfer select 4 DMA channel 2 transfer select 5 DMA channel 2 transfer select 6 DMA channel 2 transfer select 7 DMA channel 2 transfer select 8 TimerO A Timer1 Timer1 Timer2 A Timer2 A TimerBO TimerBO define DMA2TSEL__RES9 define DMA2TSEL__RES10 define DMA2TSEL__RES11 define DMA2TSEL__RES12 define DMA2TSEL__RES13 define DMA2TSEL__RES14 define DMA2TSEL__RES15 define DMA2TSEL__USCIAORX receive define DMA2TSEL__USCIAOTX transmit define DMA2TSEL__USCIBORX receive define DMA2TSEL__USCIBOTX transmit
118. ONTINUOUS 2 0x10u Timer A mode control 2 Continuous up define MC__CONTINOUS 2 0x10u Legacy define define MC__UPDOWN 3 0x10u Timer A mode control 3 Up Down define ID 1 0 0x40u Timer A input divider O 1 Hdefine ID 2 1 0x40u Timer A input divider 1 2 Hdefine ID 4 2 0x40u Timer A input divider 2 4 Hdefine ID 8 3 0x40u Timer A input divider 8 define TASSEL 0 0x100u Timer A clock source select O TACLK Hdefine TASSEL ACLK 1 0x100u Timer clock source select 1 ACLK define TASSEL SMCLK 2 0x100u Timer A clock source select 2 SMCLK define TASSEL 3 0x100u Timer A clock source select 3 INCLK TAxCCTLx Control Bits define CM1 0x8000 Capture mode 1 define CMO 0x4000 Capture mode 0 define CCIS1 0x2000 Capture input select 1 define CCISO 0x1000 Capture input select 0 define SCS 0x0800 Capture sychronize define SCCI 0x0400 Latched capture signal read define CAP 0x0100 Capture mode 1 Compare mode 0 define OUTMOD2 0x0080 Output mode 2 define OUTMOD1 0x0040 Output mode 1 Page 217 define OUTMODO define CCIE define CCI define OUT define COV define CCIFG define OUTMOD_0 define OUTMOD_1 define OUTMOD_2 define OUTMOD_3 define OUTMOD_4 define OUTMOD_5 define OUTMOD_6 define OUTM
119. PM2 bis SR register LPM2 bits Enter Low Power Mode 2 define LPM2 EXIT bic SR register on exit LPM2 bits Exit Low Power Mode 2 define LPM3 bis SR register LPM3 bits Enter Low Power Mode 3 define LPM3 EXIT bic SR register on exit LPM3 bits Exit Low Power Mode 3 define LPMA bis SR register LPMA bits Enter Low Power Mode 4 define EXIT bic SR register on exit LPMA bits Exit Low Power Mode 4 endif End defines for C Jo E EE EE EE ER CPU RATA AAA MIRE EA Roe E EE E Hdefine MSP430 HAS MSP430XV2 Definition to show that it has MSP430XV2 CPU ES OE TERRE AE RE TE ONG NOE e ER RR E TERE Eh PERIPHERAL FILE MAP e RE e RE RE IRE ACER ERE e Ous E TE SEA REC RATE e e RE E E e ee RAL EE Page 75 ADC12 PLUS EEE E e E AE RR E E ET define MSP430 HAS ADC12 PLUS _ Definition to show that Module available define MSP430 BASEADDRESS ADC12 PLUS 0x0700 SFR 16BIT ADC12CTLO SFR 8BIT ADC12CTLO 1 SFR 8BIT ADC12CTLO SFR 16BIT ADC12CTL1 SFR 8BIT ADC12CTL1 1 SFR 8BIT ADC12CTL1 Hl SFR 16BIT ADC12CTL2 SFR 8BIT ADC12CTL2 1 SFR_8BIT ADC12CTL2_H SFR_16BIT ADC12IFG SFR_8BIT ADC12IFG_L SFR_8BIT ADC12IFG_H SFR_16BIT ADC12IE SFR_8BIT ADC12IE_L SFR_8BIT ADC12IE_H SFR_16BIT ADC12IV SFR_8BIT ADC12IV_L SFR_8BIT ADC12IV_H Page 76 ADC12 Control 0
120. Port A Interrupt Flag Port 1 Interrupt Vector Word Port 2 Interrupt Vector Word PAIN 1 Port 1Input 1 1 1 PADS 1 PASEL 1 Port 1 Output Port 1 Direction Port 1 Resistor Enable Port 1 Resistor Drive Strenght Port 1 Selection PAIES 1 Port 1 Interrupt Edge Select 1 Port 1 Interrupt Enable PAIFG_L 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A Port 1 Interrupt Flag No Interrupt pending P1IV P1IFG 0 P1IFG 1 P11FG 2 P11FG 3 P1IV 4 define P1IV_P11FG5 define P1IV P1IFG6 define P1IV_P11FG7 define P2IN define P2OUT define P2DIR define P2REN define P2DS define P2SEL define 21 5 define P2IE define P2IFG Definitions for P2IV define 2 define P2IV_P2IFGO define P2IV_P2IFG1 define P2IV_P2IFG2 define P2IV_P2IFG3 define P2IV_P2IFG4 define P2IV_P2IFG5 define P2IV_P2IFG6 define P2IV P2IFG7 Page 159 0x000C 0x000E 0x0010 P1IV P1IFG 5 P1IV 6 7 PAIN Port 2 Input PAOUT H PADIR_H PAREN_H PADS_H PASEL_H PAIES_H Port 2 Output Port 2 Direction Port 2 Resistor Enable Port 2 Resistor Drive Strenght Port 2 Selection Port 2 Interrupt
121. RS2 define UCBRS1 define UCBRSO define UCOS16 define UCBRF_0 define UCBRF_1 define UCBRF_2 define UCBRF_3 define UCBRF_4 define UCBRF_5 define UCBRF_6 define UCBRF_7 define UCBRF_8 define UCBRF_9 define UCBRF_10 define UCBRF_11 define UCBRF_12 define UCBRF_13 define UCBRF_14 Page 259 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0 0 0 0 0xCO 0 00 USCI First Stage Modulation Select 3 USCI First Stage Modulation Select 2 USCI First Stage Modulation Select 1 USCI First Stage Modulation Select 0 USCI Second Stage Modulation Select 2 USCI Second Stage Modulation Select 1 USCI Second Stage Modulation Select 0 USCI 16 times Oversampling enable USCI First Stage Modulation 0 USCI First Stage Modulation 1 USCI First Stage Modulation 2 USCI First Stage Modulation 3 USCI First Stage Modulation 4 USCI First Stage Modulation 5 USCI First Stage Modulation 6 USCI First Stage Modulation 7 USCI First Stage Modulation 8 USCI First Stage Modulation 9 USCI First Stage Modulation A USCI First Stage Modulation B USCI First Stage Modulation C USCI First Stage Modulation D USCI First Stage Modulation E define UCBRF_15 define UCBRS_
122. R_L SFR_8BIT PADIR_H SFR_16BIT PAREN SFR_8BIT PAREN_L SFR_8BIT PAREN_H SFR_16BIT PADS SFR_8BIT PADS_L SFR_8BIT PADS_H SFR_16BIT PASEL SFR_8BIT PASEL_L SFR_8BIT PASEL_H SFR_16BIT PAIES SFR_8BIT PAIES_L SFR_8BIT PAIES_H SFR_16BIT PAIE SFR_8BIT PAIE_L SFR_8BIT PAIE_H Page 157 Port A Input Port A Input Port A Input Port A Output Port A Output Port A Output Port A Direction Port A Direction Port A Direction Port A Resistor Enable Port A Resistor Enable Port A Resistor Enable Port Resistor Drive Strenght Port A Resistor Drive Strenght Port A Resistor Drive Strenght Port A Selection Port A Selection Port A Selection Port A Interrupt Edge Select Port A Interrupt Edge Select Port A Interrupt Edge Select Port A Interrupt Enable Port A Interrupt Enable Port A Interrupt Enable SFR_16BIT PAIFG SFR_8BIT PAIFG_L SFR_8BIT PAIFG_H SFR 16BIT P1IV SFR 16BIT P21V define P1IN define PLOUT define P1DIR define define P1DS define P1SEL define P1IES define P1IE define P1IFG Definitions for P1IV define P1IV_NONE define P1IV P1IFGO Hdefine P1IV P1IFG1 define P1IV P1IFG2 define P1IV P1IFG3 define P1IV P1IFG4 Page 158 Port A Interrupt Flag Port A Interrupt Flag
123. R_VECTOR func int60 OxFFF8 Comparator B CCE V2 Style Hendif Hifdef 5 HEADER Begin defines for assembler define UNMI VECTOR int61 OxFFFA User Non maskable else define UNMI_VECTOR 61 1 OxFFFA User Non maskable define UNMI_ISR func ISR_VECTOR func int61 OxFFFA User Non maskable CCE V2 Style Hendif Hifdef__ASM_HEADER__ Begin defines for assembler Hdefine 5 5 62 System Non maskable Helse define 5 5 62 1u OxFFFC System Non maskable define SYSNMI_ISR func ISR_VECTOR func int62 OxFFFC System Non maskable CCE V2 Style Hendif Page 280 Hifdef ASM HEADER Begin defines for assembler define RESET VECTOR reset OxFFFE Reset Highest Priority Helse define RESET_VECTOR 63 1u OxFFFE Reset Highest Priority define RESET_ISR func ISR_VECTOR func int63 OxFFFE Reset Highest Priority CCE V2 Style Hendif E int End of Modules CEI Pt are E Hifdef cplusplus endif extern endif ifndef MSP430F5335 Page 281
124. SFR_16BIT UCA1BRW USCI A1 Baud Word Rate 0 SFR_8BIT UCA1BRW_L USCI 1 Baud Word Rate 0 SFR_8BIT UCA1BRW_H USCI 1 Baud Word Rate 0 Hdefine UCA1BRO UCA1BRW_L USCI A1 Baud Rate 0 define UCA1BR1 UCA1BRW_H USCI A1 Baud Rate 1 SFR_8BIT UCA1MCTL USCI 1 Modulation Control SFR_8BIT UCA1STAT USCI A1 Status Register SFR_8BIT UCA1RXBUF USCI A1 Receive Buffer SFR 8BIT UCA1TXBUF USCI A1 Transmit Buffer SFR 8BIT UCA1ABCTL USCI A1 LIN Control SFR 16BIT UCA1IRCTL USCI A1 IrDA Transmit Control Page 266 SFR_8BIT UCA1IRCTL_L USCI A1 IrDA Transmit Control SFR_8BIT UCA1IRCTL_H USCI A1 IrDA Transmit Control define UCA1IRTCTL USCI A1 IrDA Transmit Control define UCA1IRRCTL H USCI A1 IrDA Receive Control SFR_16BIT UCA1ICTL USCI 1 Interrupt Enable Register SFR_8BIT UCA1ICTL_L USCI 1 Interrupt Enable Register SFR_8BIT UCA1ICTL_H USCI A1 Interrupt Enable Register define UCA1IE UCA1ICTL L USCI A1 Interrupt Enable Register define UCA1IFG H USCI A1 Interrupt Flags Register SFR_16BIT UCA1IV USCI A1 Interrupt Vector Register dd di E ERRE USCIB1 FERIE EEE KE E ORA E E IA ER define MSP430 HAS USCI 1 Definition to show that Module is available define _MSP430_BASEADDRESS_USCI_B1__ 0x0620 SFR_16BIT UCB1CTLWO USCI B1 Contr
125. SFR_20BIT DMAODA SFR_16BIT DMAODAL SFR_16BIT DMAOSZ SFR_16BIT DMA1CTL SFR_8BIT DMA1CTL_L SFR_8BIT DMA1CTL_H SFR_20BIT DMA1SA SFR_16BIT DMA1SAL SFR_20BIT DMA1DA Page 112 Module Control 3 DMA Module Control 3 DMA Module Control 4 DMA Module Control 4 DMA Module Control 4 DMA Interrupt Vector Word DMA Interrupt Vector Word DMA Interrupt Vector Word DMA Channel 0 Control DMA Channel 0 Control DMA Channel 0 Control DMA Channel 0 Source Address DMA Channel 0 Source Address DMA Channel 0 Destination Address DMA Channel 0 Destination Address DMA Channel 0 Transfer Size DMA Channel 1 Control DMA Channel 1 Control DMA Channel 1 Control DMA Channel 1 Source Address DMA Channel 1 Source Address DMA Channel 1 Destination Address SFR_16BIT DMA1DAL SFR_16BIT DMA1SZ SFR_16BIT DMA2CTL SFR_8BIT DMA2CTL_L SFR_8BIT DMA2CTL_H SFR 20BIT DMA2SA SFR 16BIT DMA2SAL SFR 20BIT DMA2DA SFR 16BIT DMA2DAL SFR 16BIT DMA2SZ SFR 16BIT DMA3CTL SFR 8BIT DMA3CTL 1 SFR 8BIT DMA3CTL Hl SFR_20BIT DMA3SA SFR_16BIT DMA3SAL SFR_20BIT DMA3DA SFR_16BIT DMA3DAL SFR_16BIT DMA3SZ SFR_16BIT DMA4CTL SFR_8BIT DMA4CTL_L SFR_8BIT DMA4CTL_H Page 113 DMA Channel 1 Destination Address DMA Channel 1 Transfer Size DMA Cha
126. SLSHR_0 0 0x0200u Compare latch load sourec O immediate define SLSHR_1 1 0x0200u Compare latch load sourec 1 TBR counts to 0 define SLSHR_2 2 0x0200u Compare latch load sourec 2 up down define SLSHR_3 3 0x0200u Compare latch load sourec TBR counts to TBCTLO define CLLD_0 0 0x0200u Compare latch load sourec O immediate define CLLD_1 1 0x0200u Compare latch load sourec 1 TBR counts to 0 define CLLD_2 2 0x0200u Compare latch load sourec 2 up down define CLLD_3 3 0x0200u Compare latch load sourec TBR counts to TBCTLO TBXEXO Control Bits define TBIDEXO 0x0001 0 B7 Input divider expansion Bit O define TBIDEX1 0x0002 0 B7 Input divider expansion Bit 1 define TBIDEX2 0x0004 TimerO B7 Input divider expansion Bit 2 Page 226 define TBIDEX 0 define 1 define TBIDEX 2 define 3 define TBIDEX 4 define TBIDEX 5 define TBIDEX 6 define TBIDEX 7 Hdefine TBIDEX 1 define TBIDEX 2 define TBIDEX 3 define TBIDEX 4 Hdefine TBIDEX 5 define TBIDEX 6 Hdefine TBIDEX 7 define TBIDEX 8 TBOIV Definitions define TBOIV_NONE define TBOIV_TB1CCR1 define TBOIV_TB1CCR2 define TBOIV_3 define TBOIV_4 define TBOIV_5 Page 227 0x0006 0x0008 0x000A 0 0x0001u 1 0x0001u 2 0x0001u 3 0x0001u 4 0x0001u 5 0x0001u 6 0x0
127. T7 0x0080 define 8 0x0100 define BIT9 0x0200 define 0 0400 define BITB 0x0800 define BITC 0x1000 define BITD 0x2000 define BITE 0x4000 define BITF 0x8000 EEE ERE EALERTS ERA LEER LAL ok EEE AE STATUS REGISTER BITS EARS LALA EEE LEER A ELLE EAE RE REE ERA EAE ER define C 0x0001 define Z 0x0002 define N 0x0004 define V 0x0100 Page 73 define GIE define CPUOFF define OSCOFF define SCGO define SCG1 0x0008 0 0010 0 0020 0 0040 0x0080 Low Power Modes coded with Bits 4 7 in SR Hifdef ASM HEADER Begin defines for assembler define LPMO define LPM1 define LPM2 define LPM3 define LPM4 CPUOFF SCGO CPUOFF SCG1 CPUOFF SCG1 SCGO CPUOFF SCG1 SCGO OSCOFF CPUOFF End defines for assembler Helse Begin defines for define LPMO_bits define LPM1_bits define LPM2_bits Hdefine LPM3_bits Hdefine LPM4_bits Hinclude in430 h Page 74 CPUOFF SCGO CPUOFF SCG1 CPUOFF SCG1 SCGO CPUOFF SCG1 SCGO OSCOFF CPUOFF define LPMO _bis_SR_register LPMO_bits Enter Low Power Mode 0 define LPMO EXIT _bic_SR_register_on_exit LPMO_bits Exit Low Power Mode 0 define LPM1 bis SR register LPM1 bits Enter Low Power Mode 1 define LPM1 EXIT bic SR register on exit LPM1 bits Exit Low Power Mode 1 define L
128. TCTIM1_L RTCTIM1_H RTCDATE_L RTCDATE_H RTCYEAR_L RTCYEAR_H RTCPS_L RTCPS_H RTCAMINHR L Real Time Clock Alarm Min RTCAMINHR Real Time Clock Alarm Hour RTCADOWDAY L Real Time Clock Alarm day of week RTCADOWDAY H Real Time Clock Alarm day RTCCTLO1 Control Bits define RTCBCD define RTCHOLD Page 194 0x8000 RTC BCD O Binary 1 BCD 4000 Hold define RESERVED define RTCRDY define RESERVED define RESERVED define RTCTEV1 define RTCTEVO define RTCOFIE define RTCTEVIE define RTCAIE define RTCRDYIE define RTCOFIFG define RTCTEVIFG define RTCAIFG define RTCRDYIFG 0 2000 0 1000 0 0800 0 0400 0 0200 0 0100 0 0080 0 0040 0 0020 0 0010 0x0008 0 0004 0 0002 0 0001 RTCCTLO1 Control Bits define RESERVED define RESERVED define RESERVED define RTCOFIE_L define RTCTEVIE_L define RTCAIE_L define RTCRDYIE_L define RTCOFIFG_L Page 195 0x2000 0x0800 0x0400 0x0080 0 0040 0 0020 0x0010 0x0008 RESERVED RTC Ready RESERVED RESERVED RTC Time Event 1 RTC Time Event 0 RTC 32kHz cyrstal oscillator fault interrupt enable RTC Time Event Interrupt Enable Flag RTC Alarm Interrupt Enable Flag RTC Ready Interrupt Enable Flag RTC 32kHz cyrstal oscillator fault interrupt fl
129. TIMER GS Page 268 define MSP430 HAS WDT Definition to show that Module is available define _MSP430_BASEADDRESS_WDT_A__ 0x0150 SFR_16BIT WDTCTL Watchdog Timer Control SFR_8BIT WDTCTL_L Watchdog Timer Control SFR_8BIT WDTCTL_H Watchdog Timer Control The bit names have been prefixed with WDT WDTCTL Control Bits define WDTISO 0x0001 WDT Timer Interval Select 0 define WDTIS1 0x0002 WDT Timer Interval Select 1 define WDTIS2 0x0004 WDT Timer Interval Select 2 define WDTCNTCL 0x0008 WDT Timer Clear define WDTTMSEL 0x0010 WDT Timer Mode Select define WDTSSELO 0 0020 WDT Timer Clock Source Select O define WDTSSEL1 0x0040 WDT Timer Clock Source Select 1 define WDTHOLD 0x0080 WDT Timer hold WDTCTL Control Bits Hdefine WDTISO L 0x0001 WDT Timer Interval Select 0 Hdefine WDTIS1 L 0x0002 WDT Timer Interval Select 1 define WDTIS2 L 0x0004 WDT Timer Interval Select 2 define WDTCNTCL L 0x0008 WDT Timer Clear define WDTTMSEL L 0x0010 WDT Timer Mode Select define WDTSSELO L 0x0020 WDT Timer Clock Source Select 0 Page 269 define WDTSSEL1 L 0x0040 A WDT Timer Clock Source Select 1 define WDTHOLD 0x0080 WDT Timer hold WDTCTL Control Bits d
130. TLWO_L USCI AO Control Word Register 0 SFR_8BIT UCAOCTLWO_H USCI AO Control Word Register 0 Hdefine UCAOCTL1 UCAOCTLWO L USCI AO Control Register 1 define UCAOCTLO UCAOCTLWO H USCI 0 Control Register 0 SFR 16BIT UCAOBRW USCI A0 Baud Word Rate 0 SFR 8BIT UCAOBRW 1 USCI A0 Baud Word Rate 0 SFR 8BIT UCAOBRW USCI A0 Baud Word Rate 0 define UCAOBRO UCAOBRW USCI AO Baud Rate 0 define UCAOBR1 UCAOBRW H USCI AO Baud Rate 1 SFR 8BIT UCAOMCTL USCI Modulation Control SFR 8BIT UCAOSTAT USCI AO Status Register SFR 8BIT UCAORXBUF USCI 0 Receive Buffer SFR 8BIT UCAOTXBUF USCI 0 Transmit Buffer SFR 8BIT UCAOABCTL USCI AO LIN Control SFR 16BIT UCAOIRCTL USCI 0 IrDA Transmit Control SFR 8BIT UCAOIRCTL 1 USCI IrDA Transmit Control SFR 8BIT UCAOIRCTL USCI 0 IrDA Transmit Control define UCAOIRTCTL UCAOIRCTL USCI AO IrDA Transmit Control define UCAOIRRCTL UCAOIRCTL H USCI AO IrDA Receive Control SFR 16BIT UCAOICTL USCI 0 Interrupt Enable Register SFR 8BIT UCAOICTL L USCI 0 Interrupt Enable Register Page 254 SFR_8BIT UCAOICTL_H USCI AO Interrupt Enable Register define UCAOIE UCAOICTL_L USCI AO Interrupt Enable Register define UCAOIFG UCAOICTL_H USCI AO Interrupt Flags Register SFR_16BIT UCAOIV USCI AO Interrupt Vector Register e
131. TSEL__ RES12 12 0x0100u DMA channel 1 transfer select 12 Reserved RES13 13 0x0100u DMA channel 1 transfer select 13 Reserved RES14 14 0x0100u DMA channel 1 transfer select 14 Reserved RES15 15 0x0100u DMA channel 1 transfer select 15 Reserved USCIAORX 16 0x0100u channel 1 transfer select 16 USCIAO USCIAOTX 17 0x0100u channel 1 transfer select 17 USCIAO USCIBORX 18 0 0100 DMA channel 1 transfer select 18 USCIBO USCIBOTX 19 0x0100u DMA channel 1 transfer select 19 USCIBO USCIA1RX 20 0x0100u channel 1 transfer select 20 USCIA1 USCIA1TX 21 0x0100u channel 1 transfer select 21 USCIA1 USCIB1RX 22 0x0100u DMA channel 1 transfer select 22 USCIB1 05 23 0x0100u DMA channel 1 transfer select 23 USCIB1 ADC12IFG 24 0x0100u channel 1 transfer select 24 RES25 25 0x0100u DMA channel 1 transfer select 25 Reserved define DMA1TSEL__RES26 26 0x0100u DMA channel 1 transfer select 26 Reserved Page 137 Hdefine DMA1TSEL__RES27 27 0x0100u channel 1 transfer select 27 Reserved di Hdefine DMA1TSEL__RES28 28 0x0100u DMA channel 1 transfer select 28 Reserved define DMA1TSEL__MPY 29 0x0100u channel 1 transfer select 29 Multiplier ready define DMA1TSEL DMAOIFG 30 0x0100u channel 1 transfer select 30 previous channel DMA
132. TSSEL__SMCLK 0 0x0020u WDT Timer Clock Source Select SMCLK define WDTSSEL ACLK 1 0x0020u WDT Timer Clock Source Select ACLK define WDTSSEL 2 0x0020u WDT Timer Clock Source Select VLO CLK WDT interval times 1ms coded with Bits 0 2 WDT is clocked by fSMCLK assumed 1MHz define WDT MDLY 32 WDTPW WDTTMSEL WDTCNTCL WDTIS2 32ms interval default define WDT MDLY 8 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTISO Je 8ms define WDT_MDLY_0_5 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTIS1 0 5ms define WDT MDLY 0 064 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTIS1 WDTISO 0 064ms WDT is clocked by fACLK assumed 32KHz define WDT ADLY 1000 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTSSELO 1000ms Hdefine WDT ADLY 250 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTSSELO WDTISO 250ms define WDT_ADLY_16 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTSSELO WDTIS1 16ms define WDT ADLY 1 9 WDTPW WDTTMSEL WDTCNTCL WDTIS2 WDTSSELO WDTIS1 WDTISO 1 9ms Page 271 Watchdog mode gt reset after expired time WDT is clocked by fSMCLK assumed 1MHz define WDT_MRST_32 WDTPW WDTCNTCL WDTIS2 32ms interval default define WDT_MRST_8 WDTPW WDTCNTCL WDTIS2 WDTISO 8ms define WDT_MRST_0_5 WDTPW WDTCNTCL WDTIS2 WDTIS1 0 5ms Ed define WDT MRST 0 064 WDTPW WDTCNTCL WDTIS2 WDTIS1 WDTISO 0 064ms WDT is clocked by fACLK as
133. Time out define SYSRSTIV WDTKEY 0x0018 SYSRSTIV WDTKEY violation Hdefine SYSRSTIV KEYV 0x001A SYSRSTIV Flash Key violation Page 214 define SYSRSTIV_FLLUL 0x001C SYSRSTIV FLL unlock define SYSRSTIV PERF 0x001E SYSRSTIV peripheral config area fetch define SYSRSTIV PMMKEY 0x0020 SYSRSTIV PMMKEY violation RE TimerO A5 EERE EE EE EEE E EROR ke i define 5 430 HAS Definition to show that Module is available define __MSP430_BASEADDRESS_TOA5__ 0x0340 SFR_16BIT TAOCTL TimerO A5 Control SFR 16BIT TAOCCTLO TimerO A5 Capture Compare Control 0 SFR 16BIT TAOCCTL1 TimerO A5 Capture Compare Control 1 SFR 16 2 TimerO 5 Capture Compare Control 2 SFR_16BIT TAOCCTL3 TimerO A5 Capture Compare Control 3 SFR_16BIT TAOCCTL4 Timer0_A5 Capture Compare Control 4 SFR_16BIT TAOR TimerO 5 SFR 16BIT TAOCCRO TimerO A5 Capture Compare O SFR 16BIT TAOCCR1 TimerO A5 Capture Compare 1 SFR 16BIT TAOCCR2 TimerO A5 Capture Compare 2 SFR 16BIT TAOCCR3 TimerO A5 Capture Compare 3 SFR 16 TimerO A5 Capture Compare 4 SFR 16BIT TAOIV TimerO 5 Interrupt Vector Word SFR 16BIT TAOEXO TimerO 5 Expansion Register 0 Page 215 TAxCTL Control Bits def
134. TimerO A TAOCCRO IFG define DMA1TSEL TAOCCR2 2 0x0100u channel 1 transfer select 2 TimerO TAOCCR2 IFG Hdefine DMA1TSEL TA1CCRO 3 0x0100u DMA channel 1 transfer select 3 Timer1_A TA1CCRO IFG define DMA1TSEL TA1CCR2 4 0x0100u DMA channel 1 transfer select 4 Timer1_A TA1CCR2 IFG define DMA1TSEL TA2CCRO 5 0x0100u channel 1 transfer select 5 Timer2 TA2CCRO IFG define DMA1TSEL TA2CCR2 6 0x0100u channel 1 transfer select 6 Timer2 TA2CCR2 IFG define DMA1TSEL__TBOCCRO 7 0x0100u DMA channel 1 transfer select 7 TimerBO TBOCCRO IFG define DMA1TSEL TBOCCR2 8 0x0100u DMA channel 1 transfer select 8 TimerBO TBOCCR2 IFG define DMA1TSEL__RES9 9 0x0100u DMA channel 1 transfer select 9 Reserved define DMA1TSEL RES10 10 0x0100u DMA channel 1 transfer select 10 Reserved define DMA1TSEL RES11 11 0x0100u DMA channel 1 transfer select 11 Reserved ii Page 136 define DMA1TSEL__ di define DMA1TSEL__ define DMA1TSEL__ define DMA1TSEL__ define DMA1TSEL__ receive define DMA1TSEL__ transmit define DMA1TSEL__ receive define DMA1TSEL__ transmit define DMA1TSEL__ receive define DMA1TSEL__ transmit define DMA1TSEL__ receive define DMA1TSEL__ transmit define DMATTSEL ADC12IFGx define DMA1
135. USCIB1TX 23 0x0001u channel 4 transfer select 23 USCIB1 transmit define DMA4TSEL__ADC12IFG 24 0x0001u DMA channel 4 transfer select 24 ADC121FGx define DMA4TSEL__RES25 25 0x0001u DMA channel 4 transfer select 25 Reserved define DMA4TSEL__RES26 26 0x0001u DMA channel 4 transfer select 26 Reserved define DMAATSEL USB FNRXD 27 0 0001 DMA channel 4 transfer select 27 USB FNRXD define DMA4TSEL__USB_READY 28 0x0001u DMA channel 4 transfer select 28 USB ready define DMA4TSEL__MPY 29 0x0001u DMA channel 4 transfer select 29 Multiplier ready define DMA4TSEL__DMA3IFG 30 0 0001 channel 4 transfer select 30 previous DMA channel DMA3IFG define DMA4TSEL__DMAEO 31 0x0001u DMA channel 4 transfer select 31 ext Trigger DMAEO Page 144 define DMASTSEL REQ 0 0x0100u DMA channel 5 transfer select 0 REQ sw define DMASTSEL__TAOCCRO TAOCCRO IFG define DMASTSEL__TAOCCR2 TAOCCR2 IFG define DMASTSEL__TA1CCRO TA1CCRO IFG define DMASTSEL__TA1CCR2 TA1CCR2 IFG define DMASTSEL__TA2CCRO TA2CCRO IFG define DMASTSEL__TA2CCR2 TA2CCR2 IFG define DMASTSEL TBOCCRO TBOCCRO IFG define DMASTSEL 2 TBOCCR2 IFG define DMASTSEL RES9 define DMASTSEL__RES10 define DMASTSEL__RES11 define DMASTSEL__RES12
136. _16BIT TA1CCTL2 Timer1_A3 Capture Compare Control 2 SFR_16BIT TA1R Timer1_A3 SFR_16BIT TA1CCRO Timer1_A3 Capture Compare 0 SFR_16BIT TA1CCR1 Timer1_A3 Capture Compare 1 SFR_16BIT TA1CCR2 Timer1_A3 Capture Compare 2 SFR_16BIT TA1IV Timer1_A3 Interrupt Vector Word SFR 16BIT TA1EXO Timer1 A3 Expansion Register O Bits are already defined within the TimerO Ax TA1IV Definitions define TALIV NONE 0x0000 No Interrupt pending define TA1IV TA1CCR1 0x0002 TA1CCR1 CCIFG define TA1IV TA1CCR2 0x0004 TA1CCR2 CCIFG Hdefine TA1IV 3 0x0006 Reserved Page 220 define TA1IV 4 define 5 define 6 define TA1IV_TA1IFG Reserved Reserved Reserved 0 000 TALIFG RERE EEE EE Timer2 A3 TE E EE Hdefine _MSP430_HAS T2A3__ Definition to show that Module is available define MSP430_BASEADDRESS_T2A3__ 0x0400 SFR_16BIT TA2CTL SFR_16BIT TA2CCTLO SFR_16BIT TA2CCTL1 SFR_16BIT TA2CCTL2 SFR_16BIT TA2R SFR_16BIT TA2CCRO SFR_16BIT TA2CCR1 SFR_16BIT TA2CCR2 SFR 16BIT TA2IV SFR 16BIT TA2EXO Timer2 A3 Control Timer2 A3 Capture Compare Control 0 Timer2 A3 Capture Compare Control 1 Timer2 A3 Capture Compare Control 2 Timer2 A3 Timer2 A3 Capture Compare 0 Time
137. __ 0x0480 SFR_16BIT BAKMEMO Battery Backup Memory 0 SFR 8 1 Battery Backup Memory 0 SFR 8BIT BAKMEMO Battery Backup Memory 0 SFR 16BIT BAKMEM1 Battery Backup Memory 0 SFR 8BIT BAKMEMA1 1 Battery Backup Memory 0 SFR 8 1 Battery Backup Memory 0 SFR 16BIT BAKMEM2 Battery Backup Memory 0 SFR 8 2 L Battery Backup Memory 0 SFR 8 2 Battery Backup Memory 0 SFR 16BIT BAKMEM3 Battery Backup Memory 0 SFR 8BIT BAKMEM3 1 Battery Backup Memory 0 SFR 8BIT BAKMEM3 Battery Backup Memory 0 RES EARLE ERS Battery Charger Module ORE EEE BRIO EEE RR E RR define MSP430 HAS BATTERY CHARGER Definition to show that Module is available Page 93 define __MSP430_BASEADDRESS_BATTERY_CHARGER__ 0x049C SFR_16BIT BAKCTL Battery Backup Control SFR_8BIT BAKCTL_L Battery Backup Control SFR_8BIT BAKCTL_H Battery Backup Control SFR_16BIT BAKCHCTL Battery Charger Control SFR_8BIT BAKCHCTL_L Battery Charger Control SFR_8BIT BAKCHCTL_H Battery Charger Control BAKCTL Control Bits define LOCKBAK 0x0001 Lock backup sub system define BAKSW 0x0002 Manual switch to battery backup supply define BAKADC 0x0004 Battery backup supply to ADC
138. able SFR_16BIT PDDS Port Resistor Drive Strenght SFR_8BIT PDDS_L Port Resistor Drive Strenght SFR 8BIT PDDS H Port D Resistor Drive Strenght SFR 16BIT PDSEL Port D Selection SFR 8BIT PDSEL L Port D Selection SFR 8BIT PDSEL H Port D Selection define P7IN 1 Port 7 Input define P7OUT PDOUT L Port 7 Output define P7DIR PDDIR L Port 7 Direction define P7REN PDREN 1 Port 7 Resistor Enable define P7DS PDDS_L Port 7 Resistor Drive Strenght define P7SEL PDSEL L Port 7 Selection Page 166 define P8IN Hdefine PBOUT define P8DIR define P8REN define P8DS define P8SEL PDIN Port 8 Input PDOUT Port 8 Output PDDIR Port 8 Direction PDREN Port 8 Resistor Enable PDDS Port 8 Resistor Drive Strenght PDSEL Port 8 Selection EE ee RE DIGITAL I O Port9 Pull up Pull down Resistors ERE ROOT RE E K KE E KRE RE ERRE e OE RE E RE define MSP430 HAS PORT9 R Definition to show that Module is available define 5 430 BASEADDRESS PORT9 0x0280 define MSP430 HAS PORTER Definition to show that Module is available define MSP430 BASEADDRESS PORTE 0 0280 SFR 16BIT PEIN SFR 8 1 SFR 8BIT PEIN SFR 16BIT PEOUT SFR 8BIT PEOUT 1 SFR 8BIT PEOUT H S
139. ag RTC Time Event Interrupt Flag RTC Alarm Interrupt Flag RTC Ready Interrupt Flag RESERVED RESERVED RESERVED RTC 32kHz cyrstal oscillator fault interrupt enable RTC Time Event Interrupt Enable Flag RTC Alarm Interrupt Enable Flag RTC Ready Interrupt Enable Flag RTC 32kHz cyrstal oscillator fault interrupt flag define RTCTEVIFG L 0x0004 RTC Time Event Interrupt Flag define RTCAIFG_L 0x0002 Alarm Interrupt Flag define RTCRDYIFG_L 0x0001 RTC Ready Interrupt Flag RTCCTLO1 Control Bits define RTCBCD_H 0x0080 RTC BCD O Binary 1 BCD define RTCHOLD H 0x0040 RTC Hold define RESERVED 0x2000 RESERVED define RTCRDY_H 0x0010 RTC Ready define RESERVED 0x0800 RESERVED define RESERVED 0x0400 RESERVED define RTCTEV1_H 0x0002 RTC Time Event 1 define RTCTEVO_H 0x0001 RTC Time Event 0 define 0 0x0000 RTC Time Event 0 Min changed define RTCTEV_1 0x0100 Event 1 Hour changed define RTCTEV_2 0 0200 Event 2 12 00 changed define RTCTEV_3 0x0300 Event 00 00 changed define 0x0000 Event O Min changed define RTCTEV__HOUR 0x0100 RTC Time Event 1 Hour changed define 0000 0x0200
140. alculated zero position of accelerometer along y axis int z_base 0 calculated zero position of accelerometer along z axis int uncalibrated UNCALIBRATED variable indicating whether a calibration has occurred Page 42 adc init sets up the registers needed for analog to digital conversions to take place The function takes no inputs and has no outputs void adc_init void ADC12CTLO ADC12SHTO2 ADC120N ADC12MSC set a sample and hold time of 16 cycles turn on analog to digital conversion and set rising edges to trigger sampling ADC12CTL1 ADC12SHP ADC_SEQ use sampling timer for sequence of reads ADC12CTL2 EIGHT BIT STAND use 8 bit mode with standard settings ADC12IE ADC_BITS enable electrode and accelerometer interrupts ADC12MCTLO ELEC_0 set first ADC memory register to adc port 0 ADC12MCTL1 ELEC_1 set second ADC memory register to adc port 1 ADC12MCTL2 ELEC_2 set third ADC memory register to adc port 2 ADC12MCTL3 ELEC_3 set fourth ADC memory register to adc port 3 ADC12MCTL4 X_AXIS set fifth ADC memory register to adc port 5 ADC12MCTL5 Y_AXIS set sixth memory register to adc port 7 ADC12MCTL6 Z_AXIS indicate seventh ADC memory register is last of sequence and set it to read from adc port 15 ADC12CTLO ADC12ENC enable ADC P6SEL PORT 6 ADC set port 6 entirely to ADC mode P7SEL
141. all_diameter 15 allow random numbers to be generated random seed The class Ball describes a red ball object class Ball def init self global max speed red balls always spawn at the top left of the board self x 0 self y 0 Page 61 initial velocity is random and set speed self yv 2 random random 5 max speed self xv 2 random random 5 max_speed The class PointBall describes a green ball object class PointBall def init self global point speed global x max global y max 4 green balls can spawn anywhere self x random random x max self y random random y max green balls have random initial velocity self yv 2 random random 5 point speed self xv 2 random random 5 point speed 4 The move function updates the position of every red ball currently on the playing environment def move global balls global pointballs global x pos global y pos Page 62 global x max global x min global y max global y min global ball rad global score iterate through each red ball for ball in balls if a red ball reaches one of the boundaries reverse its partial velocity based on which boundary was reached if ball x x max or ball x x min ball xv ball xv if ball y y max or ball y y min ball yv ball yv Then increment the balls position by the balls velocity ball x ball x ball xv ball y ball y
142. ame wireless network as the wifi module on the board or the computer must be connected to the adhoc network generated by the wifi module depending on the whether the jumper component 11 is in place or not Once loaded Ball Blasters Infinity is quite simple to play The game will start with a blue ball in the center of the playing environment This is the user s ball and can be controlled by tilting the Page 5 accelerometer glove Every few seconds red and green ball will simultaneously enter the playing environment The goal of Ball Blasters Infinity is for the user ball to collide with as many green balls as possible before colliding with a red ball Each collision with a green ball will increment the score count in the top left of the play environment When the user s blue ball collides with a red ball all red and green balls on the field disappear and the score resets It should be noted that the user cannot move the blue ball beyond the bounds of the playing environment and that red and green balls will bounce off of the boundaries If the user initiates a recalibration sequence while playing Ball Blasters Infinity the game will pause until the calibration finishes Also if the wifi connection is temporarily interrupted the game will pause until data is being properly transferred again Page 6 Overview of System Hardware The basic interaction of hardware in the BioSleeve system is outlined in the following block diagra
143. ary no update occurs def update_ball x global x_pos global y_pos global x_max global x_min global y_max global y_min increment x position X_pos x if at a boundary dont allow x position to increate ifx pos x max Page 65 X max elif x pos x min x pos x min 4 do the same for y position _ y if y_pos gt y_max y_pos y_max elif y_pos lt y_min y pos y min replace the old blue ball with the new one to cause movement effect canvas delete blueball canvas create_oval x_pos y_pos x_pos ball_diameter y_pos ball_diameter fill blue tag blueball update the graphics canvas update return prepare tkinter from tkinter import create play environment window Page 66 canvas Canvas window width 400 height 300 bg white canvas pack display score at the top left of environment scorel score score2 str score score3 5 1 score2 window title score3 create the blue player ball canvas create_oval x_pos y_pos x_pos ball_diameter y_pos ball_diameter fill blue tag blueball establish socket connection to BioSleeve board host 169 254 1 1 port 2000 s socket socket socket AF_INET socket SOCK STREAM s connect host port enter main loop of game while True wait for a string to received over wifi data s recv 1024 Page 67 clear the canvas of all obj
144. ata in reverse byte Register SFR_8BIT CRCDIRB_H CRC data in reverse byte Register SFR_16BIT CRCINIRES CRC Initialisation Register and Result Register SFR_8BIT CRCINIRES_L CRC Initialisation Register and Result Register SFR_8BIT CRCINIRES_H CRC Initialisation Register and Result Register SFR_16BIT CRCRESR CRC reverse result Register SFR_8BIT CRCRESR_L CRC reverse result Register SFR_8BIT CRCRESR_H CRC reverse result Register VE dd TE EA RE DMA_X SERE KE RE ERRE KEE KE TE EEEE e e RATE E E E RR ERRE define MSP430 HAS DMAX 6 _ Definition to show that Module is available define 5 430 BASEADDRESS DMAX 6 0x0500 SFR 16BIT DMACTLO Module Control 0 SFR 8BIT DMACTLO 1 Module Control 0 SFR 8BIT DMACTLO Module Control 0 SFR 16BIT DMACTL1 DMA Module Control 1 SFR 8BIT DMACTL1 1 DMA Module Control 1 SFR 8BIT DMACTL1 DMA Module Control 1 SFR 16BIT DMACTL2 DMA Module Control 2 SFR 8BIT DMACTL2 1 DMA Module Control 2 SFR 8BIT DMACTL2 Hl DMA Module Control 2 SFR 16BIT DMACTL3 DMA Module Control 3 Page 111 SFR_8BIT DMACTL3_L SFR_8BIT DMACTL3_H SFR_16BIT DMACTL4 SFR_8BIT DMACTL4_L SFR_8BIT DMACTL4_H SFR_16BIT DMAIV SFR_8BIT DMAIV_L SFR_8BIT DMAIV_H SFR_16BIT DMAOCTL SFR_8BIT DMAOCTL_L SFR_8BIT DMAOCTL_H SFR_20BIT DMAOSA SFR_16BIT DMAOSAL
145. ation void display_wait void int i variable used for iteration for i 0 i lt WAIT TIME i continue do nothing return clear_display quite simply clears the display be setting the output of display pins to low Page 30 void clear_display void P9OUT P9 NO PINS set output of port 9 pins to low amp P4_NO_PINS set output of port 4 pins to low return Page 31 wifi h Created on Jun 6 2012 Author Josh Fromm This file contains the constants needed to establish a UART connection to the wifi module and transmit characters via wifi ifndef WIFI_H_ define WIFI_H_ Initialize the UART module on CPU void UART_init void Transmit the passed string to the wifi module for transmission void wifi_transmit_char const char DEFINE UART_PORTS 0x30 value to set UART ports to UART mode DEFINE BAUD_RATE divisor giving a baud rate of 9600 from a clock source of 2 15 MHz HDEFINE UART_SMCLK OxCO sets UART to use SMCLK DEFINE UART MOD SEL 0x44 sets a modulation pattern and leaves oversampling Page 32 turned off DEFINE UART STAT INIT Ox0 sets initial status variables DEFINE UART REC INT 0 1 enables receive interrupts on UART UART START 0 0 starts UART data transfers DEFINE UART BUSY 0 1 bit indicating if UART is busy or fr
146. ation the z axis is not updated void update_position void const char left left const char right right const char forward forward const char backward backward const char nothing check if the x axis is shifted forward enough to send a character if x_val lt x_base THRESHOLD amp x_val gt MIN_THRESHOLD wifi_transmit_char forward if so send a string then check if the x axis is shifted backwards else if x_val gt x_base THRESHOLD amp x_val lt MAX_THRESHOLD wifi_transmit_char backward check if the y axis is shifted left if ly val lt y base THRESHOLD amp val gt MIN THRESHOLD wifi_transmit_char left Page 47 check if axis is shifted right else if y_val gt y_base THRESHOLD amp y_val lt MAX_THRESHOLD wifi_transmit_char right if the accelerometer is not shifted send a blank packet to keep the the game running else wifi_transmit_char nothing return adc_handler is triggered each time a sequence of adc reads finshes The function reads the value of one of the electrode pins and converts the read value to a magnitude that is displayed on the system s LED display The function also checks the read values of each of the axes read from the accelerometer and stores the read value in a shared variable that can be accessed by the update
147. ation word define DMASWDB 2 0x0040u transfer source word to destination byte define DMASBDB 3 0x0040u transfer source byte to destination byte define DMASRCINCR_0 0 0x0100u DMA source increment 0 source address unchanged define DMASRCINCR_1 1 0x0100u DMA source increment 1 source address unchanged define DMASRCINCR_2 2 0x0100u DMA source increment 2 source address decremented define DMASRCINCR_3 3 0x0100u DMA source increment 3 source address incremented define DMADSTINCR_0 0 0x0400u DMA destination increment 0 destination address unchanged define DMADSTINCR_1 1 0x0400u destination increment 1 destination address unchanged define DMADSTINCR_2 2 0x0400u DMA destination increment 2 destination address decremented define DMADSTINCR_3 3 0x0400u DMA destination increment 3 destination address incremented define DMADT_0 0 0x1000u DMA transfer mode 0 Single transfer define DMADT_1 1 0x1000u transfer mode 1 Block transfer define DMADT_2 2 0x1000u transfer mode 2 Burst Block transfer define DMADT_3 3 0x1000u transfer mode 3 Burst Block transfer define DMADT_4 4 0x1000u transfer mode 4 Repeated Single transfer Page 120 define DMADT 5 define DMADT 6 transfer define DMADT_7 transfer DMAIV Definitions define DM
148. ber of electrodes before resetting The handler also stores the accelerometer values read a shared variable that is used by the update position function to determine if the accelerometer is sufficiently shifted to warrant the transmission of a command string Page 16 wifi c wifi c contains the code used to initialize and run the UART controller of the system The code is used to establish the appropriate baud rate to interact with the wifi module and also contains the code needed to send strings via wifi The code also includes UART receive interrupts The interrupt handler stores the received character in a buffer that is not used in the current system implementation 12 2 contains the code needed to initialize 2 controller of the system send data to any of the registers of the system s IMU and read data from any of the registers of the system s IMU This code is not used the system s current implementation BallBlasters py BallBlasters py controls the flow of wireless data on the client computer and controls the game environment of Ball Blasters Infinity When BallBlasters py is run it first connects to the wifi module on the BloSleeve system note that it can only do this if the host computer is either connected to the adhoc network generated by the wifi module or on the same wireless network as the wifi module The program then creates graphical environment that is used to p
149. ce On 0x0002 REF Reference output Buffer On 0x0004 Reserved 0x0008 REF Temp Sensor off 0x0010 REF Reference Voltage Level Select Bit 0 define REFVSEL1_L define RESERVED define REFMSTR_L define RESERVED define RESERVED define RESERVED define RESERVED REFCTLO Control Bits define RESERVED define RESERVED define REFGENACT_H define REFBGACT_H define REFGENBUSY_H define BGMODE H define RESERVED define RESERVED define RESERVED define RESERVED define REFVSEL_0 define REFVSEL_1 define REFVSEL_2 define REFVSEL_3 Page 191 0x0020 REF Reference Voltage Level Select Bit 1 0x0040 Reserved 0x0080 REF Master Control 0x1000 Reserved 0x2000 Reserved 0x4000 Reserved 0x8000 Reserved 0x0004 Reserved 0x0040 Reserved 0x0001 REF Reference generator active 0x0002 REF Reference bandgap active 0x0004 REF Reference generator busy 0x0008 REF Bandgap mode 0x1000 Reserved 0x2000 Reserved 0x4000 Reserved 0x8000 Reserved 0x0000 REF Reference Voltage Level Select 1 5V 0x0010 REF Reference Voltage Level Select 2 0V 0x0020 REF Reference Voltage Level Select 2 5V 0x0030 REF Reference Voltage Level Select 2 5V EEE EEKE EEEE EE Real Time Clock E E
150. ct 20 USCIA1 receive define DMASTSEL USCIATTX 21 0x0100u DMA channel 5 transfer select 21 USCIA1 transmit define DMASTSEL__USCIB1RX 22 0x0100u DMA channel 5 transfer select 22 USCIB1 receive define DMASTSEL USCIB1TX 23 0x0100u DMA channel 5 transfer select 23 USCIB1 transmit define DMAS5TSEL__ADC12IFG 24 0x0100u DMA channel 5 transfer select 24 ADC121FGx define DMASTSEL RES25 25 0x0100u channel 5 transfer select 25 Reserved define DMASTSEL RES26 26 0x0100u channel 5 transfer select 26 Reserved Hdefine DMASTSEL 527 27 0x0100u DMA channel 5 transfer select 27 Reserved define DMASTSEL__RES28 28 0x0100u channel 5 transfer select 28 Reserved define DMASTSEL__MPY 29 0x0100u DMA channel 5 transfer select 29 Multiplier ready Page 146 define DMASTSEL DMAA4IFG 30 0 0100 DMA channel 5 transfer select 30 previous channel DMA4IFG define DMASTSEL DMAEO 31 0x0100u DMA channel 5 transfer select 31 ext Trigger DMAEO EE E EE Flash Memory E E EE define MSP430 HAS FLASH Definition to show that Module is available define MSP430 BASEADDRESS FLASH 0x0140 SFR 16BIT FCTL1 FLASH Control 1 SFR 8BIT FCTL1 1 FLASH Control 1 SFR 8BIT FCTL1 FLASH Control 1 sfrow FCTL2 0x0142 FLASH Control 2 SFR 16BIT FCTL3 FLASH Control
151. ct Reference 6 define ADC12SREF_7 7 0x10u ADC12 Select Reference 7 define ADC12IEO 0x0001 ADC12 MemoryO Interrupt Enable ttdefine ADC12IE1 0x0002 ADC12 Memory1 Interrupt Enable define ADC121E2 0x0004 ADC12 Memory2 Interrupt Enable define ADC121E3 0x0008 ADC12 Memory 3 Interrupt Enable define ADC121E4 0x0010 ADC12 Memory 4 Interrupt Enable define ADC12IE5 0x0020 ADC12 Memory 5 Interrupt Enable define ADC12IE6 0x0040 12 Memory Interrupt Enable define ADC121E7 0x0080 ADC12 Memory 7 Interrupt Enable define ADC12IE8 0x0100 ADC12 Memory 8 Interrupt Enable define ADC12IE9 0 0200 ADC12 Memory9 Interrupt Enable define ADC121E10 0x0400 ADC12 Memory 10 Interrupt Enable define ADC121E11 0x0800 ADC12 Memory 11 Interrupt Enable define ADC121E12 0 1000 ADC12 Memory 12 Interrupt Enable ttdefine ADC121E13 0x2000 ADC12 Memory 13 Interrupt Enable define ADC12IE14 0 4000 ADC12 Memory 14 Interrupt Enable define ADC121E15 0 8000 ADC12 Memory 15 Interrupt Enable define ADC12IEO L 0x0001 ADC12 MemoryO Interrupt Enable define ADC12IE1 L 0x0002 ADC12 Memory1 Interrupt Enable Page 89 define ADC12IE2 L define ADC12IE3 L define ADC12IE4 L define ADC12IE5 L define ADC12IE6 L define ADC121E7 L define ADC121E8 H define ADC121E9 H define ADC121E10 H define AD
152. define DMADSTINCRO 0x0400 DMA destination increment bit O define DMADSTINCR1 0x0800 DMA destination increment bit 1 define DMADTO 0x1000 transfer mode bit 0 Page 118 define DMADT1 0x2000 DMA transfer mode bit 1 define DMADT2 0 4000 DMA transfer mode bit 2 DMAXCTL Control Bits define DMAREQ_L 0x0001 Initiate DMA transfer with DMATSEL define DMAABORT_L 0x0002 DMA transfer aborted by NMI define DMAIE_L 0x0004 A DMA interrupt enable ttdefine DMAIFG L 0x0008 DMA interrupt flag define DMAEN L 0x0010 DMA enable ttdefine DMALEVEL L 0x0020 DMA level sensitive trigger select ttdefine DMASRCBYTE L 0x0040 source byte ttdefine DMADSTBYTE L 0x0080 DMA destination byte DMAXCTL Control Bits define DMASRCINCRO H 0x0001 DMA source increment bit 0 define DMASRCINCR1 H 0x0002 DMA source increment bit 1 Hdefine DMADSTINCRO H 0x0004 destination increment bit 0 Hdefine DMADSTINCR1 H 0 0008 DMA destination increment bit 1 define DMADTO H 0x0010 transfer mode bit 0 define DMADT1 H 0x0020 transfer mode bit 1 define DMADT2 H 0x0040 transfer mode bit 2 Hdefine DMASWDW 0 0x0040u DMA transfer source word to destination word Page 119 define DMASBDW 1 0x0040u transfer source byte to destin
153. define P5DS PCDS 1 Port 5 Resistor Drive Strenght define PSSEL PCSEL L Port 5 Selection define PCIN H Port 6 Input define PCOUT Port 6 Output define P6DIR PCDIR_H Port 6 Direction define PGREN PCREN H Port 6 Resistor Enable define 605 PCDS 6 Resistor Drive Strenght define P6SEL PCSEL H Port 6 Selection JERE EEEE EE EEE KE E RR e RE RE EE RE EEC ERRE ER ERRE DIGITAL I O Port7 8 Pull up Pull down Resistors EAST EE E TOR E EEE ERRE RE EE EE define MSP430 HAS PORT7 R Definition to show that Module is available define MSP430 BASEADDRESS PORT 0 0260 define MSP430 HAS PORTS Definition to show that Module is available tidefine MSP430 BASEADDRESS PORT8 0x0260 define MSP430 HAS PORTD Definition to show that Module is available define MSP430 BASEADDRESS PORTD R 0 0260 SFR 16BIT PDIN Port D Input SFR 8BIT PDIN 1 Port D Input SFR 8BIT PDIN Port D Input Page 165 SFR_16BIT PDOUT Port D Output SFR_8BIT PDOUT_L Port D Output SFR_8BIT PDOUT_H Port D Output SFR_16BIT PDDIR Port D Direction SFR_8BIT PDDIR_L Port D Direction SFR_8BIT PDDIR_H Port D Direction SFR_16BIT PDREN Port D Resistor Enable SFR_8BIT PDREN_L Port D Resistor Enable SFR_8BIT PDREN_H Port D Resistor En
154. define RESERVED define DIVAO define DIVA1 define DIVA2 define RESERVED define DIVPAO define DIVPA1 define DIVPA2 define RESERVED 0 0001 Divider Bit 0 0x0002 MCLK Divider Bit 1 0x0004 MCLK Divider Bit 2 0x0008 RESERVED 0x0010 5 Divider Bit O 0x0020 SMCLK Divider Bit 1 0x0040 SMCLK Divider Bit 2 0x0080 RESERVED 0x0100 ACLK Divider Bit 0 0x0200 ACLK Divider Bit 1 0x0400 ACLK Divider Bit 2 0x0800 RESERVED 0x1000 ACLK from Pin Divider Bit O 0x2000 ACLK from Pin Divider Bit 1 0x4000 ACLK from Pin Divider Bit 2 0x8000 RESERVED UCSCTL5 Control Bits define DIVMO 1 define DIVM1 1 define DIVM2 1 define RESERVED Page 243 0x0001 MCLK Divider Bit O 0x0002 Divider Bit 1 0x0004 MCLK Divider Bit 2 0x0008 RESERVED define DIVSO_L define DIVS1_L define DIVS2_L define RESERVED define RESERVED define RESERVED 0 0010 0 0020 0 0040 0 0080 0 0800 0 8000 UCSCTL5 Control Bits define RESERVED define RESERVED define DIVAO_H define DIVA1_H define DIVA2_H define RESERVED define DIVPAO_H define DIVPA1_H define DIVPA2_H define RESERVED define DIVM_0 define DIVM_1 define DIVM_2 define DIVM_3 define DIV
155. e USCI BO SERRE CEE RE RE EEE CEE e EE E e e e ERRE define MSP430 HAS USCI Definition to show that Module is available define MSP430 BASEADDRESS USCI BO SFR 16BIT UCBOCTLWO USCI BO Control Word Register 0 SFR 8BIT UCBOCTLWO 1 USCI BO Control Word Register 0 SFR 8BIT UCBOCTLWO USCI BO Control Word Register 0 Hdefine UCBOCTL1 UCBOCTLWO USCI BO Control Register 1 Hdefine UCBOCTLO UCBOCTLWO H USCI BO Control Register 0 SFR 16BIT UCBOBRW USCI BO Baud Word Rate 0 SFR 8BIT UCBOBRW 1 USCI BO Baud Word Rate 0 SFR 8BIT UCBOBRW USCI BO Baud Word Rate 0 define UCBOBRO UCBOBRW USCI BO Baud Rate 0 define UCBOBR1 UCBOBRW H USCI BO Baud Rate 1 SFR 8BIT UCBOSTAT USCI BO Status Register Page 255 SFR_8BIT UCBORXBUF USCI BO Receive Buffer SFR_8BIT UCBOTXBUF USCI BO Transmit Buffer SFR 16BIT UCBOIZCOA USCI 126 Own Address SFR 8BIT UCBOI2COA 1 USCI BO I2C Own Address SFR 8BIT UCBOI2COA USCI BO 12 Own Address SFR 16BIT UCBOI2CSA USCI 2 Slave Address SFR 8BIT UCBOIZCSA 1 USCI 2 Slave Address SFR 8BIT UCBOI2CSA USCI BO 2 Slave Address SFR_16BIT UCBOICTL USCI BO Interrupt Enable Register SFR_8BIT UCBOICTL_L USCI BO Interrupt Enable Register SFR_8BIT UCBOICTL_H USCI BO Interrupt Enable Register
156. e UCAOBR1 0x0 upper baud rate not needed since MCLK relatively low UCAOMCTL UART MOD SEL pick bit modulation and turn off oversampling UCAOSTAT UART_STAT_INIT initialize status register UCAOIE UART_REC_INT enable receive interrupts on UART UCAOCTLO UART_START Begin running the UART module return The wifi_transmit_char function takes a string as input and sends that Page 35 string to the wifi module via UART The function does this by iterating through all the characters in the string checking each to see if it is a NULL character and then sending that character through UART When a NULL character is found the function returns void wifi_transmit_char const char transfer unsigned int i variable needed for iteration for i 0 transfer i NULL i iterate through all characters passed string as long as USCI is busy hold loop while UCAOSTAT amp UART_BUSY UCAOTXBUF transfer i transfer next character return the interrupt handler for UART interrupts triggered only by receive events simply reads the receive buffer of the UART and stores it in the buffer called in_buffer before returning pragma vector USCI_AO_VECTOR Set UART int vector to be this handler __interrupt void UART_handler void Page 36 in buffer UCAORXBUF read receive buffer return Page 37 adc
157. e DCOO_H 0x0001 DCO TAP Bit O define DCO1_H 0x0002 DCO TAP Bit 1 define 2 0x0004 A DCO TAP Bit 2 define DCO3 H 0x0008 DCO TAP Bit 3 define DCO4 H 0x0010 DCO TAP Bit 4 define RESERVED 0x2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED 0x8000 RESERVED UCSCTL1 Control Bits define DISMOD 0x0001 Disable Modulation define RESERVED 0x0002 RESERVED define RESERVED 0x0004 RESERVED define RESERVED 0x0008 RESERVED ttdefine DCORSELO 0x0010 DCO Freq Range Select Bit O ttdefine DCORSEL1 0x0020 DCO Freq Range Select Bit 1 ttdefine DCORSEL2 0x0040 DCO Freq Range Select Bit 2 define RESERVED 0x0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED Page 231 define RESERVED 0 2000 define RESERVED 0 4000 define RESERVED 0 8000 UCSCTL1 Control Bits define DISMOD_L 0x0001 define RESERVED 0x0002 define RESERVED 0x0004 define RESERVED 0x0008 define DCORSELO_L 0x0010 Hdefine DCORSEL1_L 0x0020 Hdefine DCORSEL2_L 0x0040 define RESERVED 0x0080 define RESERVED 0x0100 define RESERVED 0x0200 define RESERVED
158. e RESERVED 0x0080 RESERVED Hdefine SELAO 0x0100 ACLK Source Select Bit O define SELA1 0x0200 ACLK Source Select Bit 1 define SELA2 0x0400 ACLK Source Select Bit 2 define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0x2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED 0x8000 RESERVED Page 239 UCSCTL4 Control Bits define SELMO_L define SELM1_L define SELM2_L define RESERVED define SELSO_L define SELS1_L define SELS2_L define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0 0080 0 0800 0 1000 0 2000 0 4000 0 8000 UCSCTL4 Control Bits define RESERVED define RESERVED define 5 define SELA1_H define SELA2_H define RESERVED define RESERVED Page 240 0 0008 0 0080 0 0001 0 0002 0 0004 0 0800 0 1000 MCLK Source Select 0 MCLK Source Select Bit 1 MCLK Source Select 2 RESERVED SMCLK Source Select Bit SMCLK Source Select Bit 1 SMCLK Source Select Bit 2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ACLK So
159. e RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define XT2BYPASS_H 0x0010 2 bypass mode 0 internal 1 sourced from external pin define RESERVED 0 2000 RESERVED Page 248 define XT2DRIVEO_H 0x0040 2 Drive Level mode Bit 0 define XT2DRIVE1_H 0x0080 2 Drive Level mode Bit 1 define XCAP_0 0x0000 XIN XOUT define XCAP_1 0x0004 XIN XOUT Cap 1 define XCAP_2 0x0008 Cap 2 define XCAP_3 XIN XOUT Cap 3 define XT1DRIVE_0 0x0000 Drive Level mode 0 define XT1DRIVE 1 0x0040 Drive Level mode 1 define XT1DRIVE 2 0x0080 Drive Level mode 2 define XT1DRIVE 3 Drive Level mode 3 Hdefine XT2DRIVE 0 0x0000 XT2 Drive Level mode 0 Hdefine XT2DRIVE 1 0x4000 XT2 Drive Level mode 1 define XT2DRIVE 2 0x8000 XT2 Drive Level mode 2 define XT2DRIVE 3 0xCOO0 XT2 Drive Level mode 3 UCSCTL7 Control Bits define DCOFFG 0x0001 DCO Fault Flag define XT1LFOFFG 0x0002 XT1 Low Frequency Oscillator Fault Flag define XT1HFOFFG 0 0004 High Frequency Oscillator 1 Fault Flag define XT2OFFG 0x0008 High Frequency Oscillator 2 Fault Flag define RESERVED 0x0010 RESERVED define RESERVED 0x0020 RESERVED define RESERVED 0x0040 RESERVE
160. e pin is also connected to a large resistor to ground When the switch is pressed the connection to VCC is lost and the voltage of the reset chip drops enough to trigger the reset signal which is connected to the nRST pin on the CPU Releasing the switch returns voltage to the reset chips pin and causes the reset signal to go inactive Power The system uses a barrel jack USB3 0 jack LP 063450 lithium ion rechargeable battery MAX1555 battery management chip and a MAX1927R switching regulator to establish a system voltage of 3 3 Volts The power from either or both of the two power jacks is fed into MAX1555 which monitors the voltage of the rechargeable battery and sets the voltage on the BAT pin to maximize the batteries charging The BAT pin is directly connected to both the positive terminal of the battery and the input of the MAX1927R switching regulator This allows the switching regulator to get power from either the MAX1555 when a power jack is plugged in or the battery when no jack is plugged in The switching regulator converts the input voltage to an output voltage of 3 3 Volts which is supplied to the rest of the system The MAX1927R can source a total of 800mA the system uses around 600 mA at maximum capacity Page 11 Display The system uses a 10 segment LED bar graph as a way to convey information to the user The display is connected to the board through a 470 Ohm resistor network that is connected to a 14 pin dip socket
161. ect 18 USCIBO receive define DMAOTSEL__USCIBOTX 19 0x0001u channel O transfer select 19 USCIBO transmit define DMAOTSEL__USCIA1RX 20 0x0001u channel O transfer select 20 USCIA1 receive define DMAOTSEL__USCIA1TX 21 0 0001 DMA channel O transfer select 21 USCIA1 transmit define DMAOTSEL__USCIB1RX 22 0x0001u DMA channel 0 transfer select 22 USCIB1 receive define DMAOTSEL__USCIB1TX 23 0x0001u channel 0 transfer select 23 USCIB1 transmit define DMAOTSEL__ADC12IFG 24 0x0001u DMA channel transfer select 24 ADC121FGx define DMAOTSEL RES25 25 0x0001u DMA channel 0 transfer select 25 Reserved define DMAOTSEL RES26 26 0x0001u DMA channel O transfer select 26 Reserved define DMAOTSEL USB FNRXD 27 0x0001u DMA channel 0 transfer select 27 USB FNRXD define DMAOTSEL USB READY 28 0x0001u channel 0 transfer select 28 USB ready define DMAOTSEL__MPY 29 0x0001u DMA channel 0 transfer select 29 Multiplier ready Page 135 define DMAOTSEL DMASIFG 30 0x0001u channel 0 transfer select 30 previous DMA channel DMASIFG define DMAOTSEL DMAEO 31 0x0001u DMA channel 0 transfer select 31 ext Trigger DMAEO define DMA1TSEL REQ 0 0 0100 channel 1 transfer select 0 DMA_REQ sw define DMA1TSEL__TAOCCRO 1 0x0100u DMA channel 1 transfer select 1
162. ects canvas delete ALL update the player ball based on the received string if b forward in data update_ball 0 y_inc if b backward in data update ball 0 y inc if b left in data update ball x inc O if b right in data update ball x inc O if only the blank string is received leave the player ball alone else update ball O O draw all the red balls for ball in balls X1 ball x ball rad y1 ball y ball rad 2 ball x ball rad y2 ball y ball rad canvas create oval x1 y1 x2 y2 fill red draw all the green balls for pointball in pointballs X1 pointball x pointball rad Page 68 1 pointball y pointball_rad x2 pointball x pointball_rad y2 pointball y pointball_rad canvas create_oval x1 y1 x2 y2 fill green update the position of red balls move update the position of green balls pointmove increment counter indicating whether more balls should spawn count 1 if enough time has passed spawn more balls if count 50 balls append Ball pointballs append PointBall count 0 display the score 5 1 score score2 str score score3 scorel score2 window title score3 update the canvas to draw new objects canvas update Page 69 set this to main loop to facilitate the software window mainloop Page 70 DEE e ER RETE id Standard register and bit definit
163. ee DEFINE NULL 0 0 value of ASCII NULL endif WIEL H Page 33 wifi c Created on Jun 5 2012 Author Josh Fromm This file contains the functions needed to interact with the Wifi module on the BioSleeve board through UART Table of Contents 1 UART_init void UART init sets up the registers needed for UART to properly function 2 wifi transmit char const char This function is used to transmit the passed string through UART to the wifi module which then sends transmits the string 3 UART handler void UART handler is the interrupt handler for UART receive interrupts The function loads a buffer with value received from the wifi module This function is unused in the current implementation of the BioSleeve include lt msp430f5335 h gt Page 34 include wifi h Create buffer used to store received characters Because buffer currently isn t being used it can contain a single character string char in buffer The UART_init function sets up the registers necesarry for the UART controller of the MSP430 to function properly It has no inputs or outputs void UART_init void P2SEL UART_PORTS set the needed UART ports to UART mode UCAOCTL1 UART_SMCLK set UART source clock to be equal to the MCLK UCAOBRO BAUD_RATE divide SMCLK to give baud rate of 9600 value needed by the wifi modul
164. efine ADC121FG12 define ADC121FG13 define ADC121FG14 define ADC121FG15 define ADC121FGO L define ADC12IFG1 L define ADC12IFG2 1 define ADC12IFG3 1 define ADC12IFGA 1 define ADC12IFG5 1 define ADC12IFG6 1 define ADC12IFG7 1 ttdefine ADC121FG8 H define ADC121FG9 H ttdefine ADC12IFG10 H define ADC121FG11 H define ADC12IFG12 define ADC121FG13 H Page 91 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 ADC12 Memory 8 ADC12 Memory 9 ADC12 Memory 10 ADC12 Memory 11 ADC12 Memory 12 ADC12 Memory 13 ADC12 Memory 14 ADC12 Memory 15 ADC12 Memory 0 ADC12 Memory 1 ADC12 Memory 2 ADC12 Memory 3 ADC12 Memory 4 ADC12 Memory 5 ADC12 Memory 6 ADC12 Memory 7 ADC12 Memory 8 ADC12 Memory 9 ADC12 Memory 10 ADC12 Memory 11 ADC12 Memory 12 ADC12 Memory 13 Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Inter
165. efine SVSHIFG_H 0x0010 SVS low side interrupt flag define SVSLIFG_H 0 0020 5 5 high side interrupt flag define PMMLPM5IFG_H 0x0080 LPMS indication Flag define PMMRSTLPMSIFG PMMLPMSIFG LPMS indication Flag PMMIE and RESET Control Bits define SVSMLDLYIE 0x0001 5 5 and SVM low side Delay expired interrupt enable define SVMLIE 0x0002 5 low side interrupt enable define SVMLVLRIE 0x0004 SVM low side Voltage Level Reached interrupt enable define SVSMHDLYIE 0x0010 SVS and SVM high side Delay expired interrupt enable ttdefine SVMHIE 0x0020 SVM high side interrupt enable define SVMHVLRIE 0x0040 SVM high side Voltage Level Reached interrupt enable Hdefine SVSLPE 0x0100 SVS low side POR enable define SVMLVLRPE 0x0200 SVM low side Voltage Level reached POR enable define SVSHPE 0x1000 SVS high side POR enable ttdefine SVMHVLRPE 0x2000 SVM high side Voltage Level reached POR enable PMMIE and RESET Control Bits Page 183 define SVSMLDLYIE_L 0x0001 5 5 SVM low side Delay expired interrupt enable define SVMLIE_L 0x0002 SVM low side interrupt enable define SVMLVLRIE L 0x0004 SVM low side Voltage Level Reached interrupt enable define SVSMHDLYIE 1 0x0010 SVS and SVM high side Delay expired interrupt enable define SVMHIE L 0x0020 SVM high side in
166. efine WDTPW 0x5A00 define WDTIS 0 0 0x0001u WDT Timer Interval Select 2G Hdefine WDTIS 1 1 0x0001u WDT Timer Interval Select 128M define WDTIS 2 2 0x0001u WDT Timer Interval Select 8192k define WDTIS 3 3 0x0001u WDT Timer Interval Select 512k Hdefine WDTIS 4 4 0x0001u WDT Timer Interval Select 32k define WDTIS_5 5 0 0001 WDT Timer Interval Select 8192 define WDTIS_6 6 0x0001u WDT Timer Interval Select 512 define WDTIS_7 7 0x0001u WDT Timer Interval Select 64 define WDTIS 26 0 0x0001u WDT Timer Interval Select 2G define 5 128M 1 0x0001u WDT Timer Interval Select 128M define WDTIS 8192K 2 0x0001u WDT Timer Interval Select 8192k define WDTIS 512 3 0x0001u WDT Timer Interval Select 512k Hdefine WDTIS 32K 4 0x0001u WDT Timer Interval Select 32k define WDTIS 8192 5 0x0001u WDT Timer Interval Select 8192 define WDTIS 512 6 0x0001u WDT Timer Interval Select 512 define WDTIS 64 7 0x0001u WDT Timer Interval Select 64 Page 270 define WDTSSEL_0 0 0x0020u WDT Timer Clock Source Select SMCLK define WDTSSEL_1 1 0x0020u WDT Timer Clock Source Select ACLK define WDTSSEL_2 2 0x0020u WDT Timer Clock Source Select VLO_CLK define WDTSSEL_3 3 0x0020u WDT Timer Clock Source Select reserved define WD
167. elect 7 24 32 Ref 0 Select 0 25 32 Ref 0 Select 1 26 32 Ref 0 Select 2 27 32 Ref 0 Select 3 28 32 Ref 0 Select 4 29 32 Ref 0 Select 5 30 32 Ref 0 Select 6 31 32 Ref 0 Select 7 32 32 define CBRS 0 define CBRS 1 define CBRS 2 define CBRS_3 define CBREF1_0 define CBREF1_1 define CBREF1_2 define CBREF1_3 define CBREF1_4 define CBREF1_5 define CBREF1_6 define CBREF1_7 define CBREF1_8 define CBREF1_9 define CBREF1_10 define CBREF1_11 define CBREF1_12 define CBREF1_13 define CBREF1_14 define CBREF1_15 define CBREF1_16 define CBREF1_17 define CBREF1_18 Page 105 0x0000 0x0040 0x0080 0 0000 0 0100 0 0200 0 0300 0 0400 0 0500 0 0600 0 0700 0 0800 0 0900 Ox0A00 0x0B00 0 0000 0 0 00 0 1000 0 1100 0 1200 Comp Reference Source 0 Off Comp Reference Source 1 Vcc Comp B Reference Source 2 Shared Ref Comp B Reference Source 3 Shared Ref Off Comp Int Ref 1 Select 0 1 32 Comp B Int Ref 1 Select 1 2 32 Comp B Int Ref 1 Select 2 3 32 Comp B Int Ref 1 Select 3 4 32 Comp B Int Ref 1 Select 4 5 32 Comp B Int Ref 1 Select 5 6 32 Comp B Int Ref 1 Select 6 7 32 Comp Int Ref 1 Select 7 8 32 Comp B Int Ref 1 Selec
168. evel SVS and SVM high side Reset Release Voltage Level SVS and SVM high side Reset Release Voltage Level SVS and SVM high side Reset Release Voltage Level SVS and SVM high side Reset Release Voltage Level SVS high side Reset Release Voltage Level 0 SVS high side Reset Release Voltage Level 1 SVS high side Reset Release Voltage Level 2 SVS high side Reset Release Voltage Level 3 SVS and SVM low side Reset Release Voltage Level SVS and SVM low side Reset Release Voltage Level SVS and SVM low side Reset Release Voltage Level SVS and SVM low side delay status define SVSLMD 0x0010 SVS low side mode define SVSMLEVM 0x0040 SVS and SVM low side event mask define SVSMLACE 0x0080 5 5 SVM low side auto control enable define SVSLRVLO 0x0100 SVS low side reset voltage level Bit 0 define SVSLRVL1 0 0200 SVS low side reset voltage level 1 define SVSLE 0x0400 SVS low side enable define SVSLFP 0x0800 SVS low side full performace mode define SVMLOVPE 0x1000 5 low side over voltage enable define SVMLE 0x4000 5 low side enable define SVMLFP 0x8000 SVM low side full performace mode SVSMLCTL Control Bits define SVSMLRRLO_L 0x0001 5 5 and SVM low side Reset Release Voltage Level Bit O define SVSMLRRL1_L 0x0002 SVS and SVM low side Reset Release Voltage
169. fi_transmit_char is passed the appropriate command string which is then sent out over UART to the wifi module before being transmitted to the client running Ball Blasters Infinity for processing If a character is ever received by the wifi module it triggers UART_handler which stores the character in in_buffer for potential further handling Page 20 System Code Note that code is written in c except for BallBlasters py which is written in python C files are of type c c headers are of type h and python files of type py Also note that it is almost certainly easier to view the following files directly in the attached zip containing all system code Table of Contents main c display h display c wifi h wifi c adc h adc c I2C h 12 10 BallBlasters py 11 msp430f5335 h NAM P WNP Page 21 main c Created on Jun 4 2012 Author Josh Fromm This file contains the main loop used to run the BioSleeve system include lt msp430f5335 h gt include wifi h include display h include adc h the main function initializes all major system registers the universal clock system and runs all the coded initialization functions The main function then enters an infinite loop which allows the system to run void main void int counter 0 counter used to space out position updates turn off watch dog controller WDTCTL WDTPW WDTHOLD Page
170. g Program Error Flag define MGRO 0x0010 Marginal read O mode define MGR1 0 0020 Marginal read 1 mode define LOCKINFO 0x0080 Lock INFO Memory bit read 1 Segment is locked read only FCTL4 Control Bits define VPE_L 0x0001 Voltage Changed during Program Error Flag define MGRO_L 0x0010 Marginal read 0 mode define MGR1_L 0x0020 Marginal read 1 mode Hdefine LOCKINFO_L 0x0080 Lock INFO Memory bit read 1 Segment is locked read only FCTL4 Control Bits FERIE ERRE E E aE E EKK KERK E E RA HARDWARE MULTIPLIER 32Bit EAE AE DOR A EE E k E E define MSP430 HAS 2 Definition to show that Module is available Page 150 define _ MSP430_BASEADDRESS_MPY32__ 0x04C0 SFR_16BIT MPY SFR_8BIT MPY_L SFR_8BIT MPY_H SFR_16BIT MPYS SFR_8BIT MPYS_L SFR_8BIT MPYS_H SFR_16BIT MAC SFR_8BIT MAC_L SFR_8BIT MAC_H SFR_16BIT MACS SFR_8BIT MACS_L SFR_8BIT MACS_H SFR_16BIT OP2 SFR_8BIT OP2_L SFR_8BIT OP2_H SFR_16BIT RESLO SFR_8BIT RESLO_L SFR_8BIT RESLO_H SFR_16BIT RESHI SFR_8BIT RESHI_L SFR_8BIT RESHI_H SFR_16BIT SUMEXT Page 151 Multiply Unsigned Operand 1 Multiply Unsigned Operand 1 Multiply Unsigned Operand 1 Multiply Signed Operand 1 Multiply Signed Operand 1 Multiply Signed Operand 1 Mult
171. heck if counter should be reset if counter MAX_COUNT counter 0 Initialize non used ISR vectors with a trap function currently all interrupt vectors are unused pragma vector RTC_VECTOR PORT2_VECTOR PORT1_VECTOR TIMER1_A1_VECTOR DMA_VECTOR TIMERO A1 VECTOR TIMERO AO VECTOR COMP B VECTOR LDO PWR VECTOR PORT3 VECT OR V Page 25 PORTA VECTOR TIMER1 AO VECTOR TIMER2 AO VECTOR TIMER2 1 VECTOR USCI A1 TOR N USCI BO VECTOR WDT VECTOR TIMERO B1 VECTOR TIMERO BO VECTOR UNMI_VECTOR SYSNMI_VECTOR USCI_B1_VECTOR __ interrupt void ISR_trap void the following will cause an access violation which results in a PUC reset WDTCTL 0 Page 26 display h Created on Jun 4 2012 Author Josh Fromm This file contains the constants used to initialze the LED display for the BioSleeve system Hifndef DISPLAY_H_ define DISPLAY_H_ initialize pins used to interact with display void display_init void wait for a while void display_wait void turn off all LEDs on the display void clear_display void DEFINE P9IO_SEL 0x0 value used to select I O for all pins of port 9 DEFINE P9_OUT_SEL OxFF value used to set all port 9 pins to output Page 27 DEFINE 4 SEL OxFFE9 value used to set bits corresponding to needed port 4 pins to I O DEFINE P4_OUT_SEL 0x16 value used to set needed po
172. imerO B7 Capture Compare 4 TBOCCR5 TimerO B7 Capture Compare 5 TBOCCR6 TimerO B7 Capture Compare 6 TBOEXO TimerO B7 Expansion Register O TBOIV TimerO B7 Interrupt Vector Word TIMERO B1 VECTOR TimerO B7 CC1 6 TB TIMERO BO VECTOR TimerO B7 CCO TBxCTL Control Bits define TBCLGRP1 define TBCLGRPO define CNTL1 ttdefine CNTLO define TBSSEL1 define TBSSELO define TBCLR define TBIE define TBIFG define SHR1 define SHRO define TBSSEL 0 Page 224 0x4000 TimerO B7 Compare latch load group 1 0x2000 TimerO B7 Compare latch load group 0 0x1000 Counter lenght 1 0x0800 Counter lenght 0 0x0200 Clock source 1 0x0100 Clock source 0 0x0004 TimerO B7 counter clear 0x0002 TimerO B7 interrupt enable 0x0001 TimerO B7 interrupt flag 0x4000 TimerO B7 Compare latch load group 1 0x2000 TimerO B7 Compare latch load group 0 0 0x0100u Clock Source TBCLK define TBSSEL_1 1 0x0100u Clock Source ACLK define TBSSEL_2 2 0x0100u Clock Source SMCLK define TBSSEL_3 3 0x0100u Clock Source INCLK define CNTL_0 0 0x0800u Counter lenght 16 bit define CNTL_1 1 0x0800u Counter lenght 12 bit define CNTL_2 2 0x0800u Counter lenght 10 bit define CNTL_3 3 0x0800u Counter lenght 8 bit define SHR_0 0 0x2000u TimerO B
173. ine 64 define 128 Page 199 0x0080 0 0040 0 0020 0 0000 0 0004 0 0008 0 0010 0 0014 0 0018 0 001 0 0000 0 0004 0 0008 0x000C 0x0010 0x0014 0x0018 Prescale Timer 0 Interrupt Enable Flag Prescale Timer Interrupt Flag Prescale Timer 0 Interrupt Interval 2 RTC Prescale Timer 0 Interrupt Interval 4 RTC Prescale Timer Interrupt Interval 8 RTC Prescale Timer 0 Interrupt Interval 16 Prescale Timer 0 Interrupt Interval 32 Prescale Timer 0 Interrupt Interval 64 Prescale Timer 0 Interrupt Interval 128 RTC Prescale Timer 0 Interrupt Interval 256 Prescale Timer 0 Interrupt Interval 2 Prescale Timer 0 Interrupt Interval 4 Prescale Timer 0 Interrupt Interval 8 Prescale Timer 0 Interrupt Interval 16 RTC Prescale Timer 0 Interrupt Interval 32 Prescale Timer 0 Interrupt Interval 64 Prescale Timer 0 Interrupt Interval 128 define 256 0x001C RTC Prescale Timer 0 Interrupt Interval 256 RTCPS1CTL Control Bits define Reserved 0x0080 ttdefine Reserved 0 0040 define Reserved 0x0020 define RT1IP2 0x0010 Prescale Timer 1 Interrupt Interval Bit 2 define RT1IP1 0x0008
174. ine TASSEL1 0 0200 Timer A clock source select 1 define TASSELO 0x0100 Timer A clock source select 0 define ID1 0x0080 Timer A clock input divider 1 define IDO 0x0040 Timer A clock input divider O define MC1 0x0020 Timer A mode control 1 define MCO 0x0010 Timer A mode control 0 define TACLR 0x0004 Timer A counter clear define TAIE 0x0002 Timer A counter interrupt enable define TAIFG 0x0001 Timer A counter interrupt flag define MC 0 0 0x10u Timer A mode control 0 Stop define MC 1 1 0x10u Timer A mode control 1 Up to CCRO define MC 2 2 0x10u Timer A mode control 2 Continuous up define MC 3 3 0x10u Timer A mode control 3 Up Down Hdefine ID 0 0 0x40u Timer A input divider O 1 Hdefine ID 1 1 0x40u Timer A input divider 1 2 Hdefine ID 2 2 0x40u Timer A input divider 2 4 define ID 3 3 0x40u Timer A input divider 8 Hdefine TASSEL 0 0 0x100u Timer A clock source select O TACLK Hdefine TASSEL 1 1 0x100u Timer A clock source select 1 ACLK Hdefine TASSEL 2 2 0x100u Timer A clock source select 2 SMCLK Hdefine TASSEL 3 3 0x100u Timer A clock source select 3 INCLK Page 216 define STOP 0 0x10u Timer A mode control O Stop define MC 1 0x10u Timer mode control 1 Up to CCRO define MC__C
175. ions for the Texas Instruments MSP430 microcontroller This file supports assembler and C development for MSP430F5335 devices Texas Instruments Version 1 3 Rev 1 0 Setup Rev 1 1 Changed access type of TimerA B registers to word only Rev 1 2 Fixed definition of RTCTEV 0000 and RTCTEV 1200 Removed availabe bits RTCSSELx Rev 1 2 Fixed wrong definitions in DMA Trigger 7 and 8 ER E E RR Io RE OE RE ar I ifndef 5 430 5335 Hdefine __MSP430F5335 define _MSP430_HEADER VERSION 1063 Page 71 Hifdef cplusplus extern C I Hendif Neen i NERE PERIPHERAL FILE A RON LITI External references resolved by device specific linker command file define SFR_8BIT address extern volatile unsigned char address define SFR_16BIT address extern volatile unsigned int address define SFR_20BIT address extern volatile unsigned int address typedef void SFR FARPTR define SFR_20BIT address extern SFR_FARPTR address define SFR_32BIT address extern volatile unsigned long address FERRATE RR E RR STANDARD BITS EG E define BITO 0x0001 Page 72 define BIT1 0x0002 define BIT2 0x0004 define BIT3 0x0008 define 0x0010 define BITS 0x0020 define BIT6 0x0040 define BI
176. iply Unsigned and Accumulate Operand 1 Multiply Unsigned and Accumulate Operand 1 Multiply Unsigned and Accumulate Operand 1 Multiply Signed and Accumulate Operand 1 Multiply Signed and Accumulate Operand 1 Multiply Signed and Accumulate Operand 1 Operand 2 Operand 2 Operand 2 Result Low Word Result Low Word Result Low Word Result High Word Result High Word Result High Word Sum Extend SFR 8 5 1 SFR_8BIT SUMEXT_H SFR_16BIT MPY32L SFR_8BIT MPY32L_L SFR_8BIT MPY32L_H SFR_16BIT MPY32H SFR_8BIT MPY32H_L SFR_8BIT MPY32H_H SFR_16BIT MPYS32L SFR_8BIT MPYS32L_L SFR_8BIT MPYS32L_H SFR_16BIT MPYS32H SFR_8BIT MPYS32H_L SFR_8BIT MPYS32H_H SFR_16BIT MAC32L SFR_8BIT MAC32L_L SFR_8BIT MAC32L_H SFR_16BIT MAC32H SFR_8BIT MAC32H_L SFR_8BIT MAC32H_H SFR_16BIT MACS32L word SFR_8BIT MACS32L_L word Page 152 Sum Extend Sum Extend 32 bit operand 1 multiply low word 32 bit operand 1 multiply low word 32 bit operand 1 multiply low word 32 bit operand 1 multiply high word 32 bit operand 1 multiply high word 32 bit operand 1 multiply high word 32 bit operand 1 signed multiply low word 32 bit operand 1 signed multiply low word 32 bit operand 1 signed multiply low word 32 bi
177. ivider 6 ACLK Source Divider 7 ACLK Source Divider f ACLK 1 ACLK Source Divider f ACLK 2 ACLK Source Divider f ACLK 4 ACLK Source Divider f ACLK 8 ACLK Source Divider f ACLK 16 ACLK Source Divider f ACLK 32 ACLK from Pin Source Divider 0 ACLK from Pin Source Divider 1 ACLK from Pin Source Divider 2 ACLK from Pin Source Divider 3 ACLK from Pin Source Divider 4 ACLK from Pin Source Divider 5 ACLK from Pin Source Divider 6 ACLK from Pin Source Divider 7 define DIVPA 1 0x0000 ACLK from Pin Source Divider 1 define DIVPA 2 0x1000 ACLK from Pin Source Divider 2 Hdefine DIVPA 4 0x2000 ACLK from Pin Source Divider f ACLK 4 define DIVPA__8 0x3000 ACLK from Pin Source Divider f ACLK 8 define DIVPA__16 0 4000 ACLK from Pin Source Divider 16 define DIVPA__32 0x5000 ACLK from Pin Source Divider f ACLK 32 UCSCTL6 Control Bits define XT1OFF 0x0001 High Frequency Oscillator 1 XT1 disable define SMCLKOFF 0x0002 SMCLK Off define XCAPO 0x0004 Cap Bit O define XCAP1 0x0008 Cap Bit 1 define XT1BYPASS 0x0010 XT1 bypass mode 0 internal 1 sourced from external pin define XTS 0x0020 1 Selects high freq oscillator define XT1DRIVEO 0x0040 Dri
178. l JTAG mailbox control JTAG mailbox control JTAG mailbox input O JTAG mailbox input O JTAG mailbox input O JTAG mailbox input 1 JTAG mailbox input 1 JTAG mailbox input 1 JTAG mailbox output 0 JTAG mailbox output 0 JTAG mailbox output 0 JTAG mailbox output 1 JTAG mailbox output 1 JTAG mailbox output 1 Bus Error vector generator Bus Error vector generator Bus Error vector generator User NMI vector generator User NMI vector generator User NMI vector generator System NMI vector generator SFR_8BIT SYSSNIV_L SFR_8BIT SYSSNIV_H SFR_16BIT SYSRSTIV SFR_8BIT SYSRSTIV_L SFR_8BIT SYSRSTIV_H SYSCTL Control Bits Hdefine SYSRIVECT define RESERVED define SYSPMMPE define RESERVED define SYSBSLIND define SYSJTAGPIN define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED define RESERVED Page 207 System NMI vector generator System NMI vector generator Reset vector generator Reset vector generator Reset vector generator 0x0001 SYS RAM based interrupt vectors 0x0002 SYS Reserved 0x0004 SYS PMM access protect 0 0008 SYS Reserved 0x0010 SYS TCK RST indication detected
179. l Time Clock Time 1 Real Time Clock Time 1 Real Time Clock Time 1 Real Time Clock Date Real Time Clock Date Real Time Clock Date Real Time Clock Year Real Time Clock Year Real Time Clock Year Real Time Clock Alarm Min Hour SFR_8BIT RTCAMINHR_L Real Time Clock Alarm Min Hour SFR_8BIT RTCAMINHR_H Real Time Clock Alarm Min Hour SFR_16BIT RTCADOWDAY Real Time Clock Alarm day of week day SFR_8BIT RTCADOWDAY_L Real Time Clock Alarm day of week day SFR_8BIT RTCADOWDAY_H Real Time Clock Alarm day of week day SFR_16BIT BIN2BCD SFR_16BIT BCD2BIN Hdefine RTCCTLO Hdefine RTCCTL1 Hdefine RTCCTL2 Hdefine RTCCTL3 Page 193 Real Time Binary to BCD conversion register Real Time BCD to binary conversion register RTCCTLO1 L Real Time Clock Control 0 RTCCTLO1 Real Time Clock Control 1 RTCCTL23 1 Real Time Clock Control 2 RTCCTL23 Real Time Clock Control 3 define RTCNT12 define RTCNT34 define RTCNT1 define RTCNT2 define RTCNT3 define RTCNT4 define RTCSEC define RTCMIN Hdefine RTCHOUR Hdefine RTCDOW Hdefine RTCDAY Hdefine RTCMON Hdefine RTCYEARL Hdefine RTCYEARH Hdefine RTOPS Hdefine RT1PS Hdefine RTCAMIN Hdefine RTCAHOUR Hdefine RTCADOW Hdefine RTCADAY RTCTIMO RTCTIM1 RTCTIMO_L RTCTIMO_H RTCTIM1_L RTCTIM1_H RTCTIMO_L RTCTIMO_H R
180. lay the game in Each time data is received via wifi the game updates the graphical interface and occasionally adds balls Balls are generated with a random velocity that determines how much each update changes their position causing them to appear to move Each update the program checks if the players blue ball has collided with any of the other balls and reacts accordingly Whenever a command string is received the game updates the position of the players blue ball Page 17 Interaction of Software Functions Initialization done Page 18 Page 19 SNIHVHS FITAVIYVA dIOA WHY Explanation of Function Diagrams The system is initialized during the non loop portion of main c In the initialization code the master clock is established all ports are set to use minimal power and the peripheral initialization code is called main c then proceeds to enter the main loop and run the system by continually reactivating adc reads and occasionally checking if a command string should be sent Each time an adc read finishes an adc interrupt triggers the adc_handler function which displays the magnitude of electrical activity being measured in the electrode array and updates the shared variables indicating what position the accelerometer is in When update_ position is called it checks if the accelerometer is shifted sufficiently from its zero position to warrant the transfer of a command character If a command character should be sent wi
181. m 19019 dA331SOl8 7 Explanation of Each Block CPU The system uses an MSP430F5335 processor The CPU is the core of the system all other block interacts directly with the CPU The CPU is designed to interact with peripherals through separate ports which can be configured to have a wide range of functions Ports are either configured as non distinct I O or to specific functions such as ADC and UART It should be noted that this CPU contains internal flash memory and SRAM so external memory is not needed JTAG The JTAG block allows debuggers to interface with the CPU Clock Logic The clock logic block is used to source a 32 KHz external clock which can then be internally multiplied to generate the master clock of the system Reset Logic Reset logic allows the user to reset the system and trigger calibration sequences on demand Display The display block is used to convey information to the user IMU although unused in the current implementation of the BioSleeve the IMU can be used to determine angular offset of the system Electrode Array The electrode array measures electrical activity in the user s arm which is converted to a digital signal in the CPU then sent to the display Accelerometer The accelerometer is used to detect position changes in the accelerometer glove which is used to control the Ball Blasters Infinity game Wifi Module The wifi module is used
182. n Start Address Bit 1 define ADC12CSTARTADD2 0 4000 ADC12 Conversion Start Address Bit 2 define ADC12CSTARTADD3 0x8000 ADC12 Conversion Start Address Bit 3 Page 83 ADC12CTL1 Control Bits define ADC12BUSY_L 0 0001 ADC12 Busy define ADC12CONSEQO_L 0x0002 ADC12 Conversion Sequence Select 0 define ADC12CONSEQ1_L 0x0004 ADC12 Conversion Sequence Select Bit 1 define ADC12SSELO L 0x0008 ADC12 Clock Source Select Bit 0 define ADC12SSEL1 L 0x0010 ADC12 Clock Source Select Bit 1 define ADC12DIVO L 0x0020 ADC12 Clock Divider Select Bit O ttdefine ADC12DIV1 L 0x0040 ADC12 Clock Divider Select Bit 1 ttdefine ADC12DIV2 L 0x0080 ADC12 Clock Divider Select Bit 2 ADC12CTL1 Control Bits define ADC12ISSH H 0x0001 ADC12 Invert Sample Hold Signal define ADC12SHP H 0x0002 ADC12 Sample Hold Pulse Mode define ADC12SHSO H 0x0004 ADC12 Sample Hold Source O define ADC12SHS1 H 0x0008 ADC12 Sample Hold Source Bit 1 define ADC12CSTARTADDO H 0x0010 ADC12 Conversion Start Address Bit O define ADC12CSTARTADD1 0x0020 ADC12 Conversion Start Address Bit 1 define ADC12CSTARTADD2 H 0x0040 ADC12 Conversion Start Address Bit 2 define ADC12CSTARTADD3 0x0080 ADC12 Conversion Start Address Bit 3 define ADC12CONSEQ 0 0 2u ADC12 Conversion
183. nce IO E E RACE ERE EA RE RR define MSP430 HAS REF Definition to show that Module is available define MSP430 BASEADDRESS REF 0x01BO SFR 16BIT REFCTLO REF Shared Reference control register O SFR 8BIT REFCTLO 1 REF Shared Reference control register 0 SFR 8BIT REFCTLO REF Shared Reference control register 0 Page 189 REFCTLO Control Bits define REFON define REFOUT define RESERVED define REFTCOFF define REFVSELO define REFVSEL1 define RESERVED define REFMSTR define REFGENACT define REFBGACT define REFGENBUSY define BGMODE define RESERVED define RESERVED define RESERVED define RESERVED 0x0001 REF Reference On 0x0002 REF Reference output Buffer On 0x0004 Reserved 0x0008 REF Temp Sensor off 0x0010 REF Reference Voltage Level Select Bit 0 0x0020 REF Reference Voltage Level Select Bit 1 0x0040 Reserved 0x0080 REF Master Control 0x0100 REF Reference generator active 0x0200 REF Reference bandgap active 0x0400 REF Reference generator busy 0x0800 REF Bandgap mode 0x1000 Reserved 0x2000 Reserved 0x4000 Reserved 0x8000 Reserved REFCTLO Control Bits ttdefine REFON L define REFOUT define RESERVED define REFTCOFF 1 define REFVSELO 1 Page 190 0x0001 REF Referen
184. nd SVM high side event mask define SVSMHACE L 0x0080 SVS and SVM high side auto control enable SVSMHCTL Control Bits ttdefine SVSHRVLO H 0x0001 SVS high side reset voltage level Bit O define SVSHRVL1 H 0x0002 SVS high side reset voltage level Bit 1 define SVSHE H 0x0004 SVS high side enable define SVSHFP_H 0x0008 SVS high side full performace mode define SVMHOVPE_H 0 0010 5 high side over voltage enable define SVMHE_H 0x0040 5 high side enable define SVMHFP_H 0x0080 SVM high side full performace mode define SVSMHRRL_O 0x0000 SVS and SVM high side Reset Release Voltage Level 0 Page 177 define SVSMHRRL_1 Ly Hdefine SVSMHRRL 2 2 define SVSMHRRL 3 3 define SVSMHRRL_4 4 define SVSMHRRL_5 5 define SVSMHRRL_6 6 define SVSMHRRL 7 define SVSHRVL_0 define SVSHRVL_1 define SVSHRVL_2 define SVSHRVL_3 0x0001 0x0002 0x0003 0 0004 0 0005 0 0006 0x0007 0x0000 0 0100 0x0200 0x0300 SVSMLCTL Control Bits define SVSMLRRLO Bit 0 define SVSMLRRL1 Bit 1 define SVSMLRRL2 Bit 2 define SVSMLDLYST Page 178 0x0001 0x0002 0x0004 0x0008 SVS and SVM high side Reset Release Voltage Level SVS and SVM high side Reset Release Voltage Level SVS and SVM high side Reset Release Voltage L
185. nd accelerometer are initialzed in this function 2 calibrate void averages readings from the accelerometer over a fixed set of time and sets the average as the base position of the accelerometer meaning directional outputs will be based on the position of the accelerometer with respect to the calculated base position During calibration the function outputs to the display causing a loading sequence of bars to appear When the the display returns to showing the readings from the electrodes calibration is complete Page 41 3 update_position void checks the values of the acelerometer transmits directional outputs via UART if the the x or y axes are sufficiently shifted from their base positions 4 adc_handler void handles a read of the adc ports on the CPU Outputs an electrode pattern to the display and updates the values read from the accelerometer include lt msp430f5335 h gt include adc h include display h include wifi h shared variables int elec_count 0 counter used to keep track of which electrode should be output to the display int x_val value used for most recent x axis accelerometer read int y_val value used for most recent y axis acceleromter read int z_val value used for most recent z axis accelerometer read int x_base 0 calculated zero position of accelerometer along x axis int y_base 0 c
186. ndication Interrupt Enable define VBONIE 0x0200 PU Legacy Definiton Coming ON Interrupt Enable define VBOFFIE 0x0400 PU Legacy Definiton LDOI Going OFF Interrupt Enable FERRATE CORE RETE RAEE RR RE EE E RE E ER RAM Control Module RARE ATER EE EE REA RR EE e define 5 430 HAS RC Definition to show that Module is available define MSP430_BASEADDRESS_RC__ 0x0158 SFR_16BIT RCCTLO Ram Controller Control Register SFR_8BIT RCCTLO_L Ram Controller Control Register SFR_8BIT RCCTLO_H Ram Controller Control Register RCCTLO Control Bits define RCRSOOFF 0x0001 RAM Controller RAM Sector 0 Off define RCRS1OFF 0x0002 RAM Controller RAM Sector 1 Off define RCRS2OFF 0x0004 RAM Controller RAM Sector 2 Off Page 188 define RCRS30FF 0x0008 RAM Controller RAM Sector 3 Off define RCRS7OFF 0x0080 RAM Controller RAM Sector 7 USB Off RCCTLO Control Bits define RCRSOOFF_L 0x0001 RAM Controller RAM Sector 0 Off define RCRS1OFF L 0x0002 RAM Controller RAM Sector 1 Off Hdefine RCRS2OFF L 0x0004 RAM Controller RAM Sector 2 Off Hdefine RCRS3OFF L 0x0008 RAM Controller RAM Sector 3 Off Hdefine RCRS7OFF L 0x0080 RAM Controller RAM Sector 7 USB Off RCCTLO Control Bits define RCKEY 0x5A00 EEE ER REEE E RE RAR RE E EE EEE AE Shared Refere
187. ne X define RESERVED 0x0080 RESERVED define RESERVED 0x0100 RESERVED define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0x2000 RESERVED define RESERVED 0x4000 RESERVED define RESERVED 0x8000 RESERVED UCSCTL8 Control Bits define ACLKREQEN 0x0001 ACLK Clock Request Enable define MCLKREQEN 0x0002 Clock Request Enable define SMCLKREQEN 0x0004 SMCLK Clock Request Enable define MODOSCREQEN 0x0008 MODOSC Clock Request Enable define RESERVED 0x0010 RESERVED Page 251 define RESERVED 0x0020 RESERVED define RESERVED 0 0040 RESERVED define RESERVED 0 0080 RESERVED define RESERVED 0 0100 RESERVED define RESERVED 0 0200 RESERVED define RESERVED 0 0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x1000 RESERVED define RESERVED 0 2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0 8000 RESERVED UCSCTL8 Control Bits define ACLKREQEN_L 0x0001 Clock Request Enable define MCLKREQEN_L 0x0002 Clock Request Enable define SMCLKREQEN_L 0x0004 5 Clock Request Enable define MODOSCREQEN_L
188. nel 5 transfer select 20 USCIA1 receive define DMASTSEL_21 21 0x0100u DMA channel 5 transfer select 21 USCIA1 transmit define DMASTSEL_22 22 0x0100u DMA channel 5 transfer select 22 USCIB1 receive define DMASTSEL_23 23 0x0100u DMA channel 5 transfer select 23 USCIB1 transmit define DMASTSEL_24 24 0x0100u DMA channel 5 transfer select 24 ADC12IFGx define DMASTSEL_25 25 0x0100u channel 5 transfer select 25 DAC12 OIFG define DMASTSEL_26 26 0x0100u channel 5 transfer select 26 DAC12 1IFG define DMASTSEL__RES27 27 0x0100u DMA channel 5 transfer select 27 Reserved Hdefine DMASTSEL RES28 28 0x0100u channel 5 transfer select 28 Reserved define DMASTSEL_29 29 0x0100u DMA channel 5 transfer select 29 Multiplier ready define DMASTSEL_30 30 0x0100u DMA channel 5 transfer select 30 previous DMA channel DMA4IFG define DMASTSEL_31 31 0x0100u DMA channel 5 transfer select 31 ext Trigger DMAEO Page 133 define DMAOTSEL REQ 0 0 0001 DMA channel 0 transfer select 0 REQ sw define DMAOTSEL__TAOCCRO TAOCCRO IFG define DMAOTSEL__TAOCCR2 TAOCCR2 IFG define DMAOTSEL__TA1CCRO TA1CCRO IFG define DMAOTSEL__TA1CCR2 TA1CCR2 IFG define DMAOTSEL__TA2CCRO TA2CCRO IFG define DMAOTSEL__TA2CCR2 TA2CCR2 IFG define DMAOTSEL__TBOCCR
189. nnel 2 Control DMA Channel 2 Control DMA Channel 2 Control Channel 2 Source Address DMA Channel 2 Source Address Channel 2 Destination Address Channel 2 Destination Address Channel 2 Transfer Size DMA Channel 3 Control DMA Channel 3 Control DMA Channel 3 Control Channel 3 Source Address Channel 3 Source Address DMA Channel 3 Destination Address DMA Channel 3 Destination Address Channel 3 Transfer Size DMA Channel 4 Control Channel 4 Control DMA Channel 4 Control SFR 20BIT DMAASA SFR 16BIT DMAASAL SFR 20BIT DMA4DA SFR 16BIT DMA4DAL SFR 16BIT DMAASZ SFR 16BIT DMASCTL SFR 8BIT DMASCTL 1 SFR 8BIT DMASCTL Hl SFR 20 55 SFR 16BIT DMAS5SAL SFR 20 SFR 16 SFR 16 552 DMACTLO Control Bits define DMAOTSELO ttdefine DMAOTSEL1 define DMAOTSEL2 define DMAOTSEL3 ttdefine DMAOTSELA define DMA1TSELO define DMA1TSEL1 define DMA1TSEL2 Page 114 0 0001 0 0002 0 0004 0x0008 0 0010 0 0100 0 0200 0x0400 Channel 4 Source Address Channel 4 Source Address DMA Channel 4 Destination Address Channel 4 Destination Address DMA Channel 4 Transfer Size DMA Channel 5 Control
190. nsfer select 25 Reserved define DMA3TSEL__RES26 26 0x0100u DMA channel 3 transfer select 26 Reserved define DMA3TSEL__RES27 27 0x0100u DMA channel 3 transfer select 27 Reserved define DMA3TSEL__RES28 28 0x0100u DMA channel 3 transfer select 28 Reserved define DMA3TSEL__MPY 29 0x0100u channel 3 transfer select 29 Multiplier ready define DMA3TSEL DMA2IFG 30 0 0100 DMA channel 3 transfer select 30 previous DMA channel DMA2IFG define DMA3TSEL DMAEO 31 0x0100u DMA channel 3 transfer select 31 ext Trigger DMAEO define REQ 0 0x0001u DMA channel 4 transfer select 0 DMA_REQ sw define DMA4TSEL_TAOCCRO 1 0x0001u channel 4 transfer select 1 TimerO A TAOCCRO IFG define DMA4TSEL__TAOCCR2 2 0x0001u DMA channel 4 transfer select 2 TimerO A TAOCCR2 IFG Page 142 define DMA4TSEL_ TA1CCRO 3 0x0001u DMA channel 4 transfer select 3 Timer1 TA1CCRO IFG define DMA4TSEL_TA1CCR2 4 0x0001u DMA channel 4 transfer select 4 Timer1 TA1CCR2 IFG define DMA4TSEL_TA2CCRO 5 0x0001u DMA channel 4 transfer select 5 Timer2 A TA2CCRO IFG define DMA4TSEL TA2CCR2 6 0x0001u DMA channel 4 transfer select 6 Timer2_A TA2CCR2 IFG define DMA4TSEL__TBOCCRO 7 0x0001u channel 4 transfer select 7 TimerBO TBOCCRO IFG define DMA4TSEL__T
191. ntrol Register 0 SFR 16BIT UCSCTL1 UCS Control Register 1 SFR 8BIT UCSCTL1 1 UCS Control Register 1 SFR_8BIT UCSCTL1_H UCS Control Register 1 SFR_16BIT UCSCTL2 UCS Control Register 2 SFR_8BIT UCSCTL2_L UCS Control Register 2 SFR_8BIT UCSCTL2_H UCS Control Register 2 SFR_16BIT UCSCTL3 UCS Control Register 3 SFR_8BIT UCSCTL3_L UCS Control Register 3 SFR_8BIT UCSCTL3_H UCS Control Register 3 SFR 16BIT UCSCTLA UCS Control Register 4 SFR 8BIT UCSCTLA L UCS Control Register 4 Page 228 SFR_8BIT UCSCTL4_H SFR_16BIT UCSCTL5 SFR_8BIT UCSCTL5_L SFR_8BIT UCSCTL5_H SFR 16BIT UCSCTL6 SFR 8BIT UCSCTL6 1 SFR 8BIT UCSCTL6 SFR 16BIT UCSCTL7 SFR 8BIT UCSCTL7 1 SFR 8BIT UCSCTL7 HI SFR 16BIT UCSCTL8 SFR 8BIT UCSCTLS8 1 SFR 8BIT UCSCTL8 HI UCSCTLO Control Bits define RESERVED define RESERVED define RESERVED define MODO define MOD define MOD2 define MOD3 define MOD4 define DCOO Page 229 0 0001 0 0002 0 0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 UCS Control Register 4 UCS Control Register 5 UCS Control Register 5 UCS Control Register 5 UCS Control Register 6 UCS Control Register 6 UCS Control Register 6 UCS Control Register 7 UCS Control Register 7 UCS Control Register 7 UCS Control Register
192. ol Word Register 0 SFR_8BIT UCB1CTLWO_L USCI B1 Control Word Register 0 SFR_8BIT UCB1CTLWO_H USCI B1 Control Word Register 0 Hdefine UCB1CTL1 UCB1CTLWO L USCI B1 Control Register 1 Hdefine UCB1CTLO UCB1CTLWO USCI B1 Control Register 0 Page 267 SFR_16BIT UCB1BRW USCI B1 Baud Word Rate 0 SFR 8BIT UCB1BRW L USCI B1 Baud Word Rate 0 SFR 8BIT UCB1BRW H USCI B1 Baud Word Rate 0 define UCB1BRO UCB1BRW USCI B1 Baud Rate 0 define UCB1BR1 UCB1BRW USCI B1 Baud Rate 1 SFR_8BIT UCB1STAT USCI B1 Status Register SFR_8BIT UCB1RXBUF USCI B1 Receive Buffer SFR_8BIT UCB1TXBUF USCI B1 Transmit Buffer SFR_16BIT UCB112COA USCI B112C Own Address SFR 8BIT UCB1I2COA L USCI B1 12C Own Address SFR 8BIT UCB1I2COA USCI B1 12C Own Address SFR 16BIT UCB112CSA USCI B1 I2C Slave Address SFR 8BIT UCB1I2CSA 1 USCI B1 I2C Slave Address SFR 8BIT UCB1I2CSA USCI B1 I2C Slave Address SFR 16BIT UCB1ICTL USCI B1 Interrupt Enable Register SFR 8BIT UCB1ICTL 1 USCI B1 Interrupt Enable Register SFR 8BIT UCB1ICTL USCI B1 Interrupt Enable Register define UCB1IE UCB1ICTL USCI B1 Interrupt Enable Register Hdefine UCB1IFG UCB1ICTL USCI B1 Interrupt Flags Register SFR 16BIT UCB1IV USCI B1 Interrupt Vector Register E EE WATCHDOG
193. orts of the CPU to minimize power consumption and then moves on to set up the universal clock system to generate a master clock of 2 15 megahertz Main c then calls all the initialization functions needed for the system to interact with the hardware Once fully initialized the code enters the main loop which performs analog to digital conversions and checks whether command characters need to be sent to the wifi module This loop continues indefinitely display c display c contains the functions needed to initialize the pins used to control the display and clear the display when necessary This is accomplished through direct output control of the pins used to interact with the display adc c adc c is the code used to regulate all analog to digital conversions in the system adc c controls the CPU s interaction with both the electrode array and accelerometer The code contains the basic adc initialization code as well as the calibration code needed to calculate a zero point for the accelerometer The code also sets up an interrupt that is generated each time an adc conversion cycle finish One adc conversion cycle is set to make many adc readings one for each pin of ADC12 used When an adc interrupt occurs the adc handler reads from the electrode array converts the read data to a magnitude and displays one of the converted values on the display The electrode displayed is determined by a shared counter variable that iterates through the num
194. per is in place or to any devices on the same network as the module listening to port 2000 if the adhoc jumper is removed IMU The system contains an ITG 3200 inertial measurement unit Although the current implementation of the system does not use the IMU the code and hardware needed for IMU interaction is included in this manual The IMU communicates with the CPU over the 12C interface at a data transfer rate of 100Khz The IMU contains registers which store values indicating the tilt of the internal gyros By accessing these registers the CPU can determine the tilt of the system When interacting with the IMU the following protocol must be used Single Byte Read Sequence CPU S AD W RA S AD R NACK P DATA ACK ACK ACK Read Protocol for IMU with RA register address AD address of IMU Single Byte Write Sequence Write protocol for IMU Page 13 Software Manual This section details how the software run by the system works The following image is a diagram of how each of the functions of the software interacts with each other and the hardware For more detailed explanations on how the software works see the software section at the end of this manual Page 14 Major Code Blocks with Hardware Page 15 Explanation of Files is the code that is run immediately after a system reset or power up main c immediately sets up all p
195. position function pragma vector ADC12_VECTOR __interrupt void adc_handler void Page 48 int elec1 variable containing the selected electrode reading int elec2 variable containing the magnitude conversion of elec1 int elecout value that is output to the display only process electrodes if the system is calibrated if uncalibrated CALIBRATED clear_display clear the display read from one of the electrodes depending on elec_count if elec count 0 elec1 ADC12MEMO else if elec_count 1 elec1 ADC12MEM1 else if elec_count 2 elec1 ADC12MEM2 else if elec_count 3 elec1 ADC12MEM3 Page 49 elec_count 1 increment elec_count and set back to zero if it exceeds the number of electrodes if elec_count gt NUM_ELEC elec count 0 convert read value to a magnitude form if elec1 lt 0 elec1 0 else if elec1 RAIL_NOISE elec1 0 turn the read value into an integer indicating which bar LEDs should be set elec2 elec1 CONV_VAL determine if highest bars of display need to be set and set them if if so if elec2 LOW TRIG amp elec2 HIGH TRIG P4OUT P4 LED LOW Page 50 else if elec2 gt HIGH TRIG P4OUT P4_LED_HIGH if high bars not set then set the lower bars else elecout 0x1 lt lt elec2 1
196. r2 A3 Capture Compare 1 Timer2 A3 Capture Compare 2 Timer2 A3 Interrupt Vector Word Timer2 A3 Expansion Register O Bits are already defined within the TimerO Ax Page 221 TA2IV Definitions define TA2IV_NONE 0x0000 No Interrupt pending define TA2IV_TA1CCR1 0 0002 TA2CCR1_CCIFG define TA2IV_TA1CCR2 0x0004 TA2CCR2 CCIFG define TA2IV_3 0x0006 Reserved define TA2IV_4 0x0008 Reserved define 2 5 0x000A Reserved define TA2IV 6 0x000C Reserved define 2 TA2IFG 0x000E TA2IFG AEREE TE E ERE Ar Timer0_B7 EE IOKCEOKOIORCICICIORGIOR ICIORTIOILOKIOIOK IOIONORGIOR IOIOIIOIOR OK e ERRE Hdefine MSP430 HAS TOB7 Definition to show that Module is available Hdefine 5 430 BASEADDRESS TOB7 0x03C0 SFR 16BIT TBOCTL TimerO B7 Control SFR 16BIT TBOCCTLO TimerO B7 Capture Compare Control 0 SFR 16BIT TBOCCTL1 TimerO B7 Capture Compare Control 1 SFR 16BIT TBOCCTL2 TimerO B7 Capture Compare Control 2 SFR 16BIT TBOCCTL3 TimerO B7 Capture Compare Control 3 SFR 16BIT TBOCCTLA TimerO B7 Capture Compare Control 4 SFR 16BIT TBOCCTL5 TimerO B7 Capture Compare Control 5 SFR 16 6 TimerO B7 Capture Compare Control 6 Page 222 SFR_16BIT TBOR TimerO B7 SFR 16BIT TBOCCRO TimerO B7 Capture Compare 0 SFR 16
197. rand 2 high word 32 bit operand 2 high word 32x32 bit result O least significant word 32x32 bit result O least significant word 32x32 bit result O least significant word 32x32 bit result 1 32x32 bit result 1 32x32 bit result 1 32x32 bit result 2 32x32 bit result 2 32x32 bit result 2 32x32 bit result 3 most significant word 32x32 bit result 3 most significant word 32x32 bit result 3 most significant word SFR_16BIT MPY32CTLO MPY32 Control Register 0 SFR_8BIT MPY32CTLO_L MPY32 Control Register 0 SFR_8BIT MPY32CTLO_H MPY32 Control Register 0 define 1 Multiply Unsigned Operand 1 Byte Access define MPYS_B MPYS_L Multiply Signed Operand 1 Byte Access define MAC_B MAC_L Multiply Unsigned Accumulate Operand 1 Byte Access define MACS_B MACS_L Multiply Signed and Accumulate Operand 1 Byte Access define OP2_B OP2_L Operand 2 Byte Access define MPY32L_B MPY32L 32 bit operand 1 multiply low word Byte Access define MPY32H_B MPY32H_L X 32 bit operand 1 multiply high word Byte Access define MPYS32L_B MPYS32L L 32 bit operand 1 signed multiply low word Byte Access define MPYS32H_B MPYS32H L 32 bit operand 1 signed multiply high word Byte Access define MAC32L_B MAC32L 32 bit operand 1 mul
198. rce Select 6 define SELS_7 0x0070 5 Source Select 7 define SELS XT1CLK 0x0000 5 Source Select XT1CLK define SELS__VLOCLK 0x0010 5 Source Select VLOCLK define SELS 0 0020 5 Source Select REFOCLK define SELS__DCOCLK 0x0030 5 Source Select DCOCLK define SELS__DCOCLKDIV 0x0040 SMCLK Source Select DCOCLKDIV define 5 15 XT2CLK 0x0050 SMCLK Source Select XT2CLK Hdefine SELA 0 0x0000 ACLK Source Select 0 Hdefine SELA 1 0x0100 ACLK Source Select 1 define SELA 2 0x0200 ACLK Source Select 2 Hdefine SELA 3 0x0300 ACLK Source Select 3 Hdefine SELA 4 0x0400 ACLK Source Select 4 Hdefine SELA 5 0x0500 ACLK Source Select 5 Hdefine SELA 6 0x0600 ACLK Source Select 6 Hdefine SELA 7 0x0700 ACLK Source Select 7 define 5 XT1CLK 0x0000 ACLK Source Select XT1CLK define SELA__VLOCLK 0x0100 Source Select VLOCLK define SELA__REFOCLK 0x0200 Source Select REFOCLK define SELA 0x0300 Source Select DCOCLK define SELA DCOCLKDIV 0x0400 ACLK Source Select DCOCLKDIV define SELA XT2CLK 0x0500 Source Select XT2CLK Page 242 UCSCTL5 Control Bits define DIVMO define DIVM1 define DIVM2 define RESERVED define DIVSO define DIVS1 define DIVS2
199. rol Bits define UCSSEL1 0x80 define UCSSELO 0 40 define UCRXEIE 0x20 define UCBRKIE 0x10 itdefine UCDORM 0x08 itdefine UCTXADDR 0x04 define UCTXBRK 0x02 Page 257 USCI 0 Clock Source Select 1 USCI 0 Clock Source Select 0 RX Error interrupt enable Break interrupt enable Dormant Sleep Mode Send next Data as Address Send next Data as Break define UCSWRST 0 01 USCI Software Reset UCxxCTL1 SPI Mode Control Bits define res 0x20 reserved ttdefine res 0x10 reserved define res 0x08 reserved define res 0x04 reserved define res 0x02 reserved UCBxCTL1 I2C Mode Control Bits define res 0x20 reserved Hdefine UCTR 0x10 Transmit Receive Select Flag define UCTXNACK 0x08 Transmit NACK define UCTXSTP 0x04 Transmit STOP define UCTXSTT 0x02 Transmit START Hdefine UCSSEL O 0x00 USCI 0 Clock Source 0 Hdefine UCSSEL 1 0x40 USCI 0 Clock Source 1 Hdefine UCSSEL 2 0x80 USCI 0 Clock Source 2 Hdefine UCSSEL 3 OxCO USCI 0 Clock Source 3 Hdefine UCSSEL UCLK 0x00 USCI 0 Clock Source UCLK define UCSSEL ACLK 0x40 USCI 0 Clock Source ACLK define UCSSEL SMCLK 0x80 USCI 0 Clock Source SMCLK UCAxMCTL Control Bits Page 258 define UCBRF3 define UCBRF2 define UCBRF1 define UCBRFO define UCB
200. rs TT RK RE RACER EA REE E ER define MSP430 HAS PORTS Definition to show that Module is available define MSP430 BASEADDRESS 5 0 0240 define MSP430 HAS PORT6 Definition to show that Module is available tidefine MSP430 BASEADDRESS PORT6 0x0240 define MSP430 HAS PORTC R Definition to show that Module is available Hdefine 5 430 BASEADDRESS PORTC 0 0240 Page 163 SFR_16BIT PCIN SFR_8BIT PCIN_L SFR_8BIT PCIN_H SFR_16BIT PCOUT SFR_8BIT PCOUT_L SFR_8BIT PCOUT_H SFR_16BIT PCDIR SFR_8BIT PCDIR_L SFR_8BIT PCDIR_H SFR_16BIT PCREN SFR_8BIT PCREN_L SFR_8BIT PCREN_H SFR_16BIT PCDS SFR_8BIT PCDS_L SFR_8BIT PCDS_H SFR_16BIT PCSEL SFR_8BIT PCSEL_L SFR_8BIT PCSEL_H Hdefine 5 Hdefine define P5DIR define PSREN Page 164 Port C Input Port C Input Port C Input Port C Output Port C Output Port C Output Port C Direction Port C Direction Port C Direction Port Resistor Enable Port C Resistor Enable Port Resistor Enable Port Resistor Drive Strenght Port C Resistor Drive Strenght Port Resistor Drive Strenght Port C Selection Port C Selection Port C Selection Port 5 Input PCOUT L Port 5 Output Port 5 Direction 1 Port 5 Resistor Enable
201. rt 4 pins to output DEFINE WAIT TIME number of cycles before display wait ends HDEFINE P9 NO PINS 0x0 clear all display pins in port 9 DEFINE P4_NO_PINS OxFFE7 use to clear all display pins in port 4 Hendif DISPLAY_H_ Page 28 display c Created on Jun 4 2012 Author Josh Fromm This file contains the function used to initialize the bar panel LED display used in the BioSleeve system Table of Contents 1 display_init void display_init sets up the registers needed for the CPU to interact with the system s LED display 2 display_wait void display_wait holds for a set amount of time and is used for calibration 3 clear_display void clears the display include display h include lt msp430f5335 h gt display_init takes no inputs and has no outputs The function sets up the the ports needed to interact with the display by appropriately selecting their function and direction void display_init void Page 29 initialize port 9 and 4 to interact with the display P9SEL P9IO_SEL all pins set to digital I O P9DIR P9 OUT SEL direction set to output PASEL amp 4 SEL change only needed pins in port 4 P4DIR P4 OUT SEL set control registers to output return display_wait waits WAIT_TIME cycles before returning This function is used during accelerometer calibr
202. rt J Output SFR SBIT PJOUT Port J Output SFR 16BIT PJDIR Port J Direction SFR 8BIT PJDIR 1 Port Direction SFR 8BIT PJDIR HI Port J Direction SFR 16BIT PJREN Port Resistor Enable SFR 8BIT PJREN 1 Port J Resistor Enable SFR 8BIT PJREN Port J Resistor Enable SFR 16BIT PJDS Port J Resistor Drive Strenght SFR 8BIT PJDS L Port J Resistor Drive Strenght SFR 8BIT PJDS H Port J Resistor Drive Strenght SERATE TE ERO EEE ER E EEE E REE E EE EEE EE PORT MAPPING CONTROLLER Hdefine__MSP430_HAS_PORT_MAPPING__ Definition to show that Module is available define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0 Page 169 SFR_16BIT PMAPKEYID Port Mapping Key register SFR_8BIT PMAPKEYID_L Port Mapping Key register SFR_8BIT PMAPKEYID_H Port Mapping Key register SFR_16BIT PMAPCTL Port Mapping control register SFR_8BIT PMAPCTL_L Port Mapping control register SFR_8BIT PMAPCTL_H Port Mapping control register define PMAPKEY 0 2052 Port Mapping Key define PMAPPWD PMAPKEYID Legacy Definition Mapping Key register define PMAPPW 0x2D52 Legacy Definition Port Mapping Password PMAPCTL Control Bits ttdefine PMAPLOCKED 0x0001 Port Mapping Lock bit Read only ttdefine PMAPRECFG 0x0002 Port Mapping re configuration control bit PMAPCTL Con
203. rupt Flag define ADC121FG14 0x0040 ADC12 Memory 14 Interrupt Flag define ADC121FG15 H 0x0080 ADC12 Memory 15 Interrupt Flag ADC12IV Definitions define ADC121V NONE 0x0000 No Interrupt pending define ADC12IV ADC120VIFG 0 0002 ADC120VIFG define ADC12IV ADC12TOVIFG 0x0004 ADC12TOVIFG define ADC12IV ADC121FGO 0x0006 ADC12IFGO define ADC12IV_ADC12IFG1 0x0008 ADC12IFG1 ADC12IV ADC121FG2 0x000A ADC12IFG2 ADC12IV ADC121FG3 ADC12IFG3 define ADC12IV ADC121FG4 0 000 ADC12IFG4 define ADC12IV_ADC12IFG5 0 0010 ADC12IFG5 ADC12IV_ADC12IFG6 0x0012 ADC12IFG6 define ADC12IV_ADC12IFG7 0x0014 ADC12IFG7 define ADC12IV_ADC12IFG8 0x0016 ADC12IFG8 define ADC12IV ADC121FG9 0x0018 ADC12IFG9 define ADC12IV_ADC12IFG10 0 001 ADC12IFG10 define ADC12IV ADC121FG11 0x001C ADC12IFG11 define ADC12IV ADC121FG12 0 001 ADC12IFG12 define ADC12IV ADC121FG13 0x0020 ADC12IFG13 define ADC12IV_ADC12IFG14 0x0022 ADC12IFG14 define ADC12IV ADC121FG15 0x0024 ADC12IFG15 Page 92 ER OE E ET ER E ee ote Backup RAM Module RETREAT SETE EE EEE EEEE E define 5 430 HAS BACKUP_RAM__ Definition to show that Module is available define MSP430_BASEADDRESS_BACKUP_RAM
204. sed to facilitate the ball blasters infinity game which communicates with a BioSleeve board over wifi Movements of the BioSleeve s accelerometer allow a player to move blue dot in the ball blasters play environment Every fixed time interval both a large red and small green ball spawn in the play environment If th player controlled blue ball impacts a green ball a point is gained and added to the score at at the top left of the environment If a collision with a red ball occurs the game and score are reset import socket used for wifi data transmission import time used to generate random numbers import random also used to generate random numbers import math used for math stuff boundaries and constants create boundaries for the playing environment x min 0 0 y min 0 0 Page 59 x max 400 0 max 300 0 initial position of blue ball is the middle of the board x_pos x_max 2 2 y_pos 2 2 set speed of blue ball x 8 8 set size of red balls ball_rad 20 set size of green balls pointball_rad 10 set speed of red balls max_speed 10 set speed of green balls point_speed 5 create list of red balls Page 60 balls create list of green balls pointballs create count used to determine when to add new balls count 0 keep track of score score 0 set size of player ball b
205. sfer select 21 USCIA1 transmit define DMA3TSEL_22 22 0x0100u DMA channel 3 transfer select 22 USCIB1 receive define DMA3TSEL_23 23 0x0100u DMA channel 3 transfer select 23 USCIB1 transmit define DMA3TSEL_24 24 0x0100u DMA channel 3 transfer select 24 ADC12IFGx define DMA3TSEL_25 25 0x0100u DMA channel 3 transfer select 25 DAC12 OIFG define DMA3TSEL_26 26 0x0100u channel 3 transfer select 26 DAC12 1IFG define DMA3TSEL__RES27 27 0x0100u DMA channel 3 transfer select 27 Reserved Hdefine DMA3TSEL__RES28 28 0x0100u DMA channel 3 transfer select 28 Reserved define DMA3TSEL_29 29 0x0100u DMA channel 3 transfer select 29 Multiplier ready define DMA3TSEL_30 30 0x0100u DMA channel 3 transfer select 30 previous DMA channel DMA2IFG define DMA3TSEL_31 31 0x0100u DMA channel 3 transfer select 31 ext Trigger DMAEO define DMA4TSEL 0 0 0x0001u DMA channel 4 transfer select 0 DMA_REQ sw define DMA4TSEL_1 1 0x0001u channel 4 transfer select 1 TimerO A TAOCCRO IFG Page 129 define DMAATSEL_2 TAOCCR2 IFG define DMAATSEL_3 TA1CCRO IFG define DMAATSEL 4 TA1CCR2 IFG define DMAATSEL 5 TA2CCRO IFG define DMAATSEL 6 TA2CCR2 IFG Hdefine DMAATSEL_7 TBOCCRO IFG Hdefine DMAATSEL_8 TBOCCR2 IFG Hdefine DMA4TSEL_9 Hdefine DMA4TSEL_10 Hdefine DMA4TSEL_1
206. sumed 32KHz define WDT_ARST_1000 WDTPW WDTCNTCL WDTSSELO WDTIS2 1000ms define WDT_ARST_250 WDTPW WDTCNTCL WDTSSELO WDTIS2 WDTISO T 250ms Hdefine WDT ARST 16 WDTPW WDTCNTCL WDTSSELO WDTIS2 WDTIS1 16ms define WDT_ARST_1_9 WDTPW WDTCNTCL WDTSSELO WDTIS2 WDTIS1 WDTISO 1 9ms ER E RETE E O EER EC TLV Descriptors a E e define MSP430 HAS Definition to show that Module is available define TLV_START Ox1A08 Start Address of the TLV structure Page 272 define define LDTAG define TLV_PDTAG define TLV_Reserved3 define TLV_Reserved4 define TLV_BLANK define TLV_Reserved6 define TLV_Reserved7 define DIERECORD Hdefine ADCCAL define TLV_ADC12CAL define TLV_ADC10CAL define TLV_REFCAL define TLV_TAGEXT define TLV_TAGEND Ox1AFF Address of the TLV structure 0 01 Legacy descriptor 1xx 2xx 4xx families 0 02 Peripheral discovery descriptor 0x03 Future usage 0 04 Future usage 0 05 Blank descriptor 0 06 Future usage 0x07 Serial Number 0 08 Die Record 0x11 ADC12 calibration 0x11 ADC12 calibration 0x13 ADC10 calibration 0x12 REF calibration OxFE Tag extender OxFF Tag End of Table JER ERE KE JR
207. t 0 9 32 Comp Int Ref 1 Select 1 10 32 Comp B Int Ref 1 Select 2 11 32 Comp B Int Ref 1 Select 3 12 32 Comp B Int Ref 1 Select 4 13 32 Comp B Int Ref 1 Select 5 14 32 Comp B Int Ref 1 Select 6 15 32 Comp B Int Ref 1 Select 7 16 32 Comp Int Ref 1 Select 0 17 32 Comp B Int Ref 1 Select 1 18 32 Comp B Int Ref 1 Select 2 19 32 define CBREF1 19 define CBREF1_20 define CBREF1_21 define CBREF1_22 define CBREF1_23 define CBREF1_24 define CBREF1_25 define CBREF1_26 define CBREF1_27 define CBREF1_28 define CBREF1_29 define CBREF1_30 define CBREF1_31 define CBREFL_0 define CBREFL_1 define CBREFL_2 define CBREFL_3 define CBPDO define CBPD1 define CBPD2 define CBPD3 define CBPD4 Page 106 0x1300 0x1400 0x1500 0x1600 0x1700 0x1800 0 1900 0 1 00 0 1 00 0x1C00 0 1000 0 1 00 0 1 00 0 0000 0x2000 0x4000 0x6000 0 0001 0 0002 0 0004 0x0008 0x0010 Comp B Int Ref 1 Select 3 20 32 Comp Int Ref 1 Select 4 21 32 Comp Int Ref 1 Select 5 22 32 Comp B Int Ref 1 Select 6 23 32 Comp B Int Ref 1 Select 7 24 32 Comp B Int Ref 1 Select 0 25 32 Comp B Int Ref 1 Select 1 26 32 Comp Int Ref 1 Select 2 27 32 Comp B Int Ref 1 Select 3 28 32
208. t P2 1 mapping register Port P2 2 mapping register Port P2 3 mapping register Port P2 4 mapping register Port P2 5 mapping register define P2MAP6 define P2MAP7 define PM_NONE define PM_CBOUT define PM_TBOCLK define PM_ADC12CLK define PM_DMAEO define PM_SVMOUT define PM_TBOOUTH define PM_TBOCCROB define PM_TBOCCR1B define PM_TBOCCR2B define PM_TBOCCR3B define PM_TBOCCR4B define PM_TBOCCR5B define PM_TBOCCR6B define PM_UCAORXD define PM_UCAOSOMI define PM_UCAOTXD define PM_UCAOSIMO define PM_UCAOCLK define PM_UCBOSTE define PM_UCBOSOMI Page 172 P2MAP67_L P2MAP67_H 10 11 11 12 12 13 13 14 Port P2 6 mapping register Port P2 7 mapping register define PM_UCBOSCL 14 define PM_UCBOSIMO 15 define PM_UCBOSDA 15 define PM_UCBOCLK 16 define PM_UCAOSTE 16 define PM_MCLK 17 define PM EO 18 define EI 19 define ANALOG 31 ESA ERRE KE RKE A PMM Power Management System EEE CEE RE ORE EN ER TE e RR ee TE E E TRE e ERRE define MSP430 HAS PMM__ Definition to show that Module is available define MSP430_BASEADDRESS_PMM__ 0x0120 SFR_16BIT PMMCTLO PMM Control 0 SFR_8BIT PMMCTLO_L PMM Control 0 SFR_8BIT PMMCTLO_H PMM Control O SFR_16BIT PMMCTL1 PMM Control 1 SFR_8BIT PMMCTL1_L PMM Control 1 SFR_8BIT PMMCTL1_H
209. t operand 1 signed multiply high word 32 bit operand 1 signed multiply high word 32 bit operand 1 signed multiply high word 32 bit operand 1 multiply accumulate low word 32 bit operand 1 multiply accumulate low word 32 bit operand 1 multiply accumulate low word 32 bit operand 1 multiply accumulate high word 32 bit operand 1 multiply accumulate high word 32 bit operand 1 multiply accumulate high word 32 bit operand 1 signed multiply accumulate low 32 bit operand 1 signed multiply accumulate low SFR_8BIT MACS32L_H word SFR_16BIT MACS32H word SFR_8BIT MACS32H_L word SFR_8BIT MACS32H_H word SFR_16BIT OP2L SFR_8BIT OP2L_L SFR_8BIT OP2L_H SFR_16BIT OP2H SFR_8BIT OP2H_L SFR_8BIT OP2H_H SFR_16BIT RESO SFR_8BIT RESO_L SFR_8BIT RESO_H SFR_16BIT RES1 SFR_8BIT RES1_L SFR_8BIT RES1_H SFR_16BIT RES2 SFR_8BIT RES2_L SFR_8BIT RES2_H SFR_16BIT RES3 SFR_8BIT RES3_L SFR_8BIT RES3_H Page 153 32 bit 1 signed multiply accumulate low 32 bit operand 1 signed multiply accumulate high 32 operand 1 signed multiply accumulate high 32 bit operand 1 signed multiply accumulate high 32 bit operand 2 low word 32 bit operand 2 low word 32 bit operand 2 low word 32 bit operand 2 high word 32 bit ope
210. terrupt enable define SVMHVLRIE L 0x0040 SVM high side Voltage Level Reached interrupt enable PMMIE and RESET Control Bits Hdefine SVSLPE H 0x0001 SVS low side POR enable define SVMLVLRPE H 0x0002 SVM low side Voltage Level reached POR enable define SVSHPE H 0x0010 SVS high side POR enable define SVMHVLRPE H 0x0020 SVM high side Voltage Level reached POR enable 5 Power Mode 5 Control Bits define LOCKLPM5 0x0001 Lock I O pin configuration upon entry exit to from LPM5 PMSCTLO Power Mode 5 Control Bits define LOCKLPM5 1 0x0001 Lock I O pin configuration upon entry exit to from LPM5 5 Power Mode 5 Control Bits Page 184 define LOCKIO LOCKLPM5 Lock pin configuration upon entry exit to from LPM5 dE EE KE EET iii Port U OR RO RAEE RE ER E define MSP430 HAS PU Definition to show that Module is available define MSP430_BASEADDRESS_PU__ 0x0900 M SFR_16BIT LDOKEYPID LDO Controller peripheral ID and key register SFR_8BIT LDOKEYPID_L LDO Controller peripheral ID and key register SFR_8BIT LDOKEYPID_H LDO Controller peripheral ID and key register SFR_16BIT PUCTL PU Control register SFR_8BIT PUCTL_L PU Control register
211. the CPU for conversion to a digital signal The digital signal is then converted to a magnitude form by the CPU before being sent to the display When connected to the user s arm the electrode array allows the user to see electrical activity due to muscle contractions Accelerometer The system uses an ADXL335 accelerometer to measure the tilt of the accelerometer glove and control the player s ball in Ball Blasters Infinity The accelerometer produces 3 analog voltages that correspond to the tilt of the accelerometer one signal for each of the 3D axes The analog signals are converted to digital signals by ADC12 pins The CPU then determines if the signals indicate the accelerometer is sufficiently tilted from the calculated zero position to warrant sending a command string over wifi which results in the player Page 12 ball moving in the Ball Blasters Infinity game The accelerometer is attached to the finger of a glove for the players comfort Wifi Module The system uses a WiFly RN 131C wifi module to transfer data wirelessly The CPU communicates with the wifi module through two wire UART interface at a baud rate of 9600 set by the wifi module Communication between the CPU and wifi module is done through the transmission of ASCII characters or strings The CPU is able to both send and receive strings via UART When the wifi module receives a full string it sends it to any devices connected to its adhoc network if the adhoc jum
212. tick them to the user s arm It should be noted that it is not necessary to use the electrode array when playing Ball Blasters Infinity 3 The component labeled 3 is the system s wifi module The user only needs to know that it isimportant to keep loose wires or other conductive material away from the module as it will interfere with data transmission 4 The component labeled 4 is the system s LED display The display serves two distinct purposes The first is displaying the loading time of a calibration sequence When a calibration sequence is initiated the LED display will clear and display a loading bar sequence over the next few seconds During this time the user should not move the accelerometer glove or calibration will be unsuccessful When the system is not calibrating the LED display samples the data read from the electrodes and displays a magnitude form of it This allows the user to see how much muscle action is being measured through the electrode array component 2 5 The components labeled 5 are the system s charging jacks The left charging jack accepts a standard barrel jack When using a barrel jack the system will be able to both charge the battery and run off the jack power The right jack is a USB 3 0 jack It should be noted that the USB jack will only charge the battery it does not supply power to the system and therefore it is recommended to use a barrel jack if both options are available 6 The component labeled
213. tiply accumulate low word Byte Access define MAC32H_B MAC32H_L 32 bit operand 1 multiply accumulate high word Byte Access define MACS32L_B MACS32L 32 bit operand 1 signed multiply accumulate low word Byte Access define 532 MACS32H L 32 bit operand 1 signed multiply accumulate high word Byte Access define OP2L_B OP2L_L 32 bit operand 2 low word Byte Access Page 154 define 2 OP2H 1 32 bit operand 2 high word Byte Access MPY32CTLO Control Bits define MPYC 0x0001 Carry of the multiplier ttdefine RESERVED 0x0002 Reserved define MPYFRAC 0x0004 Fractional mode define MPYSAT 0x0008 Saturation mode define MPYMO 0x0010 Multiplier mode Bit 0 define MPYM1 0x0020 Multiplier mode Bit 1 define OP1 32 0x0040 Bit width of operand 1 0 16Bit 1 32Bit define OP2 32 0x0080 Bit width of operand 2 0 16Bit 1 32Bit define MPYDLYWRTEN 0x0100 Delayed write enable define MPYDLY32 0x0200 Delayed write mode MPY32CTLO Control Bits ttdefine MPYC L 0x0001 Carry of the multiplier ttdefine RESERVED 0x0002 Reserved define MPYFRAC L 0x0004 Fractional mode define L 0x0008 Saturation mode define L 0x0010 Multiplier mode Bit 0 define MPYM1 L 0x0020 Multiplier mode Bit 1
214. trol Bits ttdefine PMAPLOCKED L 0x0001 Port Mapping Lock bit Read only ttdefine PMAPRECFG L 0x0002 Port Mapping re configuration control bit PMAPCTL Control Bits PORRE EO GIO OO Re PORT 2 MAPPING CONTROLLER Page 170 E EEE EE e OR AE e E e Io OS define _MSP430_HAS_PORT2_MAPPING__ Definition to show that Module is available define MSP430 BASEADDRESS PORT2 MAPPING Ox01DO SFR 16BIT P2MAPO1 SFR 8 1 SFR 8BIT P2MAPO1 SFR 16BIT P2MAP23 SFR 8BIT P2MAP23 1 SFR 8BIT P2MAP23 SFR 16 2 45 SFR 8BIT P2MAPA5 1 SFR 8BIT P2MAP45 SFR 16BIT P2MAP67 SFR 8BIT P2MAP67 1 SFR 8BIT P2MAP67 Hl define define define define define define P2MAPO P2MAP1 P2MAP2 P2MAP3 P2MAP4 P2MAP5 Page 171 Port P2 0 1 mapping register Port P2 0 1 mapping register Port P2 0 1 mapping register Port P2 2 3 mapping register Port P2 2 3 mapping register Port P2 2 3 mapping register Port P2 4 5 mapping register Port P2 4 5 mapping register Port P2 4 5 mapping register Port P2 6 7 mapping register Port P2 6 7 mapping register Port P2 6 7 mapping register P2MAPO1_L P2MAPO1 H P2MAP23 L P2MAP23 H P2MAP45_L P2MAP45_H Port P2 0 mapping register Por
215. ue ball to move down tilting left will move the blue ball left and tilting right will move the blue ball right It should also be noted that any combination of two directions will cause diagonal movement If directional movement is not satisfactory a recalibration is recommended 11 Component 11 is a jumper which determines whether the wifi module is in adhoc or standard mode If the wifi module has been configured for the user s wireless network standard mode is highly recommended and the jumper should be taken out However if the wifi module has not been configured it must be set to adhoc mode by putting the jumper into place In adhoc mode the wifi module will create its own network which must be connected to by the computer that the user wishes to play Ball Blasters Infinity on To play Ball Blasters Infinity the user should first optionally attach the electrode array to his or her arm Next the user is recommended to put on the accelerometer glove and hold his her finger in the desired zero position Next the user should turn the system on via the power switch The display will then enter calibration mode and begin displaying a loading bar During this period the user should not move his her finger Once the loading bar has cleared the user should boot up Ball Blasters Infinity by double clicking on the desktop icon This will cause the game to be loaded It should be noted that the computer running Ball Blasters Infinity must be on the s
216. urce Select Bit 0 ACLK Source Select Bit 1 ACLK Source Select Bit 2 RESERVED RESERVED define RESERVED 0 2000 RESERVED define RESERVED 0 4000 RESERVED define RESERVED 0x8000 RESERVED define SELM_0 0x0000 MCLK Source Select 0 define SELM_1 0x0001 Source Select 1 define SELM_2 0x0002 Source Select 2 define SELM_3 0x0003 Source Select 3 define SELM_4 0x0004 Source Select 4 define SELM_5 0x0005 Source Select 5 define SELM_6 0x0006 Source Select 6 define SELM_7 0x0007 Source Select 7 define SELM__XT1CLK 0x0000 Source Select XT1CLK define SELM__VLOCLK 0x0001 Source Select VLOCLK define SELM__REFOCLK 0x0002 Source Select REFOCLK define SELM__DCOCLK 0x0003 Source Select DCOCLK define SELM__DCOCLKDIV 0x0004 MCLK Source Select DCOCLKDIV define SELM__XT2CLK 0x0005 MCLK Source Select XT2CLK Hdefine SELS 0 0x0000 SMCLK Source Select 0 Hdefine SELS 1 0x0010 SMCLK Source Select 1 Hdefine SELS 2 0x0020 SMCLK Source Select 2 Hdefine SELS 3 0x0030 SMCLK Source Select 3 Hdefine SELS 4 0x0040 SMCLK Source Select 4 Page 241 define 5 15 5 0x0050 5 Source Select 5 define SELS_6 0x0060 SMCLK Sou
217. us LEDs External Accelerometer Glove Using ADXL335 Accelerometer External LP 063450 100mAh Rechargeable Electrode Port 1 Battery Electrode Port 2 External Electrode Array Electrode Port 3 Electrode Port 4 Electrode Port 5 7900 00 mil gt Page 10 CPU Clock Logic Reset Logic and Power This subsection covers the interactions of the CPU clock logic reset logic and power setup used in the BioSleeve system CPU The system uses an MSP430F5335 CPU The CPU is designed to have many multifunctional separate ports which interact with peripherals The CPU of the system has its JTAG pins extended to a header which allows a JTAG debugger to connect to the CPU Clock Logic The system s clock logic is handled primarily inside the CPU which uses an adjustable PLL to control the system s clock frequency The system uses an external 32 kilohertz crystal as reference for the PLL which can be seen on the board layout The internal PLL of the system is set up via code to generate a 2 15 megahertz master clock Reset Logic The system uses a MAX809S chip and normally closed single pole single throw switch to handle resets When the MAX809S detects a drop in voltage passed a preset threshold 2 93 V it sets the reset signal low active This means that the system will be held in reset if the battery runs too low The VCC pin of the MAX809S is connected to a normally closed switch which is connected to VCC Th
218. ve Level mode Bit O define XT1DRIVE1 0x0080 Drive Level mode Bit 1 define XT2OFF 0 0100 Frequency Oscillator 2 XT2 disable define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define XT2BYPASS 0x1000 2 bypass mode 0 internal 1 sourced from external pin define RESERVED 0x2000 RESERVED define XT2DRIVEO 0x4000 2 Drive Level mode Bit O Page 247 define XT2DRIVE1 0x8000 2 Drive Level mode Bit 1 UCSCTL6 Control Bits define 1 0x0001 High Frequency Oscillator 1 XT1 disable define SMCLKOFF_L 0x0002 SMCLK Off define XCAPO_L 0 0004 XIN XOUT Bit 0 define XCAP1_L 0 0008 XIN XOUT Bit 1 Hdefine XT1BYPASS 1 0x0010 XT1 bypass mode 0 internal 1 sourced from external pin define XTS 1 0x0020 1 Selects high freq oscillator define L 0x0040 XT1 Drive Level mode Bit 0 define XT1DRIVE1_L 0x0080 Drive Level mode Bit 1 define RESERVED 0x0200 RESERVED define RESERVED 0x0400 RESERVED define RESERVED 0x0800 RESERVED define RESERVED 0x2000 RESERVED UCSCTL6 Control Bits define 2 0x0001 High Frequency Oscillator 2 XT2 disable define RESERVED 0x0200 RESERVED defin
219. vider f LFCLK 2 Hdefine FLLREFDIV 4 0x0002 Reference Divider f LFCLK A Hdefine FLLREFDIV 8 0x0003 Reference Divider f LFCLK 8 define FLLREFDIV 12 0x0004 Reference Divider f LFCLK 12 Hdefine FLLREFDIV 16 0x0005 Reference Divider f LFCLK 16 Hdefine SELREF 0 0x0000 FLL Reference Clock Select O Hdefine SELREF 1 0x0010 FLL Reference Clock Select 1 Hdefine SELREF 2 0x0020 FLL Reference Clock Select 2 Hdefine SELREF 3 0x0030 FLL Reference Clock Select 3 Hdefine SELREF 4 0x0040 FLL Reference Clock Select 4 Page 238 define SELREF_5 0x0050 FLL Reference Clock Select 5 define SELREF_6 0x0060 FLL Reference Clock Select 6 define SELREF_7 0x0070 FLL Reference Clock Select 7 define SELREF__XT1CLK 0x0000 Multiply Selected Loop Freq By XT1CLK define SELREF__REFOCLK 0x0020 Multiply Selected Loop Freq By REFOCLK define SELREF__XT2CLK 0x0050 Multiply Selected Loop Freq By XT2CLK UCSCTL4 Control Bits define SELMO 0x0001 Source Select Bit O define SELM1 0x0002 Source Select Bit 1 define SELM2 0x0004 Source Select Bit 2 define RESERVED 0x0008 RESERVED define SELSO 0x0010 SMCLK Source Select Bit O Hdefine SELS1 0x0020 SMCLK Source Select Bit 1 Hdefine SELS2 0x0040 SMCLK Source Select Bit 2 defin

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