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STMicroelectronics STM8S207RBT6 datasheet: pdf

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1. Q Q 9 x s z T Y Li oOo ugs z fap E 8F fo 5 O55 DH ie XX daezeuo z Or Y OO Se E 22222551m EES E e e e 00000 SS ES2OLLLLLIEEE ROI 4o0oN Oo0 uqwoOsnoO 9 QGGdOd82d02anbdmu l uu uoc aaaaaaaaoaaaaaad 64 63 62 61 60 59 58 57 56 55 54 53 52 51 5049 NRSTO 160 48 PIO OSCIN PA1 O 2 47 PG4 OSCOUT PA2 3 46 O PG3 Vssio 114 45 O PG2 Vss O05 44 O PG1 CAN_RX VCAP 0 6 43 PGO CAN TX Von 07 42 1 PC7 HS SPI_MISO Vppio 1 O 8 41 D PC6 HS SPI_MOSI TIM3_CH1 TIM2 CH3 PAS O 9 40 H Vppio 2 UART1_RX HS PA4 O 10 39 D Vggio 2 UART1 TX HS PA5 O 11 38 PC5 HS SPI SCK UART1_CK HS PA6 O 12 37 PC4 HS TIM1_CH4 AIN15 PF7 O 13 36 PC3 HS TIM1_CH3 AIN14 PF6 O 14 35 PC2 HS TIM1 CH2 AIN13 PF5 O 15 34 O PC1 HS TIM1 CH1 AIN12 PF4 O 16 33 PE5 SPI_LNSS N 7 18 19 20 21 22 23 24 25 26 27 28 29 3031 32 oO tr uk XC 10 st CO oct wo 9 jg m mea dmeammm uu C c T00000000000 gt FHFSRGHUTHAAH SHS Seze2e222222 SE TEEEES o 0i LILI o Q 9 9 9 AAF co pz2c EE TIM1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented
2. HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy ky Doc ID 14733 Rev 8 63 101 Electrical characteristics STM8S207xx STM8S208xx Table 31 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit em Sisi speed oscillator 4 24 MHz Rr Feedback resistor 220 kQ c Recommended load capacitance 20 pF C 20 pF 6 startup fosc 24 MHz 2 stabilized Ipp HSE HSE oscillator power consumption C 10 pF 6 Bee mA fosc 24 MHz stabilized Om Oscillator transconductance 5 mA V tsuHse Startup time Vpp is stabilized 1 ms C is approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details Data based on characterization results not tested in production sU HSE is the start up time measured from t
3. Table 9 General hardware register map continued Address Block Register label Register name Ware 00 5200h SPI CR1 SPI control register 1 0x00 00 5201h SPI CR2 SPI control register 2 0x00 00 5202h SPI ICR SPI interrupt control register 0x00 00 5203h SPI SR SPI status register 0x02 00 5204h xd SPI DR SPI data register 0x00 00 5205h SPI CRCPR SPI CRC polynomial register 0x07 00 5206h SPI RXCRCR SPI Rx CRC register OxFF 00 5207h SPI TXCRCR SPI Tx CRC register OxFF deeds Reserved area 8 bytes 00 5210h DC CR1 DC control register 1 0x00 00 5211h DC CH3 UC control register 2 0x00 00 5212h I2C FREQR DC frequency register 0x00 00 5213h I2C_OARL I C own address register low 0x00 00 5214h 12C_OARH DC own address register high 0x00 00 5215h Reserved 00 5216h GC DR DC data register 0x00 00 5217h Pc GC SR1 DC status register 1 0x00 00 5218h DC SR2 DC status register 2 0x00 00 5219h IOC SR3 DC status register 3 0x00 00 521Ah IOC ITR DC interrupt control register 0x00 00 521Bh I2C CCRL DC clock control register low 0x00 00 521Ch I2C CCRH DC clock control register high 0x00 00 521Dh I2C_TRISER DC TRISE register 0x02 00 521Eh IOC PECH DC packet error checking register 0x00 RE Reserved area 17 bytes 38 101 Doc ID 14733 Rev 8 Ier STM8S207xx STM8S208xx Memory and register map Table 9 Gener
4. Symbol Ratings Value Unit Ter Storage temperature range 65 to 150 Se Ty Maximum junction temperature 150 ky Doc ID 14733 Rev 8 53 101 Electrical characteristics STM8S207xx STM8S208xx 9 3 Operating conditions Table 17 General operating conditions Symbol Parameter Conditions Min Max Unit TA 105 C 0 24 MHz fopu Internal CPU clock frequency T ee Vpp Vpp 1o Standard operating voltage 2 95 5 5 V Cext VCAP external capacitor 0 05 lt ESR lt 0 2Qat1MHz 470 3300 nF 44 48 64 and 80 pin devices with output on 8 standard ports 2 high sink 443 Power dissipation at ports and 2 D drain ports Pp Ta 85 C for suffix 6 simultaneously mW or Ta 125 C for suffix 3 32 pin package with output on 8 standard ports and 2 high sink ports 369 simultaneously Ambient temperature for 6 Maximum power dissipation 40 85 suffix version Low power dissipation 40 105 A Ambient temperature for 3 Maximum power dissipation 40 125 e suffix version Low power dissipation 40 140 6 suffix version 40 105 Tj Junction temperature range 3 suffix version 40 1300 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 2 To calculate Pp TA use the formula Ppmax T jmax Ta Qya see Section 10 2 Thermal characteristics on page 94 with
5. 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Package characteristics 10 2 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 49 STM8S207xx 208xx performance line ordering information scheme 1 on page 96 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tamax 82 C measured according to JESD51 2 e IpDmax 15 mA Vpp 5 5V e Maximum eight standard I Os used at the same time in output at low level with Io 10 mA VoL 2V e Maximum four high sink I Os used at the same time in output at low level with lo 20 mA VoL 1 5V e Maximum two true open drain I Os used at the same time in output at low level with lot 20 mA VoL 2V PiNTmax 15 mA x 5 5 V 82 5 mW Piomax 10 MA x 2 V x 8 20 mA x 2 V x 2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 mW and Pigmax 360 mW Ppmax 82 5 mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 56 Thermal characteristics on page 94 T jmay is calculated as fol
6. 20 Oct 2008 5 Changed Vpp minimum value from 3 0 to 2 95 V Updated number of High Sink I Os in pinout Removed FLASH _NFPR and FLASH _FPR registers in Table 9 General hardware register map 08 Dec 2008 6 Removed preliminary status Removed VQFN32 package 30 Jan 2009 7 Added STM8S207C6 STM8S207S6 Updated external interrupts in Table 2 on page 1 1 Updated Section 9 Electrical characteristics Document status changed from preliminary data to datasheet Added LQFP64 14 x 14 mm package Added STM8S207M8 STM8S207SB STM8S208R8 STM8S208R6 STM8S208C8 and STM8S208C6 STM8S208SB STM8S208S8 and STM8S208S6 Replaced CAN with DeC AN 10 Jul 2009 8 Added Table 3 to Section 4 5 Clock controller Updated Section 4 8 Auto wakeup counter Added beCAN peripheral impacting Table 7 and Figure 6 Added footnote about CAN_RX TX to pinout figures 3 4 and 6 Table 6 Removed X from wpu column of I C pins no wpu available Added Table 11 Interrupt mapping d Doc ID 14733 Rev 8 99 101 Revision history STM8S207xx STM8S208xx 100 101 Table 57 Document revision history continued Date 10 Jul 2009 Revision cont d Changes Section 9 Electrical characteristics Added data for TBD values updated Table 14 Voltage characteristics and Table 17 General operating conditions updated VCAP specifications in Table 17 and in Section 9 3 1 VCAP e
7. 5 5 8 B C 3 option bit lf ffe ffe ffe UOI Sr x ui 42 POUADC ETR volx x x O1 X X PortCO m Timer 1 43 34 26 24 18 PC1 TIM1_CH1 I O X X X HS OS3 X X Port C1 channel 1 Timer 1 44 35 27 25 19 PC2 TIM1_CH2 O X X X HS OS3 X X Port C2 channel 2 Timer 1 45 36 28 26 20 PC3 TIM1_CH3 I O X X X HS OS3 X X Port C3 channel 3 Timer 1 46 37 29 21 PC4 TIM1_CH4 O X X X HS OS X X Port CA channel 4 47 38 30 27 22 PC5 SPI_SCK lO X X X HS OS X X Port C5 SPI clock 48 39 31 28 Vssio 2 S UO ground 49 40 32 29 Vppio 2 S I O power supply SPI master 50 41 33 30 23 PC6 SPILMOSI I O X X X HS OS X X Port C6 out slave in 51 42 34 31 24 PC7 SPL Miso vol X X x HS O3 x x Port c7 SP master in slave out 52 43 35 32 PGO CAN TX O X X O1 X X Port GO beCAN transmit 53 44 36 33 PG1 CAN_RX O X X O1 X X Port G1 beCAN receive 54 45 PG2 O X X O1 X X Port G2 55 46 PG3 O X X 01 X X Port G3 56 47 PG4 O X X O1 X X Port G4 57 48 PIO VO X X O1 X X Portlo 58 IPI O X X O1 X X Por 59 Pl2 VOIX X O1 X X Port 12 60 IPIS VOIX X O1 X X Portl3 61 Pl4 O X X O1 X X Port 14 62 PI5 O X X O1 X X PortI5
8. SI RC osc 16 MHz 8 0 55 fopy fMASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN HSE crystal osc 24 MH 114 is cpu fuasTER 24 MHz crystal osc z Ta 105 C HSE user ext clock 24 MHz 10 8 18 7 HSE crystal osc 16 MHz 9 0 Supply 1 c rrentin fopu fuasrER 16 MHz HSE user ext clock 16 MHz 82 15 2 run mode HSI RC osc 16 MHz 81 13 21 code executed cpu faster 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fopy fyaster 128 125 kHz HSI RC osc 16 MHz 1 1 Ve fmastep 128 15 625 SI RC osc 16 MHz 8 0 6 fcpu MASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 56 101 D Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Electrical characteristics Table 20 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fcpu faster 24 MHz HSE crystal osc 24 MHz 4 0 TA 105 C HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 2 9 Supply S currenti fopy fmaster 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 cude ted HSE user ext clock 16 MHz 1 2 4 1 execute fopy faster 28 125 kHz from RAM HSI R
9. ACCus Von 5 V 3 2 9 25 C lt Ta lt 85 C S Accuracy of HSI oscillator vem S factory calibrated 2 95 V lt Vpp 5 5 V 40 2 ei 40 C lt Ta lt 125 C S eu t HSI oscillator wakeup 10 E su HS time including calibration H HSI oscillator power 2 opman consumption MM Bee p 1 Guaranteeed by design not tested in production 2 Data based on characterization results not tested in production Figure 18 Typical HSI frequency variation vs Vpp at 4 temperatures 40 C 3 4 a 25 C 85 C 2 125 C 1 0 Pumar a a 8 1 5 8 2 1 2 H1 2 3 T T T T T T d 2 5 3 3 5 4 4 5 5 5 5 6 Vpp V ai15067 Doc ID 14733 Rev 8 65 101 Electrical characteristics STM8S207xx STM8S208xx Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and T Table 33 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 110 128 146 kHz tsutsi ESI oscillator wakeup time 70 us Ipp Lsi LSI oscillator power consumption 5 UA 1 Guaranteeed by design not tested in production Figure 19 Typical LSI frequency variation vs Vpp 25 C 3 4 2 gt 1 196 2 3 T T T T T 1 2 5 3 3 5 4 5 5 5 5 6 Voo V ai15070 66 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Electrical characteristics 9 3 5 Memory characteristics RAM a
10. 3 3 V high sink ports gt Jop 25 C 1 75 85 C 15 4 125 C z 1 25 0 75 0 5 0 25 OF 1 14 lo mA 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 40 NRST pin characteristics Symbol Parameter Conditions Min Typ 1 Max Unit Vumpen NRST Input low level voltage 1 0 3 V 0 3 x Vpp Vuen NRST Input high level voltage 0 7 x Vpp Vpp 0 3 V Vorwnsr NRST Output low level voltage 1 loL 2 mA 0 5 Reuwrst NRST Pull up resistor 30 40 60 kO tep vast NRST Input filtered pulse 9 75 ns Nre NRsT NRST Input not filtered pulse 500 ns topwrst NRST output pulse UI 15 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vj vs Vpp 4 temperatures 40 C si 25 C i 85 C 125 C 4 E _ a 1 0 T T T T T T i 2 5 3 3 5 4 45 5 5 5 6 Voo V D 74 101 Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Electrical characteristics Figure 34 Typical NRST pull up resistance vs Vpp 4 temperatures NRESET pull up resistance OW 40 C 60 25 C 8
11. ECOPACK is an ST trademark ky Doc ID 14733 Rev 8 87 101 Package characteristics STM8S207xx STM8S208xx 10 1 10 1 1 88 101 Package mechanical data LQFP package mechanical data Figure 43 80 pin low profile quad flat package 14 x 14 D 61 80 Pin 1 identification 1 18 ME Table 50 80 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 220 0 320 0 380 0 0087 0 0126 0 0150 C 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 350 0 4862 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 350 0 4862 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 8 Si STM8S207xx STM8S208xx Package characteristics Figure 44 64 pin low profile quad flat package 14 x 14 D f D1 Q ccc C D3 Si AL A2 48 33 E du
12. alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function CAN RX and CAN TX is available on STM8S208xx devices only Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Pinouts and pin description d Figure 5 LQFP 48 pin pinout Q 9 x d 9 ra zZ l x Luo S H HgS E ZE E T N NO III IQ Oxx 99O Oona aaa oo KEE zJJ222z2X070x EE ER J GELHDDDDO DSSS EOSOgILTLILIIEEL Bhoosxoaua oo aso goaaoadaonou uiu u aaaaaaanaaoan g 48474645 444342 41 40 39 38 37 NRST H1 e 36LIPG1 OSCIN PA1 r12 35 PGO OSCOUT PA2 03 34L1 PC7 HS SPI MISO Vssio 1 4 33 0 PC6 HS SPI_MOSI Vss O05 320 Vppio_2 VCAP C16 310 Vssio 2 Vpp O7 300 PCS HS SPI SCK Vppio 1 48 290 PC4 HS TIM1_CH4 TIM3_CH1 TIM2_CH3 PA3 O9 287 PC3 HS TIM1 CH3 UART1_RX HS PA4 410 2717 PC2 HS TIM1_CH2 UART1_TX HS PAG 011 261 PC1 HS TIM1 CH1 UART1_CK HS PA6 012 25H PE5 SPI NSS Le esu Ee pnm oO st CO QN QO rn oO 9 m m dm mammam ww DOCLICLLOIOCcIOO T Q ios OQ Oo oo 2222222222 ss d d SSES S LEEE oo o 000 Eer F222 EEE 1 HS high sink capability 2
13. kyy STM8S207xx STM8S208xx Performance line 24 MHz STM8S 8 bit MCU up to 128 Kbytes Flash integrated EEPROM 10 bit ADC timers 2 UARTs SPI 12C CAN Features July 2009 Core Max fcopy Up to 24 MHz 0 wait states fopy lt 16 MHz Advanced STM8 core with Harvard architecture and 3 stage pipeline Extended instruction set Max 20 MIPS 24 MHz Memories Program memory Up to 128 Kbytes Flash data retention 20 years at 55 C after 10 kcycles Data memory Up to 2 Kbytes true data EEPROM endurance 300 kcycles RAM Up to 6 Kbytes Clock reset and supply management 2 95 to 5 5 V operating voltage Flexible clock control with 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Power management Wait active halt amp halt low power modes Peripheral clocks switched off individually Permanently active low consumption power on and power down reset Interrupt management Nested interrupt controller with 32 interrupts Upto 37 external interrupts on 6 vectors Timers 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit b
14. 63 49 PG5 VOIX X 01 X X Port G5 64 50 PG6 VOIX X O1 X X Port G6 65 51 PG7 O X X O1 X X Port G7 66 52 PE4 IO XII xX O1 X X Port E4 30 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Pinouts and pin description Table 6 Pin description continued Pin number Input Output oc 5 Alt t oco tiw Q Sx S Default Persii Seil uo Pin name E D EI EI a 3r alternate Ebr rs al s 2j gajal TS function remap G Gg o G 5 5 8 B C 3 option bit lf ffe ffe ffe UOI Sr Ei LL Timer 1 break 67 53 37 PES TIMi BKIN I O X X X O1 X X Port E3 DEn 68 54 38 34 PE2 2C_SDA_ l O X X O1 ml Port E2 I2C data 69 55 39 35 PE1 PC SCL VO X X 01 ml Port E1 2C clock 70 56 40 36 PEO CLK CCO lol X x x IHS O3 X X Port Eo C figurable clock output 71 IPI6 O X O1 Port l6 72 PIZ O X O1 Port I7 TIM1_BKIN Timer 3 AFR3 73 57 41 37 25 PDO TIM3 CH2 O X X X H5 O3 X X Port DO hannel 2 CLK CCO AFR2 74 58 42 38 26 PD1 SwiM vol x x X HSlo4 x X Port p1 EW data interface 75 59 43 39 27 PD2 TIM3 eu O X X X HS O8 X X Port n2 Ier TIME Da channel 1 AFR1 76 60 44 40 28 PD3 TIM2 CH2 O X X X HS O3 X X Port pa Timer 2 ADC ETR channel 2 AFRO PD4 TIM2_CH1
15. liliis 95 STM8 development tools llleee 96 Doc ID 14733 Rev 8 3 101 Contents STM8S207xx STM8S208xx 11 1 Emulation and in circuit debugging tools 96 11 2 Software tools caus duse Et red a tg teda ara dad Ra re x 97 11 21 STMB8toolset l lslslleeeee eens 97 11 2 2 C and assembly toolchains 97 11 3 Programming tools Zare oa KREE ERE EE ERES I RR Leen weaved 97 12 Ordering information uuu adus WA Rosana e CR ow do o dn RR CR Reg 98 13 Revision history osos saecu ANERE aca EE mara Rc 99 4 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky Device SUMMA ss 22a ha eae dedos Pe ae are Uh abs and ae EE 1 STM8S20xxx performance line features 11 Peripheral clock gating bit assignments in CLK PCKENR 1 2 registers 16 TIM timer features 19 Legend abbreviations 0 0 00 hrs 27 Pin description TER 28 Flash Data EEP
16. 20 mA Vpp 5 V 20 1 Data based on characterization results not tested in production Table 39 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lio 10 MA Vpp 5 V 0 8 VoL Output low level with 4 pins sunk lio 10 MA Vpp 3 3 V 100 Output low level with 4 pins sunk lio 20 MA Vpp 5 V 1 50 y Output high level with 8 pins sourced lo 10 mA Vpp 5V 4 0 Vou Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 240 Output high level with 4 pins sourced lio 20 mA Vpp DM 3 30 1 Data based on characterization results not tested in production 70 101 Doc ID 14733 Rev 8 d STM8S207xx STM8S208xx Electrical characteristics Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin Figure 23 Typ Vo Vpp 5 V standard ports 40 C 25 C 125 85 C 125 C Vor V lo mA Figure 24 Typ Vo Vpp 3 3 V standard ports 40 C 25 C 125 85 C 125 C Vor V lo mA Figure 25 Typ VoL 8 Vpp 5 V true open drain ports 40 C 25 C 85 C 154 125 C D ecm Vor V Doc ID 14733
17. EE raa 47 Electrical characteristics 50 9 1 Parameter conditions sick 2 3 3 29 93 36 RRAREGRREISGGRASER Ra 50 9 1 1 Minimum and maximum values 50 9 1 2 Typical Values 8 ei y ka TEE dE he GG Y ARX een 50 9 1 3 Typical curves 0 cee tee 50 9 1 4 Typical current consumption 50 9 1 5 Pin loading conditions 51 9 1 6 Loading capacitor serris rasake reinii EE OEE eh 51 9 1 7 Pin input voltage 24 05 ce Eu kh skod deaan nkita eroarea 51 9 2 Absolute maximum ratings 52 9 3 Operating conditions du eds aleet kNGRRR ERES BER S Rr seed 54 9 3 1 VCAP external capacitor 55 9 3 2 Supply current characteristics aeaaaee eee 56 9 3 3 External clock sources and timing characteristics 63 9 3 4 Internal clock sources and timing characteristics 65 9 3 5 Memory characteristics 67 9 3 6 I O port pin characteristics 0 0 0 0 ees 68 9 3 7 Reset pin characteristics 74 9 3 8 SPI serial peripheral interface 76 9 3 9 DC interface characteristics 0 00 ccc cece eee eee eee es 79 9 3 10 10 bit ADC characteristics 0 0 0 0 81 9 3 11 EMC characteristics 0 00 00 eee 84 Package characteristics Leeeees s 87 10 4 Package mechanical data 88 10 1 1 LQFP package mechanical data 88 10 2 Thermal characteristics 94 10 2 1 Reference document 94 10 2 2 Selecting the product temperature range
18. Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T True open drain OD Open drain PP Push pull Reset state Bold X d Doc ID 14733 Rev 8 27 101 Pinouts and pin description STM8S207xx STM8S208xx Table 6 Pin description Pin number Input Output Ge oc zo Alternate 2 o0 Default o x 9 3 F s 9 Pinname SLE Bt v S alternate Unctionafter EE EE ps S I B cg function remap lololol l 5 2 ai option bit ul 1 14 71417 1 NRST yo X Reset 2 2 2 2 2 PAI OSCIN vo x x O1 x X Port A1 Resonator crystal in 3 3 3 3 3 PAZ2 OSCOUT JO x x x O1 X X Port A2 Resonator crystal out 4 14 4 4 Vgsio 1 S I O ground 5 5 5 5 4 Vss S Digital ground 6 6 6165 VCAP S 1 8 V regulator capacitor 7 7 7 716 Vpp S Digital power supply 8 8 8 8 7 Vppo 1 S I O power supply Timer 2 TIM3_CH1 9 99 PA3 TIM2_CH3 I O X X X O1 X X Port A3 channel3 AFR1 10 10 10 9 PA4 UART1_RX I O X X X HS O3 X X Port A4 UART1 receive 11 11 11 10 PAD UARTA TX I O X X X IHS OS X X Port A5 VARTI transmit UART1 12 12 12 11 PASG UART1 CK IO X X X HS OS
19. T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Doc ID 14733 Rev 8 25 101 Pinouts and pin description STM8S207xx STM8S208xx LQFP 44 pin pinout fo Q 9 x un 9 ra Zz I v ui zu o8 D ugs z gale E IT SD O05 oBg a X x Il x Ql 10a FS o E Oo Soi gtzz22257 FREEEESEORS m tQ Qao oo ESSLLELEIEE oogeao085eqgum ooaaaaadogaaa Oooo oO 44 43 42 41 40 39 38 37 36 35 34 NRST Die 33H PG1 CAN_RX OSCIN PA1 12 32107 PGO CAN TX OSCOUT PA2 r13 31H PC7 HS SPI MISO Vssio 1 04 30H PC6 HS SPI MOSI Vss O15 290 Vppio 2 VCAP 6 280 Vssio 2 Vpp O7 270 PC5 HS SPI_SCK Vppio 1 08 26H PC3 HS TIM1_CH3 UART1_RX 09 250 PC2 HS TIM1_CH2 UART1_TX 010 240 PC1 HS TIM1_CH1 UART1_CK 011 230 PE5 SPI_LNSS 12131415 1617 18192021 22 DUTOT TTT OOO TO rn oO i0 st Oo QN O o G Of rm oo oo oO u XQ DO 0 c 0o o c ROW sg oO Oe oO 222222222 d ds ss d dd d THE a SS S S z s CEZzZZ EEE 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same a
20. Vggl Variations between all the different ground pins 50 see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 85 1 All power Vpp Vppjo VppA and ground Vss Vgsio Vssa pins must always be connected to the external power supply 2 Iw must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the lj pi value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected D Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Electrical characteristics Table 15 Current characteristics Symbol Ratings Max Unit Jupp Total current into Vpp power lines source 60 lyss Total current out of Vss ground lines sink 2 60 T Output current sunk by any UO and control pin 20 Output current source by any I Os and control pin 20 Total output current sourced sum of all UO and control pins for devices with two Vppio pins 200 Total output current sourced sum of all UO and control pins for devices with one Vppjo pin 100 A Ho m Total output current sunk sum of all I O and control pins for devices with two Vggio pins 160 Total output current sunk sum of all UO
21. X X O1 X X Port B5 Analog input 5 AFR6 DC SCL 30 26 18 17 12 PB4 AIN4 VO X X X O1 X X Port B4 Analog input 4 AFR6 31 27 19 18 13 PB3 AIN3 VO X X X O1 X X Port B3 Analog input 3 or d TIM1 32 28 20 19 14 PB2 AIN2 VO X xX X O1 X X Port B2 Analog input CH3N AFR5 TIM1_ 33 29 21 20 15 PB1 AIN1 VOIX xX X O1 X X Port B1 Analog input 1 CH2N AFR5 TIM1_ 34 30 22 21 16 PBO AINO VO X X X O1 X X Port BO Analog input O CH1N AFR5 35 PH4 TIM1_ETR O X X O1 X X Port H4 Timer 1 trigger input ases ads vol x x ail ela poins neg TIM1_CH3N channel 3 37 PHG VO X X O1 X X Port H6 Ken TIM1_CH2N S one channel 2 B sd dose re PEUT vol x x Biles leone iera TIM1_CH1N channel 2 39 31 23 PE7 AIN8 VO X X x O1 X X Port E7 Analog input 8 40 32 24 22 PE6 AIN9 UO O1 Port E6 Analog input 9 SPI 41 33 25 23 17 PES SPI NSS VO XXX O1 X X Port E5 master slave select ky Doc ID 14733 Rev 8 29 101 Pinouts and pin description STM8S207xx STM8S208xx Table 6 Pin description continued Pin number Input Output oc 5 Alt t ol et ol sti GN o S x 2 2 Default inean aes Seil uo Pin name E D EI EI a 3r alternate Ebr rs a al 2 7 3 ala c9 function remap G GGG
22. and control pins for i Wo 80 devices with one Vssio pin Injected current on NRST pin 4 linue 9 Injected current on OSCIN pin 4 Injected current on any other pin 4 ITT Total injected current sum of all I O and control pins 20 Data based on characterization results not tested in production 2 All power Vpp Vppio Vppa and ground Vas Vsgjo Vssa pins must always be connected to the external supply 3 UO pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppjo Vsgio pins 4 Iw must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the liy py value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vss For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics on page 81 6 When several inputs are submitted to a current injection the maximum Zus is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with lj up maximum current injection on four I O port pins of the device Table 16 Thermal characteristics
23. and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 Timers with 3 or 2 individually configurable capture compare channels PWM mode Interrupt sources 2 or 3 x input capture output compare 1 x overflow update Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Product overview 4 12 TIM4 8 bit basic timer e 8 bitautoreload adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source CPU clock e Interrupt source 1 x overflow update Table 4 TIM timer features Counter Timer Timer size Prescaler Counting CAPCOM Complem Ext synchr bits mode channels outputs trigger onization chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No m TIMA 8 Any power of 2 from 1 to 128 Up 0
24. bytes stack 0x00 1800 Reserved 0x00 3FFF 0x00 4000 Up to 2 Kbytes data EEPROM 0x00 47FF 0x00 4800 0x00 487F Option bytes 0x00 4900 Reserved 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF see Table 8 and Table 9 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 CPU SWIM debug ITC 0x00 7FFF registers see Table 10 0x00 8000 i 0x00 807F 32 interrupt vectors 0x00 8080 Flash program memory 64 to 128 Kbytes 0x02 7FFF d Doc ID 14733 Rev 8 33 101 Memory and register map STM8S207xx STM8S208xx 6 2 34 101 Table 7 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 7 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start address End address 128K 0x00 8000 0x02 7FFF Flash program memory 64K 0x00 8000 0x01 7FFF 32K 0x00 8000 0x00 FFFF 6K 0x00 0000 0x00 17FF RAM 4K 0x00 0000 0x00 1000 2K 0x00 0000 0x00 07FF 2048 0x00 4000 0x00 47FF Data EEPROM 1536 0x00 4000 0x00 45FF 1024 0x00 4000 0x00 43FF Register map Table 8 UO port hardware register map Address Block Register label Register name MESEI status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input
25. pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CHR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Memory and register map d Table 8 UO port hardware register map continued Address Block Register label Register name ee 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Po
26. profile quad flat package 4Axvi i 89 64 pin low profile quad flat package xipo 90 48 pin low profile quad flat package xv 91 44 pin low profile quad flat package O0xim0 eee 92 32 pin low profile quad flat package xv 93 Doc ID 14733 Rev 8 7 101 List of figures STM8S207xx STM8S208xx Figure 49 STM8S207xx 208xx performance line ordering information scheme 98 8 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Introduction 1 Introduction This datasheet contains the description of the STM8S20xxx performance line features pinout electrical characteristics mechanical data and ordering information e Forcomplete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STMB core please refer to the STM8 CPU programming manual PM0044 ky Doc ID 14733 Rev 8 9 101 Description STM8S207xx STM8S208xx 2 10 101 Description The STM8S20xxx performance line 8 bit microcontrollers offer from 32 to 128 Kbytes Flash program memory They are referred to as high den
27. reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The app
28. series inductance to less than 15 nH Figure 13 External capacitor Cgx1 ESR C ESL ERE E Cac Rleak 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Doc ID 14733 Rev 8 55 101 Electrical characteristics STM8S207xx STM8S208xx 9 3 2 Supply current characteristics The current consumption is measured as described in Figure 9 on page 50 Total current consumption in run mode The MCU is placed under the following conditions e AN UO pins in input mode with a static value at Vpp or Vas no load e All peripherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the MCU is clocked at 24 MHz T4 x105 C and the WAITSTATE option bit is set Subject to general operating conditions for Vpp and T4 Table 19 Total current consumption with code execution in run mode at Vpp 2 5 V Symbol Parameter Conditions Typ Max Unit fopy faster 24 MHz HSE crystal osc 24 MHz 4 4 Ta 105 C HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 3 3 Supply 16 MH HSE t clock 16 MH 2 7 currenti fopu fuAsrER 16 MHz SE user ext clock 16 MHz 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 ae mm HSE user ext clock 16 MHz 1 2 4 1 128 125 kHz from RAM HU MASTER HSI RC osc 16 MHz 10 1 300 rn fmastep 128 15 625
29. th SO ms Prt nar DEN dis SO MISO OUTPUT MSB OUT BIT our our OUT su Sl d an X ums XC INPUT L ths ai14134 Figure 38 SPI timing diagram slave mode and CPHA 1 NSS input A CPHA 1 rh an CPOL 0 CPHA 1 t T CPOL 1 man e Inc mE SCK Input tg p SCK at di th SO Za is Ge MISO OUTPUT Velour wsHour BIT6 OUT Bou OUT me Sl E EE SI INPUT C wen IN l 4 l Lem IN ai14135 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Von d Doc ID 14733 Rev 8 77 101 Electrical characteristics STM8S207xx STM8S208xx Figure 39 SPI timing diagram master mode SCK Input SCK Input High NSS input i SCKj CPHA 0 CPOL 0 f A W E CPHA 0 3 Y MU xa rit MISO _ f SCK ECCE OUTUT L waan 1 BIT1 OUT i Leo OUT Wo h MO ex ai14136 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp 78 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Electrical characteristics 9 3 9 I2C interface characteristics Table 42 I C characteristics Standard mode DC Fast mode GC Symbol Parameter Unit Min 2 Max Min Max twiscLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 tsp SDA data ho
30. 0 0079 D 12 000 0 4724 D1 10 000 0 3937 E 12 000 0 4724 E1 10 000 0 3937 0 500 0 0197 K 0 000 3 500 7 000 0 0000 3 5000 7 0000 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 1 Values in inches are converted from mm and rounded to four decimal places 90 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Package characteristics d Figure 46 48 pin low profile quad flat package 7 x 7 D D1 C ccc C D3 A A 36 25 I 37 24 n ES b E E3 E1 E 48 i E 1 12 f KC 5B ME Table 53 48 pin low profile quad flat package mechanical data mm inches Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 8 91 101 Package characteristics STM8S207xx STM8S208xx Figure 47 44 pin low profile quad flat package 10 x 10 D1 c c
31. 0 No 4 13 Analog to digital converter ADC2 STM8S20xxx performance line products contain a 10 bit successive approximation A D converter ADC2 with up to 16 multiplexed input channels and the following main features e Input voltage range 0 to VppA e Dedicated voltage reference VREF pins available on 80 and 64 pin devices e Conversion time 14 clock cycles e Single and continuous modes e External trigger input e Trigger from TIM1 TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented e UART 1 Full feature UART SPI emulation LIN2 1 master capability Smartcard mode IrDA mode single wire mode UARTS Full feature UART LIN2 1 master slave capability SPI Full and half duplex 10 Mbit s 12C Up to 400 Kbit s beCAN rev 2 0A B 3 Tx mailboxes up to 1 Mbit s Doc ID 14733 Rev 8 19 101 Product overview STM8S207xx STM8S208xx 4 14 1 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fepy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiv
32. 01 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and T4 Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean x 2 x Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in Figure 9 Fig
33. 07xx STM8S208xx Electrical characteristics 9 3 10 10 bit ADC characteristics Subject to general operating conditions for VppA fuasrER and Ta unless otherwise specified Table 43 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vppa 3 to 5 5 V 1 4 fapc ADC clock frequency MHz Vopa 24 5to5 5V 1 6 VppA Analog supply 3 5 5 V Vngr Positive reference voltage 2 750 Vopa V Vper Negative reference voltage Vssa 057 v Vssa Vppa V Vain Conversion voltage range Devices with external VREF Vrer V Vrer Vrer pins Internal sample and hold Canc capacitor 3 pF fap 4 MHz 0 75 tg Sampling time El nia E us fapc 6 MHz 0 5 tstap Wakeup time from standby 7 Hs fADC 4 MHz 3 5 US Total conversion time including conv sampling time 10 bit resolution fanc 6 MHz ied HS 14 1 fapc 1 Data guaranteed by design not tested in production 2 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming d Doc ID 14733 Rev 8 81 101 Electrical characteristics STM8S207xx STM8S208xx
34. 08xx Electrical characteristics d Figure 20 Typical Vu and Vu vs Vpp 4 temperatures 40 C a 25 C 85 C 125 C 2 I 2 a gt 04 r r r r r r d 25 3 3 5 4 45 5 55 6 Von V Figure 21 Typical pull up resistance vs Vpp 4 temperatures Pull up resistance QW Voo V Figure 22 Typical pull up current vs Vpp 4 temperatures 140 T 5 80 5 o a 60 oe 2 m 25 C amp 40 a 85 C 20 s 125 C Pal oke 0 1 2 3 4 5 6 Voo V ai15068 1 The pull up is a pure resistor slope goes through 0 Doc ID 14733 Rev 8 69 101 Electrical characteristics STM8S207xx STM8S208xx Table 37 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lio 10 mA Vpp 5 V 2 VoL Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 100 Von Output high level with 8 pins sourced le 10 mA Vpp 2 5 V 2 8 y Output high level with 4 pins sourced lig 4 mA Vpp 3 3 V 2 0 1 Data based on characterization results not tested in production Table 38 Output driving current true open drain ports Symbol Parameter Conditions Max Unit lio 10 mA Vpp 5 V 1 VoL Output low level with 2 pins sunk lio 10 mA Vpp 3 3 V 1 500 V lio
35. 2B TIM3 ARRH TIM3 auto reload register high OxFF 0x00 532C TIM3_ARRL TIMS auto reload register low OxFF 0x00 532D TIM3_CCR1H TIM3 capture compare register 1 high 0x00 0x00 532E TIM3 CCR1L TIM3 capture compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture compare register 2 low 0x00 piura Reserved area 15 bytes 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIMA status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF pecie Reserved area 185 bytes 42 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ee 0x00 5400 ADC _CSR ADC control status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ae ADC_DRH ADC data register high undefined 0x00 5405 ADC_DRL ADC data register low undefined 0x00 5406 ADC_TDRH ADC Schm
36. 32 n Lea Lea Lea b IL Lea ES E1 E l 64 17 Y Pint HHHHHH Goes identification 1 16 Calis ie Table 51 64 pin low profile quad flat package mechanical data 14 x 14 mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places d Doc ID 14733 Rev 8 89 101 Package characteristics STM8S207xx STM8S208xx Figure 45 64 pin low profile quad flat package 10 x 10 49 o La E 64 Pin 1 D D1 D3 48 Ses c A A2 identification AL 16 c A get Table 52 64 pin low profile quad flat package mechanical data 10 x 10 mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035
37. 5 C 55 125 C 50 1 6 pS EST 40 35 30 25 3 3 5 4 45 5 5 5 6 Voo V Figure 35 Typical NRST pull up current ly vs Vpp 4 temperatures 140 4 120 100 80 60 40 NRESET Pull Up current uA 20 40 C p a 25 C e mee o P 85 C we 125 C 2 0 1 2 3 4 5 6 Vpp V ai15069 The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 36 Otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection External reset circuit Von Rpu Internal reset optional NRST Filter STM8 d Doc ID 14733 Rev 8 75 101 Electrical characteristics STM8S207xx STM8S208xx 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 41 are derived from tests performed under ambient temperature faster frequency and Vpp supply voltage conditions tMASTER l fuASTER Refer to UO port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 41 SPI characteristics Symbol Parameter Conditions Min Ma
38. 752 8 standard for test software board layout and pin loading Table 47 EMI data Conditions Max fuse fcpu z Symbol Parameter Unit General conditions Monitored frequency band 8 MHz 8 MHz 8 MHz 8 MHz 16 MHz 24 MHz 0 1MHz to 30 MHz 15 20 24 Peak level Vpp 5V 30 MHz to 130 MHz 18 21 16 dBuV 5 Ta 25 C EMI LQFP80 package 130 MHz to 1 GHz 1 1 4 conforming to SAE J 1752 3 die EMI SAE EMI level 2 2 5 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 48 ESD absolute maximum ratings Symbol Ratings Conditions Class ee at Unit value Electrostatic discharge voltage TA 25 C conforming to VESD HBM Human body model JESD22 A114 A 2000 V Electrostati
39. 82 101 Table 44 ADC accuracy with Bam lt 10 KO VppgA 5 V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 2 5 IE Total unadjusted error fapc 4 MHz 14 3 fapc 6 MHz 1 6 3 5 fapc 2 MHz 0 6 2 IEg Offset error fapc 4 MHz 1 1 2 5 fapc 6 MHz 1 2 2 5 fapc 2 MHz 0 2 2 lEg Gain error fApc 4 MHz 0 6 2 5 LSB fapc 6 MHz 0 8 2 5 fapc 2 MHz 0 7 1 5 lEpl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 6 MHz 0 8 1 5 fapc 2 MHz 0 6 1 5 IE I Integral linearity error 2 fapc 4 MHz 0 6 1 5 fapc 6 MHz 0 6 1 5 Data based on characterisation results for LQFP80 device with Vngr Vpgr not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for In up and Zlins Piny in Section 9 3 6 does not affect the ADC accuracy Table 45 ADC accuracy with Rain lt 10 kQ RAIN VppA 3 3V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 1 2 IE Total unadjusted error fapc 4 MHz 1 6 2 5 f
40. 9 3 16 16 128K 2048 6K STM8S207R8 64 52 36 9 3 16 16 64K 1536 4K STM8S207R6 64 52 36 9 3 16 16 32K 1024 2K STM8S207CB 48 38 35 9 3 10 16 128K 2048 6K No STM8S207C8 48 38 35 9 3 10 13 64K 1536 4K STM8S207C6 48 38 35 9 3 10 16 32K 1024 2K STM8S207SB 44 34 31 8 3 9 15 128K 1536 4K STM8S207S8 44 34 31 8 3 9 15 64K 1536 4K STM8S207S6 44 34 31 8 3 9 15 32K 1024 2K STM8S207K6 32 25 23 8 3 7 12 32K 1024 2K STM8S208MB 80 68 37 9 3 16 18 128 K 2048 6K STM8S208RB 64 52 37 9 3 16 16 128 K 2048 6K STM8S208R8 64 52 37 9 3 16 16 64K 2048 6K STM8S208R6 64 52 37 9 3 16 16 32K 2048 6K STM8S208CB 48 38 35 9 3 10 16 128 K 2048 6K Yes STM8S208C8 48 38 35 9 3 10 16 64K 2048 6K STM8S208C6 48 38 35 9 3 10 16 32K 2048 6K STM8S208SB 44 34 31 8 3 9 15 128 K 1536 4K STM8S208S8 44 34 31 8 3 9 15 64K 1536 4K STM8S208S6 44 34 31 8 3 9 15 32K 1536 4K d Doc ID 14733 Rev 8 11 101 Block diagram STM8S207xx STM8S208xx 3 Block diagram Figure 1 STM8S20xxx performance line block diagram 12 101 Single wire debug interf Master slave autosynchro C 16 channels 400 Kbit s C N 10 Mbit s die LIN master Lt SPI emul r1 1 Mbit s E 1 2 4 kHz beep C Reset block XTAL 1 24 MHz Clock controller Reset RC int 16 MHz Detector POR BO
41. C osc 16 MHz 1 0 1 3 eech fmastep 128 15 625 SI RC osc 16MHZ 8 0 55 fopy fMASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN mA fopy fuasrER 24 MHz HSE crystal osc 24 MHz 11 0 Ta 105 C HSE user ext clock 24 MHz 10 8 18 0 HSE crystal osc 16 MHz 8 4 Supply 15 2 BEE fopy fmaster 16 MHz HSE user ext clock 16 MHz 8 2 5 run mode HSI RC osc 16 MHz 8 1 13 2 code 2 executed CPU fMAsTER 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fcpu fuaster 1 28 125 kHz HSI RC osc 16 MHz 1 1 ae fmasteR 128 15 625 Luet RC osc 16 MHz 8 0 6 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration ky Doc ID 14733 Rev 8 57 101 Electrical characteristics STM8S207xx STM8S208xx Total current consumption in wait mode Table 21 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit fopu faster 24 MHz HSE crystal osc 24 MHz 2 4 Ta 105 C HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 2 0 Supply fcpu fmaster 16 MHz HSE user ext clock 16 MHz 1 4 4 4 Ipp wel current in HSI RC osc 16 MHz 12 16 mA wait mode fopu fMasTER 1 28 125 kHz HSI RC osc 16 MHz 1 0 EH fasten 128 15 625 SI RC osc 16 MHz g 0 55 fo
42. Current consumption curves Figure 14 and Figure 15 show typical current consumption measured with code executing in RAM Figure 14 Typ Ipp RUN vs VDD HSI RC osc fcpu 16 MHz 40C 4 25 C 85 C 3 5 125 C 3 J T Eene a 25 SS Io E g a 15 2B 1 0 5 0 r r r T T r j 2 5 3 3 5 4 45 5 55 6 Voo V Figure 15 Typ Ipp wF vs Vpp HSI RC OSC fopy 16 MHz 40 C 25 1 25 C 85 C 2 125 C E 15 a ee E S SS T S S I d RR RE e e y yc s 5 1 B 05 0 25 3 35 4 45 5 55 6 Von V Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T Table 30 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit Berg Se SE clock source 0 24 MHz Vuseu SCH input pin high level 0 7 x Vpp Vpp A 0 3 V Hea Sech input pin low level We 0 3 x Vpp j ILEAK HSE Soch ENEE Vss lt Vin lt Von 1 1 pA 1 Data based on characterization results not tested in production Figure 16 HSE external clock source VHSEH L I mmm VHSEL VE gt fuse External clock source OSCIN Nadsasgd H STM8
43. E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 8 93 101 Package characteristics STM8S207xx STM8S208xx 10 2 10 2 1 94 101 Thermal characteristics The maximum chip junction temperature T wess must never exceed the values given in Table 17 General operating conditions on page 54 The maximum chip junction temperature T wus in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X ya Where Tamax is the maximum ambient temperature in C Oya is the package junction to ambient thermal resistance in C W e Ppmax is the sum of Pintmax and Promax Ppmax Pintmax Pivomax Pintmax iS the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Promax represents the maximum power dissipation on output pins where Promax Vor loL Z Vpp Vouy lou and taking account of the actual Vo Jo and Vou log of the I Os at low and high level in the application Table 56 Thermal characteristics Symbol Parameter Value Unit Oa ee T Sege ge W is use o 45 Cu E EES a GA dog dca m iw e num Hue EET Ga iege junction ambient SS m
44. FFh 480Dh Flash wait OPT7 Reserved Wait state 00h 480En Stetes NOPT7 Reserved Nwaitstate FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 FFh ki Doc ID 14733 Rev 8 47 101 Option bytes STM8S207xx STM8S208xx Table 13 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages 0 to 3 defined as UBC memory write protected 0x03 Pages 0 to 4 defined as UBC memory write protected OxFE Pages 0 to 255 defined as UBC memory write protected OxFF Reserved Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2_CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function DC SDA port B4 alternate function FG SOL AFRB5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alt
45. MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 13 in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 128 Kbytes minus UBC User specific boot code UBC Configurable up to 128 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation r Data Data memory area 2 Kbytes EEPROM memory Option bytes Programmable area from 1 Kbyte UBC area 2 first pages up to 128 Kbytes Remains write protected during IAP 1 page steps Up to 128 Kbytes Flash E program memory Program memory area Write access possible for IAP Doc ID 14733 Rev 8 15 101 Product overview STM8S207xx STM8S208xx 4 5 16 101 Read out protection ROP The read out protection blocks read
46. R Clock master status register OxE1 0x00 5004 CLK_SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register SE 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 OUS CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register XX 0x00 50CD CLK_SWIMCCR SWIM clock control register Du 0x00 50CE to 0x00 50D0 Reserved area 3 bytes 0x00 50D1 Hune WWDG_CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 0x00 50DF Reserved area 13 bytes 0x00 50E0 IWDG_KR IWDG key register 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control status register Ox1F 0x00 50F4 to 0x00 50FF Reserved area 12 bytes ky Doc ID 14733 Rev 8 37 101 Memory and register map STM8S207xx STM8S208xx
47. R EE RUE Ne 13 4 1 Central processing unit GTM 13 4 2 Single wire interface module SWIM and debug module DM 14 4 3 Interrupt controller 4v ess n EROR ERR x ERG e me RR Ra 14 4 4 Flash program and data EEPROM memory sslses else 15 45 Cok cOnltoller aset be BEER EEN ween Aere Ae g 16 4 6 Power management 0 000 ee nne 17 4 7 Watchdog timers sole ERRRERE ERI ERR EE E ER EE EE REESE 17 48 Auto wakeup counter 0000 c ee es 18 4 9 Beeper vow iem deel apa Run oe Mine ot Ecos Qum dubiae en eee Meee 18 4 10 TIM1 16 bit advanced control timer 18 4 11 TIM2 TIMG 16 bit general purpose mer 18 4 12 TIM4 8 bit basic mer 19 4 13 Analog to digital converter ADC2 ansaan 19 4 14 Communication interfaces 19 KI UABT aaier Rer ERR a Oa RM xe IRL a S 20 4142 MARIS sariranira aaa a i s hate ies E tob ped a E PR ee 20 4443 SBliiiouocexeew ka vu RR RERO be EA EEEN EORR Re RUE CORR d 21 ECKE 22 4 14 5 DECAN aote de Rhe REENEN D ee Ro ROS Dc oa e ee 22 5 Pinouts and pin description 23 5 1 Package HEURE RE ri S a EE Bn ced 23 5 2 Alternate function remapping llsseie enn 32 6 Memory and register map eee 33 6 1 suem dro TET p E ee 2 33 2 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Contents 10 6 2 Register map eer Berg 34 Interrupt vector mapping leeren 46 Option DyfeS E ANER css EE RE ENEE ek 6278 97
48. R RC int 128 kHz Clock to peripherals and core lt gt Window WDG STMB core lt gt lt gt Independent WDG Debug SWIM lt gt Up to 128 Kbytes high density program Flash 2 Fc lt gt Up to 2 Kbytes data EEPROM 3 SPI lt gt p lt gt Up to 6 Kbytes 5 RAM E E bal 5 gt Boot ROM UART1 E 9 E lt gt 16 bit advanced control UART3 timer TIM1 beCAN lt gt 5 gt 16 bit general purpose timers TIM2 TIM3 ADC2 qs GE 8 bit basic timer TIM4 Beeper 5 gt 5 gt AWU timer Up to 4 CAPCOM channels 3 complementary outputs SCH Up to 5 CAPCOM channels Doc ID 14733 Rev 8 d STM8S207xx STM8S208xx Product overview 4 4 1 Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers e
49. ROM and RAM boundary addresses nanana uaaa 34 UO port hardware register map 34 General hardware register map 36 CPU SWIM debug module interrupt controller registers llli less 44 Interrupt mapping lssleleeseleen eee 46 Option AE 47 Option byte description 48 Voltage characteristics 0 0 n 52 Current characteristics silii 53 Thermal characteristics irrena nesne iaae EEA EE en 53 General operating conditions 54 Operating conditions at power up power down 55 Total current consumption with code execution in run mode at Vpp 2 5 V 56 Total current consumption with code execution in run mode at Vpp 3 8V 57 Total current consumption in wait mode at Vpp2 DN 58 Total current consumption in wait mode at Vpp 23 N eee eee 58 Total current consumption in active halt mode at Vpp 5 V T4 40 to 85 C 59 Total current consumption in active halt mode at Vpp 233N nna 59 Total current consumption in halt mode at Vpp 5 V T4 40 to 85 C 1 eee 60 Total current consumption in halt mode at Von 3 3V 000 000 0002 60 Wakeup mes ENEE ea eme Ry ER RA RUE ea GRO DR RE RUNE ee ROS Red 60 Total current consumption and timing in forced reset state 61 Peripheral current consumption 0 00 0 cee rn 61 HSE user external clock characteristics liliis 63 HSE oscillator characteristics llis 64 HSI oscillator character
50. Register name nesel status 0x00 5050 to Reserved area 10 bytes 0x00 5059 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status 0x00 register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR EE 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area 59 bytes 0x00 50A0 ime EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register XX 0x00 50B4 to 0x00 50BF Reserved area 12 bytes 0x00 50C0 ae CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 36 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name Re status 0x00 50C3 CLK_CMS
51. Rev 8 71 101 Electrical characteristics STM8S207xx STM8S208xx Figure 26 Typ Vo Vpp 3 3 V true open drain ports 40C 25 C 85 C 15 125 C Vor V Figure 27 Typ VoL Vpp 5 V high sink ports 40C 25 C 1 25 85 C 125 C 0 75 Vor V lo mA Figure 28 Typ Vo Vpp 3 3 V high sink ports ini eem 40 C 25 C 125 85 C 125 C gt Si gt lo mA 72 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Electrical characteristics d Figure 29 Typ Von Von Vpp 5 V standard ports C 25 C 85 C 125 C Von Von V lo mA 40 C Figure 30 Typ Vpp Von Vpp 3 3 V standard ports 25 C 85 C 125 C Von Vox V lo mA Figure 31 Typ Von Vou Vpp 5 V high sink ports 15 1 25 40 C 25 C 85 C 125 C Von Von V e go a 0 5 0 25 25 lo mA Doc ID 14733 Rev 8 73 101 Electrical characteristics STM8S207xx STM8S208xx Figure 32 Typ Von Von 9 Vpop
52. STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 14733 Rev 8 101 101
53. Timer 2 BEEP output 77 61 45 41 29 cc VO X X X HS O3 X X Port D4 hannel 1 AFR7 78 62 46 42 30 PD5 UART3_TX lO X X X 01 X X Port ps VARTS data transmit 79 63 47 43 31 PD6 UART3 RX l O X X X 01 x X Port pe VARTS data receive 80 64 48 44 32 PD7 TLI vo x x x O1 x X Port pz 1 level es interrupt AFR4 1 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented ky Doc ID 14733 Rev 8 31 101 Pinouts and pin description STM8S207xx STM8S208xx 5 2 32 101 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes on page 47 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Memory and register map 6 Memory and register map 6 1 Memory map Figure 8 Memory map 0x00 0000 RAM up to 6 Kbytes 0x00 17FF U T 1024
54. Typ Max Unit Jop Supply current in reset state Re 2 mA Vpp 2 3 3 V 0 8 fecere je release to bootloader vector 150 us 1 Data guaranteed by design not tested in production Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T HSI internal RC fcpy fuAsrER 16 MHz Table 29 Peripheral current consumption Symbol Parameter Typ Unit Ibom TIM1 supply current 220 Ippcimz TIM2 supply current 120 Ipp TiM3 TIMS timer supply current 1 100 Ipp TiM4 TIM4 timer supply current 1 25 Ipp uart1 UART1 supply current 2 90 Ipp uanrs UARTS supply current 110 i Ippsey SPI supply current 40 love DC supply current 17 50 Ipp caN beCAN supply current 210 IDD ADC2 ADC2 supply current when converting 3 1000 d 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production Doc ID 14733 Rev 8 61 101 Electrical characteristics STM8S207xx STM8S208xx 62 101
55. X X Port A6 synchronous clock 13 PHO O X X HS OS3 X X Port HO 14 PH1 O X X HS O3 X X Port H1 15 PH2 O X X O1 X X Port H2 16 PH3 O X X O1 X X Port H3 17113 PF7 AIN15 VO x x 01 x X Port F7 Si input 18 14 PF6 AIN14 vo x x O1 X X Port F6 dove input 19115 PF5 AIN13 VO x x 01 x X Port F5 input 20 16 8 PF4 AIN12 O xx O1 X X Port FA es input 21 17 PF3 AIN11 O xx O1 X X Port F3 SE input ADC positive reference 22 18 VREE S voltage 23 19 13 12 9 VppA S Analog power supply 28 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Pinouts and pin description Table 6 Pin description continued Pin number Input Output oc o tco el oi 2 i ux 92 Default maton eoi Seil uo Pin name E D EI EI a 3r alternate EIEIEIEIE C 2 82 g ajae F8 function remap lololol l E 5 29 si option bit lf l3 4 4 o x ui 24 20 14 13 10 VssA S Analog ground ADC negative reference SIE VREF S voltage 26 22 PFO AIN10 V O X x O1 X X Port FO 2 input 27 23 15 14 PB7 AIN7 VO X X X O1 Port B7 Analog input 7 28 24 16 15 PB6 AING UO O1 Port B6 Analog input 6 DC SDA 29 25 17 16 11 PB5 AIN5 VOIX
56. al hardware register map continued Address Block Register label Register name Wee 0x00 5250 TIM1 CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TM TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1_ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture com
57. al hardware register map continued Address Block Register label Register name ee 0x00 5230 UART1 SR UART status register O0xCO 0x00 5231 UART1 DR UART1 data register XX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 te a Reserved area 5 bytes 0x00 5240 UART3_SR UARTS status register Coh 0x00 5241 UART3 DR UARTS data register XX 0x00 5242 UART3 BRH1 UARTS baud rate register 1 0x00 0x00 5243 UART3 BRR2 UARTS baud rate register 2 0x00 0x00 5244 UART3_CR1 UARTS control register 1 0x00 0x00 5245 menm UARTS CR2 UARTS control register 2 0x00 0x00 5246 UART3_CR3 UARTS control register 3 0x00 005247 UART3_CR4 UARTS control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3_CR6 UARTS control register 6 0x00 pus SC Reserved area 6 bytes STA Doc ID 14733 Rev 8 39 101 Memory and register map STM8S207xx STM8S208xx Table 9 Gener
58. ap 2 MHz 0 7 1 5 lEol Offset error E fapc 4 MHz 1 3 2 fap 2 MHz 0 2 1 5 IEg Gain error LSB fapc 4 MHz 0 5 2 fap 2 MHz 0 7 1 IEp Differential linearity error E fADC 4 MHz 0 7 1 fap 2 MHz 0 6 1 5 IE Integral linearity error E fADC 4 MHz 0 6 1 5 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Electrical characteristics Figure 41 ADC accuracy characteristics A Ce oe e Vna V el 1022 Vpopa SSA i 1LSB EE 7 7 IDEAL 1024 z 1021 4 Jee i pm 1 2 247 7 Ld k Er mea 3 zi gt _ 4 a pus poe j 1 M Pi 1 5 zal Zz 4 D 1 1 L P i i 34 i Pa i a B F ED 2 1 B Ta 7 gt 1 1 MA 1 LSBipEAL al l 14 pipi d LL 0 1 2 3 4 5 6 7 1021102210231024 Vssa Vopa 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line E7 Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 42 Typical appl
59. asic timer with 8 bit prescaler LQFP64 14x14 LQFP64 10x10 LQFP32 7x7 LQFP48 7x7 LQFP44 10x10 Auto wakeup timer Window watchdog independent watchdog m Communications interfaces High speed 1 Mbit s active beCAN 2 0B UART with clock output for synchronous operation LIN master mode UART with LIN 2 1 compliant master slave modes and automatic resynchronization SPI interface up to 10 Mbit s C interface up to 400 Kbit s m 10 bit ADC with up to 16 channels m I Os Up to 68 I Os on an 80 pin package including 18 high sink outputs Highly robust UO design immune against current injection Development support Single wire interface module SWIM and debug module DM for fast on chip programming and non intrusive debugging Table 1 Device summary Part numbers STM8S207xx STM8S207MB STM8S207M8 STM8S207RB STM8S207R8 STM8S207R6 STM8S207CB STM8S207C8 STM8S207C6 STM8S207SB STM8S207S8 STM8S20786 STM8S207K6 Part numbers STM8S208xx STM8S208MB STM8S208RB STM8S208R8 STM8S208R6 STM8S208CB STM8S208C8 STM8S208C6 STM8S208SB STM8S208S8 STM8S208S6 Doc ID 14733 Rev 8 www st com 1 101 Contents STM8S207xx STM8S208xx Contents 1 Introd ctio i NEIE d RR tb i RR EE NN 9 2 DescrIDHO EE 10 3 Block diagram 1cuaaaa es ck nci deh cab ae ew 670 08 09 8 3r a haa 12 4 Product overview en wwe wien nnnm hm ee OR KR 08 O
60. auaanaanononoanonnoannmunna SLRREKREKKKLSSSSSSSIG NRSTCI 1 60 LiPI3 OSCIN PA1L 2 59 CG OSCOUT PA2LI 3 58 Cen Vssio 1l 4 57 Up Vss 5 56 LI PG4 VCAPLI 6 55 LIPG3 Voll 7 54 D PG2 Vppio 1l 8 53 D PG1 CAN_RX TIM3 CH1 TIM2 CH3 PASL 9 52 LIPGO CAN TX UART1_RX HS PA4LI 10 51 DPC7 HS SPI_MISO UART1 TX HS Pet 11 50 1 PC6 HS SPI MOSI UART1_CK HS PDAGL 12 49 O Vppio 2 HS PHOL 13 48 O Vssio 2 HS PH10 14 47 m PC5 HS SPI_SCK PH2LI 15 46 1 PC4 HS TIM1_CH4 PH3LI 16 45 J PC3 HS TIM1_CH3 AIN15 PF7 0 17 44 PC2 HS TIM1 CH2 AIN14 PF6C 18 43 LIPC1 HS TIM1 CH1 AINT3 PFSLI 19 42 LI PCO ADC ETR AIN12 PFAL 20 41 PE5 SPI_LNSS Ayt or QW C9 st ot o e D OU QU QV ON ON CV QN CO C0 CO C0 CO CD CO CO O 4 e XXiOILOIDAXOQ Osxi O0KMr o iG urmmmmrmnmnmmrrTrr r z ulu GrOPeoooaargogeaoaaaaaa gt EECHER EES EE EES z zPzzceeszccpoegres 00 8 i000 EZI rrr EEIEEEEEEE o o z999 REE qa az EZZEI EEE 1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 4 CAN RXand CAN TX is available on STM8S208xx devices only ky Doc ID 14733 Rev 8 23 101 Pinouts and pin description STM8S207xx STM8S208xx 24 101 Figure 4 LQFP 64 pin pinout
61. c discharge voltage TA 25 C conforming to VESD CDM Charge device model JESD22 C101 2 1900 y 1 Data based on characterization results not tested in production Doc ID 14733 Rev 8 85 101 Electrical characteristics STM8S207xx STM8S208xx 86 101 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable UO pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 49 Electrical sensitivities Symbol Parameter Conditions Class Ty 25 C A LU Static latch up class Ta 85 C A Ta 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Package characteristics 10 Package characteristics To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com
62. cc c BER E 4Y_ME Table 54 44 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 c 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D3 8 000 0 3150 E 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 000 10 200 0 3858 0 3937 0 4016 ES 8 000 0 3150 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Package characteristics d Figure 48 32 pin low profile quad flat package 7 x 7 i ce Table 55 32 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 e 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205
63. ch third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of
64. check on the LIN identifier field LIN error management Hot plugging support SPI Maximum speed 10 Mbit s fyasteR 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin Doc ID 14733 Rev 8 21 101 Product overview STM8S207xx STM8S208xx 4 14 4 4 14 5 22 101 e l Cmaster features Clock generation Start and stop generation e lC slave features Programmable DC address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz beCAN The beCAN controller basic enhanced CAN interfaces the CAN network and supports the CAN protocol version 2 0A and B It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load For safety critical applications the beCAN controller provides all hardware functions to support the CAN time triggered communication option TTCAN The maximum transmission speed is 1 Mbit Transmission e Three transmit mailboxes e Configurable transmit priority by identifier or order request e Time stamp on SOF transmission Reception 8 11 and 29 bit ID One r
65. eceive FIFO 3 messages deep Software efficient mailbox mapping at a unique address space FMI filter match index stored with message Configurable FIFO overrun Time stamp on SOF reception Six filter banks 2 x 32 bytes scalable to 4 x 16 bit each enabling various masking configurations such as 12 filters for 29 bit ID or 48 filters for 11 bit ID Filtering modes Mask mode permitting ID range filtering I Dlist mode e Time triggered communication option Disable automatic retransmission mode 16 bit free running timer Configurable timer resolution Time stamp sent in last two data bytes Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Pinouts and pin description 5 Pinouts and pin description 5 1 Package pinouts Figure 3 LQFP 80 pin pinout Qo Q 9 x mI E m zZ ce fI uo m a lel 2 wae aln E F zc Or CN Oo I Xd I O Dese Ster S ER Re 49o0 zJjJB22z2 SOE ERREEEOE DORT 4E tooo o oS Iz ES2O2LLLLIL ZEEE SEET EE c
66. er wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame 4 14 2 UART3 Main features 20 101 1 Mbit s full duplex SCI LIN master capable High precision baud rate generator Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Product overview 4 14 3 Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes Address bit MSB Idle line interrupt e Transmission error detection with interrupt generation e Parity control LIN master capability e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame LIN slave mode Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated initial clock deviation 15 Synch delimiter checking 11 bit LIN synch break detection break detection always active Parity
67. ernate function AINO 1 Port B3 alternate function TIM1 ETR port B2 alternate function TIM1_CHS8N port B1 alternate function TIM1_CH2N port BO alternate function TIM1_CH1N AFRA Alternate function remapping option 4 0 Port D7 alternate function TLI 1 Port D7 alternate function TIM1_CH4 AFR3 Alternate function remapping option 3 0 Port DO alternate function TIM3_CH2 1 Port DO alternate function TIM1_BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2_CH3 port D2 alternate function TIM3_CH1 1 Port A3 alternate function TIM3_CH1 port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option O 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternate function ADC_ETR 48 101 D Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Option bytes d Table 13 Option byte description continued Option byte no OPT3 Description LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG windo
68. es Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 ky STM8S20xxx performance line block diagram 12 Flash memory organisation 15 LOFP 80 pint PINOUT cruci eee eee ea e RR bet eee Os 23 LQFP 64 pin pinout 0 0 0 0 tenet eee 24 EQEP 48 pin pINOUt EE irre reme ard RR ox Re ea dem rna a EE 25 LQFP 44 pin pinout lssssssseeeeee RR RR I mn 26 LQFP S2 pin PINOUT e e nra Rie a ra RR dex s rea A e E end s 27 Memo map usse oye e e n e ENEE ENT a RUE RON n Rol Ae ce ia E 33 Supply current measurement conditions 50 Pin loading conditions liiis eee 51 Pin input voltage secius s moe ek ENER gr ue Rr eee OUR RR e ERR ds 51 Ve ILLAD MPH 55 External capacitor Cer 55 Typ IDD RUN VS Vpp HSI RC OSC fopu 16MHZ 2 ee ee 62 Typ IDD WFI VS VDD HSI RC OSC fopu 16 MHZ hii a nad Ca wad cam e hed p 62 HSE external clock source 63 HSE oscillator circuit diagram 2 0 ete 64 Typical HSI frequency
69. ge pitch No character 0 5 mm B 0 65 mm C 0 8 mm Packing No character Tray or tube TR Tape and reel For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you Doc ID 14733 Rev 8 2 Referto Table 2 STM8S20xxx performance line features for detailed description ky STM8S207xx STM8S208xx Revision history 13 Revision history Table 57 Document revision history Date Revision Changes 23 May 2008 1 Initial release Added part numbers on page 1 and in Table 2 on page 1 1 05 Jun 2008 2 Updated Section 4 Product overview Updated Section 9 Electrical characteristics 22 Jun 2008 3 Added part numbers on page 1 and in Table 2 on page 1 1 Added 32 pin device pinout and ordering information Updated UBC option description in Table 13 on page 48 USART renamed UART1 LINUART renamed UART3 Max ADC frequency increased to 6 MHz Removed STM8S207K4 part number Removed LQFP64 14 x 14 mm package Added medium and high density Flash memory categories Added Section 6 Memory and register map on page 33 Replaced beCANS3 by beCAN in Section 4 14 5 beCAN Updated Section 9 Electrical characteristics on page 50 Updated LQFP44 Figure 47 and Table 54 and LQFP32 outline and mechanical data Figure 48 and Table 55 12 Aug 2008 4
70. ging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on six vectors including TLI Trap and reset interrupts Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Product overview 4 4 Flash program and data EEPROM memory e Upto 128 Kbytes of high density Flash program single voltage Flash memory e Upto 2K bytes true data EEPROM e Read while write Writing in data memory possible while executing code in program memory User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a
71. he moment it is enabled by software to a stabilized 24 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 17 HSE oscillator circuit diagram STM8 inse n e EAS 4 f to core E HSE R Co l I Lm m i Cu OSCIN du NN 2 A Resonator Consumption control L Resonator OSCOUT Cio HSE oscillator critical gm formula Imeri 2X TIX fyse x Rm 2C0 C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42C 52C Grounded external capacitance Im gt gt Omcrit 64 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Electrical characteristics 9 3 4 d Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta fuse High speed internal RC oscillator HSI Table 32 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz Trimmed by the Accuracy of HSI oscillator CUR Fie TIMP register A0 10 96 for given Vpp and TA conditions Vop 5 V Ta 25 C 2 2
72. ication with ADC Vop STM8 A Vr e Z 0 6V AIN AINx 10 bit A D Vain NNN LI f NNN conversion alle Can VT AL m ZN osv i IL Z Cape 1pA ky Doc ID 14733 Rev 8 83 101 Electrical characteristics STM8S207xx STM8S208xx 9 3 11 84 101 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user ap
73. ing and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fuAsrER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 224 MHz high speed external crystal HSE Up to 24 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Sta
74. istics llle 65 LSI oscillator characteristics lille eh 66 RAM and hardware registers 0 0 cee n 67 Flash program memory data EEPROM memory 67 UO static characteristics liliis n 68 Output driving current standard porte 70 Output driving current true open drain porte 70 Output driving current high sink porte 70 NRST pin characteristics 74 SPI characteristics 0 2 2 0 onua ida kenia i ban rn 76 Eesen 79 ADC characteristics 81 ADC accuracy with Rain lt 10kQ VppA EE 82 ADC accuracy with RAIN lt 10 kQ RAIN VDDA S Vennen dubai ugha pa Ze 82 EMS Gata EE 84 EMI dala sc S 85 ESD absolute maximum ratings res 85 Doc ID 14733 Rev 8 5 101 List of tables STM8S207xx STM8S208xx Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 6 101 Electrical sensitivities 86 80 pin low profile quad flat package mechanical data 88 64 pin low profile quad flat package mechanical data 4xvia t anana 89 64 pin low profile quad flat package mechanical datat xvipt aaaaa 90 48 pin low profile quad flat package mechanical dats 91 44 pin low profile quad flat package mechanical dats 92 32 pin low profile quad flat package mechanical data 93 Thermal characteristics lille 94 Document revision history 99 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx List of figures List of figur
75. itt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 HE Reserved area 24 bytes 0x00 5420 CAN MCR CAN master control register 0x02 0x00 5421 CAN MSR CAN master status register 0x02 0x00 5422 CAN TSR CAN transmit status register 0x00 0x00 5423 CAN_TPR CAN transmit priority register OxOC 0x00 5424 CAN DER CAN receive FIFO register 0x00 0x00 5425 CAN_IER CAN interrupt enable register 0x00 0x00 5426 CAN_DGR CAN diagnosis register OxOC 0x00 5427 CAN FPSR CAN page selection register 0x00 0x00 5428 CAN_PO CAN paged register 0 0x00 5429 CAN_P1 CAN paged register 1 0x00 542A CAN_P2 CAN paged register 2 0x00 542B beCAN CAN_P3 CAN paged register 3 0x00 542C CAN_P4 CAN paged register 4 0x00 542D CAN_P5 CAN paged register 5 0x00 542E CAN_P6 CAN paged register 6 0x00 542F CAN_P7 CAN paged register 7 0x00 5430 CAN_P8 CAN paged register 8 0x00 5431 CAN_P9 CAN paged register 9 0x00 5432 CAN_PA CAN paged register A 0x00 5433 CAN_PB CAN paged register B 0x00 5434 CAN_PC CAN paged register C 0x00 5435 CAN_PD CAN paged register D 0x00 5436 CAN_PE CAN paged register E ky Doc ID 14733 Rev 8 43 101 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map continued Address Block Register label Register na
76. keup Table 26 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Unit Flash in operating mode HSI clock after 61 5 Suppl hal d m A upply current in halt mode H POH Flash in powerdown mode HSI clock after 45 wakeup i Low power mode wakeup times Table 27 Wakeup times Symbol Parameter Conditions Typ Max Unit Se Wakeup time from wait note Wurt mode to run model fopu faster 16 MHz 0 56 Flash n operating 4 DG model MVR voltage regulator on Flash in powerdown 3 5 i Wakeup time active halt mode HSI after us WU AH mode to run mode Flash in operating Wakeup 5 48 model MVR voltage regulator off Flash in powerdown 50 9 model Wakeup time from halt Flash in operating mode 52 t 3 WU H mode to run mode Flash in powerdown mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 7 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH_CR1 register 6 Plus 1 LSI clock depending on synchronization 60 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Electrical characteristics Total current consumption and timing in forced reset state Table 28 Total current consumption and timing in forced reset state Symbol Parameter Conditions
77. ky STM8S207xx STM8S208xx Memory and register map Table 10 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name E Ox007F90 DMBKIRE DMbreakpoint1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1HRL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BKA2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BKA2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF E Gg Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 8 Memory map ky Doc ID 14733 Rev 8 45 101 Interrupt vector mapping STM8S207xx STM8S208xx 7 Interrupt vector mapping Table 11 Interrupt mapping Sak Description WH OTT Vector adres RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up fro
78. ld time o9 o9 90089 SDA SDA and SCL rise time 1000 300 ns t scL DA SDA and SCL fall time 300 300 tyScL Iwer START condition hold time 4 0 0 6 us tsuigta Repeated START condition setup time 4 7 0 6 tsuisTo STOP condition setup time 4 0 0 6 Hs STOP to START condition time Im STO STA bus free 4 7 1 3 us Cp Capacitive load for each bus line 400 400 pF 1 fmaster must be at least 8 MHz to achieve max fast Pc speed 400kHz Data based on standard 1 C protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL d Doc ID 14733 Rev 8 79 101 Electrical characteristics STM8S207xx STM8S208xx 80 101 Figure 40 Typical application with DC bus and timing diagram IC bus 100 Q MM SCL VDD VDD STM8S20xxx sna m ig e AMI SDA L START REPEATED i g START IsuSTA p e SDA PH He SDA tsu SDA ANY STOP 4 su STA STO 9 h STA n w SCKL Ih SDA o tw SCKH gt gt l SCK PH gt e tSCk lsu STO ai15385 1 Measurement points are done at CMOS levels 0 3 x Vpp and 0 7 x Vpp Doc ID 14733 Rev 8 d STM8S2
79. ler register 0x00 0x00 530D TIM2_ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2_CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 poe ed Reserved area 11 bytes ky Doc ID 14733 Rev 8 41 101 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map continued Address Block Register label Register name Wee 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIMS interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIMG status register 1 0x00 0x00 5323 TIM3_SR2 TIMG status register 2 0x00 0x00 5324 TIM3 EGR TIMS event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture compare enable register 1 0x00 0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 53
80. lication software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Doc ID 14733 Rev 8 17 101 Product overview STM8S207xx STM8S208xx 4 8 4 9 4 10 4 11 18 101 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down
81. llator 940 IDD AH active halt mode 16 MHz HA Powerdown mode LSI RC oscillator 140 128 kHz Off Operating mode Let RC oscillator 68 Powerdown mode 128 kHz 11 45 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 24 Total current consumption in active halt mode at Vpp 3 3 V Conditions Symbol Parameter Main voltage Typ Unit regulator Flash mode Clock source MVR O HSE crystal osc 16 MHz 600 Operating mode LSI RC osc 128 kHz 200 n HSE crystal osc 16 MHz 540 IDD AH Se H Powerdown mode pA active halt mode LSI RC osc 128 kHz 140 Operating mode 66 Off k LSI RC osc 128 kHz Powerdown mode 9 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register ky Doc ID 14733 Rev 8 59 101 Electrical characteristics STM8S207xx STM8S208xx Total current consumption in halt mode Table 25 Total current consumption in halt mode at Vpp 5 V T4 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 63 5 i See clock after wakeup upply current in halt mode u TR Flash in powerdown mode HSI 6 5 30 clock after wa
82. lows for LOFP64 10 x 10 mm 46 C W TJmax 82 C 46 C W x 443 mW 82 C 20 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 Doc ID 14733 Rev 8 95 101 STM8 development tools STM8S207xx STM8S208xx 11 96 101 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STMB8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 micr
83. lternate function is shown twice it indicates an exclusive choice not a duplication of the function 4 CAN RXand CAN TX is available on STM8S208xx devices only Doc ID 14733 Rev 8 d 26 101 STM8S207xx STM8S208xx Pinouts and pin description Figure 7 LQFP 32 pin pinout Q Q 9 x aa 9 n Z ET Y n a 9 was ote E E rat N i ECL OE VUE o Se M i QN ole oi SS Jal eezz EEEEELOE 300000 ESO2LLLLL e O OD st CO Oe OD adadad aqaaaaaaada 32 31 30 29 28 27 2625 NRST Die 240 PC7 HS SPI MISO OSCIN PA1 rj2 230 PC6 HS SPI MOSI OSCOUT PA2 03 220 PC5 HSy SPI SCK Vss O14 21H PC4 HS TIM1_CH4 VCAP OS 200 PC3 HS TIM1_CH3 Vpp Cp 190 PC2 HS TIM1_CH2 Vppio 07 1810 PC1 HS TIM1_CH1 AIN12 PF4 CS 170 PES SPI NSS 9 10111213141516 10 st OQ e Oo A AN AAAA EE EE E E E WD st oO ole CH z22222 xac Jrzzz OO oc oO t IT ous 999 aWSerer CES EBEE 1 HS high sink capability 2 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Table 5 Legend abbreviations Type l Input O Output S Power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2
84. m OPTx and a complemented one NOPTXx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 12 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 12 Option bytes Option bits Factory Option Option Addr don 5 E ie default Mense og 6 5 4 3 2 1 0 setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot OPT1 UBC 7 0 00h 4802h code UBC Nopr4 NUBC 7 0 FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function 4804n remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 4805h OPT3 Reserved 00h Watchdog EN HW HW HAUT option NLSI NIWDG NWWDG NWWDG 4806h NOPT3 Reserved _EN HW HW HAUT FER EXT CKAWU PRS PRS 4807h OPT4 Reserved 00h CLK SEL C1 CO Clock option NEXT NCKAWUS NPR NPR 4808h NOPT4 Reserved FFh CLK EL SC1 SCO 4809h HSE clock OPT5 HSECNT 7 0 00h 480Ah __ Startup NOPT5 NHSECNT 7 0 FFh 480Bh OPT6 Reserved 00h Reserved 480Ch NOPT6 Reserved
85. m halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes veel 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 beCAN beCAN RX interrupt Yes Yes 0x00 8028 9 beCAN beCAN TX ER SC interrupt 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIM1 a R 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 13 TIM2 TIM2 update overflow 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 TIM3 Update overflow 0x00 8044 16 TIM3 Capture compare 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 Se DC interrupt Yes Yes 0x00 8054 20 UART3 Tx complete 0x00 8058 21 UARTS Receive register DATA FULL 0x00 805C 22 ADC2 ADC2 end of conversion 0x00 8060 23 TIM4 TIM4 update overflow 0x00 8064 24 Flash EOP WR_PG_DIS 0x00 8068 R served 0x00 806C to 0x00 807C 1 Except PA1 46 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular for
86. me Heset status 0x00 5437 DECAN CAN_PF CAN paged register F cont d 0x00 5438 to 0x00 57EF Reserved area 968 bytes Table 10 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name nese Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7FOB to 0x00 7F5F Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ae ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 OxFF 0x00 7F78 to 0x00 7F79 Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to 0x00 7F8F Reserved area 15 bytes 44h01 Doc ID 14733 Rev 8
87. mless integration of the Cosmic and Raisonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code STM8 toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Haisonance C compiler for STM8 Available in a free version that ou
88. nabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Doc ID 14733 Rev 8 13 101 Product overview STM8S207xx STM8S208xx 4 2 4 3 14 101 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debug
89. nd hardware registers Table 34 RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 18 on page 55 for the value of Vir ay Flash program memory data EEPROM memory General conditions T4 40 to 125 C Table 35 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage Vo all modes execution write erase fopu lt 24 MHz iu ue y Standard programming time including erase for byte word block 6 6 6 ms luos 1 byte 4 bytes 128 bytes Fast programming time for 1 block 128 bytes JR NE lerase Erase time for 1 block 128 bytes 3 3 3 ms i 2 Erase write cycles Ty 85 C 10k Naw program memory cycles Erase write cycles data memory Ta 125 C 300k 1M Data retention program memory after 10 k erase write cycles at Tret 55 C 20 Ta 85 C Data retention data memory after 10 EEG RET k erase write cycles at TA 85 C NN 20 ere Data retention data memory after 300k erase write cycles at Tret 85 C 1 Ta 125 C Supply current Flash programming or 2 WA DD erasing for 1 to 128 bytes Data based on characteri
90. ocontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx STM8 development tools 11 2 11 2 1 11 2 2 11 3 Software tools STMB8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides sea
91. pare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1 DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 RECH Reserved area 147 bytes 40 101 Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name eeh 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture compare enable register 1 0x00 0x00 5309 TIM2_CCER2 TIM2 capture compare enable register 2 0x00 0x00 530A TIM2 TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530C0x TIM2_PSCR TIM2 presca
92. plication and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 46 EMS data Symbol Parameter Conditions Level class V Voltage limits to be applied on any I O pin to SEN nu K SES C 2B FESD j i MASTER induce a functional disturbance conforming to IEC 1000 4 2 Fast transient voltage burst limits to be Vpp 5 V Ta 25 C Verta applied through 100pF on Vpp and Vss pins fyaster 16 MHz 4A to induce a functional disturbance conforming to IEC 1000 4 4 Doc ID 14733 Rev 8 i STM8S207xx STM8S208xx Electrical characteristics Electromagnetic interference EMI Emission tests conform to the SAE J 1
93. pu fMASTER 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 22 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fopy fmaster 24 MHz HSE crystal osc 24 MHz 2 0 Ta 105 C HSE user ext clock 24 MHz 1 8 47 HSE crystal osc 16 MHz 1 6 ES fopu fuasrER 16 MHz HSE user ext clock 16 MHz 1 4 4 4 upply IDD weEl current in HSI RC osc 16 MHz 1 2 1 6 mA wait mode fopu fmastep 128 125 kHz HSI RC osc 16 MHz 1 0 rn fmastep 128 15 25 uer RC osc 16 MHz 8 2 0 55 EH fmastep 128 15 625 inc osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 58 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Electrical characteristics Total current consumption in active halt mode Table 23 Total current consumption in active halt mode at Vpp 5 V T4 40 to 85 C Conditions Symbol Parameter Mainvoltage Typ Max Unit regulator Flash mode Clock source MVR HSE crystal oscillator 16 MHz 1999 Operating mode TT i oscillator 128 kHz 200 ep m S ill Supply current in HSE crystal osci
94. rt E PE_DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register 0x00 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register 0x00 0x00 5025 Port H PH_DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch register 0x00 0x00 5029 PI IDR Port input pin value register 0x00 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI_CR1 Port control register 1 0x00 0x00 502C PI_CR2 Port control register 2 0x00 Doc ID 14733 Rev 8 35 101 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map Address Block Register label
95. rtup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 3 Peripheral clock gating bit assignments in CLK PCKENR1 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 beCAN PCKEN23 ADC PCKEN16 TIM2 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM3 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 DC PCKEN24 Reserved PCKEN20 Reserved Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Product overview 4 6 4 7 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or
96. sity devices in the STM8S microcontroller family Reference Manual RM0016 All devices of the STM8S20xxx performance line provide the following benefits Reduced system cost Integrated true data EEPROM for up to 300 k write erase cycles A High system integration level with internal clock oscillators watchdog and brown out reset Performance and robustness 20 MIPS at 24 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system Short development cycles A Applications scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation and a wide choice of development tools Product longevity Advanced core and peripherals made in a state of the art technology Afamily of products for applications with 2 95 V to 5 5 V operating supply Doc ID 14733 Rev 8 ky STM8S207xx STM8S208xx Description Table 2 STM8S20xxx performance line features 2 23 o 3 amp 2 2 E n o E o E g o D S SS 5 o gt Ey p Di E e rz t 2 o t 2 m MS S B3 29 z E e x cen S Device 3 EOI S 2 8 8 Sse O g E c s 2 z 2 S E e S a z z D E E lt 2 z gt SH Wi lt 7 O E 6 yo ul t o o x n 9 O I E S8 2 S g 5 8 k FE 3 LE STM8S207MB 80 68 37 9 3 16 18 128K 2048 6K STM8S207M8 80 68 37 9 3 16 18 64K 2048 6K STM8S207RB 64 52 36
97. the value for 1 kuss given in Table 17 above and the value for Oja given in Table 56 Thermal characteristics Refer to Section 10 2 Thermal characteristics on page 94 for the calculation method In low power dissipation state T4 can be extended to this range as long as Ty does not exceed T ymax see Section 10 2 Thermal characteristics on page 94 5 TJmax is given by the test limit Above this value the product behavior is not guaranteed d 54 101 Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Electrical characteristics 9 3 1 d Figure 12 fcpumax versus Vpp fcpu MHz 24 FUNCTIONALITY m E EN NOT GUARANTEED ASANO IN THIS AREA i T FUNETIONALITY _ _ GUARANTEED 8 E l 4 PE e M E Jii a 0 I I SUPPLY VOLTAGE V Table 18 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate EA e tvpp us Vpp fall time rate 2 Reset release AS TEMP delay Vpp rising 170 ms Power on reset Vir threshold 2 65 2 8 2 95 V Brown out reset Vir threshold 2 58 2 73 2 88 V Brown out reset Vuvs BOR 70 mV hysteresis 1 Guaranteed by design not tested in production VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin Geer is specified in Table 17 Care should be taken to limit the
98. tputs up to 16 Kbytes of code For more information see www raisonance com e STMS8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family Doc ID 14733 Rev 8 97 101 Ordering information STM8S207xx STM8S208xx 12 98 101 Ordering information Figure 49 STM8S207xx 208xx performance line ordering information scheme Example STM8 Product class STM8 microcontroller S Family type S Standard 208 M Sub family type 208 Full peripheral set 207 Intermediate peripheral set Pin count K 32 pins S 44 pins C 48 pins R 64 pins M 80 pins B T 6 B TR Program memory size 6 32 Kbyte 8 64 Kbyte B 128 Kbyte Package type T LQFP Temperature range 3 40 C to 125 C 6 40 C to 85 C Packa
99. ure 9 Supply current measurement conditions 5Vor3 3V P m Vpp Ge D L1 Vppa Vppio Vss Vssa Vssio WNN Doc ID 14733 Rev 8 y STM8S207xx STM8S208xx Electrical characteristics 9 1 5 Pin loading conditions 9 1 6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Figure 10 Pin loading conditions 41 STMB8 pin 50PF ASS 9 1 7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11 Figure 11 Pin input voltage l STM8 pin ky Doc ID 14733 Rev 8 51 101 Electrical characteristics STM8S207xx STM8S208xx 9 2 52 101 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 14 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including VppA and Vppio 0 3 6 5 Input voltage on true open drain pins PE1 PE2 Vss 0 3 6 5 V VN Input voltage on any other pin Vas 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 em IVssx
100. variation vs Vpp at 4 temperatures 00 0005 65 Typical LSI frequency variation vs Vpp 25 C 2 6k eee 66 Typical Vu and Vj vs Vpp 4 temperatures 2 0 2 ee 69 Typical pull up resistance vs Vpp 4 temperatures 0000 cee eee eee 69 Typical pull up current vs Vpp 4 temperatures 69 Typ VoL 9 Vpp 5 V standard porte 71 Typ VoL Vpp 3 3 V standard ports 0 2 eee 71 Typ VoL 9 Vpp 5 V true open drain porte 71 Typ VoL 9 Vpp 3 3 V true open drain porte 72 Typ VoL 9 Vpp 5 V high sink porte 72 Typ VoL 9 Vpp 8 3 V high sink porte 72 Typ Vpp Vou 9 Vpp 5 V standard porte 73 Typ Vpp Vou 9 Vpp 3 3 V standard porte 73 Typ Vpp Vou 9 Vpop 5 V high sink porte 73 Typ Vpp Vou 9 Vpop 3 3 V high sink porte 74 Typical NRST Vu and Vj vs Vpp 4 temperatures 74 Typical NRST pull up resistance vs Von 4 temperatures 75 Typical NRST pull up current lpu VS Vpp Atemperatures 75 Recommended reset pin protection ees 75 SPI timing diagram slave mode and CPHA 0 2 0 0 ee 77 SPI timing diagram slave mode and CPHA 2 21 77 SPI timing diagram master mode RTT NE AE 78 Typical application with DC bus and timing diagram pu c d Ge een mt aerate dE 80 ADC accuracy characteristics liliis 83 Typical application with ADC lsssssssseee RR Ine 83 80 pin low profile quad flat package 4Axvi i een 88 64 pin low
101. w watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 24 MHz to 128 kHz prescaler 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilisation time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash data EEPROM memory 1 wait state is required if fopy gt 16 MHz 0 No wait state 1 1 wait state OPTBL BL 7 0 Bootloader option byte This option is checked by the boot ROM code after reset Depending also on the content of the reset vector the CPU jumps to the bootloader or to the reset vector Refer to STM8S bootloader manual for more details Doc ID 14733 Rev 8 49 101 Electrical characteristics STM8S207xx STM8S208xx 9 9 1 50 1
102. x Unit f Master mode 0 10 SCK SPI clock frequency MHz 1 te Sck Slave mode 0 6 ec sPI clock rise and fall time Capacitive load C 30 pF 25 sch tsunss NSS setup time Slave mode 4 X MASTER thuss NSS hold time Slave mode 70 1 W SCKH SCK high and low time Master mode tsck 2 15 tsck 2 15 tw SCKL t 1 Master mode 5 su MI 4 Data input setup time tsusi Slave mode 5 t 1 Master mode 7 ns h MI 4 Data input hold time thisn Slave mode 10 taso Data output access time Slave mode 3 X tuAsTER tasso 9 Data output disable time Slave mode 25 tyso Data output valid time Slave mode after enable edge 75 Luc Data output valid time Master mode after enable edge 30 Kasel Slave mode after enable edge 31 S9 Data output hold time baue Master mode after enable edge 12 Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 76 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S208xx Electrical characteristics Figure 37 SPI timing diagram slave mode and CPHA 0 NSS input lc SCK Input OO 32 wh id o li Oo CH A e tv SO gt n t SCK t ta SO lt lt
103. xternal capacitor updated Figure 18 replaced Figure 19 updated Table 34 RAM and hardware registers updated Figure 22 and Figure 35 added Figure 40 Typical application with 12C bus and timing diagram 1 Removed Table 56 Junction temperature range Added link between ordering information Figure 49 and STM8S20xx features Table 2 d Doc ID 14733 Rev 8 STM8S207xx STM8S208xx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of su
104. zation results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte ky Doc ID 14733 Rev 8 67 101 Electrical characteristics STM8S207xx STM8S208xx 9 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 36 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 0 3 x Von V Input high level Vpp 5V Vin voltage 0 7 x Vpp Von 0 3 V V Vhys Hysteresis 700 mV Rpu Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 ns ae Rise and fall time Load 50 pF PF 10 90 Standard and high sink I Os 425 B ns Load 50 pF Input leakage lkg current Vss Vin Vpp 1 yA analog and digital Analog input likg ana See ker Vss S Vin S Vpp 250 nA Leakage current in er likg inj aie vo Injection current 4 mA 1 uA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data based on characterization results not tested in production 68 101 Doc ID 14733 Rev 8 D STM8S207xx STM8S2

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