AD9286-500EBZ_UG-191 (Rev. A)
Contents
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4. ANALOG DEVICES AD9286 500EBZ User Guide UG 191 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Evaluating the AD9286 Analog to Digital Converter FEATURES Full featured evaluation board for the AD9286 SPI interface for setup and control Support LVDS output mode option External or on board oscillator options Balun transformer or amplifier input drive options Switching power supply VisualAnalog and SPIController software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source if not using the on board oscillator Two switching power supplies 6 0 V 2 5 A CUI EPS060250UH PHP SZ provided PC running 32 bit Windows XP Window Vista or Windows 7 USB 2 0 port recommended USB 1 1 compatible AD9286 evaluation board HSC ADC EVALCZ FPGA based data capture kit SOFTWARE NEEDED VisualAnalog SPIController DOCUMENTS NEEDED AD9286 data sheet HSC ADC EVALCZ data sheet AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding High Speed ADC Testing and Evaluation GENERAL DESCRIPTION This user guide describes the AD9286 evaluation board which provides all of the support circuitry required to operate
5. Precision thick film chip 0402 resistor Film SMD 0603 resistor 0 1 UF 4 7 pF 1000 pF S2A TP LNJ308G8TRA green HSMS 2822 BLK 100 MHz 1 6A BNX016 01 RAPC722X Z5 530 3625 0 SAMTECTSW10608G S3PIN TSW 102 08 G S SMA J P X ST EM1 2 2 uH 100 nH 6469169 1 300 0 100 00 10 kO 1 1 100 00 Rev Page 22 of 24 Reference Designator Manufacturer Part No 9286CE01A Murata GRM21BR61C106KE15L Murata GRM155R60J105KE19D Murata GRM21BR71H105KA12L Murata GRM155F51C104ZA01D Murata GRM033R60J104KE19D Murata GRM1555C1H4R7CZ01D Murata GRM1555C1E102JA01D Micro Commercial Components Corp S2A TP Panasonic LNJ308G8TRA Avago Technologies HSMS 2822 BLK Panasonic EXC ML20A390U Tyco Electronics MINISMDC160F 2 Murata BNX016 01 Switchcraft RAPC722X Wieland Z5 530 3625 0 Samtec TSW 103 08 G S Samtec TSW 102 08 G S Samtec SMA J P X ST EM1 Coilcraft LPS4012 222MLC Bourns CW201212 R10J Tyco 6469169 1 Panasonic ERJ 2GEJ301X Panasonic ERJ 3EKF1003V Panasonic ERJ 6GEY JO O Panasonic ERJ 2RKF 1002X Panasonic ERJ 2GEJ112X Panasonic ERJ 2RKF1003X Panasonic ERJ 3GEYOROOV Qty Reference Designator Manufacturer Part No 22 R405 R407 R408 R414 Film SMD 0402 resistor Panasonic ERJ 2GEOROOX R415 R416 R417 R449 R450 R504 R507 R508 R509 R510 R516 R517 R520 R521 R522 R523 R601 R602 4 R410 R411 R412 R413 Film SMD 0402 resistor 330 Panasonic ERJ 2GEJ330X
6. 1 R436 Precision thick film chip 0402 resistor 61 90 Panasonic ERJ 2RKF61R9X 1 R437 Precision thick film chip 0402 resistor 27 4 Q Panasonic ERJ 2RKF27R4X 4 R438 R439 R440 R441 Precision thick film chip 0402 resistor 200 Q Panasonic ERJ 2RKF2000X 2 R442 R443 Film SMD 0402 resistor 240 Panasonic ERJ 2GEJ240X 4 R505 R506 R518 R519 Precision thick film chip 0402 resistor 24 9 Q Panasonic ERJ 2RKF24R9X 2 RN601 RN602 Network 16 pin 8res surface mount 00 Panasonic EXB 2HVROOOV resistor 1 T401 XFMR RF MINICD542 ADT1 1WT Minicircuits ADT1 1WT 2 T502 T504 XFMR RF 1 1 6 pin special ETC1 6P MABA 007159 000000 Macom MABA 007159 000000 1 U101 Compact 600 mA 3 MHz TSOT 5 ADP2108AUJZ 3 3 R7 Analog Devices step down dc to dc converter ADP2108AUJZ 3 3 R7 1 0102 600 3 MHz TSOT 5 ADP2108AUJZ 1 8 R7 Analog Devices step down dc to dc converter ADP2108AUJZ 1 8 R7 1 U201 Analog to digital converter AD9286BCPZ 500 Analog Devices AD9286BCPZ 500 1 U301 IC tiny logic UHS dual buffer NC7WZO7P6X Fairchild NC7WZO7P6X 1 0302 IC tiny logic UHS dual buffer NC7WZ16P6X Fairchild NC7WZ16P6X 1 0401 Ultralow distortion differential ADC ADA4937 1YCPZ R7 Analog Devices driver ADA4937 1YCPZ R7 Rev A Page 23 of 24 NOTES ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection t
7. I m gt DATA 1 69 16979 ON Td 1 69 16979 9N ld 8d 1198 8d 0 05 FIFO Board Connector Figure 19 Rev A Page 15 of 24 050 97560 AO 2000000 OOOOOO 000000 OO J Jj N 20 9000 BOG BIO NU Ma Figure 20 Top Side Rev Page 16 of 24
8. Rev A Page 13 of 24 810 97560 MYOMLAN LNdLNO 0 god O06 80d 209NH 0 0L Z dod Z09NH 0 Le 9 92 Z09NH 0 O S ded Z09NH 0 Ma o L v Wed ara 209NH 0 _ nAnT s n asd o vL ded 98 Z09NH 0 g9q TIM Wea 209NH 0 8 d O 91 L 0 Wo 8 ood 09 8 ood 0 v ood root ood ood O gt 2 2 m UJ 0 o 6 8 Ara vod LOONY 0 vid o 0L n dvd vid LO9NH 0 A y y A Ng EE o m 9 wsa ved 109 0 y O Zh S ved LO9NH 0 O y vrd LO9NH 0 a 55 o L09NY 0 v9q O A nza LO9NH 0 AJ Y y O 91 I L09NH AGOW SONO MHOMLAN YOLSISSY WHO ec AGOW SAAT HOF MHOMLAN HOLSIS3H WHO 0 V TANNVHO Figure 18 Output Buffer Circuits Rev A 14 of 24 610 97560 SNOILO3NNOO 60415 6916979 v E c 0 m gt v gt 1 6916979 ano H3QvaH ONId vra O vod o o goq o 9fr1d 1nd aso 6916979 6916979 vod o O aso gsn ood v
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10. check the following e Make sure an appropriate filter is used on the analog input e Make sure the signal generators for the clock and the analog input are clean low phase noise e Change the analog input frequency slightly if noncoherent sampling is being used e Make sure the SPI configuration file matches the product being evaluated If the FFT window remains blank after Run is clicked do the following e Make sure the evaluation board is securely connected to the HSC ADC EVALCZ board e Make sure the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC ADC EVALCZ board If this LED is not illuminated make sure the U4 switch on the HSC ADC EVALCZ board is in the correct position for USB configuration e Make sure the correct FPGA program was installed by selecting the Settings button in the ADC Data Capture block in VisualAnalog Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part If VisualAnalog indicates that the FIFO Capture timed out do the following e Make sure all power and USB connections are secure e Probe the DCOA signal at RN601 on the evaluation board and confirm that a clock signal is present at the ADC sampling rate Rev A Page 8 of 24 EVALUATION BOARD SCHEMATICS AND ARTWORK 2014 10141 sent anro anot gt 0619 6219 dad SVITV 53H
11. the AD9286 in its various modes and configurations The application software used to interface with the device is also described The AD9286 data sheet provides additional information and should be consulted when using the evaluation board All documents and software tools are available at the FIFO page For additional information or questions send an email to highspeed converters analog com TYPICAL MEASUREMENT SETUP 8104 555 e 9286CE01A DEVICES 11723 sorrnnmmmn V s h x s s gt a r 5 P u eean e coeca 09346 001 Figure 1 AD9286 Evaluation Board and HSC ADC EVALCZ Data Capture Board PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev A Page 1 of 24 TABLE OF CONTENTS I lili Sa a daana a aa baa Equipment nni Documents Need l uy aaa naea General Description u kan Typical Measurement Setup REVISION STO arc Evaluation Board Hardware Power SUP PHOS sn REVISION HISTORY 6 14 Rev 0 to Rev A Changes to Figure Pu Chances to Figure Aaron Changes to Figure Changes to Figure iei Changes
12. to Figure aros Changes to lan Chansesto Bioute 19 sinus REVISION HISTORY 5 11 Revision 0 Initial Version Rev A Page 2 of 24 1 u een RM 1 is na ER 1 Default Operation and Jumper Selection Settings 4 ads 1 Evaluation Board Software Quick Start Procedures 5 ER 1 The Board nee E 1 Using the Software for Testing nn unde re 2 Evaluation Board Schematics and Artwork 9 3 Orderme een een 3 Bill or Materials a anne 9 a 10 11 P 12 N 13 14 I5 EVALUATION BOARD HARDWARE The AD9286 evaluation board provides all of the support circuitry required to operate the AD9286 in its various modes and configurations Figure 2 shows the typical bench charac terization setup used to evaluate the ac performance of the AD9286 It is critical that the signal source used for the analog input and clock have very low phase noise lt 1 ps rms jitter to realize the optimum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance See the Evaluation Board Software Quick Start Procedures section to get started and see Figure 13 to Figure 25 for the complete sch
13. 01 C302 C401 C403 C404 C416 C502 C505 C506 C507 C508 C510 C511 C513 C514 C515 C516 C202 C204 C206 C208 C210 C212 C214 C216 C218 C220 C222 C406 C504 C512 CR101 CR102 CR103 CR501 CR503 E101 E102 E105 E107 E109 E110 E111 E112 F101 FL101 J101 J102 J103 J104 J105 J106 J201 J202 J204 J401 J405 J502 1504 L101 L103 L102 L104 P1 P2 R101 R102 R103 R104 R105 R301 R306 R307 RBIAS R302 R303 R305 R304 R308 R309 R403 0805 monolithic capacitor Ceramic 0402 monolithic capacitor Ceramic 0805 X7R capacitor Ceramic 80 20 16 V Y5V 0402 Capacitor Ceramic 6 3 V Y5V 0201 capacitor High Q microwave chip NPO 0402 Capacitor Ceramic 25 V 5 COG 0402 capacitor Recovery rectifier diode DO214AA3 Green surface mount 0603 LED RF Schottky diode MINIPAK1412 2 Inductor 0805 ferrite bead Fuse F1812 polyswitch PTC device Filter noise suppression LC combined type FLBNX01 PCB powerjack mini 0 08 in R A T H connector PCB header 6 position connector PCB berg header ST male 3 position connector PCB header 2 position connector PCB SMA ST edge mount connector Shielded power inductor LSMSQ154H47 SMD L9075 inductor CB 60 pin RA connector CNTYCO1469169 1 Film SMD 0402 resistor Precision thick film chip 0603 resistor Jumper SMD 0805 SHRT resistor Precision thick film chip 0402 resistor Film SMD 0402 resistor
14. 286 board has on chip circuitry to distribute a single clock to each interleaved ADC channel Alternatively the AD9286 evaluation board supports driving each internal ADC core with its own separate half speed clock This is useful in applications where the user wants to externally control the clock timing per channel To enable separate clocking write a value 0 to SPI Address 0x09 and place a jumper across J204 to tie AUXCLKEN to DRVDD Non SPI Mode For users who want to operate the DUT without using SPI remove the shorting jumpers on J302 This disconnects the CSB SCLK and SDIO PWDN pins from the SPI control bus allowing the DUT to operate in non SPI mode In this mode the SDIO PWDN pin takes on an alternate function to enable power down functionality To enable the power down feature add a shorting jumper across J202 at Pin 2 and Pin 3 to connect the SDIO PDWN pin to DRVDD DNI 00 00 33 Q 33 Q 33 Q 33 Q 00 00 00 00 Rev A Page 4 of 24 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9286 evaluation board Both the default and optional settings are described CONFIGURING THE BOARD Before using the software for testing configure the evaluation board using the following steps 1 Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2 2 Connect one 6 V 2 5 A switching power supply su
15. BILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention
16. Graph AD9286 FFT 2 2 2011 5 17 48 PM File m aje ela 2 ar amp Ch AFFT Device 4D9286 Date 2 2 2011 Time 5 17 48 PM 25M 50M 75M 100M 125M 150M 175M 200M 225M Sample Frequency 500 MHz Samples 32768 SNA 47 898 dB SNRFS 47 895 dB SINAD 46 638 dBc DC Frequency 0 MHz DC Power 34 554 dBFS Fund Frequency 10 3 MHz Fund Power 0 002 dBFS f 2 4 6 Fund Bins 21 Harm 2 Power 56 194 dBc 3 Harm 3 Power 74 302 dBc Harm 4 Power 58 031 dBc Harm 5 Power 68 188 dBc Harm 6 Power 58 872 dBc Worst Other Frequency 82 398 MHz Worst Other Power 59 359 dBFS Noise Hz 131 875 dBFS Hz Average Bin Noise 30 04 dBFS THD 52 627 dBc SFDR 56 194 dBc 09346 012 Figure 12 Graph Window of VisualAnalog 2 Repeat this procedure for Channel B 3 Click the disk icon within the Graph window to save the performance plot data as a csv formatted file Troubleshooting Tips If the FFT plot appears abnormal do the following e Ifyou see a normal noise floor when you disconnect the signal generator from the analog input be sure you are not overdriving the ADC Reduce the input level if necessary e VisualAnalog click the Settings button in the Input Formatter block Check that Number Format is set to the correct encoding offset binary by default Repeat for the other channel If the FFT appears normal but the performance is poor
17. HON38 74 o 0 poly WHO6E 8219 1219 185 7 HON38 L OA AE E WHO6E 2 L 0113 KK 5 E Anro X19 AGE WHO6E 9219 9219 O3H 110 A 6013 501 AlddNS DA lt L NOLLO3NNOO YOLVWINDAY lt SONILLAS HIdNNF 9017 8017 0 9Z9 0 S SZ 9 lt 81 ao net Pt ano C nee 2010 LAdNI AIdANS H3MOd DA an WHO6E BERO fh 2013 an WHO6E zio A an WHO6E 6019 O3H X19 A fi 2019 an WHO6E 1019 d 1019 008 1019 10 91 NIA 10114 ano ano 70 A 0119 ms 3001 NIA HNOOL ola 9011 eorn eo 14 8 LZPnvsoredav ano ano 59 19 A z ano ano ano a4 8019 9010 sold sms 3001 NIA HNOOL re 2011 1011 23 88 SHOLVINOAY A1ddnS X22L04V8 1013 TIO LAdNI 5 H3MOd Ant 219 Ant 7019 9115 019 115 2019 NIA Figure 13 Board Power Inp
18. Window Routine DC Corr T X Window Help ADC Data Capture Input Formatter Router Window Routine FFT Graph AD3286 FFT m 2 F Figure 6 VisualAnalog Main Window Rev A Page 6 of 24 09346 006 Setting Up the SPIController Software After the ADC data capture board setup is complete set up the SPIController software using the following procedure 1 Open the SPIController software by selecting Start gt SPIController or by double clicking the SPIController software desktop icon If prompted for a configuration file select the appropriate one If not check the title bar of the window to determine which configuration is loaded If necessary choose Cfg Open from the File menu and select the appropriate file based on your part type Note that the CHIP ID 1 field should be filled to indicate whether the correct SPI controller configuration file is loaded see Figure 7 gt SPIController 1 0 72 3 USB Ezusb 0 CS 1 AD9286_BBit_500MSspiRO3 cfg AD9286_8Bit_500 EBR File Config Help CHIP PORT CFG 0 LSB First Controller will also be Reset updated from DLIT CHIPID 1 Read 4D9286 8 bit 500 MSPS CHIP GRADE 2 Read 500 MSPS 2 2 2011 5 02 01 PM 09346 007 Figure 7 SPIController CHIP ID 1 Box 2 Click the New DUT button in the SPIController window see Figure 8 gt SPiController 1 0 72 3 USB Ezu
19. ass filter with 50 terminations is recommended Analog Devices Inc uses and K amp L Microwave Inc band pass filters The filters should be connected directly to the evaluation board If an external clock source is used it should also be supplied with a clean signal generator as previously specified Typically most Analog Devices evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform HSC ADC EVALCZ for data capture 2 7 lt a j 8 2 Ka RUNNING IT ve E VisualAnalog O sa AND SPlController HSC ADC EVALCZ 2222 1 USER SOFTWARE 09346 002 Figure 2 Evaluation Board Connection Rev A Page 3 of 24 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9286 evaluation board Power Circuitry Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and J101 Analog Input The analog input on the evaluation board default configuration uses a single transformer input with a 50 impedance The default analog input configuration supports analog input fre quencies of up to 200 MHz This input network is optimized to support a wide frequen
20. ation board the device is powered down To wake up the device the SDIO PWDN pin must be pulled low This occurs automatically by VisualAnalog after you complete Step 1 VisualAnalog New Canvas New Existing Recent Categories Templates 403215 L C AD3226 C 4D3223 Average FFT Two Tone Average AD3230 Two Tone AD3233 09235 4D9236 C 09237 4093244 AD3245 C AD3246 409255 C ADS261 09265 AD9266 09285 8 Bit 500 MSPS device found 09346 003 Figure 3 VisualAnalog New Canvas Window 2 After the template is selected a message appears asking if the default configuration can be used to program the FPGA see Figure 4 Click Yes to close the window VisualAnalog i Visual nalog will now attempt to program the on board FPGA with a default file for the 4D9286 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Before clicking Yes please make sure the HSC ADC EVALC is powered with the correct supply and that the board is connected to the computer Also make sure the dipswitch U4 on the HSC 4DC EVALC is set to the following configuration M ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light Do not show this message again 09346 004 Figure 4 VisualAnalog Default Configuration Message 3 change features to settings other than the default setti
21. ch as the CUI Inc EPS060250UH PHP SZ to the AD9286 board 3 Connect one 6 V 2 5 A switching power supply such as the supplied CUI EPS060250UH PHP SZ to the HSC ADC EVALCZ board 4 Connect the HSC ADC EVALCZ board to the PC with a USB cable 5 Onthe ADC evaluation board confirm that six jumpers are installed as described as follows e J103 Pin 2 and Pin 3 clock with regulator e J104 Pin 2 and Pin 3 amp with regulator e J105 Pin 2 and Pin 3 DRVDD with regulator e J106 Pin 2 and Pin 3 AVDD with regulator e 7201 Pin and Pin 2 SCLK SPI e J202 Pin 1 and Pin 2 SDIO SPI 6 Onthe ADC evaluation board use a clean signal generator with low phase noise to provide an input signal to the desired A and or channel s Use a 1 m shielded RG 58 50 coaxial cable to connect the signal generator For best results use a narrow band band pass filter with 50 Q terminations and an appropriate center frequency Analog Devices uses TTE Allen Avionics and K amp L band pass filters USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the board set up the ADC data capture using the following steps 1 Open VisualAnalog on the connected PC The appro priate part type should be listed in the status bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 3 Note that once power is applied to the AD9286 evalu
22. cy band An alternate analog input configuration uses a single ADA4937 1 ultralow distortion amplifier which drives both VIN1 and VIN2 Special attention has been paid to provide a symmetrical layout between the two differential inputs to realize best performance To configure the analog input circuitry see Table 1 The nominal input drive level is 10 5 dBm to achieve 1 2 V p p full scale into 50 Q At higher input frequencies slightly higher input drive levels are required due to losses in the front end network VREF The AD9286 operates with a fixed 1 0 V reference This sets the analog input span to 1 2 V p p RBIAS RBIAS has a default setting of 10 R206 to ground and is used to set the ADC core bias current Note that using a resistor value other than a 10 1 resistor for RBIAS may degrade the performance of the device Table Analog Input Mode Configurations Analog Input Mode Passive Path Active Path 1 DNI do not install Clock Circuitry The default clock input circuit on the AD9286 evaluation board uses a simple transformer coupled circuit using a high bandwidth 1 1 impedance ratio transformer T501 that adds a very low amount of jitter to the clock path The clock input is 50 terminated and ac coupled to handle single ended sine wave types of inputs The transformer converts the single ended input to a differential signal that is clipped by CR501 before entering the ADC clock inputs The AD9
23. display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIA
24. ematics and layout diagrams These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing appli cation boards using the AD9286 POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V 2 A maximum output Connect the supply to the rated 100 V ac to the 240 V ac wall outlet at 47 Hz to 63 Hz The output from the supply is provided through a 2 1 mm inner diameter jack that connects to the printed circuit board PCB at J101 The 6 V supply is fused and conditioned WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL GENERATOR __ CLOCK SOURCE SIGNAL GENERATOR tier 9286CE01 REVA AD9286 ANALOG 9286CE01A gt DEVICES on the PCB before connecting to the low dropout linear regulators default configuration that supply the proper bias to each of the various sections on the board INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz SMA or HP8644B signal generators or an equivalent Use a 1 m shielded RG 58 50 coaxial cable for connecting to the evaluation board Enter the desired frequency and amplitude see the specifications in the AD9286 data sheet When connecting the analog input source a multipole narrow band band p
25. g oas asn las asn X19 AGE IdS AdLINDUID 185 Figure 15 SPl Interface Circuit Rev A Page 11 of 24 910 97260 NIM ING 0 8 HLVd NOWWOO 1nO dv ING LNO NUN 5 a5 5 1NO AWO 4074 1nO 3AISSVd LNO 3AISSVd LNO LNO dv 100 3AISSVd Anto LNO 3AISSVd 0v9 HLYd 3ALLOV LMIE LLOV HLVd 3AISSVd ING NIV V NIV V NIV Lovr 0vu 1075 d31N39 OL 431N39 STIN OVS 38 5 SIVIAS LNOAVI Figure 16 Analog Input Circuits Rev A Page 12 of 24 410 97260 0010 Nr ING anvo g 9199 118 2282 SdINH 419 usa 9199 JUVHS ING YVAN NOILVNINYSL IVNOILdO 2278 g gostHo E IMI LLOV g oN3 0SL 9199 g no anro vosr LAdNI 8 9019 IWNOILdO WLSX NI WLSX 4168 5 39019 HOLVTIVIOSO IWLSAYO TIVNOI LdO 000000 6S 20078 290005 ON 7080 NI 1V1SX 5 3nro 8059 M 18 c28c SdlWH 9 anro To LMI LLAV T 2090 gt Quvog NO NI3YOSYIIS a Y gt NI 1V1SX S 2098 ING Losr AYLINOYIO 419 NO 1V8 HINAX da31Nd3O OL YALNSO SIIN OVS 38 GINOHS SYNS LNOAVI UFSLN39 OL 83 1N39 SIIN 099 38 AINOHS SYNS LNOAVI Figure 17 Default Clock Path Input Circuits
26. lt circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood MA 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temporary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease
27. ngs click the Expand Display button located on the bottom right corner of the window to see what is shown in Figure 6 Detailed instructions for changing the features and capture settings can be found in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual After the changes are made to the capture settings click the collapse display button see the collapsed display in Figure 5 gt VisualAnalog Canvas AD9286 FFT File Edit View Canvas Tools Window Help al e 09346 005 Figure 5 VisualAnalog Window Toolbar Collapsed Display Rev Page 5 of 24 gt VisualAnalog Canvas AD9286 FFT a File Edit View Canvas Tools too Board Interfaces ADC Data Capture FIFO4 x Interface DEBUG ONLY Debug Graphics Process 24 Filter Process Miscellaneous Comment Models ADC Model Generic Model Processes 3 Array Math Average 021 Bit Processor E Bit Shifter ib Complex Waveform Merger Ii Complex Waveform Splitter Data Router DNL INL Analysis ul FFT ub FFT Analysis Hilbert Transform L J Histogram 111 1 Histogram Analysis vs 3 Input Formatter Inverse FFT gt Inverse Sinc XX Logic Analysis 9 Mixer 3 Output Formatter Peak Hold dB Power Phase 3 Resampler Resolution Formatter 7 Scalar Math Stop JH Subset Waveform Analysis
28. on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 2011 2014 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG09346 0 6 14 A DEVICES Rev A Page 24 of 24 www analog com
29. peed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information on the available settings gt SPIController 1 0 72 3 USB Ezusb 0 CS 1 AD9286_BBit_500MSspiRO3 cfg AD9286_8Bit_500 File Config Help Global CLOCK DCS 3 OUTPUT MODE 14 TEST IO D Clock Boost Output Disable Reset PN Long Gen DCS Enable Output Invert Reset PN Short Gen Data Format Select Output Test Mode Offset Binary C Twos Complement Gray Code User Test Mode y CLOCK TIMING 37 38 Course Adjustment ANALOG INPUT CTRL F Disconnect Input 0 0 ps DATA PATH OFFSET 10 Fine Adjustment Offset Adjust oops v v 09346 010 Figure 10 SPIController ADC 0 Page Rev A Page 7 of 24 5 Click the Run button in the VisualAnalog toolbar see Figure 11 VisualAnalap Canvas AD9286 FFT Fie inco 1 ux E lt 09346 011 Figure 11 Run Button VisualAnalog Toolbar Collapsed Display Adjusting the Amplitude of the Input Signal The next step is to adjust the amplitude of the input signal for each channel as follows 1 Adjust the amplitude of the input signal so that the funda mental is at the desired level examine the Fund Power reading in the left panel of the VisualAnalog Graph AD9286 FFT window See Figure 12
30. sb 0 CS 1 09286 File Config Help Fi ga a Global ADCBase 0 ADC 0 ADC CHIP PORT CFG 0 DEVICE INDEX 4 5 ADC LSB First in Reset Controller will also be updated from DUT CHIP ID 1 Reset Read AD3285 8 bit 500 MSPS 09346 008 Figure 8 SPIController New DUT Button 3 Inthe ADCBase 0 tab of the SPIController window you can access all global register settings see Figure 9 See the AD9286 data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information gt SPIController 1 0 72 3 USB Ezusb 0 CS 1 AD9286 8Bit 5OOMSspiRO3 cfg AD9286_8Bit_500 DBR File Config Help Global ADCBase 0 ADC O ADC 1 POWER 8 LVDS CTRL 15 VREF 18 el LVDS Swing Full Scale Adjust f Normal C Power Down 350mv 1 200 V CLOCK 9 OUTPUT PHASE 16 MISR 24 25 Invert DCO Read C Simultaneous 2 2 2011 5 09 04 PM 09346 009 Figure 9 SPIController ADC BaseO 4 Note that other settings can be changed on the ADCBase 0 page see Figure 9 and the ADC 0 and ADC 1 pages see Figure 10 to set up the part in the desired mode The ADCBase 0 page settings affect the entire part whereas the settings on the ADC 0 and ADC 1 pages affect the selected channel only See the AD9286 data sheet the AN 878 Application Note High S
31. ut and Supply Circuits Rev A Page 9 of 24 Ina 710 97560 10 A S 9 80 201 MSL ao lt 2 ayo lt Loannoo gor voer zz 2 gt gt 5 e 000 0 9024 god doa aid ERE B 5 8555 8 5 333 dia aed 5 Ee 5 DUAE h wea ard T geq vea ara a Wd 7 8p c E NIY nea aed SL Hae 75 ING g d 9 y good cay aav 1229 yona r 229 SASN 082 66 1 69 vr aprq vra woq Nu Pep 98c6QV 7 vid 0c NO AWO asa vsa wza ly wsa ved Te Sah m asa vsa vea Or ved Ze n ec NIV wed ved 9q vs 890 vga vsa A gc NIV cod 33 33 7E aa v s 25 ved ee 5 22 9002 41 08 585 Pes Lozn 2 ce oj o o o j ro o 5 o o O m m gt gt 2 2 O O Z 2 lt lt lt 5 500099 2 gge s IN 1 5 S 9 80 201 MSL amp 5 ng 1na1no lt 1 2 22 1na1no lt
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