FPD to Serdes (UR) Translator Chip DS99R421
Contents
1. ASN 65 JequunN 94102 p 20 2 agqepuooeg 90 PIS sseuxorulL 690070 JP no zo 1 90v u i PFS 0 6 Z zo 90 PIS ssouxoruL 600070 2222222222222 2 T zo 27 1 5 Date 4 23 2014 Page 28 of 39 National Semiconductor Corporation pueog ASN 5 j3ueuinooq Jezijeuese 4 065 pJeog ASN 65 6dlo Lic 2 SL vL1nOM 9 L1n0OM 2 a 9 001 TT 3 4 SSA 990 8 OLLQOM elg 61now 6 105 9 8INOY o 211102 SSA TAATA 0 2 eouepeduui papua wyo 05 t OOOO 45559 SSSS 292222 SASS NUNN 93900280 aon OO 00000 DDD DDD _ CICICICITSN CICICIC AliAmieuammimaas s fad 8 3 O 1 Co cO LE 888853888888088882. ou 1esn eu ui suomejedes 4 pue sjojr2edeo 5 4esn ay Jeu e jou S 4 sped azis g pue 090 510122022 Buljdnosap Lp2 L22 esiou 20 1 e jou uoee ur senes 510151501 0 7 e jou 4289 jo Asea 10 sped 9215 20 0 SaaS GLY OLY OWJA FHL NO SNOILdO Sasn 734 Date SSA 62 Suid Jeau Jni q4nro ANZ ezo SSA zz suid anzz 222 05349 SSA LN 40 uid Jn d3nio ANZ 70007 National Semiconductor Corporation SSA LN 40 21 uid Jn 4110 ANC 055 5 SSA LN 40 LL uid Jni q3nio anzz 552 lt lt VNVNV8 N N SSA SSA LN Jo uid eau LN 40 uid anzz anzz 989 Ho lizer Rx PCB Schematic Seria De
3. LVLO0OM 9LLNOY SLLNOY cLLNOw W194 OLLNOY 6LNOY LINOH 9LNOY SLNOY LLOOMS OLNOY SSVd lt PN eS OWN UN IN SOR HS AN SN IN gt 3201 021 6LLNOY 8LLNOY ZLLNOUY 9LLNOY SLLNOY VLLOOM LLOOM LLLOOM OLLOOM 6LNOY 8LNOY 4 91n038 SLNOY vino OLNOY SSVd SSA lt SSA Date 4 23 2014 Page 31 of 39 National Semiconductor Corporation Serializer Tx PCB Layout National Semiconductor COPYRIGHT C 2006 VDD RED ee mo P2 J2 DOUT C2 JPG VRI DOUT PRE m EMPHASIS R6 JP8 VDD BLK VSS 10 1 ASSY DS99R421 XLATO mm TOP VIEW National Semiconductor Corporation TO DS90UR124 600 Y w i ommo 06 00 em mm om mjo ro PCB DS99R421 XLATOR APPS DEMO BD REV 1 o BOTTOMSIDE VIEW Date 4 23 2014 Page 32 of 39 0008000000 PRIMARY COMPONENT SIDE LAYER 1 E ae B ee ee ae ee e ee ee oa ee ee 08 299A AOTAIX 5 824 SECONDARY COMP SIDE LAYER 4 9 0 PRIMARY COMP SIDE SOLDER MASK LAYER 1 National Sem
4. ntt 99 22 Wc ndm lee seo UE Pes oH 15 aco 0 Qu HO UT won cH e 29 eos es S use z a Ua 7 uei 99 amp a eo CE I ee sunan 99900 css 92 2 0 BENENE CZI 0 HHHH F 9 o a SERRE Re 000000 J osooso 28 000000 66 99 00 e 6 t crauoeed o e e SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 National Semiconductor Corporation Date 4 23 2014 Page 37 of 39 p 34 L IL _ PRIMARY COMP SIDE SOLDER PASTE LAYER 1 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 xs 7 OFO 22 2 JP4 e National RoT Semiconductor zzz PI 2 n H 3 scr C2 4 mca SI 5 wo VSS 5 0 no 6 i 4826 49 32 a 9 z Bp 90 Uo aa oo 10 2 3 55 NTIS _ _ Dg 00 erc 17 12 5 022 0523 JP2 1 T3 16 15 VDD TPs Ut we 14 BLK 1 15 CJ 55203 teca ML tsa COOSA 5527 T MS wa esa CI 8
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6. Digital Video Source DS99R421 Receiver Board Board A In FPD Link II le Interface Cable National Semiconductor Corporation Logic Analyzer Oscilloscope Figure 3 Typical SERDES Test Setup for Evaluation Date 4 23 2014 Page 20 of 39 Typical Connection Diagram DS99R421 User Quick DS99R421 BxINO C1 C5 27 RxIN1 Serial lt lt as multi ee VDDDES lt Eu VDDD LVDS FF VDDSER Interface gt S C2 C6 RXIN2 RxCLKIN VDDDR e e S0 NLLERxCLKIN C3 C7 3 3V LVCMOS OSO Parallel 4 OS1 as Interface OS2 VDDPO e e VDDP1 4 8 DEN if used or tie High ON PWDNB GPOs if used tie Low OFF BISTEN C9 DOUT z VODSEL L 350mV DOUT RESRVD L SI C10 PRE open OFF or R2 6KO ON VSSDES cable specific VS
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9. National Semiconductor FPD to Serdes UR Translator Chip DS99R421 Evaluation Kit User s Manual NSID FPDXSDUR 43USB Hev 0 0 National Semiconductor Corporation UU ate 4 23 2014 age 1 of 39 Table of Contents TABLE TEIN LSN 2 INTRODUCTION 3 CONTENTS OF THE EVALUATION 4 SERDESTYPICAL APPLICATION aaa ng anaa ga e uva eeu 4 HOW TOSET UP THE EVALUATION e egen e ngae ngapa akang eaaa raa nag aan agan pa a agawe gan 6 EVALUATION BOARD POWER CONNECTION ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccees 6 05998421 TRANSLATOR BOARD DESCRIPTIONS e eee 000000000000 000000000000 0000000 0000000000000000 0000000000000000 7 CONFIGURATION SETTINGS FOR THE SERIALIZER BOARD ccccccecceccecceccecscecceccsccscsscscceccecscesesccecscsscsseeceecesees 8 TRANSLATOR INPUT FPD LINKII AND OUTPUT FPD LINK II PINOUT BY IDC CONNECTOR rn 11 BOM BILL OF MATERIALS TRANSLATOR 2 DS90UR124 DE SERIALIZER BOARD sessessssssssssscssssssessssosessssosessssessssosesscsessssosessssosessssosessssessssosessssosesso 13 CONFIGURATION SETTINGS FOR THE DE SERIALIZER 2 404 40000000
10. 4 groupings as shown above Analog PLL VCO Digital Logic Analog LVDS Digital LVCMOS O P Decoupling specified C1 C8 is the minimum that should be used Figure 7 Typical DS90C124 Rx SERDES Hookup National Semiconductor Corporation Date 4 23 2014 Page 22 of 39 Troubleshooting If the demo boards are not performing properly use the following as a guide for quick solutions to potential problems Representative for assistance n CHECKS If the problem persists please contact the local Sales Check that Power and Ground are connected to both Tx AND Rx boards Check the supply voltage typical 3 3V and also current draw with both Tx and Rx boards The Serializer board should draw about 55 65mA with clock and all data bits switching at 43MHz Rpre 9KQ The De serializer board should draw about 5 85mA with clock and all data bits switching at 2 minimum ROUT loading Verify input clock and input data signals meet requirements for ViLmin VlLmax ViHmin tset thold also verify that data is strobed on the selected rising falling RFB pin edge of the clock 4 Check that the Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING CHART Problem There is only the output clock There is no output data No output data and clock Power ground input data and input clock are connected correctly but no outputs The devices are pulling
11. EE Sta ec gdy 22V 0525 RRFB BISTEN BISTM RAOFF SLEW ue gt 21 L COPYRIGHT C 2006 22 i MADE IN U S A SERDESUR 43USB 059008124 RX ASSY 059008124 RX USB DEMO REV 4 PRIMARY COMP SIDE SILKSCREEN LAYER 1 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 4 23 2014 Page 38 of 39 Deserializer Rx PCB Stackup ASSEMBLY SIDE 1 SILKSCREEN ASSY SIDE 1 V2 OZ LAYER 1 SOLDERMASK ASSY SIDE 1 COMP SIDE 22 PREPREG 0045 THK JI GND PLANE 02 LAYER 2 052 0 SILKSCREEN ASSY SIDE 2 ASSEMBLY SIDE 2 SOLDERMASK ASSY SIDE 2 4 500 900909090 0060000 E _ T 450 06 R TYP 4 PLCS 3 000 0 450 NATIONAL SEMICONDUCTOR CORP SERDESUR 43USB 059016124 RX USB DEMO BOARD PWB 059008124 RX USB DEMO REV 1 DRILL DRAWING National Semiconductor Corporation o o o o o o o o o oo 55 99999 te h CORE 039 PWR PLANE b ae LAYER 3 07 PREPREG 0045 SOLDER SIDE 2 05 LAYER 4 s Tar pap A 0125 3 wo 000 B jJ ose 4 5 005 C 2 005 _ NOTES UNLESS OTHERWISE SPECIFIED 1 2 3 lt gt 10 PRIMARY COMPONENT SIDE IS SHOWN HOLES MARKED A ARE T
12. 14 OUTPUT MONITOR PINS FOR THE DE SERIALIZER 2 000000000000000 15 DE SERIALIZER FPD LINKII PINOUT AND LVCMOS 022 00000000000000 17 BOMA BIEEOPFAMATERIAESJOE SERIALIZER PD pi 18 TYPICAL CONNECTION AND TEST EQUIPMENT eee een 00000 0000000000000009 00000 ee 000000000 19 TYPICAL CONNECTION DIAGRAM DS99R421 USER QUICK REFERENCE 6o000000000000000000000000000000000 21 TYPICAL CONNECTION DIAGRAM USER QUICK REFERENCE 4 eee eee ee eee eee 00000000000000 22 TROUBLES HOO o es SEN IN VERIS Vain UV ODE 23 APPENDENX bees d Tun eei ag IN ses ide 25 SERIALIZER TX PCB SGHE MA SENENG PR FEAR NE CE DEE G NGE CP 25 DE SERIALIZER RX PCB 5 ee et eae reete 0000000000000009 0000 000000000000 000000000000 0000000000000000 00000000 28 SERIALIZER TX PCB LAYOUT bag ie CI 32 SERIALIZER IX PCBSTACKUPB CEU E es NE 35 DESERIALIZER RX PCB LAYOUT 36
13. DESERIALIZER RX PCB STACKUPS 22 39 National Semiconductor Corporation Date 4 23 2014 Page 2 of 39 Introduction National Semiconductors DS99R421 standard multi channel LVDS to FPD LinkII translator SERDES evaluation kit contains 1 DS99R421 translator board and 1 DS90UR124 De serializer Rx board and 1 two 2 meter high speed USB 2 0 cable Note the evaluation boards are not for EMI testing The evaluation boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals additional pads for termination loading and multiple connector options The DS99R421 DS90UH124 chipset supports a variety of display and general purpose applications The single LVDS FPD LinkII interface is well suited for any display system interface Typical applications include navigation displays automated teller machines ATMs POS video cameras global positioning systems GPS portable equipment instruments factory automation etc The DS99R421 can be used to take existing standard multi channel LVDS and convert them to a single channel FPD Link II format DS99R421 can be used as a 21 bit general purpose LVDS translator used in conjunction with the DS90UR124 FPD LinkII De serializer chipset and transmit data at clocks speeds ranging from 5 to 43 MHz The DS99R421 LVDS to FPD LinkII translator board accepts four 4 standard LVDS multi channel LVDS input signals a
14. HDC 0603 Header 3P Header 2P Header 2X3P Header 2X10P CON HDR 10P B CON BANANA S mini B USB surface mount USB TYPE A 4P RES HDC 0402 RES HDC 0402 RES HDC 0402 RES HDC 0805 DIP 8 36 Id LLP socket Surface Mount 4mm Square TP 0402 Date 4 23 2014 Page 12 of 39 DS90UR124 Rx De serializer Board The USB connector J2 mini USB on the topside of the board provides the interface connection for FPD Link signals to the Serializer board Note J1 mini USB on the bottom side is un stuffed and not used with the cable provided in the kit The SERDES de serializer board is powered externally from the J4 VDD and J5 VSS connectors shown below For the de serializer to be operational the Power Down RPWDNB and Receiver Enable REN switches on S1 and S2 must be set HIGH Rising or falling edge reference clock is also selected by 51 HIGH rising or LOW falling The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs 4 Ja J5 COPYRIGHT 2006 MADE IN U S A 257 VSS Note m Vcc and Gnd MUST be applied externally here U2 JP4 2 LED1 al e National ROUT Semiconductor 2 H 5 2 J3 e 51 ea 486 2 JP3 8 _ 49 MM 32 9 ow mam oo 10 D E 2 11 c 64 E RCLK gt BACKSIDE ud 2 LVCMOS OUTPUTS UNSTUFFED 15 3 FUNCTION CONTROLS POWER SUPPLY H 3 52 2
15. J2 Hirose GT17H 4P 2H 13 1 J3 IDC2X25 Unshrouded 14 2 J4 J5 BANANA 15 1 LED1 0402 orange LED 16 1 LED2 0603 green LED 17 1 H1 100 ohm 0402 18 9 R2 R3 R4 R34 R35 R36 R37 10K R38 R39 19 1 51 SW DIP 3 20 1 52 SW DIP 6 21 1 U1 DS90UH124 National Semiconductor Corporation PCB Footprint CAP HDC 0402 CAP HDC 0402 3528 21 EIA CAP N 1206 CAP EIA B 3528 21 CAP HDC 0603 CAP HDC 0603 Header 3P Header 2P mini USB surface mount Hirose GT17H A4P 2H IDC 50 CON BANANA S 0402 0603 Super Thin RES HDC 0402 RES HDC 0805 DIP 6 DIP 12 64 pin TQFP Date 4 23 2014 Page 18 of 39 Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller with 18 bit RGB LVDS output 2 Astro Systems VG 835 This video generator may be used for video signal sources for 18 bit RGB LVDS output 3 Any other signal video generator that generates the correct input levels as specified in the datasheet 4 Optional Logic Analyzer or Oscilloscope The following is a list of typical test equipment that may be used to monitor the output signals from the RX 1 LCD Display Panel which supports digital RGB 3 3 LVCMOS inputs 2 National Semiconductor DS99R421 LVDS to FPD Link II translator 3 Optional Logic Ana
16. effect is to hook up a differential probe to the 100 termination resistor R1 on the DS90UR124 Rx demo board NOT to R5 on the DS99R421 demo board The reason for monitoring R1 on the Rx side is because you want to see what the receiver will see the attenuation signal AFTER the cable connector National Semiconductor Corporation Date 4 23 2014 Page 9 of 39 Table 3 JP5 JP8 USB Red and Black wire JP5 Power wire in USB cable Red wire tied Red wire Hed wire thru P2 and P1 not tied to VSS floating mounted connector Default not Jumper RED to VSS recommended recommended 5 5 VDD VDD Note Normally VDD in USB application RED RED VSS VSS Power wire in USB cable Black wire Black wire Black wire thru P2 and P7 not tied to tied to VSS floating mounted connector Default not Jumper BLACK to VSS recommended recommended JP8 JP8 JP8 VDD VDD VDD Note Normally VSS in USB application BLK BLK BLK VSS VSS VSS imi 3 top thru the board view i mounted on solder side National Semiconductor Corporation Date 4 23 2014 Page 10 of 39 Translator Input FPD LINKII and Output FPD Link Pinout by IDC Connector The following four tables illustrate how the LVDS and FPD LINKII inputs are mapped to the IDC connector J1 the FPD Link II outputs on the USB A connector and the mini USB P1 not mounted pinouts There are also three 3 3 3V LVCMOS over sampled bits OS1 OS2 O
17. or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components that have not been so designated is solely at Buyer s risk and Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2014 Texas Instruments Incorporated
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19. support up to 18 bit color depth TFT LCD Panels Refer to the proper datasheet information on chipset provided on each board for more detailed information National Semiconductor Corporation Date 4 23 2014 Page 5 of 39 How to set up the Evaluation Kit The PCB routing for the translator LVDS input pins RxIN have been laid out to plug directly into FPD HSL Tx demo board note only 6 bit mapping is used The FPD Link TxOUT RxIN DOUT RIN interface uses a standard USB 2 0 connector cable assembly The PCB routing for the Rx output pins ROUT are accessed through a 50 pin IDC connector Please follow these steps to set up the evaluation kit for bench testing and performance measurements 1 A two 2 meter high speed USB 2 0 cable has been included in the kit Connect the 4 pin USB A A side of cable harness to the DS99R421 board and the other side the 5 pin mini USB jack to the DS90UR124 de serializer board This completes the FPD Link II interface connection NOTE The DS99R421 and DS90C124 are NOT USB compliant and should not be plugged into a USB device nor should a USB device be plugged into the evaluation boards 2 Jumpers and switches have been configured at the factory they should not require any changes for immediate operation of the chipset See text on Configuration settings for more details From the Video Decoder board connect a flat cable not supplied to the translator board and connect another flat cable no
20. 2 2 2 4 lt e SLEW v ea RRFB BISTE SERDESUR 43USB DS90UR124 RX ASSY 059008124 RX USB DEMO REV S N National Semiconductor Corporation Date 4 23 2014 Page 13 of 39 Configuration Settings for the De serializer Board Table 4 51 52 De serializer Input Features Selection Reference RPWDNB PTOSEL RESRVD Reference RRFB REN BISTEN BISTM RAOFF SLEW Descripion InputzL 5 L PoWerDowN Bar Power Down Normal Disabled Operational Default L Progressive Turn On SELect Default Description InputzL Input H Latch input data on Rising Falling Edge Rising Edge or Falling edge of TCLK Default Receiver Output Data ENabled Default BIST ENable Normal BIST Mode Note MUST set DS99H421 Operating Enabled BISTEN H Use in M BIST combination with BISTM pin oce Default BIST Mode Per Channel RxOUT 7 0 Don t care if BISTEN L pass fail binary error BISTEN MUST be High RxOUT 23 0 counting enabled for this pin to be H pass mode up to functional RxOUT 23 0 255 errors H fail RxOUT 23 8 normal operation RAndomizer OFF Randomizer Randomizer ON OFF Default Note Note DS99R421 DS99H421 RAOFF MUST RAOFF MUST also be set Low also be set High SLEW rate control Default 2X slew rate for ROUT 23 0 and RCLK 2X drive strength National Semiconductor Corpo
21. ARDS TO THE REQUIRED IMPEDANCE NOMINALS TO A TOLERANCE OF 5x BOARD BE FABRICATED IN COMPLIANCY TO ROHS REQUIREMENTS Date 4 23 2014 Page 39 of 39 IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated TI reference designs are solely intended to assist designers Buyers who are developing systems that incorporate semiconductor products also referred to herein as components Buyer understands and agrees that Buyer remains responsible for using its independent analysis evaluation and judgment in designing Buyer s systems and products TI reference designs have been created using standard laboratory conditions and engineering practices Tl has not conducted any testing other than that specifically described in the published documentation for a particular reference design may make corrections enhancements improvements and other changes to its reference designs Buyers are authorized to use 1 reference designs with the component s identified in each particular reference design and to modify the reference design in the development of their end products HOWEVER NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY THIRD PARTY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any c
22. OMPONENT SIDE IS SHOWN HOLES MARKED A ARE TOOLING HOLES UNPLATED AND SHALL BE ONCE DRILLED FABRICATE USING MASTER FILM DS99R421 XLATOR APPS DEMO BD REV 1 USE GERBER FILE 517 FOR BOARD ROUTE 4 ACCEPTABILITY SHALL BE BASED ON IPC A 600 CLASS 2 5 MATERIAL BASE MATERIAL IS POLYCLAD FR 370HR OR EQUIV Tg gt 170 DEG Td gt 350 DEG C COLOR GREEN 0 062 006 INCH NOM THICKNESS COPPER CLADDING SHALL 1 07 PLATING ALL HOLES AND CONDUCTIVE SURFACES SHALL BE PLATED WITH A MIN OF 001 INCH COPPER SURFACE PLATING TO BE ELECTROLESS NICKEL IMMERSION GOLD ENIG FABRICATION TOLERANCES END PRODUCT CONDUCTOR WIDTHS AND LAND DIAMETERS SHALL NOT VARY MORE THAN 002 INCH FROM THE 1 1 DIMENSIONS OF THE MASTER PATTERN THE CONDUCTIVE PATTERN SHALL BE POSITIONED SO THAT THE LOCATION OF ANY LAND SHALL BE WITHIN 002 INCH DIAMETER TO THE TRUE POSITION OF THE HOLE IT CIRCUMSCRIBES THE MINIMUM ANNULAR RING SHALL BE 002 INCH BOW AND TWIST SHALL NOT EXCEED 07 INCH PER INCH SOLDERMASK BOTH SIDES PER 5 840 TYPE A CLASS COLOR GREEN THERE SHALL BE NO SOLDERMASK ON ANY LAND SILKSCREEN THE LEGEND ON BOTH SIDES USING NON CONDUCTIVE EPOXY INK COLOR WHITE THERE SHALL BE NO INK ON ANY LAND THE 008 TRACES LAYER 1 TO BE 50 OHM SINGLE ENDED IMPEDANCE THE 007 TRACES LAYER 1 TO BE 100 OHM DIFFERENTIAL IMPEDANCE AND THE DIELECTRIC REFERENCED IN BOARD STACK DETAIL IS SUGESTED HOWEVER T
23. OOLING HOLES UNPLATED AND SHALL BE ONCE DRILLED FABRICATE USING MASTER FILM DSSOUR124 RX USB DEMO REV 1 USE BOARD OUTLINE FILE 472 FOR BOARD ROUTE ACCEPTABILITY SHALL BE BASED ON IPC A 600 CLASS 2 MATERIAL BASE MATERIAL IS NEMAL 1 GRADE FR 406 COLOR GREEN 0 052 INCH NOM THICKNESS COPPER CLADDING SHALL BE 1 2 07 OUTSIDE LAYERS AND 1 OZ INSIDE LAYERS PLATING ALL HOLES AND CONDUCTIVE SURFACES SHALL BE PLATED WITH A MIN OF 001 INCH CU SURFACE FINISH GOLD FLASH 000005 MIN FABRICATION TOLERANCES END PRODUCT CONDUCTOR WIDTHS AND LAND DIAMETERS SHALL NOT VARY MORE THAN 003 INCH FROM THE 1 1 DIMENSIONS OF THE MASTER PATTERN THE CONDUCTIVE PATTERN SHALL BE POSITIONED SO THAT THE LOCATION OF ANY LAND SHALL BE WITHIN 010 INCH DIAMETER TO THE TRUE POSITION OF THE HOLE IT CIRCUMSCRIBES THE MINIMUM ANNULAR RING SHALL BE 002 INCH BOW AND TWIST SHALL NOT EXCEED 010 INCH PER INCH SOLDERMASK BOTH SIDES PER IPC SM 840 TYPE A CLASS B COLOR GREEN THERE SHALL BE NO SOLDERMASK ON ANY LAND SILKSCREEN THE LEGEND ON BOTH SIDES USING NON CONDUCTIVE EPOXY INK COLOR WHITE THERE SHALL BE NO INK ON ANY LAND THE 008 LAYER 1 TRACES TO BE 50 OHM SINGLE ENDED IMPEDANCE AND THE 007 TRACES LAYER 1 TO BE 100 OHM DIFFERENTIAL IMPEDANCE AND THE DIELECTRIC REFERENCED IN BOARD STACK DETAIL IS SUGGESTED HOWEVER TRACE WIDTHS AND OR DIELECTRIC THICKNESS MAY BE MICRO MODIFIED IN ORDER TO FABRICATE BO
24. RACE WIDTHS AND OR DIELECTRIC THICKNESS MAY BE MICRO MODIFIED IN ORDER TO FABRICATE BOARDS TO THE REQUIRED IMPEDANCE NOMINALS TO A TOLERANCE OF 54 11 THE PCB SHALL BE E U ROHS COMPLIANT Date 4 23 2014 Page 35 of 39 Deserializer Rx PCB Layout J4 J6 o VDD M VSS e 1 Fat U2 JP4 LED1 National Semiconductor ON ener 606 J 3 25 52 0 gt IN e JP3 64 17 sips 5 2m 5 U1 Te eTP6 eTP7 eTP8 j COPYRIGHT 2006 MADE IN U S A TOP VIEW mcs 6 9 e sc 6 suc e 9 Eac 6 mcis e Hac 6 mci 6 6 9 xc 6 mc 6 9 25 6 6 gt e 6 xc e 9 90505 e VSS VDD 817 Ro Ro 28 RI9 R20 C51 jm C39 90 cao BOTTOMSIDE VIEW National Semiconductor Corporation Date 4 23 2014 Page 36 of 39 LN X X M 6 ce Ei C TN 5 7 IL _ PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 ale m n al on ole A po e oon 15 e ee Con 00 g ibid So i Quim 1 99 es ee S m sgi 29 ues e
25. S3 extra unused bits not required for operation see datasheet for description of these bits Note both the LVDS input and FPD Link outputs LVDS INPUT Ji Symbol RxIN1 RxIN2 RxCLKIN RxCLKIN CD CD qoe 6 15 P3 Symbol 1 E 23 DOUT a BLK _ National Semiconductor Corporation labels are also printed on the evaluation boards for P1 topside not mounted FPD LinkiI OUTPUT 55 JP NC DOUT DOUT JP Date 4 23 2014 Page 11 of 39 Bill of Materials Translator PCB DS99R421 Xlator Bench Board Board Stackup Revised Friday February 29 2008 DS99R421 Xlator Bench Board Bill Of Materials 10 11 12 13 14 15 16 17 18 19 20 21 22 23 N 4 Revision 1 February 29 2008 18 31 46 Qty Reference Part C1 C2 0 1uF C18 22uF C19 2 2UF C20 0 1UF C21 C22 C23 C30 C33 C36 22uF C41 C24 C26 C28 C32 C35 C37 C40 C25 C27 C29 C31 C34 C38 0 01uF C39 JP2 JP 1 3 Pin Header JP2 2 Pin Header JP3 2X3 Pin Header J1 2X10 Pin Header open J2 2mm 2X5 J5 J4 BANANA P1 mini USB 5 open P2 USB A H5 100 ohm 0402 H8 5 76K R10 R11 R12 R13 R14 R15 0 Ohm 0402 R16 R18 R20 R21 R23 10K 51 SW DIP 4 U1 DS99R421 VR1 SVR20K X2 X1 TP 0402 National Semiconductor Corporation PCB Footprint CAP HDC 0402 CAP N 3528 21 EIA CAP HDC 1206 CAP EIA B 3528 21 CAP HDC 0603 CAP
26. SD VODSEL VSSSER e RESRVD 4 VSSDR e PRE VSSP0 e VSSP1 e R2 Note VDDs can be combined into four 4 groupings as shown top to bottom 3 3V C1 to C4 O 1uF C5 to C8 0 01 uF C9 C10 100nF 50WVDC NPO or X7R R1 1000 Serial FPD Link Interface Jj 1 Analog LVDS 2 Digital 3 Analog FPD Link and 4 Analog PLL VCO for best performance Absolute minimum grouping should be Analog Power and Digital Power Decoupling specified C1 C8 is the minimum that should be used Figure 6 Typical DS90C241 Tx SERDES Hookup National Semiconductor Corporation Date 4 23 2014 Page 21 of 39 Typical Connection Diagram Rx User Quick Reference DS90C124 DES 3 3 VDDPRO 3 3V VDDPR1 C5 C1 C2 VDDOR 1 VDDOR2 VDDOR3 p C7 C3 C4 C1 to C8 0 1 uF to 0 01 ROUTO C9 100 nF 50 WVDC NPO or 7 ROUT1 C10 100 nF 50 WVDC or X7R ROUT2 R1 1000 ROUT3 ROUT4 C9 ROUT5 ROUT6 a ROUT7 Serial ROUT8 FPD Link ROUTS Interface ROUT10 ROUT 1 ROUT12 LVCMOS C10 ROUT13 Parallel ROUT14 Interface GPO RPWDNB ROUT 15 REN ROUT16 RRFB ROUT17 RPWDNB System GPO ROUT18 REN High ON ROUT19 RRFB High Rising edge ROUT20 RESRVD Low ROUT21 ROUT22 RESRVD ROUT23 RCLK LOCK or ON coe 202202 ooocgo ADHA ANAA gt gt gt gt 33535 A Note VDDs can be combined into a minimum of four
27. age 8 of 39 Table 2 JP6 VR1 Pre Emphasis Feature Selection BEEF V NM floating Path to GND JP6 Pre Emphasis helps to Disabled Enabled increase the eye pattern no jumper With jumper opening in the FPD LINKII Default stream JP6 JP6 8 Pre Emphasis adjustment Clockwise Counter via screw Clockwise JP6 MUST have a jumper to VRI use VH1 potentiometer VH1 00 to 20KQ JP6 VR1 6KQ H6 L 6KQ maximum pre increases decreases emphasis to value value 26KQ minimum pre which which emphasis decreases increases 1 2 RPRE 40 ub D pre 2 HPRE minimum gt emphasis emphasis Note maximum is based on resistor value In this case 26KQ value is based on the 6kQ fixed resistor plus 20KQ maximum potentiometer value User use hundreds of Kohms to reduce the pre emphasis value Pre emphasis user note Pre emphasis must be adjusted correctly based on application frequency cable quality cable length and connector quality Maximum pre emphasis should only be used under extreme worse case conditions for example at the upper frequency specification of the part and or low grade cables at maximum cable lengths Typically all that is needed is minimum pre emphasis Users should start with no pre emphasis first and gradually apply pre emphasis until there is clock lock and no data errors The best way to monitor the pre emphasis
28. e right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques for Tl components are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards Reproduction of significant portions of TI information in TI data books data sheets or reference designs is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Tl is not
29. esl pin 3 T T pin 4 NO connect pin 5 1 ae T 7 uo 1 2 eprs do3 ES 9 urd c T ura lt lt SSA gt Mu LYOGGA Date 4 23 2014 Page 29 of 39 National Semiconductor Corporation v jo jeeus 9002 S eunf ASN XY 5 1equinN 4 23 2014 Page 30 of 39 Date pue Burdno4B samod 10 82u848J89M 1951 xy 5 eard ees JIR Jaye sped pue 5 ppe uey ejejndod un Jaiseea 51 esee 10 pepiAo4d 4 pue sJojroedeo 991 1osn y ui 4 pue Je jsnui sasn y Jeu e jou 51 4 sped azis g pue 090 S10jroedeo 962 2 LP2 2 20 4 ASIOU 10 JASN e jou u ee ui 10j2npul JO swojrv s101sisoJ 0 1 5 5
30. iconductor Corporation GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 es ii HE 3 tia SECONDARY COMP SIDE SOLDER MASK LAYER 4 Date 4 23 2014 Page 33 of 39 PRIMARY SIDE SOLDER PASTE LAYER 1 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 4 23 2014 Page 34 of 39 Serializer Tx PCB Stackup ASSEMBLY SIDE 1 SILKSCREEN ASSY SIDE 1 SOLDERMASK ASSY SIDE 1 062 1 007 SILKSCREEN ASSY SIDE 2 SOLDERMASK ASSY SIDE 2 ASSEMBLY SIDE 2 12 4 PLCS 4 740 600 3 250 350 NATIONAL SEMICONDUCTOR CORP DS99R421 XLATOR APPS DEMO BOARD PWB DS99R421 XLATOR APPS DEMO BD REV 1 DRILL DRAWING National Semiconductor Corporation COMP SIDE 107 LAYER 1 PREPREG 0045 THK GND PLANE 1 OZ LAYER 2 h Go CORE 042 THK 22 PWR PLANE 102 LAYER 3 PREPREG 0045 T COMP SIDE 1 OZ LAYER 4 HK ov rato f oon 18 ves 003 x rs 005 ves o Cx ooo ve 0 002 0125 3 NO 003 000 c oos o f oo 2 38 C Ce one ves 000 pes o NOTES UNLESS OTHERWISE SPECIFIED PRIMARY C
31. lyzer or Oscilloscope 4 Any SCOPE with a bandwidth of at least 2 for LVCMOS and or 2GHz for looking at the differential signal L VDS FPD LinkII signals may be easily measured with high impedance high bandwidth differential probes such as the T EK P6330 differential probes National Semiconductor Corporation Date 4 23 2014 Page 19 of 39 The picture below shows a typical test set up using a Graphics Controller and LCD Panel Digital RGB TTL from Graphic Contoller DS99R421 Receiver Board Board eo a n pj gt f FPD Link ne Digital RGB o Interface Cable TTL to Panel Graphics Controller Video Processor Board Contents of Demo Kit LCD Panel Figure 2 Typical SERDES Setup of LCD Panel Application The picture below shows a typical test set up using a generator and scope VIDEO LVDS
32. more than 1A of current After powering up the demo boards the power supply reads less than when it is set to 3 3V National Semiconductor Corporation Solution Make sure the data is applied to the correct input pin Make sure data is valid at the input Make sure Power is on Input data and clock are active and connected correctly Make sure that the cable is secured to both demo boards Check the Power Down pins of both Translator and De serializer boards to make sure that the devices are enabled PD Vcc for operation Also check DEN on the Serializer board and REN on the Deserializer board is set HIGH Check for shorts in the cables connecting the Translator and RX boards Use a larger power supply that will provide enough current for the demo boards a 500mA minimum power supply is recommended Date 4 23 2014 Page 23 of 39 Note Please note that the following references are supplied only as a courtesy to our valued customers It is not intended to be an endorsement of any particular equipment or hardware supplier Connector References Hirose Electric Europe B V Beech Avenue 46 1119 PV Schiphol Rijk The Netherlands Phone 31 20 655 7467 Fax 31 20 655 7469 www HiroseEurope com Cable References Nissei Electric Co LTD 1509 Okubo Cho Hamamatsu City Shizuoka Pref 432 8006 Japan Phone 81 53 485 4114 Fax 81 53 485 6908 www nissei el co p Cable Recommendations For optimal pe
33. nd converts them into a single serialized FPD LinkII data pair with an embedded LVDS clock The serial data stream toggles at 28 times the base clock rate with an input clock at up to 43 MHz The maximum transmission rate for the FPD LinkII line is 1 204Gbps The DS90UR124 de serializer board accepts the FPD LinkII serialized data stream with embedded clock and converts the serialized data back into parallel 3 3V LVCMOS signals and clock Note that NO reference clock is needed to prevent harmonic lock Suggested equipment to evaluate the chipset are a standard LVDS signal source such as a video generator or FPD or Channel Link or equivalent transmitter and or word generator or pulse generator and oscilloscope with a bandwidth of at least 43 MHz will be needed The user needs to provide the standard multi channel LVDS inputs to the FPD LINKII translator and also provide a proper interface from the de serializer output to an LCD panel or test equipment The translator and de serializer boards can also be used to evaluate device parameters A cable conversion board or harness scramble may be necessary depending on type of cable connector interface used on the input to the DS99R421 and to the output of the 059008124 Example of suggested display setup 1 video generator with an 18 bit data LVDS output 2 18 bit LCD panel with a 3 3V LVCMOS input interface National Semiconductor Corporation Date 4 23 2014 Page 3 of 39 Contents of the Evaluati
34. ombination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI TI REFERENCE DESIGNS ARE PROVIDED AS IS TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS EXPRESS IMPLIED OR STATUTORY INCLUDING ACCURACY OR COMPLETENESS TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE QUIET ENJOYMENT QUIET POSSESSION AND NON INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES HOWEVER CAUSED ON ANY THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING IN ANY WAY OUT OF TI REFERENCE DESIGNS OR BUYER S USE OF TI REFERENCE DESIGNS TI reserves th
35. on Kit DS99R421 LVDS to FPD LinkII translator board One DS90UR124 De serializer board Evaluation Kit Documentation this manual 1 2 3 2 meter high speed USB 2 0 cable 4 pin USB A to 5 pin mini USB 4 5 DS99R421 DS90UR241 124 Datasheet SERDES Typical Application PC Graphics Board Video Processor Video Source Digital Input Analo Input Video Input Host Display LCD Monitor LCD TV Digital TV 1 Pair data 1 Pair data gt DS99R421 1Pairdata Translator DE gt DS90UR124 Digital gt HSYNC FPD Link Il De Serializer Display HSYNC 1 Pair clk VSYNC LVDS 3data 1clock 3 3V_LVCMOS NG a E a J Figure 1a Typical Application 18 bit RGB Color Video Processor Board TMDS Rx Digital Video ADC Processor EC Graphics Controller data 5 Tok DS99R421 NTSC PAL LVDS Decoder FPD Link II LCD Monitor LCD TV Digital TV DS90UR124 y 3 3V_LVCMOS LCD Drivers LCD Controller Timing Custom Logic Figure 1b Typical SERDES System Diagram National Semiconductor Corporation Date 4 23 2014 Page 4 of 39 Figures 1a and 1b illustrate the use of the chipset DS99R421 DS90UR124 in a Host to Flat Panel Interface The chipsets
36. rate probe on TCLK the input clock into the DS90UR241 Tx To view the serial stream correctly do not trigger on the probe monitoring the serial stream National Semiconductor Corporation Date 4 23 2014 Page 16 of 39 De serializer FPD LINKII Pinout and LVCMOS IDC Connector The following two tables illustrate how the FPD LINKII inputs are mapped to the mini USB connector J2 and the Rx outputs are mapped to the IDC connector J3 Note labels are also printed on the demo boards for both the FPD LINKII inputs and LVCMOS outputs Symbol J3 pin no 1 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 all even pins LVCMOS OUTPUT JP3 pin no Symbol 1 LOCK PLL VSS 1 y National Semiconductor Corporation Date 4 23 2014 Page 17 of 39 BOM Bill of Materials De serializer PCB DS90UR124 Rx USB Demo Board Board Stackup Revised Monday October 23 2006 059008124 Rx USB Demo Board Revision 1 Bill Of Materials October 23 2006 Item Qty Reference Part 1 2 C2 C1 0 1UF 2 27 C3 C7 C8 C9 C10 C11 C12 open0402 C13 C14 015 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C42 3 1 C4 2 2uF 4 1 C5 22uF 5 1 C6 0 1UF 6 8 32 633 634 41 47 650 22uF C53 C54 7 8 C35 38 C40 C43 C46 CA8 0 1UF C52 C55 8 8 C36 C37 C39 C44 C45 C49 0 01uF C51 C56 9 2 JP2 JP1 3 Pin Header 10 2 JP4 JP3 2 Pin Header open 11 1 Ji mini USB 5 open 12 1
37. ration Date 4 23 2014 Page 14 of 39 Output Monitor Pins for the De serializer Board Table 5 JP3 Output Lock Monitor Output L Output H _ LOCK Receiver PLL LOCK unlocked PLL LOCKED Note LED2 will DO NOT PUT A SHORTING illuminate JUMPER IN JP4 PASS Monitor PASS Receiver BIST monitor PASS flag LED1 will Note illuminate DO NOT PUT A SHORTING a JUMPER IN JP1 National Semiconductor Corporation Date 4 23 2014 Page 15 of 39 Table 6 JP1 JP2 USB Red and Black wire JP1 Power wire in USB cable Hed wire tied Red wire Hed wire thru J2 and J1 not tied to VSS floating mounted connector Default not Jumper RED to VSS recommended recommended qe JP1 RED JP1 RED Note Normally VDD in USB application VSS VSS Power wire in USB cable Black wire Black wire Black wire thru J2 and J1 not tied to tied to VSS floating mounted connector Default not Jumper BLACK to VSS recommended recommended VDD VDD VDD 2 Ie BLK JP2 IO BLK JP2 IO BLK Note Normally VSS in USB application VSS VSS VSS RED WIRE BLACK WIRE top side view mounted on component side The following picture depicts a typical example of the FPD Link serial stream This snapshot was taken with a differential probe across the 100 ohm termination resistor R1 on the DS90UR124 Rx evaluation board H1 is the termination resistor to the RxIN Note The scope was triggered with a sepa
38. rformance we recommend Shielded Twisted Pair STP 1000 differential impedance cable for high speed data applications Equipment References Astro Systems 425 S Victory Blvd Suite A Burbank CA 91502 Phone 818 848 7722 Fax 818 848 7799 www asiro systems com Digital Video Pattern Generator Astro Systems VG 835 or equivalent Extra Component References TDK Corporation of America 1740 Technology Drive Suite 510 san Jose CA 95110 Phone 408 437 9585 Fax 408 437 9591 www component tdk com Optional EMI Filters TDK Chip Beads or equivalent National Semiconductor Corporation Date 4 23 2014 Page 24 of 39 Appendix Serializer Tx PCB Schematic IN OD Date 4 23 2014 Page 25 of 39 National Semiconductor Corporation 8 uoueg 665 1equinN SSA m m 4 1 b 1 C ul X185 sade JegueJagip wyo 001 401 8 tutu 55 L 10 poq 128 49 jua2 ZX LX 3LON LNOAVT SSA ub UC LNOAVT 592244 95991 uo pasinbas sy bua 92e 10 eouepeduii ON
39. t supplied from the De serializer board to the panel 3 Power for the Tx and Rx boards must be supplied externally through Power Jack VDD Grounds for both boards are connected through Power Jack VSS see section below Evaluation Board Power Connection The translator and de serializer boards must be powered by supplying power externally through J3 VDD and J4 VSS on the translator board and J4 VDD and J5 VSS on de serializer board Note 4 is the absolute MAXIMUM voltage not operating voltage that should ever be applied to the translator DS99R421 or de serializer DS9O0UR124 VDD terminal Damage to the device s can result if the voltage maximum is exceeded National Semiconductor Corporation Date 4 23 2014 Page 6 of 39 DS99R421 Translator Board Description The 20 pin IDC connector J1 accepts standard 18 bit 3 channels of LVDS RGB data RxINO RxIN1 RxIN2 and clock RxCLK 100 ohm terminations are integrated in the DS99R421 FPD LINKII RxIN inputs so no external resistors required The translator board is powered externally from the J3 VDD and J4 VSS connectors shown below For the serializer to be operational the Power Down S1 PWDNB and Data Enable S1 DEN switches on 51 must be set HIGH The board 15 factory configured JP1 and JP2 are configured from the factory to be shorted to VSS these are the unused power wires in the cable harness The USB connector P2 USB A side on
40. the bottom side of the board provides the interface connection to the FPD Link signals to the De serializer board Note P1 mini USB on the top side is un stuffed and not to be used with the cable provided in the kit 4 J5 Note o e 6 VDD and VSS MUST be applied externally from here E NOT FOR EMI TESTING 2 National LLI e Semiconductor 4 vR1 JP6 LL 2 COPYRIGHT c 2006 Note gt Connect cable 23 to P2 on BACKSIDE 2 2 P2 BACKSIDE J2 DOUT DOUT ZI ml EMPHASIS D FPD LinkII OUTPUT E 050 2 FPD LINKII INPUTS e NOT FOR EMI TESTING 2 R 2 0 P1 UNSTUFFED P1 VDD BLK VSS E VSS 3 LVCMOS INPUTS 4 FUNCTION CONTROLS si 5 POWER SUPPLY ASSY DS99R421 XLATO mm National Semiconductor Corporation Date 4 23 2014 Page 7 of 39 Configuration Settings for the Serializer Board Table 1 S1 Serializer Input Features Selection Down operation Default WM We Data ENabled Default VODSEL FPD LINKII 350 00mV output VOD Default SELect e ca BISTEN BIST ENabled BIST BIST DISABLED ENABLED MUST be low for 2 DS90UR124 normal BISTEN MUST operation also be set Default High see datasheet for operational modes National Semiconductor Corporation Date 4 23 2014 P
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