USER`S MANUAL
Contents
1. o 5 02 5 G D 125 11 aa lt q ADDRESS DECODE od JUMPER BLOCK J1 J1 A B G D ee A Pe p 00000000000000000 MODEL AVME967 BASE ADDRESS PROGRAMMING ADJACENT PINS OF JUMPER Jl ics 2 lt REPRESENT THE UPPER 6 BITS OF THE eo 274144020 74712 BASE ADDRESS A JUMPER PRESENT Y FER ie REPRESENTS A BIT VALUE OF 1 A 0400 RE 2 5185 BE 2 002 JUMPER REMOVED REPRESENTS A BIT 11 EGOA E Fee oseo lt lt ALL PRESENT AVME9670 JUMPER amp IP LOCATIONS 4501 755A 02963INAV Sd3ld3S IVIH LSPIQNI Qquvoa N9 M2 x 6 A FLAT HEAD SCREW THREADED M2 SPACER Motos SIDE OF IP MODULE D1 eL Mesum 8 ASSEMBLY PROCEDURE PAN HEAD SCREW 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LE THE SHORTER LE BOARD SHOWN REQUIREMENTS GTH IS FOR USE WITH AVME9670 CARR 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SI P MODULE AND 3 CAREFULLY ALIG TOGETHER UNTIL 4 INSERT PAN HEAD OF CARRIER BOAR TIGHTEN 4 PLACES TO HEX SPACERS ITEM B A2. 12 34 5 6 7 8 9 10 1112131415 16 17 18 19 20 21 22 2524 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 45 44 45 46 47 48 49 50 TB1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC 5 315 135 0 TOP VIEW 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 FRONT VIEW RAIL DIN MOUNTING SHOWN HERE DIN 50035 52mm PANEL ACROMAG PART NUMBER 4001 048 T RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35mm EN SCREWDRIVER SLOT FOR REMOVAL FROM T RAIL SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 10 020 49 5 MODEL 5025 552 TERMINATION PANEL 4501 464A 02963INAV SSIYAS IVIH LSPIQNI Qquvoa daluHvo N9 P1 P2 P3 P4 CONNECTORS gt 1 2 3 48 49 50 123 48 49 50 123 48 49 50 1 2 3 48 49 50
3. 9 Series AVME9670 Industrial I O Pack VME64x Bus 6U Non Intelligent Carrier Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1999 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 608 D01D003 INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARDS The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 2 0 3 0 4 0 5 0 GENERAL KEY AVME9670 FEATURES sse VME64x INTERFACE SIGNAL INTERFACE PRODUCTS i INDUSTRIAL I O PACK SOFTWARE LIBRARY PREPARATION FOR 06 UNPACKING AND INSPECTION enn CARD C
4. 40 to 85 E Versions Note that visual LED performance May be degraded below 20 C 5 95 non condensing 55 to 100 C VME64x bus and IP module logic commons have a direct electrical connection As such unless the IP module provides isolation between the logic and field side the field I O connections are not isolated from the VME64x bus Designed to comply with IEC1000 4 3 Level 3 10V m at frequencies 27MHz to 500MHz and European Norm EN50082 1 No digital upset under the influence of EMI from switching solenoids commutator motors and drill motors Complies with IEC 1000 4 2 Level 1 2KV direct contact discharge at field input output terminals and European Norm EN50082 1 Complies with IEC 1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Meets or exceeds European Norm EN50081 1 for class B equipment 15 INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD APPENDIX CABLE MODEL 5028 187 SCSI 2 to Flat Ribbon Shielded Type Round shielded cable 50 wires SCSI 2 male connector at one end and a flat female ribbon connector at the other end The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog Application Used to connect Model 5025 552 termination panel to the TRANS 200 Transition Module The transition module then connects to all four IP module
5. Carrier registers for control amp status monitoring Interrupt release mechanism is Release On Register Access RORA type IANCE This device meets or exceeds all written Industrial Pack specifications per ANSI VITA 4 1995 For 8 Mhz operation only and IP I O Mapping to VME64x ANSI VITA 4 1 1996 AVME9670 E supports four single size IP modules A D or two double size 32 bit IP modules are Not Supported A16 D16 or 08 supports 128 byte values per IP A16 D08 O supports 32 bytes per IP consecutive odd byte addresses ID Data Format l D16 is also supported with pull ups on the carrier board holding the upper 8 bits high A24 D16 or 008 supports 1M to 8M bytes per IP module INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD Interrupts Access LED Illuminate duration ENVIRONMENTAL Operating Temperature Relative Humidity Storage Temperature Non Isolated Radiated Field Immunity RFI Electromagnetic Interference Immunity EMI Electrostatic Discharge Immunity ESD Electric Fast Transient Immunity EFT Radiated Emissions Supports two interrupt requests per IP and interrupt acknowledge cycles D16 D08 O 0 125 second typical 0 to 70 C
6. ANSI VITA 1 1 1997 VME64x as an interrupting slave including the following data transfer types e 16 D16 DO8 O Carrier Register Short I O Access e 16 016 008 0 IP Module ID Space A16 D16 D08 EO IP Module I O Space e A24 D16 D08 EO IP Module Memory Space The carrier board s VME64x bus data transfer rates are typically e 450ns for accesses to the carrier board registers e 450ns for data transfers to the IP modules assuming 0 wait states on IP The carrier board s FPGA monitors the base address jumper Setting which is jumperable on 1K byte boundaries in the VME64x bus Short I O A16 Address Space When the selected base address matches the A16 address provided by the VME64x bus master the FPGA controls and implements the required bus transfer allowing communication with the carrier board s registers or IP modules Carrier Board Registers The carrier board registers presented in section 3 are implemented in the logic of the carrier board s FPGA An outline of the functions provided by the carrier board registers includes e Software reset can be issued to reset the FPGA Logic and all IP modules present on the carrier board via the Status Register e Monitoring the error signal received from each IP module is possible via the IP Error Register e Configuration of VME64x bus A24 standard address space for optional Memory Space on each IP module is possible Memory Space access to the IP modules can be indivi
7. GIP this bit is Global Interrupt Pending Where Bits 1 0 Not used equal 0 if read Bit 7 Writing a 1 to this bit will enable automatic clear of pending interrupts on the carrier When this bit is set pending interrupts will not be latched or registered on the carrier An interrupt will only remain set as pending on the carrier if its corresponding IP module has an active interrupt request Bit 6 When this bit is set to 1 automatic Auto Acknowledge acknowledge of the IP module access is Disable disabled Thus an access to an empty IP module slot can result in a bus error due INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD Bit 5 Timed Out Access Bit4 Software Reset Write Bit 3 Global Interrupt Enable GIE Read Write Bit 2 Global Interrupt Pending GIP Read to time out When this bit is set to 0 automatic acknowledgement is enabled The carrier will acknowledge the access even if the IP module does not or if there is no IP module present Bit 5 of this register will be set to indicate that the last IP module access has timed out This bit when set to 1 indicates that the last IP module has timed out The IP did not acknowledge the access This bit will be 0 on power up Reading the carrier board status register will clear this bit to 0 Writing a 1 to this bit causes a software reset Writing 0 or reading the bit has no effect When set the
8. 552 DIN rail mountable panel provides 50 screw terminals for universal field termination Connects to Acromag AVME9670 with the TRANS 200 or other compatible carrier boards via SCSI 2 to Flat Ribbon Cable Shielded Model 5028 187 VME64x Transition Module Model TRANS 200 This module plugs into the rear backplane directly behind the carrier board The field I O connections are made through the backplane to PO and P2 connectors of the carrier board and then routed to four SCSI 2 connectors on the transition module marked IP module slots A through D for rear exit from the card cage It is available for use in VME64x bus card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VME64x bus mechanical dimensions and IEEE Standard 1101 11 1998 with a printed circuit board depth of 80mm which is a standard transition module depth The transition module connects to Acromag Termination Panel Model 5025 552 using SCSI 2 to Flat Ribbon Cable Shielded Model 5028 187 to the rear of the card cage and to AVME9670 boards within the card cage INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial I O Pack Software Library diskette Model IPSW LIB M03 1 44MB MSDOS f
9. Board Diagnostics GENERATING Interrupt Configuration Sequence of Events for an Interrupt THEORY OF CARRIER BOARD OVERVIEW T 4 Interface Carrier Board IP Logic Interface usare adie Carrier Board Clock IP Read and Write Cycle Timing s 4 22 Power Failure Monitor eee Access LEDs and Pulse Stretcher Circuitry Power Supply SERVICE AND REPAIR 2 SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE U OO CO O1 CO O O1 O1 O1 P PO Fo 6 0 14 PHYSICAL d 14 VME64x COMPLIANCE nu 14 INDUSTRIAL I O PACK COMPLIANCE 14 ENVIRONMENT itt otto testen eer 15 APPENDIX inodo dn 16 CABLE SCSI 2
10. ON FRONT PANEL x x x CONNECTORS C S S S S c ONES ONU RP2 RP2 RPQ RPQ lt 9 19 233 4 gt RP2 9 RPG A 3 15 3 35 80 0 85 1 SLOT A SLOT B SLOT C SLOT D 2 4 1 al J 1 J J TOP VIEW lt 10 31 261 9 gt 0 78 5 gt _ I _ _ 5 29 19 8 DL 5 5 5 5 se css NOTE DIMENSIONS ARE IN INCHES MILLIMETERS FRONT VI EW 5 200 MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 760B 02963INAV Sd3ld3S OVd WIELSNANI Qquvoa daluHvo N9
11. software reset bit will have a duration of 105 The effect of software reset on the various registers is noted in the description of each register Reset Condition Set to O Writing a 1 to this bit enables interrupts to be serviced provided that interrupts are supported and configured A 0 disables servicing interrupts Reset Condition Set to 0 interrupts disabled This bit will be 1 when there is an interrupt pending This bit will be 0 when there is no interrupt pending Polling this bit will reflect the board s pending interrupt status even if the Global Interrupt Enable bit is set to 0 Reset condition Set to O Interrupt Level Register Read Write Base C3H The carrier board passes interrupt requests from the IP modules to the VME64x bus It does not originate interrupt requests The Interrupt Level Register allows the user to control the mapping of IP interrupt requests to the desired VME64x bus interrupt level Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board Also the specific IP interrupt request must be enabled via its corresponding bit in the Interrupt Enable Register described subsequently MSB D7 LSB 01 DO Not Not Not Not Not IL2 IL1 ILO Used Used Used Used Used Where Bits 7 6 5 4 3 Bits 2 1 0 IL2 ILO Read Write Not used equal 0 if read These bits con
12. 81 Not Used ID Space Low Byte 02BF 02C1 Not Used Not Used 02FF IP D IP D 0301 Space Space High Byte Low Byte 037F IP D 0381 Not Used ID Space Low Byte 03BF 03C1 Not Used Not Used 03FF INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD Table 3 1B AVME9670 Carrier Board Registers Base Address Base Hex D15 008 007 000 00 0 Carrier Board Not Used Status Register 00C1 00C2 Interrupt Level Not Used Register 00C4 IP Error Not Used Register 00C6 IP Memory Not Used Enable Register 00C3 00C5 00C7 00C8 00C9 Not Used Not Used 00CE 00CF 00D0 IP_A Memory Base Address amp Size Register IP_B Memory Base Address amp Size Register IP_C Memory Base Address amp Size Register IP_D Memory Not Used Base Address amp Size Register 00D7 00D8 00D9 Not Used Not Used 00DE 00DF IP Interrupt Not Used Enable Register IP Interrupt Not Used Pending Register IP Interrupt Not Used Clear Register 00E6 00E7 Not Used Not Used 00 OOFF Identification ROM Read Only 32 Odd Byte Addresses 00D1 00D4 00D6 00E1 Each IP contains identification information ID that resides in the ID space per the IP specification This area of memory contains 32 bytes of information at most ID ROM Format 1 Both fixed and variable information may be present within the ID ROM Fixed information includes the IPAC identifier model number a
13. AGE BOARD CONFIGURATION INTERFACE Address Decode Jumper Configuration VME64x Address Interrupt Configuration eee CONNECTORS w Carrier Field I O Connectors IP modules A D IP Field I O Connectors IP modules 0 IP Logic Interface Connectors IP modules A D VME64x Connections eee POWER UP TIMING AND LOADING 2 DATA TRANSFER eene FIELD GROUNDING CONSIDERATIONS PROGRAMMING MEMORY MAPS greet perte Identification PROM Carrier Board Status 1 Interrupt Level IP Error Register eere IP Memory Enable IP Memory Base Address amp Size Registers IP Interrupt Enable IP Interrupt Pending IP Interrupt Clear GENERAL PROGRAMMING CONSIDERATIONS
14. ME64x bus P2 CONNECTIONS Row B Row C RowD 41 B42 B43 Not Used B44 B45 B46 B47 B48 B49 B50 A2 lot Used Not Used A10 A11 A12 A13 A14 A15 Not Used A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 Not Used A26 A27 A28 A29 A30 A31 lot Used A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 Not Used A48 GND A49 A50 Not Used Not Used Not Used GND Not Used NotUsed NotUsed Not Used C46 GND C49 GND GND Bs GND z gt B9 A1 A3 A5 GND A9 B11 GND B14 GND B17 GND B20 GND B23 GND B26 GND B29 GND B32 GND B35 GND B38 z z z 1 646 2 GND 3 64 4 GND 6 GND 8 GND 9 Ps 10 GND i2 GND 135 Bi4 14 GND 15 817 i6 GND 17 B20 18 GND 19 B23 20 GND 21 826 22 GND 23 9 24 GND 25 B32 26 GND 27 85 28 GND 29 B38 30 GND 31 Not Used 32 GND Note The letter in front of the number indentifies the IP Module Slot The number indentifies the I O pin number of that IP Module Example C46 C IP Module in Slot 46 I O Pin number 46 This pin on the IP Module connects to P2 Pin 1 Row Z Shaded area are pins defined under the VME64Xbus specification BOLD ITALIC Logic Lines are NOT USED by the carrier board 0 Elongated mate first br
15. Maximum rise 14 Data Transfer Bus VME64x bus Access Time A24 A16 D16 D08 EO DTB slave supports Read Modify W rite cycles 450nS Typical all carrier board registers measured from the falling edge of DSx to the falling edge of DTACK 450nS Typical IP registers with no wait states See IP specifications for information on wait states IP register access time will increase by the number of wait states multiplied by 125nS the period of the 8 Mhz clock VME64x bus Address Modifier Codes Short Standard Address Interrupts INDUSTRIAL I O PACK COMPL Specification Electrical Mechanical Interface Memory Space Base address is hardware jumper selectable Occupies 1K byte Responds to both address modifiers 29H amp 2DH in the VME64x bus short space for carrier board registers and IP I O and ID spaces Responds to both address modifiers 39H amp 3DH in the VME64x bus standard address space when such accesses to IP memory are enabled via programmable registers on the carrier board Base addresses and sizes of IP memory are programmable from 1M to 8M bytes Creates 1 1 7 programmable request levels up to two requests Sourced from each IP D16 D08 O interrupter interrupt vectors come from IP modules
16. ND TIGHTE UNTIL HEX SPACER IS COMPLETELY SEATED P MODULE TO CARRIER BOARD AND PR SCREWS ITEM C THROUGH SOLDER SI CONNECTORS AND SPACERS ARE SEATED D AND INTO HEX SPACERS ITEM B AND UUUUVU 39 GTHS ER CHECK YOUR CARRIER BOARD TO DETERMINE ITS OUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS DE OF 4 PLACES ESS DE IP MODULE TO AVME96 0 CARRIER BOARD MECHANICAL ASSEMBLY COMPONENT SIDE OF AVME9670 CARRIER BOARD P2 CONNECTOR 4501 756A 02963INAV SSIYAS IVIH LSPIQNI Qquvoa dalgHvo N9 6 IP A 02 m FPGA LOGIC 1 ACCESS GREEN CONTROL BUS LED STATUS MEMSELA REGISTER lei ADDRESS MODIFIERS Bi DSO DS1 D AS gt FIELD IP MODULE A BAG be LWORD gt 5 La WRITE ERROR gt SYSRESET IP ERROR he SXSCDK REGISTER DTACK
17. ON CABLE CONNECTS TO P2 SHIELDED BACKSH N Q O 00 O P1 2 SCHEMATIC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 N G Q O ELL 1 INCH 0 25 INCH TO MODEL 5025 552 1 0 TERMINATION TO MODULE FIELD 1 0 CONNECTOR PANEL 2 METERS gt 78 72 INCHES 4 0 0 0 INCHES P2 P1 TOP VIEW STRAIN RELIEF 1004 534 N N WW SPRING SHRINK LATCH CABLE 2006 353 2002 4358 1 INCH LENGTH IN 25 fea 24 PIN 50 56 PLUG CONNECTOR 1804 876 88 SHIELDED BB BACKSHELL BE 1004 877 AE PIN 1 B Ede 26 RIBBON CABLE PE PIN 2 CONNECTOR ts P2 1004 512 P1 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS MODEL 5028 187 SCSI 2 TO FLAT RIBBON CABLE SHIELDED 4501 758B 02963INAV SSIYAS IVIH LSPIQNI Qquvoa dalguHvo N9 2 203 58 5 123456 78 9 10111213 1415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1
18. SUPPLY B FILTERS IP B be ACCESS 0 GREEN IP MEMORY DATA IACKIN B ENABLE I TRANSFER lt IACKOUT REGISTER amp INTERRUPT IOSELB NTR R MEMSELB ENNER 5 INTERRUPT INTSELB x E gt REQUEST Pan pete BASE ADDR amp gt DRIVERS SIZE REGISTERS BS x BS 1s ACKBs POWER FIELD IP MODULE B BS 4 INTERRUPT lt FAILURE 1 0 INTREQOBs T ENABLE 5 MONITOR REGISTER 5V c POWER A INTERRUPT SUPPLY PENDING lt gt FILTERS 5 REGISTER A access WD GREEN 2 01 INTERRUPT LED 2 D CLEAR lt gt REGISTER IOSELC 0 MEMSELC Oo 5 INTSELC IDSELC S R W E CLKC B J1 SHORT 818 ADDRESS u D SELECTION DECODE LATCHES FIELD IP MODULE C BAI BAS 5 15 A i 1C ERRORC PULSE ADDRESS B C STRETCHER BUFFERS 12 D lt xd IP D amp 12v 5 1 ACCESS GREEN D LED lt RESET PO 0580 MEMSELD INTSELD IDSELD R W CLKD IP D BS BS1 FIELD IP MODULE D BD15 BDO 170 INTREQOD 1D 54 ERRORD POWER SUPPLY 2 FILTERS 12V AVME9670 CARRIER BLOCK DIAGRAM BOARD 4501 757A 02963INAV SSIYAS OVd IVIH LSPIQNI Qquvoa N9 02 GROUND SHIELD
19. Supports Standard I O Address Modifiers Supports standard A24 address modifiers 39H 3DH H Hex Standard address space is used when an IP supports memory space The carrier board is configured using programmable registers to set the IP starting address and size 1Mbyte to 8Mbytes e Supports Read Modify Write Cycles Carrier board supports VME64x bus read modify write cycles Interrupt Support 1 1 7 interrupter 016 008 O Up to two interrupt requests are supported for each IP module The VME64x bus interrupt level is software programmable Carrier board software programmable registers are utilized as interrupt request control and status monitors Interrupt release mechanism is Release On Register Access RORA type SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP carrier board will mate directly to all industry standard 8 MHz IP modules Acromag provides the following interface products all connections to field signals are made through the carrier board and transition module which passes them to the individual IP modules Cables Model 5028 187 SCSI 2 to Flat Ribbon Cable Shielded A round 50 conductor shielded cable with a male SCSI 2 connector at one end and a flat female ribbon connector at the other end The cable is used for connecting AVME9670 with the TRANS 200 or other compatible carrier boards to Model 5025 552 termination panels Termination Panel Model 5025
20. an be individually enabled on the carrier board After interrupts are enabled on the carrier board via the Interrupt Enable Register see section 3 for programming details an IP generated interrupt is recognized by the carrier board and is recorded in the carrier board s Interrupt Pending Register A carrier board pending interrupt will cause the board to release the interrupt to the VME64x bus provided the Global Interrupt Enable bit of the carrier s Status Register has been enabled see section 3 for programming details The carrier board releases the interrupt to the VME64x bus by asserting the interrupt request level as pre programmed in the carrier s Interrupt Level Register The carrier board s interrupt logic then monitors the VME64x bus Interrupt Acknowledge Input IACKIN signal An active IACKIN signal detected by the carrier board is either passed to Interrupt Acknowledge Output or consumed by the carrier board IACKIN is passed to IACKOUT if the VME64x bus interrupt level does not match that programmed into the carrier s Interrupt Level Register If a match is detected the carrier board responds to the interrupt by consuming IACKIN The carrier board also responds to an interrupt by driving IP Interrupt Select INTSEL active to the IP that generated the interrupt provided only one interrupt has been issued If two or more interrupts occur at the same time then INTSEL is driven active to th
21. and low power detection reset signals to the IP modules per the IP specification e Individually Filtered Power Filtered 5V 12V and 12V DC power is provided to the IP modules via passive filters present on each supply line serving each IP This provides optimum filtering and isolation between the IP modules and the carrier board and allows analog signals to be accurately measured or reproduced on IP modules without signal degradation from the carrier board logic signal noise ESD Strip on AVME9670 Board The AVME9670 board has been designed to provide electrostatic discharge ESD capability by using an ESD strip on the board per ANSI VITA 1 1 1997 and IEEE1101 10 New Injector Ejector Handles The AVME9670 uses modern injector ejector handles which push the board into the rack during installation and pull the board out of the rack for removal or replacement These handles are needed to give you leverage to install and remove the board VME64x bus INTERFACE FEATURES e Slave Module Carrier Register Short I O Access A16 016 008 0 IP Module ID Space A16 016 008 0 IP Module I O Space A16 D16 D08 EO IP Module Memory Space A24 D16 D08 EO Supports Short I O Address Modifiers Supports short I O A16 address modifiers 29H 2DH H Hex Short I O space is used for all carrier registers and IP module I O and ID spaces The carrier board base address is set by hardware jumpers and decoded on 1K byte boundaries e
22. arrier board The user must also configure the VME64x bus interrupt level using the Interrupt Level Register LSB D1 DO IP D IPD IPC IPC IPB IPB IPA IPA MSB D7 Int1 IntO Int1 IntO Int1 IntO Int1 IntO Ena Ena Ena Ena Ena Ena Ena Ena Where All Bits Writing a 1 to a bit enables interrupts for IP Interrupt Enable the corresponding IP module and interrupt Read Write level A zero disables the corresponding interrupt Reset Condition Set to 0 IP interrupts disabled 10 IP Interrupt Pending Register Read Base E3H The IP Interrupt Pending Register is used to individually identify pending IP interrupts If multiple IP interrupts are pending they will be serviced with the lowest priority given to the last IP interrupt and the highest priority is given to all other pending interrupts This prevents the continuous interrrupts of one IP module from blocking the interrupts of other modules IP D IP D IP C IP C IP B IP B IPA IPA Int IntO Int1 IntO Int1 IntO Int1 IntO Pend Pend Pend Pend Pend Pend Pend Pend Where All Bits A bit will be a 1 when the corresponding IP IP Interrupt Pending X interrupt is pending A bit will be a 0 when Read its corresponding interrupt is not pending Polling this bit will reflect the IP modules pending interrupt status even if the IP interrupt enable bit is set to 0 Reset Condition Set to O IP Interrupt Clear Register Writ
23. at memory space corresponding to IP modules A through D The memory size for each enabled IP module is user programmable from 1MByte to 8MByte in multiples of two Note that memory on IP modules can only be accessed if enabled within the IP Memory Enable Register and that the memory bases for enabled IP modules must not be programmed to overlap with each other The size selected by these registers should be matched to that required by the associated IP MSB D7 Base Address Serr U Used Used Uses 17 mi Use Uses Uses Uses mee Used a U ses ond Used Used Where Bit 7 6 5 4 These bits define the memory base address IP Memory Base Read and write operations are implemented Address on all bits even if labeled unused Thus a Read Write read operation will return the last value written Reset Condition Set to 0 memory base address 0 Bit 3 2 Not used equal 0 if read Bit 1 0 These bits define the memory size selected IP Memory Size Read Write 1MB 2MB 4MB or 8MB as shown in the previous table Reset Condition Set 0 1MB memory size IP Interrupt Enable Register Read Write Base E1H The IP Interrupt Enable Register is used to individually enable disable IP interrupts Each IP A through D may have up to two requests Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the c
24. ble 3 1A The Input Output IO and Identification ID spaces of each IP are accessible via the VME64x bus Short I O space as shown in Tables 3 1A The carrier board may optionally occupy memory in the VME64x bus standard A24 address space if needed for IP modules containing Memory space IP memory will only be mapped into the standard memory space if it is enabled for a particular IP per the user programmable IP Memory Enable Register see Table 3 1B and subsequent description The starting memory address for each enabled IP and the memory size for each enabled IP module is user programmable via its associated IP Memory Base Address amp Size Register see Table 3 1B and subsequent description MEMORY MAPS Table 3 1A AVME9670 6U Carrier Bd Short I O Memory Map Base Address Hex 0000 007 0080 00 00 0 00 0100 017 0180 01BE 01 0 01FE 0200 027 0280 02 02 0 02 0300 037E 0380 03 03 0 03 Base EVEN Byte ODD Byte Address D15 D08 D07 000 Hex IPA IPA 0001 Space Space High Byte Low Byte 007F IPA 0081 Not Used ID Space Low Byte 00BF Carrier Board 00C1 Not Used Registers See Table 3 1B 00FF IP B IP B 0101 Space Space High Byte Low Byte 017F IPB 0181 Not Used ID Space Low Byte 01BF 01C1 Not Used Not Used 01FF IP C IP C 0201 Space Space High Byte Low Byte 027F IP C 02
25. dually enabled via the IP Memory Enable Register The base address and address range size is programmed via carrier registers IP A IP B C and IP D Memory Base Address amp Size Registers The address size can be selected from 1M 2M 4M or 8M bytes Enabling of VME64x bus interrupt requests from each module via the IP Interrupt Enable Register is possible The desired VME64x bus interrupt level desired can be set via the Interrupt Level Register and pending interrupts can be monitored and cleared via carrier registers IP Interrupt Pending and IP Interrupt Clear Registers e Lastly pending interrupts can be globally monitored and released to the VME64x bus via the Status Register IP Logic Interface The IP logic interface is also implemented within the carrier board s FPGA The carrier board implements ANSI VITA 4 1995 for 8 MHz operation only Industrial I O Pack logic interface specification includes four IP logic interfaces on an AVME9670 The VME64x bus address and data lines are linked to the address 12 and data of the IP logic interface This link is implemented and controlled by the carrier board s FPGA The VME64x bus to IP logic interface link allows a VME64x bus master to Access up to 32 ID Space bytes for IP module identification ID ROM Data Format l via D08 O data transfers using VME64x bus A16 short address space e Access up to 128 I O Space bytes of IP data via D16 D08 EO data trans
26. e Base E5H The IP Interrupt Clear Register is used to individually clear the IP interrupt Pending bits set in the IP Interrupt Pending register LSB D1 DO IP D IP D IP C IP C IP B IP B IPA IPA Int1 IntO Int IntO Int1 IntO Int1 IntO Clear Clear Clear Clear Clear Clear Clear Clear Where All Bits Writing a 1 to a bit causes the corresponding IP Interrupt Clear interrupt Pending bit to clear Writing 0 or Write reading has no effect Reset Condition Set to 0 GENERAL PROGRAMMING CONSIDERATIONS The carrier board register architecture makes the configuration fast and easy The only set of configuration hardware jumpers is for the base address of the carrier board in the VME64x bus short I O space Once the carrier board is mapped to the desired base address communication with its registers and the I O and ID spaces of the IP modules is straightforward The carrier board is easily configured to communicate with IP memory space if present through two configuration registers Interrupt configuration control if supported by IP modules is also easily done through registers INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD Board Diagnostics The board is a non intelligent slave and does not perform self diagnostics It does however provide front panel LED s to indicate successful communication with each of the four IP modules A through D These LED s are driven by the co
27. e components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The carrier board may be configured for different applications All possible configuration settings will be discussed in the following Sections The jumper locations and IP module positions are shown in Drawing 4501 755 Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 756 and your IP module documentation for specific configuration and assembly instructions VME64x INTERFACE CONFIGURATION The carrier board is shipped from th
28. e IP with the highest priority The carrier board will prioritize the requests based on the last interrupt serviced The last interrupt serviced will be given the lowest priority See section 3 for more detail The IP module responds by placing the interrupt vector on the data bus and asserts ACK The carrier then asserts active and the VME64x bus master responds by executing the code at the address of the interrupt vector The user written interrupt routine should include code to clear the carrier board s pending interrupt via the carrier s Interrupt Clear Register see section 3 since the interrupt release mechanism is Release on Register Access RORA type In addition the IP module may need similar attention see your IP module documentation Power Failure Monitor The carrier board contains a 5 volts undervoltage monitoring circuit which provides a reset to the IP modules when the 5 volt power drops below 4 27 volts typical 4 15 volts minimum This circuitry is implemented per the Industrial Pack specification Access LEDs and Pulse Stretcher Circuitry An LED display and pulse stretcher circuit is dedicated to each IP module for indication of a data transfer to from the corresponding IP module An IP acknowledged data transfer activates the pulse 13 stretcher circuit The pulse stretcher s circuit is programmed to illuminate the LED for a duration of 0 125 seconds typical Power Supply Filters Power
29. e factory configured as follows Carrier board with VME64x bus Short I O Base Address of 0000H Board will respond to both Address Modifiers 29H and 2DH Registers on the carrier board plus the I O and ID Spaces on any installed IP modules will be accessible Programmable software registers default to IP memory space VME64x bus standard address space accesses disabled Programmable software registers default to IP interrupt requests disabled and VME64x bus interrupt level none Address Decode Jumper Configuration The carrier board interfaces with the VME64x bus as a 1K byte block of address locations in the VME64x bus short I O address space refer to Section 3 for memory map details J1 decodes the six most significant address lines A10 through A15 to provide segments of 1K address space The configuration of the jumpers for different base address locations is shown in Table 2 1 IN means that the pins are shorted together with a shorting clip OUT indicates that the clip has been removed Table 2 1 Address Decode Jumper Selections J1 Pins Base A15 A14 A13 A12 A11 A10 11 amp 12 9810 7 amp 8 5 amp 6 3 amp 4 1 amp 2 Addr Hex Consult your host CPU manual for detailed information about addressing the VME64x bus short I O A16 16 bit space In many cases CPU s utilizing 24 bit addressing will start the 16 bit address at FF0000 Hex and 32 bit CPU s at FFFF0000 Hex VME64x bus Addr
30. eak last connector contact The I O signals for the P2 connector are mapped per the IP Module I O to VME64x bus Standard ANSI VITA 4 1 1996 Refer to this standard for additional information on the VME64x bus signals VME64x bus Connections for PO Table 2 5 lists the pin assignments for the VME64x bus signals at the PO connector The PO connector is the center connector the AVME9670 board as viewed from the front The connector consists of 6 rows of 19 pins labeled A B C D E and F Pin A1 is located at the upper right hand corner of the connector near the center of the board viewed from the front component side The I O signals for the PO connector are mapped per the IP Module I O to VME64Xbus Standard ANSI VITA 4 1 1996 Refer to this standard for additional information on the VME64x bus signals TABLE 2 5 VME64x bus P0 CONNECTIONS Pin RowA RowB RowC RowD Rowe RowF Fi or pz 0s p Ds GND gt po o 08 09 Dio NP NP GND NP P P P P mi GND N GND N N GND GND N GND Note The letter in front of the number indentifies the IP Module Slot The number indentifies the I O pin number of that IP Module Example D1 6 8 9 D IP Module in Slot D 1 Pin number 1 This pin on the IP Module connects to PO Pin 1 Row A NP No Pin for PO connector Row F is for upper ground shield POWER UP TIMING AND LOADING The AVME9670 boa
31. ess Modifiers No hardware jumper configuration is needed The carrier board will respond to both address modifiers 29H and 2DH in the VME64x bus short I O space This means that both short supervisory and short non privileged accesses are supported The carrier board will respond to both address modifiers 39H and 3DH in the VME64x bus standard address space when standard address space accesses to IP memory are enabled via INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD programmable registers on the carrier board refer to Section 3 for programming details Interrupt Configuration No hardware jumper configuration is required All interrupt enabling status and VME64x bus interrupt level selections are configured via programmable registers on the carrier board see Section 3 for programming details The carrier board passes interrupt requests from the IP modules to the VME64x bus It does not originate interrupt requests Refer to the IP modules for their specific configuration requirements CONNECTORS Carrier Field Connectors IP modules A through D Field I O connections are made through the rear via transition module TRANS 200 connectors A B C and D for IP modules in positions A through D respectively IP module assignment is marked on the transition module for easy identification see jumper amp IP location drawing 4501 756 for physical locations of the IP modules SCSI 2 Round cable assemblies a
32. f five pins labeled A B C D and Z Pin Z1 is located at the upper right hand corner of the connector if the board is viewed from the front component side Refer to the VME64x bus specification for additional information on the VME64x bus signals TABLE 2 3 VME64x bus P1 CONNECTIONS Rowa RowB RowD Do sss veo Doo end BGOIN 007 BG2INN BG20UT BG3OUT LWORD WRITE GND A23 aas SYSCLK BG3IN SYSFAIL Gao 23V 3 3 006 BGIOUT INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD GND ND GND 9 RsvBus N JACKI sera At RsvBus ND SERB GND 5 RsvBus ND 6 IRQ6 A13 RsvBus N N N ND VPC Asterisk is used to indicate an active low signal Shaded area are pins defined under the VME64 bus specification BOLD ITALIC Logic Lines are NOT USED by the carrier board 0 Elongated mate first break last connector contact VME64x bus Connections for P2 Table 2 4 indicates the pin assignments for the VME64x bus signals at the P2 connector The P2 connector is the lower rear connector on the AVME9670 board as viewed from the front The connector consists of 32 rows of five pins labeled A B C D and Z Pin Z32 is located at the lower right hand corner of the connector if the board is viewed from the front component side TABLE 2 4 V
33. fers using VME64x bus A16 short address space e Access up to 8Mbytes of IP data mapped to Memory Space via D16 or D08 EO transfers using VME64x bus A24 standard address space Respond to two IP module interrupt requests per IP with software programmable VME64x bus interrupt levels Carrier Board Clock Circuitry The VME64x bus 16MHz system clock is divided down by U10 CDC3030D to obtain the IP module 8MHz clock signals Separate IP clocks are driven to each IP module All clock lines include series damping resistors to reduce clock overshoot and undershoot and similar length PC board trace lengths are employed to minimize clock skew between the IP modules IP Read and Write Cycle Timing An IP read or write cycle is carried out via a VME64x bus A24 or A16 data transfer The data transfer starts when the VME64x bus Data Strobe 0 0 0 goes active and ends when the carrier board drives Data Transfer Acknowledge DTACK active back to the VME64x bus master The carrier board typically has a 450ns IP module data transfer cycle time A typical IP module data transfer cycle is described here starting with 050 going active DS0 is sampled on the rising edge of the system 16MHz clock edge after it goes active All operations are then synchronized to the IP 8MHz clock as required by the IP module specification Thus typically one 8MHz clock cycle later an IP select line goes active IOSEL IDSEL MEMSEL or INTSEL and is held act
34. has no effect on the and ID spaces of the module MSB D7 Not Not PE m IP D Used Used Used Used Mem Ena Ena Ena Ena Where Bits 7 6 5 4 Bit 3 IP D Memory Enable Read Write Bit 2 IP C Memory Enable Read Write Bit 1 IP B Memory Enable Read Write Bit 0 IP A Memory Enable Read Write LSB DO IP C IP B IP A Mem Mem Mem Not used equal 0 if read Writing a 1 to this bit enables the memory space for IP D A zero disables memory Space accesses Reset Condition Set to 0 memory Space accesses disabled for IP D Writing a 1 to this bit enables the memory space for IP C A zero disables memory Space accesses Reset Condition Set to 0 memory Space accesses disabled for IP C Writing a 1 to this bit enables the memory space for IP B A zero disables memory Space accesses Reset Condition Set to 0 memory space accesses disabled for IP B Writing a 1 to this bit enables the memory space for IP A A zero disables memory Space accesses Reset Condition Set to 0 memory Space accesses disabled for IP A INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD IP Memory Base Address amp Size Registers Read Write IP A Base D1H IP B Base D3H IP C Base D5H IP D Base D7H The IP Memory Base Address amp Size Registers are user programmable to define the starting address of standard A24 memory space and the size of th
35. ion module TRANS 200 to the Termination Panel At the Termination Panel field I O signals are connected to a 50 position terminal block via screw clamps The AVME9670 contains four IP modules and thus 200 I O connections are provided via the transition module through four SCSI 2 connectors marked A B C and D The VME64x bus and IP module logic commons have a direct electrical connection i e they are not electrically isolated However the field I O connections can be isolated from the VME64x bus if an IP module that provides this isolation between the logic and field side is utilized A wide variety of IP modules are currently available from Acromag and other vendors that allow interface to many external devices for both digital and analog I O applications INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD VME64x bus Interface The carrier board s VME64x bus interface is used to program and monitor the carrier board s registers for configuration and control of the board s documented modes of operation see section 3 In addition the VME64x bus interface is also used to communicate with and control external devices that are connected to an IP module s field I O signals assuming an IP module is present on the carrier board The VME64x bus interface is implemented in the logic of the carrier board s Field Programmable Gate Array FPGA The FPGA implements VME64x bus specification ANSI VITA 1 1994 VME64 amp
36. ive for one clock cycle With no IP wait states an active IP Acknowledge signal is driven by the IP on the next rising edge of the 8MHz clock The carrier board samples ACK one clock cycle later and then asserts DTACK ending the VME64x bus data transfer Timing Diagram CLK 16MHz CLK 8mhz 0 0 j IOSEL ACK DTACK A Time out error will result for the following condition if Auto Acknowledge is disabled in the carrier status register If a select line IOSEL IDSEL INTSEL or MEMSEL is driven active to an IP module and the IP module does not return active then DTACK will also not be generated by the carrier board This will cause a bus transfer time out error and the VME64x INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD bus system may need to be reset In addition the carrier board will remain in a state waiting for ACK from the IP To take it out of this state a software reset can be issued When an IP module places data on the bus for all data read cycles any undriven data lines are read by the VME64x bus as high because of pull up resisters on the carrier board s data bus VME64x bus Interrupter Interrupts are initiated from an interrupting IP module However the carrier board will only pass an interrupt generated by an IP module to the VME64x bus if the carrier board has been first enabled for interrupts Each IP module can initiate two interrupts which c
37. l 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to TRANS 200 Transition Module P1 50 pin male header with strain relief ejectors Use Acromag 5028 187 cable to connect panel to TRANS 200 transition module Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packed 16 VME64x TRANSITION MODULE MODEL TRANS 200 Type Transition module for AVME9670 board Application To repeat field I O signals of IP modules A through D for rear exit from VME64x card cages This module is available for use in card cages which provide rear exit for I O connections via 80 mm wide transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VME64x bus mechanical dimensions and IEEE Standard 1101 11 1998 for 80
38. line filters are dedicated to each IP module for filtering of the 5 12 and 12 volt supplies The power line filters are a T type filter circuit comprising ferrite bead inductors and a feed thru capacitor The filters provide improved noise performance as is required on precision analog IP modules Specifically the filters are typically capable of over 40dB of insertion loss for undesirable noise and oscillations in the 100MHz frequency range and over 20dB of insertion loss for noise and oscillations in the 10MHz frequency range Power Supply Fuses Power line fuses are dedicated to each IP module for fusing of the 5 12 and 12 volt supplies The 5 volt supply uses a 2 Amp fuse and the 12 volt supplies use a 1 Amp fuse These fuses are needed to protect the power suppy in the VME64x bus cage system 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details
39. mm depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9670 boards within card cage via connectors RPO and RP2 Schematic and Physical Attributes See Drawing 4501 760 Electrical Specifications 30 VAC per UL and CSA SCSI 2 connector spec s 1 Amp maximum at 50 energized SCSI 2 connector spec s Field Wiring Four SCSI 2 50 pin female connectors AMP 787082 5 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via round shielded cable Model 5028 187 Connections to AVME9670 Connections are made though the PC board connectors RPO 95 pin female with upper ground shield and RP2 160 pin female The transition module plugs directly behind the AVME9670 board into the VME64x bus backplane within the card cage system Mounting Transition module is inserted into a 6U size 80 mm width slot at the rear of the VME64Xbus card cage Directly behind AVME9670 board Printed Circuit Board Eight layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 85 C Storage Temperature 40 C to 85 C Shipping Weight 1 25 pounds 0 6Kg packed JL
40. nd manufacturer s identification codes Variable information may include unique information required for the module The identification Section for each IP module is located in the carrier board memory map per Table 3 1A ID bytes are addressed using only the odd addresses in a 64 byte block The ID contents are shown in Table 3 2 for a generic IP Refer to the documentation of your IP module for specific information Table 3 2 Generic IP Module ID Space Identification ID ROM Hex Offset From ID PROM Base Address ASCII Character Equivalent Numeric Value Field Description All IP modules have IPAC Acromag ID Not Used Revision Not Used Driver ID Low Not Used Driver ID High Total Number of ID PROM Bytes or j c oc 19 to 2 nn 1 XX IP Specific Space 2 1 Notes Table 3 2 1 The model number is represented by a two digit code within the ID ROM e g the IP405 model is represented by 01 Hex Carrier Board Status Register Read Write Base C1H The Carrier Board Status Register reflects and controls functions globally on the carrier board MSB LSB D7 D1 DO TOA Soft Not Not Reset Used Used Notes 1 ACE this bit is Auto Clear Interrupt Enable 2 AAD this bit is a Auto Acknowledge Disable 3 TOA this bit is a Time Out Access Enable 4 GIE this bit is a Global Interrupt Enable 5
41. nd Acromag termination panels or user defined terminations can be quickly mated to the transition module connectors Pin assignments are defined by the IP I O Mapping to VME64x Standard ANSI VITA 4 1 1996 Connectors A through D are 50 pin SCSI 2 right angle female connectors AMP Connectors are high density and there is one connector for each IP module marked with A B C amp D on the transition module panel These connectors include spring latch hardware and 30 microns of gold in the mating area for excellent connection IP Field I O Connectors IP modules A through D The field side connectors of IP modules A through D mate to connectors P5 P7 and P9 respectively on the carrier board IP location is silk screened on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly P3 P5 P7 and P9 are 50 pin male plug header connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 756 for assembly details Pin assignments for these connectors are made by the specific IP model used and correspond identically to the pin numbers of the transition module panel connectors IP Logic Interface Connec
42. ng to the IP interrupt request 3 The VME64x bus host interrupt handler asserts IACK and the level of the interrupt it is seeking on 01 03 4 When the asserted VME64x bus IACKIN signal daisy chained is passed to the AVME9670 the carrier board will check if the level requested matches that specified by the host If so the carrier board will assert the IntSel line to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to IntReq0 A1 high corresponds to IntReq1 5 The IP puts the appropriate interrupt vector on the local data bus 000 007 if an 008 O interrupter 000 015 if a D16 interrupter and asserts to the carrier board The carrier board passes this along to the VME64x bus D08 O or D16 and asserts DTACK 6 The host uses the vector to point at which interrupt handler to execute and begins its execution 7 Example of Generic Interrupt Handler Actions A Disable the interrupting IP by writing a 0 to the appropriate bit in the IP Interrupt Enable Register B Take any IP specific action required to remove the interrupt request at its source C Clear the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Clear Register D Enable the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Enable Register 8 Ifthe IP interrupt stimulus has been removed and n
43. o other IP modules have interrupts pending the interrupt cycle is completed i e the carrier board negates its interrupt request A If the IP interrupt stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed then the IP should be disabled or reconfigured B If other IP modules have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the carrier board Refer to the Block Diagram shown in the Drawing 4501 757 as you review this material CARRIER BOARD OVERVIEW The carrier board is a VME64x bus slave board providing up to four industry standard IP module interfaces for the AVME9670 The carrier board s VME64x bus interface allows an intelligent single board computer VME64x bus Master to control and communicate with electronic devices that are external to the VME64x bus card cage The external electronic hardware is linked to the carrier board rear access via a transition module TRANS 200 The electronic link from the field I O connections to the carrier board is made via the IP module selected for your specific application To facilitate easy connection of external devices to the IP field I O pins of the carrier board optional Termination Panels are available SCSI 2 cables connect a 50 pin IP field connector the transit
44. on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag INDUSTRIAL I O PACK SERIES AVME9670 VME 64x 6U CARRIER BOARD 6 0 SPECIFICATIONS PHYSICAL AVME9670 6U 9 187 inches 233 3 mm 6 299 inches 160 0 mm 0 062 inches 1 59 mm Max Component Height 0 550 inches 13 97 mm Recommended Card Spacing 0 800 inches 20 32mm Connectors P1 amp P2 bus DIN 41612 160 pin Type C Level Il J3 Type B Right Angle Female 95 contacts with upper ground shield PO VME64x bus P3 5 7 9 IP Field l O 173280 3 or equivalent P4 6 8 10 IP Logic Interface 173280 3 or equivalent Power Board power requirements are a function of the installed IP modules This specification lists currents for the carrier boards only The carrier boards individually fil
45. ormat to simplify communication with Acromag IP modules All functions are written in the programming language and can be linked to your application Refer to the README TXT file in the root directory on the diskette for more details and the info9670 TXT files of the AVME9670 subdirectories that correspond to your carrier model 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power V CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitiv
46. r the boards are considered non isolated since there is electrical continuity between the VME64x bus and the IP grounds Therefore unless isolation is provided on the IP module itself the field I O connections are not isolated from the VME64x bus Care should be taken in designing installations without isolation to avoid ground loops and noise pickup This is particularly important for analog I O applications when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IP input output modules 3 0 PROGRAMMING INFORMATION This Section provides the specific information necessary to operate the AVME9670 non intelligent carrier board The board is addressable on 1K byte boundaries in the Short A16 Address Space This Acromag VME64x bus non intelligent slave carrier board has a Board Status register but no identification information Identification information is provided per the Industrial I O Pack logic interface specification on the mezzanine IP boards which are installed on the carrier The 1K byte of memory consumed by the board is composed of blocks of memory for the I O and ID spaces of up to four IP modules The rest of the 1K byte address space is unused or contains registers or memory specific to the function of the carrier board The memory map for the AVME9670 is shown in Ta
47. rd uses a Field Programmable Gate Array FPGA to handle the bus interface and control logic timing Upon power up the FPGA automatically clocks in configuration vectors from a local PROM to initialize the logic circuitry for normal operation This time is measured as the first 145mS typical after the 5 Volt supply rises to 2 5 Volts at power up The VME64x INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD bus specification requires that the bus master drive the system reset for the first 200mS after power up thus inhibiting any data transfers from taking place IP control registers are also reset following a power up sequence disabling interrupts etc see Section 3 for details DATA TRANSFER TIMING VME64x bus data transfer time is measured from the falling edge of DSx to the falling edge of DTACK during a normal data transfer cycle Typical transfer times are given in the following table Data Transfer Time All Carrier Registers 450 nS Typical IP Registers 450 nS Typical If No Wait States See IP module specifications for information on wait states IP module register access time will increase by the number of wait states multiplied by 125nS the period of the 8 MHz clock FIELD GROUNDING CONSIDERATIONS Carrier boards are designed with passive filters on each supply line to each IP module This provides maximum filtering and signal isolation between the IP modules and the carrier board Howeve
48. rresponding IP acknowledge signal which is lengthened by the logic in the FPGA on the carrier board to make the access visible to the user This means that frequent accesses to an IP will result in constant LED illumination The LED s indicate I O memory interrupt acknowledge and ID space accesses Note that the LED s will not illuminate during accesses of carrier board registers or accesses to IP modules which are not physically present or to unsupported memory space Additional information about the error status of the IP modules can be obtained by reading the IP Error Register GENERATING INTERRUPTS Interrupt requests do not originate from the carrier board but rather from the IP modules Each IP may support 0 1 or 2 interrupt requests The carrier board processes the request from the IP and uses the Interrupt Level Register data to map the request to the desired VME64x bus interrupt level if locally enabled within the Interrupt Enable Register and globally enabled within the Carrier Board Status Register The carrier board then waits for an interrupt acknowledge from the VME64x bus host after asserting the appropriate VME64x bus interrupt request When the carrier board recognizes an interrupt acknowledge cycle on the VME64x bus it checks for a match of the IP interrupt requests If none is pending or the interrupt level does not match it will pass the acknowledgment signal along without consuming it If there is a match the ca
49. rrier board will initiate an acknowledgment cycle with the requesting IP which must supply the interrupt vector during the cycle The VME64x bus interrupt acknowledge signal is consumed by the carrier board during a valid cycle Note that if multiple IP interrupt requests are pending then the carrier board will prioritize the requests based on the last interrupt serviced Lowest proirity will be given to the last interrupt serviced Interrupt Configuration Example 1 Clear the global interrupt enable bit in the Carrier Board Status Register by writing a 0 to bit 3 2 Write interrupt vector to the location specified on the IP and perform any other IP specific configuration required do for each supported IP interrupt request 3 Write to the Interrupt Level Register to program the desired interrupt level per bits 2 1 0 4 Write 1 tothe IP Interrupt Clear Register corresponding to the desired IP interrupt request s being configured 5 Write 1 to the IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the carrier board by writing 1 to bit 3 global interrupt enable bit in the Carrier Board Status Register Sequence of Events For an Interrupt 1 The IP asserts an interrupt request to the carrier board asserts IntReq0 or IntReq1 2 The AVME9670 carrier board acts as an interrupter in making the VME64x bus interrupt request asserts IRQx correspondi
50. s PO and P2 access to field I O signals mapped per the VME64x IP I O ANSI VITA 4 1 1996 specification A transition module Acromag Model TRANS 200 routes the field I O signals from PO and P2 to the rear of the cage system with separate SCSI 2 connectors for each IP module All SCSI 2 connectors can be connected with a standard SCSI 2 cable from the transition module without interference from boards in adjacent slots Spring latch hardware on the transition module provide for excellent connection integrity and easy cable removal Optional Screw Termination Panel Model supports field connection via screw terminals using the optional DIN rail mount termination panel Model 5028 182 Memory Space Access Support IP memory space accesses are supported and software configurable from 1Mbyte to 8Mbytes in the VME64x bus standard address space Supports Two Interrupt Channels per IP Up to two interrupt requests are supported for each IP The VME64x bus interrupt level is software programmable Additional registers are associated with each interrupt request for control and status monitoring Interrupt Priority Control Interrupts use a proirity shifting scheme based on the last interrupt serviced This prevents the continuous interrupts of one IP module interrupt request from blocking the interrupts of other IP modules e Supervisory Circuit for Reset Generation microprocessor supervisor circuit provides power on power off
51. ser can create a board which is customized to the application which saves money and space a single carrier board populated with IP modules may replace several dedicated function VMEbus boards The AVME9670 non intelligent carrier boards provide impressive functionality at low cost Model is available in one standard VME64x bus 6U size with support for up to four IP modules MODEL VME64x Supported Board Size IP Slots Operating Temperature Range KEY AVME9670 FEATURES Supports Four IP Modules Provides an electrical and mechanical interface for up to four industry standard IP modules IP Modules are available from Acromag and other vendors in a wide variety of Input Output configurations to meet the needs of varied applications INDUSTRIAL I O PACK SERIES AVME9670 VME64x 6U CARRIER BOARD Provides Full IP Data Access Supports accesses to IP input output memory identification data and interrupt spaces Full IP Register Access Makes maximum use of logically organized programmable registers on the carrier boards to provide for easy configuration and control of IP modules The only hardware jumper settings required on the carrier boards set the base address of the card in the VME64x bus short I O space e LED indicators Simplify Debugging Front panel LED s are dedicated to each IP module to give a visual indication of successful IP accesses Rear Backplane Connectors Access I O Rear backplane connector
52. slots to the rear of the AVME9670 Slots A D Length Standard lenght is 2 meters 6 56 feet Consult factory for other lenghts It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil oraided shield inside a PVC jacket Connectors One End SCSI 2 50 pin male connector with backshell and spring latch hardware Other End IDC 50 pin female connector with strain relief Keying The SCSI 2 connector has a D Shell and the IDC connector has a polarizing key to prevent improper installation Schematic and Physical Attributes See Drawing 4501 758 Electrical Specifications 30 VAC per UL and CSA SCSI 2 connector spec s 1 Amp maximum at 50 energized SCSI 2 connector spec s Operating Temperature 20 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For Carrier Boards Application To connect field I O signals to the Industrial Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the TRANS 200 transition module via a cable Model 5028 187 Field signals are accessed via screw terminal strips The terminal strip markings on the termination pane
53. ter and provide 5V 12V and 12V power to each IP from the VME64x bus Note that the VME64x bus standard does not support 15V and 15V supplies but the carrier boards are designed to handle these if needed for unique situations The power supply filters are typically capable of over 40dB of insertion loss for undesirable noise and oscillations in the 100MHz frequency range and over 20dB of insertion loss for noise and oscillations in the 10MHz frequency range Power line fuses are dedicated to each IP module for fusing of the 5 12 and 12 volt supplies These fuses are used to protect the power suppy in the VME64x bus cage system The power failure monitor circuit provides a reset to IP modules when the 5 volt power drops below 4 27 volts typically 4 15 volts minimum Currents specified are for the carrier board only add the IP module currents for the total current required from each supply 5 Volts 45 time of 100 m Seconds 12 Volts 5 or 15 Volts 5 12 Volts 5 or Not Used OmA Not Used VME64x bus COMPLIANCE This device meets written VME specifications per VME64 ANSI VITA 1 1994 VME64 Specification Extensions ANSI VITA 1 1 1997 and IP I O Mapping to VME64x ANSI VITA 4 1 1996 50 pin male plug header AMP 50 pin male plug header AMP AVME9670 E 350 mA Typical 525 mA Maximum
54. to Flat Ribbon Shielded MODEL 5028 1871 2 piece 16 TERMINATION PANEL MODEL 5025 552 16 VME64x TRANSITION MODULE MODEL TRANS 200 16 DRAWINGS Page 4501 755 AVME9670 JUMPER 8 IP LOCATIONS 17 4501 756 MECHANICAL ASSEMBLY DRAWING 18 4501 757 AVME9670 BLOCK DIAGRAM 19 4501 758 CABLE SCSI 2 to Flat Ribbon Shielded 20 5028 187 cete tens 4501 464 TERMINATION PANEL 5025 552 21 4501 760 VME64x TRANSITION MODULE 200 esent 22 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The AVME9670 VME64x bus card is a carrier for the Industrial Pack IP mezzanine board field modules The Industrial I O Packs field I O exits the carrier via the rear panel per the VME64 Extensions ANSI VITA 1 1 1997 The carrier boards facilitate a modular approach to system assembly since each carrier can be populated with any combination of analog input output and digital input output IP modules Thus the u
55. tors IP modules A through D The logic interface sides of IP modules A through D mate to connectors P4 P6 P8 and P10 respectively on the carrier board IP location is silk screened on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly P4 P6 P8 and P10 are 50 pin male plug header connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 756 for assembly details Pin assignments for these connectors are defined by the IP module specification and are shown in Table 2 2 Table 2 2 Standard IP Logic Interface Connections P4 6 8 10 Pin Description Number Pin Description Number Do 4 058 29 Do2 6 memset 3 04 8 3 05 9 DA 54 06 0 10544 3 Do 13 DMAEnd 38 A 3 Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by the carrier board VME64x bus Connections for P1 Table 2 3 indicates the pin assignments for the VME64x bus signals at the P1 connector The P1 connector is the upper rear connector on the AVME9670 board as viewed from the front The connector consists of 32 rows o
56. trol the VME64x bus interrupt request level associated with IP interrupt requests as illustrated in the following table Reset Condition Set to 0 no interrupt request VME64x bus Interrupt Level None Oo 0 IP Error Register Read Base C5H The IP Error Register allows the user to monitor the Error signals of IP modules A through D The Industrial I O Pack specification states that the error signals indicate a non recoverable error from the IP such as a component failure or hard wired configuration error Refer to your IP specific documentation to see if the error signal is supported and what it indicates MSB D7 LSB DO Not Not Not Not Not Not Not IP Used Used Used Used Used Used Used Error Where Bits 7 6 5 4 3 2 1 Bit 0 IP Error Read Not used equal 0 if read This bit will be a 1 when any IP module asserts its Error signal This bit will be O when there is no error Reset Condition Bit will be 0 no error unless driven by IP IP Memory Enable Register Read Write Base C7H The IP Memory Enable Register allows the user to program which IP modules will be accessible in the standard A24 memory Space An enable bit is associated with each IP A through D This register must be used in conjunction with the IP Memory Base Address amp Size Registers to fully define the addressable memory space of the IP modules Enabling IP memory
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