Implementing a Boolean function in LabVIEW FPGA on the Xilinx
Contents
1. This will add the FPGA Target to the Project Explorer view You see this target is placed under My Computer Project Explorer Untitled Project 1 SEE File Edit View Project Operate Tools Window Help gt Sa x OO x eee R Fall Items Files S g Project Untitled Project 1 a amp He FPGA Target Dev1 Spartan 3E Starter Board i Bb OnboardClock i i BP Dependencies L Build Specifications f E3 Dependencies t jee Build Specifications Step 4 Adding FPGA I O The next step we make is adding FPGA I O s that we will use in this project to the Project Explorer view For this you have to right click the FPGA Target you added in Step 3 Select New FPGA I O File Edit view Project Operate Tools Window Help gt Sa xX OOX Files S fb Project Untitled Project 1 E My Computer lt a pao o Virtual Folder Add ieee Control odia a ae Statechart Collapse All i FPGA TIO Remove From Project R F2 FPGA Base Clock ename FIFO Help Memory Properties The next screen will appear 2008 Vincent Claes ki s Hogeschool Limburg New FPGA 170 Available Resources New FPGA IJO Slide Switches Name Resource Sw0O Swi Sw2 SW Push Buttons Discrete LEDs LCD YGA Port 4 Remove Digital to Analog DAC Analog to Digital ADC StrataFlash SPI STMicro Serial F2. Peter Gesprek Lab 1 Boolean Index of jgan Project Explor FPGA_VI vi Bl FPGA_VI viFr 2008 Vincent Claes When the Bitstream gener and the server status is set to tools have done their job FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target S le ee i LabVIEW FPGA Compile Server 8 5 0 Compile Status Server Service ID Wo wos signal does not drive any load ois in the design signal does not drive any load pins in the design signal does not drive any load pins in the design signal does not drive any load pins in the design DRC detected 0 errors and 24 warnings Saving Il File in spartan3estarter Il Creating bit map Saving bit stream in spartan3estarter bit Saving bit stream in spartan3estarter rbt Bitstream generation is complete Compile List Lab1_BooleanLogic vproj FPGA Target lt a Q Windows Medi Peter Gesprek Lab 1 Boolean You get a implementation details of your code FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target Successful Compile Report Summary Advanced Client Service ID Lab1_Boolw7C_FPGATarg A _FPGA_VI_aMe95chd cD Client Name Status Coe ation is Start Time e __sosere J __a__ http fusers b Project Explor FPGA_VI vi Bl Successful Compile Report You have to Press O X Status Compilation successful Compilation Summary Design Summary Report Number of Exter
3. Opslaan als type Projects vproj D IOS 2008 dos Hogeschool Limburg Vincent Claes Step 5 Running the FPGA VI This step is where we created the vi for We designed it to run on an target For starting the executing of this vi we have to press the Run arrow on either the Block Diagram or on the Front Panel FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target olx FPGA_VI vi Block Diagram on Untitled Project 1 FPGA Target SEE File Edit View Project Operate Tools Window Help File Edit wiew Project Operate Tools Window Help 13pt Application Font x D 13pt Application Font The first step LabVIEW does is Generating Intermediate Files This files will be send to the Xilinx Synthesis Tools But this is not important for us as application developers FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target PE X FPGA_VI vi Block Diagram on Untitled Project 1 FPGA Target Generating Intermediate Files Generating intermediate files This may take a Few minutes Stage 5 of 6 Printing intermediate Files Ut Booms LS Nero Ven Peet Labi_BooleanLogic wproyFPGA Target S y OS C windows Medi P Peter Gesprek Lab 1 Boolean idex of jgan FPGA VI vi Bl Generating Int 2008 Vincent Claes In this step you see that LabVIEW is starting the Compile Server This Compile Server can also be executed on another more powerful machine that is in your
4. option Project Explorer Lab1_BooleanLogic v Eek FPGA_VI vi Block Diagram on Lab1_BooleanLogic lvproj FPGA Target File Edit View Project Operate Tools Window Help ile Edit wiew Project Operate Tools Window Help is aixooxiwkia ealll pale ale A Files B i Project Lab1_BooleanLogic lvproj S E My Computer amp Fe FPGA Target Dev1 Spartan 3E Starter Board oo Slide Switches i i gh 5W0 Slide Switches l a SW Slide Switches Discrete LEDs LB LEDO Discrete LEDs i OnboardClock Open Explore i Show in Files View Ctrl E a BP Depende iu ES Build Spe Print Run Find Save Save S Target Specific Properties Compile Reconnect to Compilation Download Download VI To Flash Memory Remove From Project Rename Replace with Properties ab1_BooleanLogic lyproj FPG4 Target lt You will see that there are some previous explained steps executed When the Successful Compile Report shows up you have to press the OK button Now we will download it to the Miew 2008 Vincent Claes dos Hogeschool Limburg Flash For this you have to go to the Project Explorer view and do a right mouse click on the FPGA VI you created Then choosing the Download VI to Flash Memory option will start downloading it to the Spartan 3E starter board flash Project Explorer
5. os Hogeschool Limburg Lab 1 Implementing a Boolean function in LabVIEW FPGA on the Xilinx SPARTAN 3E Board Keywords LabVIEW LabVIEW FPGA Xilinx SPARTAN3E Starter Kit Implementing a Boolean Function Miew 2008 Vincent Claes KIDS Hogeschool Limburg Introduction Welcome to Labl in the serie of programming a SPARTAN3E Starter Kit by use of LabVIEW FPGA These labs are created by Vincent Claes If you encounter problems using this labs or want some advice consultancy on LabVIEW and especially LabVIEW FPGA you can always contact the author These labs are free to use however to show respect to the author please email him when you use them with your contact details feedback is also welcome Contact Information Vincent Claes claesvincent gmail com http www linkedin com in vincentclaes Software Requirements e LabVIEW 8 5 or above LabVIEW 8 5 FPGA module e XUP Spartan3E starter board download for free from https lumen ni com nicif us infolvfpgaxilsprtn content xhtml Hardware Requirements e Xilinx Sparctanse Starter kit http www xilinx com products devkits HW SPAR3E SK US Gelem e User manual www xilinx com support documentation boards_and_kits ug23 O pdf Getting Started When you want to use this labs you have to setup your board This labs are written for the Xilinx SPARTAN3E Starter Kit so it 1S quite interesting to read the user manual of the board Be sure to plug in the USB cable
6. plug in the Power cord and Switch the board on before starting the lab 2008 Vincent Claes wos Hogeschool Limburg Step 1 Starting LabVIEW The first step is to start the National Instruments LabVIEW 8 5 environment F PHP Editor gt fan Download Accelerator Plus DAP gt E adobe Bridge c53 F Adobe Device Central C53 Programma s A Documenten g Instellingen gt GY Adobe Dreamweaver C53 E T Adobe ExtendScript Toolkit 2 Se Adobe ExtendScript Too gt A Zoeken d P Adobe Extension Manager C53 Help en ondersteuning Xilinx ISE 9 2i gt a M Actel Libero IDE v8 1 Beta gt a Uitvoeren l m F Actel Libero IDE v8 1 A T SynapticAD gt 3 El Toro afmelden T Lavalys gt Computer uitschakelen R National Instruments LabVIEW 8 5 T MProg 3 0a gt start eS Cams 7 Digi MaxStream gt Step 2 Create a LabVIEW project After we have started the LabVIEW environment we get the following screen gt Getting Started File Operate Tools Help id LabVIEW 8 o 5 Licensed for Professional version New To Lab IEW tea Blank VI Getting Started with LabVIEW H Empty Project LabYIEW Fundamentals Real Time Project Guide to LabVIEW Documentation O More LabYIEW Help Upgrading Lab IEW LabYIEW Project Enhancements bl E JEW FPGA Untitled Project 2 lyproj E Ei GA PS2 MOUSE P52 MOLISE FPGA vproj Pears im E 008PWO
7. Board amp Slide Switches is hy SWO Slide Switches i gy 5W1 Slide Switches J Discrete LEDs is ge LEDO Discrete LEDs 8 OnboardClock jm i BP Dependencies Yj Build Specifications 5 2P Dependencies i Build Specifications It is also a good idea to save the project file for this select in the Project Explorer New then Save As Project Explorer Untitled Project 1 TBR aG Edit Yiew Project Operate Tools Window Help New VI Ctrl N i mF All Open Ctrl 0 Close Ctrl w Close All Save Ctrl S arter Board Save All Ctrl Shift 5 Save All this Project Save for Previous Version Revert New Project Open Project Save Project Close Project Page Setup Print Print Window Ctrl P YI Properties Ctrl I Recent Projects gt Recent Files gt Exit Ctri Q I did use the name Labl_BooleanLogic Project Explorer Untitled Project 1 BAN File Edit Yiew Project Operate Tools Window Help 6 a XO Xl ee ee m F all Items Files S fe Project Untitled Project 1 S My Computer amp i FPGA Target Dev1 Spartan 3E Starter Board Ep Slide Switches Name the Project Untitled Project 1 Opslaan in 9 Ni Labs by VincentClaes 7 em Onlangs geopend 3 Bureaublad Mijn documenten Deze computer Min Bestandsnaam Lab _BooleanLogic netwerklocaties K3 oO ras
8. network for this please see the information on the NI website FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target O X FPGA_VI vi Block Diagram on Untitled Project 1 FPGA Target ieee DOU DE VI for FPGA lt ne a Ta i eo Refresh Updates the client with the latest information from the server Disconnects from the Compile Server while the YI continues to compile To reconnect to the Compile EG right click the YI in the target and select Reconnect to Compilation or click the Run button on the VI Stop Compilation Stops the compilation on the Compile Server and closes the client Lab1_BooleanLogic lvproj FPGA Target lt FPGA_VI vi Front Panel on Untitled Project 1 FPGA Target OX Ele Edt Yiew Sale Tools Window Help LabVIEW FPGA Compile Server 8 5 0 Compile Status Server Service ID Client Service ID Se es Time Lab1_Boolv7C_FPGATarg A7_FPGA_VI_aMa Schd cD 13 03 2008 11 34 04 O OoOO Last e Time p VHDL 13 03 2008 11 34 26 OO Details Using Flow File C NIFPGA amp 85 srvrTmp LOCALH 1 LAB1_Be1 fpga flw Using Option File s C NIFPGA85 srvrTmp LOCALH 1 LAB1_Be1 balanced opt C NIFPGA85 srvrTmp LOCALH 1 L4B1_B 1 bitgen opt C NIFPGA8S srvrTmpiLOCALH 1 LAB1_Be1 vhdl_area opt Creating Script File rs Starting program xst xst ifn Spartan3EStarter_xst scr sam alae xst log configure Server Status Compia S OS eme so conte stoner
9. see the option Run when loaded to FPGA Make sure you select this option Then press the OK button FPGA Target Properties wm General Top Level Clock Conditional Disable Symbols Name FPGA Target Target Class Spartan 3E Starter Board VI Properties J Run when loaded to FPGA Miew 2008 Vincent Claes adios Hogeschool Limburg Project Explorer Lab1_BooleanLogic lv Seles FPGA_VI vi Block Diagram on Lab1_BooleanLogic vproj FPGA Target wy Eile Edit view Project Operate Tools Window Help ile Edit Yiew Project Operate Tools Window Help esM ixaoxiiskia ealif Brae ale ave All this Project B il Project Lab1_BooleanLogic vproj My Computer E FPGA Target Dev1 Spartan 3E Starter Board GD Slide Switches i if gh 5W0 Slide Switches ke ge SW Slide Switches Discrete LEDs i LEDO Discrete LEDs i e H OnboardClock io bej FPGA VI vi i BP Dependencies Yj Build Specifications s amp Dependencies be Build Specifications ab1_BooleanLogic lvyproj FPG4 Target lt r Gesprek w Lab 1 Boolean http fusers t Project Explor FPGA YI vi Bl FPGA VI vi Fr LabVIEW FPG NL i a AT We must recompile the VI because we made a change Do this by going to the Project Explorer view Click with the Right Mouse button on the FPGA VI you have created for this project Select the Compile
10. Addons gt Favorites Select a VI b Fixed Point Math Place 2 I O Nodes on the Block Diagram of the LabVIEW FPGA vi Untitled 1 Block Diagram on Untitled Project 1 FPGA Target Se File Edit Yiew Project Operate Tools Window Help A E D Yo Item ee D YO Item4 2008 Vincent Claes dos Hogeschool Limburg Now do a right mouse click on one of the I O Nodes Select Select FPGA I O then Slide Switches then SWO Untitled 1 Block Diagram on Untitled Project 1 FPGA Target mB File Edit View Project Operate Tools Window Help a tems Visible Items Help Description and Tip Set Breakpoint FPGA I O Palette Create Replace Find FPG Show Error Terminals Add Element Add New FPGA I O j Properties _ Discrete LEDs gt Swit i You should see that the I O node is filled with a green SWO label The color green is standing for a Boolean variable This is correct since a slider switch can only have the value of true or false Untitled 1 Block Diagram on Untitled Project 1 FPGA Target Se File Edit View Project Operate Tools Window Help SST amp YO Item This project will be using 2 slider switches so we have to add another FPGA I O For this do a right click on the FPGA I O you just filled with SWO Select Add Element Untitled 1 Block Diagram on Untitled Project 1 FPGA Target File Edit View Project Operat
11. ILabVIEW FPGA Untitled 1 vi Conditional Terminals in For Loops fm E chart LY FPGA SPARTANSE FPGA_VI vi iera anenee E E BYIEW FPGA P52 MOUSE Untitled 1 wvi Web Resources E Generator LabVIEW FPGA FPGA_YI vi B Browse Discussion Forums Training Courses Lab IEW Zone Examples FPGA Project QA Find Examples We have to create an Empty Project where we will add the Xilinx Spartan3E starter board on as a hardware target In a future lab I will explain how we can create a HOST vi this is a LabVIEW application that runs on a desktop PC that communicates with a LabVIEW FPGA vi 2008 Vincent Claes wios Hogeschool Limburg Step 3 Add the Spartan3E board as a hardware target The next screen shows the Project Explorer view of the Empty PROJCCL Chat We Just Created Be i Project Explorer Untitled Project 1 SE File Edit View Project Operate Tools Window Help 26 x Items Files S fg Project Untitled Project 1 S g EE i BP Dependencies i ES Build Specifications Now we have to add the Spartan3E starter board as a Hardware target For this we do a right click on My Computer in the Project Explorer view We select New and then Targets and Devices Project Explorer Untitled Project 1 SEE File Edit Yiew Project Operate Tools Window Help o x er be Ry F A Items Files i Project Untitled Project 1 re Dep add Sim
12. Lab1_BooleanLogic tv E E X gt FPGA Vivi Block Diagram on Labi_Booleanl ogic lvproj FPGA Target BAZ File Edit view Project Operate Tools Window Help a ile Edit View Project Operate Tools Window Help jaogalixnaax e n a Fal if Items Files B el Project Lab1_BooleanLogic lyproj S E My Computer amp F FPGA Target Dev1 Spartan 3E Starter Board GO Slide switches i i i GB SWO Slide Switches i bt gy Swe Slide Switches B 0 Discrete LEDs i i LEDO Discrete LEDs 5 fb OnboardClock e Open na Del Explore o bs Bul Show in Files View Ctri E j BP Depen _ i Build 5 Print Run Find gt Save Save s Target Specific Properties Compile Reconnect to Compilation Download Download VI To Flash Memory Remove from Project Rename F2 Properties When this box appears the LabVIEW FPGA VI is downloaded to the Flash LabVIEW FPGA Status Download successful Now you can pull out the USB cable out of the Xilinx Spartan3E board and press the PROG button on this board You will see that the function is implemented in it Enjoy Vincent Claes XIOS Hogeschool Limburg Department of Industrial Sciences and Technology Universitaire Campus Agoralaan Gebouw H B 3590 Diepenbeek Belgium vincent claes xios be tel 32 11 26 00 39 fax 32 11 26 00 54 mobile 32 478 35 38 49 Miew 2008 Vincent C
13. TTT je gt x a Q gt m a Not Exclusive v gt Not Or gt y Vi i 4nd Array Ele Number ToB m B p Boolean Arra Boolean To 0 F Miew 2008 Vincent Claes adios Hogeschool Limburg Wire the SWI and SWO FPGA I O to the Exclusive OR inputs Wire the output of the function to LEDO Untitled 1 Block Diagram on Untitled Project 1 FPGA Target File Edit wiew Project Operate Tools Window Help amp 7 13pt Application Font Font Ron id a aaa SSS seeeeee Sie i Leno auu swo amp When you implement the function like presented above the function will run only once We would like to implement it that it runs continuously For this we place a While Loop around it and we wire a Boolean False constant to the stop Condition of this loop This you normally don t do on a PC because this will put your PC in a never ending loop The While Loop you find on the Functions Palette Untitled 1 Block Diagram on Untitled Project 1 FPGA Target File Edit Yiew Project Operate Tools Window Help Functions a R search sven P v Programming L Structures D D z F Wu Swi JS D D For Loop D eee ae eee gt UU LEDO eee Pn SWO fe LOCAL Local variable Global variable aN Decorations Feedback Node gt Addons gt Favorites Select a YI gt Fixed Point Math 2008 Vincent Cl
14. aes a dos Hogeschool Limburg fe Constant Create Control Create Indicator JZ Stop if True Continue if True p Now it is time to save your vi that you created for the FPGA You do this by selecting New Save As in either the Front Panel or the Block Diagram Untitled 1 Block Diagram on Untitled F Edit view Project Operate Tools Winc New VI Ctrl N New Open Ctrl o E Close Ctrl Close All Ctrl S Ctrl Shift 5 Save For Previous Version Revert New Project Open Project Save Project Close Project Page Setup Print Print Window Ctrl P VI Properties Ctrl I Recent Projects b Recent Files gt Exit Ctr Q The name I usually use is FPGA_VI for the vi running on the FPGA Name the VI Untitled 1 Opslaan in Ni Labs by VincentClaes Onlangs geopend Bureaublad Mijn documenten Deze computer Bestandsnaam FPGA_ l Min Opslaan als type 1s vi vit netwerklocaties New LLB Miew 2008 Vincent Claes adios Hogeschool Limburg In Project Explorer you should see the following Project Explorer Untitled Project 1 SE File Edit view Project Operate Tools Window Help lS l x Oo Xi et Ry F al Items Files S b Project Untitled Project 1 E My Computer amp i FPGA Target Dev1 Spartan 3E Starter
15. all the steps right you have to see in the left corner of either the Front Panel or Block Diagram the name of the vi you created with FPGA target behind it This shows that the vi you are creating is aimed at the FPGA target Untitled 1 Front Panel on Untitled Project 1 FPGA Target mB Untitled 1 Block Diagram on Untitled Project 1 FPGA Target O X oo S Peer ied p p p gt a 13t Appicaton Font io e i vi Untitled Project 1 FPGA Target lt gt fUntitled Project 1 FPGA Target lt gi 2008 Vincent Claes For now have a look at the Functions Palette which you can see when you click in the Block Diagram on View and then Functions Palette You see that the available functions are different You see FPGA I O Memory amp Fifo and FPGA Math amp Analysis Those are specially for using on FPGA targets Functions v Programming uw o g Ei ag 3 o uw wr o Ss w Bel E z l m A b D lt in amp 7 Y M sa 6 o T o a im o 3 amp uw TE a v 3 G pee o Memory amp FIFO FPGA Math e dik Synchronization a Advanced gt Addons gt Favorites Select a VI gt Fixed Point Math Click in the Functions Palette on FPGA I O Functions v Programming L FPGA 1 0 Ea muu I O Node I O Constant Eas ak I O Method I O Property gt
16. e Tools Window Help A D ee A ae Items p JO Items Help Description and Tip Set Breakpoint FPGA I O Palette gt Boolean Palette gt Create b Replace gt Find FPGA I O in Project Show Error Terminals He Add Element Add New FPGA I O Select FPGA I O gt Properties 2008 Vincent Claes dos Hogeschool Limburg The following is the screen you should have now Untitled 1 Block Diagram on Untitled Project 1 FPGA Target DEAR File Edit View Project ee a Operate Tools Window Help es Pate eS A D YO Item4 Try now to fill the I O Item yourself with SW1 Try also to fill the I O Node that is empty with LEDO This is done by right mouse clicking it then selecting Select FPGA I O In the option of Select FPGA I O you see only the resources you added an the Project Explorer view to the project The following screen will be created Untitled 1 Block Diagram on Untitled Project 1 FPGA Target File Edit View Project Operate Tools Window Help m 5 EE TEW Pan Levo Enn swo Now we will as an example implement an exclusive OR Boolean function into the FPGA From the Functions Palette select Programming Boolean and look for the Exclusive Or function Place this one on the Block diagram Functions v Programming L Boolean o er a v gt 4nd Or a SS Sau swi amp Brn LEDO E gt Pa swo gt
17. ions BP Dependencies i Build Specifications 2008 Vincent Claes Pate Hogeschool Limburg Step 5 Creation of the FPGA VI The next step is the creation of a hardware program that runs on the Xilinx Spartan 3E hardware target For this we do again a right mouse click on the FPGA target in the Project Explorer view Select New VI Be sure that you have right clicked the FPGA target and not My Computer because otherwise you will be creating a vi that runs not in Hardware on the FPGA but on your computer Project Explorer Untitled Project 1 TER File Edit View Project Operate Tools Window Help liSa x OO Xl ae a Fall gB e Project Untitled Project 1 o Re My Computer G re Slide Switches Virtual Folder i de Swe Slide Switc Control i Bey Swi Slide Swite Arrange by i a 7 Discrete LEDs Expand Al Library i E Statechart z i LEDO Discrete L Collapse All i Onboardclock SS FPGA 1 0 p Sa Dependencies yr het anee FPGA Base Clock S Build Specifications Rename FIFO j BP Dependencies i eae Help Memory i Build Specifications Properties This step will open the Front Panel and Block Diagram of the FPGA VI you just started creating The code we will be implementing is an Exclusive OR function The view I always use in LabVIEW is the tile left and right view You can select this by going to Window and then selecting Tile Left and Right We you did
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19. lash Expansion Connectors FPGA Configuration 1 Wire Secure EEPROM DS EE EE EEEE EE EE EE EE E EE E Place new I O in folders On the left side of this screen you see all the resources that are available on the Spartan 3E board To add FPGA I O to the project you have to select it in the left window and press the Add button Now the FPGA I O that you wanted to add has to show up in the window on the right side For this project you have to add SW0O SW1 and LEDO to the project New FPGA 170 Available Resources New FPGA I O Slide Switches Name Resource swo Slide Switches SWO E A Sw1 Slide Switches SW1 welll HLEDO Discrete LEDs LEDo Discrete LEDs LEDO Discrete LEDs LEDO LED1 LED2 LEDS LED4 LEDS Digital to Analog DAC Analog to Digital ADC StrataFlash H xi lt Place new I O in folders C e Ce If we go back to the Project Explorer view we see the FPGA I O that we have added With this I O we will implement an Exclusive OR function Project Explorer Untitled Project 1 Se File Edit Yiew Project Operate Tools Window Help S XO amp Xl er ee Ry E all Items Files S fe Project Untitled Project 1 My Computer 2 EET G Slide Switches i b a SWO Slide Switches ft gh SW41 Slide Switches Discrete LEDs a LEDO Discrete LEDs 86 OnboardClock p DE Dependencies i Build Specificat
20. nal IOBs Number of External Input IOBs Number of External Input IBUFs Number of LOCed External Input IBUFs Number of External Output IOBs Number of External Output IOBs Number of LOCed External Output IOBs 131 0ut of 232 27 27 27 out of 27 104 104 104 out of 104 Number of External Bidir IOBs 0 Number of BSCANs Number of BUFGMUXs Labi _BooleanLogic vproj FPGA Target C Windows Medi P Peter Gesprek Lab 1 Boole http fusers t 1 out of 1 2 out of 24 Project Explor 2008 complete Talen FPGA_VI vi Block Diagram on Untitled Project 1 FPGA Target m 13 03 2008 11 34 04 Last Update Time 13 03 2008 11 36 38 FPGA VI vi Bl message appears the Xilinx synthesis ox FPGA YI vi Fr where you can see the ujer p FPGA_VI vi Block Diagram on Untitled Project 1 FPGA Target 56 100 100 FPGA_VI vi Fr Vincent Claes After you have pressed the Ok button your VI starts running on the FPGA target It is indicated on your screen by the black Run arrow FPGA_VI vi on Lab1_BooleanLogic lvproj FPGA Target FPGA_VI vi Block Diagram on Lab1_BooleanLogic lvyproj FPGA Target SE File Edit Yiew Project Operate Tools Window Help File Edit View Project Operate Tools Window Help T m a Labi_BooleanLogic lvproj FPGA Target elas Windows Medi P Peter Gesprek Try to play with the switches SWO and SW1 on the Spa
21. rtan3E starter board you will see they have an XOR function the led LDO will be on when one of those switches is turned on The problem with this implementation is that when you stop the VI the function is erased on the LabVIEW FPGA board If you don t want this effect you can download this VI to the FLASH of the Xilinx Spartan3E starter board see next step 2008 Vincent Claes xios Hogeschool Limburg Step 6 Implementing the LabVIEW VI into Flash For implementing your VI into the Flash on the Spartan3E Starter board you have to do some things The first thing is setting the option of Run when loaded to FPGA on For this you have to go to Project Explorer Then Right Mouse click on your FPGA target Select the Properties option Project Explorer Lab1_BooleanLogic lv E E K gt FPGA Vivi Block Diagram on Lab1_BooleanLogic vproj FPGA Target BAR File Edit View Project Operate Tools Window Help ile Edit View Project Operate Tools Window Help oeaixoOx ee a ealll pale ale Items Files B il Project Lab1_BooleanLogic vproj My Computer a 5 New gt GO Slide Sw k i Swi Arrange by gt i amp CY Discrete Expand All 2 ER LED Collapse All 4 i b M Onboar i a FPGA Remove from Project lig E3 Depend Rename F2 c b Build Spy Diss is Dependenc Properties g i Build Specific 3 rg 3 3 t In this screen you
22. ulation Subsystem jy Build Virtual Folder Arrange by gt Control Expand All Coll All Library T Variable Help IO Server Properties Class _ _ XControl Statechart Targets and Devices New In the screen that now appears we have to select the XUP starter board select New target or devico gt Add Targets and Devices on My Computer Targets and Devices Existing target or device Discover an existing target s or device s Existing device on remote subnet No items can be added to My Computer QO New target or device Create a new target or device by type Targets and Devices HO FPGA Target rare Jo Joe J A list of Targets and Devices will be shown You have to scroll down till the end and select Spartan 3E Starter board from the Xilinx university Program map 2008 Vincent Claes isis Hogeschool Limburg Add Targets and Devices on My Computer Targets and Devices Existing target or device Discover an existing target s or devices Existing device on remote subnet No items can be added to My Computer New target or device Create a new target or device by type Targets and Devices HO R Series amp PCI 7811R fej PcI 7813R amp PCI 7830R fej PCI 7831R fej PCI 7833R i PXI 7811R fej PxI 7813R Fe PXI 7830R fej PXI 7831R PXI 7833R BO Xilinx University Program Spartan 3E Starter Board gt
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