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1. Run Flow Apply Help TX Technology Setings A Advanced Setings View Technology Schematic f Working Directory miniuart ext clean 2 Ln 313 Col 40 Figure 2 12 Leonardo Schematic Design Flow Guide for ATAOKEL DK C esa issue 1 revision 0 page 11 of 23 2 1 3 POST SYNTHESIS SIMULATION A post synthesis simulation is an optional way of testing the design after synthesis This is done by generating files that can be run in simulation usually with the same simulation tool as the pre synthesis simulation In this case it was a bit tricky since macros generated by the place amp route tool was not fully compatible with the file received from the synthesis tool Macros are design elements that are already predefined in the most efficient way for place amp route so by using them your design will be more efficient The macros were always used in this project even though it should be possible to turn the option off There were even plans to synthesise with macros and without and then compare the result but it was not possible within the timeframe of the project If you are using macros in your post synthesis simulation you need to import them from the place amp route tool IDS Figaro The file you receive from Leonardo if you choose a VHDL file as output see the previous chapter for description on how
2. CSN miniUART ke RON SysCIk clkUnit lt WR N gt IntRx_N gt IntTx_N DataOut RxD gt RxUnit gt lt f Datal w O Un Figure 7 2 mini UART Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 19 of 33 7 2 1 1 1 clkUnit The clkUnit receives the system clock SysCIk and divide it to appropriate speeds for the enables of RxUnit and TxUnit The design was originally made for a clock speed of 40 MHz and was divided down to 155 kHz for the receiver and to 9 6 kHz for the transceiver This was modified to work at 4 MHz which was instead divided down to the mentioned speeds There was also reset functionality for resetting the internal counters The reset was changed to active high SysClk EnableRx gt Reset clkUnit EnableTx Figure 7 3 clkUnit 7 2 1 1 2 RxUnit RxUnit is designed to receive signals at 9 6 kHz It uses the 155 kHz enable signal from clkUnit and samples 16 times and retains the value in the middle The serial RxD signal is received in one end and after one byte has arrived it is put on the parallel output DataIn RxUnit also contains different status signals like Frame Error Output Error and Received Data Ready DRdy These signals are used in a status register among other signals DRdy is used in the control of the dataflow but the others are error flags and only showed on the output never used in the control RxUnit also has
3. Tools amp Equipment list Description Equipment Work Station Office PC XP Pentium 4 2 50GHz 1GB RAM Work Station Lab PC PC9 XP 1 70 GHz 512 MB RAM Motherboard Design Kit ATDH40M from ATMEL Daughterboard Design Kit MQFP160 from ATMEL Rad Hard FPGA Design Kit Part Number AT40KEL040K W1 E Parallel cable Design Kit Standard Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library UART adapter converter Serial cable page 12 of 33 Standard Male Female Logic Analyser Agilent Technologies 1681 AD Pattern Generator Logic Analyser Tektronix TLA 7012 Logic Analyser portable Software Modelsim SE 6 1b From ESA lincense Leonardo Spectrum v2002c 37 OEM Atmel From System Designer 3 0 IDS Figaro 7 6 7 patch level 3a2 From System Designer 3 0 CPS 8 05 From System Designer 3 0 Terminal v1 9b Freeware Free Hex Editor Freeware Table 5 1 Tools and Equipment list 5 2 Testing a small design After reading the documentation the whole design flow was tested with a very simple design to verify that everything was working properly In this case both an AND gate and a counter were taken through the design flow This process was more time consuming than first thought since the software were made for the commercial FPGAs and when working with the RAD Hard FPGA many special cases had to be taken into account First of all System Designer could not
4. Open as a Design or a Macro Figure 2 13 IDS Open Design Then you can choose to open a new design or an old one The old ones are listed in the menus while you start a new design on clicking New Design Design Directory Setup gt i x Design Name Configuration OK adds_unreg AT40KAL _ Design Directory Cancel c XestsWmniniuart test add c tests niniuart_test_add_regout c ttests Macro_test_add3_regout c XMestsMacro test add8 unreg Tools Flow r Tools Flow Description Import Net EDIF Export Net Flat VHDL Exemplar Yerilog Everest Verilog Everest VHDL Export Delay Flat Hier SDF Figure 2 14 IDS Select Design Remove If you chose to create a new design a new window will appear figure 2 14 In that window you can choose a name for your new design which type of netlist to import and which configuration In the last choice it is of course important to choose AT40KAL technology issue revision 0 QC Design Flow Guide for ATAOKEL DK Design Name Design Directory Scie unr es add8 unreg edf Files of Type EDIF Netlist edf es v m a Tools Flow Tools Flow Description Import Net EDIF Export Net Flat VHDL Exemplar erilog Everest Verilog Everest VHDL Export Delay Flat Hier SDF H Figure 2 15 IDS Select Technology After creating your design file or choosing
5. have already instanced all the needed macros so in theory you only need to compile the file from Leonardo together with the files from IDS But since there are some compatibility problems you need to do some modifications before it works First of all it is important to not allow writing buses when you generate the file from Leonardo this is vital because the VHDL files of the macros from IDS do not have buses in there ports Then you also need to call for the AT40KAL library to have the generated file ready for simulation Now you need to retrieve the VHDL model for the generated macros from IDS If you already have generated macros by hand in the IDS tool the models already exist but if they are automatically generated by Leonardo you need to generate the models in IDS The simplest way of doing that is by running the first steps in the place amp route process This process is described in the next chapter and you only have to follow it until you have generated the macros Independent on how you generated the macros you copy the VHDL files from their current folder to a convenient directory The files can be found in figba macro name vhd and is the only VHDL file in the folder After that you need to change the names of all the signals here you have the choice of to make the changes in the file from Leonardo instead but I strongly recommend making the changes in these files This is because as it seems the macros with the same generated
6. revision 0 page 14 of 23 the synthesis tool The only thing that needs to be done is to click Generate It can be interesting to see what is generated so it can be a good idea to look through the macros Now all the macros are created so if you only wanted them for a post synthesis simulation you are done It has been noticed during this project that if you are reopening and old design file IDS has problems to import the old timings constraint setting and they may have to be set again AT40KAL Macro Generators x h I C C Ipm add t f 4 0 Ipm eq 7 0 cx ipm counter tt t t 1 5 0 Ipm counter t t tt 1 5 1 O 5 I i ipm counter tt tt 1 5 2 Ipm counter f ttt 1 5 0 Pitch o Aspect Ratio ooo ipm counter f t f 1 1 5 0 Ipm add t f 7 0 I i Ipm edd t 1_5_0 s Cc ipn it f 7 Ipm_add_t_t_6_0 Ipm_add_t_f_6_0 Mal Macro Type Updated Pin Map File Hame R compone la User Library user40kal lib Browse Figure 2 17 IDS Macro Generator After that you map the design by clicking on map and since there are no settings in this process it is only to wait until it is done Then it is time to choose a part so continue and click part to get the options in the window in figure 2 18 below To reduce the number of parts to choose
7. 2004 11 27 30 0 View Log File Figure 2 26 CPS When everything is set in CPS you power on the board with SW1 and then choose start procedure in CPS You will relatively fast get a log in CPS telling you if the transfer was a success or not If the transfer was successful it is time to read from the EEPROM to the FPGA If you want to be extra careful you can switch off the board before you change the following switches Switch SW4 and SW5 to the Boot from configurator mode described on the board SW4 is set to up and SW5 to down Power on the board if it was off and now the design is implemented into the FPGA Control that the clock goes to the right pin it is changed by a jumper if you use the board oscillator Connect your test equipment to the right pins and then it is time to start testing the design Design Flow Guide for ATAOKEL DK esa mE page 23 of 23 CLOSING REMARK During this process several obstacles were found most of them could be worked around and they can be read about in this document Experiences and feed back have also been gathered to be presented as results in the project report Some of the problems can be better described there and there are also issues not directly connected to the design flow presented in that report It is therefore recommended to also read the project report
8. Input Option ss eene teet inet ein ARS NE NASSER NASA RA ariei Tienie te enne 6 Figure 2 7 Leonardo Constraints Option nee ee trennt tre nr tret rene reiner inrer AKS KAR rr KKR re rer es A Figure 2 8 Leonardo Optimize Option sense amp Figure 2 9 Leonardo Output Option o cccccccccceceescesesseesesseesecnseescnseescesecseesecsesecsceeseeaecsessecsessecaeseseaeeseeaeceesecaeseecaeeseeaeesesaeeteeeeaeens 9 Figure 2 10 Leonardo Output Option I eene eeneneeneee entren erret rerit rene trente ene tre eren rre trenes 9 Figure 2 11 Leonardo Output Option HT rene enet tren ARK RAA treten KR ARR ener enee er KKR re sese eet 9 Figure 2 12 Leonardo Schematic 5 a e RUE RUE REED NF SE ERR 10 Fig re 2 13 IDS Open Designo iet oie nete ec e qe RR EI CE e Ne RD Ee in 12 Figure 2 14 IDS Select Design ecce e ded p Re hich E qp elc er eet ben 12 Figure 2 15 IDS Select Technology e eae e rtc mre ie e ae te e eoe oer d eee ent 13 Figure 2 16 IDS Import EDIF Nelilist itte ee te ehe ene an Ee e e OR EE RE ne e reed 13 Pig re2 7IDS Macro renerator a e ie eto esse eu Bes sua CHEESE EDS VAGGAN KA OE E EEA TRE REEL EE nes een dede ne EVER US 14 Figure 2 18 IDS Select Part se ERE WE QR RE NR TR UR URGERE NUN edet aed 15 Figure 2 19 IDS Part Graphical View ineo eh Tr Rn oen e e RR PESE 16 Figure 2 20 IDS Place amp Route Options oneris inii e eene then teinte sng i A sekr Ne ske treni trennt eerte En ae kr ERS 16 F
9. LED L1 indicates if the power is on or off with the board used in this project you had to be extra careful to keep an eye on the LED since the board had a loose connector Some other settings that must be set before you start are the switches for which mode you are using to download the configuration to the FPGA More information about the different modes can be found in the document AT40K Series Configuration This project used mode 0 which also is the mode best described on the board itself To set the board to mode 0 you put all the four switches CS M2 M1 MO to ground 0 With this mode you first download the configuration to an EEPROM and then to the FPGA from the memory this will be more closely described in the next chapter Design Flow Guide for ATAOKEL DK C e S a issue 1 revision 0 page 22 of 23 2 2 2 DOWNLOAD CONFIGURATION To download the configuration you set the switches SW4 and SWS to download to the EEPROM SWA should be set to down and SWS5 to up After that you start up the CPS tool on your computer and set the right configurations the family should be AT40K and the device AT17LV010 A 1M It can be good to check if this is the component name for your EEPROM you can find more information in the documentation In addition you choose your bst file as input file and if you want to change the location of the output file If you have the same name and location for the output file it will be overwri
10. 1b win32 std ii Loading C Modetech_6 1b win2 ee Goat Were WD Loading C Modeltech_6 1b win32 ieet uart wrapper tb dut td n Loading C Modeltech_6 1b win32 ieer uart wrapper tb dut addr LV euis ie uart wrapper tb dul data buffer out 00001111 oading work uart_wrapperibehy ii Loading CAModellech amp 1bwin32 iee Lael RR E Loading work uart control rtl uart wrapper tb dut wr addr Loading work tun test clillbehv dures HR sd ddan Loading work uart_def body Loading work miniuart uart Juatt wrapper tb dut we n 1 Loading work clkunit behaviour uart wrapper tb dut we n 2 Loading work tunit behaviour uart wrapper tb dut re n 1 Loading work rxunit behaviour s Es up Loading work tam datalr Le 7 Now 200000000 ns i ux E HE zz 75334175 ns to 90185599 ns Now 200 ms Delta 1 Now 200 ms Delta 1 sim uart wrapper tb Limited Visibility Region 75334175 ns to 90185599 ns P Figure 2 3 Modelsim in the wave window esa Design Flow Guide for ATAOKEL DK issue I revision 0 2 1 2 SYNTHESIS The tool used for synthesis was Leonardo Spectrum for Atmel version 2002c 37 OEM _ Atmel which was provided by the evaluation kit The synthesis can be done on many levels for example a simple design will not require many constraints while a more advanced design may need many complicated constraints This is of course also a q
11. ATAOKEL DK C a Sa issue revision 0 page 17 of 23 Now you can compile the design and if you want to follow it step by step you double click on the drawn out FPGA instead of pushing the compile button If you do that a window with an empty FPGA will appear see figure 2 21 At top of that window you now have buttons for the compile flow in the same way as the design flow was shown in the previous steps Ini Place Opt Place Pini Route Opt Route Bit sura ost Figure 2 21 IDS Compile Flow If you now click on Ini Place you will start the initial placement and the whole design will be placed in the FPGA but with no care on placement whatsoever It is not until you push Opt Place you get a placement that is more optimal for timings and area Figure 2 22 shows a design after optimal placement i m gt TO 0 in oo Los SESE QBEO RO B38 AHL Oo o0O 0o oo o00 oa Figure 2 22 IDS Optimize Placement Design Flow Guide for ATAOKEL DK C e S a issue 1 revision 0 page 18 of 23 When you have done the initial routing you do not see much difference in the FPGA unless you zoom in Figure 2 23 demonstrates how you can see the routing between the different LUTs and pins In the figure you can also see that the design has a contention score of ten this means that several connection are made on the same place and if this was the final result the design would not work In mo
12. CHECK indicate that this is so then the first byte is sent to the miniUART and a counter starts to count the bytes sent The process is coded so that it will not send another byte to miniUART until it has stopped sending to the computer This is implemented by an internal ARM signal that after sending a byte will not arm again until INTTX N has stopped being active As a result of this the buffer is not fully used but almost no performance is lost because the system clock is much faster than the transmission speed When all 64 positions are sent the design stop the test and awaits the next command An important note is that all data in the Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 23 of 33 RAMs are read independent on how many bytes of relevant data there is The memories are also read one after another in the same way as it is written so if the RAMs are not filled then there will be bytes of irrelevant data between the wanted data bytes If MEM CHECK is not asserted then the process looks to the SETTING received from UART control and runs the specified test At the present time there are only two different tests that can be run The default one is 32 runs with 8 bits that means that 32 bytes each are sent to the two separate outputs which in turn is fed to the DUT The result is then collected in another RAM through a single bus This setup is very suitable for test on DUTs like adders and mul
13. Engineers through the IEEE 1076 standard Pedroni 2004 It has since then evolved through standard updates a couple of times Because it is standardised it is to a great extent independent from various software platforms As the same design can be simulated and synthesised with tools from different vendors it is not dependent on specific companies That makes it easier to develop designs or Intellectual Products IP now that they can be sold or licensed more independently to others There is more information on how to implement a design into a device in the chapter Project Design Flow Instead of drawing schematics the design can now be described in code This may not be very helpful with very small designs but when it becomes a little bit larger it will be of immensely more help There are roughly three levels of coding in VHDL there is Gate Level Register Transfer Level and Behavioral Level It is possible to use all three levels in the same code but it is good to keep them in mind when planning the design and not to mix them so that it will be hard to follow the code It is also important to remember that all code that can be simulated does not have to be synthesizable VHDL code can look in many different ways even though it has a common structure the example below show a very basic design in VHDL Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 5 of 33 Example 3 1 Library ieee Adding libr
14. Global Glock Input Output A Signal Figure 2 7 Leonardo Constraints Option Optimize is also an important option where you can choose which optimisation effort you want or if you want to remap instead There is also the possibility of choosing different parts of the design to optimise or remap Even though there are many option here the only thing that has been used more frequently in this project is to preserve the hierarchy for debugging purposes It is easier to follow the schematic tool when you have the same build up as in your coding More about this schematic tool will come later on Select design to optimize H D uart control H D run test ctrl D gt ClkUnit H D TxUnit Optimize Remap D gt AxUnit H D miniJART Optimize Effort H D RAM data H uart wrapper H behy XRTL 5 3 FE v Extended Optimization Effort C Ports M Pass1 IV Pass2 C Nets M Pass3 M Pass4 C3 Cells S D control I 4 Optimize For 1 D mun test cj Auto C Delay C Area D miniuart 1 D ram result Hierarchy D DUT RAM C Auto Preserve Flatten D ram I RAR D ram 2 RAH M Addl O Pads EE Ee Re RE GB E Run Flow Apply Help TSE ovtrize f navanced Setings 7 Figure 2 8 Leonardo Optimize Option The last one is the output option and that is also the option that has been used most in this project The main reason was to be able to change the output file so that
15. a read input which enables the receiver FErr CIk Reset OErr Enable gt RxUnit DRdy RD L y Datal RxD atain Figure 7 4 RxUnit 7 2 1 1 3 TxUnit TxUnit receives the 9 6 kHz enable signal from SysClk and sends one bit every enable pulse as long as there is data to send Data is loaded into TxUnit in parallel one byte at a time every time the load signal gets asserted There is only a buffer of one byte which means that one byte can be loaded while it is still sending the previous byte but if a second byte is loaded before the sending is done the first byte will be overwritten without a warning TxUnit have also flags for when the buffer is empty and the output register is empty There is also a synchronous reset in the design Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 20 of 33 Clk TRegE Reset Enable a d TxUnit L 34 WE oa DataO TxD Figure 7 5 TxUnit 7 2 1 1 4 miniUART miniUART is mainly a wrapper for the other parts but it also contains some control functions In addition to connecting internal signals it combines the status signal into one status register asserting control flags IntRx N IntTx N and directs the external enables CS N RD N WR N CS N is the chip enable RD N enables the receiver and WR N activates the transceiver So if CS N and RD N are both enabled then the read signal to the receiver gets asserted If CS N and WR N are
16. aa epe adea eb do Gigi e aida 21 Figure 7 8 run test ON ee estate soe hs Cass dans ine rte eod dta eres Gated beste 22 Figure 7 9 Test with R M s eet eee sala Vtech tum ide 28 Figure 7 10 Test with RAM Grey code ss 28 Figure 7 11 Test with Unreg Aderat a aeri ea tread 29 Figure 7 12 Unreg Adder Higher Constr ie d etg eese 29 Figure 7 13 Test Signals on a RAM at 55 MHz 30 LIST OF TABLES TUBES PP IAE acte etu b Sae ans 8 Table 5 1 Tools and Equipment lists shoes coii Pa bande 12 Table 7 1 Test with RAM nent 28 Table 7 2 Test with RAM Grey code ss 28 Table 7 3 Test with Unreg Mak inu dace et een uoa he eds 29 Table 7 4 Unreg Adder Higher Constr ss 29 Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 1 of 33 INTRODUCTION Microelectronics have at all times been a complicated area in space technology the radiation environment have always created heavy restriction This is still true today but development of new and better devices has steadily opened up this field for new applications FPGAs have been used in space for some time now but that is mostly One Time Programmable devices Only a few reprogrammable FPGA have flown on real space missions but in the near future this technology can cut down on development time and open up for new exciting applications in space The Microelectronics Section in ESA has received a design kit ATAOKEL DK for a reprogr
17. be used by itself and instead the programs included in System Designer had to be used on their own There were also some problems of finding the right library for IDS Figaro but after all the issues were taken care of all of the equipment worked in the end For future guidance a simple design flow guide is included as an appendix in this report Below you can find a print screen from the Logic Analyser demonstrating a working counter It was an 8 bit counter with an asynchronous reset counting clock pulses aq SO 00000100 50000 A A 0000 0001 0000 0010 0000 0011 0000 0100 J Reset 0 D clk FPGA 1 0 1 0 1 0 1 0 1 0 1 0 Figure 5 1 Test Signals with a counter Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 13 of 33 THE SPACEWIRE CODEC 6 1 Additional Preparations For this special test with the SpaceWire node from University of Dundee some extra preparation had to be made The major preparation and the most obvious one were to learn about the SpW technology and this IP core in particular The first step was to read the SpW standard ECSS E 50 12A together with some drafts on possible additions to the standard After getting a general knowledge about SpW the second step was reading the documentation for the IP core the two most important documents were the User Manual and the VHDL Functional Description But also other documents like the RTL Verification User Manual became useful during the proce
18. continuous test run 1000 Reset No Reset by command Table 5 3 Control Section commands in Config mode In most cases 64 bytes were sent to the test Interface 32 bytes to each Input RAM and the default test was run Next chapter will give examples on how these commands can be used and walk through the test sequence step by step e S a User Guide for the Test Interface issue 1 revision 0 page 6 of 7 6 TEST SEQUENCE STEP BY STEP This chapter will give an example on how a normal test sequence could look like and walk through the procedure step by step What will be described below should only be a guideline on what can be done feel free to make improvements and work out other ways to use the Test Interface First of all everything has to be connected the right way See to it that the UART converter is connected to the right pins on the board there are only one pin for receiving one pin for transmitting and one pin each for ground and supply Then a standard serial cable is needed to connect the UART converter with the computer If every device has power and the design is loaded into the FPGA correctly there should not be any more hardware preparations The pins used in this project can be seen in the table below or in the example later on Pin connections 1 0303 Reset 1 0298 A3 RxD 1 0297 CSI A2 START M 1 0292 TxD 1 0288 GCK6 SYSCLK Table 6 1 Pin connections If appropriate software is avai
19. encountered and solutions to some of them in addition to suggestions on improvements Not all problems described are related to the FPGA and its software even issues not related to the main objective are accounted for here Something that early was identified as a difficulty was the single clock input to the embedded RAMs in the FPGA The SpW node in its core did not need dual port asynchronous RAMs to work but the receiver buffer and transceiver FIFO would enjoy a big advantage with such an option The design would have a great benefit of using the RAMs as clock domain interfaces since it is not a trivial problem to get around otherwise Initially a lot of problems with the software System Designer were encountered this could be expected with the lack of previous experience in these typical programs but Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 16 of 33 the learning process could have been made much easier The software belonging to the FPGA was first of all made for commercial FPGAs with a few modifications for this particular device This meant that it was hard to know which part that was applicable for use in this case For instance could not System Designer itself be used but its included parts had to be used by itself instead It is understandable that there is no software specific to such a small area but a better documentation could be suggested Something that also made the working load hea
20. files is not enough Free Hex Editor is also started The prepared files can be seen in table 4 2 The system clock was started at 4 MHz in this case by a pattern generator The design was then reset by having the reset pin connected and unconnected pin 1 0303 in this design Some initial test communication is carried out to see that everything is working before the memories are reset A command sequence could look like this RR 64B RB NULL 64B RB and NULL 64B RUN RR If the RAMs do not have zeros on all positions after the last command NULL 64B RUN RR is run again To send data and commands via Terminal the hex code were either written in the Send window which were followed by a click on the gt Send button or more commonly a file were sent To send a file the Send File was simply pushed where the wanted file could be chosen If new files had to be created in Free Hex Editor the data or commands were simply written in the editor and saved as a hex file If the file were to be used directly after its creation it was made sure that Free Hex Editor were closed down since it otherwise produced a conflict with Terminal After the RAMs been reset 64B RB were sent to load the input RAMs with data and read it back to control that nothing went wrong The system clock was then changed to the test frequency for example 47 MHz This was followed by manually asserting the Start m for a short while to run the test In this c
21. from select Aerospace under Application and the number to choose from will be reduced In this project ATAOKELO40KWIS was used In the bottom of the window you can also see how much area and memory this design will take on this particular device Design Flow Guide for ATAOKEL DK issue revision 0 page 15 of 23 File Edit View Library Flow Tools Options Window Help im 10 4 BRO BSS PAM ras honie Ae amp Part Select x Q HO RESET_ibuf IBUF Architecture Part Hame usable pins Q EC miniuart ONE Atmel at40kal AT4OKALO4OKWVIM 130 E d AT40KALO40KZ1M 233 E sinit GNDO ZERO Add HOI miniuart_ 10 ZERO Package AT40KELO40KWV1M 130 EB 7 any AT40KELO4OKWIS 130 EEE AT40KELO40KZ1M 233 E d PE AT40KELO40KZ1S 233 Aerospace v Cancel SYSCLK ibuf IBUF Speed HL miniuart G 3 1 he any gt Help EC miniuart G SCE H miniuart_1 TxDev x117 o Relative Logic Size Gray and Part Capacity Green 3E C minium im a E vinit g nt 0 FGENTR eg BitCnt 1 FGEN1R Relative Memory Size Gray and Part Capacity Green ee viGNDO ZERO HO miniuart PL miniuart 3 EC miniuart _ NE EC miniuart 1 FGEN1 PL miniuart HC miniuart HL miniuart HL miniuart _ FE o e d Figure 2 18 IDS Select Part After you have selected which part to use it is recommended to assign signals to pins It is of course a possibility to l
22. it could be used for post synthesis simulation Automatically the settings are set to auto which means that the output will be an edf file the netlist to use for place amp route If you instead want to do a post synthesis simulation you most change the output file to a vhd file this you do by choosing VHDL as format For the post synthesis simulation there will also be very useful to not allow writing buses for a better compatibility with the place amp route tool more information about the convenience of this can be found in the chapter post synthesis simulation Anyhow this setting can be switched on and off if you go to the furthest right among the sub option and click on VHDL Out Options In the new window that comes up you can choose to mark or unmark a box for allowing writing busses of the ports Design Flow Guide for ATAOKEL DK issue 1 revision 0 page 8 of 23 Design Flow Guide for ATAOKEL DK issue revision 0 page 9 of 23 Enron 4 Hep TRIP DAD ove Fes Figure 2 9 Leonardo Output Option I lean 2 UART wrapper O vhd Figure 2 10 Leonardo Output Option II J OIC std_logic_vector ABB Figure 2 11 Leonardo Output Option III Design Flow Guide for ATAOKEL DK C a Sa issue 1 revision 0 page 10 of 23 After choosing all the required settings the only remaining thing is to push Run Flow and check the result in the information window to t
23. on how these signals are handled produced is given in the closer description of their various processes Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 21 of 33 SYSCLK x START MEM CHECK RESET gt READ RESULT CSN STOP A pRD_N UART control MEN START_M WE N 2 8 DATA_BUFFER_OUT INTRX N 5 pVR_ADDR 4 ETTING DATA UART IN amp p 2 LADDR Figure 7 6 UART control 7 2 1 2 1 The data in process First of all this process has an asynchronous reset which resets various internal signals addresses and control flags If no reset signal is active it is a synchronous process that is waiting for INTRX N to be asserted when that happens it means that it is time to read a byte If this is the first byte coming in then it is a configuration byte When a configuration byte is received it sends out a flag CON F to the controller process which read in the byte and configure the setting accordingly In the configuration byte information can be given on how many of the following bytes is considered data bytes and should be written to memory instead If that is the case then when the next byte comes in a counter will start counting the bytes received and instead of sending the data to the controller it is written to the two RAMs for incoming data When all the expected data bytes are acquired the process expect the next byte to be a configuration byte and so it continues There are also two options o
24. piae hues atto eique hadas oe ated ape e wads tae ea aes se 4 LIST OF TABLES Table d beEgIDIHOHES Solas emot cto m LE Mua Ee alee d 2 Tabledi LES SOWIE LEE c C eL Pe d 3 Table tad Test Files numero nt 4 Table 5 1 Data Length commands usi ads tectus ve ec veal sates aan de salen pedet teme vieles 5 Table 5 2 Control Section commands in normal mode ss 5 Table 5 3 Control Section commands in Config mode see uma near ee dede ere sne nr sr nr dues 5 Table 6 E Pin CONNCCHONS i dre ete tectae tete tede tete eere ERE 6 e S a User Guide for the Test Interface issue revision 0 page 1 of 7 1 INTRODUCTION The Test Interface is a small design developed during a project to test the performance of a development kit including an SRAM based FPGA from ATMEL AT40KEL Parts of the testing of the FPGA were done by an internal Test Interface inside the FPGA which communicated with a computer through a UART The internal structure of the Test Interface is better described in the project report Performance Test of AT40KEL DK while this document is dedicated to a user description This Test Interface is a very small design with only one purpose but with a possibility to be upgraded and extended 2 OVERVIEW The Test Interface receives data and commands from a computer through a UART When the Test Interface is communicating with the computer it is working at 4 MHz but is sending at 9 6 kHz over the serial connection Whe
25. several issues with FPGAs and radiation Many studies have been done on the radiation effects on FPGAs and proved them to be often sensitive to both Total Ionizing Dose TID and Single Event Upsets SEUs Bonacini et al 2006 These two radiation effects are very different and the problems need to be solved in different ways They differ that much because of their different sources As Tiwari and Tomko 2005 explain TID is caused mainly by composite of gamma rays x rays and other radiation particles Ion radiation low energy alpha particles and neutron radiation are responsible for single event effects SEU is a common type of single event effect and implies that a bit flip has occurred somewhere in the device A bit flip in an FPGA can also be a more serious concern than in a normal case since it can happen in the configuration logic if that is the case the device can be rendered defective until it is reprogrammed In space missions this is a major problem as it can be a huge risk to reprogram a space borne FPGA without the right preparation The SEU problem needs to be mitigated in some way and as Sterpone and Violante 2005 states Triple Module Redundancy TMR is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques This method or a similar one is most commonly used for this purpose In its simplest explanation it implements three flip flops instead of one and then there is always a vo
26. socero ae dene e E ere is a cce am RAA NRA ciel ep atria 2 2 1 2 S VEINS 15 td eh asc dde EA Mao eta mue de seas tata oet US SETT ud o ios uS 4 2 1 3 Post s nthesis SITBU TOU TOTIC ucc ate aaa tel n a a a ea a a Ceci dne ie iria 11 2 1 4 Place amp Rote er rotae odes AR A a ae A eWay ia 12 2 1 5 Post Place amp Route Simulation x iis egens etse tasa tai need add use erT a ne PR IUOS 19 2 2 Implementing te desit ee aciei et otav sa e ders ca E Mn SAN RAN TERS ox ed NT AR 2 2 2 1 Equipment and preparation o oasis po tpe dti depre tabs edat tue de Dave upset tides 21 222 Download Contbsufatlofi 1 ensi to aao etse vale agentem obe diede Saag mac the e ends 22 3 CLOSING REMARMK etai eei Fus ep ea phan eR eiut s EE eh esos eh eae ea pen exea en eise Pede Rec eR cista P RR ERR tess 23 LIST OF FIGURES Hisure2 1 Desigm TOW us cbc ted Mesut lic re lode bedient dle e te esa ei Due ele eet eerte dear reo 1 Figure 2 2 Modelsim execute Macros entente nete teen nos NN ANA snart trennt tritt teet tenente enne a aeaiee 2 Figure 2 3 Modelsim in the wave window sine 3 Figure 2 4 Leonardo Quick Setup ccccccsccscssccssseccesseseesesseesecceecceseescesecseesecaessccaceecessessessecsessecaeeeeceaeeseesecsessecaeseeceaeeseaeeseesecaeeeeeneeers 4 Figure 2 5 Leonardo Technology Option cccccccccccesesseesessssesenseeecesesscesecseesecseseecnceeseesesseesecsevecaesescaaeeseesecseesecaeeeeeeeeseeaeeseeeeneseeeneeets 6 Figure 2 6 Leonardo
27. start tb pr My Dacuments My Computer File name Files of type star tb X Macro Files do tcl Figure 2 2 Modelsim execute Macros page 2 of 23 Design Flow Guide for ATAOKEL DK C esa issue 1 revision 0 page 3 of 23 For the test interface design there were no already made macros but to ease the process small macros were created by coping command lines into DO files These macros did usually not include the compilation step since a file path had do be defined which would limit reusability and some of the time savings would be lost As a result the main purpose of the macro at this level was to start simulation add signals to the wave window and run the simulation for a certain time The macros mostly used were at first source and later on start tb Source was a test bench in itself for very small initial tests Every signal was hard coded into the macro which pretty soon became too complicated so a more advanced solution had to be created A VHDL coded test bench was produced and the start tb macro to start the simulation using the test bench In the new test bench whole series of bytes could be defined and sent which allowed for a much easier testing 1 isix amp gm ser73ema sa Profile Details EET aj Design unit Design unit type M numeric std numeric std Package Name Under t
28. test runs but with the more advanced designs macros were used to speed up the process The macros automated much of the work associated with performing a new test run With the SpaceWire node design from University of Dundee macros for various purposes were included Minor changes were made to some of these macros for it to work with this software version therefore it is recommend to use these modified macros when working with the SpaceWire node yj ModelSim SE PLUS 6 1b File Edit View Format Compile Simulate Add Tools Window Help C SystemDesi C SystemDesir C SystemDesir C tests miniua MODEL TEC MODEL TEC MODEL TEC MODEL TEC MODEL TEC userd KAL MODEL TEC 3 MODEL TEC work Library C tests miniua Desktop HE clkunit Entity C tests miniua GE miniuart Entity C tests miniua e E ram data Entity C tests miniua E ram reslut Entity C tests miniua E run test ctrl Entity C tests miniua J E rxunit Entity C tests miniua wr E tnit Entity C tests miniua e uart_control Entity C tests miniua iP uart def Package C tests miniual EJ uart_wrapper Entity C tests miniua ba HE uart wrapper tb Entity C tests miniua My Network Places Library AT40KAL Library ATS4K Library exemplar Library ieee Library modelsim lib Library std Library std developerskit Library synopsys Library user40KAL unavailable Library verilog Library vital2000 Library Ge Ge E E E E En E DEN le
29. the only issue since the two test designs are synthesised and placed and routed separately it is hard to tell if the designs are exactly the same Because of the problems with putting proper constraints during development procedure this problem could not be verified within this projects timeframe These are the results Test with Unreg Adder Unreg Adder MHz 1st 2nd 3rd 4th 5th 4 0 100 00 10 0 80 00 4 30 0 Failure 60 00 32 0 0 0 0 0 rate 40 00 4 A 33 4 4 4 4 3 20 00 35 4 4 5 is 40 14 14 4 10 30 32 33 35 40 45 45 32 M Table 7 3 Test with Unreg Adder Figure 7 11 Test with Unreg Adder To test if the result could be improved by more demanding constraints a small test was done with a very tough constraint on the system clock In the end this constraint were not met but could push the tool for higher performance But the result did not show any signs of improvement which indicates that the problem is not that easy The results are shown below Unreg Adder Higher Constr Test with Unreg Adder 40 0095 Higher Constraints 35 0095 4 MHz 1st 2nd 3rd 4th 5th eid 4 0 Failure 29 0076 rate 2000 31 0 0 15 0096 32 1 4 1 10 90 5 00 33 2 0 00 Table 7 4 Unreg Adder Higher Constr Figure 7 12 Unreg Adder Higher Constr Evaluation of a European SRAM based FP
30. used Time was spent getting acquainted with the programs mainly through tutorials and reading 5 1 Test Environment All the software oriented tests and developments were made in an office environment on a PC The computer was running Windows XP and had a Pentium 4 processor running at 2 80GHz with 1GB of RAM The software used for simulation was Modelsim 6 1b with licence from the Microelectronics section and not the Modelsim provided by System Designer For synthesis and place amp route programs and licences from the development kit were used These programs were Leonardo Spectrum for Atmel version 2002c 37 OEM Atmel from Mentor Graphics and IDS Figaro 7 6 7 patch level 3a2 from ATMEL It is important to point out that System Designer by itself was never used only some of the software that came along with it For the hardware tests TEC EDP s lab was used Access was granted to computer PC9 for configuring the FPGA while a Logic Analyser and Pattern Generator were also made available PC9 was using Windows XP and had a 1 70 GHz processor and 512 MB of RAM The Logic Analyser was an Agilent Technologies 1681 AD while the Pattern Generator was the pattern generator part of TLA 7012 Logic Analyser portable mainframe from Tektronix As a test board for the FPGA the board in the development kit were used At a very late stage of the project the Logic Analyzer part of TLA 7012 arrived which proved to be useful for some late testing
31. your old one it is time to import your netlist file You have two types of file to choose from and if you are working on an old design you may have an fgd file you want to use but otherwise it is almost always an edf file you want to import It is also possible to see in the Existing Design File field if there is a file of that type in the specified directory and what the name is of the file Since you cannot write in the fields yourself in this window it is important to have done the previous setting correctly to avoid problems For instance it is vital that the edf file that you want to import is in the same folder as you chose for your design directory mi UART wrapper c tests miniuart_ext_clean_2 File Edit View Library Flow Tools Options Window Help ABRROVSE hopen map Parts jcomie S TA A bd pen as Design Design Directory c tests iminiuart_ext_clean_2 gt Design Name Files of Type E VART wrapper amp j i Tools Flow Configuration m Exemplar mTI AT40KAL J New Design Existing Design File e UART_wrapper edt Figure 2 16 IDS Import EDIF Netlist When you clicked OK and started the design IDS will read the imported file and if there are automatically generated macros in the design it will start up the macro generator The window that appears has all the settings prepared by the information from page 13 of 23 QC Design Flow Guide for ATAOKEL DK issue
32. 2 Test PEroGOuMY e scm d oe ott tete e s ca 24 ee RESULTS sisse es E Mein e MM mers rent TED ESTO ei dent 27 7 3 1 Test with test interface ses 27 7 3 2 Test without test interface ss 30 8 CONCLUSIONS on sn epen eee nent e ovens eae aen koe de o nea gae nee ete der sance tee 31 9 DISCUSSION AND FOLLOW UP eee eee eren eese enne eee enne etta tn esee ease esee enses ner 32 10 REFERENCES s v evevssosesccsiseoss esssss sensecerseoseesiinesssveseecsossovsererseosessssivesssrersbsiisesere 33 APPENDIX I User Guide for the Test Interface APPENDIX II Design Flow Guide Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page x of x LIST OF FIGURES Figure 3 1 FPGA Structure uiis Mantente das talents 2 PUP CD PMR ads ea EU dtu e ecu M UU ne er 3 Figure4 I Test Setup tat uaa aeu tet M RE eheu Gage edu seu sM eMe 8 Fig re4 2 Desien FLOW eis scl Pach eas nt ad tos t adeo quas NU dE ra se 9 Figure 5 1 Test Signals with a counter ss 12 Figure 6 1 Loopback Tels ce oft ee cdi e EN ER s mee end 15 Figure 7 1 Fest ANICNI ACE vm si cav oa t ei OP do re a b D NOR erts 18 Figure 7 2 mini UART iai dee tid cc eo E CR Ee ERR XII aetna 18 Figure 7 3 CEU A een cpt aan eq tense qe ena Ael m Re dia ood 19 Fig re TEA TOOL MIT acres ote cu e MU M e CL LE na 19 Fiure 1 3 DX A eee ust a ee ies e get nn e s 20 Figure 7 6 UART GOBFOL i etri l a ber da a RI plaga 21 Figure 7 7 Configuration Byte
33. 2007 138 CIV MASTER S THESIS Evaluation of European SRAM based FPGA Using the ESA VHDL IP Core Library HAKAN HELZENIUS MASTER OF SCIENCE PROGRAMME in Space Engineering Lulea Uni usb mpi Departmen ie cience Kiruna UNIVERSITY OF TECHNOLOGY 2007 138 CIV ISSN 1402 1617 ISRN LTU EX 07 138 SE Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library Hakan Helzenius Master of Science Programme in Space Engineering Department of Space Science Lulea University of Technology Gavle March 2007 Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page ii of x Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page iii of x ABSTRACT AT40KEL DK is a design kit from ATMEL including the Rad Hard SRAM based reprogrammable FPGA AT40KEL040 The use of reprogrammable FPGAs in space is fairly limited since they are often sensitive to radiation Today only a few reprogrammable FPGAs have flown on real space missions but in the near future this technology can cut down on development time and open up for new applications in space Most of the mentioned technology is at present developed in USA with export restrictions which makes it even more interesting with a European product This Master Thesis has focused on the overall evaluation of AT40KEL DK and all of its content The design kit contains both the evaluation board and the FPGA t
34. 408 3416 Pedroni V A 2004 Circuit design with VHDL ebook Massachusetts Institute of Technology pp 3 ISBN 0 262 16224 5 Pellerin D amp Thibault S 2005 Practical FPGA Programming in C ebook Prentice Hall PTR ISBN 0 13 154318 0 Tiwari A amp Tomko K A 2005 Enhanced Reliability of Finite State Machines in FPGA Through Efficient Fault Detection and Correction IEEE Transactions on Reliability Vol 54 No 3 pp 459 467 Sterpone L amp Violante M 2005 Analysis of the Robustness of the TMR Architecture in SRAM based FPGAs IEEE Transactions on Nuclear Science Vol 52 No 5 pp 1545 1549 Online material and documentation AT40KEL DK Design Kit User Guide 2006 Atmel Corporation Available www atmel com AT40KEL040 datasheet 2006 Atmel Corporation Available www atmel com ECSS E 50 12A 2003 European Cooperation for Space Standardization ECSS Available www ecss nl for a free registration Microelectronic Section s Webpage Synthesizable IP Cores Available from ESA Online Available http microelectronics esa int core corepage html 2007 February 10 SpaceWire Codec VHDL User Manual 2005 University of Dundee Available http microelectronics esa int core ipdoc uodspacewire Space Wire Codec VHDL User Manual pdf 2007 February 11 SpaceWire Link Interface RTL Verification 2005 University of Dundee Available http microelectronics esa int core ipdoc
35. GA using the ESA VHDL IP Core library page 30 of 33 These results make it very interesting to see how an adder with registered output would perform since it shortens the length the signals have to travel If it performs better than the unregistered adder it is possible to get a feeling on how large impact signal travel length has on the performance in this particular case Unfortunately this test run into design issues in the very last stage of the project and had to be abandoned due to the lack of time In addition to these results mentioned above there were also some additional issues found in the software There are essentially two problems and the first one has to do with the enables for the internal RAM When a RAM that was generated in IDS was inserted into the design the enables got inverted which obviously made the design non functional The second issue was with the software s interpretation of the port map in some cases Leonardo s schematics show ports as if they were not connected The post synthesis simulation still works but when the design is loaded into IDS Figaro problems occur and the tool complains about ports not existing The reasons for these two problems were never found but they could be worked around 7 3 2 TEST WITHOUT TEST INTERFACE Testing without the Test Interface brings many benefits since it does not have to adhere to the limitations of the Test Interface itself This would in the end give the most reliable res
36. Most of the equipment that is needed is provided by the development kit but there a few external things that is necessary like a computer and a power supply In the kit you can find a parallel cable to connect the motherboard to a computer and a mother and daughterboard with the FPGA already mounted There is also a CD with the necessary software included in the kit Together with the power supply that is the only things needed for implementing the design but then equipment to examine if the design is working properly is recommended In this project Logic Analysers a Pattern Generator and a UART interface circuit were used The first thing you need to do is to install the CPS tool the software that downloads the data to the FPGA The tool is most probably on your computer already since it is installed together with the other programs on the System Designer CD You also connect the parallel cable to the board and to the computer as well as connect the power supply to the board There are two options when it comes down to power supply one is to feed the board with 3 3V directly to connector J1 and J2 and switch SW3 on the board to external power supply The other option is to feed the board through connector P1 with 9V and have the board switched to internal instead The latter was chosen for this project as it was easier When it comes to power it is also very important to have switch SW2 to 3 3V so that the FPGA does not risk to take any damage
37. Section at the European Space Research and Technology Centre ESTEC one of European Space Agency s key establishments situated in Noordwijk the Netherlands The work has been very interesting and rewarding and I will look back with fond memories on my time at ESTEC I would like to thank the Microelectronics Section and especially my supervisor David Merodio Codinachs for the warm welcome and support Thanks also to the section head Agust n Fern ndez Le n for letting me come and be a guest in their section for these month I would like to thank the Payload Section as well for making their lab and equipment available to me Last but not least thanks also to all new friends that have made this time truly wonderful Hakan Helzenius G vle March 2007 Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page viii of x Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page ix of x TABLE OF CONTENTS 1 INTRODUCTION nn Rene tn Line dei 1 2 GLOSSARY LR TN Tee E ds Ne rt ety cu daa deve vue Oe 6 1 3 BACKGROUND eise eee eso uera ca Nee Pape SUeT eESe een rage Eee Fa e RENE te sodiedsascdeoetasessossaceesesses 2 3 1 FPGA 2 3 1 1 FPGAs and Radiation ji tette e eoe elt eb ett ee iseot edet 3 3 2 MAsipe H 4 3 3 ESA IP3CORES eot M AU e rote oet eb eese ei Pedes ce tuens 5 3 4 SPA GE WIRE 003650 a
38. Speed Optimised X X Table 4 1 Test Plan First of all the memories will be tested because the Test Interface need to use buffers and then it is important to now their limitations The integrated SRAMs are also a special feature that AT40KEL provides and that makes it even more interesting to test But the memories will only be tested by the Test Interface as it would be too complicated to control it directly from the pins The Test Interface will allow for an easier use of larger amount of data as well as providing a better user interface After that other designs will be tested the adder and multiplier designs are chosen because they are so frequently used in almost every design which makes them of great interest The test procedure has been divided into the following steps e Create a test interface that can communicate with a computer and perform test by instructions Test that it works properly e Start testing the internal SRAMs inside the FPGA using the Test Interface Figure 4 1 shows a test setup with the Test Interface FPGA Serial connection Test Interface Figure 4 1 Test Setup e Test the other designs with high priority in the test plan Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 9 of 33 e Test the same designs but without the Test Interface and compare with previous results e Ifthe time allows test the lower priority designs e As an optional test des
39. The baud rate could be changed to a higher speed even if it meant minor changes in the Test Interface design it is not recommended Since there is no handshake in use a higher baud rate increases the risk of transmission errors which would be an unnecessary vulnerability when sending test results There are not any great benefits of a higher transmission rate because of the relatively low amount of data that needs to be sent As can be seen in the picture above two stop bits are used instead of the usual one For short commands it is possible to use only one stop bit but when series longer than a couple of bytes has to be sent two stop bits are recommended to avoid errors Since this means only an insignificant difference in functionality there were not any focus on solving this issue During the tests several files with commands and data series were created These files are kept and can be provide for additional testing The files available right now can be seen in the table below along with a short description User Guide for the Test Interface issue 1 revision 0 page 4 of 7 HEX Test Files Name Description RB Read back input RAMs RUN Run default test RR Read back results 2B Send 2 data bytes 2B RB 2B followed by RB 6B Send 6 data bytes 64B Send 64 data bytes Grey code 64B RB 64B followed by RB 64B RB noGrey 64B no grey code followed by RB 64B RUN RB 64B fol
40. active then the load signal gets asserted IntRx N is an interrupt control flag which is asserted when DRdy from the RxUnit is asserted which in principle means that it gives a pulse every time a byte is received IntTx N is an interrupt control flag and is asserted when the transceiver buffer is empty which makes it a good indicator when it is time to load the next byte There is also some reset functionality in this design 7 2 1 2 UART control UART control consist of mainly two processes one receives the bytes from the UART and keeps track if it is a configuration byte or data byte and one process that takes care of the incoming configuration bytes and sets the device in the right setting The data is obtained from the signal DATA UART IN when INTRX N is active both signals is received from miniUART It has also two additional control inputs one is a manual start taken from an input pin and a stop signal from run test ctrl UART control also receives the system clock SYSCLK for clocking and RESET resets the system Since this is the control segment of the design many control flags are going out from this part There are some addresses and write enables to RAMs a MEM CHECK flag for memory data check READ RESULT flag for reading back the results through the UART and START flag for starting a test via command There is also two control signal sent back to miniUART that is always kept active and it is CS N and RD N More information
41. age 5 of 23 In the Quick setup you first choose technology The figure above shows the right technology AT40K as highlighted At the time there is no special library for AT40KAL or ATAOKEL but it is recommended to check for updates in this area For instance with this technology the synthesis is optimised for a supply of 5V instead of 3 3V Through correspondence with the support they claim this problem is solved by the place amp route tool that optimise the design for 3 3V but at the same time they indicated that it might come a new patch with the 3 3V settings This shows one of the reasons it could be good to be on the look out for a newer patch library After choosing technology it is time to import the input files You do that by clicking on open files It is important to remember that the order of the input files are vital where the highest hierarchy file has to be last in the list while the lowest hierarchy file has to be first Another issue that easily can create mistakes is the working directory which can be set by clicking on the button underneath the open files button or when you start a project The problem is that there is a disturbing delay on when the working directory becomes active It is very common that it is the old working directory that is active when you want to import files so if you are not careful you can import an old version of the file since you still are in the old directory This is also a proble
42. ajor role since the limit now was at 47 MHz which is a little bit higher but the small variation can as well be due to some other cause With such a few samples it is very hard to say if there is a difference RAM Grey code Test with RAM Grey code MHz 1st 2nd 3rd 4th Sth Table 7 2 Test with RAM Grey code Figure 7 10 Test with RAM Grey code After the initial test of the RAMs it was time to change the DUT Instead of having a RAM as DUT an unregistered adder was tested Now data was taken from the two input RAMs and added so the result could be written into the result RAM under the same clock pulse The result from this test was first surprising since better results were expected but after examining the procedure the results are a bit more understandable Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 29 of 33 The design was now functional up to only 32 MHz which is far lower than for the RAMs This can probably be explained by that the signals had to travel further per clock pulse than with the RAMs even though the RAM test included more elements In the adder test the signals had to go from the input RAM through the adder and then be written to the result RAM in one clock pulse While in the RAM test the signal had only to go from one RAM to another in one clock pulse even though it included more transitions But this may not be
43. ammable FPGA developed in Europe by ATMEL This FPGA is radiation harded and is of large interest for ESA and parts of the space industry This report has focused on the overall evaluation of ATAOKEL DK and all of its content The design kit contains both the evaluation board and the FPGA together with the required software The approach has been to use the ESA VHDL IP core library and try to implement one of its designs into the FPGA The IP core chosen was a SpaceWire codec developed by the University of Dundee In addition to the test with the codec the FPGA was also tested with smaller designs to assess additional characteristics like clock speed limitations The report will first give a brief background of subjects touched by the project and then describe the project itself and its objectives It is then possible to read about the preparations before the description of the two major tests are presented in Ch 6 and 7 The report is then to be completed with a conclusion and discussion GLOSSARY DSP Digital Signal Processing LVDS Low Voltage Differential Signaling DUT Device Under Test OTP One Time Programmable ESA European Space Agency RAM Random Access Memory FPGA Field Programmeble Gate Array SEU Single Event Upset FIFO First In First Out SpW SpaceWire HDL Hardware Description Language SRAM Static Random Access Memory IP Intellectual Product TID Total Ionizing Dose ITAR International Traffic in Arms Regulations TMR Triple Modular Redundan
44. aries use ieee std logic 1164 all Entity adder is Port declaration port x y c in in std logic S c ut out std_logic end Architecture behv of adder is Structure and behaviour begin Gate level coding s lt x XOR y XORc in c ut lt x AND y OR x ANDc in OR y ANDc in 3 3 ESA IP cores The Microelectronics section at ESA administrates many different IP cores These have been developed in the scope of ESA activities both as in house developments and as contracting work The complexity range from smaller designs to larger System On Chip devices Microelectronic Section s webpage 2007 The IP cores can also be licensed from ESA with special restrictions more information about the IP cores can be found at the Microelectronic Section s webpage http microelectronics esa int core corepage html 3 4 SpaceWire SpaceWire SpW is a standard for inter satellite communication and is described in the document ECSS E 50 12A issued by European Cooperation for Space Standardization ECSS The SpW technology provide a high speed data link intended to meet the needs for remote sensing instruments and other high demanding space applications SpaceWire is a full duplex bidirectional serial point to point data link It encodes data using two differential signal pairs in each direction That is a total of eight signal wires four in each direction ECSS E 50 12A 2003 A SpW connection range from 2 to 400 Mb s but an updat
45. ase pin I O297 CSI A2 After the test run the system clock was changed back to 4 MHz to allow for the results to be sent back To send back the results the file RR was sent and the results could then be read in the 66 Terminal s receive screen The results were studied manually and to avoid that errors during transmission would corrupt the data the results were received two times from the result RAM and compared There were never under the whole project any errors find during transmission The results were then documented by hand d2esa document title titre du document DOCUMENT DESIGN FLOW GUIDE FOR ATA4OKEL DIC APPENDIX prepared by pr par par Hakan Helzenius reference r ference issue dition 1 revision r vision date of issue date d dition status a Draft Document type yge de document Technical Note Distribution distribution European pace Agency Agence spatiale europ enne ESTEC Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel 31 71 5656565 Fax 31 71 5656040 Design Flow Guide e S a Design Flow Guide for ATAOKEL DK issue I revision 0 page ii of ii TABLE OF CONTENTS 1 INTRODUC TION esr RR RR NN 1 2 GUIDE THROUGH DESIGN FLOW lceseeeeeeeeeeeeeee eee enn nnn n nennen nnn nnn nnns nnn 1 2 1 Preparing the Design for Implementation ss 1 2 1 1 Pre layout Simulation
46. aw Infraw Under _ inf Mem under Mem in M standard standard Package M std logic 1164 std logic 1164 Package M std logic arith std logic arith Package M std logic unsigned std logic unsigned Package M uat det uart def Package m uart wrapper tb uart wrapper tb behv Architecture dut uart wrapper behv Architecture 2d L ine 192 uart wraooer tbibehvl Process L ine 194 iu wave default e line 197 File Edit View Insert Format Tools Window NU AE DECERN RKE uart wrapper tb syscik uart wrapper tb reset uart wrapper tb r d uart wrapper tb start m Transcript uart wrapper tb txd Reading C Modeltech 6 1b tcl vsim pre uart_wrapper_tb esregout 77771000 NL LL OL OL RU i ModelSim SE 6 1b Sep 8 2005 uart wrapper tb tx clk z uart wrapper tb dut sysclk Copyright Mentor Graphics Corporation HV All Rights Reserved uart wrapper tb dut reset 27 THIS WORK CONTAINS TRADE SEC ETE 1177 PROPRIETARY INFORMATION WHIt uat wrapper aaan OF MENTOR GRAPHICS CORPORAT uart wrapper tb dut tid 1 B AND IS SUBJECT TO LICENSE TERI uatt wrapper tb dut csregout 11111000 TOO EE DL LED cd C tests miniuart ext clean 2 uart wrapper tb dut data uart in 00001111 Doo I ll I homot reading C Modeltech_6 1b win32 moc Juart wrapper tb dut int n ModelSim gt do C tests miniuart ext clean uat wrapper tb dut intts n H vsim yolk var wrapper tb uart wrapper Ib dut cs n Loading C Modeltech_6
47. ctory were updated globally This meant that by mistake the old design could easily be synthesised instead of the new design which sometimes could be a difficult error to discover The second problem is that the design is synthesised with a supply voltage of 4 75 V instead of 3 3 V which AT40KEL is using According to the support from ATMEL this issue are taken care of during place and route which is done at 3 3 V but under high demand synthesis it can be beneficial to be aware of this problem The main objective was not to test the design of the SpW node but one issue with the configuration is worth mentioning As noted earlier in the report the setting of SYS DEFAULT have some problems and does not pass the required tests This setting is an unusual configuration of the clock domains and is not originally in the test even if it is not specified in the documentation If it is added to the test errors are generated and the design cannot pass the test This was not further investigated and the problem was instead solved by changing setting Another positive result was that a guide for a simple design flow procedure was developed which contains several advice and guidelines on how to handle the basic processes This guide can be found in appendix II in this report Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 17 of 33 PERFORMANCE TEST 7 1 Additional Preparations Since some of the preparations where th
48. cy LB Logic Block UART Universal Asynchronous Receiver Transmitter LUT Lookup Table VHDL Very High Speed Integrated Circuit HDL Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 2 of 33 BACKGROUND 3 1 FPGA FPGA stand for Field Programmable Gate Array and is an integrated circuit that can be programmed after it is manufactured hence its name Field Programmable There are two different types of FPGAs one that only can be programmed once called One Time Programmable OTP and one that is reprogrammable OTP technology is much more common in space qualified designs because it is in general more robust than the reprogrammable one But as Bonacini et al 2006 writes the in system reprogrammability of FPGAs is of great importance giving extreme flexibility to the application which can be updated in case of changing requirements or failure recovery The issue is the reprogrammable FPGA s sensitivity to radiation which will be discussed more in detail in the next chapter To be programmable a FPGA contains numerous configuration switches that after programming routes the different Logic Blocks LB together Described by Pellerin and Thibault 2005 a typical FPGA contains Logic Blocks that make up the bulk of the device and they are based on Lookup Tables LUT of perhaps four or five binary inputs combined with one or two single bit registers and additional logic elements such as clock enables and mu
49. e the integration of an application like the optional last step of integrating the SpaceWire in a SpaceWire network These features could be external RAMs spike free switches or LVDS outputs Also the FPGA had very clean characteristics without many extra features This can put some limitations on some designs but the FPGA included rad hard internal RAMs which is an important attribute Something that would improve the RAM even further would be two separate clock inputs for the dual port RAMs With only one clock input the RAMs cannot function as a clock domain interface as easily as it would have done otherwise The problem can be worked around but it is convenient to use the RAMs as interfaces It is also worth mentioning that the FPGA always booted correctly There were some cases where errors occurred while loading the design from the computer but these cases were always detected and it was working after a retry Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 32 of 33 DISCUSSION AND FOLLOW UP Since there is few users of this product at this stage the feedback from this project has been useful in ATMELs development of future products in addition to its use within ESA Already today it is known that the next product from ATMEL AT280F will include features asked for in AT40KEL DK There will for example be a better equipped board to mount the FPGA in with external memories among other things The softwar
50. e result could then be analysed usually by manual observation on the screen of the Logic Analyser Many designs were prepared according to the project plan but because of unfortunate events and lack of time not many results were produced see the results section for more information Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 26 of 33 According to the project plan many designs were to be tested but as mentioned above not many designs were tested in the end Mainly two designs were tested and some additional designs were prepared The unregistered adder was to be tested in both test approaches An adder with registered outputs was also designed to be tested in the same way as the unregistered one The settings chosen when these DUTs where generated can be seen below Unregistered Adder Carry In Disabled Carry Out Disabled Register None Signed Overflow Pin No Width 8 Pitch 1 Aspect Ratios 0 00 Macro Name add8 no reg This gave following size and speed described by the generator Logic Size 1 x 8 logic cells Max Speed 101 6 MHz Adder with Registered Outputs Carry In Disabled Carry Out Disabled Register Output Width 8 Pitch 1 Aspect Ratios 0 00 Initialization Reset Macro Name add8 regout Initialization Polarity Low No This gave following size and speed described by the generator Logic Size 1 x 8 logic cells Max Speed 118 3 MHz The RAM design was mainly de
51. e same for the SpaceWire test as for the performance test time could be saved For instance a major part of the reading was already done and most of the lab equipment was already in place One of the extra equipment needed was a signal generator which could go up to 60MHz In the end the signal generator could not provide the frequencies promised so as an emergency solution a pattern generator was used as clock instead 7 2 Execution First of all a good test environment had to be created In an early stage it was decided that to be able to load the Device Under Test DUT with data a test interface would be created internally inside the FPGA This would include a UART for communi cation with a computer a controller to write the data into the RAMs another controller for carrying out the tests and obviously RAMs to store the data 7 2 1 FUNCTIONAL DESCRIPTION OF THE TEST INTERFACE A functional description of the Test Interface is presented here but there is also a User Guide produced for the Test Interface presented as appendix I in this report For more information on how to practically use the Test Interface see the User guide To interconnect all the different parts in the Test Interface a wrapper UART_wrapper was created This was a pure wrapper with at most a couple of and and or gates to connect different signals to the same output in a correct way The parts connected in the wrapper was e miniUART a simple UART from w
52. e vhd files for the generated macros and this time there is no need to do any changes like you needed to do for the post synthesis simulation To do this simulation you need the libraries AT40K and AT40KAL which you used for the synthesis simulation so if you for some reason do not have them compiled already it is a good idea to do that The top hierarchy level may not look exactly the same so you better check that it is compatible with your test bench Hopefully there is not many modifications that needs to be done but it can be good to know that there is also a framework for a test bench generated at the same time the other files are created In this test bench you only have to add the stimuli but that can be a relatively tedious work if there is not a very simple test bench When you have the files and everything ready for simulation there is the possibility to do a simulation without the timings to confirm the functionality however a simulation with the timings are strongly recommended To do a simulation with timings you need to import the sdf file you received from IDS Working in Modelsim you do that either in the command line or when you setup the simulation To do the setup you go to simulate menu and choose start simulation and in the window that appears click on SDF on the tabs at the top x Design VHDL Verilog Libraries Gor Power QE SDF Files i Add SDF Options Multi Source delay Di
53. e will also be updated and the new synthesis tool from Mentor Graphics Precision will replace Leonardo Spectrum as well as there will be an updated version of IDS Figaro The next generation will also be more than four times as big which will allow for more complex designs Most of the internal structure is the same however so there will still not be two clock inputs to the dual port RAMs One important factor is also that this FPGA is based on European technology which means it will not be subject to the ITAR restrictions that the U S government has put on U S exports This is good for the market outside USA as it will be easier to buy these products It is also good for the European market to be able to produce such technology The project had to be stopped in its most interesting phase before most of the results could be produced That means that many results can be produced with relatively little effort from where the projected ended Because of this there is a wish and hope that this work will go on and continue where this project ended 10 Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 33 of 33 REFERENCES Books and papers Balch M 2003 Complete Digital Design ebook McGraw Hill pp 222 ISBN 0 07 143347 3 Bonacini S et al 2006 An SEU Robust Configurable Logic Block for the Implementation of a Radiation Tolerant FPGA JEEE Transactions on Nuclear Science Vol 53 No 6 pp 3
54. ed version with SpaceFiber as working name is currently in development and will be able to reach much higher speeds The standard describes the technology in several different levels physical signal character exchange packet and network level For information on SpW see the standard this can be retrieved for a free registration at ECSS s website www ecss nl Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 6 of 33 3 5 AT40KEL DK AT40KEL DK is a design kit developed by ATMEL to allow designers to evaluate and prototype applications using their rad hard FPGA AT40KEL040 The kit includes a motherboard with a configuration EEPROM a daughterboard with the FPGA already mounted a standard parallel cable to program the FPGA and CD ROMs containing software and documentation AT40KEL DK Design Kit User Guide 2006 AT40KEL040 is a relatively small FPGA with around 40000 logic gates but its rad hard feature together with its reprogrammability and internal SRAMs makes it an interesting device Its development has been centred in Nantes France which makes it a European product This means that it is not ITAR restricted and is easier to buy ITAR is a restriction U S government has but on export of advanced military or space technology Without ITAR the purchaser do not have to state the precise use of the device and ask U S government for permission before it can be bought The FPGA has not yet been flown o
55. eed which can in turn be raised when everything is working satisfactory During this process it is expected that further modification has to be done so this step and the previous one will function as an iterative loop until good results are reached e As an optional last step the whole design will be tested together in a real SpW network if the possibility is given The node will not be working in high speed but if it works in initialisation speed it will be considered a success The second part of this project is more of a traditional testing structure Several small designs have been chosen to be implemented into the device and stressed the results will then be documented and compared In this way different fundamental designs performances can be measured and at the same time a clearer picture is produced around the generated macros The macros will be tested in two different ways one where an internal Test Interface is used and one where the macro is connected directly to the pins and probed The test plan can be seen below and tests within brackets are of lower priority than the others Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 8 of 33 8 bit 16 bit 32 bit Only Registers X ALL Ripple Carry Adder No Registers X IO Registers X X X Multiplier Signed X X X Unsigned X X Signed pipeline X1 X X Memory RAM Dual Port Area Optimised X X
56. elow for a figure of the configuration and a table summarising the equipment UART Converter vi LA Power Board la supply 9v Figure 3 1 Hardware Configuration Equipment used Description Mother amp Daughterboard for the FPGA From ATMEL Power supply for the motherboard 9v UART converter Standard serial cable Male Female Computer PC Table 3 1 Equipment 4 SOFTWARE AND START UP To be able to communicate with the Test Interface the computer need to have access to certain functionalities It needs to have bit control over the signals sent through the serial port This can probably be done by the Hyperterminal in Windows but this project used a freeware called Terminal v1 9b because of its better access to single commands In Terminal there was the possibility to write short sequences in hexadecimal code in the software and then simply push send But there was also the option to prepare sequences in files and import them which is very helpful when data has to be sent The files that were going to be imported to Terminal had to be created in another software able to create hex files for this a different freeware Free Hex Editor was used In Free Hex Editor longer series of data could easily be written and saved in hex format among other format options Below a figure of the Terminal tool is shown as well as a list over the software In the figure it is also possible to see the se
57. et IDS choose for you but then you may not get the pins where you want them To assign pins you go to the Edit menu and select Assign Pin Lock and a new window appears where it is possible to lock signals to pins There is also a possibility to import a pin configuration file so that you always have the same pins for your design The easiest way of creating such a file is to save the previous setting Another good feature is that the pin configuration file is easy to read and work with and even if the file is not a hundred percent correct it still assign the pins that are correct In the case you have made some small changes among the pins you can still use the old pin configuration file and correct the changes afterwards and save it as a new file which will save a lot of work After you have added the part and assigned the pins you also get a graphical view of the device with pins figure 2 19 Design Flow Guide for ATAOKEL DK C a Sa issue 1 revision 0 page 16 of 23 LE C no CsREGOUT 5 csREGOUT SYSCLK RESET M _ CSREGOUT S sep 2 C csREGouT 4 START M D C csREGOUTE RT C CSREGOUTG CTcsREGOUT A C csREGOUT LOGIC RAM A ATAOKELO40KW 1 S Figure 2 19 IDS Part Graphical View The only thing left now in the place amp route process is to compile the design You can do that simply by pushing the compile button but you can also follow the procedure step by step But before
58. gn was reset zeros were loaded into the memories and driven through the design so that all RAMs had zeros at all positions When all the RAMs were cleared a test sequence of data where sent to the first pair of memories This was usually 1 to 32 or 64 in ordinary binary form or in Grey code So far everything has been done in 4 MHz the speed the UART interface was designed to work at Now when the data is ready to go through the DUT the clock speed were changed to the speed that was going to be tested With a new system clock speed the test was started manually by asserting a pin The results were now collected and saved in a RAM waiting to be retrieved The system clock speed was once again set to 4 MHz and the result where received through the UART and displayed on the computer screen The RAMs with the result were read two times after each other to confirm that there were no bitflips when the data was transmitted During this project there were never any bitflips found during UART communication As a temporary solution the Pattern Generator provided the system clock since the Signal Generator could not provide the speeds it was specified for When the Test Interface was not used signals were instead treated with the Pattern Generator and Logic Analyser In this case the procedure was simple first of all a pattern of signals were created in the Pattern Generator and sent through the DUT and then collected at the output pins by the Logic Analyser Th
59. gs that contain many faults could actually be a result of one fault that created a shift through the whole test sequence While other tests with fairly many faults could have several individual faults The highest speed that did not result in any errors was 46 MHz which is reasonable under these circumstances Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 28 of 33 MHz 1st 2nd 3rd 4th 5th 4 0 40 00 4 35 0094 10 0 30 00 40 0 0 Failure 45 0 0 rate 13 00 46 01 0 O O 0 10 00 47 1 1 0 0 1 5 0096 0 00 48 25 9 0 1 26 4 10 40 45 46 47 48 50 50 8 7 MHz Table 7 1 Test with RAM Figure 7 9 Test with RAM It can be seen in the table that the results are irregular and it is far too few samples to define a certain failure rate What the graph does is only to display the data in a more accessible way The picture is not as easy at it seems in the results for instance the first and fifth reading at 48 MHz has a very high failure rate because whole series have been shifted due to an initial error while at other times errors can be spread out individual errors It most be said though that the most common errors were detected in bursts The RAMs was then also tested with grey coded data to avoid racing and see if there is a difference between the results In the end it does not seem like racing play a m
60. he right It is important to check that all chosen setting have been applied and not gone back to default setting which easily can happen The synthesis tool does not only synthesise the design but also provide some other helpful functions like the schematic tool The schematic tool is a way of getting your design visualised as boxes and connections This is a convenient tool for looking for errors after synthesis and see if there has been any changes made especially if the hierarchy is not preserved You can see two different schematics and figure 2 12 displays an example of a Technology schematic The black oval shows where you choose to display a schematic Mentor Graphics LeonardoSpectrum for Atmel UART_wrapper Isp Interface work uart_wrapper behy Page 1 of 1 Fie View Tools Schematic Viewer Window Helo EE ls tala amp m e n DA NE CN EAN Sx Trew Technology Schematic Technology input Constraints Optimize Dua a Click ASIC or FPGA to extend device tree and select a library Click on the selected technology logo to open the vendor website Use all defaults Set advanced technology options under Advanced Settings Press Apply or Li Library to apply settings AIMEL Er Atmel AT40K ATEKO2 ATEK04 ATS4K
61. hich slow clock enable internal or external CFG SLOW CE SEL STD LOGIC 1 External After finalising the setting above work on the transceiver FIFO and the receiver buffer was started No major changes were needed in this part The SpW IP used RAM memories with nine data I O ports while the macro generator in the place amp route tool only could handle a multiple of four ports This problem was easily solved by using only nine ports out of twelve defined A relatively big issue with the FPGA technology was that the internal memory blocks had only one clock input The FIFO and the Receiver Buffer were designed for a read and a write clock and in that way be able to work as an interface between different clock domains This problem had to be worked around somehow it is not impossible but it would have been convenient to use the memory blocks as interfaces After the design modifications the verification test for the node was not longer applicable It might have been possible to adapt the verification test but it would have taken a great deal of time Designing a smaller and simpler test for the basic functionality was deemed quicker The test was only a simple loop back where input and output data were compared at the backside of the node Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 15 of 33 Test bench Loopback SpW Data In Data Out p Figure 6 1 Lo
62. igns created without the Macro Generator can be tested and the results compared with the equivalent design already tested 4 2 1 PROJECT DESIGN FLOW Figure 4 2 shows a flow chart over the design process when a design is implemented into an FPGA This flow was followed with all designs in this project and so became an important structure in the project plan For those that are not familiar with these concepts a short description will follow For more case specific information see appendix II Design Flow Guide VHDL gt SIMULATION Y CONSTRAINTS gt SYNTHESIS pe jr coles y NETLIST CONSTRAINTS SFR PLACE amp ROUTE FREUE E RATE y BITSTREAM CONFIGURE FPGA TEST IMPLEMENTATION Figure 4 2 Design Flow First of all the design is written in a Hardware Description Language HDL in this project it has always been in VHDL The design is then run in a simulation program to do early testing and check the correct functionality After probably a couple of iterations between code writing and simulation a design is ready for synthesis Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 10 of 33 During synthesis the code is transformed into a representation of real electronic parts and on the bottom line logic gates It is in this process most of the major constraints are put on the design the most notable is clock speed and input output delays During this process it is not
63. igure 2 21 IDS Compile Flow eto eet ee E a rete rq IER IGI een 17 Figure 2 22 IDS Optimize Placement ede o et en do I E eRe aos 17 Figure 2 23 IDS Routing eee tee tren etae bre E EREE eee e Re Er E EREE re iun ede atte eene tene oe ret nee VK a 18 Figure 2 24 Modelsim Import SDF fll2 tee tee ine eee terre etrangers neue eiue NN 19 Figure 2 25 Modelsim Apply the SDF file c cccccsccsssssssssesceseeseesecscescuceecesseeseesecacesccuaescessecsssecaeesecuassseessecessecasseseeesaeeaesesaeeeesnaes 20 Fiure 2 20 CPS ER 22 Design Flow Guide for ATAOKEL DK C a Sa issue I revision 0 page 1 of 23 INTRODUCTION This document is merely a set of experiences collected during the work with the design kit AT40KEL DK from ATMEL As a first approach only a very small design was tested and when it was functional more advanced designs were taken through the design flow This document walks you through the process step by step with inserted comments and reflections There are several ways of implementing a design into the device but in this document not all approaches are accounted for For more information please see the documentation from ATMEL DESIGN FLOW GUIDE This walkthrough is divided into two parts where the first part describes the purely software oriented elements and the second part the work directly related to the hardware 2 1 Preparing the Design for Implementation Included in the development kit is the Syste
64. in RAM In the special version it manages this in another way Instead of receiving the results at the same time as it is written into the DUT RAM it waits until the test has finished and then transfers the test data to the result RAM This is also done in system clock speed which makes it a part of the test In this way both read and write is tested Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 24 of 33 7 2 1 3 3 The send result process Like most other processes in this design this is a synchronous process with an asynchronous reset The process awaits the READ RESULT signal to go active when it is asserted the data in the result RAM is sent back through the UART to the computer This is done with the same principle as when the data in the data in memories are checked through the UART but since it is only one RAM instead of two there is a little bit less logic 7 2 1 3 4 The run ctrl process Run ctrl is a very small process and does not even have a reset since it is not needed The only thing this process control is the RUN signal It receives the START signal and when it gets asserted the process assert RUN and when the STOP signal becomes active the RUN signal is unasserted 7 2 1 4 RAMs There are several RAM in the design and the number can vary depending on which kind of DUT to test At the present time the different designs for the test are not integrated into a larger de
65. in the FPGA and not design a working copy for future projects At first this setting was chosen Bit clock configuration CFG BITCLK CfgBitclk T SYS DEFAULT In this setting only one clock were used the SYS DEFAULT option uses the system clock SYSCLK also in the transceiver This option was chosen out of simplicity since it would avoid any problems caused by the use of multiple clock domains Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 14 of 33 Unfortunately there were problems with the verification of this setting so after some consideration the setting was changed to TXCLK DEFAULT This setting uses a separate clock asynchronous to the system clock for the transceiver This is also a simple setting and it is used as default setting in the verification test After the changes the final settings were Address length for receiver buffer CFG RXBUF ADDRLEN INTEGER 5 52 32 Number of bits used for transmit and slow rate CFG RATE NUMBITS INTEGER 6 Bit clock configuration CFG BITCLK CfgBitclk T TXCLK DEFAULT Set if double data rate should be used CFG DDROUT STD LOGIC 0 Single Data Rate is used Set to one if pipelining is used CFG PIPELINE STD LOGIC 1 Pipelining is used Choose which clock is used to read from read buffer CFG SYNCRDCLK STD LOGIC 1 Sysclk is chosen Set if receiver discards empty packets CFG DISCARD EMPTY PKT STD LOGIC l Yes Set w
66. ing Input File Search Path a mi Add Before Run Flow Read Help E Te De Ty Input Files A VHDL Options Verilog Options A SDF Options A XNF Op Figure 2 6 Leonardo Input Option esa Design Flow Guide for ATAOKEL DK issue 1 revision 0 page 7 of 23 Constraints can be one of the major functionality differences between the quick setup and the advanced setup since there is many additional option available here If you look at some of the sub options on the bottom tabs there are a lot of useful alternatives like input and output delays to choose from Unfortunately there was no time in this project to optimise the design by using more demanding constraints For more information please see the Leonardo Spectrum documentation Technology Input Constraints optimize Output between each The clock reference time is zero Specify clock frequency clock cycle and global path constraints for the entire design The smallest design for a given frequency is then created All paths between ports and registers are constrained to one clock period You can customize delays between ports and registers by specifying a Maximum Delay Speciy Clock Frequency A MHz Specify Clock Period 250 ns C Specify Maximum Delay Between all 250 Input Ports to Registers Mises Registers to Registers 250 Registers to Output Ports Inputs to Outputs ns 125 Run Flow
67. lable in the computer it is time to start testing the design Test commands for reading back from input RAMs run test and read back result Try also to reset the memories by filling the RAMs with zeros and drive it through the test sequence When all of this is working and the RAMs are reset a set of test data can be written to the input memories If the test is going to be run at another speed than 4 MHz the system clock speed is changed to the appropriate frequency After that start is activated manually by asserting a pin and after waiting a couple of seconds the clock speed is changed back to 4 MHz The result can then be read back through the UART and analysed An example below goes through the whole testing procedure step by step Example Test of an Unregistered Adder After the design is prepared and loaded into the FPGA it is time to set up the test The UART converter is checked so that it is connected correctly In this case the receiver input of the Test Interface is at pin I O298 A3 and its transceiver output is at pin I O292 The converter is also connected to ground and power supply through pins on the board In addition to that it is connected to computer by an ordinary serial cable The power supply of the board is turned on and if the computer is off it is turned on as well e S a User Guide for the Test Interface issue revision 0 page 7 of 7 The program Terminal v1 9b is started and if the already prepared data
68. lowed by RUN and then RB 64B RUN RR 64B followed by RUN and then RR NULL 64B Send 64 nulls to reset the RAMs NULL 64B RB NULL 64B followed by RB NULL 64B RUN RR Table 4 2 Test Files NULL 64B followed by RUN and then RR 5 COMMUNICATION PROTOCOL The protocol used with the Test Interface was created as an ad hoc solution for this purpose Originally it was created for many more features but in the end only a few were realised The main idea behind the protocol was to have something simple to transfer data and commands The approach chosen was to start with a configuration byte which stated how much data was going to be sent and when that amount of data was received the Test Interface was once again waiting for a configuration byte This way of working mainly put the work load on the FPGA decoder side while having a human interface on the other The first byte was divided into two major parts see figure below Configuration I MSB Control Section cs Byte LSB Data Length DL Figure 5 1 Configuration Byte The Data Length part of the configuration byte defines how many data bytes there are to expect after this byte The other section of the byte is called the Control Section and it decides which test to run But if the DL part is set to zero 0000 the design goes into Config Mode instead and then CS is interpreted as a different set of commands The chart below shows which functions we
69. ltiplexers These Logic Blocks and LUTS look differently depending on the technology used different companies use different technologies but it usually also differ between product series within a company These Logic Blocks are then connected through a grid surrounding them which also connect with the I O pins at the edges of the chip See figure 3 1 Figure 3 1 FPGA structure Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 3 of 33 Many FPGAs provide internal SRAMs located between the Logic Blocks to greatly improve functionality This feature opens up to new possibilities although it also brings about another trait that is usually sensitive to radiation But despite that the use of SRAM based FPGA is growing in space based applications because of low application development cost short time to market and the reprogramming flexibility that they offer as Tiwari and Tomko 2005 describes The need is recognised and today there are FPGAs with radiation tolerant SRAM designs Other FPGAs also include additional internal blocks to increase the performance in different applications like internal DLLs PLLs multipliers or even more advanced DSP block DSP Slices hard macro processors PowerPCs high speed serial links etc But these bring about even more radiation issues to overcome 3 1 1 FPGAS AND RADIATION As have been mentioned in the previous chapter there are
70. lyser during test without the Test Interface When the Test Interface was in use all communication was done through the UART The Pattern Generator was connected to the input of the DUT but since the different DUTS did not have the exact same pin configuration small changes had to be done between tests These changes were unavoidable but they were kept to a minimum to reduce extra work The same problem applies for the output pins that are connected to the Logic Analyser A feature in the software were helpful here it made it possible to import an incomplete pin connection scheme which could then easily be updated It is possible to read more about this in the appendix II Design Flow Guide The software used to communicate through the UART was Terminal v1 9b a freeware The commands received by the Test Interface were in binary code but the information sent by Terminal was described in hexadecimal so a simple conversion has to be made Terminal could also send files of data so the practice used was to prepare files with commands and data to import These files were written in the software Free Hex Editor which easily could prepare hexadecimal data files The data received by Terminal could be in binary but as the familiarity with the hex commands was better than the binary commands hex was preferred When everything was set the first thing done was to reset and clear the design The reset does not clear the memories so when the desi
71. m Designer 3 0 This software is mainly made for the AT94 series and cannot be used for the AT40KEL FPGA alone System Designer lacks the right libraries to work with AT40KEL the programs included in System Designer must instead be used standalone The software included are Modelsim Leonardo Spectrum and IDS Figaro The design flow that is described below is illustrated in figure 2 1 for a better understanding The process behind most of the boxes in the figure will be described in the following chapters VHDL P SIMULATION Y CONSTRAINTS gt SYNTHESIS POSTSYNTHESIS Y NETLIST CONSTRAINTS 3 gt PLACE amp ROUTE t p POST ELACE B ROUTE y BITSTREAM CONFIGURE FPGA TEST IMPLEMENTATION Figure 2 1 Design Flow esa Design Flow Guide for ATAOKEL DK issue I revision 0 2 1 1 PRE LAYOUT SIMULATION First of all a simulation of the code must be done this can be very easy for a simple design but more complicated for larger designs In this case Modelsim was used but not the Modelsim provided from System Designer 3 0 instead a full license for the windows based Modelsim SE 6 1b was used In the pre layout simulation the design is tested usually with a test bench that send test signals to the design while the result is observed even though it is possible to force signals into the design without a test bench For the simple designs the work is straight forward and there may not be a need for many
72. m when you start a new project so be always careful so that you import the right files A simple constraint can be set here and that 1s the speed of the system clock It is only to put in the required clock speed in MHz in the empty box If your design has high demands on clock speed you probably also need more advanced constraints but it is also good to put the constraint a bit higher since the design most probably will lose in performance during place and route This loss can be significant when you are working with an FPGA and it was not uncommon to go from a speed of around 30 MHz in synthesis to around 10MHz in place and route There is also the option on how high the level of optimisation should be The highest level was almost always used and the lower level was only used for testing and error solving There were never any significant differences that could be seen between the levels though a closer examination was never done In the output file option a name and place for the output file can be chosen The option is preset to an edf file with the same name as the highest hierarchy input file This file can later on be exported to the place amp route tool To have more option for the output file was one of the major reasons why the advanced options were used in the later design process As a last thing it is simply to push the run flow button and read the result in the window to the left of the setup window In the advanced setup you g
73. mia eck seated e e e ette orto Beaks 5 3 5 ATAOKBEZDK nte mte e emails 6 4 PROJECT DESCRIPTION eee orto eo eost e enar ee eaaet ea ee bae a e erro ra eee eE s a repa euo 6 4 1 OBJECTIVES in preset te ope eren inedia 6 4 2 PROJEGT PEAN v ce cte ce teo recette re ore WE E Ree D Re eee TEE ead de 7 4 2 1 Project Design Flow eene entrent 9 4 3 DEVIATIONS DURING EXECUTION sisi 10 5 PREPARATION Ic 11 5 1 TEST ENVIRONMENT cccceessssecececeesesececececsesessececececseneseaeeeesesenenseaeeeeeesenensaaeees 11 5 2 TESTING A SMALL DESIGN eee enne nr er rr seen nennen nnns 12 6 THE SPACEWIRE CODEC eseesseseessecesssccssocecssoceessecssssecssoceesseceessecessoeessoceessee 13 6 1 ADDITIONAL PREPARATIONS ssccccccccsessssscececececsenssaececececsenseaeceeeeeesenssaeeeeeesesenees 13 6 2 EXECUTION aaa Bice Sota a a a a a Be e e a Maire 13 6 3 RESULTS se EE EEE EE EE E E E EE E E EEE 15 7 PERFORMANCE TESTi ecssv ssvigsssedessssesbsv0ssssy vsssvisbsdasssrsvsssvibssdedssssvsssvissssedssasvess 17 7 1 ADDITIONAL PREPARATIONS sossorsorerersrserreressrrserrerererserrrreresrrrrrr enes rrrerr rr er rese cesse 17 7 2 BXECULPION A Rte nine rtt nt em rh tao nter tet 17 7 2 1 Functional description of the test interface sss 17 1352 lh VART re i n P t o ac De e OI ES SEE 18 7 2 1 UART control we 20 42 1 3 TU t st Ctrl oi eee 4522 dod MRAM Se cote cere te it as haut tte ho Rei ae ne Mas Ee 24 7 2
74. n a real space mission but its use is growing and it is likely that it will be flown relatively soon For the moment Kongsberg Defence amp Aerospace in Norway is working on designs that make use of this FPGA There is also a new generation of this device in development that is larger but built on the same structure PROJECT DESCRIPTION 4 1 Objectives The main objective of this project is to make a general assessment of the design kit AT40KEL DK from ATMEL and the included FPGA AT40KEL040 It is not only the hardware that is important to evaluate it is also necessary to test the effectiveness and user friendliness of the belonging software as well As a first stage the FPGA will be tested by implementing a SpaceWire codec from University of Dundee which will raise the level of experience with the kit and in that way simplify further testing Problems that might have been overlooked otherwise will emerge before the final testing plan is made for the additional tests The goal is not to have a fully operational SpW node working at high speed but to have basic functionality at low speed Different generated macros will also be created and stressed in several ways This will both examine some of the specific technologies and test the macro generator software The results are a good indicator of the performance and functionality of the design kit as well A comparison can then also be made between identical functionalities not created by the mac
75. n everything is prepared for a test the UART is not needed anymore and the system speed can be changed At other clock speeds than 4 MHz the few commands necessary are operated manually instead of from the computer After the test when it is time to retrieve results the system clock is set back to 4 MHz and the results are sent to the computer This procedure is done to be able to stress the clock speed over the DUT to its limits while the UART only works at 4 MHz As can be understood from above the Test Interface can be divided into two main parts the interface towards the computer and the external environment and the part for testing The overall design is described in the picture below Start m TE RAM 8 RxD i 32 id r 8 i 8 Byte kk 4 4 H DR miniUART gt Run test DUT lt H 8 RAM 32 t gt 8 1 Byte AB P gt RAM 32 8 Bytes ESS Test Interface Figure 2 1 Test Interface e S a User Guide for the Test Interface issue revision 0 page 2 of 7 3 PHYSICAL LAYER The design itself does not really contain a physical layer except the FPGA it is loaded into but there is a need for some additional equipment to be able to perform a test Apart from the FPGA and the evaluation board it is mounted on a computer a serial cable and a UART converter is needed The UART converter adapts the board s 3 3V CMOS signals to the standard serial connector signals See b
76. n how to write the data to the memories the default setting is that the first half of the data is written to RAM 1 and then the other half to RAM 2 but there is also the possibility to write the same data to both RAMs It is then of course important not to send to much data to the memories since only half the amount of data is needed Z 2 1 22 The controller process This process has also an asynchronous reset but is otherwise synchronous It awaits the CON F control flag from the data in process which signals that it is time to read in a configuration byte If the data length DL part of the byte is 0000 then it is in configuration mode and indicates that the control section CS is giving a command instead of deciding which test to run Since no data is expected after this command the next byte received must also be a configuration byte Configuration Byte MSB LSB Control Section CS Data Length DL Figure 7 7 Configuration Byte Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 22 of 33 Otherwise the DL section is usually for deciding how many data byte there will follow and CS section which test to run In the current design the CS section is not that important when data is loaded and is only important when the run test command is sent The CS section is however sent to the run test ctrl part to inform which test to run 7 2 1 3 run test ctrl This part consists of four
77. name are exactly the same which gives the possibility of reuse So a recommendation is to keep track of all your already changed macros and you can save plenty of time in the end There is also the possibility to write a script that will do the name change and other modifications but no such script was created during this project Now all the files should be ready and you only have to add the AT40K and AT40KAL libraries to Modelsim and compile the files and simulate esa 2 1 4 PLACE amp ROUTE To do the place amp route you need the netlist edf file from the synthesis tool and how you retrieve it is more closely described in the synthesis chapter This is a process involving several steps and in many of them changes can be made by hand to further optimise the final result For this you need a very deep understanding of the tool and the design so in this project there was no time to reach that level and instead the software s optimisation function was trusted Below you will get a description on how you take a design through the process Design Flow Guide for ATAOKEL DK issue revision 0 page 12 of 23 To open the design and import the netlist for the first time you do the following you push the open button and choose design in the window that pop up Figaro UART_wrapper c tests miniuart_ext_clean_2 File Edit View Library Flow Tools Options Window Help ABRBOVSE p krans compile 5 Epu RE
78. o load the design into the FPGA The place amp route tool gives a bitstream file as a result when it finish This file is then sent to the FPGA by special software and the FPGA should then be operational Even if it is likely the design is working it is important to test that everything is functional 4 3 Deviations during Execution Unfortunately the timeframe of the project did not allow for the whole project plan to be carried out In the end the SpaceWire codec never got as far as being implemented into FPGA and the performance tests did not produce as many results as hoped But interesting results were acquired and plenty of feedback about the overall assessment could be reported Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 11 of 33 PREPARATION To begin with all equipment that could be of use in the lab was tested If something important was not available or not working the problem was either solved by lending or ordering equipment It was then verified that the Development Kit contained all of its parts The board was powered up to see that it did not fail to do so The software belonging to the Development Kit System Designer 3 0 was installed at the working station The attached patches were also added Modelsim and other useful software were installed as well The documentation for the FPGA and its development kit must be read and understood along with documentation for many of the software
79. o through almost the same steps as for quick setup but instead of having only a small portion of a window the option get at least a window for their own In most of the cases the option has several windows with different sub options The options that have their own window are Technology Input Constraints Optimize and Output Design Flow Guide for ATAOKEL DK C a Sa issue 1 revision 0 page 6 of 23 Technology is chosen in the same way as in the quick setup and there are not many other options As you see in the bottom of the window it is also more alternatives than in the first window but neither of the other options were used in the Technology option Technology Jinput Constraints Optimize Output El Atmel AT40K ATEKO2 ATEKO4 ATS4K Run Flow Apply Help Technology Settings Advanced Settings 7 Figure 2 5 Leonardo Technology Option Input is the second of the options with its own window Also in this case only the basic functionality was used Since only VHD files were used as inputs many of the sub option were not applicable You can set the working directory and import files but in addition to that there is also the option to choose encoding style for your state machines for example Technology Input Constraints Optimize Output UAR T_control vhd UART_wrapper vhd Encoding Style C Binay Onehot Twohot C Random Gray Auto IV Resource Shar
80. of the RAM is stated in an older version which will limit the memory to a clock speed of around 55 6 MHz The overall maximum internal clock speed achievable for the FPGA is 60 MHz according to the data sheet which puts the RAMs slightly lower By having a RAM as DUT a maximum speed can be tested this can then be used in the following tests If the DUT is changed to something else and it breaks down below the limit achieved with the RAMs it can be assumed it is the DUT breaking down But if the test instead breaks down at the limit or above it can be assumed that it is probably the Test Interface that gives up The RAM was tested a little bit differently than other tests First of all only one of the input memories were used and at the first clock pulse the data was read from the input RAM to the DUT RAM On the second pulse the data from the DUT RAM were written to the result RAM Instead of only excluding the DUT and read from the input RAM to the result RAM directly this extra RAM was included to add some additional read and write steps which would make it easier for errors to manifest when the test was run on its limits As mention earlier the test does not include many samples since all of them have to be checked by hand When no errors were detected on 5 x 32 bytes the design was considered to work well enough In the following diagram the number of faults at each frequency can be seen This gives merely a simplistic view since readin
81. ogether with the required software The approach has been to use the ESA VHDL IP core library and try to implement one of its designs into the FPGA The IP core chosen was a SpaceWire codec developed by the University of Dundee In addition to the test with the codec the FPGA was also tested with smaller designs to assess additional characteristics like clock speed limitations The timeframe of the project was rather limiting and there was only time for a few test results Instead the project focused on its main objective a general assessment of the whole design kit The experiences of both the software and the hardware were documented and given as feedback to ATMEL as well as laying the foundation for further testing by ESA Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page iv of x Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page v of x SAMMANFATTNING AT40KEL DK r en utvecklingssats fran ATMEL vilket inkluderar den str lnings h rdade SRAM baserade omprogrammerbara FPGA n AT40KEL040 Anv ndandet av omprogrammerbara FPGA er i rymden r relativt begr nsat eftersom de ofta ar k nsliga f r str lning Idag s har endast n gra f omprogrammerbara FPGA er anv nts i rymden men inom en snar framtid kan denna teknologi b de sk ra ned p utvecklingskostnader samt ppna upp f r nya anv ndningsomr den i rymden N stan all den involverade teknologin r i dag u
82. opback Test A way of comparing the data in with the data out automatically as well as a more advanced test bench were planed but were postponed because of more important task at hand at the time The design worked in pre synthesis simulation but after synthesis it was very hard to verify the design because a convenient way to do this simulation was never found Integrated software generated macros had to have there code modified by hand to be compatible In this case it was certain that the design did not work since it encountered problems in the place amp route Configuration signals in the SpW Ip core could not be handled correctly by the synthesis tool or at least the place and route tool could not understand the synthesis tool at all time This was not expected since the IP core was synthesised by the same tool Leonardo Spectrum during development 6 3 Results The hopes of having a SpaceWire node working in the FPGA were never fulfilled and therefore no test results from a working version in the lab can be showed But what is more important is that the experiences of the process can be presented The main goal of the project was to test the FPGA and the software belonging to it This objective is accomplished thanks to the extensive work put into solving the numerous issues Most if the issues were solved especially in collaboration with a fast and helpful support service provided by ATMEL The following text describes problems
83. re planned from the beginning and which were realised in the end Cesa User Guide for the Test Interface issue revision 0 page 5 of 7 Data Length DL Command Description Functional Comments 0000 Enter Config Mode Yes CS from same byte counts as in Config Mode 0001 1 byte Yes Not recommended without Input Mem Config 0010 2 bytes Yes 0011 4 bytes Yes 0100 6 bytes Yes 0101 8 bytes Yes 0110 10 bytes Yes 0111 16 bytes Yes 1000 24 bytes Yes 1001 32 bytes Yes 1010 64 bytes Yes 1111 Start Test Yes Works only at 4 MHz test speed Table 5 1 Data Length commands Control Section CS in normal mode Command Description Functional Comments 0000 time 8 bits Yes Runs one test with 8 bits width 0001 32 times 8 bits Yes Default Runs 32 tests with 8 bits width 0010 time 16 bits No Runs default instead 0011 time 32 bits No Runs default instead 0100 32 times 16 bits No Runs default instead 0101 Continuous 8 bits No Runs default instead 0110 Continuous 16 bits No Runs default instead Table 5 2 Control Section commands in normal mode Control Section CS in config mode Command Description Functional Comments 0000 Idle State Yes 0001 Check Input Yes Reads back from the input RAMs 0010 Input Mem Config Yes Writes the same data to both input RAMS 0011 Read Results Yes Reads back the results 0101 Stop No Stops a
84. ro generator Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 7 of 33 4 2 Project Plan Since the objectives are split up into two major goals the project plan and even the whole project is divided into two parts In the first part the goal is to implement a SpW node into the FPGA and to reach this goal the process has been broken up into several steps e The first step is to get a general knowledge of the hardware and software provided by ATMEL mainly through reading documentation and following tutorials e After understanding the essential elements in the implementation process it is important to try the whole design flow with a very simple design This will give an early indication of possible problems in any of the design stages so that they can be mitigated before too much work already has been completed e Before the SpW node can be implemented the SpW technology and IP core must be understood This will be done by reading the SpW standard and the documentation of the IP core Test simulation will also help to get a better understanding e The next step is to make the required modifications of the IP core so that it is compatible with the AT40KEL specific technology With the adjustments it should be possible to take the design through both synthesis and place amp route e The design is then downloaded into the FPGA and tested on the prototyping board At first it will be tested in very low sp
85. sable SDF warnings Reduce SDF errors to wamings xi Dk Cancel Figure 2 24 Modelsim Import SDF file Design Flow Guide for ATAOKEL DK C a Sa issue revision 0 page 20 of 23 In this window you can push add and you will get a new window where you can choose which sdf file to import and to which region you want to apply it You can browse for the sdf file but for specifying the region you need to write which entity to look in and which instantiation to apply it on If you are using the generated test bench named post test bench and want to apply the sdf file on instance inst uart wrapper you simply write it like this post test bench inst uart wrapper aol x SDF File Browse r Apply to Region Delay w l Ok Cancel Figure 2 25 Modelsim Apply the SDF file After all the sdf files have been applied usally one the only thing left is to run the simulation as you normally do In this project the command line was copied into a do file start tb pr together with some other settings to do the preparation work more straight forward Design Flow Guide for ATAOKEL DK C esa issue revision 0 page 21 of 23 2 2 Implementing the design You can divide the implementation into two parts the first part is to prepare the equipment and the settings and the second part is to load the design into the FPGA itself 2 2 1 EQUIPMENT AND PREPARATION
86. sign instead there is a special device for every test This is most evident when it comes to RAM since it is a feature that is changed the most depending on the test is 8 bits 16 bits or if the DUT produce results that require a larger result collecting RAM In the basic design there are two memories at the input receiving the data for running the test data in and one RAM to acquire the data from the DUT during or after test 7 2 2 TEST PROCEDURE Much of the previous set up could be used in this case The computer was already connected to the board through a parallel cable and the software to download the design was already installed The logic analyser and pattern generator was also available but needed to be connected to the right pins on the board In addition to a small circuit to convert the UART signals to 3 3 V there was also a need to install software in the computer to communicate through the UART with the test interface The UART converter circuit was connected through an ordinary serial cable to COM2 port on the computer in one end In the other end the circuit was connected to the board with the pins for the receiver and transceiver as well as the ground and supply The connectors were not there on the ordered product and had to be soldered there on its arrival Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 25 of 33 Signals were only sent by the Pattern Generator and received by a Logic Ana
87. signed to be tested with the Test Interface but its outputs were also tested manually in a test resembling the test above For the test without the Test Interface additional designs were also prepared and that was signed and unsigned multipliers as well as a pipelined multiplier Unfortunately these were never tested Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 27 of 33 7 3 Results As described in Test Procedure two different kinds of test were made on the device The results from these two tests are described under its own headline 7 3 1 TEST WITH TEST INTERFACE The results are only acting as a guideline on what can be achieved There was no time in this project to optimise the Test Interface so that the DUTs could be pushed to the limit during test The tests have been done on small number of samples which also limits the precision of the test With this in mind the test shows that a design can be loaded to the FPGA in a successful way and the design can also communicate through a UART in a satisfactory level The first test preformed was to test the internal RAMs Since the Test Interface included RAMs and they were deemed to be the bottleneck when it comes to system clock speed in the test feature part of the interface it was important to test them first The data sheet AT40KEL040 2006 states that the access time for the internal RAM is 18 ns two different values for the maximum speed
88. ss Except the VHDL Fuctional Description all these documents can be found on internet the standard can be found on ECSS website while all the others can be found on the Microelectronic Section s website See the references for more information 6 2 Execution At first the SpaceWire IP core had to be modified to suit the ATMEL technology The modifications can be divided into to levels of adjustments one that uses the configuration option already made available by the IP core and one where code is added or even changed In the end no code in the IP itself was modified and all customisation were done in wrappers and in added parts The IP did not include a transceiver FIFO and receiver buffer and instead gave an example on code of how it could look like This example was important for verification since it was used during the verification test that was delivered together with the IP core This example code was not officially a part of the IP but worked as a groundwork on which the modifications were done These were also the areas most sensitive to changes in technology and could in many cases expect modifications The configuration settings were the first to be adjusted because these would be the platform all other changes had to be done By choosing only one configuration and excluding the others from modification limits the options in the future but this was deemed reasonable since this project only was supposed to demonstrate a working SpW node
89. st cases this is not a problem since the contention score usually drops to zero after the routing has been optimised Mini Place Opt Place kni Route kopt Route b t str cb COPS Bs M4 gute info Current route contention score 10 Figaro Writing statistics for device 4 fo eserftswniniuart ext clean 21JART wrapper a sts Initial Route info Finished Initial Route at October 6 2006 at 3 01 42 pm Success Figure 2 23 IDS Routing The last step in the compile process is to create a bit stream It is during this phase that many of the output files are generated where the bst file is the most important The bit stream file bst file is a file which contains the data that is going to be downloaded into the FPGA But there is also many other files created and some of them are to be in the post place amp route simulation which you can read more about in the next chapter One of the more essential files that are created is the sdf file with all the timings for the post place amp route simulation Design Flow Guide for ATAOKEL DK C a Sa issue I revision 0 page 19 of 23 2 1 5 POST PLACE amp ROUTE SIMULATION This simulation is essential since it is a chance to test the design with the final layout and timings If this simulation works it is a good chance that the design is functioning in the device as well To make this simulation work you have to import several files that IDS generated You need th
90. synchronous processes and a small amount of parallel logic It also receives many of the control signals from UART control like MEM CHECK READ RESULT START and SETTING These signals decides if the input data should be sent back and checked if the results should be read back which test to run or if the test should be started Run test ctrl also acquires a signal from the miniUART INTTX N indicating if the UART is sending for the moment or if a new byte can be sent The standard signals SYSCLK and RESET are also received For outputs there are address and enables both for the RAMs with the input data and for the one collecting all the data In the special case when the DUT is a RAM the control for that RAM is also run from this part There is also a STOP signal that is asserted when the test is done and a MEM SEL signal that which specify which RAM to read from during the memory check This part is also responsible for asserting WR_N for miniUART when something is sent back through the UART SYSCLK RESET START MEM CHECK READ RESULT INTTX N SETTING STOP MEM SEL RENA REN 2 WRN pRE_RES_N 5 _yRD_ADDR_RES 5 _ ADDR_DUT_IN RUN TEST CTRL Yr y A MS A Figure 7 8 run_test_ctrl 7 2 1 3 1 The run test process The process begins with an asynchronous reset and is synchronous in all its remaining functionality The synchronous part starts with checking if the in data in the RAMs should be controlled for errors If MEM
91. ting between them That means that if one flip flop gets a bit flip the other two will win the vote and the correct answer will be sent see figure 3 2 FF i FF Figure 3 2 TMR Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 4 of 33 The question is if this method should be applied to every flip flop and how will it be implemented in the best way The area the flip flops occupy will at least be tripled and how is this best designed Today s Radiation Hard FPGAs intended for space applications have already TMR or similar built into the device so that the designer do not have to include it in its design 3 2 VHDL VHDL is a Hardware Description Language HDL and stands for Very High Speed Integrated Circuit HDL As Balch 2003 writes Hardware description languages were developed to ease the implementation of large digital designs by representing logic as Boolean equations as well as through the use of higher level semantic constructs found in mainstream computer programming languages In this way complex logic can be described in an easier way and with today s modern tools implemented in devices like FPGAs There are currently two major HDLs in the world VHDL and Verilog they have about equally many devoted users around the globe VHDL was the original and first hardware description language to be standardized by the Institute of Electrical and Electronics
92. tipliers but there is also another version that is made for RAMs as DUT That version uses the same address and enable signals that are used for reading from the data in memory and in that way creating a control for the DUT RAM In the case of a DUT RAM only the first data in RAM is used The second test setting that can be run is when only the first position in both RAMs is used and in all the other aspects it is the same as the default setting This results in merely one run instead of 32 Both these test are sending a STOP signal when the test is done so that the design is open for new tasks When a test has started only a reset can stop it before it is done this should however never be a problem since the test finish in micro seconds A good benefit of this feature is that it is possible to use a non spike free input for the manual start without getting unreliable results the last spike will always produce a clean test PPS PR S The read DUT data process This is a synchronous process that writes the results from the DUT into a RAM There are two versions of this one default version where the result is read under the same clock cycle as it is fed into the DUT and a special version for when the DUT is a RAM Both versions include an asynchronous reset In the default version it operates in a very straight forward way by using the same addresses and enables for writing into the result RAM as is used for reading from the data
93. tten that is good to know if you want to go back and check manually if the transfer was correct ATMEL AT17 CONFIGURATOR PROGRAMMING SYSTEM iol xl File Calibrate Help Please select Family first for the corresponding Procedure menu Procedure P Partition program and verify from an Atmel file r Files Info One or more Atmel bst files may be generated for Input File c MitmeNwWDRKSATSTKAO test z zl subsequent download sessions The optional checksum can be obtained from the log output of Output File c temp out bst x E each programming session In this version of CPS HEX values are only appended to the BST output Checksum 295553 files which have been pattitioned The output file must be of the form lt file gt bst Options S Family AT40K Cypress COMM Port eri gt Device AT17LV010 4 1M Vv Data Plate Fast h Reset Polarity Low A2 Bit Level Low soseste oT r Console Sum of device bytes 295553 Setting reset polarity to Low Handling Reset Polarity for AT17LV010 device Device data 10979 bytes has been written to file c temp out bst Verifying AT17LV010 contents The Procedure Completed 10979 bytes of 10979 total bytes successfully verified checksum PASS read value 295553 matches expected 295553 U RY Number of Warnings 1 Number of Errors 0 Number of Fatal Errors Normal prog Il Completed CPS on June 7
94. ttings used during test e S a User Guide for the Test Interface issue revision 0 page 3 of 7 Eel FER Baud rate Data bits 5 Parity Stop Bits 5 Handshaking C 600 C 14400 C 57600 C5 none C1 none C 1200 C 19200 C 118200 g odd C RTS CTS C 2400 28800 128000 C7 even C 15 C X N XOFF C 4800 38400 256000 mark C RTS CTS XON XDFF 9600 C 56000 C custom 8 space 2 C RTS on TX Settings Setfont ES on E dim UNE po sl Asciltable E CTS COSR OC Or Receive HEX CLEAR Reset Counter 13 Counter 72 C Sting StartLog Dec IV Hex Vv Bin 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00010100 00 01 03 02 06 07 05 04 OC OD OF OE 04 OB 09 08 18 19 1814 1E 1F 1D 1C 14 15 17 16 12 13 11 10 00010101 30 31 33 32 36 37 35 34 3C 3D 3F 3E 34 3B 39 38 28 29 2B 2A 2E 2F 2D 2C 24 25 27 26 22 23 21 11 00010111 00 00 03 02 06 07 05 04 OC OD OF OE 0A OB 09 08 18 19 18 14 1E 1F 1D 1C 14 15 17 16 12 13 11 10 00010110 00 00 03 02 06 07 05 04 OC OD OF OE 04 OB 09 08 18 13 1B 14 1E 1F 1D 1 14 15 17 16 12 13 11 10 00010010 00010011 00010001 00010000 Transmit CLEAR SendFile CR CR LF DT ERTS gt Send M Transmit Macros Figure 4 1 Terminal v1 9b Software used Description Terminal v1 9b _ To send and receive signals over the COM port Free Hex Editor To prepare files to be sent Table 4 1 Test Sofiware
95. tvecklad i USA med export restriktioner d rf r r det extra intressant med en Europeisk produkt Det h r examensarbetet har fokuserat p att utv rdera helheten av AT40KEL DK med all dess inneh ll Utvecklingssatsen inneh ller b de ett kretskort f r att testa FPGA n samt all mjukvara som beh vs Infallsvinkeln har varit att anv nda ESA s VHDL IP bibliotek och f rs ka att implementera en av dess konstruktioner i FPGA n Fr n biblioteket valdes en SpaceWire codec utvecklad av Universitetet i Dundee Ut ver testet med SpaceWire s var FPGA n ocks testad med mindre konstruktioner f r att utv rdera andra aspekter som t ex den maximala klockhastigheten under varierande omst ndigheter Tiden begr nsade dock projektet kraftigt och det fanns bara tid f r n gra f testresultat Ist llet s fokuserade projektet p dess huvudm l en generell utv rdering av hela utvecklingssatsen Erfarenheterna fr n b de mjukvara och h rdvara var dokumenterade och gavs sedan som feedback till ATMEL men har samtidigt skapat en bra grund f r fortsatt testning av ESA Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page vi of x Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page vii of x PREFACE This thesis is the final report of the Master of Science programme in Space Engineering at Lule University of Technology The work has been carried out in the Micro electronics
96. uestion about how important optimisation is especially for timings This project mainly used relatively simple constraints so for a deeper knowledge in working with constraints please read Leonardo Spectrum documentation The quick setup option was used for the small test design that was used in the beginning but the quick setup could also be used for first time tries with a more advanced design Later on the advanced setup was used but constraint wise more complex constraints than in the quick setup was rarely used The advanced setup was used mainly to make changes on the output file or to keep the hierarchy after synthesis ni esse a oxi Quick setup or Run the entire flow from this one condensed page Specify your source Advanced setup file sL technology and desired frequen en press Run Flow Technology El Atmel ATAO ATEKOZ ATBKO4 ATS4K run test ctrl vhd UART control vhd UART wrapper vhd Open files UA es Working Directory I r Constraints CON L Optimize Effort Fastest High Runtime Effort r Output Output File C tests miniuart ext cle n 2 UART wrapper ed r Place And Route Run Integrated Place and Route re Figure 2 4 Leonardo Quick Setup page 4 of 23 Design Flow Guide for ATAOKEL DK C esa issue revision 0 p
97. ults if only the problem of visual inspection could be solved Since the results would be evaluated manually on the screen of the Logic Analyser it is hard to define the transition from good to bad signals Otherwise it is few aspects to consider when analysing the results compared to the Test Interface which gives a much more complicated picture A more straight forward approach is traded with the lack of automation and long run time which could be provided by a test interface Unfortunately the timeframe did not allow much testing and only a few results were produced In figure 7 13 test signals from a RAM test at 55 MHz can be seen this was also the only test made with satisfying results The reason for this was that the testing had initially some problems and before some of them could be solved the FPGA stopped working The RAM test showed that the output gradually worsened between 50 and 55 MHz and at 55 MHz the functionality were lost for certain There was also a test performed on an adder with registered outputs but the test never presented any reliable result The test phase had then to be abandoned regrettably due to the lack of a working FPGA and the short timeframe DO 1 0000 0100 0000 0110 DO 2 0010 0100 0010 0010 0110 EH CSREGOUT Time Figure 7 13 Test Signals on a RAM at 55 MHz Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 31 of 33 CONCLUSIONS The results from this project are b
98. unusual with new problems arriving which needs to be fixed back at the coding stage These new issues are found during post synthesis simulation Since it is very common with new problems at the first synthesis run it is important to do the post synthesis simulation Without this simulation the problems will not surface until later in the design flow and there is still the need to go back to coding and start over The simulation makes sure that every part has been connected correctly and the design still does what it is intended to do If the simulation is working it is time to import the netlist to the place amp route tool The netlist is a file created by synthesis containing information about the parts included During place amp route the parts defined by synthesis get their placement inside the FPGA and is then routed together Now an exact representation including detailed timing on how the design will be implemented in the FPGA is created even though it is not loaded into the FPGA yet First it is recommended to do a post place amp route simulation to confirm that everything is working properly The post place and route simulation is the last simulation needed if it works then it is likely that the design will work inside the FPGA itself This simulation is more accurate since it is able to use timings during simulation That is possible because signal path length is now known after the routing With a working simulation it is time t
99. uodspacewire Space Wire Link Interface RTL Verification pdf 2007 February 11 d2esa document title titre du document CUMENT UsER GUIDE FOR THE TEST INTERFACE APPEN DIX prepared by pr par par Hakan Helzenius reference r ference issue dition 1 revision r vision date of issue date d dition status a Draft Document type yge de document Technical Note Distribution distribution European pace Agency Agence spatiale europ enne ESTEC Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel 31 71 5656565 Fax 31 71 5656040 User Guide for the Test Interface C e S a User Guide for the Test Interface issue 1 revision 0 page ii of ii TABLE Or CONTENTS 1 INTRODUCTION enam UP tes t tet en 1 2 OVERVIEW Pr M MS 1 3 PHYSICAL LAYER 5c seeks aa o RP Eph ea ERE FERRE FLA UR eB S FR SEP ERZEI T aanecanee tn ane ete emmetat 2 4 SOFTWARE AND START UP aor ar i nr id RD oO re 2 5 COMMUNICATION PROTOCOL sssesssssssssssnssssssnssssnnnssssnnnnnnnn reser nns nn nn nn nn EAR nn RARE aS 4 6 TEST SEQUENCE STEP BY STEP area us na 6 LIST OF FIGURES Fig re DED TONE A CII OCE NRA Nec uates tua Meet E Sea acl MG oe dU ences 1 Figure 3 1 Hardware Confeukdtiolu s eene eoa sehen temone aloe as tta ou vod uet 2 Figure 4 L Terminal v1 eed pU c ite dana At FAN ARS qute edita OR RAO sR tui deoa da Ped ais 3 Figure sl Configuration Byte s aisle phani
100. vier was the compatibility issues found between the synthesis tool Leonardo and the place and route tool IDS Figaro When post synthesis simulation was to be done with a design that included generated macros some conversion had to be made by hand Because the two tools use different ways of writing port names an underscore has to be added or removed this can of course be done by a user created macro but it still involves extra work No such macro was created during this project There were also other observations that indicated misunderstandings between the software even though the real cause is not confirmed What was blocking the process when this part of the project had to be abandoned was the misinterpretation of configuration signals in the SpW node design In the SpW design pre synthesis configuration of the node itself were done by signals and not generics these signals were misinterpreted and could not be placed and routed If the mistake is made in the place and route tool or already in the synthesis tool is hard to tell without a closer investigation Leonardo Spectrum were also providing some other inconveniences the first one has no impact on the end result but the second one can be of more importance under more high demanding circumstances There is a hitch with the working directory function as the project was updated and eventually moved to a new folder the old working directory was still active locally even when the working dire
101. ww opencores org e UART control a control that reads commands and writes data to the RAMs e run test ctrl control memory checks run tests and read back the results e RAMS there are separate RAMs for storing data to test and to collect the results Evaluation of a European SRAM based FPGA using the ESA VHDL IP Core library page 18 of 33 RAM 8 324i 1 ff v 5 Byte b Ctrl Run test DUT RxD lt 330 miniUART lt 8 gt RAM a Byte A8 RAM i 32 4 8 Test Interface Figure 7 1 Test Interface 7 2 1 1 UART The UART was not constructed from scratch but instead was acquired from www opencores org to save time Even though this was a complete functional UART it had to be adapted to fit its purpose better which also made it easier to create a control for it Some of the more noticeable modifications done were changing the reset to active high and removing the tri states which would have become internal otherwise The system clock was also changed from 40 MHz to 4MHz At the time the UART design was acquired from www opencores org no documentation was available so no references can be made Instead a short overview will be presented here based on experience The UART is built up by four parts and a small package One of the four parts was mainly a wrapper but since it also contains a control process it could be seen as a building block
102. y themselves not a satisfactory description of the FPGA and its software But the test of the software that the first part of the project provided in addition to the functioning design in the FPGA that the second part demonstrated it can be said that the main objective have been fulfilled Together these two parts have been able to give useful feedback about the implementation process at the basic level The overall conclusions from this project are divided into three distinct areas which are the Evaluation board the FPGA and the Software Apart from these areas it is also important to mention the support from ATMEL since their quick and helpful answers have been of great importance at several occasions The software was the first area encountered in this project and as can be read in the results it was fairly hard to get a good understanding of the software initially This was mainly due to the problem to know what features were applicable for the Rad Hard version of the FPGA The software also showed signs of other problems like compatibility issues but most of them could be solved or avoided thanks to the help from the support The evaluation board was of a simple design with almost only the FPGA and its configuration and power circuitry mounted This gave a very easy access to all the pins of the FPGA which made probing and testing easier Even if this simple approach made the probing easier a development board with extra features would eas
103. you start compiling the design you have to decide which settings to use The most important decision is to choose if the place amp route should be timing driven or not a strong recommendation is to use timing driven place amp route at least in the later part of the design work If you choose to use timings driven place amp route it is also advisable to define some timings requirements in the Edit menu under timings Another option that is good to keep in mind is that you can choose to auto soften if there are problems to fit the design into the FPGA To change these settings and many more you click on options in the options menu and you will get a window like in figure 2 20 There are so many options here so please refer to the documentation for more guidance ry Options ioj x Topic Design Checker Design Configuration Quality Design Constraints Revert to Defaults Eco Timing driven Export Format 3 Cancel t i Route if Place contention Help M Auto set parameters Mapping r Help MGI Support Equivalent port swap MGL Editor B Part Selection PE Editing Partitioner Auto re route after manual move Synthesis Tool Invocation Atmel 40K Timing Analysis F x Viewlogic Import Allow global clock reset signals Xilinx to use non global resources Iv Allow auto pin swap on locked macros 4 gt el Figure 2 20 IDS Place amp Route Options Design Flow Guide for

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