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1. 2 27 SS JUMPERS JMPRI M2 J3 4 f N LATI 1 Nos PURPOS1 GND GND _JMPR2VJMPROV MI MO lt 11500000000 Olt 000000001 Pg DUO aC 3 30 GND 41 AN Bud 324 n gaz Eg 2 GND 1 417 2 CPLD TLK C DONE CPLD_TDO C DIN 5 CPLD_TD1 C PROG 1 d CPLD TMS C INIT m C8 amp enol 2 84 e 5 5 He Eo Tbe LTD y 167 RN3 RM Tu _ 7 TP3 pF BA 12 C9 GND 9986 12 R5 R6 R7 C25 19 20 n4 04 SS 14 n Vo
2. _ CPLD FPGA JUMPERS JMPRI M2 J3 si __ 2 2 5 PURPOSI GND GND _JMPR2VJMPROV MI MO Tene 23 1 19 1 C 24 gril M GND 7 7 re Y 3 3V GND 4s 1 5 BR 2 GND C_CCLK F ES 1 JIT 3 ce CPLD_TLK C_DONE CPLD_TDO C DIN E CPLD_TD1 C PROG 1 01 R2 CPLD_TMS C_INIT m C8 5 84 2 li y 7x H2 OO O j qp 187 RN3 RNA Sul _ C TP3 pu pe 12 GND naga ab 7 R5 R6 RT 49 9 20 O C25 j S 38 cl d U 12 C24 oe 15 1
3. J25 423 424 12 GND 12 GND 12V GND gt 102 157 3 103 15 AG aJI We 45V 45 104 MBCKO 5V rele 7 404 MBCK2 5V E 7 104 4 517 7 105 33 3 5l 105 3 3V 5 7 105 3 3V 5V 6 106 5 6 406 5V 6 106 _ 8 717 7 GND DCLK6 1 7 GND CCLK4 1 7 GND GND 8 ECLKI GND ad FCLK4 GND 8 7 108 4 3 3V GND 3 3V 7 D GND 3 3 E GND P2N3 m 7 nm GND PIN7T 3 nm GND 1 i nm GND GND 11 7 METTI P2N5 GND 11 METTI PTN73 GND 11 7 Dn P7N51 12 112 PONG PIN70 12 112 PIN72 P7N48 12 112 P7N50 P2Ni 13 113 2 11 1 69 13 113 PIN67 P7N47 13 113 P7N45 2 0 14 7 7 114 P2NX10 PINGS 14 7 114 P1N66 P7N46 14 7 P7N44 P2NX7 15 415 P2NX9 1 63 15 7 415 P1N65 P7N41 15 415 P7N43 P2NX6 16 116 P2NX8 1 62 16 116 P1N64 P7N40 16 116 P7N42 P2NX5 17 7 az P2NX3 PiN61 17 7 P1N59 P7N39 17 7 az P7N37 GND 2217 7 122 P3NX7 GND 2217 7 422 PINST GND 22 7 122 P7N29 P3NX5 24 7 7 124
4. SEE TABLE 2 4 0 044 1 12 5 0 040 X 0 047 DIA REF OVAL REF E 0 062 1 57 DRAIN AREA ZVN 5 0 015 0 38 IN HGT 3 E 0 8 0 20 CONTACT mM e 8 POS 1 2 0 116 2 95 SECTION REF 2X ird ROTATED COUNTERCLOCKWISE 90 g SCALE 10 1 1 ana REF 2x a e 5 0 220 5 59 2x 0 104 2 64 H REF 2X a A Lem R 107 R2 72 R 110 R2 79 A v 2x e 20 052 1 32 H REF EH 1 E PROCESSING CAP v 375 9 52 QUTSIDE PROFILE SHOWN ONLY pue Bg ica ee 3 5 5 N Tope ee 5 060 1 52 E SOLDER TAILS 4 050 1 27 t VIEW 5 58 t I cod Sm usows BERG 8 eon ar doe COPY ELECTRONICS c vso245 TH 03 11 93 lineor _ 005 projection tile MICROPAX 025 SMT 5 16 411 9 9 06 11 93 0020 p RE angles o gt PLUG DOUBLE 1 VOPUE 40280 02 07 94 13 4 9357 incu mm product famiy MICROPAX code X 50646 06 23 95 3 4 93 size A no pond VIEW OPTIONAL HOLD DOWN BOTH ENDS FOR 51287 MRC 10 20 95 chr _ 3 4 93 scale 9 1 294 A 6 0964 005 2451 08 PCB HO
5. P7N 771 SDA m F11 pri SAO D 212 e7N 75 SA1 v31 Figure 5 11 SDRAM U3 Bus Signals Page 2 of 2 The CD ROM has a datasheet of an acceptable 1 Gbyte SDRAM module from Micron The file name is SDF36C64 127x72G B pdf Header Header 118 is connected to the WP Write Protect input of the SDRAM Descriptions EEPROM and to ground A pullup resistor keeps the WP signal high when the header is unconnected adding a jumper between the two pins drives J19 and J18 the signal low The default configuration is no jumper The EEPROM holds data describing the size configuration and timing characteristics of the SDRAM The data is write protected when the WP signal is high There should be little or no reason to want to overwrite the EEPROM data Some SDRAM manufacturers simply connect the WP pin of the EEPROM chip to the power supply of the SDRAM in which case J18 has no effect whatsoever Header J19 is connected to the REGE Register Enable input of the SDRAM and to ground A pullup resistor keeps the REGE signal high when the header is unconnected adding a jumper bewtween the two pins drives the signal low The default configuration is no jumper DN3000k10S User s Manual 5 11 Memories User Notes DCMs for Clock Management on Memories 5 12 On some SDRAMs the REGE input may be used to select Registered or Non Registere
6. 42 4 n 8 _ VERSION 1 2 A 23 622 m e EC BEAC 4 YN NOTTE Mem ue 95288 1 10144BEN0037 F1143823A SZXILINX CEA ur Uns S AM RNS GND 29 J m w ede 2 6000 EF1152AFT0133 88512 4C ES wma ES amm anm 3 a m The DINI Group DN3000k10S User s Manual Version 1 2 April 9 2003 The DINI Group The TE INE Group The information contained within this manual and the accompanying software program protected by copyright all rights are reserved by the DINI Group Therewith the DINI group reserves a the right to make periodic modifications to this project without obligation to notify any person or entity of such revision Copying duplicating selling or otherwise distributing any part of this product without the prior written consent of an authorized representative of the DINI Group is prohibited DN3000k10 DN3000k10S DN5000k10 DN5000k10S DN3000k10SD and DNPCIEXT S3 are trademarks of the DINI Group 1010 Pearl Street Suite 6 La Jolla CA 92037 5165 www dinigroup com info dinigroup com 858 454 3419 FAX 858 454 1728 Copyright 2003 The DINI Group All Rights Reserved DN3000k10S User s Manual The
7. 7 551 lt 541 lt 531 lt 521 lt 7 511 E P7N 50 lt P7N 49 E P7N 40 E P7N 39 P7N 38 lt 7 Figure 5 2 SSRAM 1 018 Bus Signals DN3000k10S User s Manual Memories SSRAM 1 U18 2 ADV ADSP ADSC OE BWE GW BWA BWB BWC BWD MODE ZZ _ 10 1 2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 for future expansion Suld D1 D2 D3 D31 PARO PAR1 PAR2 PAR3 99999909 BEEN Memories FPGA U16 AK33 AF28 AG28 AJ31 AK31 AG29 AH29 AF26 AG26 AL32 AK32 AK34 AL34 L28 AJ27 AJ26 AH18 AH20 AH22 AJ32 AH32 AF30 AG30 AG33 AF33 AF32 AG32 AH33 AJ33 AH34 AJ34 AG31 AF31 AL33 AL21 AL20 AM22 AM21 AN18 AP18 AP20 AN18 AE18 AE19 AP22 AP21 AN26 AN25 AD18 AD19 AG19 AG20 AF20 AF21 AE20 AE21 AG21 AG22 AH24 AH25 AF22 AF23 AL26 AL27 AH26 AJ25 AK26 AK27 AG23 AF24 a P6N 79 P6N 77 lt M 6 76 lt lt P6N 75 lt lt oR P
8. seek oe tone Daughter Card 05 PowerSupply 2 229299 DER Options Power Connector 8 Unbuffered Connectors J3 4 Connector J5 6 7 B ffered l O esce Soe dae ACTING cra ose xd GAR teh M rte PASSIVE oscuro ER Testint rfaGe 2 Ea ex E Gonnector JT 2 2 Daughter Card I O Connections Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset DN3000k10S User s Manual J26 LED Signals Header 8 4 Bus Bars 8 5 The 200 Pin Connectors J23 J24 J25 8 5 The Signals soie enkaa uv eke oo a idu 8 5 Chapter 9 Utilities PCI Debug General Pontificating 9 1 9 1 AETEST Utility Installation Instructions 9 2 Installation Instructions for 005 9 2 Installation Instructions for Windows NT 9 2 Installation Instructions for Windows 2000 9 2 Installation Instructions for LINUX
9. pEVSEL LE DEVSEL B36 DCAP3 IB EH IRDY uo GND eens Le C BE2 30 AD17 HE AD17 DCAP4 DR3X2 AD19 19 021 B29 AD21 021 GND AD23 AD23 C BE3 B28 C BE3 LH DCAPS AD25 HE AD25 B AD27 205 GND AD29 AD31 B20 AD31 031 Bred B REQ R54 10k GND CLK PCLK GND KEYWAY J31 B PRSNT2 PRSNT2 HE PME 4 1 INTD 8 INTE 5v HDR4X2 5V 5V TDX 400 Ba GND 12V COMPONENT SIDE SIDE Figure 3 2 Edge Connector DN3000k10S User s Manual PCI 3 3 PCI PADMASTER SHOWN ALL DIAMETERS FINAL AFTER PLATING VIEWED FROM PRIMARY SIDE 6 010 oboo MARET amp z 9 50000 99 999 o soonpop 000090808 5550555555 3 362 gt Be gt al Jo Frer rere ee rrrr 11 985 1 310 1 882 1 955 4 426 4 510 6 126 Figure 3 3 DN3000k10S Dimensions Remember that the function of this pin was deleted in the 2 2 version of the PCI Specification The pull up is 1M which should not adversely impact PCI functionality in any way The PCI JTAG signals TDI TDO TCK TRSTZ are not used TDI and TDO are connected together per the PCI Specification to maintain JTAG chain integ rity on the mothe
10. C15 21 BS BS 51 R11 C KU 0110000010000 0000000000000000 32 14 52 5 5 cd at 200 151 C39 mu _ L C53 C54 Y 1 or J25 Lt 09 g 5 m JS Ss 50 U16 151 o aoe BORN 5 4 0 13 x1 A H 2 B 5 o o 2468 10121416 1820222426 28 30 32 34 42 931 I LE 55 B1 B62 863 SOCAL EO Figure 2 12 Location of J1 on the DN3000k10S DN3000k10S User s Manual 2 17 DN3000k10S Features Overview and General Description you will find that the signals are placed on the connector in the same order as the JTAG cable A schematic of J1 is shown in Figure 2 13 Table 2 1 Signals and Connections to JTAG Cable J1 Signal Name Red 3 3 1 2 3 4 Black GND 5 6 17 19 21 or 24 Yellow CPLD TCK 8 Purple CPLD TDO 10 White CPLD TDI 12 Green CPLD TMS 14 J1 1 2 5 6 C_CCLK _ 8 CPLD_TCK C DONE 9 10 CPLD C DIN 11 12 CPLD TDI C PROG 13 14 CPLD TMS C INIT 15 16 FTCK 18 19 20 FTDI 21 22 FTMS PUPOS1 23 24 HDR12x2 90 DEG M Figure 2 13 J1 CPLD JTAG Configuration FPGA Serial Configuration and FPGA JTAG
11. 6531 lt 621 lt lt 650 lt 59 lt 58 lt 571 lt 561 lt 551 lt 541 lt 53 lt 52 E 51 ee 50 lt 491 lt 481 lt 71 lt 461 lt 451 Figure 5 4 SSRAM 0 15 Bus Signals DN3000k10S User s Manual Memories SSRAM 3 015 2 ADV ADSP ADSC OE BWE GW BWA BWB BWC BWD MODE ZZ _ Suld 1 SAO SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 for future expansion Suld sseJppy mE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 PARO PAR1 PAR2 PAR3 Pp suld Memories Table 5 1 has the details of each SSRAM Table 5 1 Requirements for Non Standard SSRAMs 3 3V Install Resistor R55 R48 R49 R90 R182 3 3V Short to Pin 15 43 3 V Short to Pin 65 Flowthrough Syncburst Flowthrough or Pipeline GND Install Resistor R56 R50 R51 R98 R181 NC No Resistors 43 3 V Sho
12. BX DS gt SR gt Figure 2 2 General Slice Diagram DCM DCM gt Configurable Logic Programmable I Os 1 1 1 90000000 Block SelectRAM Multiplier Figure 2 3 Virtexll Architecture Overview 2 4 The DINI Group Multipliers DN3000k10S Features Overview and General Description embedded memory is dual ported and quite flexible Virtually any type of memory be constructed FIFOs dual port RAMs single port RAMs etc The 18 Kb block SelectRAM dual port memory consists of an 18 Kb storage area and two completely independent access ports A and B The structure is fully symmetrical and both ports are interchangeable See Figure 2 4 for a diagram of the memory Data can be written to or read from either port in almost any configura tion Each port is synchronous with its own clock clock enable and write enable Note that the read operation is also synchronous and requires a clock edge We have found that a functional description of the memory is sufficient for the synthesis tools to recognize the memories and implement the embedded blocks More on the synthesis issues in Synthesis and Emula tion Issues on page 2 29 Virtexll devices feature a large number of embedded 18 bit x 18 bit two s complement embedded multipliers see Figure 2 5 The XC2V6000 contains 144 of
13. 8 lt lt 5 9 lt 5 lt 5 1 lt 5 21 lt 5 lt 5 lt 5 151 lt 5 6 lt 5 171 lt 5 18 lt 5 9 lt 5 20 lt 5 21 Figure 5 3 SSRAM 2 017 Bus Signals SSRAM 2 017 CE CE2 ADV ADSP ADSC OE BWE Gw BWA BWB BWC BWD MODE 22 Suld SAO SA1 SA2 SA3 SA4 SA5 7 8 9 10 11 12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 for future expansion Suld SseJppy mE DO D1 D2 D3 D4 D5 D6 D7 08 09 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 PARO PAR1 PAR2 PAR3 PF suld The DINI Group 016 V34 P33 N33 M33 L33 W24 V24 P32 N32 L32 M32 T30 030 L30 M28 P29 N29 M27 L27 M34 L34 T29 U29 M29 129 27 N27 R28 R29 N31 P31 N30 P30 V33 T28 W28 V28 T32 R32 M31 L31 U34 033 925 T25 U27 U26 w25 V25 R34 T33 R31 T31 R27 T27 M25 N25 M26 N26 V27 V26 T24 U24 P26 R26 P25 R25 N34 P34 N28 p MM PONI 25 lt lt Aha p0NI 3 X M 22 lt 21 1201 4
14. P6N 4 CKEO G20 P7NX 6 1 A28 28 WE 2 K19 6 6 26 CAS 26 lt 6 20 RAS PONAT F24 PONE BA1 J20 6 27 4 26 6 23 DQMB1 00 022 lt P6N 1 2 T 422 PONIO DQMB3 m C28 4 P6N 25 5 27 6 24 DQMB5 c A24 lt 11 DQMB6 9 A23 6 1 0 DQMB7 024 6 18 AO C24 6 19 A1 H24 P6N 17 A2 6 15 A3 H25 P6N 16 4 gt H22 6 141 5 2 4 6 11 A6 3 B30 4 P6N 13 A7 B32 PENi A8 v B31 lt 6 121 A9 5 223 6 9 10 a E31 4 6 6 A11 B24 4 PENES A12 C22 lt 6 9 1 K28 c 64 K23 lt 6 63 001 125 P6N 59 002 D32 P6N 57 E32 P6N 56 DQ4 4 nis DQ5 K26 P6N 50 DQ6 G29
15. PENGA H29 4 pas 033 P6N 45 9 E33 lt 6 441 0010 J27 P6N 43 DQ11 A31 6 38 DQ12 G25 P6N 37 DQ13 G24 6 DQ14 5 E26 P6N 35 0015 K20 6 4 DQ16 5 F21 6 3 DQ17 o 22 lt 11 0018 B21 lt 10 DQ19 F20 DQ20 020 7 5 DQ21 021 4 0022 7 0023 F19 lt 7 91 DQ24 F18 7 190 DQ25 J17 lt 7 89 DQ26 K17 88 DQ27 K16 7 83 DQ28 K15 7 82 DQ29 H10 P7N 81 DQ30 P7N 80 0031 Figure 5 10 SDRAM U3 Bus Signals 1 of 2 5 10 The DINI Group Memories FPGA U16 SDRAM 03 continued K22 6 21 2 B28 PENES lt 60 K24 PENES DQ35 29 6 54 6 J23 PENES DQ37 J24 4 PENES 126 PENES 118 PENAT DQ40 119 prs qt DQ41 428
16. ops S Matrix 4 ike Divide and lt 1850 ES Phase select lt Matrix gt i Figure 4 6 Functional Diagram of Roboclockll 1 and Roboclockil 2 4 8 The DINI Group Clocks and Clock Distribution 1 GND 8 1 GND 8 o o O O0 O O0 O0 O PLLSEL1 PLLSEL2 MODE1 MODE2 INV1 2 FBDIS1 FBDIS2 RBDFO RBDF1 DDSO 0051 RBCF0 RBCFi CDSO CDS1 o o o o O O O O O O O O O O RBFFO RBFF1 FDSO FDS1 RBEFO RBEF1 EDSO EDS1 FS1 FBF01 501 FBDS11 52 FBF01 FBDS02 FBDS12 o 0o o o o o Oo gt o o o O 6 1 1 3 3V 8 1 3 3V 8 Figure 4 7 Header Layout Note that the final two pins for header J14 J16 have been omitted from the layout diagram The Header Classifications are shown in Table 4 2 Table 4 2 Header Classifications Controls Input Pins Group I General Control Group 2 PPL1 Divider Control Group 3 PLL2 Divider Control Group 4 Feedback and fyoy Control The input pins are either LVTTL or 3 level input pins The LVTTL pins need to be jumpered HIGH or LOW which is achieved by connecting the input pin to the neighboring 43 3 V or GND pin using a jumper The 3 level input pins can be in a HIGH MID or LOW state The HIGH and LOW states are achieved in the same way as the LVTTL pins The MID state is reached by leaving the input pin unjumpered The Roboclockl
17. 1 AP31 AN30 AP30 AM29 AN29 AP29 AM28 AN28 AP28 AM27 AM26 125 25 AM24 AL24 AJ24 AK24 AP23 AM23 123 AJ23 AN22 AL22 AK22 21 21 AM20 AJ21 AJ20 117 19 AJ17 Figure 3 1 FPGA Pin Connections for PCI Signals 68 lt 86 6 8 G2 6 68 468 lt 4 8 5 6 5 0 868 EDSEL i i REa lt REQ64 48 6 48 868 868 5 LOCK _0 4 lt CGIBE 7 6 A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A52 B44 B33 B26 A34 B35 B16 A36 B37 A38 A26 B18 A60 B60 A67 A6 B40 B42 B39 A43 A17 A15 A91 B90 A89 B89 88 87 86 86 85 B84 A83 B83 A82 B81 A80 B80 79 78 A77 B77 76 75 74 B74 A73 B72 A71 B71 A70 B69 A68 B68 A65 B66 A64 B65 PCI Pin P2 PCI Pin P3 The DINI Group GND AD32 GND AD34 AD36 GND AD38 AD40 AD42 AD44 GND AD46 AD48 GND AD50 AD52 VIO AD54 AD56 GN
18. 9 3 Installation Instructions for Solaris 9 3 Installation Instructions for Windows 98 9 4 AETEST Options Description and Definitions 9 4 E deber bate 9 4 AETEST Main Screen 9 6 Options zc Sect Bi MER RED 9 6 Menu mE mI UU 9 7 Memory 9 9 APPENDIX ABerg Connector Datasheets vi The DINI Group List of Figures FIGURE 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 3 1 3 2 3 3 3 4 3 5 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 5 1 5 2 5 3 5 4 5 5 5 6 5 7 DN3000k10S User s Manual List of Figures TITLE PAGE DN3000k10S Block Diagram 2 2 General Slice Diagram 2 4 Virtexll Architecture 2 4 Dual Port Data Flows 2 5 Embedded 2 6 Block Diagram of ATmega128L and DN3000k10S Interfaces clou eed wt 2 10 44 Analog to Digital Connections 2 11 AVCC 2 12 93 Unused uP Connections 2 13 ATmega128L JTAG 2 13 J29 Schematic coc ee eee i eee a A 2 14 Location of J1 on
19. Off Board Clock to the DN3000K10S i ERG e RAW aero a dee BERS 4 6 Roboclockll PLL Clock Buffers 4 7 Jumper 4 7 General 4 11 Feedback and Clock Multiplication 4 11 Clock 8 4 11 Clock SKEW rrr Ere eet ened 4 12 Differential Clocks 4 13 Useful Notes and 4 14 Customizing the Oscillators 4 14 Chapter 5 Memories ssa md 5 1 SSHAM Notes 5 1 Pipeline Flowthrough 2 5 7 SDRAM oes dd en uiae dedans 5 9 Header Descriptions J19 and J18 5 11 iv The DINI Group Chapter 6 Chapter 7 Chapter 8 User Notes DCMs for Clock Management on 5 12 DCM B asi68 EUR Power Supplies and Power Distribution oii thi wae hed setae te ee ERR 13 gt tari ea eel eg eet eee ee CE Header J17 Off Board Power Stand Alone Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors betes eam wis e Features codon
20. PiN49 24 7 7 124 PiN47 P7N27 24 7 7 124 P7N25 P3N89 26 7 126 PiN43 26 7 126 PIN45 P7N21 26 7 126 P7N23 P3N88 27 7 127 1 42 27 7 427 PiN44 P7N20 272 7 127 P7N22 P3N87 28 7 428 P3N85 PIN4T 28 7 128 P1N39 P7N19 28 7 128 P7N17 P3N86 29 129 GND PIN40 29 7 429 GND P7N18 29 i29 GND P3N83 30 7 130 P3N84 PiN37 30 7 130 PiN38 P7Ni5 30 7 130 P7N16 GND 22 152 P3N79 GND 42 5 154 PTN33 GND 22 152 P3N76 3417 134 P3N78 PIN3O 3417 134 PIN3Z P7N8 3417 134 P7NTO P3N74 36 7 7 136 P3N72 1 28 36 7 7 136 P1N26 P7N6 36 7 7 136 P7N4 P3N69 37 7 7 437 P3N71 23 aj 7 437 PIN25 P7Ni 7 437 P7N3 P3N68 38 7 138 P3N70 1 22 38 7 138 PIN24 P7NO 38 138 P7N2 P3N67 39 139 P3N65 PiN21 39 7 139 PiN19 PON77 39 7 439 PON75 P3N66 40 140 GND 1 20 40 140 GND PON76 40 7 440 GND P3N63 41 7 7 141 P3N64 PiN17 41 7 141 PINTS PON73 4117 7 141 74_ GND PSN GND a GND 4413 dd P3N56 4617 145 P3N58 PINTO 4617 145 PINT2 PUN66 4617 145 PONS P3N55 46 7 146 P3N53 PiN9 46 7 146 PON65 46 7 146 PON63 P3N54 AZz 7 P3N52 PINS 47 7 7 447 PING PONG4 47 7 7 447 PON62 P3N49 48 7 148 P3N51 PiN3 48 7 148 PINS 59 48 7 148 PON61 P3N48 49 7 149 P3N50 PiN2 49 7 149 PING 5
21. 9 4 AETEST Startup Screen No PCI Peripheral Recognized isiro 9 5 AETEST Main Screen 9 6 AETEST PCI 9 7 AETEST Memory 9 9 AETEST Write to Memory Test 9 10 AETEST Read Memory 9 10 AETEST Write Read Test 9 11 AETEST Memory 9 11 AETEST Memory 9 12 AETEST Write Memory Byte 9 12 AETEST Read Memory 9 13 AETEST Write Read Memory Byte 9 13 Berg 91403 003 Datasheet Page 1 of 2 A 2 Berg 91403 003 Datasheet Page 2 2 A 3 Berg 91294 003 Datasheet Page 1 of 3 A 4 The DINI Group List of Figures Continued FIGURE TITLE A 4 Berg 91294 003 Datasheet Page 2 of 3 A 5 Berg 91294 003 Datasheet Page 3 of 3 DN3000k10S User s Manual List of Figures The DINI Group List of Tables TABLE 2 1 2 2 2 3 2 4 2 5 3 1 3 2 3 3 3 4 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 1 5 2 6 1 6 2 7 1 7 2 8 1 DN3000k10S User s Manual TITLE Signals and Connections to J1 FPGA Serial Configuration Header FPGA JTAG Configuration Header J2 Configuration Jumper Settings
22. 91 lt 18 lt 7 lt 6 lt 51 p PON 14 P0N 13 lt 2 lt 11 lt 44 lt 43 lt 2 lt 41 lt 40 lt 39 lt 8 lt 371 lt 36 lt 351 E 4 E 33 lt 321 lt 1 lt 301 lt 29 lt 28 lt 271 lt 26 lt 24 lt 7 21 lt lt 7 01 lt lt 6 lt 51 E 74 lt P0N 73 E 72 lt 71 lt 70 lt 69 lt 6 lt 671 E PON 66 E 65 lt 641 lt
23. Figure 4 3 Common Clock Configurations more than enough information to satisfy the user s needs See Figure 4 4 NOTE C55 C57 C61 and C62 are stuffed with 0 ohm resistors Note that the schematic shows capacitors in positions C55 C57 C61 and C62 The DN3000k10S has 0 ohm resistors in these capacitor positions The termination resistors R20 R23 and R25 R28 are not stuffed DN3000k10S User s Manual 4 5 Clocks and Clock Distribution 5V C62 PLL2B_PRE R20 68 1 Ribbon Cable 105 gives the user a simple means to provide off board clocks Providing an onto the board The user can attach 10 pin ribbon cable to J21 and J22 of the Clock Grid J21 consists of an input to 3807 1 and differential pair Off Board inputs to both Roboclockll s J22 consists of ground pins for signal integ Clock to the rity These signals are described in Table 4 1 on page 4 3 BUFINA is a stan DN3000k10S dard 3 3 V TTL input Both differential pairs provide some flexibility The user can bring a single 3 3 V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair The differential clock inputs must obey the electrical specifica tions listed in Table 4 8 on page 4 13 4 6 The DINI Group Clocks and Clock Distribution While attaching a ribbon cable the user can jumper either oscillator signal CLOCKA CLOCKB to BUFINB
24. PAN 1 P2N 21 1 11 1 0 P2N 20 P1NX 10 0 PANX 13 P2N 19 13 12 P2N 18 12 P4NX P2N 15 GND P2N 14 P2N 9 P1N 77 P2N 8 P1N 76 P2N 7 P1N 75 P2N 6 P1N 74 7 14 The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors Chapter 8 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Reset Schemes A LTC1326 chip from Linear Technology controls reset functionality for the DN3000k10S Figure 8 1 shows the distribution of the reset signal PWRRST In addition to controlling the reset the power supplies rails 5 V 43 3 V and 1 5 V are threshold detected by the LTC1326 Under voltage conditions will case the assertion of the reset signal The LTC1326 has a push button Momentarily depressing this button causes a 200 ms reset pulse on the signal PWRRST If the push button is depressed for 2 seconds and held PWRRST is asserted continuously LED5 when lit means that reset is asserted so if you press and hold S1 you should see LED5 illuminate after a few seconds If LED5 illuminates for any reason during normal operation this indicates that PWRRST is active and that something is wrong Note that if you press S1 and release it quickly you probably won t see LED5 since the 200 ms reset pulse is not strong long enough for the eye to observe Depre
25. configuration bit file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible Virtexll FPGA is shown below in Table 2 5 Note that several BIT files can be put on a 16 megabyte card We supply two 16 megabyte SmartMedia cards with the DN3000k10S SmartMedia is a standard so you can get more SmartMedia cards if you want The DN3000k10S requies a 3 3 V card Card sizes of 16 32 64 and 128 mega bytes have been tested on the DN3000k10S We have not seen 256 MB or larger cards for sale yet but when we do there will probably be an update to the CPLD and processor on our website to support them Table 2 5 Virtexll FPGA Approximate File Sizes Number of Configuration Bytes Virtexll FPGA XC2V3000 1 311 804 XC2V4000 1 957 500 XC2V6000 2 731 196 XC2V8000 3 632 892 We get our SmartMedia cards from http www computers4sure com A Delkin Devices 16 megabyte card part number DDSMFLS2 16 sells for about 15 A 32 megabyte card part number DDSMFLS2 32 will set you 2 28 The DINI Group DN3000k10S Features Overview and General Description back about 20 see Figure 2 15 New SmartMedia cards require format ting before use NOTE SmartMedia cards must be formatted before they are used The Windows format command does not is necessary to use the FlashPath utility to format a SmartMedia card Figure 2 15 Delki
26. 1 digital clock manager 5 12 See also DCM DIMM 5 1 5 9 6 2 DINDOF 2 16 divider function 4 10 to 4 12 DLL 7 1 DN3000k10 7 1 7 6 to 7 7 DN3000K10S 2 20 DN3000k10S 1 1 2 1 to 2 3 2 6 to 2 7 2 9 2 11 to 2 12 2 14 to 2 16 2 20 to 2 21 2 24 to 2 25 2 27 to 2 28 2 30 to 3 1 3 4 4 1 4 3 4 5 7 1 block diagram 2 2 clock grid 4 3 configuration 2 9 features 2 1 to 2 2 FPGA configuration 2 20 memories 5 1 power supplies 6 1 1 2 SelectMAP configuration 2 25 serial port configuration 2 21 DN3000k10SD 7 1 7 6 to 7 8 DN300k10S battery 2 9 description 2 2 DN3k10D1 7 4 DNPCIEXT S3 3 1 DONEF 2 16 DOS 9 1 to 9 2 9 4 9 6 DOS extender 9 1 to 9 2 9 4 DOUTBSY 2 19 DOUTBSYF 2 16 drive power connector 6 4 dual port 2 5 E ECLK 4 13 EEPROM 2 12 5 11 to 5 12 embedded memory 2 1 2 3 2 5 2 30 encryption 2 1 2 7 to 2 8 ESD 1 1 extender card 3 1 external memories 2 2 5 1 F FBDIS 4 10 to 4 11 FBDS 4 10 to 4 11 FBFO 4 10 4 13 FCLK 4 10 4 13 to 4 14 5 1 5 12 feedback clock 4 11 feedback disable 4 10 feedback output divider function 4 10 feedback output phase function 4 10 FIFO 2 5 FLASH 2 1 2 3 2 9 2 12 2 15 9 6 FlashPath 2 25 2 28 to 2 29 FPGA 7 8 FPGA Configuration 2 9 FPGA configuration 2 1 2 3 2 9 2 16 2 26 8 1 frequency select 4 10 FS 4 10 to 4 12 4 14 FTCK 2 16 2 20 FTDI 2 16 2 20 FTDO 2 16 2 20 The DINI Group Index Continued FTMS 2 16 2 20 FWRTSM 2 16
27. 198 P4NX2 P2N10 98 7 198 P2N8 PiNXO 98 7 198 P1N76 GND 99 b GND 99 3 2 7 GND 99 1 75 12V P 3 12V m P2N6 12V T H 74 100 e 200 100 e 200 100 e 200 GND 203 201 GND GND 203 201 GND GND 203 201 GND GND 204 i2 202 GND GND 204 i2 202 GND GND 204 i2 202 GND Em 200 1 200 2 200 3 Figure 8 6 200 Pin Connectors Signal Connections 8 8 The DINI Group Chapter 9 Utilities PCI Debug General Pontificating Debugging of PCI based hardware can be troublesome so it is best to do so with a tiered approach The following sequence of events needs to occur for PCI based peripheral to start working 1 The hardware must boot itself at power up in the case of the DN3000k10S a The pP must boot b Recognize the SmartMedia card Configure the FPGA Hopefully all this occurs before RST on the PCI bus is deasserted 2 The PCI BIOS executes the PNP routines and configures the BARs on all PCI peripherals The operating system driver initializes the card 4 The application initiates communication with the driver and the application executes The steps are dependant Each of the steps must start and execute flaw lessly before the next step occurs When you get a PCI card for the first time it is necessary to debug each step before attempting to go to the next We provide utilities to help w
28. 2 BCLK 3 BCLK 1 45V 45V 45V DCLK 6 CCLK 4 CCLK 1 GND GND GND 3 3 V 3 3 V 3 3 V 1 71 P7N 49 P2N 3 GND GND GND P1N 70 P7N 48 P2N 2 P1N 69 P7N 47 P2N 1 P1N 68 P7N 46 2 0 P1N 63 P7N 41 P2NX 7 P1N 62 P7N 40 P2NX 6 P1N 61 P7N 39 P2NX 5 4 P1N 60 P7N 38 P2NX 4 1 P1N 57 P7N 35 PNX 0 P1N 56 P7N 34 P2NX 0 9 P1N 53 P7N 31 P3NX 9 GND GND GND GND P3NX 8 P1N 52 P7N 30 P3NX 8 P3NX 5 P1N 49 P7N 27 P3NX 5 P3NX 4 P1N 48 P7N 26 P3NX 4 P3N 89 P1N 43 P7N 21 P3N 89 7 8 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec tor Connections 123 123 124 724 J25 Pin P3N 88 P1N 42 P7N 20 P3N 88 P3N 87 P1N 41 P7N 19 P3N 87 P3N 86 P1N 40 P7N 18 P3N 86 P3N 83 P1N 37 P7N 15 P3N 83 P3N 82 P1N 36 P7N 14 P3N 82 P3N 77 P1N 31 P7N P3N 77 GND GND GN GND P3N 76 P1N 30 P7N P3N 76 P3N 75 P1N 29 P7N P3N 75 P3N 74 P1N 28 P7N P3N 74 P3N 69 P1N 23 P7N 1 P3N 69 P3N 68 P1N 22 P3N 68 P3N 67 P1N 21 PON 77 P3N 67 P3N 66 P1N 20 PON 76 P3N 66 P3N 63 P1N 17 PON 73 P3N 63 P3N 62 P1N 16 PON 72 P3N 62 P3N 57 PIN 11 PON
29. 3807 2 on J20 This results in full use of all of the timing devices on the DN3000k10S See Figure 4 5 WITHOUT 10 PIN RIBBON CABLE CLKOUT 20 1 CLOCKA J20 3 CLOCKB 420 5 to to 1 PLL2B J21 PLL2B J21 1 PLL1A PLLIA J202 2 BUFINB BUFINB J20 4 4 Buffer A undriven A undriven PLL2B PLL2B J21 1 BUFINB J20 4 of PLL1B J21 5 Buffer A or B BUFINA J21 undriven PLL1A J20 2 BUFINA 421 3 BUFINB J20 4 Roboclock2 E BUFINA J21 3 PLL1A 120 2 BUFINB J20 4 5 driven by Roboclock 1 BUFINA J21 3 BUFINB 9204 PLL1B J21 5 Requires wire wrap BUFINA Buffer A ACLK BUFFINB 9 Buffer B gt BCLK PLL1A Roboclock1 gt CCLK DCLK PLLSEL1 low PLL1B gt gt CCLK PLLSEL1 high PLL2B gt Roboclock2 gt PLLSEL2 high Roboclock1 gt Roboclock2 with PLLSEL2 low WITH 10 PIN RIBBON CABLE Connected to J21 J22 3 external PLL1B PLL2B and BUFINA are driven from cable BUFINB can be clocks jumpered to CLOCKA or CLOCKB or left undriven 2 external PLL2B and BUFINA are driven from cable with PLL1A jumpered to clocks CLKOUT or CLOCKA Same options as above for BUFINB PECL The board can be set up for PECL inputs in PLL1B and PL
30. 71 2 71 3 11 4 2 JTAG Programming The JTAG connection can be used to configure the FPGA and can also be used to connect the ChipScope Logic Analyzer www xilinx com xInx xil_prodcat_product jsp title chipscope_ila or other solutions such as the Bridges2silicon system see www bridges2silicon com The JTAG method of configuration should be used if the SmartMedia method isn t working Remember that a different bit file is necessary the bit file must use the JTAG clock for configuration Table 2 3 has the pinouts Table 2 3 FPGA JTAG Configuration Header Name on Schematic Cable Color Header Pin J1 16 J1 18 J1 20 J1 22 J1 5 J1 17 J1 19 J1 21 J1 6 J1 24 J1 1 J1 2 J1 3 J1 4 3 signal PUPOS1 on header J1 23 serves no purpose The FPGA on the 3000 105 can be configured SelectMAP mode using a Smart Media card SelectMAP configuration is the easiest and quickest way to configure the FPGA The DN3000k10S is shipped with two 32 MB Smart Media cards One of these Smart Media cards contains a reference design bit file produced for SelectMAP configuration and a file main txt that sets options for the configuration process for description of options see Creating Main Configuration File main txt on page 2 23 This Smart Media card has been marked as read only by the silver circular sticker on the card The other Smart Media card is empty and is for use with your
31. BARs are configured If AETEST does not see a PCI peripheral it recognizes you will see the following Figure 9 2 Searching Searching searching Searching searching Searching Searching searching searching searching searching searching Searching Searching Searching searching searching searching searching searching for for for for for for for for for for for for for for for for for for for for Quad Sharc VENDOR ID 5045 DEVICE ID DN2000K10 Asic Emulator VENDOR ID abcd DN2000K10 Asic Emulator DN2000K10 Asic Emulator DN2000K10 Asic Emulator DN3000K10S Asic Emulator 15064 15064 15064 15064 15064 15064 15064 15064 15064 15064 415064 Greg s Cohu s 2 2200 0 interface test VENDOR ID 1234 PowerPC bridge VENDOR ID 11e3 PowerPC bridge AntiFuse test 1 VENDOR ID 71f3 AntiFuse test 2 VENDOR ID 507 DEVICE ID 2367 AntiFuse test 3 VENDOR ID bc92 AntiFuse test 4 VENDOR ID e125 AntiFuse test 5 VENDOR ID e62c AntiFuse test 6 VENDOR ID 448b PCI Device VENDOR ID 5143 PCI Device Didn t find known device in the following list DEVICE ID 1234 2000E VENDOR ID abcd DEVICE ID 1235 1000E VENDOR ID abcd DEVICE ID 1236 1600E VENDOR ID abcd DEVICE ID 1237 6000 VENDOR ID abcd DEVICE ID 5678 64MB dram LFSR VENDOR ID 1234 DEVICE ID 5679 DEVICE ID old VID DID VENDOR ID 1010 DEVICE ID 50
32. DEVICE ID 0x02 PCI CS COMMAND 0x04 PCI CS STATUS 0x06 PCI CS REVISION ID 0x08 PCI CS CLASS CODE 0x09 PCI CS CACHE LINE SIZE 0x0c PCI_CS MASTER LATENCY 0x0d PCI_CS HEADER TYPE 0x0e PCI CS BIST 0x0f PCI CS BASE ADDRESS 0 0x10 PCI CS BASE ADDRESS 1 0x14 PCI CS BASE ADDRESS 2 0x18 PCI CS BASE ADDRESS 3 0 1 PCI_CS BASE ADDRESS 4 0x20 PCI CS BASE ADDRESS 5 0x24 PCI CS EXPANSION ROM 0x30 PCI CS INTERRUPT LINE 0x3c PCI CS INTERRUPT PIN 0x3d PCI CS MIN GNT 0x3e PCI CS MAX LAT 0x3f Input config offset hex 0x00 0xff word to write in hex Loop indefinitely y or n If looping was selected any keypress will stop the loop 9 8 The DINI Group Memory Menu Utilities Read config uration DWORD Allows read from configuration space Has options for single read loop read with display and loop read without display Configure BARs from File Reloads the PCI configuration of the active device from a file It writes 0x001F to the command register and writes the 6 bars with the values from the file This is useful for hot swap ping devices power switch still required on extender or reinitializing a device when its configuration has been altered WARNING Because the PCI BIOS is not assigning the BARs for this device you may induce a memory conflict by using this option This option is for advanced users only Save Bar Configuration to File writes PCI Device ID Vendor ID and the BARs into a file from the a
33. DINI Group Table of Contents Chapter 1 Getting Started The DINI Group Technical Support 1 1 Relevant Information 1 1 CONVENTIONS 1 3 Chapter 2 DN3000k10S Features Overview and General Description DN3000k10S Features 2 1 DN3000k10S Description 2 2 Easy Configuration via SmartMedia 2 3 FPGA Virtexll U16 2 3 Flip Flops and 2 3 Embedded 2 3 Multipllets teas eee Rx RA XXE RERO 2 5 VO ISSUCS i tn RR ERREUR ENNIUS EE 2 6 Bitstream 5 2 7 WhatDES IS dca la xe edes 2 7 Programming Encrypted Bitstreams Using JTAG 2 8 Programming Encrypted Bitstreams Using SmartMedia 2 8 The Battery i creek ace of wae 2 9 uP and FPGA Configuration 2 9 The pP Some 2 9 A D Analog to Digital Converter 2 10 93 Unused Connections 2 12 ATmega128L JTAG 2 12 Programming the ATmega128L 06 2 14 Detailed 1 5 5 2 14 95288 1 2 16 Some Miscellaneous Not
34. DONE pin and prints out whether or not the FPGA s have been config ured along with the file name that was used for configuration Select file to use in place of main txt By default the processor uses the file main txt to get the name of the bit file to be used for configuration as well as options for the configuration process How ever a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the config uration process By selecting the main menu option 4 the user can select a bit file from a list of files that should be used in place of main txt After selecting new file to use in place of main txt the user should select Main Menu option 1 to configure the FPGA s according to this new file If the power is turned off or the reset but ton S1 is pressed the configuration file is changed back to the default main txt List files on SmartMedia This option prints out al ist of all the files found on the SmartMedia card Memory test BlockRAM SSRAM SDRAM This option will only appear if the FPGA is configured In addition the test will only be run if the FPGA is configured with the reference bit file that was shipped with the DN3000k10S PC Bit File Sanity Check A version of the sanity check has been compiled for use on a PC the executable is sanityCheck exe which can be found on the CD shipped with the DN3000k10S This allows you to run the sanity
35. DQ42 1 DQ43 9 D27 40 DQ44 5 A30 4 Po 39 DQ45 v 27 eeN 34 DQ46 2 025 PENE DQ47 eenxt21 DQ48 9 E22 PENX DQ49 a E21 penx DQ50 H21 9 0051 5 e7Nx 81 pas2 lt 21 0053 Gis 7 11 pasa G19 7 2 DQ55 19 P7wr 931 pase 18 P7Nr 921 DQ57 7 871 DQ58 7 86 DQ59 117 7 85 116 P7N 841 015 79 0062 D14 PTNT E24 PONE A29 29 CB1 E 022 2 J22 PONEO D26 2 E25 Peni CB5 A24 lt 11 A23 amp 10 CB7 F26 Pe7N 761 sce n 25
36. Don t Display Vendor and Device ID 4 Loop on all PCI device numbers and Display Device Vendor ID s 5 Display all PCI information for PCI device function 7f 0 6 Write config dword 7 Read config dword C Configure BAR s from File V Save BAR Configuration to File M Main Menu Q Quit PCI BASE ADDRESS 0 d800000 1 e0000000 2 00000000 3 00000000 4 00000000 5 00000000 Please select option Figure 9 4 AETEST PCI Menu Set PCI Device Number sets a PCI device number of your choice as the active device hex input This option lists the available Device Numbers to help you match up your Device ID and Vendor ID with the device number Set PCI Function Number sets a PCI function number of your choice as the active function of a multi function device hex input This option lists the Device ID and Vendor ID of each function within the active device number to help you to choose the desired function Display all Configured PCI Devices Displays the PCI Device Numbers and corresponding Device ID and Vendor ID of all devices seen on the bus This does not display device numbers with a Device ID and Vendor ID of all ones OxFFFF Display Vendor and Device ID for PCI device function Displays the Vendor ID and Device ID of the active device and function number In the example above this would display the Vendor ID and Device ID of the PCI device at device number 0x7F function number 0x00 Loop on PCI de
37. Easy FPGA configuration via standard SmartMedia FLASH card Microprocessor controlled ATmega128L RS232 port for configuration operation status and control Fastest possible configuration speed via SelectMap Partial reconfiguration supported 5A on board linear regulator for 3 3V and 1 5V Standalone operation via separate power connector 43 3V not needed on backplane 6low skew clocks distributed to all FPGA and test connectors 2CY7B993 4 Roboclockll PLLs 2 socketed oscillators PCI Clock 1dividable clock via CPLD e Direct support for Synplicity s Certify TDM interconnect multiplexing DN3000k10S User s Manual 2 1 DN3000k10S Features Overview and General Description e Robust observation debug with 500 connections for logic analyzer observability or for pattern generator stimulus e Status LEDs e User designed daughter PWB for custom circuitry and interfaces e Chipscope fully supported via JTAG interface Figure 2 1 shows a block diagram of the DN3000k10S DN3000k10S Description 95288XL 32kx8 SRAM CPLD 16 32 64 byte FPGA confi figurat ion Smart Medie Car The 3000 105 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions The DN3000k10S can be hosted in a 32 64 bit PCI PCI X slot or can be used stand alone device A
38. For write access only Writes to all four bytes The DN3000k10S has a socket for a 43 3 V 168 SDRAM DIMM Either registered or unbuffered modules fit in the socket U3 The same PC100 PC133 SDRAM modules that you put into your PC are used here Your DN3000k10S will be stuffed and tested with 1 Gbyte PC133 SDRAM DIMM unless otherwise requested All DIMM pins are connected to the FPGA and the pins are shown in Figure 5 10 and Figure 5 11 We aren t quite sure what the largest size SDRAM DIMM is that will work in the DN3000k10S but here is the math as best we understand it 14 Address lines A 13 0 multiplexed between RAS and CAS address 10 not used for CAS 27 2 bank address BA 1 0 2 4 chip selects S 3 0 used in pairs 1 So we think that there are 29 address bits 27 2 and 2 possible chips selects which add one more address bit This totals 30 address bits 1 of 72 bit long words which is 8 Gbytes Please tell us if this math is wrong The 43 3 V power supply may not be able to handle 8 Gbytes SDRAM array A bank of this size probably consumes more than 5 A on 3 3 V SDRAM modules require 4 clocks CK 3 0 These clocks are driven by the RoboClockll 1 and the signal names DCLK 3 0 DN3000k10S User s Manual 5 9 Memories FPGA U16 SDRAM U3 B27 lt P6N 22 50 G26 6 6 121 61 G22 6 PeN 2 S2 PeN 3 53 9 B23 6
39. MCE 2 16 MCLE 2 16 MRE 2 16 MRTMED 2 16 MWE 2 16 MWP 2 16 SMCE 2 16 NDNNNNNN SMCLE 2 16 SMRE 2 16 SMRTMED 2 16 SMWE 2 16 SMWP 2 16 SRAMCS 1 4 2 16 TCK 2 12 2 20 3 4 TDI 2 12 2 20 3 4 TDO 2 12 2 20 3 4 TMS 2 12 2 18 2 20 3 4 TRST 3 4 UPAD 2 16 UPADC 2 10 UPADDR 2 16 WR 2 16 slice 2 3 to 2 5 SMALE 2 16 SmartMedia 8 1 9 1 SmartMedia card 2 9 2 15 to 2 16 2 19 2 25 to 2 29 8 1 9 1 SMCE 2 16 SMCLE 2 16 SMRE 2 16 SMRTMED 2 16 SMWE 2 16 SMWP 2 16 speed grade 2 3 2 30 to 3 1 SRAM 2 9 2 16 5 1 6 2 SRAMCS 1 4 2 16 SSRAM 2 26 to 2 27 5 1 5 3 to 5 9 5 12 6 2 8 7 9 2 9 13 Startup Clock 2 21 static electricity 1 1 Synopsys 2 29 to 2 30 Synplicity 2 1 2 29 to 2 30 synthesis 1 2 2 5 to 2 6 2 29 to 2 30 synthesis tools 2 5 to 2 6 2 29 to 2 30 T target design 2 2 TCK 2 12 2 20 3 4 TDI 2 12 2 20 3 4 TDO 2 12 2 20 3 4 technical support The DINI Group 1 1 TMS 2 12 2 18 2 20 3 4 TRST 3 4 The DINI Group Index Continued U UCF 2 6 3 1 UPAD 2 16 UPADC 2 10 UPADDR 2 16 V Vendor 9 7 Vendor ID 9 7 to 9 9 verbose level 2 23 to 2 26 Verilog 1 2 2 2 2 6 2 16 VHDL 1 2 2 6 Virtexll 1 2 2 1 2 3 2 5 2 7 2 9 2 19 2 21 2 28 3 1 3 4 5 12 6 2 to 6 3 DN3000k10S User s Manual Index architecture 2 3 to 2 4 voltage 2 6 2 11 to 2 12 2 21 3 4 4 11 4 13 6 2 to 6 3 7 5 to 7 6 WR 2 16 X XC2V3000 2 3 2 28 XC2V4000 2
40. P3N2 75 7 175 P3N1 P2N50 75 7 175 P2N49 PONTZ 75 7 115 PONTT 80 da Pone g GND GND GND 5 PANZ1 7917 179 P4N23 2 791 479 P2N43 PONS 79 479 PONS P4N20 80 7 480 P4N22 P2N40 80 7 180 P2N42 PONZ 80 7 180 PONG 4 19 8117 181 P4N17 P2N39 8117 181 P2N37 PONT 8117 181 PONX13 4 18 8217 7 482 P4N16 P2N38 82 7 182 P2N36 PONO 82 7 182 12 4 13 83 7 183 15 P2N33 83 7 183 P2N35 83 7 183 P4NT2 84 184 GND P2N32 84 184 GND 84 184 GND 11 85 7 485 4_ P2N31 85 7 185 P2N34 PONX7 85 7 485 4 10 86 7 186 P4N9 P2N30 86 7 186 P2N29 PONX6 86 7 186 5 Soo pans GND 874 HE pz GND 2 94117 F491 PANO P2N22 91 F491 P2N20 12 94117 391 92 7 192 P4NX13 P2N17 92 7 492 P2N19 PINX7 92 7 192 PINX9 1 5V 193 12 1 5V 93 7 193 P2N18 1 5V 93 7 193 PINX8 4 10 9417 7 194 P4NX9 P2N16 94 7 194 P2N15 PiNX6 94 7 194 PiNX5 PANX7 95 195 GND P2N13 95 7 195 GND 95 195 GND 6 96 7 196 _ P2N12 96 7 196 P2Ni4 PiNX2 96 7 7 196 PiNX4 5 97 197 2 11 97 7 497 P2N9 PiNXi 97 7 497 PIN77 98 7
41. Roboclockll 1 receives a clock input from the CPLD Also 2 can use DCLK7 from Roboclockll 1 as an input This is explained in Roboclockll PLL Clock Buffers on page 4 7 The common clock configurations are diagrammed in Figure 4 3 Second the input clock distribution can be configured as Configuration 2 CLKOUT PLL2B PRE CLOCKA lt gt PLL1A and CLOCKB lt gt BUFINB In this configuration a 3807 2 receives an oscillator input Roboclockll 1 receives an oscillator input while Roboclockll 2 receives the CPLD output clock signal 3807 1 is unused Finally the grid may be configured as Configuration 3 CLOCKA lt gt PLL1A and CLOCKB lt gt PLL1B PRE Both Roboclockll s receive oscillator clock signal inputs this case Mean while both 3807s are unused In the last two configurations 3807 clock driver chips are not used The user can wire wrap a clock to the unused driver s as needed This enables full use of the timing devices on the DN3000k10S Also the destination of the output clocks might dictate some other configuration This manual and other documentation should provide The DINI Group Clocks and Clock Distribution M A Dck ACLK1 _ __ 1 Ribbon cable foi external clocks connect DCLK 0 6 RoboClock 1 MBCLK4 BCLK3 MBCLK5 CONS usone ECLK4 MBCLK8
42. Virtexll FPGA Approximate File Sizes Present Signal Definitions M66EN Jumper Descriptions PCIXCAP Jumpers M66EN and PCIXCAP Encoding Clock Grid Signal Descriptions Header Classifications Jumper Definitions Frequency Range Settings Output Divider Settings Time Unit Clock Skew 06 LVPECL Input Specifications Clock OE Pin Jumper Settings Requirements for Non Standard SSRAMs Syncburst and ZBT SSRAM Timing Specification for 3 3 V Power Specification for 41 5 V Power Connector J8 Pins External Power DN3000k10SD Daughter Card I O Interconnects J26 Pin Outs List of Tables xi xii The DINI Group Chapter 1 Getting Started The DN3000k10S is sensitive to static electricity so treat the PWB accord ingly The target market for this product is engineers that are familiar with FPGAs and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However we have sold some of these units to people who are not as familiar with this issue The following web page has an excellent tutorial on the Fundamentals of ESD for t
43. able to see any error messages In addition without a serial port connection a user cannot select any Main Menu options after the config uration process is complete Creating Main Configuration File main txt To control which bit file on the Smart Media card is used to configure the FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media card The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow an example of a main txt file Options Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages Level 0 Fatal error messages Bit file errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration A single message will appear once the FPGA is configured e Level 1 messages that Level 0 displays Displays configuration type should be SelectMAP Displays current FPGA being configured if the configuration type is set to Select MAP Displays a message at the completion of configuration for each FPGA configured e Level 2 messages that Level 1 displays Options that are found in ma
44. data one clock cycle after the address phase and ZBT PL SSRAMs Figure 5 8 accept and return data two clock cycles after the address phase This allows the user to begin a write burst immediately after the last word of a read burst because read data will be returned before the first write data is required The timing is illustrated in Figure 5 9 and Table 5 2 Write Control amp Data Coherency Memory Block Figure 5 7 Syncburst ZBT Write Control amp Data Coherency Input K 1 lt Memory 18 2 Address Register urst pies ES Output Buffers 5 18 2 Burst Control 1 0 write write Addr Addr Reg1 gt Reg 2 Block epa 5 Address gt Register Figure 5 8 Syncburst ZBT PL oe 25 Setup i Address Phase Syncburst Write pen ADSP ZBT PL Phase ZBT FT T 1 1 1 1 i Flowthrough Pipelined Phase Ja if 1 1 Figure 5 9 Syncburst and ZBT SSRAM Timing 5 8 The DINI Group SDRAM Memories Table 5 2 Syncburst and ZBT SSRAM Timing Syncburst Address Phase CE CE2 CE CE CE2 CE address address or or 1 ADV 2 Write Phase BWE BWx data data Read Phase Valid Data Valid Data continue a burst 2ADV LD is low to load a new address high to continue bust
45. for the number of long words you with to write 1 to 1024 Three options are available 1 2 3 Read once and display Read indefinitely and display Read indefinitely and don t display Option 3 is a very useful scope loop Memory Fill Fill memory with a selected pattern Figure 9 9 Fill with 0 address data 0x55555555 Oxaaaaaaaa Oxffffffff data address O PWN EH 1 Input starting address hex and 32 bit aligned 000000 Input number of bytes divisible by 4 1000 Figure 9 9 AETEST Memory Fill You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be written The program will prompt for the number of bytes in hex you wish to fill 4 to The following fill options are available 1 DN3000k10S User s Manual fill with 0 fill all the locations with 0x00000000 clear the memory address data fill each long word with its address alternating 0x55555555 OXAAAAAAAA Oxffffffff set all of memory data address fill each long word with the address each bit inverted Utilities Memory Display Display 160 long words of memory You are prompted for the starting address in hex Input starting address hex and 32 bit aligned The following screen is displayed Figure 9 10 0 000000 000020 000040 000060 000080 0000a0 0000c0 0000e0 00
46. is a very nice feature and we recommend you use it on all signals The correct IOATTRIBUTE standard for the file is 33 All VCCO pins are connected to 43 3 V The VREF pins are used as 1 05 so the DN3000k105 does not support I O standards that require VREF No signals have a Board Termination Voltage So the I O standards supported are LVTTL Low Voltage TTL The low voltage TTL or LVTLL standard is a general purpose EIA JESDSA standard for 3 3 V applications that use the LVTLL input buffer and a Push Pull output buffer The standard requires a 3 3 V input and output source voltage Vcco but does not require the use of a reference voltage Veer a termination voltage LVCMOS33 3 3 Volt Low Voltage CMOS This standard is an extension of the LVCMOS standard JESD8 5 It is used in general purpose 3 3 V applications The standard requires a 3 3 V input output source voltage Vcco but does not require the use of a refer ence voltage or a termination voltage PCI X Peripheral Component Interface The PCI standard specifies support for 33 MHz 66 MHz and 133 MHz PCI bus applications It uses a LVTTL input buffer and a Push Pull output buffer This standard does not require the use of a reference voltage or a board termination voltage however it does require 3 3 V input output source voltage Vcco The DINI Group DN3000k10S Features Overview and Ge
47. on the DN3000k10 ASIC prototyping board This is a Mini D Ribbon MDR connector 50 pin manufactured by 3M used specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX OLC where is 050 0 5m 150 1 5m 300 3 0m 500 5 0 m Please contact 3M for further details http www1 3m com The DN3000k10SD Daughter Card provides 66 unbuffered signals including 5 single ended clock signals The function of these signals is position dependent NOTE Signals P4NX7 and P4NX6 are also used for direction select and output enable on U2 and U3 respectively J3 J4 Buffered Interface header IDC headers 50 pin providing 48 buffered signals See Table 7 2 on page 7 8 J5 J6 J7 Unbuffered Interface Header IDC headers 50 pin providing 66 buffered signals See Table 7 2 on page 7 8 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Buffered I O Test Interface Connector J1 The DN3000k10SD Daughter Card provides 48 buffered signals The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic lev
48. point to point The two Roboclockll s offer functional control of clock frequency and skew among other things The two RoboclocklI PLL clock buffers U11 and U12 are configured via header arrays J8 J10 J11 J13 J14 J16 and J5 J7 The DN3000k10S comes from the factory stuffed with CYB993V which can operate at frequencies from 12 MHz to 100 MHz The CY7B or AV versions of the chip are available These chips operate from 12 MHz to 100 MHz and 24 MHz to 200 MHz respec tively Each chip has 16 output clocks along with two feedback output clocks Two sets of eight output clocks are jumper selectable for each chip The feedback clocks are controlled separately The PLL clock buffers can accept either 3 3 V LVTTL or LV Differential LVPECL reference inputs The devices can operate at up to 12x the input frequency while the output clocks can be divided up to 12x the operating DN3000k10S User s Manual 4 1 Clocks and Clock Distribution ACLK CCLK 5 0 Roboclock1 X1 CLOCKA DCLK 7 0 Clock 2 CLOCKB Selection FCLK 5 0 Grid Roboclock2 ECLK 5 0 J20 J22 CLKOU CPLD ACLK 9 0 BCLK 9 0 X2 stuffed at factory with 100 MHz X1 stuffed at factory with 14 318 MHz PCI CLK PCI Connector Figure 4 1 Clock Distribution Block Diagram 4 2 The DINI Group Clock Grid Orientation and Description Clocks and Clock Distribution frequency Phase adjustments can be made in 625 ps or 1300 ps steps up to 10
49. serial port is mandatory and the FPGA can not be configured via the SmartMedia card until you have completed all the instructions in this section Reset the DN3000k10S by pressing S1 After about 10 seconds you should see the following in the HyperTerminal window ck k NEED FPGA STUFFING INFORMATION Enter number of FPGAs on Board 1 6 Using the keyboard enter the number of FPGAs on the board should be 1 for the DN3000k10S After you have entered this you should see the following menu Virtex II 1000 FG456 Virtex II 6000 FF1152 Virtex II 4000 FF1152 Virtex II 3000 FG676 Please enter selection 1 4 for FPGA Enter the type of FPGA that is stuffed on your DN3000k10S If you enter the wrong type of FPGA or the incorrect number of FPGAs on the board then you will need to reprogram the processor and follow these steps again DN3000k10S Features Overview and General Description CPLD XC95288XL 2 16 10 The processor and the CPLD are now ready to configure the FPGA S Please see the section titled Starting SelectMAP Configuration on page 2 25 for further instructions Some non volatile logic is needed to handle the counters and state machines associated with the high speed interface to the SmartMedia card We used an XC95288XL CPLD from Xilinx for this function The datasheet is on the CD ROM is titled xc95288x1 pdf Approximately 90 of the resources of t
50. single DN3000k10S stuffed with one XC2V6000 can emulate up to 500k gates of logic as measured by LSI A high I O count 1152 pin flip chip BGA package is employed The FF1152 package has 824 1 05 which allows for abundant connections to daughter connectors and external memories A total of 500 test pins are provided on the top of the PWB via high density connec tors for logic analyzer based debugging or for pattern generator stim ulus Custom daughter cards can be mounted to these connectors as a means of interfacing the DN3000k10S to application specific circuits A reference 32 bit PCI target design and test bench is provided in Verilog at no additional cost 5V ATmega103L Flash based uP FPGA Configuration Controller 45V External Cable mni Regulator Regulator 12V Roboclock PLL 1 CCLK gt DCLK control address 19 FlowThrou data 36 I i Pipelines conum T 18 ssRAM 512k x 36 Xilinx Virtexll FPGA 2V6000 4000 8000 FF1152 JL 32 64 Bit FlowThrough Pipelined control SSRAM 512k x 36 FCLK Module 2 2 Figure 2 1 DN3000k10S Block Diagram The DINI Group DN3000k10S Features Overview and General Description Easy The configuration bit files for the FPGA are copied onto 32 megabyte Configuration SmartMedia FLASH card provided and an on board microprocessor 5 co
51. the battery is limited only by its shelf life The method used to encrypt the data is Data Encryption Standard DES This is an official standard supported by the National Institute of Stan dards and Technology NIST and the U S Department of Commerce DES is a symmetric encryption standard that utilizes a 56 bit key Because of the increased sophistication and speed of today s computing hardware single DES is no longer considered to be secure However the Triple Data Encryp tion Algorithm TDEA otherwise known as triple DES is authorized for use by U S federal organizations to protect sensitive data and is used by many financial institutions to protect their transactions Triple DES has yet to be cracked Both DES and Triple DES are available in Virtexll devices What DES Is DES and Triple DES are symmetric encryption algorithms This means that the key to encrypt and the key to decrypt are the same The security of the data is kept by keeping the key secret This contrasts to a public key system like RSA or PGP One thing to note is that Virtexll devices use DES in Cipher Block Chaining mode This means that each block is combined with the previous encrypted block for added security DES uses a single 56 bit key to encrypt 64 bit blocks one at a time This section is being updated mid March 2002 At this time only the Xilinx tools version 4 2 or a patched 4 1 03 support the encryption function of the Virtex devices There are
52. these the XC2V4000 contains 120 The embedded multi pliers offer fast efficient means to create 18 bit by 18 bit signed multi pliers The multiplier blocks share routing resources with the Block SelectRAM memory allowing for increased efficiency for many applica tions Cascading of multipliers can be implemented with additional logic resources of Virtexll slices 18 Kbit Block SelectRAM DIA DIPA ADDRA Port A ENB Figure 2 4 Dual Port Data Flows DN3000k10S User s Manual 2 5 DN3000k10S Features Overview and General Description 2 6 Issues Applications such as signed signed signed unsigned and unsigned unsigned multiplication logical arithmetic and barrel shifters two s complement and magnitude return are easily implemented We were surprised to find that the synthesis tools had no problem recog nizing multipliers in Verilog and VHDL So it appears that functional RTL is all that is necessary to use the embedded multipliers More on the synthesis issues in Synthesis and Emulation Issues on page 2 29 36 18 A B P MULT18X18 Figure 2 5 Embedded Multiplier Digitally Controlled Impedance is supported on all pins The resistors used for VRN and VRP are 51 1 ohms 1 The PWB impedance is 50 ohms So the Xilinx tools should be adjusted to reflect the fact that the reference resistors match the board impedance and NOT half the resistance of the reference resistors
53. uses the current phase shift which can be read back at offset 000D for DCLK 000F for FCLK to determine whether to increment or decrement the phase shift See Figure 5 12 DCM Basics The Virtexll datasheet has more information about using DCMs There are three functions of the DCM relevant to phase issues 1 De Skew The DCM may be used to de skew a clock signal by connect ing the CLKO or CLK2X outputs to the CLKFB input This connection is required for the other DCM functions and it must go through a clock buffer to achieve the correct timing for the de skew 2 Coarse Phase Shift Outputs CLK0 CLK90 CLK180 and CLK270 are phase shifted outputs of the same clock signal According to Xilinx s datasheet only four of the nine clock outputs may be used at once The reference design uses only CLKO See Figure 5 13 3 Fine Phase Shift Inputs PSEN and PSINCDEC can be used to phase shift all DCM outputs while running The phase shift is in units of of the clock period and according to the datasheet it is limited to no more than 2 5 ns in either direction from the de skewed clock See Figure 5 14 The DINI Group Memories CLKO CLKFB PSCLK DC PSEN DC PSEN Control PSINCDEC Logic PSDONE PSDONE zz Control Logic PSINCDEC DCLK FCLK Pad Pad Figure 5 12 DCM Connections in Reference Design CLKIN LJ LI L phase shifted www L LI same pha
54. with the input clocks The feedback clock divider function actually serves as a clock multiplication mechanism for the oper ating frequency The divider function and the clock skew function are set in the same manner for the feedback and the normal clock outputs See Clock Division on page4 11 and Clock Skew on page 4 12 respectively Clock Division pairs of DS inputs per chip are used to control the two groups of clock outputs and the feedback outputs of each PLL The user can simply follow the Divider Function Table to acquire the desired output frequency There are two things to remember First FS 2 1 must be set properly according to fNOM Second the FBDS feedback inputs act as operating DN3000k10S User s Manual 4 11 Clocks and Clock Distribution clock frequency multipliers The Output Divider Settings are shown in Table 4 5 Table 4 5 Output Divider Settings Input Signals Output Divider Function C fF DS1 and FBDS1 2 1 C F DSO and FBDSO 2 1 Feedback Output Signals Output Signals Clock Skew 4 12 Clock skew is controlled by the F inputs The clock skew may be any integer value from 0 to 8 times the Roboclockll time unit ty The time unit value is derived from the operating frequency fyoy and the FS 2 1 setting The following equation yields the time unit ty __1 The possible values for are given in Table 4 6 The available sk
55. 00000000 00000000 00000000 00000000 1 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Figure 9 10 AETEST Memory Display f forward pages the screen forward in memory b back pages the screen backwards in memory j jump jump to a specific location in hex 0 goto jump back to the original address location specified at the beginning d delay and display loop display wait for a second and dis play again Loop until a key is struck Write Memory Byte Write a specific number of bytes to a single memory address Figure 9 11 Input address byte to write byte to write Please select Numbers of long words to write 1 Display 2 Display 3 Don t display result and loop indefinitely 5000000 in decimal 2 hex hex SEE aa in in result result and loop indefinitely 9 12 Figure 9 11 AETEST Write Memory Byte You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 bytes will be written in sequential order to the same address A looping option is available if you want to use The DINI Group Utilities an oscilloscope If you are in a scope loop any keypress will terminate the loop and re
56. 00000000 4 00000000 5 00000000 Please select option Figure 9 3 AETEST Main Screen Options Read FPGA Revision Display the revision ID of the FPGA We will update the revision ID of the FPGA every time we change the reference design PCI Menu Display the PCI utilities menu Memory Menu Display the Memory Menu Flash Menu Display the FLASH Utilities Menu DN2000k10 series only Clock Menu Display the Clock Utilities Menu Dedicated Multiplier Test Execute the multiplier test Q Quit and return to the DOS prompt The selections are sometimes case sensitive so be aware of the status of the CAPS LOCK on your keyboard The base addresses for each of the configured BARS is displayed on all screens You will need these addresses if you want to manually read and write to address locations within the PCI reference design In this example Figure 9 3 above BARO is configured to OxFD800000 and BART is configured to 0xE0000000 BAR 5 2 are configured so they show up as 0x0 9 6 The DINI Group Utilities PCI Menu The AETEST PCI menu is shown in Figure 9 4 ASIC Emulator PCI Controller Driver v8 PCI Device Function Num Ox7F 0x00 S Set PCI Device Number F Set PCI Function Number D Display all Configured PCI Devices 1 Display Vendor and Device ID for PCI device function 7f 0 2 Loop on PCI device fun 7f 0 and Display Vendor and Device ID 3 Loop on PCI device fun 7f 0 and
57. 0100 000120 000140 000160 000180 0001a0 0001c0 0001e0 000200 000220 000240 000260 orward 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4 8 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 j ump goto 0 10 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 14 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
58. 1 2 3 2 5 2 28 XC2V6000 2 1 to 2 3 2 5 2 28 XC2V8000 2 1 2 3 2 28 XC95288XL 2 9 2 16 Index Continued 1 8 The DINI Group
59. 2 C21 _ HO N BRK1 z x 7 E 32114 E 00000000000 00000000000000 5 06 200 2 108 cas IS 2 10000000000000000 ere ba Tone C53 C54 1 1 1 um O 925 U9 J26 C68 GND E E LUE E 5 5 E U16 98 2 150 E 1 3 5 7 9 111315171921 23252729 31 33 WRRS 2 a1 20 19 2 b 28 18 Se lt 758 88 15 10 8 1 5 q HB AN o 2 4 6 8 10121416182022242628303234 54 I Bl 862 B63 A d BIEN LILILILI Figure 2 14 J27 RS232 Port Assembly Drawing 2 22 The DINI Group DN3000k10S Features Overview and General Description The RS232 port is configured with the following parameters Bits per second 9600 Data bits 8 Parity None Stop Bits 1 FLow control None Terminal Emulation VT100 We use the Windows based program HyperTerminal Hypertrm exe The configuration file DN3000k10S ht is supplied on the CD ROM or can be downloaded from our web page Users have the option of connecting the serial port if they wish to see any messages during the configuration process NOTE It is NOT mandatory to have the serial port connection in order to configure the FPGA in SelectMAP mode However if an error occurs during the configuration then without a serial port connection the user will not be
60. 2 21 serial port 2 14 to 2 15 2 23 to 2 25 Signals C F DS 4 10 4 12 uP SSRAM SRAMCS 1 4 2 16 UPADDR 2 16 ACLK 4 1 ADSC 5 7 5 9 ADSP 5 7 5 9 ADV 5 9 ALE 2 16 ATmega 128 uP BCPUCLK 2 18 CPUCLK 2 18 ATmega128 uP ALE 2 16 CPUCLK 2 16 RD 2 16 UPAD 2 16 UPADC 2 10 WR 2 16 BCLK 4 1 BCPUCLK 2 18 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 BWE 5 9 BWx 5 9 C_CCLK 2 16 2 19 C_DIN 2 16 2 19 C_DONE 2 16 2 19 C INIT 2 16 2 19 The DINI Group Index Continued _ 2 16 2 19 CCLK 2 19 2 21 4 13 CE 5 9 CE2 5 9 CLKOUT 4 1 4 3 to 4 4 Clock C F DS 4 10 4 12 ACLK 4 1 BCLK 4 1 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 CCLK 2 19 2 21 4 13 CLKOUT 4 1 4 3 to 4 4 CLOCKA 4 3 to 4 4 4 7 CLOCKB 4 3 to 4 4 4 7 DCLK 4 10 4 13 to 4 14 5 1 5 9 5 12 ECLK 4 13 FBDIS 4 10 to 4 11 FBDS 4 10 to 4 11 FBFO 4 10 4 13 FCLK 4 10 4 13 to 4 14 5 1 5 12 FS 4 10 to 4 12 4 14 INV1 4 14 INV2 4 10 4 14 MODE 4 10 PLL1A 4 3 to 4 4 4 10 PLLIB N 4 10 PLLIB PRE 4 3 to 4 4 PLLIBN PRE 4 3 PLL2B 4 13 to 4 14 PLL2B N 4 10 PLL2B PRE 4 3 to 4 4 PLL2BN 4 13 to 4 14 PLL2BN PRE 4 3 PLLSEL2 4 10 RB C F F 4 10 4 13 CLOCKA 4 3 to 4 4 4 7 CLOCKB 4 3 to 4 4 4 7 CPLD TCK 2 18 CPLD TDI 2 18 CPLD TDO 2 18 CPLD TMS 2 18 CPUCLK 2 16 2 18 CSF 2 16 D 2 16 DCLK 4 10 4 13 to 4 14 5 1 5 9 5 12 DINDOF 2 16 DONEF 2 16 DOUTBSY 2 19 DOUTBSYF 2 16 ECLK 4 13 DN3000k10S User s Manu
61. 37 21 CONNECTOR 404 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 OPTIONAL SAPS INSTALLED 2404 200 2330 7442 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 ON CONNECTOR 011 120 1 930 50 95 830 21 08 725 18 42 1 550 39 37 2 150 54 61 1 790 45 47 965 24 51 01 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 CAPS SUPPLIED 01 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 5 150 80 01 2 790 70 87 1 465 37 21 LOOSE 41 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 PIECE i 91294 413 200 2 930 74 42 1330 3378 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 NOTES 1 5 DIELECTRIC LCP CONTACTS PHOS BRONZE FRAME ZINC ALLOY 3 2 PLatine SOLDER TAILS 150 u 3 81um Sn Pb FRAME 150u 3 81um BRIGHT TIN CONTACTS 30u 76um OVER 50u 1 27um Ni OR 60u 1 52um OVER 75u 1 90um Ni 5 WHEN CONNECTOR 1 WITH OPPOSITE HALF THE PARALLEL BO TO BD IS 47 01 APPLYS TO VERT THRU amp SURFACE MT STYLES 5 THE SOLDER TAILS ON THIS PRODUCT ARE DESIGNED TO BE COMPLIANT IN ORDER TO ACCOMMODATE PRINTED CIRCUIT BOARD DIMENSIONAL VARIATIONS
62. 4 ns All adjustments are jumper selectable The clock grid J20 J22 gives the user the ability to customize the clock scheme on the DN3000k10S A brief description of each pin is given in Table 4 1 The physical orientation of the pins is diagrammed in Figure 4 2 Table 4 1 Clock Grid Signal Descriptions Signal Description CLKOUT Clock signal from CPLD Typically 12 MHz PLL1A Input to Roboclockll 1 CLOCKA Clock signal of oscillator 1 X1 BUFINB Clock input to 3807 1 CLOCKB Clock signal of oscillator 2 X2 PLL2B PRE Secondary clock input to Roboclockll 2 Differential pair with PLL2BN PLL2BN PRE Secondary clock input to Roboclockll 2 Differential pair with PLL2B PRE BUFINA Clock input to 3807 2 PLL1BN PRE Secondary clock input to Roboclockll 1 Differential pair with PLL1B PRE PLL1B PRE Secondary clock input to Roboclockll 1 Differential pair with PLL1BN PRE GND DN3000k10S User s Manual Ground signals to provide signal integrity for ribbon cables 4 3 Clocks and Clock Distribution Jumper Control for the Most Common 4 4 Applications b Figure 4 2 Clock Grid Three main configurations are the most common First the grid may be jumpered as follows Configuration 1 CLKOUT PLL1A CLOCKA lt gt BUFINA and CLOCKB lt gt BUFINB Both 3807s receive their inputs from the oscillators
63. 5 12 clock distribution 4 2 4 4 clock division 4 11 clock edge 2 5 clock enable 2 5 clock frequency multipliers 4 12 clock grid 4 1 4 3 to 4 4 4 6 clock input 4 4 4 6 4 10 4 13 8 7 Clock Menu 9 6 clock multiplication 4 11 clock multiplication mechanism 4 11 clock output 4 10 to 4 11 clock outputs 5 12 clock signals 7 6 clock skew 4 1 4 11 to 4 13 settings 4 13 Clock Utilities Menu 9 6 CLOCKA 4 3 to 4 4 4 7 CLOCKB 4 3 to 4 4 4 7 configuration 2 1 2 3 2 5 2 7 2 9 2 16 2 18 to 2 21 2 23 to 2 28 3 4 to 3 5 4 1 4 4 5 11 6 4 9 2 9 5 9 8 to 9 9 uP 2 9 bitstream 2 7 clock grid 4 4 expansion 3 5 FPGA 2 3 2 9 2 18 to 2 19 2 28 3 4 FPGA Serial Headers 2 19 JTAG 2 18 2 20 signals 2 16 stand alone 6 4 status 2 1 Index Continued via SelectMap 2 19 to 2 21 2 23 to 2 28 via SmartMedia 2 3 Configuration Pin Powerdown 2 21 configuration space 9 2 9 5 9 8 to 9 9 CPLD 2 1 2 3 2 14 2 16 2 18 to 2 19 2 28 4 1 4 3 to 4 4 6 2 8 1 8 4 CPLD_TCK 2 18 CPLD_TDI 2 18 CPLD_TDO 2 18 CPLD_TMS 2 18 CPUCLK 2 16 2 18 CSF 2 16 custom daughter cards 2 2 CY7B993V 4 11 to 4 12 4 14 D D 2 16 daughter card 2 2 6 5 7 1 to 7 4 7 7 to 7 8 8 5 8 7 9 2 custom 2 2 DCI 2 6 DCLK 4 10 4 13 to 4 14 5 1 5 9 5 12 DCM 5 12 to 5 13 debug 2 2 8 4 9 1 to 9 2 9 4 9 8 decryption 2 7 to 2 8 DES 2 1 2 7 Device ID 2 24 9 4 9 7 to 9 9 differential clocks 4 13 differential LVDS pairs 7
64. 6 Choose Other Devices from Hardware Types list and press The DINI Group Utilities 7 Click on Have Disk 8 In Copy Manufacturer s Files From window find the directory where q1driver sys is located then press OK 9 You should see dn2000k10 driver under Models click on Next 10 Press and then Finish 11 Run aetestnt exe Installation Instructions for LINUX This has been tested on Red Hat Linus 7 2 kernel version 2 4 x Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 You must be root to start the driver and the program dndev load and dndev unload are scripts that load and unload the driver dndev o is the driver file Load the driver type sh dndev load Unload the driver type sh dndev unload After driver is loaded run the utility aetest linux Note You might need to run chmod aetest_linux to make it executable type chmod u x aetest linux Installation Instructions for Solaris The utility and driver are tested on Solaris 7 0 Sparc with the 32 bit kernel Note that all the text files including the scripts are DOS text format with an extra carriage return character after every new line so you need to convert them 1 To install the driver go to the driver directory make sure the driver file dnde
65. 6 2 6 4 to 6 5 8 5 8 7 9 1 to 9 2 9 4 to 9 14 I 3 Index Continued clock 2 1 PCI bracket 8 5 PCI Bus 1 3 2 6 3 1 9 1 9 8 9 14 PCI card 3 1 9 1 PCI memory 9 9 to 9 13 PCI slot 3 1 3 4 6 1 6 4 8 7 PCI Specification 1 1 to 1 2 3 1 3 4 to 3 5 PCI X 1 2 to 1 3 2 1 to 2 2 2 6 3 1 3 3 to 3 7 PCIXCAP 3 6 to 3 7 PECL 4 13 phase shift 5 12 to 5 14 PLL 4 1 47 4 11 8 4 PLL Clock Buffers 4 1 PLL1A 4 3 to 4 4 4 10 PLL1B N 4 10 PLL1B PRE 4 3 to 4 4 PLL1BN PRE 4 3 PLL2B 4 13 to 4 14 PLL2B N 4 10 PLL2B PRE 4 3 to 4 4 PLL2BN 4 13 to 4 14 PLL2BN PRE 4 3 PLLSEL2 4 10 polarity 4 15 power 2 14 2 25 2 27 3 1 3 4 6 1 to 6 5 7 4 8 1 8 5 to 8 7 9 1 9 9 connector 2 1 distribution 3 1 power distribution 3 1 Power Down Status Pin 2 21 2 28 power management 1 2 Power Management Enable 3 5 power rails 6 1 to 6 5 8 5 power supply 2 29 5 9 5 11 6 2 to 6 5 7 4 to 7 5 8 6 to 8 7 power switch 9 9 power up 8 1 9 1 PROG 2 16 prototyping boards 7 1 7 6 to 7 7 PWB 1 1 2 1 to 2 3 2 6 2 16 2 18 to 2 19 3 1 6 2 8 5 R R W 5 9 RB 4 13 RB C F F 4 10 4 13 RD 2 16 4 RDYBUSY 2 16 regulator 2 1 3 1 6 2 reset button 2 26 to 2 27 RoboClock 5 9 Roboclock 2 1 4 1 4 3 to 4 4 4 6 to 4 8 4 13 to 4 14 5 12 6 2 8 4 Roboclockll 6 2 8 4 RST 3 4 9 1 5 SDRAM 2 26 to 2 27 5 1 5 9 to 5 12 6 2 6 5 9 2 9 13 security 2 7 Selectl O 7 1 SelectRAM 2 3 2 5 Serial Port
66. 64 DEVICE ID 2454 DEVICE ID 2e6c DEVICE ID c38c DEVICE ID ca76 DEVICE ID e6a Emulated with 8051 VENDOR ID 1243 DEVICE ID 4321 DEVICE ID sensor board VENDOR ID dead DEVICE ID beef LYNX 9610 VENDOR ID 10 5 DEVICE ID 9610 DEVICE ID 1240 vendor id 5045 vendor id abcd vendor id abcd vendor id abcd vendor id abcd vendor id abcd vendor id 1234 vendor id 1234 vendor id 11e3 vendor id 1010 vendor id 71f3 vendor id 507 vendor id bc92 vendor id e125 vendor id e62c vendor id 448b vendor id 1243 vendor id 5143 vendor id dead vendor id 10b5 device id 1 device id 1234 device id 1235 device id 1236 device id 1237 device id 1240 device id 5678 device id 5679 device id 6 device id 5064 device id 2454 device id 2367 device id 2e6c device id c38c device id ca76 device id e6a device id 4321 device id 2 device id beef device id 9610 Hit a key to continue Figure 9 2 AETEST Startup Screen No PCI Peripheral Recognized AETEST will still run but many DINI product specific options will not be available DN3000k10S User s Manual 9 5 Utilities AETEST Main The AETEST Main Screen is shown in Figure 9 3 Screen ASIC Emulator PCI Controller Driver v8 Read FPGA revision PCI Menu Memory Menu Flash Menu Clock Menu Dedicated Multiplier Test Quit PCI BASE ADDRESS 0 800000 1 e0000000 2 00000000 3
67. 67 P3N 57 GND GND GND GND P3N 56 P1N 10 PON 66 P3N 56 P3N 55 P1N 9 PON 65 P3N 55 P3N 54 P1N 8 PON 64 P3N 54 P3N 49 PON 59 P3N 49 P3N 48 PON 58 P3N 48 P3N 47 1 1 57 P3N 47 P3N 46 1 0 PON 56 P3N 46 P3N 43 P2N 91 PON 53 P3N 43 P3N 42 P2N 90 PON 52 P3N 42 P3N39 P2N 87 PON 49 P3N 39 GND GND GND GND P3N 38 P2N 86 PON 48 P3N 38 DN3000k10S User s Manual 7 9 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec tor Connections 123 123 124 724 J25 Pin P3N 35 P2N 83 PON 45 P3N 35 P3N 34 P2N 82 PON 44 P3N 34 P3N 29 P2N 77 PON 39 P3N 29 P3N 28 P2N 76 PON 38 P3N 28 P3N 27 P2N 75 PON 37 P3N 27 P3N 26 P2N 74 PON 36 P3N 26 P3N 23 P2N 71 PON 33 P3N 23 P3N 22 P2N 70 PON 32 P3N 22 P3N 19 P2N 67 PON 29 P3N 19 GND GND GND GND P3N 18 P2N 66 PON 28 P3N 18 P3N 15 P2N 63 PON 25 P3N 15 P3N 14 P2N 62 PON 24 P3N 14 P3N 9 P2N 57 PON 19 P3N 9 P3N 8 P2N 56 PON 18 P3N 8 P3N P2N 55 PON 17 P3N P3N P2N 54 PON 16 P3N P3N P2N 51 PON 13 P3N 3 P3N 2 P2N 50 PON 12 P3N 2 P4N27 P2N 47 PON 9 PAN 27 GND GND GND GND PAN 26 P2N 46 PON PAN 26 PAN 21 P2N 41 PON PAN 21 PAN 20 P2N 40 PON PAN 20 PAN 19 P2N 39 PON 1 PA
68. 6N 74 lt 731 lt 6 721 lt 71 lt 6 701 lt 69 lt 6 681 lt 677 E M A lt lt 6 65 lt 5 1221 lt 24 805425 A 26 P6N 93 E 6 9 E P6N 91 E P6N 90 E P6N 89 PONE css P6N 87 lt 6 86 lt 85 lt lt 83 lt 2 lt 81 lt 80 lt 781 lt 5 0 lt 5 lt 5 21 lt 5 lt 5 41 lt 5 5 lt 5 6 lt 5 71 lt 5 8 lt 5 91 lt 5 lt 5 11 lt 5 2 lt 5 13 lt 5 lt 5 1 lt 5 2 lt 5 lt 5 lt 5 5 i P5NI 6 P5N 7 E
69. 8 49 7 149 PONGO P3N47 50 7 150 P3N45 PINT 50 7 150 P2N93 PON57 50 7 150 PON55 P3N46 51 151 GND PINO 51 151 56 51 151 GND P3N43 52 152 3 44 P2N91 52 3152 P2N92 PONS3 52 152 P3N42 53 7 153 P3N41 P2N90 53 7 153 P2N89 0 52 53 7 153 PON51 GND a D TA P3N37 GND 24 14 P2N85 GND i TA 47 P3N38 56 156 P3N36 P2N86 5617 156 P2N84 PON4S 56 156 PON46 P3N35 57 A57 P3N33 P2N83 57 A57 P2N81 0 45 57 A57 P3N34 58 7 158 P3N32 P2N82 58 7 158 P2N80 PON44 58 7 158 PON42 P3N29 59 7 159 P3N31 P2N77 59 7 7 159 P2N79 PON39 59 7 159 41 P3N28 60 7 160 P3N30 P2N76 60 7 160 P2N78 PON38 60 7 460 PON4O P3N27 61 161 P3N25 P2N75 61 461 P2N73 PON37 61 161 5 P3N26 62 7 462 GND P2N74 62 7 462 GND PON36 62 162 GND P3N23 63 7 7 163 P3N24 P2N71 63 7 163 P2N72 PON33 63 7 7 463 PON34 GND GND GND P3Ni5 68 168 P3NT3 P2N63 68 168 P2N61 25 68 168 PONZ3 14 69 7 169 P3Ni2 P2N62 69 7 7 169 P2N60 PON24 69 7 169 PON22 P3N9 70 7 7 170 P3N11 P2N57 70 7 170 P2N59 PONTO 70 7 7 170 PON21 P3N8 7l 7 171 P3N10 P2N56 7i 471 P2N58 PONTS 71 PON20 P3N6 73 7 473 GND P2N54 73 7 473 GND PONT6 zl L4za3 GND P3N3 74 7 P3N4 P2N51 74 7 474 P2N52 PONT3 74 14_
70. AP mode You can also press the reset button S1 to reconfigure the FPGA in Select MAP mode 2 Interactive FPGA configuration menu This option takes you to a menu titled Interactive Configuration Menu and allows the FPGA to be configured through a set of menu options instead of using the main txt file The menu options are described below Description of Interactive Configuration Menu options 1 Select a bit file to configure FPGA s This menu option allows the user to select a bit file from a list of bit files found on the SmartMedia card to use to configure the FPGA 2 Set verbose level current level 2 This menu option allows the user to change the verbose level from the current setting Please note if the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt 3 Disable Enable sanity check for bit files This menu option either allows the user to disable or enable the sanity check depending on what the current setting is Please note if the user goes back to the main menu and configurest the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt The DINI Group DN3000k10S Features Overview and General Description M Main menu This menu option takes the user back to the Main Menu described above Check Configuration status This option checks the staus of the
71. Configuration Some Miscellaneous Notes on the CPLD X3 is a 48 MHz oscillator This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 8 MHz in the CPLD to provide the clock for the ATmega128L pP The processor clock signal is labeled CPUCLK and BCPUCLK on the schematic and may have note that describes the frequency as 4 MHz Initially we used ATmega103L instead of the ATmega128L The ATmega103L maximum frequency was 4 MHz The DINI Group DN3000k10S Features Overview and General Description The 48 MHz is used directly for the state machines in the CPLD for control ling the interface to the SmartMedia card The frequency of 48 MHz is interesting because it is the closest frequency to 50 MHz that can be divided by an integer to get 8 MHz The frequency 50 MHz is the fastest that the Xilinx Virtexll parts can be configured with SelectMap without wait states So FPGA configuration using SelectMap occurs at very nearly the fastest theoretical speed Serial and JTAG configuration of the Virtexll FPGA are back off positions only that is why those signals are connected to the CPLD Xilinx has a long history of botching the configuration method in new FPGA families so we made sure we had all possible options available If you want to use 100 of the CPLD and pP for your own purposes you can configure the FPGA using the JTAG cable The 48 MHz clock can be divided down in th
72. Connections to DN3000k10SD Observation Daughter Card for 200 pin Connec YSN Vk ber 52 1002 9 nous gt auvaa N31H9ny ODIO00 Na ESD SENSITIVE Bottom Figure 7 2 DN3000k10S Daughter Card DN3000k10S User s Manual Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors MADE IN USA DN3000K10 DAUGHTER BOARD THE DINI GROUP 2001 L Figure 7 3 Daughter Card LEDs Power Supply 7 4 o R2 aam mr 8 Jd HHH HH OH LI U3 WWW 02 mm C16 C19 621 2 i CCIC R6 N e e o o IDT74FST163245 chips are used as bus switches in the passive mode and the IDT74LVC16245A chips are used as bus transceivers in the active mode The DN3k10D1 has separate enable direction signals for each driver NOTE Availability of these I O signals depends on the location of the daughter card with respect to the development board The LEDs act as visual indicators representing the active power sources e D1 LED indicating 43 3 V present e D2 LED indicating 5 0 V present e LED indicating 12 V present Under normal operating conditions all LEDs should be on A linear power supply U4 is present to provide level shift translation functions when the board is populated with bus switches The DINI Group Daughter Connec
73. D AD58 AD60 GND AD62 PAR64 VIO 5 7 GND 5V 5V REQ64 VIO ADO AD2 GND AD4 AD6 DCAP1 C BEO GND GND AD9 GND AD11 AD13 DCAP2 AD15 PAR GND DCAP3 STOP GND TRDY GND FRAME DCAP4 AD16 AD18 GND AD20 AD22 DCAP5 IDSEL AD24 GND AD26 AD28 DCAP5 AD30 PME GND GNT RST 5V INTA 5V TDX 12V AG 45V 45V VIO ADOO A AD02 GND AD04 ADO6 3V C BEO ABO GND GND F GND 7 AD11 AD13 3V AD15 r GND 10 SBO SDONE 3V STOP A GND TRDY GND 3V AD16 A30 AD18 GND AD20 AD22 A 3V DSEL AD24 GND AD26 AD28 3V AD30 RSVD GND GNT Na VIO RST RSVD A10 RSVD e VIO RSVD 45V INTC INTA 45V TDI TMS 12V TRST SOLDER REQ64 FRAME B94 GND B GND AD33 AD35 VIO AD37 AD39 GND AD41 AD43 GND AD45 AD47 B 4VIO B78 AD49 B77 AD51 B76 GND B AD53 B74 AD55 B GND B AD57 B AD59 B70 VIO B69 AD61 B AD63 B GND B66 C BE4 B6 C BE6 B64 GND KEYWAY B6 5V EN B60 eter 858 01 GND Bss AD3 AD03 Bss ADS 005 asa DCAP1 53 A07 GND GND 850 N B ADIO AD12 B 12 C169 GND GND ADTA 0 01uF DCAP2 SEE B SERR ay DCAP2 Penn B40 PERR B LOCK R7 1M_43 3V
74. D28 AD34 AC34 AF29 AE29 W27 Y27 AC32 AB32 AB27 AA27 AA25 25 4 AD33 AC33 AD26 AE26 AA32 Y32 AC28 AB28 Y28 Y29 Y26 AA26 Y34 W33 w29 v29 AD29 2717 P7N 10 lt lt 7 8 lt 7 lt 7 6 lt 51 7 E M 7 lt 6 lt 5 lt 4 lt 7 lt 21 lt lt 0 lt 7 29 7 281 lt 2 gt lt 7 261 lt 25 lt 2 lt 23 lt 221 lt 21 lt 201 lt 6 lt 721 E 7 68 lt H 7 67 E 7 66 7 65 lt 7 E P7N 63 lt P7N 62 lt 61 lt 7 60 lt 591 lt 581 lt 7 5 lt 7 56 lt
75. E 5 V Signaling on Virtexll parts causes them to smoke This is quite BAD Do NOT modify the DN3000k10S board to fit into your PCI sxlot PCI Mechanical 105 is not a standard sized PCI card it is too tall The board Specifications is compliant to the PCI specification for the length 12 25 inches long but it is 5 25 inches high This is sometimes an issue in servers that have a bracket installed over the top of the PCI cards If you need to close the case on a DN3000k10S most tower configurations should work Figure 3 3 shows the exact dimensions of the DN3000k10S Some Notes power is not needed on the host PCI connector 43 3 V power is on the derived from 5 V using an on board 5 A liner regulator Power distribu tion for the DN3000k10S is described in Power Supplies and Power Distri DN3000K10S bution on page 6 1 and PCI PCI X LOCK has a pull up This is technically a violation of the PCI specification but we have seen systems from SUN that have the pin floating DN3000k10S User s Manual 3 1 PCI 3 2 FPGA U16 AN27 AP26 AN24 AP24 AN23 AH23 AJ22 AJ19 AL16 AK14 AN14 AN13 AP14 AK13 AP13 AJ13 AJ11 AM8 AL12 AN12 AM9 AJ12 AL11 14 7 6 9 5 4 4 AM2 AJ14 AP12 AM12 AP7 16 15 19 17 118 AJ18 8 2 AJ16 AL19 AM19 AN11 113 11 AM13 AP11 5 AL1 AM33 AN32
76. G GW 5 9 H heat sink 6 2 HyperTerminal 2 15 2 23 Impedance 2 6 impedance 2 6 INITF 2 16 2 19 input clock 4 10 input clock select 4 10 Interconnect 9 2 interconnect 2 1 5 2 7 8 8 7 9 2 INV1 4 14 INV2 4 10 4 14 IOATTRIBUTE 2 6 J JTAG 2 2 2 8 to 2 10 2 12 2 14 2 16 2 18 to 2 20 2 25 3 4 JTAG clock 2 20 jumper 4 15 jumper definitions 4 9 to 4 10 jumper settings 2 25 4 15 L LD 5 9 LED 2 26 7 4 8 3 to 8 4 LOCK 2 19 LOCK 3 1 LOCK N 2 16 2 19 logic analyzer 2 2 2 20 LTC1326 8 1 DN3000k10S User s Manual Index LUT 23 LVCMOS33 2 6 LVDS 2 7 7 1 7 6 8 6 M M 2 16 M66EN 3 5 3 7 main configuration file 2 23 see also main txt main txt 2 20 2 23 to 2 27 8 1 MBCK 8 7 MDR 7 6 memories 2 2 2 5 2 30 5 1 5 12 8 5 to 8 7 9 13 to 9 14 microprocessor 2 1 2 3 2 9 6 2 see also uP MODE 4 10 mounting holes 8 5 multiplexers 2 3 2 11 multiplexing 2 1 5 9 Multiplication 4 11 multiplication 2 6 4 11 multiplier 2 5 multiplier blocks 2 5 oscillator 2 1 2 18 4 1 4 3 to 4 4 4 7 4 11 4 14 to 4 15 6 2 oscillators 2 1 4 1 oscilloscope 7 1 8 4 to 8 5 9 8 9 10 9 13 to 9 14 output divider function 4 10 4 12 output mode 4 10 output phase function 4 10 output enable 7 7 P2NX6 2 16 2 19 P3N 2 16 2 19 2 16 2 19 pattern 2 2 8 5 pattern generator 2 2 8 5 PCI 1 1 to 1 3 2 1 to 2 2 2 6 3 1 3 4 to 3 7 6 1 to
77. I Special Interest Group 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 503 693 8344 1 1 Getting Started As of October 2001 the most current versions of the PCI Specifications are PCI Local Bus Specification Revision 2 2 PCI Hot Plug Specificadtion Revision 1 0 PCI Power Management Interface Specification Revision 1 1 PCI X Addendum to the PCI Local Bus Specification Revision 1 0a Other recommended specifications include PCIMG 2 0 Compact PCI Specification Revision 2 1 or greater PCI Industrial Computer Manufacturers Group PICMG 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1100 FAX 781 224 1239 http www picmg org The best book to get if you need an introduction to PCI is PCI System Architecture Fourth Edition MindShare Inc Tom Shanley and Don Anderson Ignore some of the ignorant statements made in the Customer Review section at http www amazon com This is an excellent book for PCI and well worth the money The best book to get if you need an introduction to PCI X is PCI X System Architecture MindShare Inc Tom Shanely and Karen Gettman You are going to need to know Verilog or VHDL to use the Virtexll FPGA If you need a reference we recommend the following book for Verilog Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar ISBN 0 13 451675 3 If you are one of those people that actually like VHDL we feel sorry for you The follow
78. L1BN and in clocks PLL2B and PLL2BN PECL ready boards cannot function without the cable except as in options 3 and 4 above Figure 4 5 External Ribbon Cable Connections Roboclocklil PLL Clock Buffers Figure 4 6 is a functional diagram of Roboclockll 1 and Roboclockll 2 Jumper Descriptions Headers J5 through J16 are used to control the PLLs The headers are grouped in sets of three Of the groups of three one header consists of GND pins One consists of various PLL inputs The final header consists of 3 3 V pins The layout of the headers is shown in Figure 4 7 DN3000k10S User s Manual 4 7 Clocks and Clock Distribution ROBOCLOCK1 Control Logic Frequency Divide and Phase Clock Detector Generator Selection Matrix Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix Divide and Phase select Matrix ROBOCLOCK2 1051 PLLSEL2 E MODE1 Duplicate of Clock A gt gt arao See details above gt Phase select LK Matrix 4F0 3 FS1 Aj E Divid d 1 INR lt Divide an 1 EKI 4DS0 gt Phase select 71 40814 gt Matrix FBDSO1 FBDS11 idi gt oF Divide and FS2 Y 3050 5 Phase select 1 1 435 Matrix 3 INV3 i B E 2Fo 35 2F1 ES Divide and Phase select
79. LE 2X Lese ses wee HAHN __ 3 4 95 1 1 5 B sheet index form no 7530 001 103 112 The DINI Group Figure A 3 Berg 91294 003 Datasheet Page 1 of 3 A 4 PRODUCT NO Berg Connector Datasheets Droits de reproduction BERG ELECTRONICS INC Tous droits strictement reserves Reproduction ou communication a des tiers interdite sous quelque forme que ce soit sans autorisation ecrite du propietaire Propriete de C BERG ELECTRONICS ELECTAONICS All rights strictly reserved Reproduction or issue to third parties in form whatever is not permitted without written authority from the proprietor Property of BERG ELECTRONICS Copyright BERG ELECTRONICS INC TABLE 000 0 0 0 050 91 27 0 110 82 79 REF ex 0 220 5 58 REF 2 FRAME TO BOARD CONTACT AREA 0 075 1 91 REF 2X 0 160 4 06 REF 0 052 1 33 2X REF form no 7530 001 105 100 2 54 REF 1000 0000000000000000000000000000000000000 90 045 01 14 005 0 08 000 0 0 m 160 4 06 090 2 29 025 0 64 050 1 27 h TYP FULL R TYP 410 10 41 002 05 015 0 38 001 0057 13 TYP PROPOSED TERMINATION REQUIREMENTS 010 25 0 010 001 25 03 DIM REF KEY SIDE BOTTOM VIEW mat l code tolerances unless otherwise
80. N 19 PAN 18 P2N 38 PON O PAN 18 PAN 13 P2N 33 PONX 9 PAN 13 PAN 12 P2N 32 8 PAN 12 PAN 11 P2N 31 PONX 7 PAN 11 PAN 10 P2N 30 6 PAN 10 7 10 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec tor Connections 123 123 J24 J24 or J25 Pin No P2N 27 PONX 3 GND GND P2N 26 PONX 2 3 P2N 23 P1NX 13 3 PAN 2 P2N 22 P1NX 12 PAN 2 PANX 11 P2N 17 P1NX 7 PANX 11 1 5V 1 5V 1 5 1 5V PANX 10 P2N 16 PANX 10 PANX 7 P2N 13 PANX 10 PANX 6 P2N 12 PANX 6 PANX 5 P2N 11 PANX 5 4 P2N 10 4 EN o c rn A St ECLK 1 FCLK 4 ECLK 4 ECLK 1 e e e e e e e e P2N 5 P1N 73 P7N 51 P2N 5 P2N 4 P1N 72 P7N 50 P2N 4 P2NX 11 P1N 67 P7N 45 P2NX 11 P2NX 10 P1N 66 P7N 44 P2NX 10 P2NX 9 P1N 65 P7N 43 P2NX 9 P2NX 8 P1N 64 P7N 42 P2NX 8 DN3000k10S User s Manual 7 11 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec to
81. Open No expansion board present Ground Open Expansion board present 25W maximum Open Ground Expansion board present 15W maximum Ground Ground Expansion board present 7 5W maximum We have never seen the present signals ever used but we have heard of systems that will not PNP Plug and Play configure a PCI board if both the present pins are left open We recommend installing a jumper in location 1 2 for PRSNT2 or 5 6 for PRSNT1 or both J31 M66EN 66MHz Enable Pins 7 8 The 66 27 ENABLE pin M66EN indicates to the host whether the device can operate at 66 MHz or 33 MHz Section 7 5 1 in the PCI Specification 2 2 provides the gory details For 33 MHz only FPGA designs install a jumper between pins 7 and 8 For 66 MHz capable designs leave this jumper unin stalled Table 3 2 shows the jumper descriptions for M66EN Table 3 2 M66EN Jumper Descriptions Busen _ Installed Uninstalled J31 PME Power Management Enable Pin 3 This board does not have built in support for PME power management enable Connecting PME to an FPGA that is not powered is a bad idea DN3000k10S User s Manual 3 5 PCI 3 6 PCIXCAP R54 10k Figure 3 5 PCI X Capability Header the system powers up as the board is installed PME is connected to pin 3 of J31 This header pin allows the user to connect external circuitry to PME if this functionality is desired J30 PCI PCI X Capabi
82. P3N 44 1 P2N 89 PON 51 41 40 P2N 88 PON 50 40 37 P2N 85 PON 47 P3N 37 P3N 36 P2N 84 PON 46 P3N 36 P3N 33 P2N 81 PON 43 P3N 33 P3N 32 P2N 80 PON 42 P3N 32 P3N 31 P2N 79 41 P3N 31 P3N 30 P2N 78 40 P3N 30 P3N 25 P2N 73 PON 35 P3N 25 GND GND GND GND P3N 24 P2N 72 PON 34 P3N 24 P3N 21 P2N 69 PON 31 P3N 21 P3N 20 P2N 68 PON 30 P3N 20 P3N 17 P2N 65 PON 27 P3N 17 P3N 16 P2N 64 PON 26 P3N 16 P3N 13 P2N 61 PON 23 P3N 13 P3N 12 P2N 60 PON 22 P3N 12 P3N 11 P2N 59 PON 21 P3N 11 P3N 10 P2N 58 PON 20 P3N 10 P3N 5 P2N 53 PON 15 P3N 5 D GND GND D P2N 52 PON 14 P2N 49 PON 11 P2N 48 PON 10 DN3000k10S User s Manual 7 13 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Connectors Table 7 2 DN3000k10SD Daughter Card I O Interconnects DN3000k10 I O Connec tor Daughter Card Connections 123 123 124 124 J25 Pin No PAN 25 P2N 45 PON 7 PAN 25 PAN 24 P2N 44 PON 6 PAN 24 P4N23 P2N 43 PON 5 PAN 23 PAN 22 P2N 42 PON 4 PAN 22 PAN 17 P2N 37 PONX 13 PAN 17 PAN 16 P2N 36 PONX 12 PAN 16 PAN 15 P2N 35 PONX 11 PAN 15 GND GND GND GND PAN 14 P2N 34 PONX 10 PAN 14 PAN 9 P2N 29 PONX 5 PAN 9 PAN 8 P2N 28 PONX 4 PAN 8 P2N 25 PONX 1 P2N 24
83. RIC LCP CONTACTS BeCu FRAME ZINC ALLOY 3 2 PLATING SOLOER TAILS 150u 3 81um Sn Pb FRAME 150u 3 8tum BRIGHT TIN CONTACTS 0 7 OVER 50u 1 27um Ni OR 60u 1 52um GXT OVER 75u 1 90um 0 WHEN THE CONNECTOR IS MATEO WITH THE OPPOSITE HALF THE PARALLEL BD TO 8D IS 47 01 APPLYS TO VERT THRU amp SURFACE MT STYLES THE SOLDER TAILS ON THIS PRODUCT ARE DESIGNED TO BE COMPLIANT IN ORDER TO ACCOMMODATE PRINTED CIRCUIT BOARD DIMENSIONAL VARIATIONS THEREFORE HOLODOWN HARDWARE IS REQUIRED TO SECURE THE CONNECTOR TO THE PRINTED CIRCUIT BOARD FOR MOST TYPES OF SOLDER REFLOW OPERATIONS FOR FURTHER APPLICATION DATA INCLUDING HOLE SIZES FOR VARIOUS TYPES OF HARDWARE SEE 932 8 DO NOT REMOVE PROCESSING CAP UNTIL SOLDERING 15 COMPLETED CAP WILL PREVENT POTENTIAL NOSE PIECE BOW DURING HIGH TEMP SOLDERING PROCESS BERG ELECTRONICS projection MICROPAX 025M SMT THoUTZ 3 8 95 RECEPT SINGLE MODULE revision sheet cage code 22526 Figure A 2 Berg 91403 003 Datasheet Page 2 of 2 A 3 DN3000k10S User s Manual Tous droits strictement reserves Reproduction ou communication des tiers interdite sous quelque forme que soit sans oulorisation ecrite du propietaire All rights strictly reserved Reproduction or issue to third parties in any form Berg Connector Datasheets
84. THEREFORE HOLDDOWN HARDWARE IS REQUIRED TO SECURE THE CONNECTOR TO THE PRINTED CIRCUIT BOARD FOR MOST TYPES OF SOLDER REFLOW OPERATIONS FOR FURTHER APPLICATION DATA INCLUDING HOLE SIZES FOR VARIOUS TYPES OF HARDWARE SEE TA 932 DO NOT REMOVE PROCESSING CAP UNTIL SOLDERING 15 COMPLETED BY ADDING LETTER H 10 IABULAIED P N THE OPTIONAL HOLD DOWNS WILL BE SUPPLIED INTEGRAL W CONNECTOR EXAMPLE XXXXX XXXH HOLD DOWN code tolerances unless otherwise specified CUSTOMER RE RG tr ecn no dr dote Xx to ELECTRONICS XR i009 La MICROPAX 025M SMT ___ EU d LN THOUTZ 3 4 93 INCH MM product family MICROPAX en MHAHN 3 4 93 ze dwg no cz m NT TUN n sheet revision index sheet form no 7530 001 103 cage 22526 The DINI Group Figure A 5 Berg 91294 003 Datasheet Page 3 of 3 A 6 Glossary and Acronyms ASIC AVCC BAR BGA BIOS CLB CMOS DCI DCM DES DIMM EEPROM EIA ESD FAQ FAT FIFO FPGA FT GND HDL y o IDC IP LED LSI microprocessor analog to digital Analog Voltage Reference application specific integrated circuits Analog Vcc Base Address Register ball grid array Basic Input Output Services configurable logic block complementary metal oxide semiconductor digitally controlled impedance Digital Clock Manager data encryption standard dual in
85. a mechanical datasheet for both the Berg 91403 003 and 91294 003 connectors This style of connector has four mounting holes two screw holes at each end and two alignment holes between pins 50 51 and after pin 100 see Figure 8 5 These mounting holes are part of the metal shell of the connector and make an important connection to the mating connector All four of these mounting holes are connected to digital ground on the DN3000k10S therefore the shell of the connector is grounded We used the pin numbering shown in Figure 8 5 for the 200 pin 91294 003 connectors The Signals Each of the three 200 pin connectors has the following 162 signals connected to the FPGA All 162 are connected to the FPGA subset of the 162 are also connected to the memories e 7 clocks The following power rails 12V 1 pin 12V 1 pin 5V 2 pins 43 3V 2 pins 41 5V 2 pins GND 23 pins case DN3000k10S User s Manual 8 5 Reset Schemes LEDs Bus Bars and 200 Pin Connectors Regarding the amount of current that the power pins can carry the following text is lifted directly from the specification for the Micropax family of connectors 6 1 Current Rating Current rating shall be evaluated in still air at 25 C ambient temperature Under the following conditions the temperature rise shall be no greater than 30 All contacts powered at 0 5 amp One contact powered at 3 0 amps Most of the signa
86. ach external TTL signals to these pins the voltage level of these signals must not exceed 43 3 V The J3 schematic is shown in Figure 2 9 ATmega128L JTAG Interface The ATMega128L processor has a JTAG interface that can be used for on chip debugging real time emulation and programming of FLASH EEPROM fuses and Lock Bits In order to take advangtage of the JTAG interface you must hav ethe Atmel AVR JTAG ICE kit part number ATAVR JTAGICE and AVR studio software that Atmel provides free at www atmel com The JTAG interface for the ATmega128L can be accessed through four pins TCK TMS TDO and TDI on header J4 of the DN3000k10S see Figure 2 10 The DINI Group DN3000k10S Features Overview and General Description SMCD SMWP1 UP5 UP7 UPINT5 UPINT6 BRXD UPINT7 BTXD 55 1 3 5 7 9 1 1 1 GO 0 JMPRO HDR10X2 JMPR1 JMPR2 UPINT5 UPINT6 UPINT7 g Figure 2 9 J3 Unused pP Connections 1 3 5 HDR10X2 Figure 2 10 ATmega128L JTAG Interface DN3000k10S User s Manual PDO INTO PD1 INT1 PD2 INT2 PD3 INT3 PD4 IC1 PD5 PD6 T1 PD7 T2 PEO PDI RXD PE1 PDO TXD PE2 AC PE3 AC PE4 INT4 5 5 6 6 PE7 INT7 2 13 DN3000k10S Features Overview and General Description Programming ATmega128L the U6 A cable used to reprogram the ATmega128L is shipped with the DN3000k10S You will need to reprogram the ATmega128L if we update the co
87. al Index FBDIS 4 10 to 4 11 FBDS 4 10 to 4 11 FBFO 4 10 4 13 FCLK 4 10 4 13 to 4 14 5 1 5 12 FPGA C CCLK 2 16 2 19 C DIN 2 16 2 19 C DONE 2 16 2 19 INIT 2 16 2 19 PROG 2 16 2 19 CSF 2 16 D 2 16 DINDOF 2 16 DONEF 2 16 DOUTBSY 2 19 DOUTBSYF 2 16 FWRTSM 2 16 INITF 2 16 2 19 M 2 16 P2NX6 2 16 2 19 P3N 2 16 2 19 PAN 2 16 2 19 PROG 2 16 FPGA JTAG FTCK 2 16 2 20 FTDI 2 16 2 20 FTDO 2 16 2 20 FTMS 2 16 2 20 FS 4 10 to 4 12 4 14 FTCK 2 16 2 20 FTDI 2 16 2 20 FTDO 2 16 2 20 FTMS 2 16 2 20 FWRTSM 2 16 GW 5 9 INITF 2 16 2 19 INVI 4 14 INV2 4 10 4 14 LD 5 9 LED 2 16 LOCK 2 19 LOCK 3 1 LOCK_N 2 16 2 19 M 2 16 MBCK 8 7 MODE 4 10 P2NX6 2 16 2 19 P3N 2 16 2 19 P4N 2 16 2 19 PCIJTAG CPLD_TCK 2 18 1 5 Index Continued CPLD_TDI 2 18 CPLD_TDO 2 18 CPLD_TMS 2 18 TCK 2 12 2 20 3 4 TDO 2 12 2 20 3 4 TMS 2 12 2 18 2 20 3 4 TRST 3 4 PCI JTAG Signals TDI 2 12 2 20 3 4 PCI Signals ADSC 5 7 5 9 ADSP 5 7 5 9 ADV 5 9 BWE 5 9 BWx 5 9 CE 5 9 CE2 5 9 GW 5 9 LD 5 9 LOCK 2 19 LOCK 3 1 R W 5 9 RST 3 4 9 1 PLL1A 4 3 to 4 4 4 10 PLLIB 4 10 PLLIB 4 3 to 4 4 PLLIBN PRE 4 3 PLL2B 4 13 to 4 14 PLL2B N 4 10 PLL2B PRE 4 3 to 4 4 PLL2BN 4 13 to 4 14 PLL2BN_PRE 43 PLLSEL2 4 10 PROG 2 16 R W 5 9 RB C F F 4 10 4 13 RD 2 16 RDYBUSY 2 16 RST 3 4 9 1 SMALE 2 16 SmartMedia Card RDYBUSY 2 16 MALE 2 16
88. ast for 5 years or so and FPGA Configuration The DN3000k10S has an ATmega128L microprocessor uP that is used to control the configuration process U6 The amount of internal SRAM 4 Kbytes was not large enough to hold the FAT needed for SmartMedia so an external 32 k x 8 SRAM was added The address latching function is done in the XC95288XL CLPD U5 The microprocessor has the following responsibilities e Reading the SmartMedia card e Configuring the Virtexll FPGA e Executing DN3000k10S self tests Other than FPGA configuration the uP has no responsibilities Less than 25 of the 128 Kbytes of FLASH is used for FPGA configuration and utili ties so you are welcome to use the rest of the resources of the for your own purposes Instructions for customizing the pP are contained in the file Custom Atmegal28L pdf This file is on the CD ROM or it can be down loaded from the DINI Group web page REMEMBER You can use the microprocessor for your own purposes We ship a programming cable for the ATmega128L with the DN3000k10S Updates to the code will be posted on our web site If you wish to do your own development you will need the compiler which we do not ship with the product The compiler is available from IAR http www iar com The part number is EWA90PCUBLV 150 Note that if you are willing to program the FPGA with the JTAG or serial cable the CLPD and the pP have no function In this case you can use all
89. check on bit files before copying them onto the Smart Media card This PC bit file sanity check verifies that the right version of Xilinx tools was used and the bitgen options have been set correctly To run the sanity check from the command line sanityCheck f fpga bit d s Command line options e The f option is required and must be followed by the name of the bit file to perform the sanity check on The d option is optional It prints out a description of the differ ent bitgen options and their different values e s option is optional It prints out the current bitgen settings found in the file specified with the f option Expected output DN3000k10S User s Manual e Ifthe bit file passes the sanity check you should see something similar to sanityCheck f fpga sm bit Performing Sanity Check on File fpga sm bit 2 27 DN3000k10S Features Overview and General Description DATE 2001 10 01 TIME 10 47 01 PART 2V6000ff1152 FILE SIZE 2470068 bytes ALL BITGEN OPTIONS ARE SET CORRECTLY e If the bit file does not pass then a message stating why it didn t pass will print out For example sanityCheck f fpga sm bit Performing Sanity Check on File fpga sm bit DATE 2001 10 01 TIME 10 47 01 PART 2v6000ff1152 FILE SIZE 2470068 bytes ERROR PowerDown status pin is enabled you must disable this option to configure the FPGA in SelectMAP mode SmartMedia
90. ctive device This option is for advanced users only The memory menu Figure 9 5 allows you to perform a variety of tests of PCI memory along with some DN3000k10 specific tasks 1 3 8 9 a b c f g n u M 0 2 2 ASIC Emulator PCI Controller Driver v8 Write To Memory Test Write Read Test Memory Display Write Memory Byte Read Memory Byte Write Read Memory Byte memory test on SSRAM 1 memory test on SSRAM 2 memory test on SSRAM 3 memory test on SDRAM full memory test including blockram memory test on FPGA block memory bar memory range test SRAM memory test Main Menu Q Quit 2 Read Memory Test 4 Memory Fill PCI BASE ADDRESS 00000 1 0000000 2 00000000 00000000 4 00000000 5 00000000 Figure 9 5 AETEST Memory Menu DN3000k10S User s Manual 9 9 Utilities Write to Memory Test Write a selected number of long words to a specific memory location Figure 9 6 Numbers Memory location hex b000000 long word to write in hex aaaaaaaa long word to write in hex 55555555 Loop indefinitely y or n Hit a key to continue of long words to write in decimal 2 Figure 9 6 AETEST Write to Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be accessed A minimum of 1 to a maximum of 1024 long words can be w
91. d STK500 correct the situa tion and then select TOOLS gt STK500 AVRISP JTAG ICE again You will not be able to continue unless you see something very similar to the following at the bottom fo the STK500 window The DINI Group DN3000k10S User s Manual DN3000k10S Features Overview and General Description Detecting AVRISP found on COMI Getting revisions HW 0x01 SW Major 0x01 SW Minor 0x07 0K On the PROGRAM tab select the ATmega128 under the DEVICE drop down menu and in the FLASH section where it says INPUT HEX FILE browse and select the file DN3000k10S 128 90 that can be found in the downloaded zip file uP_CPLD zip from the Dini Group web site To program the device all you need to do is hit the PROGRAM but ton in the FLASH section When the programming is complete it takes about 45 seconds you should see a message at the bottom of the window that looks something like this Detecting AVRISP found on COMI Getting revisions HW 0x01 SW Major 0x01 SW Minor 0 07 Reading FLASH input file OK Setting device parameters serial programming mode OK Entering programming mode OK Erasing device OK Programming FLASH using block mode 100 OK Leaving programming mode OK After programming the processor close all AVR Studio windows and setup the serial port according to the section titled Setting up the Serial Port 127 RS232 Port on page 2 21 Please note that in this situation connecting the
92. d behavior If REGE is high the control signals will go through registers before being sent to the individual DRAMs delaying access by one clock cycle but improving fanout if it is low the signals will be passed directly to the DRAMs The 1 GB SDRAM module shipped as part of the package is affected by both J18 and J19 i e its EEPROM is connected to the WP input and it can be configured for Registered or Non Registered behavior SSRAM1 and the SDRAM run on DCLK SSRAMs 2 and 3 run on FCLK Both clocks use an internal digital clock manager DCM in the reference design to reduce skew There is also a phase shifter in the reference design but all memories should run at the default phase shift for frequencies up to 120 MHz note however that Roboclock CY7B993 is not rated for frequencies over 100 MHz To change the DCM phase shift by one step 156 of the clock period PSEN must be high for one cycle of the PSCLK input The phase will be shifted forward if PSINCDEC is high or backward if it is low PSDONE goes high for one cycle to indicate that the shift is finished and PSEN must remain low until it does The reference design s control logic uses 8 bit registers to store phase shift information The decimal number 128 or hex 80 represents a phase shift of 0 i e the point at which the clock is de skewed The user may write a new number to an address in BARO hexadecimal offset 000C for DCLK 000E for and the control logic
93. de or you intend to use the processor for your own application J29 is used for this purpose Figure 2 11 illustrates J29 HDR5X2 Figure 2 11 J29 Schematic Detailed Instructions 1 Download the latest update for the processor and CPLD at www dini group com fileuP CPLD zip You will first need to reprogram the CPLD Please see CPLD XC95288XL 2 16 instructions use the file DNk10S CPLD jed that can be found in the downloaded zip file Next you will program the processor ATmetga128L Connect the AVR cable that was shipped with the DN3000k10S to header J29 with the red purple wire on the cable connected to pin 1 and connect the other end to the serial port of your PC In order to program the processor you will need to install AVR Studio that is included on the Atmel CD that was shipped with the DN3000k10S This software can also be downloadted at www atmel com From the Windows START menu choose PROGRAMS gt Atmel AVR Stu dio x xx where x xx is the version number Once AVR Studio is open select TOOLS gt STK500 AVRISP JTAG ICE and a new window should appear with the title STK500 At the bottom of the STK500 window if you see Detecting FAILED that means either there is no power on the DN3000k108 there is another program open that is using the serial port or the serial cable connecting the AVR tool is not connected properly If this happens you should close down the window title
94. e VREF reference voltage ZBT zero bus turnaround 2 Xilinx Intellectual Property Solutions Index Symbols C F DS 4 10 4 12 2 9 to 2 10 2 12 to 2 13 2 16 2 18 to 2 19 2 28 8 1 9 1 see also microprocessor A ACLK 4 1 ADSC 5 7 5 9 ADSP 5 7 5 9 ADV 5 9 AETEST 9 1 to 9 2 9 4 to 9 7 9 9 to 9 13 ALE 2 16 ASIC 2 1 to 2 2 2 30 4 1 5 1 7 1 7 6 to 7 7 asic 4 1 ATMega128L 2 13 ATmega128L 2 1 2 9 to 2 10 2 12 Atmega128L 2 9 battery 2 1 2 7 to 2 9 BCLK 4 1 BCPUCLK 2 18 Berg connector 8 5 A 1 BIOS 9 1 9 9 bitgen options 2 21 2 23 to 2 24 2 27 to 2 28 bitstream encryption 2 1 2 7 BIockRAM 2 26 to 2 27 7 1 9 13 to 9 14 Blockram 7 1 board termination voltage 2 6 Bridges2silicon 2 20 BUFINA 4 3 to 4 4 4 6 BUFINB 4 3 to 4 4 4 7 BWE 5 9 BWx 5 9 C C CCLK 2 16 2 19 C DIN 2 16 2 19 C DONE 2 16 2 19 C INIT 2 16 2 19 C PROG 2 16 2 19 DN3000k10S User s Manual Index carry chains 2 3 CCLK 2 19 2 21 4 13 CE 5 9 CE2 5 9 Certify TDM 2 1 ChipScope ILA Logic Analyzer 2 20 Cipher Block Chaining 2 7 CLB 2 3 CLKOUT 4 1 4 3 to 4 4 clock 2 1 2 5 2 16 2 18 to 2 20 3 1 4 1 4 6 4 11 to 4 12 5 7 5 12 7 6 8 6 to 8 7 clock multiplication mechanism 4 11 differential clocks 4 13 feedback clock divider function 4 11 startup clock 2 21 clock arrays 2 30 clock buffer 4 1 4 7 5 12 clock buffers 4 1 4 13 5 12 6 2 clock configurations 4 5 clock cycle 5 7 to 5 8
95. e CPLD and used to drive the PWB clock network See Chapter 4 for a more detailed description of this option The signals P3N 91 90 P4N 29 3 and P2NX6 are spare connections between the CPLD and the FPGA INITF and DOUTBSY are used by the CPLD and the uP for self test purposes when the FPGA is configured with our reference design LOCK N 2 1 are the logical invert of LOCK 2 1 The lock LEDs should go on when the respective Roboclockll PLLs are locked Notes on Header J1 SelectMap using the SmartMedia card is the best way to configure the FPGA Two other options exists if for some reason the SmartMedia media method is not working 1 Serial Programming Using the Cable Header J1 has the 5 serial connections that are used to configure the FPGA using the serial method Table 2 4 has the pinouts Note that this is a back off position to SmartMedia and JTAG and should only be used in dire circumstances Note also that header J1 will need to change to reflect slave serial configuration Table 2 2 FPGA Serial Configuration Header Name on Schematic Cable Color Header Pin yellow blue green orange none DN3000k10S User s Manual 2 19 DN3000k10S Features Overview and General Description SelectMAP Configuration 2 20 Instructions Table 2 2 FPGA Serial Configuration Header Name on Schematic Cable Color Header Pin 71 5 J1 17 71 19 71 21 71 6 71 24 71 1
96. e power and temperature so you can use typical commercial timing NOTE In a lab environment the FPGA never sees the worst case temper ature and power You can use typical commercial timing Header J17 Off Board Power J17 is a power header A standard IDC cable can be attached to this header and is useful for providing power to other circuits that may be attached to the DN3000k10S This header is not keyed and the signals are not fused so make sure you get pin 1 in the correct location putting a cable on this header incorrectly will cause lots and lots of damage All the power rails are on this connector 12 V 12 V 41 5 V 5 V and 3 3 V The 0 25 pins on this header are rated at more than the 3 A per pin so the cable probably limits the amount of power that you can get from this header We did not intend for this connector to provide the power to the DN3000k10S so don t use it for that purpose J17 Power Header is shown in Figure 6 2 DN3000k10S User s Manual 6 3 Power Supplies and Power Distribution HDR10X2 Figure 6 2 Header J17 Power Stand Alone Operation 6 4 The DN3000k10S can be used stand alone meaning it doesn t have to be plugged into a PCI slot Connector P1 is used to provide power to the DN3000k10S in this configuration P1 is a Molex drive power connector and will connect to any standard ATX power supply see Figure 6 3 The power supply that we used is shown in Figure 6 4 bu
97. e used provided that the 5 V and 12 V power rails on the connector are supplied by the same power source as the PCI fingers DN3000k10S User s Manual 6 5 Power Supplies and Power Distribution 6 6 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Chapter 7 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors The traditional approach to experiment with new devices involving wiring together some ICs on a breadboard is fast becoming impractical and inef fective Instead designers using new high density devices need custom PC boards representing a substantial investment of time and money Prototype boards from manufacturers can meet this demand for experi mentation while eliminating the expense and time involved with custom PC boards Additionally such prototype boards facilitate the under standing and advantages of new device features Purpose The DN3000k10SD daughter card allows external connection to the signals present on the DN3000k10S series ASIC prototyping boards The DN3000k10S allows logic emulation with Virtex devices prior to commit ting to using them for specific applications It allows designers to try Virtex features such as BlockRAM DLLs and Selecti O resource with off the shelf resource Features The DN3000k10S Daughter Card has the following features e Buffered I O Passive and Active Bus Drivers e U
98. el at the direction control DIR input The output enable input can be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance path for an external driver The output enable input can be used to disable the device so that the busses are effectively isolated The DN3000k10SD Daughter Card provides a 200 pin connector to inter face to one of three test connectors on the DN3000k10 ASIC prototyping board J23 J24 and J25 J1 Test Interface Connector Micropax connector 200 pin used as a standard interface to all the DINI Group development boards This connector has a specified current rating of 0 5 amps per contact See Table 7 2 on page 7 8 DN3000k10S User s Manual 7 7 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 pin Connectors Daughter Card I O Connections Table 7 2 shows the DN3000k10SD Daughter Card Interconnects to connectors J23 J24 and J25 Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec tor Connections 123 J23 J24 J24 or J25 Pin FPGA Signal No Signal FPGA Signal Pin Pin 12 V 12 V 12 V GND GND GND ACLK 2 ACLK 3 ACLK 1 45V 45V BCLK
99. enerally not worth your time to preserve your Synopsys ASIC compiler directives and scripts by using the FPGA synthesis products from Synopsis The time you save using Synopsys products is offset by other hassles 1 The FPGA used on your DN3000k10S is either a 2v4000 or 2v8000 in FF1152 package Unless you paid for a faster speed grade the 4 is what you will be getting 2 Memories are best implemented by describing them behaviorally in your RTL All four synthesis products are sophisticated enough to map your behavioral descriptions into the memory blocks It is NOT neces sary to instantiate Xilinx memories manually Make sure however to check the report files to make sure that your memories were imple mented in memory blocks if this is possible Sometimes subtle changes are needed to your RTL to get the synthesis programs to rec ognize that you intended to use an embedded memory block 3 Much to our surprise the synthesis programs recognized RTL multi plier code and used the embedded multipliers without any trouble So like the memories RTL description of your multipliers is all that is necessary Make sure to check the report files multipliers that are implemented using logic blocks as opposed to the embedded mem ory blocks take huge amounts of FPGA resources 4 Clocks are the biggest problem when converting ASIC code to FPGA code FPGAs only have a limited number of clock arrays This is far too complicated to desc
100. ere is not a valid SmartMedia card detected LED2 Lights when there is a configuration error LED3 Lights on data transfer from SmartMedia to FPGA LED4 Lights when FPGA is not configured when DONE is not high DN3000k10S User s Manual 8 3 Reset Schemes LEDs Bus Bars and 200 Pin Connectors LED5 Lights on reset S1 must be down for at least 3 seconds for LED1 to light LOCK1 Lights when the PLL in Roboclockll 1 is LOCKED LOCK2 Lights when the PLL in Roboclockll 2 is LOCKED You are free to reprogram the CPLD to use any or all of the LEDs for your own purposes J26 LED The header 326 Figure 8 4 contains the LED signals for oscilloscope Signals Header observations and debugging You can also route FPGA signals through the CPLD to this header for debug purposes Status LEDs U7 FRONT ANODE1 ANODE2 ANODE4 ANODE1 CATHODE1 ANODE2 CATHODE2 CATHODE3 ANODE4 CATHODE4 555 4003 Figure 8 4 J26 LED Signals Header The Pin Outs for J26 are shown in Table 8 1 Table 8 1 J26 Pin Outs LEDO LOCK_N2 LED1 LOCK_N1 LED2 LED5 LED3 LED4 8 4 The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors Bus Bars The two bus bars B1 and B2 are installed to prevent flexing of the PWB and serve no other purpose They are connected quite solidly into the ground plane of the DN3000k10S at every hole and you can use the metal bars to ground test equipment
101. es the CPLD 2 18 Notes on Header 1 2 19 SelectMAP Configuration Instructions 2 20 Creating Bit Files for Select MAP 2 21 Setting up the Serial Port J27 RS232 Port 2 21 Creating Main Configuration File main txt 2 23 Starting SelectMAP Configuration 2 25 DN3000k10S User s Manual iii Description of Main Menu Options 2 26 PC Bit File Sanity Check 2 27 SmartMedia SS 2 28 Synthesis and Emulation Issues 2 29 Synthesis Notes 2 30 Chapter3 3 1 PCI Mechanical Specifications 3 1 Some Notes on the DN3000K10S and PCI PCI X 3 1 J31 Present Signals for PCI PCI X Pins 1 2 and 5 6 3 5 931 M66EN 66MHz Enable Pins 7 8 3 5 931 PME Power Management Enable Pin 3 3 5 J30 PCI PCI X Capability 3 6 JSO PCIXCAP suada ERR dake 3 6 Chapter 4 Clocks and Clock Distribution Functional 4 1 Clock Grid eee 4 3 Orientation and 4 3 Jumper Control for the Most Common Applications 4 4 Ribbon Cable Providing
102. ew for each Roboclockll derived clock is given in Table 4 7 Based on the following information the user will be able to adjust the skew for any of the Roboclockll outputs ly Table 4 6 Time Unit N factor CY7B993V CY7B994V fom MHz fom MHz at which at which ty 1ns ty 1ns The DINI Group Input Signals RB C F F1 LOW RB C F FO and FBFO 2 1 LOW Clocks and Clock Distribution Table 4 7 Clock Skew Settings CCLK 3 1 0 or ECLK 3 1 0 4 Output Skew Function CCLK 5 4 or ECLK 5 4 4 DCLK 3 0 or FCLK 3 0 8ty DCLK 7 4 or FCLK 5 4 8ty Feedback Output Signals LOW MID 3ty 3ty 7ty LOW HIGH 2ty 2ty 6ty 6ty MID LOW 1 1ty COL1 COL1 MID MID Oty Oty Oty Oty MID HIGH 11 1ty COL2 COL2 HIGH LOW 2ty 2ty 6ty 6ty HIGH MID 3ty 3ty 7ty 7ty HIGH HIGH 4ty 4ty 8ty 8ty The clock skew is equivalent to the skew on CCLK 3 1 0 or ECLK 3 1 0 The clock skew is equivalent to the skew CCLK 5 4 or ECLK 5 4 Differential Clocks In addition to LVTTL clock signals the Roboclockll clock buffers can handle LV Differential LVPECL clocks The user can cable in an acceptable differ ential signal to PLL1B and PLL1BN or PLL2B and PLL2BN through the c
103. f Pull Up Setting up the Serial Port 227 RS232 Port 127 is for an RS232 connection to a terminal ICL3221 U10 provides voltage translation to RS232 levels A cable that converts the 10 pin header to 089 is shipped with the DN3000k10S This cable comes pack aged with a bracket attached Remove the bracket to eliminate the possi bility of it falling on the DN3000k10S which could short signals and damage the board After you have removed the bracket plug the cable into J27 J27 is not keyed so make sure you get the orientation correct Pin2is clearly labeled Pin 1 is opposite of Pin 2 and PIn 1 is identified with a dot Figure 2 14 is a cutout from the assembly drawing and shows the location of J27 and Pin 1 A female to female RS232 cable is provided with the DN3000k10S This cable will attach directly to the RS232 port of a PC We get our cables from Jameco http www jameco com The part number is 132345 Male to female extension cables are part number 25700 DN3000k10S User s Manual 2 21 DN3000k10S Features Overview and General Description
104. feature Dark shading indicates items that are not supported or reserved SDONE in out Snoop Done signal Not Supported Square brackets indicate an optional entry or a bus index ngdbuild option name design name DATA 31 0 A vertical or horizontal ellipsis indicates repetitive material that has been omitted 2 The use of 5161 SIGn in HDL pseudocode frag ment should be interpreted as combinational function of signals SIG1 through SIGn SUM fn A B Cin The prefix or the suffix n indicate hexadecimal notation A read of address 0x00110373 returned 45524943h A ff an n means the signal is active low INT4 is active low fpga inta nis active low SRAMCS is active low The DINI Group DN3000k10S Features Overview and General Description Chapter 2 DN3000k10S Features Overview and General Description DN3000k10S Features The DN3000k10S features include e 32 64 bit 3 3V PCI PCI X based PWB with one Xilinx VirtexII FPGA FF1 152 BGA Initial availability XC2V6000 2V4000 and 2V8000 to follow when available e 500k ASIC gates per PWB with 2V6000 LSI standard Embedded Memory 18k bit blocks 18 18 Device Flip Flops Multipliers XC2V4000 46 080 120 XC2V6000 67 584 144 e On board battery supports Virtexll Data Encryption Standard DES Bitstream Encryption e Fast
105. gnal connections for SSRAM 1 are shown in Figure 5 2 The signal connections for SSRAM 2 are shown in Figure 5 3 The signal connections for SSRAM 3 are shown in Figure 5 4 Flowthrough SSRAMs are functionally the closest to ASIC style memories Pipeline SSRAMs can be clocked at faster frequencies ZBT SSRAMs are typi cally one generation behind in density The subtle differences between the styles of memories are described in the next section Each SSRAM position can be stuffed with a different style of SSRAM but pin 14 is shared between the three SSRAMs Pin 14 may be pulled high by stuffing R55 pulled low by stuffing R56 or left unconnected by not stuffing R55 or R56 DN3000k10S User s Manual 5 1 Memories Y ox MX Y x ox 9000 9990 J23 J24 qmouw P1N 77 74 P2N 93 6 P1NX 13 0 P1N 73 0 162 PONX 13 0 SEMEN PON 10 0 P7N 2 0 43 P2N 5 0 J25 P3NX 11 0 162 P3N 89 0 P4N 27 0 PANX 13 0 70 110 P5NX 13 0 P7N 72 52 P7NI 51 3 P5N 26 0 P6N 93 65 SSRAM 2 P7N 93 73 SSRAM 1 U17 P7NX 11 0 U18 PeNX 11 0 P6N 64 0 FCLK DCLK SDRAM U3 DCLK Figure 5 1 FPGA Interconnect Block Diagram 5 2 The DINI Group 016 1 27 AD27 AB33 AA33 AC26 AB26 AF25 AE25 AB25 AC25 AE27 AF27 U28 AC29 AE30 AD30 AA29 AB29 w30 4 4 AC31 AD31 AB30 AA30 Y31 W31 AA31 AB31 W32 V32 AD32 031 24 AD25 AE28 A
106. his device are utilized so 1096 are available for your own purposes The Verilog source for the CPLD is provided on the CD ROM The file name is CPLD V The CPLD performs the following functions e Level Translation and logic inversion for LED 5 0 LOCK N 2 1 e uP SRAM Interface pP upper lower address latch for 32K x 8 SRAM U4 UPADDR 14 0 SRAMCS e Interface to ATmega128L uP Data Bus UPAD 7 0 Control ALE RD WR Clock CPUCLK e Interface to FPGA configuration signals PROG DOUTBSYF DONEF M 2 0 SelectMap Interface Data Bus D 7 1 DINDOF Chip Select 5 Read Write FWRTSM FTMS FTDO FTDI FTCK e Interface to SmartMedia Card Data Bus SMRTMED 7 0 Control SMCLE SMALE SMWE SMWP SMCE SMRE RDYBUSY e Interface to Serial FPGA Configuration Cable DONE C PROG C CCLK e 30 Spare Connections to the FPGA P3N 91 90 P4N 29 3 P2NX6 We may periodically update the CPLD The CPLD can be reprogrammed using the Xilinx JTAG cable supplied with the DN3000k10S The connec tions are on the 90 header on the top left corner of the PWB labeled J1 The relevant signals and the connections to J1 are listed in Table 2 1 Figure 2 12 shows the location of J1 With the exception of Vcc and GND The DINI Group DN3000k10S Features Overview and General Description
107. hose of you who are new to ESD sensitive products http www esda org basics part1 cfm The DINI Group Technical Support The following means of technical support are available 1 The DN3000k10S User s Manual This is the main source of technical information We strive to produce excellent documentation and this manual should contain most of the answers to your questions The DINI Group Web Page The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com index php product DN3000k10s E Mail to support dinigroup com You may direct questions and feedback to The DINI Group using this e mail address Phone Support We are happy to help Call us at 858 454 3419 during the hours of 8 00 A M to 5 00 P M Pacific Time Some of us get in early and stay late so you might try us outside of these hours also Frequently Asked Questions In the downloads section of our web page you can find a document called DN3000k10 S Frequently Asked Questions FAQ We will update this document occasionally with information that may not be in the User s Manual Relevant Information Information about PCI can be obtained from the following sources The PCI Special Interest Group has a web page that has lots of good stuff Copies of the latest PCI specification may be ordered here DN3000k10S User s Manual http www pcisig com PC
108. i List of Figures List of Figures Continued viii FIGURE 5 8 5 9 5 10 5 11 5 12 5 14 5 13 6 1 6 2 6 3 6 4 7 1 7 2 7 3 8 1 8 2 8 3 8 4 8 5 8 6 9 1 9 2 9 3 9 5 9 6 9 7 9 8 9 9 9 10 9 11 9 12 9 13 A 1 A 2 A 3 TITLE PAGE Syncburst 2 5 8 Syncburst and ZBT SSRAM Timing 5 8 SDRAM U3 Bus Signals Page 1 of 2 5 10 SDRAM U3 Bus Signals Page 2 2 5 11 DCM Connections in Reference Design 5 13 Fine Phase Shift Inputs 5 13 Coarse Phase Shift 5 5 14 Power Distribution DN3000k10S 6 1 Header 17 6 4 Molex Connector P1 Auxiliary 6 4 Example ATX Power Supply 6 5 DN3000k10SD Daughter Card Block Diagram 7 2 DN3000k10S Daughter 7 8 DN3000k10SD Daughter Card Assembly Drawing 7 4 Reset 8 2 DN3000k10S LEDs 8 3 DN3000k10S LED 8 3 J26 LED Signals 8 4 91291 Pin Numbering 8 6 200 Pin Connectors Signal Connections 8 8 AETEST Startup Screen DN3000k10S Recognized
109. id level then the default verbose level will be 2 e The second nonempty uncommented line in main txt tells whether or not to perform a sanity check on the bit files before configuring an FPGA Sanity check y where y stands for yes n for no If the line is missing or the character after the is not y or n then the sanity check will be enabled e For each FPGA that the user wants to configure there should be exactly one entry in the main txt file with the following format FPGA F example bit In the above format the following FPGA is to signal that this entry is for FPGA F and FPGA F would then be configured with the bit file example bit The DN3000k10S only has one FPGA which is FPGA F There can be any number of spaces between the and the configuration file name but they need to be on the same line e Comments are allowed with the following rules 1 All comments must start at the beginning of the line 2 All comments must begin with The DINI Group DN3000k10S Features Overview and General Description 3 If acomment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the user s purpose e The file main txt is NOT case sensitive IMPORTANT All configuration file names have a maximum length of eight 8 characters with an additional three 3 for the extension Do not name your configuration bit files with
110. in txt file names for each FPGA as entered in main txt DN3000k10S User s Manual 2 23 DN3000k10S Features Overview and General Description 2 24 Maker ID device ID and size of Smart Media card files found on Smart Media If sanity check is chosen the bit file attributes will be dis played part package date and time of the bit file During configuration a will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA Sanity Check The Sanity Check if enabled verifies that the bit file was created for the right part the right version of Xilinx was used and the bitgen options were set correctly If any of the settings found in the bit file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the bit file Please see the section Creating Bit Files for SelectMAP on page 2 21 for details on which bitgen options need to be changed from the default settings A PC version of the sanity check can be run on your bit files before copying them onto the Smart Media card see section PC Bit File Sanity Check on page 2 27 for more details Format The format of the main txt file is as follows e The first nonempty uncommented line main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an inval
111. ing books may be helpful Essential VHDL RTL Synthesis Done Right Sundar Rajan The IQ Booster Improve Your IQ Performance Dramatically Edwin Breecher 1 2 The DINI Group Conventions Getting Started This manual uses the following conventions An example illustrates each convention DN3000k10S User s Manual The term will be used generically unless there is a specific instance where PCI applies This design guide generically refers to PCI X protocol When the PCI X HalfBridge core is in PCI mode PCI protocol will be followed Courier font denotes the following items Signals on PCI Bus side of the PCI X Interface FRAME IO PCI X Interface signal name FRAME PCI X Bus signal name Signals within the user application BACK UP START Command line input and output setenv XIL MAP LOC CLOSED HDL pseudocode assign question to be to be assign cannot have cake amp eat it Design file names pcim top v pcim top vhd Courier bold denotes the following items Signals on the user side of the LogiCORE PCI X Interface ADDR VLD Menu selections or button presses FILE gt OPEN Italic font denotes the following items Variables in statements which require user supplied values ngdbuild design name References to other manuals See the Libraries Guide for more information 1 3 Getting Started 1 4 Emphasis in text It is not a bug it is a
112. ip on the DN3000k10 Full Memory Test Including BlockRAM Tests all of the memo ries This includes the SSRAM chips the SDRAM and the BlockRAM internal to the FPGA DN3000k10S User s Manual 9 13 Utilities Memory test on FPGA block memory Tests the BlockRAM inside the FPGA On the DN2000k10 the BlockRAM is only in FPGA F BAR memory range test Generic memory test that prompts the user for BAR number starting address offset DWORD count and number of iterations The user is also prompted if the program should stop if error occurs or if the program should display any errors that occur This allows for maximum flexibility when debugging a design with an oscilloscope or debugging any memories or memory locations on your PCI bus The memory test is very complete performing a write then a read to every location a read from every location and then a read write read test to every location All other memory test options listed in the memory menu are based on this generic memory test function 9 14 The DINI Group Appendix Berg Connector Datasheets Figure A 1 and Figure A 2 contain the schematics for the Berg 91403 003 Connector Figure A 3 through Figure A 5 contain the schematics for the Berg 91294 003 connector DN3000k10S User s Manual A 1 Berg Connector Datasheets Reproduction ou communication a des tiers interdite sous quelque forme que ce soit sons autorisation ecrite du propieloire Tous droits
113. is hot swappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as there is a valid SmartMedia card inserted DN3000k10S User s Manual 2 25 DN3000k10S Features Overview and General Description 2 26 properly in the socket If there is not a valid SmartMedia card in the socket then LED1 will be lit see Figure 8 2 on page 8 3 for LED descrip tions and the Main Menu will appear from the serail port A SmartMedia card is detemined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Other wise an error message will appear The LEDs on U7 and U9 give feedback during and after the configuration process see LEDs on page 8 3 for further details After the FPGA has been configured the following Main Menu will appear on the serial port 1 Configure 5 using main txt Interactive FPGA configuration menu Check Configuration status p 3 4 Select file to use in place of main txt 5 List files on SmartMedia 6 Memory test BlockRAM SSRAM SDRAM Description of Main Menu Options 1 Configure FPGAS in Using main txt as the Configuration File By selecting this option the FPGA will configure in SelectM
114. ith each step Steps 1 and 2 are best done without an operating system in place Windows NT based systems take minutes to reboot after a crash the BLUE screen death and an NT driver won t work unless the hardware is debugged Since crashing is a regular occurrence in a PCI hardware debug environment we find it easiest to do our debug and manufacturing test in the old DOS environment Virtually all PCI peripherals get configured with addresses beyond the IM boundary On a PC C programs cannot access memory locations beyond IM unless special programs called DOS extenders are used Several freeware DOS extenders are available We use a free DOS extender called DJGPP More information can be found http www delorie com DJGPP PC Based AETEST EXE A utility program called AETEST is provided with the DN3000k10S AETEST can be run under DOS Windows 98 ME Windows NT 2000 or LINUX When used under DOS you must boot your PC with a DOS disk We ship one with the DN3000k10S in case you don t know how to make on your own All features work in the native mode of AETEST which is DOS DN3000k10S User s Manual 9 1 Utilities AETEST Utility 9 2 Installation Instructions All source code for AETEST is provided so you are welcome to customize the program to your own applications AETEST is not a stable program We add and subtract features when we need to for debug and verification purposes so don t be concerned if the sc
115. l s have internal circuitry to bring the pin to 1 5 V when left open The Jumper Definitions are shown in Table 4 3 DN3000k10S User s Manual 4 9 Clocks and Clock Distribution Table 4 3 Jumper Definitions Name Type Default Description PLLSEL2 1 Input Clock Select If LOW U12 DCLK7 U11 PLL1A is selected as the input clock If HIGH the U12 PLL2B U11 PLL1B_N pair is selected as the input clock MODE 2 1 Output Mode If HIGH clock outputs disable to high Z state If MID clock outputs disable to HOLD OFF mode If LOW clock outputs disable to factory test mode INV2 1 Invert Mode When HIGH clocks DCLK 3 0 FCLK 3 0 are inverted When MID these clock outputs are non inverting When LOW the pairs DCLK 1 0 and DCLK 3 2 FCLK 1 0 and FCLK 3 2 will be complementary FBDIS 2 1 Feedback Disable When HIGH feedback is disabled When LOW feedback is enabled RB C F F 1 0 Output Phase Function Each pair controls the phase function of the respective group of outputs See Clock Skew on page 4 12 for more information C F DS 1 0 Output Divider Function Each pair controls the divider function of the respective group of outputs See Clock Division on page 4 11 for more information Frequency Select The input specifies the operating range of the nominal frequency See General Control on page 4 11 for more information FBF0 2 1 Feedback Output Phase Function The input c
116. line memory module Electrically Erasable PROM Electronic Industries Association electrostatic discharge frequently asked questions file allocation table first in first out field programmable gate array flowthrough ground Hardware Description Language input output integrated desktop connector intellectual property light emitting diode large scale integration DN3000k10S User s Manual LUT LVCMOS LVDS LVDS LVTTL MDR NIST PCI PCI X PGP PL PLL PNP PWB RAM RISC RSA RTL SDRAM SRAM SSRAM TDEA TTL Glossary and Acronyms lookup table low voltage complementary metal oxide semiconductor low voltage differential signalling Low Voltage Differential Signaling low voltage transistor transistor logic Mini D Ribbon National Institute of Standards and Technology peripheral component interconnect peripheral component interconnect extended Pretty Good Privacy pipelined phase lock loop plug and play printed wire board random access memory reduced instruction set computer A public key cryptosystem developed by MIT professors Ronald L Rivest Adi Shamir and Leonard M Adleman resistor transistor logic synchronous dynamic random access memory shadow random access memory synchronous static random access memory riple data encryption algorithm transistor transistor logic UCF user configuration file VHDL VHSIC Hardware Description Languag
117. lity Figure 3 5 shows the PCI X Capabilities Header Add in PCI X boards tell the system what speed they are capable of running by the correct setting of this header Add in cards indicate at which fregency they support PCI X using a pin called PCIXCAP If the card s maximum frequency is 133 MHz this pin is left unconnected except for a decoupling capacitor C93 If the card s maximum frequency is 66 MHz it connects PCIXCAP to ground through a resistor R54 and decoupling capacitor C93 Conventional PCI cards connect this pin to ground J30 PCIXCAP For PCI only not PCI X capable jumper between pins 1 and 2 For PCI X 133 MHz capable jumper between pins 3 and 4 For PCI X 66 MHz capable jumper between pins 3 and 4 and pins 5 and 6 The DINI Group The PCIXCAP jumpers are detailed in Table 3 3 Table 3 3 PCIXCAP Jumpers PCIXCAP Jumper s Installed PCI Only PCI X 133 MHz PCI X 66 MHz The M66EN and PCIXCAP Encodings are shown in Table 3 4 Table 3 4 M66EN and PCIXCAP Encoding Conventional PCI X Device Device Frequency Frequency xs Capability Capability PCIXCAP Ground Ground Not Capable Not Ground Not Capable Connected Ground Pull down PCI X 66 MHz Not Pull down PCI X 66 MHz Connected Not PCI X 133 MHz Connected Not Not PCI X 133 MHz Connected Connected Ground DN3000k10S User s Manual 3 7 PCI 3 8 The DINI Group Clocks and Clock Distrib
118. lock grid J20 J22 The signals must obey the specifications given in Table 4 8 Onboard circuitry is available to center the signals about the proper voltage if needed Table 4 8 LVPECL Input Specifications Description Differential Voltage Highest HIGH Voltage Lowest LOW Voltage Common Mode range crossing voltage The clock input of the Roboclockll can accept a superset of PECL PECL involves 1 V swing about 2 The Roboclockll clock input can accept a swing of up to 3 3 V about 2 which gives the user another dimension of flexibility DN3000k10S User s Manual 4 13 Clocks and Clock Distribution Useful Notes and Hints The CY7B993V 4V can output LVTTL complementary differential signals too Setting INV1 INV2 LOW will result in clocks DCLK 1 0 and DCLK 3 2 FCLK 1 0 and FCLK 3 2 becoming complementary pairs A network of series and parallel resistors could be used to reduce the nominal swing of the clock signals The CYB993V consistently outputs 32 5 MHz signals in cases of improper settings or unacceptable clock inputs This was observed when e The CY7B993V part was operating at a nominal frequency fyom of 36 4 MHz with FS set LOW e identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz However the maximum output frequency is 185 MHz This means when 185 MHz x fyoy 200 MHz the output divider must be set
119. long file names In addition all file names should be located in the root directory of the Smart Media card no subdirectories or folders are allowed Since the main txt file controls which bit file is used to configure the FPGA the Smart Media card can contain other bit files Example of main txt start of file main txt Verbose level 2 Sanity check y FPGA F fpgaF bit the line above configures FPGA F with the bit file fbgaF bit end of main txt Given the above example file e Verbose level is set to 2 e sanity check on the bit files will be performed e FPGA F will be configured with file fpgaF bit Starting SelectMAP Configuration If using the reference design SmartMedia card that came with the DN3000k10S then no files need to be copied to the card Otherwise copy your bit file and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter Make sure the jumpers on J2 are set for SelectMAP as shown in Table 2 4 Table 2 4 12 Configuration Jumper Settings Pins 1 amp 2 Pins 3 amp 4 Pins 5 8 6 Configuration Mode No Jumper Jumper No Jumper JTAG Jumper No Jumper No Jumper SelectMAP Set up the serial port connection as described above in Setting up the Serial Port 127 5232 Port on page 2 21 Next place the SmartMedia card in the SmartMedia socket on the DN3000k10S and turn on the power NOTE the card can only go in one way The SmartMedia card
120. ls are TTL or some low current variation such as LVDS so you can reasonably expect to get up to 3 amps per power pin through this connector Remember that the 3 3V and 1 5V power supplies are limited to 5 amps total the memories the FPGA and the clock circuitry on the DN3000k10S consume 3 3V The FPGA only consumes 1 5V 8 110152 79 2x REF 2x 2 220 5 55 2x Mounting Holes OH EE ETE ED DT 7 B R 10 7272 2 REF Figure 8 5 91291 Pin Numbering The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors If you need more power consider using a cable connecting J17 to your daughter card in addition to the pins on the 200 pin connectors See Header J17 Off Board Power on page 6 3 for more detail If you use the DN3000k10S stand alone meaning that it is not plugged into a PCI slot the auxiliary power connector has 5V and 12V but does not have 12V So unless you provide 12 to the DN3000k10S via another connection 12 will not be available for use by a daughter card NOTE 12V is not required by the DN3000k10S The DN3000k10S will operate normally without 12 power supply Some of the interconnect with the 200 pin connectors is shared with the memories See Figure 5 1 on page 5 2 to see which signals are shared J25 CON1 has no signa
121. ls that are shared Figure 8 6 Notes e Some signals have an X designation Early in the design stage for the DN3000k10S the X designation meant that the signal existed for the 2v4000 6000 8000 but not for the 2v3000 Signals were swapped during the torturous layout process and in the final product this is no longer true So signals with an X desig nation are no different than other FPGA signals e careful with the control signals for the SSRAMs that are shared with J23 and J24 If the OE is active the SSRAM drives its data bus If the CEs are active a write may occur e The signals designated MBCK where 2 is 0 1 2 3 4 5 6 7 or 8 are connected only between the 200 pin connectors and the FPGA These signals are connected to a clock input pin on the FPGA and therefore can be used as a method to externally clock the FPGA Also some of MBCK s may be combined to provide dif ferential I Os DN3000k10S User s Manual 8 7 Reset Schemes LEDs Bus Bars and 200 Pin Connectors
122. n 32 MB 3 3 V Smart Media Card Do not press down on the top of the SmartMedia Connector J28 if a Smart Media card is not installed The metal case shorts to the 43 3 V power supply and the case gets hot enough to burn your finger We suggest that you leave a SmartMedia card in the connector to prevent this from occur ring NOTE Do NOT press on the SmartMedia Connector J28 if a card is not installed WARNING Do NOT format a SmartMedia card using the default Windows format program All Smart Media cards come preformatted from the factory and files can be deleted from the card when they are no longer needed If for some reason you absolutely need to format a SmartMedia card you must use the format program that is included in the FlashPath SmartMedia floppy adapter software Synthesis and Emulation Issues We use the following tools for synthesis Synplicity Symplify http www synplicity com Synopsys FPGA Express http www synopsys com Synopsys FPGA Compiler II DN3000k10S User s Manual 2 29 DN3000k10S Features Overview and General Description 2 30 Synthesis Notes Exemplar LeonardoSpectrum http www exemplar com products leonardospectrum html Of the four listed here we find that Synplicity offers the best perfor mance followed by Exemplar The Synopsys products are not the easiest products to use and probably should be avoided until Synopsys decides that they want to be in this market It is g
123. nbuffered I O e Differential LVDS pairs Note Not available DN3000k10S ASIC prototyping board e Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 7 1 is a block diagram of the DN3000k10SD Daughter Card The DN3000k10SD Daughter Card is pictured in Figure 7 2 Figure 7 3 shows the assembly drawing of the DN3000k10SD Daughter Card The DN3000k10SD Daughter Card provides 16 differential pairs 48 buff ered passive active and 66 unbuffered signals DN3000k10S User s Manual 7 1 Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Connectors DIFFERENTIAL ACLK1 CONNECTOR BCLK1 CCLK1 ECLK1 J5 MBCK6 3 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED 70 0 17 DF CLOCK J2 DIFF PAIR A0 A15 J6 UNBUFFERED 0 23 50 PIN MINI D RIBBON CABLE CONNECTOR J7 UNBUFFERED 1 0 0 23 LINEAR REGULATOR 12VDC TO 3 3V J1 POWER INDICATORS BUFFERED 0 15 U1 UNBUFFERED 0 15 O O O 3 3V 5 0V 12 0V BUFFERED 0 7 3 9VDC POWER U2 UNBUFFERED 0 15 HEADER 3 3V J4 5 0V 12 0V J6 U3 UNBUFFERED 1 0 0 15 12 0V GND 20 PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST163245PA BOTTOM OF PWB U1 U2 U3 BUFFERS OR LEVEL TRANSLATORS Figure 7 1 DN3000k10SD Daughter Card Block Diagram 7 2 The DINI Group Daughter
124. neral Description LVDS is supported on some pins to the 200 pin connectors See The 200 Pin Connectors J23 J24 J25 on page 8 5 Bitstream virtexll devices have on chip decryption circuitry that can be enabled to Encryptions make the configuration bitstream and thus the whole logic design secure Ultimately you will be able to encrypt the bitstream in the Xilinx software and the Virtexll chip will perform the reverse operation decrypting the incoming bitstream and internally recreating the intended configuration The DN3000k10S has a battery socket to support this function Encrypting the bitstream is important if you want to use the DN3000k10S as a platform to demonstrate intellectual property IP but don t want anybody reverse engineering the bitstream in an attempt to steal the design NOTE It is possible to recreate a design from the configuration bitstream This method provides a very high degree of design security Without knowledge of the encryption decryption key or keys potential pirates cannot use the externally intercepted bitstream to analyze or even to clone the design System manufacturers can be sure that their Virtexll implemented designs cannot be copied and reverse engineered The devices store the internal decryption keys in few hundred bits of dedicated RAM backed up by a small externally connected battery BTI on the circuit board At less than100 nA per load the endurance of
125. ntrols the FPGA configuration process Visibility into the configuration via process is enhanced with an RS232 port Sanity checks are performed auto SmartMedia matically on the configuration bit files helping to avoid the time consuming process of debugging the configuration process FPGA config uration runs quickly at 48 MHz Eight LEDs provide instant status and oper ational feedback Two of these LEDs are connected to the CPLD and can be user configured FPGA Virtexll 016 The DN3000k10S contains a single Virtexll FPGA The package is a flip chip fine pitch BGA with 1152 pins FF1152 The pitch on the pins is 1 mm This isn t important but this pin density makes the PWB a bitch to layout Keep that in mind if you try to make one of these at home All 824 I O pins are utilized on the FF1152 package The DN3000k10S can be stuffed with the XC2V4000 XC2V6000 and 2 8000 The XC2V3000 is available in FF1152 but since it has fewer I O pins it should not be used The standard speed grade we stuff is 4 We can use the 5 and 6 speed grades but don t fall out of your chair when you get the price Note that Xilinx has cancelled plans for the XC2V10000 Even though this part appears in some Xilinx literature we have been told that the XC2V8000 is the largest part that the process will handle Don t expect to see anything larger than the XC2V8000 until the 2003 time frame The following is a very brief overview of the Vir
126. nx User s Guide to create an encrypted bitstream Two files will be created The first is the encrypted bit file the second is a key file nky which you can specify using the g Key File lt filename gt option The key file contains the encrypt decrypt keys used to encrypt decrypt the bit file 2 Programming the Key File Using the Xilinx iMPACT tool and a JTAG programmer program the key file nky into the FPGA that will decrypt the encrypted bit streams Make sure that a 3 V 2032 type lithium coin battery is installed in BT1 prior to programming The battery is required for key retention 3 Programming the Encrypted Bitstreams Using the Xilinx iMPACT tool and a JTAG programmer program the encrypted bitstreams into the FPGA The FPGA will then decrypt the bitstream using the previously programmed decryption keys Programming Encrypted Bitstreams Using SmartMedia The procedure for this is very similar to the procedure for JTAG However support for this is not complete and will be coming shortly For more detailed information contact us directly or visit our web site at http www dinigroup com products 3000k10ns html The DINI Group DN3000k10S Features Overview and General Description The Battery The DN3000k10S has a socket for a battery BT1 The socket uses a 3 V 2032 coin style lithium battery Don t eat the battery Most lithium batteries are rated at about 200 mAh so at 100 nA the battery should l
127. of the resources of the for your own purposes The pP Some ATmega128L is gross overkill for the FPGA configuration function The Details datasheet and user s manual are on the CD ROM that was shipped with the DN3000k10S file names ATmegal28 UM pdf atmegal28 DS pdf But if you intend to use the for your own purposes you should check the Atmel web page to get a copy of the latest user s manual datasheet and erratas The Atmel web is http www eu atmel com atmel The ATmega128L is under the section called Flash Microcontroller AVR 8 Bit RISC Most of the features are unused A variety of test headers allow for possible use of these features Each header and the various possible functions are described in the sections that follow Figure 2 6 is a block diagram of the ATmega128L and its various interfaces on the DN3000k10S DN3000k10S User s Manual 2 9 DN3000k10S Features Overview and General Description Translator es T um lt 85232 Serial CL 3221 Port 2 1 Atmel AVR ATmega128L 128kbytes FLASH 4kbytes SRAM 4kbytes EEPROM User I O General Purpose I O uP U6 Crystal Smart 32 768MHz ZZ Media Card Inserted Programming Header J29 Reset O Switch T Ji Programming Header TOD wy PWR RST 5V 3 3V 1 5V Reset amp Power Threshold Detection 08 Fig
128. ontrols the phase function of the feedback outputs See Feedback and Clock Multiplication on page 4 11 for more information FBDS 1 0 2 1 Feedback Output Divider Function Each pair controls the divider function of the feedback outputs See Feedback and Clock Multiplication on page 4 11 for more information 4 10 The DINI Group Clocks and Clock Distribution General FS 2 1 is a 3 Level input which determines the allowable range for the Control operating frequency fyom of the device Depending on the chip grade the PLL can operate between 12 100 MHz or 24 200 MHz The actual frequency can be determined by setting all jumpers to their defaults Thus will be seen on all of the divide by one clock outputs The user can set FS accordingly The Frequency Range Settings are shown in Table 4 4 Table 4 4 Frequency Range Settings CY7B993V CY7B994V from MHz from MHz MIN MAX MIN MAX Feedback and First of all FBDIS 2 1 must be set LOW enabling feedback The feed Clock back output is looped back to the feedback input When a divided output 3 is applied to the feedback input the VCO voltage controlled oscillator of Multiplication the PLL aligns the feedback input with the original input clock Thus with 10 MHz input clock and the feedback outputs set to divide by 2 must be 20 MHz Consequently 10 MHz is seen on the feedback output clocks and can be aligned
129. own designs To configure the FPGA with the reference design please skip to Starting SelectMAP Configuration on page 2 25 The DINI Group DN3000k10S Features Overview and General Description Creating Bit Files for SelectMAP Create bit files with Xilinx 3 3i with service pack 8 or Xilinx ISE 4 x e Use Xilinx 3 3i with service pack 8 and the patch for Virtexll see http support xilinx com techdocs 11805 htm or Xilinx ISE 4 For Xilinx 3 3i Design Manager e After creating a project in Xilinx go to the menu Design Options choose Edit Options for Configuration and uncheck the box Enable the Power Down Status pin Done pin onthe Configuration tab Also make sure that on the Startup tab the Startup Clock is CCLK For Xilinx ISE 4 x Design Manager e After creating a project in Xilinx go to the menu Design Options choose Edit Options for Configura tion and go to the Startup tab and make sure the Startup Clock is CCLK on the Readback tab select SelectMap For Xilinx ISE 4 x Project Navigator e NOTE All the bitgen options are set correctly by default how ever you may want to double check a few of the options After creating a project and adding your source file right click on Gen erate Programming File in the Process View window Select the Startup Options tab and make sure that the Star tup Clock is set to CCLK Select the Configuration Options tab and make sure Configuration Pin Powerdown has a value o
130. ption BFO FBDSO1 1 2 3 4 5 6 7 8 9 e e HDR10x1 HDR10x1 HDR10X1 Figure 4 8 Clock OE Pin Jumper Settings Table 4 9 Clock OE Pin Jumper Settings Clock OE Jumper Settings Active High OE for X1 Jumper J15 9 to J16 9 Active Low OE for X1 Jumper J14 9 to J15 9 Active High OE for X2 Jumper J15 10 to J16 10 Active Low OE for X2 Jumper J14 10 to J15 10 DN3000k10S User s Manual 4 15 Clocks and Clock Distribution The DINI Group Memories SSRAMs SSRAM Notes Memories Chapter 5 The DN3000k10S has four external memories three 36 bit SSRAMs and one 72 bit SDRAM DIMM The three SSRAMS are referred to as SSRAM 1 U18 SSRAM 2 U17 and SSRAM 3 U15 The SSRAMs can be stuffed with ZBT non ZBT pipeline or flowthrough parts We believe we have anticipated the additional address lines for the 1M x 36 and 2 M x 36 parts when they are available The DN3000k10S is stuffed at the factory with 512 K x 36 bit Synchronous Pipeline Burst SRAM Samsung K7A163600M QC1400 are probably the parts you will have stuffed into your DN3000k10S The datasheet is on the CD ROM in the file DS K7A1636 18 00M pdf The SSRAMs are tested at 100 MHz SSRAM 1 and SSRAM share some 1 05 with 124 See Figure 5 1 to figure out which ones SSRAM 1 is clocked by DCLK SSRAM 2 is clocked by SSRAM is clocked by The si
131. r Connections 123 123 124 724 J25 Pin P2NX 3 P1N 59 P7N 37 P2NX 3 GND GND GND GND P2NX 2 P1N 58 P7N 36 P2NX 2 P3NX 11 P1N 55 P7N 33 P3NX 11 P3NX 10 P1N 54 P7N 32 P3NX 10 P3NX P1N 51 P7N 29 P3NX P3NX P1N 50 P7N 28 P3NX P3NX P1N 47 P7N 25 P3NX P3NX P1N 46 P7N 24 P3NX P3NX P1N 45 P7N 23 P3NX P3NX P1N 44 P7N 22 P3NX P3N 85 P1N 39 P7N 17 P3N 85 GND GND GND GND P3N 84 P1N 38 P7N 16 P3N 84 P3N 81 P1N 35 P7N 13 P3N 81 P3N 80 P1N 34 P7N 12 P3N 80 P3N 79 P1N 33 P7N 11 P3N 79 P3N 78 P1N 32 P7N 10 P3N 78 P3N 73 P1N 27 P7N 5 P3N 73 P3N 72 P1N 26 P7N 4 P3N 72 P3N 71 P1N 25 P7NI 3 P3N 71 P3N 70 P1N 24 7 2 P3N 70 P3N 65 P1N 19 PON 75 P3N 65 GND GND GND GND P3N 64 P1N 18 PON 74 P3N 64 P3N 61 P1N 15 PON 71 P3N 61 P3N 60 P1N 14 PON 70 P3N 60 P3N 59 P1N 13 PON 69 P3N 59 P3N 58 P1N 12 PON 68 P3N 58 P3N 53 1 7 PON 63 P3N 53 7 12 The DINI Group Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Table 7 2 DN3000k10SD Daughter Card I O Interconnects Daughter Card DN3000k10 I O Connec tor Connections 123 123 124 724 J25 Pin P3N 52 P1N 6 PON 62 P3N 52 P3N 51 P1N 5 PON 61 P3N 51 P3N 50 60 P3N 50 P3N 45 P2N 93 PON 55 P3N 45 GND GND GND GND P3N 44 P2N 92 PON 54
132. rboard The signals TMS and TRST are left uncon nected The Virtexll FPGAs are not 5 V tolerant so you must plug the DN3000k10S into a 3 3 V PCI slot Do NOT modify the connector to get the board to fit If you need 5V to 43 3 V PCI voltage translation get one of our extenders The link is http www dinigroup com products pciextender html The FPGA is volatile meaning it loses its brains when power is off The SmartMedia method takes about 1 second to configure a 2V6000 after power is stable It is likely that the FPGA will finish the configuration process before RST is deasserted If your system has an unusually fast RST it is possible that the FPGA will not be configured when RST deas serts A RST that deasserts before the FPGA has finished cannot properly configure the PCI PCI X mode latch The signal 3 3Vaux is not connected The signals INTB INTCZ and INTD are not connected 3 4 The DINI Group PCI J31 Present Signals for PCI PCI X Pins 1 2 and 5 6 The present signals indicate to the system board whether an add in card is physically present in the slot and if one is present the total power requirements of the add in card The 131 PCI X Present Header is shown in Figure 3 4 J31 PRSNT2 HDR4X2 Figure 3 4 J31 PCI X Present Header Table 3 1 shows the Present Signal Definitions for PCI PCI X Table 3 1 Present Signal Definitions PRSNT1 PRSNT2 Expansion Configuration Open
133. reens that you see aren t exactly replicated here In a nutshell AETEST lets you do the following Determine if PCI recognizes the DN3000k10S Read write loop any memory location Read write loop configuration space Display all configured PCI devices Display memory setting from any locations Fill memory with various patterns Run various tests on the DN3000k10S SSRAM Test Multiplier Test SDRAM Test Interconnect Test Daughter Card Test Installation Instructions for DOS 1 The files aetestdj exe and cwsdpmi exe the DOS extender need to be in the same directory 2 Runaetestdj exe Installation Instructions for Windows NT 1 Install the device driver install exe and qldriver sys must be in the same directory 2 Type install 3 After the driver is installed start the driver by selecting Control Panel gt Devices gt find QLDriver click Start 4 Runaetestnt exe Installation Instructions for Windows 2000 1 Install the device driver qldriver2000 inf and the driver file qldriver sys should be in the same directory 2 Open Control Panel click on Add Remove Hardware and then go to 3 Choose Add Troubleshoot a device the default option and click on Next 4 Wait until it finishes new hardware device searching choose Add a new device and click on Next gt 5 Choose want to select the hardware from a list and press Next
134. ribe here so get the Virtex User s Manual and read about the clocks The DINI Group PCI Chapter 3 Overview The DN3000k10S can be hosted a 32 bit or 64 bit PCI slot PCI X is also supported Standalone operation is described in Stand Alone Operation on page 6 4 A 2v6000 4 with care should be able to support a 64 bit 66 MHz PCI or PCI X controller We have not tested the PWB at PCI X speeds of 100 MHz and 133 MHz We suspect but won t guarantee that the DN3000k10S can support these high frequencies provided the speed grade of the FPGA is adequate Figure 3 1 shows the FPGA pin connections for the PCI signals This data is provided on the CD ROM in a UCF file titled fpga ucf for your convenience The PCI PCI X edge connector is shown in Figure 3 2 Virtexll parts cannot tolerate 5 V TTL signaling so the DN3000k10S must be plugged into a 3 3 V PCI slot PCI X by definition is 3 3 V signaling The PWB is keyed so that it is not possible to mistakenly plug the board into a 5 V PCI slot Do NOT grind out the key in the PCI host slot and do NOT modify the DN3000k10S to get it to fit into the slot If you need a 43 3 V PCI slot the DNPCIEXT S3 Extender card can do this function The link is http www dinigroup com products pciextender html This extender also has the capability to slow the clock frequency of the PCI bus by a factor of two a function that is very useful when prototyping ASICs NOT
135. ritten in sequential order to the same address A looping option is available if you want to use an oscilloscope If you are in a scope loop any keypress will terminate the loop and return you to the main menu Read Memory Test Read a single long word from a specific PCI memory location Figure 9 7 b000000 Please s Input address f b000000 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely elect 9 10 Figure 9 7 AETEST Read Memory Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display The DINI Group Utilities Write Read Test Write a long word to a specific memory location and immediately read what was written Repeat for a selected number of long words Figure 9 8 Input address fb000000 long word to write in hex 000 long word to write in hex aaa l Display result Please select Numbers of long words to write in decimal 2 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Figure 9 8 AETEST WritelRead Test You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read The program will prompt
136. rt to Pin 15 NC No Short GND Short to Pin 67 NC No Short NOTE R55 and R56 on DN3000k10S board connect Pin 14 of all three SSRAMs together 5 6 The DINI Group Memories Pipeline Syncburst FT Flowthrough Figure 5 5 is the most straightforward type Flowthrough of SSRAM available for the DN3000k10S Write data may be accepted on the same clock cycle as the activation signal and address and read data is ZBT returned one clock cycle after it is requested Syncburst is designed to allow two controllers to access the same SSRAM using two activation signals ADSC and ADSP an activation with ADSP requires data and byte enables one clock cycle after the address and activation Syncburst PL Pipelined Figure 5 6 is identical except for registered outputs which delay read data an additional clock cycle but may be necessary for high speed designs Zero Bus Turnaround ZBT SSRAMs are designed to eliminate wait states between reads and writes by synchronizing data Thus ZBT FT SSRAMs Write Control Logic 18 2 MK Burst i Control 1 0 Memory Block Address Register Output Buffers Read Control Logic Figure 5 5 Syncburst FT emory Block gt Write Control Logic 18 2 Address Register Burst Control Read Control Logic Figure 5 6 Syncburst PL DN3000k10S User s Manual 5 7 Memories Figure 5 7 accept and return
137. se regulators has a heat sink and thermal issues were considered in the design of the PWB Each regulator should be able to supply the minimum 5 5 A of current without strain The most demanding application of the DN3000k10S should fit within the 5 5 A budget on these two power rails The heat sinks on the regulators will get hot possibly too hot to touch The specification for the 3 3 V power is shown in Table 6 1 The 3 3 V supply is used by the following components on the DN3000k10S Virtexll FPGA 016 Roboclockll s 011 012 2 Clock buffers 013 014 CPLD U5 Microprocessor U6 Microprocessor SRAM U4 3 SSRAMs U15 U17 U18 SDRAM DIMM U3 3 Oscillators X1 X2 X3 We do run 3 3 V a little hot At worst case for all components the 3 3 V power supply should never fall below 3 30 V Table 6 1 Specification for 3 3 V Power Voltage Current The DINI Group Power Supplies and Power Distribution 1 5 V Power The specification for the 1 5 V power is shown in Table 6 2 The 1 5 V supply is used by the following component the DN3000k10S Virtexll FPGA V INT 016 We also run 41 5 V a little hot At worst case for all components the 41 5 V power supply should never fall below 1 50 V Table 6 2 Specification for 1 5 V Power Manum Voltage 1 55 V 41 56 41 58 If you use the DN3000k10S in a lab environment the Virtexll FPGA will never see worst cas
138. se shift Figure 5 14 Fine Phase Shift Inputs DN3000k10S User s Manual 5 13 Memories LJ LI LI L CLKO J LJ LI LI L qc CLK180 CLK270 Figure 5 13 Coarse Phase Shift Outputs 5 14 The DINI Group Power Supplies and Power Distribution Chapter 6 Power Supplies and Power Distribution The DN3000k10S be hosted in a 3 3 V PCI slot or it can be used stand alone Figure 6 1 shows the various supplies used on the DN3000k10S and the connections of these supplies on the circuit board The supply 5 V from the PCI connector or P1 supplies the basic power to the DN3000k10S The 3 3 V power from the PCI connector is not used nor is it connected to any circuitry on the DN3000k10S P1 V J23 5 V 3 3 V 41 5 V 12 V 5A 5A 12V Regulator Regulator Molex J24 5 V 43 3 V i DE 41 5 V 200 pin Micropax 412 V Header Connectors 12 V J25 5 V 43 3 V PCI X 41 5 V Connector 412 V 12 Figure 6 1 Power Distribution DN3000k10S The DN3000k10S when plugged into a PCI slot has the following different power rails e 45V e 433V DN3000k10S User s Manual 6 1 Power Supplies and Power Distribution 3 3 V Power 6 2 e 41 5V e 12V e 412V The power rails 3 3 V and 1 5 V are created using an LM1084 regulator with 5 V as the input 3 3 V from the PCI fingers is not used U1 is for 3 3 V and U2 is for 1 5 V Each of the
139. specified CUSTOMER xx 01 COPY 1 005 projection title 0 050 1 27 ex 0 480 12 19 010 25 QY 6 BERG ELECTRONICS MICROPAX 025M SMT LL dee 374 93 product fomily PLUG DOUBLE MODULE MICROPAX ee mran 3 4 93 code size dwq no l heet 91294 5 A 5 Figure A 4 Berg 91294 003 Datasheet Page 2 of DN3000k10S User s Manual Droits de reproduction BERG ELECTRONICS INC Reproduction ou communication a des tiers interdite sous quelque forme que soit sons autorisation ecrite du pro Tous droits strictement reserves Propriete de C BERG ELECTRONICS re Copyright BERG ELECTRONICS INC All rights strictly reserved Reproduction or issue to third parties in any whatever is not permitted without written authority from the proprietor Berg Connector Datasheets Property of C BERG ELECTRONICS PRODUCT NO OF PROCESSING NUMBER CONTACTS HOLD DOWN CAP 91294 001 120 1 930 50 95 830 21 08 725 18 42 1 550 39 37 2 150 54 61 1 790 45 47 965 24 51 5 INSTALLED 002 160 2 430 61 72 1 080 27 43 975 24 76 2 050 52 07 2 650 67 31 2 290 58 16 1 215 30 86 ON 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465 37 21 CONNECTOR NOT SHIPPED 200 2 930 74 42 1 330 33 78 1 225 31 12 2 550 64 77 3 150 80 01 2 790 70 87 1 465
140. ssing the push button S1 causes the following sequence of events 1 Reset of the CPLD and uP 2 FPGA configuration is cleared 3 If the jumpers on 12 set for SelectMAP and there is a valid SmartMedia card inserted into the socket then the FPGA will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 4 The Main Menu will appear The identical sequence of events occurs at power up DN3000k10S User s Manual 8 1 Reset Schemes LEDs Bus Bars and 200 Pin Connectors 3 3 V PST SRRST Reset Button Reset Control LT1326 Power 1 5 Monitor 51 PWRRST uP ATmega128 Programming U6 Header Figure 8 1 Reset Functionality 8 2 The DINI Group Reset Schemes LEDs Bus Bars and 200 Pin Connectors LEDs The 3000 105 has eight LEDs that are used to visually communicate the status of circuitry Figure 8 2 Figure 8 2 DN3000k10S LEDs From left to right the LEDs are labeled LEDO LED1 LED2 LED3 LED4 LED5 LOCK1 LOCK2 see Figure 8 3 U7 U9 LOCK for Roboclock II 2 LEDO LED1 LED2 LED3 LED4 LED5 LOCK for Roboclock 1 Figure 8 3 DN3000k10S LED Diagram The LEDs have the following functions LEDO Lights when the configuration from the SmartMedia was successful LED1 Lights when th
141. st started it tries to find a device that it recognizes We have arbitrarily defined the DN3000k10S with a DEVICE ID of 0x1240 and a VENDOR ID of OxABCD You should see the following screen if AETEST recognizes a DN3000k108 Figure 9 1 searching for DN2000K10 Asic Emulator 1000E VENDOR ID abcd DEVICE ID 1236 searching for DN2000K10 Asic Emulator 1600E VENDOR ID abcd DEVICE ID 1237 searching for DN3000K10S Asic Emulator 6000 VENDOR ID abcd DEVICE ID 1240 found device vabcd d1240 name DN3000K10S Asic Emulator 6000 Configuration space 00 1240abcd 04 0000001f 08 000047 0c 00000000 10 fd800000 14 e0000000 18 00000000 1c 00000000 20 00000000 24 00000000 28 00000000 2c 90ab5678 30 00000000 34 00000000 38 00000000 3c 00000000 BARO base 0xfd800000 size 0x00800000 BAR1 base 0xe0000000 size 0x10000000 BAR2 base 0x00000000 size 0x00000000 BAR3 base 0x00000000 size 0x00000000 BAR4 base 0x00000000 size 0x00000000 BAR5 base 0x00000000 size 0x00000000 press any key 9 4 Figure 9 1 AETEST Startup Screen DN3000k10S Recognized Most of this initial display is debug information The program is looking for a Vendor and Device ID that it recognizes and finds vendor abcd and device 1240 which is a DN3000k10S stuffed with a 2V60000 The The DINI Group lines after Configuration space Utilities show what is in the configuration space and how the
142. strictement reserves Propriete de c BERG ELECTRONICS ELECTRONICS All rights strictly reserved Reproduction or issue to third porties in any form whatever is not permitted without written authority from the proprietor Droits de reproduction BERG ELECTRONICS INC Copyright BERG ELECTRONICS INC Property of C BERG ELECTRONICS PRODUCT NO SEE TABLE TABLE REF CONTACT THICKNESS SECTION ROTATED CCW 90 SCALE 10 1 375 9 52 NOSEPIECE FRAME 200 5 08 SEE NOTE 3 5 form no 7550 001 105 040 1 02 X 047 1 19 OVAL REF 044 1 12 DIA REF 0 1042 64 REF 2X 052 1 32 REF 2x CONNECTOR PROVIDED WITH PROCESSING CAP NOTE 5 0 060 1 52 100 2 54 REF matl code tolerances unless otherwise specified 01 51960 XXX_ 005 V51238 0020 60875 8 1 96 70095 SAR_ 7 22 97 dr V81703 9 25 98 enar 050 1 27 ELECTRONICS MICROPAX 025M SMT RECEPT SINGLE MODULE INCH MM product family MICROPAX jsize dwg no code 22526 Figure A 1 Berg 91403 003 Datasheet Page 1 of 2 The DINI Group A 2 Berg Connector Datasheets Reproduction ou communication a des tiers interdite Tous droits strictement reserves Alt rights strictly reserved Reproduction or issue to third parties in any form whotever is not permitted wi
143. such as oscilloscopes and pattern genera tors Be careful not to short any power rails or signals to these metal bars they can carry a lot of current The PCI bracket BRK1 is also connected to the ground plane at each of the screw mounts The 200 Pin Connectors J23 J24 J25 The DN3000k10S contains three 200 pin connectors J23 124 and 125 Daughter cards of any sort may be plugged into these connectors The relative pin location of the powers grounds and signals is identical for each of the three connectors which means that the same daughter card can be plugged into any of the three slots A hole that can be used to attach a standoff is located at the same relative position from each connector Figure 8 5 This hole is grounded on the DN3000k10S so connect this mounting hole to digital ground on your daughter card The mechanical position of the 200 pin connectors on the DN3000k10S is shown in Figure 8 5 The 200 pin connector used on the DN3000k10S is a Berg Electronics 91294 003 in the Micropax family This link will take you to the Berg website http www berg com This Berg connector was chosen because of its high pin density performance and availability The part number for the mating connector is 91403 003 We stock the mating connector at our offices in La Jolla CA so if you are designing a daughter card and are having trouble getting this part call us We would be happy to send you a few at our cost Appendix A contains
144. t any ATX or AT style power supply will work We use a 250 watt ATX supply Since the DN3000K10S does not draw enough current to meet the minimums required by the supply we plug an old disk drive into another one of the Molex connectors The current drawn by the disk drive sinks enough current to make the switchers in the power supply happy The P1 connector is rated to 13 A far more current than the DN3000k10S can use The DN3000K10S when used stand alone has the following different power rails 5 3 3 1 5 12 V 1 12 77 Figure 6 3 Molex Connector P1 Auxiliary Power The DINI Group Power Supplies and Power Distribution vs 1 Figure 6 4 Example Power Supply The power rail 12 V if needed by a daughter card can be supplied to the DN3000k10S using the Power Header J17 NOTE If you use the DN3000k10S stand alone with ATX power supply the DN3000k10S may not draw enough current to meet the minimum current required by the switchers in the supply Connecting a disk drive to another connector will solve this problem By specification a PCI board may consume a maximum of 25 watts from the fingers of the PCI connector This power limit is below that the DN3000k10S is capable of consuming even if daughter cards and or large SDRAM banks are installed The P1 connector can be used to augment the power obtained from the PCI fingers P1 can b
145. texll family More information be gleaned from the Virtexll Datasheet VirtexII Datasheet pdf the Virtexll User s Guide VirtexII UserGuide pdf Both files are on the CD ROM supplied with the DN3000k10S but you are better off getting the latest versions from the Xilinx Web page http www xilinx com Make sure to get the latest errata sheet also Flip Flops and Figure 2 2 shows what Xilinx calls a slice Each slice contains 2 flip flops A LUTs configurable logic block CLB contains 4 slices The XC2V6000 is a 96 x 88 grid of CLBs Therefore the XC2V6000 contains 67 584 flip flops This flip flop count does not include the six flip flops contained in each I O block Each flip flop has a 4 x 1 look up table LUT An LUT can do any Boolean function of the four inputs The rest of the multiplexers allow for carry chains and other functions An overview of the Virtexll Architecture is shown in Figure 2 3 Embedded Virtexll has boatloads of embedded memory The XC2V6000 contains 144 Memory 18 Kbit blocks Each memory block can be configured as 16K x 1 2K x 9 8K x 2 1K x 18 4 or 512 x 36 Remember that unused LUTs may also be used as memory Xilinx refers to the embedded memory as Block SelectRAM and to the LUT based memory as Distributed Memory The DN3000k10S User s Manual 2 3 DN3000k10S Features Overview and General Description LUT gt inputs gt gt ae 1 gt Fics inputs
146. the 3000 10 2 17 J1 CPLD JTAG Configuration FPGA Serial Configuration and FPGA JTAG Configuration 2 18 J27 RS232 Port Assembly Drawing 2 22 Delkin 32 MB 3 3 V Smart Media 2 29 FPGA Pin Connections for PCI Signals 3 2 PCI PCI X Edge 3 3 DN3000k10S 3 4 J31 PCI X Present Header 3 5 PCI X Capability 3 6 Clock Distribution Block 4 2 Clock Grid cecus uve 4 4 Common Clock 5 4 5 PECL Clock Input and Termination 4 6 External Ribbon Cable Connections 4 7 Functional Diagram of Roboclockll 1 and Roboclockll 2 4 8 Header 4 9 Clock OE Pin Jumper Settings 4 15 FPGA Interconnect Block Diagram 5 2 SSRAM 1 018 Bus 5 3 SSRAM 2 U17 Bus 5 4 SSRAM U15 Bus 5 5 Syncburst vere ae a E es 5 7 Synicburst PL csvset ee Roe pare eee 5 7 Syncburst 2 5 8 vi
147. the result of a resistor division or R16 and R15 The 3000 105 is shipped with 30 ohm 1 resistors size 1210 in these locations resulting in an AREF voltage of AVCC 2 or approx imately 1 65 V If you wish to supply your own AVCC and VREF voltages remove L1 R15 and R16 and input your signals on J4 pins 18 and 20 Remember that the ATmega128 also has an internal reference voltage of 2 56 V If you use the internal 2 56 V reference leave C45 stuffed Atmel documents state that externally decoupling AREF will improve the noise performance of the A D 9 7 7 UPADCO UPADG1 PF ADCO PF1 ADC1 UPADC2 PF2 ADC2 UPADC3 58 PF3 ADC3 UPADC4 PF4 ADC4 UPADC5 56 1 PF5 ADC5 UPADCG 3 UPAD gt gt PF6 ADC6 5 PF7 ADC7 HDR10X2 ATmega103L 4AC Figure 2 7 J4 Analog to Digital Connections DN3000k10S User s Manual 2 11 DN3000k10S Features Overview and General Description ALE RD WR AREF AGND AVCC ADO PAO AD1 PA1 AD2 PA2 J3 Unused pP Connections 2 12 R16 30 0 1 1210 C45 R15 0 1 30 0 1 1210 Figure 2 8 AVCC Connections J3 contains connections to the ATmega128L that were not used elsewhere These ten connections can be used for external TTL connections to the pP externally generated interrupts or any other function that the ATmega128L supports on these pins Remember that the ATmega128L is not 5 V tolerant so if you att
148. thout written authority from the proprietor ELECTRONICS sous quelque forme que ce soit sons autorisation ecrite du propietaire Propriete de C BERG ELECTRONICS Droits de reproduction BERG ELECTRONICS INC Copyright BERG ELECTRONICS INC Property of C BERG ELECTRONICS PRODUCT NO OF NUMBER A 1 930 50 95 91403 001 1403 001 830 21 08 725 18 42 1 550 39 37 91403 002 1403 002 1465 093 2 430 61 72 2 930 74 42 2 050 52 07 1 700 43 18 965 2451 30 2200 5588 1 215 30 86 30 cxr 2 550 64 77 51405 402 2 430 61 72 2 930 74 42 RO 110 R2 79 0 220 5 58 REF 2X FRAME TO BOARD CONTACT AREA 4 003 0 08 0 050 61 27 3 903 007 Tg 204 18 SAG 1604 06 REF form 7530 001 103 2 700 68 58 1 465 37 21 30 2 200 55 88 1 215 30 86 2 700 68 58 1 465 37 21 DIM C 2 050 1 27 025 0 63 100 2 54 gr 0000000000000000000000000000000000000000 4 002 05 0 015 0 38 001 ox 41010 41 160 4 06 0 075 1 91 REF 2X DIM B DIM G 0 053 1 33 REF 2X 090 2 29 0 050 1 27 0 045 91 14 003 0 08 2 000 0 0 Ex PROPOSED TERMINATION REQUIREMENTS 480 12 19 mat l code tolerances unless otherwise specified XX_ 01 date linear 005 NOTES MATERIALS DIELECT
149. tions to DN3000k10SD Observation Daughter Card for 200 Options Resistors R10 and R11 can be used to select different voltage sources 5 V or 43 3 V respectively When used U4 must be removed in order to prevent contention NOTE Never populate R10 R11 simultaneously this will result in a shorted power supply Power Rating Connector J8 Table 7 1 shows the connections of J8 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A 12 V power supply is rated for 0 5 A 12 V power supply is rated for 0 5 Table 7 1 Connector J8 Pins External Power Function gt Function 2 3 4 5 6 7 8 9 gt DN3000k10S User s Manual Daughter Connections to DN3000k10SD Observation Daughter Card for 200 Connectors LVDS Connector J2 Unbuffered I O Connectors J3 J4 Connector J5 J6 J7 7 6 Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards NOTE Not available
150. to at least 2 Otherwise the Roboclockll s will output garbage Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing oscillators in X1 and X2 The DN3000k10S is shipped with a 14 318 MHz oscillator in location X1 and 100 MHz oscillator in X2 The Roboclockll s not 5 V tolerant so 43 3 V oscillators are necessary NOTE If you stuff your own oscillators 3 3 V CMOS outputs are neces sary since the Roboclockll s are not 5 V signalling tolerant We get our oscillators from Digi Key http www digikey com Of note is an Epson line of oscillators called the SG 8002 Programmable Oscilla tors Any frequency between 1 00 MHz 106 25 MHz can be procured in the normal Digi Key shipping time of 24 hours A half can 43 3 V CMOS version is needed with a tolerance of 50 ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND package SG 531 output enable 3 3V CMOS 50ppm If the order is placed via the web page the requested frequency to two decimal places is placed in the Web Order Notes The datasheet is on the CD ROM for this oscillator The file name is SG8002DC pdf The DINI Group Clocks and Clock Distribution Any polarity of output enabled for each oscillator on pin 1 is acceptable Make sure that you have the proper jumper settings at positions 9 and 10 of J14 J15 and J16 See Figure 4 8 and Figure 4 9 for a descri
151. turn you to the main menu Read Memory Byte Read a single byte from a specific PCI memory location Figure 9 12 Input address fb000000 b000000 1 Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Please select Figure 9 12 AETEST Read Memory Byte You will be prompted for the memory location in hex The physical address is needed All 4 gigabytes of PCI memory can be read Three options are available 1 Read once and display 2 Read indefinitely and display 3 Read indefinitely and don t display Write Read Memory Byte write and read a single DWORD from a specific memory location After entering a memory address hex 32 bits you specify how many DWORDS you want written and read back and the data Then you choose from the 3 options as above The menu option does not perform any data checking Figure 9 13 Numbers of long words to write in decimal 2 byte to write in hex 88888888 byte to write in hex 99999999 l Display result 2 Display result and loop indefinitely 3 Don t display result and loop indefinitely Please select Figure 9 13 AETEST WritelRead Memory Byte Memory test on SSRAM1 Tests one of the SSRAM chips on the DN3000k10 Memory test on SSRAM2 Tests one of the SSRAM chips on the DN3000k10 Memory test on SSRAMS Tests one of the SSRAM chips on the DN3000k10 Memory test on SDRAM Tests the SDRAM ch
152. ure 2 6 Block Diagram of ATmega128L and 105 Interfaces A D Analog to Digital Converter 2 10 J4 connects to the A D inputs of the ATmega128L Header pins for AVCC and AREF are also provided if you wish to use AVCC elsewhere or want to provide a cleaner AREF to the uP The odd pins of J4 are grounded making for a clean connection with an IDC cable The eight A D pins UPADC 7 01 may also be used as TTL I O UPADC 7 4 also may be used to connect to the JTAG port of the ATmega128L See ATmega128L JTAG Interface on page 2 12 According to Atmel documentation the following features apply to the A D e 10 bit Resolution e 0 5 LSB Integral Non linearity The DINI Group DN3000k10S Features Overview and General Description 2 LSB Absolute Accuracy 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 ADC Input Voltage Range Selectable Internal 2 56 V ADC Reference Voltage Free Running or Single Conversion Mode Interrupt on ADC Conversion Complete Sleep Mode Noise Canceller The J4 Connections are shown in Figure 2 7 The AVCC port connections are shown in Figure 2 8 3 3 V is filtered via 100 L1 inductor 100pF capacitor C47 and 0 1 capacitor C46 as shown in Figure 2 8 The output is AVCC analog VCC Inductor L1 is rated 120 ma VREF is
153. ution Chapter 4 Clocks and Clock Distribution Functional Overview The DN3000k10S ASIC emulation board has a flexible and configurable clock scheme Figure 4 1 is a block diagram showing the clocking resources and connections The clocking structures for the DN3000k10S include the following features e 2user selectable socketed oscillators X1 X2 148 MHz oscillator X3 e 2 CY7B993 or CY7B994 RoboclocklI Multi Phase PLL Clock Buffers 2FCT3807 Low Skew Clock Buffers The Clock Grid J20 J22 a 5X3 0 1 in header distributes clock signals to two FCT3807 clock buffers and two RoboclocklI PLL clock buffers CY7B993 or CY7B994 The clock outputs from the buffers are dispersed throughout the board Two 3 3 V half can oscillator sockets X1 and X2 and the signal CLKOUT from the CPLD provide on board input clock solutions The DN3000k10S is shipped with both a 14 318 MHz X1 and a 100 MHz X2 oscillator Neither X1 nor X2 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillator in the X1 and X2 posi tions more detail later in Customizing the Oscillators on page 4 14 The Clock Grid can also accept a 5X2 ribbon cable This cable can provide input clocks to both of the Roboclockll s and one of the 3807 buffers The FCT3807 clock buffer provides a high speed 1 to 10 buffer with low skew 0 35 ns allowing clocks A ACLK 3 0 and B BCLK 3 0 to be distributed
154. v is in the sparc sub directory and run sh dndev uninstall sh 2 Touninstall the driver run sh dndev uninstall sh 3 Torun the test utility run aetest solaris asroot after the driver is loaded The driver is compiled with the gcc compiler aetest solaris is compiled with gmake You can download it from the GNU website The make from the Solaris installation does not work with our makefile format You may need to make aetest solaris executable run chmod u x aetest solaris DN3000k10S User s Manual 9 3 Utilities AETEST Options Description and Definitions Installation Instructions for Windows 98 ME There are two ways to run AETEST You can run the DOS version aetestdj exe directly or you can run AETEST with a device driver To run AETEST with a device driver follow the steps below 1 Choose a default PCI driver for the device When Windows first starts with the device plugged in it should ask for a device driver Select Specify the location of the driver Select Display a list of the drivers in a specifice location Select Other devices Under Manufacturers tab select unknown device Under Models select unsupported device OF uui UJ The driver file pcifg vxd and aetest98 exe must be in the same directory Run aetest98 exe NOTE To re compile the driver file pcicfg vxd you need the VtoolsD compiler from www numega com Startup When AETEST is fir
155. various erratas updates and white papers DN3000k10S User s Manual 2 7 DN3000k10S Features Overview and General Description 2 8 available at the Xilinx web site http www xilinx com Also our most updated information regarding using Virtex Il devices with encryption can be found at our web site at http www dinigroup com products 3000k10ns html As of now encryption is fully supported using the JTAG chain program ming the parts Encryption using SmartMedia programming will be supported soon We have found several undocumented features of the Xilinx Virtex Il parts with SelectMAP programming that we are now working to accommodate Note that encryption and partial reconfiguration are mutually exclusive You can do one or the other but not both There is also a previous errata on the sizes of bit files generated for Virtex II parts being larger than the originally intended size by approximately 10 This does NOT apply to encrypted bitstreams The size of an encrypted bit file is the originally intended size For more detailed information regarding Virtex II parts and encryption see our Encrypted Bitstream documentation at http www dinigroup com products 3000k10ns html Programming Encrypted Bitstreams Using JTAG 1 Creating the Encrypted Bitstreams A new option has been added to the Xilinx bitgen utility for all devices that support encryption Add the g Encrypt Yes option to the bitgen command line see Xili
156. vice fun 7f 0 and Display Vendor and Device ID Reads and displays the Vendor ID and Device ID of the active device number and function number Repeats this action until the user hits a key to stop it DN3000k10S User s Manual 9 7 Utilities Loop on PCI device fun 7f 0 and Don t Display Vendor and Device ID Same as previous menu option except doesn t display results This menu option is useful when using an oscilloscope to debug configuration reads Loop on all PCI device numbers and Display Device Vendor ID s Loops on each device number reading the Vendor ID and Device ID for each It moves onto the next device number when you press any key That is it continually reads the Vendor ID and Device ID from device number 0 until you hit a key at which point it continually reads the Vendor ID and Device ID from device number 1 It moves all the way through device number 0 to device number 0x7F in case there are any bridges on your PCI bus Display all PCI information for PCI device function 71 0 Reads and displays all of the configuration space for the active device and function number Use options S and F to change between the active device number and function number and then use this option to view the entire configuration space Write config uration DWORD Allows write to configuration space The following text will appear to remind you what is in configuration space for a PCI device PCI CS VENDOR ID 0x00 POI CS

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