ECP Standard Parallel Interface for DSP56300 Devices
Contents
1. read JELE nREVERSEREQUEST x hdr Wait for nRevReq line to bset x hdr go high and then sets the PeriphClk line rdi jclr nREVERSEREQUEST x hdr time out rd Check if nRevReq is low and if so a time out condition occured jset HOSTCLK x hdr rd1 If HostClk is low then Sets PerphClk and bset PERIPHACK x hdr continue rd2 jclr nREVERSEREQUEST x hdr read end JELE HOSTCLK x hdr rd2 Wait for HostClk to go bsr data in high and then samples the data bus time out rd bclr PERIPHACK x hdr Reset the PeripAck line read_end res data_in move x hdr a0 Get one byte from data extractu 58000 bus and store it in a0 rts 5 1 3 Reverse Data For the ECP reverse data cycle the DSP implements a write routine in accordance with the corresponding ECP protocol specifications Figure 7 is a flowchart of the read routine 12 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA Implementation on the DSP Side Start Write Yes nRevR eq HIGH nAckRev LOW Call DataOut PeriphAck HIGH PeriphClk LOW lt HostAck LOW No PeriphClk HIGH nRevR eq HIGH No No Call Lineln PeriphAck LOW nAckRev HIGH END Write Figure 7 ECP Write Routine Flowchart M MOTOROLA ECP Interface Implementation Software 132. Base 1 Status Register Read Reflects the inputs on the parallel port interface Base 2 Control Register Read Write Directly controls several output signals sets the direc tion of communication and enables an interrupt on the rising edge Base 400h Data FIFO Parallel Port FIFO Mode Read Write In Parallel Port FIFO Mode any data written to the Data FIFO is sent to the peripheral using the SPP handshake hardware generates the handshaking required Data FIFO ECP Mode Read Write When data direction is 0 output to peripheral bytes written or DMAed from the system to this FIFO are transmitted to the peripheral by hardware handshake using the ECP parallel port protocol When data direc tion is 1 input from peripheral bytes from the periph eral are read into this FIFO under automatic hardware handshake from ECP Test FIFO Test Mode Read Write Data can be read written or DMAed to or from the system to this FIFO in any direction data is not trans mitted to the parallel port lines using a hardware pro tocol handshake but can be displayed on the parallel port data lines Configuration Register A Configuration Mode Read Write Indicates if the card generates level or edge trig gered interrupts and the bus widths within the card and determines if there are any bytes left in the FIFO Configuration Register A is accessible only when the ECP Portis in Configuration Mode Base 401h Configuration Reg
3. ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA ECP Handshaking Protocols HostClk PeriphAck HostAck id C Figure 2 ECP Forward Command Cycle 3 2 3 ECP Reverse Data Cycle In the reverse data cycle the peripheral sends a single byte of data to the host There are eight steps specified for the reverse data cycle 1 Host sets nReverseRequest Low to request a reverse channel Peripheral asserts nAckReverse low to acknowledge reverse channel request Peripheral places data on data lines Peripheral pulls PeriphAck high to select data cycle Peripheral pulls PeriphCIk low to indicate that valid data is present Host pulls HostAck high to acknowledge that valid data is present zd gy AD Ae o s p Peripheral pulls PeriphClk high The ve edge is used to shift data into the host oo Host deasserts HostAck low to acknowledgment receipt of the byte These steps are illustrated in Figure 3 nReverse Request N nACkR everse N PeriphClk HostAck PeriphAck Figure 3 ECP Reverse Data Cycle M MOTOROLA ECP Standard Specifications 5 3 2 4 ECP Reverse Command Cycle In the reverse command cycle the peripheral sends a channel address to the host There are eight steps specified for the reverse command cycle l Wu 90 Host sets nReverseRequest Low to request a reverse channel Peripheral asserts nAc
4. The write routine performs a non blocking scan on the nReverseRequest data direction handshake line If the line is high indicating that the host is in the Forward Data phase of ECP operation and is not ready to receive the data byte from the DSP the program exits the write routine and goes to the read routine Otherwise the write routine sends the byte out on the ECP data bus The code for the write routine is given in Example 3 write wrl wr2 Example 3 ECP Write Routine Code jset bclr VERSE x bsr data out bset PERIPHACK x hdr bclr PERIPHCLK x hdr jset nREVERSEREQUEST x hdr time out wr jclr STACK X hdr wrl RI bset PHC U K x hdr nREVERSEREQUEST x hdr write end If nRevReq line is low exit from write routine else reset nAckRev output the data on data lines Assert PeriphAck de assert PeripClk Wait for HostAck to go high and set PeripClk jset nREVERSEREQUEST x hdr time out wr jset HOSTACK x hdr wr2 time out wr bsr line in bclr PERIPHACK x hdr bset nACKREVERSE x hdr write_end rts data_out move a0 x0 move x hdr a0 insert 8000 x0 a move a0 x hdr move x hddr al or Sff a movev al x hddr rts Wait for HostAck to go low Switch the data bus direction to in Reset PeriphAck and Set nAckRev Ta
5. DSP The Host Interface data lines HADO HAD7 are assigned to the ECP data bus 00 07 The ECP handshake signals are connected to the HIO8 port as shown in Table 3 Table 3 ECP to HI08 Pin Assignments ECP Signal Direction 08 Signal HostClk p gt HAS A0 Data 0 7 qp HADO HAD7 PeriphClk lt q HA8 Al PeriphAck lt q HA9A2 nAckReverse HRW RD HostAck p HDS WR nReverseR equest HCS A10 In some cases the electrical signal coupling between the DSP and the host computer may require voltage level shifters to accommodate the 3 3 V DSP56300 family I O port voltage levels and the 5V TTL parallel interface signals of the host computer Tests run with the ECP implementation on the DSP56303 issued satisfactory results without such voltage level interface buffers but special care must be taken with each DSP56300 family device 8 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA Implementation on the DSP Side 5 ECP Interface Implementation Software The ECP handshake signals required to control data transactions between the DSP and the host computer can be generated either in hardware using a customized ECP controller or in software This section describes the latter approach for the DSP side in which software polls the HIO8 port to generate the ECP handshake signals The host side employs a hardware controller but does require some initi
6. Standard Parallel Interface for DSP56300 Devices M MOTOROLA Buffered Transmission Example 6 Host Side Performance Evaluation Routine void main 4 unsigned char ch old_ch int error_no 0 i time t tl t2 long 1 init ecp Initialize the ECP controller init read Place ECP in Reverse phase while fifo empty 0 Wait for ECP FIFO to receive a byte old ch inb b 0 400 Read that byte tl time NULL Store the transfer begin time for 1 0 1 lt 4096000 1 while fifo_full Wait for ECP FIFO to fill for 1 0 1 lt 16 1 ch inb b_addr 0x400 Read a byte if ch old_ch Compare with previous value error_not and increment the error counter old_ch ch if an error occured t2 time NULL Store the transfer end time printf nErrors d error_no Display the error counter and printf MnSpeed f double 4096000 0 16 0 t2 t1 transfer speed Again a similar algorithm is employed for the ECP forward mode A test system incorporating the programs in Example 5 and Example 6 was run in both forward and reverse mode yielding results shown in Table 4 Table 4 ECP Performance Evaluation Results for Single Byte Transfers Transfer Direction Byte Count Transfer Rate Error Count Forward Mode 62 5 Mega 590 KBps 0 Reverse Mode 62 5 Mega 451 KBps 0 The difference between the forward mode and reverse mode transfer ra
7. in software as well The ECP handshaking protocol features the following four cycles Forward Data Reverse Data Forward Command Reverse Command M MOTOROLA ECP Standard Specifications 3 2 1 ECP Forward Data Cycle In the forward data cycle the host sends a single byte of compressed data to the peripheral This cycle consists of six steps 1 2 3 4 5 6 Host places data on data lines Host asserts HostAck to indicate the start of a data cycle Host asserts HostClk to low to indicate valid data Peripheral asserts PeriphAck to acknowledge valid Host deasserts HostClk high The ve edge is used to shift data into the peripheral Peripheral de asserts PeriphAck to acknowledge receiving the byte These steps are illustrated in Figure 1 HostClk PeriphAck X HostAck I N A a Figure 1 ECP Forward Data Cycle 3 2 2 ECP Forward Command Cycle In the forward command cycle the host sends a channel address to the peripheral This cycle consists of six steps 1 2 3 4 5 6 Host places data on data lines Host deasserts HostAck to indicate the start of a command cycle Host asserts HostClk low to indicate valid data Peripheral asserts PeriphAck to acknowledge valid data Host deasserts HostClk high The ve edge is used to shift data into the peripheral Peripheral deasserts PeriphAck to acknowledge receiving the byte These steps are illustrated in Figure 2
8. A Introduction 1 3 ECP Standard Specifications The Extended Capabilities Port is a fast bidirectional parallel interface developed by Microsoft and Hewlett Packard It is backward compatible with the existing PC standard parallel port SPP configurations using the existing parallel connectors and cables Pre existing parallel communication methods utilized a wide variety of hardware and software interfaces each with unique and incompatible signaling schemes The ECP standard was developed to provide a standard open path for communications between computers and more intelligent printers and peripherals The availability of this standard bidirectional protocol encourages the development of new peripherals that can return both data and status to the host computer The ECP protocol generates handshake signals identical to those of the Extended Parallel Port EPP and runs at the same speed as EPP It also supports Run Length Encoding RLE to achieve data compression ratios up to 64 1 In summary the ECP provides the following features High performance half duplex forward and reverse channel e Interlocked handshake for fast reliable data transfer e Optional single byte RLE compression for improved throughput e Channel addressing for low cost peripherals e Active output drivers e Adaptive signal timing e Peer to peer capability The ECP provides three operational modes for compatibility with various systems e Compatible mode asynchr
9. C Dunnihoo Application Note 4 17 Revision 13 January 1994 Standard Microsystems Corporation M MOTOROLA About the Authors 21 22 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA
10. ECP Standard Parallel Interface for DSP56300 Devices Application Note by Mihai V Micea Dan Chiciudean and Lucian Muntean AN2085 D Rev 0 11 2000 MOTOROLA This document contains information on a new product Specifications and information herein are subjectto change without notice Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warran the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the applic specifically disclaims any and all liability including without limitation consequential or incidental damages Typica ty representation or guarantee regarding ation or use of any product or circuit and parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the Motoro a product could create a situation where personal injury or death may occu
11. MA Controller 19 7 a Reads the DMADIR to determine the direction of data transfer b Prepares the data buffer to be sent c Configures the on chip DMA controller with the start address of the data buffer and the total number of data words d Starts the DMA transfer and asserts DMAACK DSP resumes the current program execution while the DMA transfer is performed in parallel When the buffer is transferred the on board DMA controller issues an internal interrupt The DSP interrupted to assert TC end of DMA transfer and reset the internal DMA controller DSP resumes the execution of the current program A similar operation is executed for an ECP forward data cycle initiated by the host 8 Conclusion The ECP interface enables medium to high speed parallel data transfers between a host computer and a DSP based application without the physical limitations of a direct connection between the data buses of the host and DSP This solution is easy to implement requiring little or no additional hardware beyond the standard DB25 parallel connector and minimal software development System performance can be enhanced by using DMA transfers between the host ECP controller and the DSP 20 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA Buffered Transmission 9 About the Authors Mihai V Micea is a lecturer at the Computer Software and Engineering Department at the Politehnica University of Timisoara and Exe
12. aS as 6 4 ECP Interface Implementation Hardware 8 5 ECP Interface Implementation Software 9 5 1 Implementation on the DSP 1 9 5 1 1 ero D e MCA TO 0 9 5 1 2 Forward Data cs eee TR duse ret ie E dt 10 5 1 3 Keyerse Data d rad ien Schweden A RAT ders 12 52 ECP Programming on the Host 51 14 6 Performance Evaluation of the ECP Interface 16 6 1 Single Byte Transmission 125 tu velas tt rear Dali das edu 16 6 2 Buffered 1 17 7 Boosting Performance with Controller 18 M moroROLA Abstract and Contents ii 8 Conclusion ooo e Sou dud oe ew She x VA Em n ue n oes 20 9 About the Authors 21 10 References 21 ECP Standard Parallel Interface for DSP56300 Devices M moroROLA 1 Introduction An important set of real life digital signal processing applications involves a host computer functioning as a system controller or interactive graphical user interface In these applications reliable high speed data communication between the DSP and the host computer is an important de
13. advantage is that many DSP based evaluation modules use the DSP serial port for code development and debugging making it difficult to develop a DSP program that can initiate serial data transactions autonomously with a host computer For high performance parallel data transfers the DSP56300 family provides a full duplex double buffered parallel port called the Host Interface This interface is either 8 bits or 32 bits wide depending on the particular DSP device selected The HIO8 HI32 can connect directly to the data bus of a host processor or computer with minimal glue logic allowing direct data links to microcontrollers such as the Motorola HC11 or the Intel 8051 family as well as to microprocessors such as the Motorola 68k family or Intel x86 family The Host Interface can easily connect with the high speed ISA or PCI bus on a PC to form a communication channel that is substantially faster than a serial connection up to 16 MBps for the ISA bus for example However this solution requires a very close physical connection which drastically reduces overall system flexibility A good compromise between maximum data transfer speed and system flexibility is the parallel cable interconnection The standard PC protocol for high performance parallel communication is the Extended Capabilities Port ECP This document describes the hardware and software implementation of the ECP Standard with the HIO8 port of a DSP56300 family device M MOTOROL
14. alization software which is also described 5 1 Implementation on the DSP Side The ECP standard defines four main protocol phases ECP forward data and reverse data cycles for data transactions and ECP forward command and reverse command cycles to indicate single byte data compression or channel address This section presents DSP software for the two data cycles which are the basic requirement for the ECP communication as well as an initialization routine 5 1 1 Initialization The DSP initialization routine includes e Configuring the HIO8 port as GPIO e Setting the direction of each line used for handshaking Generating the correct logical levels on the output lines e Initializing the HIO8 lines that connect to the ECP data bus as inputs The code for this routine is presented in Example 1 M MOTOROLA ECP Interface Implementation Software 9 Example 1 hpcr equ Sffffc4 hddr equ Sffffc8 hdr equ Sffffc9 HOSTCLK EQU 8 PERIPHCLK EQU 9 PERIPHACK EQU 10 nACKREVERSE EQU 11 HOSTACK EQU 12 nREVERSEREQUEST EQU 13 init ecp bset 0 x hpcr bclr HOSTCLK x hddr bset PERIPHCLK x hddr bset PERIPHCLK x hdr bset PERIPHACK x hddr bclr PERIPHACK x hdr bset nACKREVERSE x hddr bset nACKREVERSE x hdr bclr HOSTACK x hddr bclr nREVERSEREQUEST x hddr bsr line_in rts line_in move x hddr a and S 00 a move a x hddr ECP Ini
15. cates valid data atthe host When this pin is de asserted the ve clock edge should be used to shift the data into the peripheral 2 9 Data 0 7 Data 0 7 1 0 Bidirectional data bus 10 Ack PeriphCLK Input A low on this line indicates valid data atthe peripheral When this pin is deasserted the ve clock edge should be used to shift the data into the host 11 Busy PeriphAck Input In reverse channel operation a high on this pin indicates a data cycle while a low indicates a command cycle In forward channel operation the pin functions as P eriphAck 12 Paper Out End nAckReverse Input The peripheral pulls this pin low to acknowledge a reverse request 13 Select X Flag Input Extensibility Flag 14 Auto Linefeed Host Ack Output In forward channel operation a high on this pin indicates a data cycle while a low indicates a command cycle In reverse channel operation the pin functions as HostAck 15 Error Fault PeriphRequest Input The peripheral pulls this pin low to indicate that reverse data is available 16 Initialize nR everseR equest Output This pin is pulled low to indicate that data is in the reverse direction 17 Select P rinter 1284 Active Output The host pulls this pin high to indicate 1284 transfer mode and pulls the pin low to terminate 18 25 Ground Ground GND Ground 3 2 ECP Handshaking Protocols The ECP can be fully implemented by hardware with custom parallel communication controllers It can be implemented
16. cutive Director of the DSP Applications Lab Timisoara DALT sponsored by Digital DNA from Motorola Dan Chiciudean and Lucian Muntean are students at the Automation and Computer Science Faculty at the Politehnica University of Timisoara and members of the research and development team at DALT Contacts e micha dsplabs utt ro http dsplabs utt ro dalt 10 References 1 DSP56300 Family User s Manual order number DSP56300FM AD Motorola Incorporated 1999 2 DSP56303EVM User s Manual order number DSP56303EMUM AD Motorola Incorporated 1999 3 DSP56307EVM User s Manual order number DSP56307EVMUM D Motorola Incorporated 1999 4 DSP5630x Port A Programming Application Note order number AN1751 D Motorola Incorporated 1999 5 Motorola DSP Assembler Reference Manual Motorola Incorporated 1996 6 IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers Draft D1 1 November 5 1999 Institute of Electrical and Electronic Engineers Inc 7 Extended Capabilities Port Specifications Revision 1 06 July 14 1993 Microsoft Corporation 8 Interfacing the PC Interfacing the Extended Capabilities Port Craig Peacock February 28 2000 Internet Resource 9 W91284PIC IEEE 1284 Peripheral Interface Controller Data Sheet Revision 4 00 29 October 1999 Warp Nine Engineering 10 High Performance ECP EPP Printer Interface Using the PPC34C60 PPIC Jeffrey
17. he ECP in Forward phase void init_write unsigned char x outh 0x34 b_addr 0x402 outh b_addr 2 amp 0x0C b_addr 2 b_addr 2 outh 0x34 b_addr 0x402 outh 0x75 b_addr 0x402 outb x 4 b_addr 2 while inb b_addr 1 amp 1 lt lt 6 Place the ECP in Reverse phase void init_read unsigned char x outb 0x34 b_addr 0x402 outb inb b_addr 2 0x20 b_addr 2 x inb b_addr 2 outb 0x75 b_addr 0x402 outb x amp 0xfb b_addr 2 while inb b_addr 1 amp 1 lt lt 5 Test if ECP FIFO is empty int fifo_empty return inb b_addr 0x402 amp 1 Test if ECP FIFO is full int fifo full return inb b 0 402 amp 2 M MOTOROLA ECP Interface Implementation Software 15 6 Performance Evaluation of the ECP Interface This section describes a time based data counting performance evaluation program for the ECP interface and presents results for forward and reverse data transfer modes To evaluate data communication performance through the ECP interface programs must be developed for both the host and the DSP The performance parameters of primary concern are the occurrence of errors during the transfer and the data transfer rate To determine the maximum transfer rate of the proposed ECP implementation a large amount of data must be sent through the parallel link with minimal interference from other act
18. ister B Configuration Mode Read Write Selects compression option RLE for outgoing data returns the status of the IRQ pin IRQ assignmentand DMA Channel assignment Configuration Register B is accessible only when the ECP Portis in Configura tion Mode Base 402h Extended Control Register Read Write Configures the ECP mode and returns the status of the ECP FIFO Modes of operation include Standard Mode Byte 5 2 Mode e Parallel Port FIFO Mode ECP FIFO Mode EPP Mode FIFO Test Mode Configuration Mode M MOTOROLA ECP Standard Specifications 7 4 ECP Interface Implementation Hardware The hardware connection between the PC and DSP is a standard DB25 parallel cable On the host side the cable connects to the standard parallel port configured for the ECP protocol On the DSP side the cable connects to a male DB25 header which is directly connected to the HI08 port as illustrated in Figure 5 Parallel DB25 Header 1 14 21 2 4 15 3 42 HA 16 30 HC 4 17 5 40 18 6 37 HA 19 1 36 HA 8 34 HA 21 9 22 10 32 HA 23 11 24 12 22 HR 25 13 SAO R WR DO D1 S A10 D2 D3 D4 D5 D6 D7 8 Al 9 A2 W RD Motorola DSP563xx Figure 5 HIO8 to DB25 Header Interconnection In this implementation all HIOS signals are configured as General Purpose I O lines GPIO during the ECP initialization routine for the
19. ivities during the data transfer 6 1 Single Byte Transmission A first approach is to transmit one byte at a time For reverse mode the ECP test routine on the DSP side simply transmits a byte of data on the ECP in an infinite loop incrementing the value sent after each transferred byte Example 5 lists the reverse mode ECP test routine on the DSP Example 5 DSP Side Performance Evaluation Routine Single Byte Transfer Reverse Mode ECP test lest the ECP Reverse phas bsr init ecp Initialize the 8 again move b a jsr write Write a byte from a0 to the host inc b lncrement the valu jmp again Infinite loop A similar algorithm is used for the ECP forward mode The actual ECP performance evaluation program resides on the host computer The host routine measures the time it takes to transfer a large amount of data through the ECP interface checks the data and counts the errors that occur The routine for reverse mode evaluation includes the following steps 1 Initialize the host parallel port controller for ECP mode 2 Configure the ECP for reverse data mode to receive data from peripheral 3 When the port receives the first data byte start the communication timer and initialize the error counter 4 After receiving a predefined number of data bytes from the DSP calculate the overall data transfer speed and display the error count These steps are incorporated in the test routine in Example 6 16 ECP
20. kReverse low to acknowledge reverse channel request Peripheral places data on data lines Peripheral pulls PeriphAck low to select command cycle Peripheral pulls PeriphCIk low to indicate that valid data is present Host pulls HostAck high to acknowledge that valid data is present Peripheral pulls PeriphClk high The ve edge is used to shift data into the host Host deasserts HostAck low to acknowledgment receipt of the byte These steps are illustrated in Figure 4 everse nReverse Request PeriphCIk HostAck E PeriphAck N Figure 4 ECP Reverse Command Cycle 3 3 ECP Software Registers The software registers implemented in a standard PC on the host side of the ECP interface are listed in Table 2 The first 3 registers are identical to those in the Standard Parallel Port ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA ECP Software Registers Table 2 ECP Registers Address Port Name Read Write Description Base 0 Data SPP Read Write Standard parallel port data register Writing to this register in SPP mode drives data on the parallel port data lines In all other modes the drivers can be tri stated by setting the direction bit in the Control Register ECP Address FIFO ECP mode Read Write Data written to this address is placed in the FIFO and tagged as ECP Address RLE ECP port hardware transmits the byte to the peripheral automatically
21. ke the least 7 Significant byte from a0 and send it without modifying the most significant 7 byte from Host Data Register 5 2 ECP Programming on the Host Side The host computer generates the ECP communication protocol with a hardware controller on the motherboard so the only programming requirements are proper ECP controller initialization and a pair of routines for data transmission and reception between the ECP port and the user application Example 4 presents all the initialization routines needed for data communication through the host ECP port User applications should call these functions in a similar manner to the communication evaluation program described in Section 6 Performance Evaluation of the ECP Interface on page 16 14 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA ECP Programming on the Host Side Example 4 Host ECP Initialization Routines define b_addr 0x378 unsigned char Read_cnfg int reg return inb b_addr 0x400 reg void Write_cnfg int reg unsigned char x outb x b_addr 0x400 reg Write_cnfgA unsigned char x Write_cnfg 0 x Write_cnfgB unsigned char x Write_cnfg 1 x unsigned char Read_cnfgB void return Read cnfg 1 Initialize the parallel port in ECP mode void init_ecp outb 0x34 b_addr 0x402 outh 0xf4 b_addr 0x402 Write_cnfgA 0x14 Write_cnfgB Read cnfgB amp 0x7f Place t
22. onous byte wide forward channel host to peripheral parallel port interface Data and status lines are used according to the original SPP and EPP definitions e Nibble mode asynchronous byte wide reverse channel peripheral to host parallel port compatible with all existing PC hosts Data bytes are transmitted as two sequential 4 bit nibbles using four peripheral to host status lines e Byte mode asynchronous byte wide reverse channel using the eight data lines of the interface for data and the control status lines for handshaking compatible with IBM PS 2 hosts In addition the ECP offers e ECP mode fast bidirectional channel with or without RLE compression This mode requires custom hardware 3 1 ECP Hardware Description The Extended Capabilities Port uses the industry standard DB25 connector and is backward compatible with the SPP and EPP parallel standards When the ECP operates in SPP or EPP mode the data and handshake lines operate according to the SPP and EPP definitions When the port operates in ECP mode each of the DB25 connector pins has a unique function as listed in Table 1 2 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA ECP Handshaking Protocols Table 1 Pin Assignments for Extended Capabilities Parallel Port Connector Input SPP Signal ECP Signal Output Function 1 Strobe HostCLK Output A low on this line indi
23. outine described in Example 2 on page 12 To transfer 16 bit words the Send_Buffer routine can be modified as shown in Example 8 Similar modifications can be used for forward transfers and to send or receive 14 bit words Example 8 16 bit Word Buffer Send Routine Send_Buffer_16 move buffer do buf_len loop_sb move x r0 a0 bsr write extract 8008 a a Replace the 8 least significant bits in AO with the 7 next 8 more significant ones to be used further 7 by write bsr write loop_sb rts 7 Boosting Performance with a DMA Controller The performance of an ECP based communication system can be substantially enhanced by incorporating a dedicated ECP controller with a DMA interface into the DSP56300 based system A typical connection of a DMA capable ECP controller such as the PPC34C60 from Standard Microsystem Corporation or the W91284PIC from Warp Nine Engineering to a DSP56300 family processor is shown in Figure 8 18 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA Buffered Transmission Data La Eee Expansion Port Port Host ECP ntroller DSP563XX Controlle Interface Port Configured as GPIO Figure 8 Typical Connection of an ECP Controller to the DSP563xx As the master of the ECP data link the host computer uses the ECP control lines to select the type of data transfer forward or reverse and initiates the transaction
24. r Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against al and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated wi even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Acti All other tradenames trademarks and registered trademarks are the property of their respective owners claims costs damages and expenses h such unintended or unauthorized use on Employer How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola J apan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 J apan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Customer Focus Center 1 800 521 6274 HOME PAGE http motorola com semiconductors 80217 Copyright Motorola Inc 2000 Abstract and Contents The data communication between the DSP and a host computer is one of the important i
25. s Thus the ECP Controller always initiates the DMA cycles with the DSP by asserting DMAREQ DMA transfer request and DMADIR direction of the transfer The actual DMA transfer begins when the DSP asserts DMAACK DMA transfer acknowledge and CS The DMA transaction ends when the DSP asserts the TC terminal count signal On the DSP side some preliminary configuration and initialization is required to perform DMA transactions with the ECP controller including the following steps Port A Data lines are used for data transfers Port A Address lines specify the location of the transferred data Port A RD and WR signals command the read and write cycles respectively Port A AA One of the four Address Attribute 0 3 lines functions as the chip select signal for the ECP controller Interrupt line IRQ serves as the DMA request signal from the ECP controller An interrupt handler for the DMA request is installed Three HI08 Port B signals are configured as GPIO to function as follows DMAACK output DMADIR input TC output When the host initiates an ECP reverse data cycle i e reads a data buffer from the DSP the following steps are executed 1 2 3 Host configures the ECP controller and initiates the ECP reverse data cycles ECP controller asserts DMAREQ The DSP interrupts the execution of its current program and handles the corresponding interrupt as follows M MOTOROLA Boosting Performance with a D
26. sign and implementation issue This document describes the implementation of a high performance yet relatively simple parallel data communication protocol for a DSP connected to a PC The paper focuses on the implementation of the Extended Capabilities Port ECP parallel communication standard on the DSP56300 family processors Specific ECP communication protocols are described as well as hardware and software implementation details for both the DSP and the PC Performance evaluation routines designed for the ECP data link are also presented along with corresponding results and conclusions Details of the ECP standard can be found in the Microsoft document Extended Capabilities Port Specifications Revision 1 06 2 DSP Host Communication Tradeoffs The DSP56300 family features various data communication interfaces suitable for a large variety of system interconnections through its built in peripheral ports The Serial Communication Interface SCI provides a full duplex port for serial data transfers Using three dedicated signals Data Transmit Data Receive and Serial Clock this interface supports industry standard asynchronous bit rates and protocols up to 115200 bps as well as high speed synchronous data transmission up to 8 25 Mbps for a 66 MHz clock The primary disadvantage of a SCI based connection with a host computer is that the maximum data transfer rate is limited to 115200 bps by the computer s serial interface Another dis
27. ssues in designing DSP based systems directly connected to PCs which are commonly used as process controllers or as interactive user interfaces This application note proposes the implementation of a high performance yet relatively simple parallel data communication protocol for a DSP connected to a PC This document focuses on the implementation of the Extended Capabilities Port ECP parallel communication standard on the DSP56300 family processors Specific ECP communication protocols are described along with the characteristic hardware and software implementation details both on the DSP and on the PC side The performance evaluation routines designed for the ECP data link are also presented along with the corresponding results and conclusions 1 Introduction eee aes I Re Td det eh a pee 1 2 DSP Host Communication Tradeoffs 1 3 ECP Standard Specifications 2 3 1 ECP Hardware 2 32 Handshaking Protocols ib EA nike tease EE 3 321 BCP Porwart Data Cycler 255 dae ev Phe hy ete eA Phe 4 322 ECP Forward Command 1 4 3 2 3 ECP Reverse Data Cycle 5 3 2 4 ECP Reverse Command 1 6 3 3 ECP fan tat ee
28. tes in Table 4 is due to the fact that the reverse data routine requires more DSP instruction cycles than the forward data routine 6 2 Buffered Transmission A second more practical approach is to implement a buffered type data transfer through the ECP interface The code in Example 7 on page 18 is a simple DSP routine for reverse mode that transfers an entire buffer to the host computer In this example the buffer variable represents the base address of the data buffer to be sent and the buf variable represents the buffer length The routine scans the buffer in one step word increments and calls the ECP write routine described in Example 3 on page 14 to send the least significant byte of each word in the buffer to the host These routines can be interrupted by other asynchronous events such as timer interrupts serial or DMA transfers etc M MOTOROLA Performance Evaluation of the ECP Interface 17 Example 7 DSP Side Performance Evaluation Routine Buffer Transfer Reverse Mode Send Buffer move buffer Initialize pointer to the start of the buffer do buf_len loop_sb Initialize the Loop Counter LC Register with buffer length move x r0 a0 Prepare the current data word 24 bits to be sent bsr write Send the 8 least significant bits of AO register loop_sb rts In the same manner one can easily implement the corresponding Receive Buffer routine on the DSP using the read r
29. tialization Routine Host Port Control Register Address Host Data Direction Register address Host Data Register address The next 6 equates are used for addressing the handshaking lines in Host Data Register Configures the 8 data lines aS inputs rts 5 1 2 Forward Data For the ECP forward data cycle the DSP implements a read routine which is called each time a byte is to be transferred from the host to the DSP Figure 6 is a flowchart of the read routine 10 ECP Standard Parallel Interface for DSP56300 Devices M MOTOROLA Implementation on the DSP Side Start Read nRevR eq LOW No PeriphCIk HIGH nRevR eq LOW No No PeriphAck HIGH nRevR eq LOW No Call Read Data PeriphAck LOW Figure 6 ECP Read Routine Flowchart In accordance with ECP specifications the read routine performs a blocking scan of the nReverseRequest data direction and HostClk data valid lines If the host pulls the data direction line low indicating a host request to read data from the DSP a time out condition occurs the program exits the read routine and goes to the write routine Otherwise the read routine waits for a byte to be sent by the host indicated by a high on the HostClk line The code for the read routine is given in Example 2 on page 12 M MOTOROLA ECP Interface Implementation Software 1 Example 2 ECP Read Routine
Download Pdf Manuals
Related Search