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Xilinx DS861 LogiCORE IP Interleaver/De

1. XCO Parameter Valid Values has_col_sel_valid true false has_col_valid true false component_name Aha nee it aera based upon the following character set has_fdo true false memory_style automatic distributed block minimum_columns Integer in the range defined in Table 3 default value is 15 minimum_rows Integer in the range defined in Table 3 default value is 15 mode interleaver deinterleaver number_of_branches Integer in the range defined in Table 3 default value is 16 number_of_columns constant selectable variable number_of_columns_ constant_ value Integer in the range defined in Table 3 default value is 15 number_of_columns_ selectable value Integer in the range defined in Table 3 default value is 4 number_of_ F s configurations Integer in the range defined in Table 3 default values is 1 number_of_rows constant selectable variable number_of_rows_ constant_ value Integer in the range defined in Table 3 default value is 15 number_of_rows_ selectable value Integer in the range defined in Table 3 default value is 4 pipelining minimum maximum medium has_rdy true false row_permutations none use_coe_file_to_define_row_permutations row_port_width Integer in the range defined in Table 3 default value is 4 has_row_sel_valid true false has_row_valid true false has_aresetn true false symbol_memory internal external symbo
2. XILINX LogiCORE IP Interleaver De Interleaver v7 0 Internal to FPGA I External to FPGA Interleaver Core l s_axis_ctrl_tvalid m_axis_data_tvalid s_axis_ctrl_tready m_axis_data_tready s_axis_ctrl_tdata m_axis_data_tdata External Single Po rt RAM m_axis_data_tuser m_axis_data_tlast s_axis_data_tvalid s_axis_data_tready s_axis_data_tdata s_axis_data_tlast event_tlast_unexpected event_tlast_missing event_halted event_row_valid event_col_valid event_row_sel_valid event_col_sel_valid event_block_size_valid wr_addr wr_data rd_addr acik rd_data aresetn rd_en aclken DS861_23_081111 Figure 26 Connections to External Symbol RAM for Rectangular Interleaver Table 8 External Memory Pinout Table for Rectangular Cores Signal Direction Description RD_ADDR Output This is the address for the external symbol RAM As the RAM is only single port for the Rectangular Block Interleaver there only needs to be one address bus RD_ADDR and WR_ADDR are actually identical for the Rectangular Block Interleaver RD_DATA Input This is the read data bus from the external symbol RAM It has the same width as the DIN field in the Data Input Channel ignoring padding RD_EN Output This is the read enable for the RAM The Rectangular Block Interleaver uses only a single port symbol RAM and RD_EN is driven high all the time Note that it is high even when aclken is low so care must be taken if using it
3. 251 251 154 330 322 184 313 303 172 328 337 180 Notes 1 Area and maximum clock frequencies are provided as a guide They can vary with new releases of the Xilinx implementation tools 2 Clock frequency does not take clock jitter into account and should be derated by an amount appropriate to the clock source jitter specification 3 This is the total number of block RAMs used when map was run In reality two 18k block RAM primitives can usually be packed together giving an absolute minimum total block RAM usage of block RAMs 36k block RAMs 18k 2 rounded up DS861 October 19 2011 www xilinx com 49 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 21 Example Rectangular Block Implementations Parameter 3GPP2 F SPDCCH 3GPP2 F SPDCCH Mode Interleaver Interleaver Block Size Type Rows Columns Rows Columns Column Type Selectable Selectable Row Type Constant Constant Permutations Column Column Symbol Width 1 1 Pipelining Maximum Maximum Optional Pins and Fields None ACLKEN ARESETn RDY BLOCK_START BLOCK_END Memory Style Automatic Automatic Spartan 6 XC6SLX75 Test cases used an xc6sIx75 fgg484 with 2 speed grade device and ISE speed file version PRODUCTION 1 19 2011 07 25 Area LUT FF pairs 7 141 143 Block RAMs 36K 18K 9 0 1 0 1 o 246 246 Vi
4. XILINX LogiCORE IP Interleaver De Interleaver v7 0 Using the Symbol Interleaver De interleaver IP Core The CORE Generator GUI performs error checking on all input parameters Resource estimation and latency infor mation are also available Several files are produced when a core is generated and customized instantiation templates for Verilog and VHDL design flows are provided in the veo and vho files respectively For detailed instructions see the CORE Gener ator software documentation Simulation Models The Symbol Interleaver De interleaver core has a number of options for simulation models e VHDL behavioral model in the xilinxcorelib library e VHDL UNISIM structural model e Verilog UNISIM structural model The models required can be selected in the CORE Generator tool project options Xilinx recommends that simulations utilizing UNISIM based structural models are run using a resolution of 1 ps Some Xilinx library components require a 1 ps resolution to work properly in either functional or timing simulation The UNISIM based structural models might produce incorrect results if simulation with a resolution other than 1 ps See the Register Transfer Level RTL Simulation Using Xilinx Libraries section in Ref 1 This document is part of the ISE Software Manuals set available at www xilinx com support documentation dt_ise htm XCO Parameters Table 4 defines valid entries for the XCO parameters Parameters are not c
5. m_axis_data_tvalid i j l l l m_axis_data_tuser BLOCK_START l l l l l l m_axis_data_tuser BLOCK_END l a a S E E E lt lt a a event_block_size_valid i i i i s i i I I I l l I I 1 ke VALID Delay 5 clock cycles l l l 1 Figure 23 Response to Illegal Rectangular Blocks DS861 October 19 2011 www xilinx com 29 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 ak FLT LE LEPLEPLIELE LIL s_axis_ctrl_tvalid s_axis_ctrl_tdata BLOCK_SIZE s_axis_data_tvalid s_axis_data_tready s_axis_data_tdata DIN s_axis_data_tlast m_axis_data_tvalid m_axis_data_tuser BLOCK_START m_axis_data_tuser BLOCK_END event_block_size_valid le VALID Delay 5 clock cycles Figure 24 Response to Illegal Rectangular Blocks VALID Delay is not Affected by Waitstates External Symbol Memory The core can use internal or external memory to store the data symbols External memory might be necessary if there is insufficient block RAM left in the FPGA to implement a large interleaver The Convolutional Interleaver requires a dual port RAM with separate addresses for read and write ports The Rectangular Block interleaver requires only a single port RAM The connections for a Convolutional Interleaver example are shown in Figure 25 It is assumed th
6. Branch Length Constant 1 See Notes 1 2 Branch Lengths 1 See Notes 1 Rectangular Block Block Size Constant 6 65025 1 8 Block Size Width 3 16 1 Column Constant 2 255 1 4 Column Width 2 8 1 Minimum Number of Columns 2 255 1 4 Number of Selectable Columns 2 32 Row Constant 1 255 1 4 Row Width 1 8 1 Minimum Number of Rows 1 255 1 4 Number of Selectable Rows 2 32 Notes 1 This parameter is limited such that the maximum depth of individual memories within the core do not exceed certain limits The GUI detects if these limits have been exceeded This can mean the maximum value allowed by the GUI appears to be less than the absolute maximum value given in Table 3 In reality these parameters are limited by the maximum size of device available 2 The branch length constant is the value entered as the constant difference between consecutive branches The GUI displays the range of legal values based on the restrictions mentioned in Note 1 3 Block Size Constant must be within the following range R 1 C lt Block Size Constant lt R C where R number of rows and C number of columns If there is only a single row then Block Size Constant must equal the number of columns 4 The resulting block size must be within the absolute limits for Block SIze Constant given in this table DS861 October 19 2011 www xilinx com 18 Product Specification
7. The area of the Rectangular Block interleaver increases with the block size and if row column or block size are selectable or variable Adding optional pins such as m_axis_data_tready also increases the size Some example configurations are shown in Table 21 The slice counts can be reduced slightly by selecting the option to map primary I O registers into IOBs during placement This option should certainly be selected if the core I Os are to be connected directly onto a PCB via the FPGA package pins This gives lower output clock to out times and predictable set up and hold times The map options used were map pr b ol high The par options used were par ol high Performance Characteristics It is important to set a maximum period constraint on the core clock input The figures in Table 20 and Table 21 show clock speeds that can be achieved when this is done It might be possible to improve slightly on these values by trying different seed values for the place and route software If necessary performance can be increased by selecting a part with a faster speed grade For performance characterization the examples used a wrapper external to the core which adds an extra register on every synchronous input and output DS861 October 19 2011 www xilinx com 48 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 20 Example Forney Convolutional Implementations Parameter DVB
8. and the PCB layout DS861 October 19 2011 www xilinx com 33 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 aclk l l l l s_axis_data_tvalid l l l l l l l I I CCH eee l l I I I l l l 1 l l I l l l s_axis_data_tdata DIN wr_en wr_addr l T wr_data 2 2 ie eo ee ee ee ee a ee ee ee ee er Gl nn a es a ee ee i a en a l l l l l l 2 m i ee S l Ie td t2 t8 t4 th t6 j l l l l l l l l rd_en l 1 l _ a e l l l L l l eS EE 2 l l l l l l l l m_axis_data_tvalid m_axis_data_tdata DOUT Eoi Figure 28 External RAM Interface Timing when EXTERNAL_MEMORY_LATENCY 0 Figure 29 shows the same design but with an EXTERNAL_MEMORY_LATENCY of 3 The effect of this is to delay the symbols appearing on the Data Output Channel I aclk I I l s_axis_data_tvalid I aah a ee e a s_axis_data_tdata DIN 2 a sje I I i I l i wre f il wa 2 ee ee ee wt a i 1 1 i 3 2 3 l l rd_en I l l l td addr Bee SE Es es i l i EXTERNAL MEMORY_LATENCY je i l i i i 2 G Ji oof i i i i i l i l l pe foe foufe fr fetch s Figure 29 External RAM Interface Timing when EXTERNAL_MEMORY_LAT
9. s_axis_data_tvalid s_axis_data_tready s_axis_data_tdata s_axis_data_tlast event_tlast_unexpected event_tlast_missing event_halted event_row_valid event_col_valid event_row_sel_valid event_col_sel_valid event_block_size_valid wr_addr wr_data rd_addr aclk rd_data aresetn rd_e n aclken wr_en DS861_11_081111 Figure 9 Rectangular Block Schematic Symbol CORE Generator Graphical User Interface The CORE Generator GUI for the Symbol Interleaver De interleaver core uses several screens for setting core parameters To move between screens click Next or Back After selecting the desired parameters for type of core you want click Generate to generate the core when you reach the final screen Some parameters are relevant to both types of interleavers and some are specific to only one type Component Name Used as the base name of the output files generated for the core Names must begin with a letter and must be com posed of the following characters a to z 0 to 9 and _ DS861 October 19 2011 www xilinx com 13 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Memory Style The following options are available e Distributed The core should not use any block memories if possible This is useful if they are required elsewhere in the design e Block The core should use block memories wherever possible This keeps the number of slices used to a minimum but might waste blo
10. ARM is a registered trademark of ARM in the EU and other countries The AMBA trademark is a registered trademark of ARM Limited All other trademarks are the property of their respective owners DS861 October 19 2011 Product Specification www xilinx com XILINX LogiCORE IP Interleaver De Interleaver v7 0 Functional Description An interleaver is a device that rearranges the order of a sequence of input symbols The term symbol is used to describe a collection of bits In some applications a symbol is a single bit In others a symbol is a bus The classic use of interleaving is to randomize the location of errors introduced in signal transmission Interleaving spreads a burst of errors out so that error correction circuits have a better chance of correcting the data If a particular interleaver is used at the transmit end of a channel the inverse of that interleaver must be used at the receive end to recover the original data The inverse interleaver is referred to as a de interleaver Two types of interleaver de interleavers can be generated with this core Forney Convolutional and Rectangular Block Although they both perform the general interleaving function of rearranging symbols the way in which the symbols are rearranged and their methods of operation are entirely different For very large interleavers it might be preferable to store the data symbols in external memory The core provides an option to store data symbo
11. amp XILINX LogiCORE IP Interleaver De Interleaver v7 0 DS861 October 19 2011 Introduction The interleaver de interleaver core is appropriate for any application that requires data to be rearranged in an inter leaved fashion including many popular communications standards such as CDMA2000 and DVB Terrestrial T Cable C and Satellite S The multiple configuration mode is particularly useful for standards that require swapping between a number of convolutional interleavers for example ITU J 83 Annex B Features e High speed compact symbol interleaver de interleaver with AXI4 interfaces e Supports many popular standards such as DVB and CDMA2000 e Drop in module for Kintex 7 Virtex 7 Spartan 6 Virtex 6 e Forney Convolutional and Rectangular Block type architectures available e Easy to use interface signals e Fully synchronous design using a single clock e Symbol size from 1 to 256 bits e Internal or external symbol RAM e Convolutional type features e Parameterizable number of branches e Parameterizable branch lengths e Supports uniform and non uniform branch length increments e Multiple configurations with on the fly swapping e Rectangular Block type features e Parameterizable variable or selectable numbers of rows and columns e Parameterizable or variable block size e Can change numbers of rows columns or block size at start of each new block e Row and column permutations e Multiple permutat
12. are accepted until channel fills core starts block 2 while still processing block 1 s_axis_data_tready if m Block 2 held off until core is ready to start block 2 s_axis_data_tdata DIN 1 2 3 4 5 6 v 11 12 13 14 15 16 17 18 19 s_axis_data_tlast Size of block 1 7 2 m_axis_data_tvalid m_axis_data_tdata DOUT GOGAT Ca es m_axis_data_tuser BLOCK_START m_axis_data_tuser BLOCK_END Figure 22 Loading Rectangular Blocks Back to Back If any of the fields in the Control Channel contain illegal values the core deasserts the appropriate event_ _valid signal after a delay Using Table9 page35 we see that the delay to the event_block_size_valid output changing is 7 2 5 clock cycles event_block_size_valid changes five clock cycles after the block starts The block starting does not necessarily correspond to the first symbol being con sumed on the Data Input Channel see Figure 22 Figure 24 shows that the VALID Delay is not affected by wait states If an invalid block configuration is sampled the core aborts the processing of the block and treats the next symbol as being the first symbol in a new frame Xilinx recommends resetting the core if any of the event_ _valid outputs go low I aclk s_axis_ctrl_tvalid j l l l l l l a eT ee a s_axis_data_tvalid sea ae a oe I s_axis_data_tready l l s_axis_data_tlast l I Oe a A a a A a S l
13. correct operation when using MIF files they must be copied to the directory in which the simulation is to be run The vectors used in the COE file differ depending on whether the core is a Forney Convolutional or Rectangular Block type Forney Convolutional Type If the branch lengths are defined in a file then it must be a correctly formatted COE file The length of all the branches is defined in a comma separated list in a branch_length_vector Figure 11 shows an example COE file for a Forney Convolution interleaver with eight branches The number of branches must also be set to 8 in the GUI radix 10 branch_length_vector 3 10 20 40 80 160 320 640 Figure 11 Example Convolutional COE File DS861 October 19 2011 www xilinx com 22 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 The branch length values can also be placed on a single line as shown in Figure 12 radix 10 branch_length_vector 3 10 20 40 80 160 320 640 Figure 12 Example Convolutional COE File Values on a Single Line COE Files for Multiple Configurations The COE file is used to specify the branch length constant and number of branches for each configuration Figure 13 shows a COE file for an example with 16 configurations If the CONFIG_SEL field 0 then the interleaver has 128 branches and a branch length constant of 1 If the CONFIG_SEL field 3 then the interleaver has 64 branc
14. de inter leaver Input Data 0 1 2 3 4 5 6 7 8 9 10 11 Write row wise starting with top row 0 1 2 3 4 5 6 7 8 9 10 11 Inter row permutations P 0 2 2 0 1 4 5 6 7 8 9 10 11 0 1 2 3 Output Data 4 8 0 5 9 1 6 10 2 7 11 3 Figure 4 Block Interleaving Example with Row Permutations Although this example shows only row permutations it is possible to do both row and column permutations simul taneously This is shown in Figure 5 Figure 6 shows the output data from the interleaver of Figure 5 being de interleaved All the parameters are the same apart from mode which is set to de interleaver in this case Notice how the permute vectors are identical to those for the interleaver but they are interpreted in a different way This ensures that output data from the inter leaver is correctly restored to the original data by the de interleaver as shown in Figure 7 The inter row permutation pattern is again 2 0 1 However for the de interleaver this means row 2 is permuted to row 0 row 0 is permuted to row 1 and row 1 is permuted to row 2 DS861 October 19 2011 www xilinx com 6 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Input Data 0 1 2 3 4 5 6 7 8 9 10 11 Write row wise starting with top row 0 1 2 3 4 5 6 7 8 9 10 11 Int
15. have gone catastrophically wrong before further error correction is attempted Block Interleaver Specifications Sometimes a specification requires a Rectangular Block Interleaver but it is specified in the form of an equation It is not always immediately obvious that the equation represents a block interleaver It might be necessary to evaluate the equation for a number of values to see if it can be translated into the parame ters required by the block interleaver core For example one way of defining a block interleaver is to specify that the symbols are all written to a memory in sequential order 0 1 block_size 1 as in the write phase of Figure 4 The symbols are then read back from mem ory in an order defined by the following equation Read Address 2 i mod R BRO Round Down i R where i increments from 0 to block_size 1 2 is the number of columns and R is the number of rows BRO x is the bit reversed c bit value of x for example BRO3 1 4 Examination of the Read Address equation shows that the first part 2 i mod R yields the start address of each row The second part BRO Round Down i R yields how far along the row to go The BRO part produces column permutations For example if c 3 column 4 is permuted to column 1 and column 1 is permuted to column 4 If c 3 and R 4 then the resultant column permute vector is 0 4 2 6 1 5 3 7 DS861 October 19 2011 www xilinx com 9 Product Specifica
16. l Latency 7 clock cycles l j l l l i i i l Ll B j i l OCK_ST RT delay 7 symbols i i i I i 1 ji 4 4 1 I 1 J I f 1 i 1 l 1 T T f 1 1 1 l l 1 l 1 l 1 1 l 1 I i i T T Latency 7 clock cycles 1 1 Figure 21 Rectangular Block Interface Timing The block begins when s_axis_data_tvalid 1 and s_axis_data_tready 1 and a control word has been sent to the core In this example the first symbol has the value 1 The block size is sampled as 7 at this time If the core had ROW COL ROW_SEL or COL_SEL inputs they would also be sampled at this time The seven input symbols are sampled The symbol with value 4 is initially ignored because s_axis_data_tvalid is 0 The symbol with value 7 is the seventh and final symbol in the block and is designated as such by the assertion of s_axis_data_tlast The BLOCK_START Delay is reported as seven symbols plus the seven clock cycle latency The latency is indepen dent of the block size the fact that they are both 7 in this example is coincidence Note that s_axis_data_tvalid being low does affect the count of the number of symbols but it does not affect the latency The output symbols are always output consecutively on the Data Output Channel even if there were gaps between some of the input symbols In the example there was a one clock cycle gap in the input symbols between 3 and 4 because s_axis_data_
17. when BLOCK_START field in the Data Output Channel is actually asserted assuming aclken is high all the time The number of new symbols that must be sampled is equal to the block size An example is shown in Figure 21 In this example the block size is variable and the number of rows and columns is constant There are two rows and four columns There are no permutations Using Table 6 the latency is seven clock cycles The block size is resampled at the start of each new block I os mAT l 1 l j 1 7 s_axis_ctrl_tvalid 1 1 j 1 1 j 4 4 4 4 T T 7 T 7 T T T T T T T T T T T T T T T j id l 1 l l l li l l 1 1 l l l l 1 1 j l l l 1 l s_axis_data_tvalid 1 l l j l l 1 1 i L L i i L I s_axis_data_tready l 1 1 1 l I i Baan a l l I j i i i l 1 1 l I l l I i i I i i 1 l l 1 l l l 1 l l l l l 1 1 s_axis_data_tlast l 1 l l ji l 1 1 I l l l l l I 1 T T T T T T T T T T T T T T T T T i id 1 1 1 1 1 m_axis_data_tvalid L f ji i ji L L i i i L L m_axis_data_tdata DOUT 1 4 7 2 5 3 6 l m_axis_data_tuser BLOCK_START 4 1 1 l l l l 1 1 l l 4 4 4 4 l 1 l l l l m_axis_data_tuser BLOCK_END 1 I I 1 1 1 l l i 1 i 4 4 I i I ii I 1 f il f f
18. 10 11 and 12 DS861 October 19 2011 www xilinx com 15 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 This block size type can be used only if the row and column types are also set to constant Row and column permutations are not supported for pruned block sizes 2 Rows Columns If the number of rows and columns is constant selecting this option has the same effect as setting the block size type to constant and entering a value of rows columns for the block size If the number of rows or columns is not constant selecting this option means the core calculates the block size automatically whenever a new row or column value is sampled Pruning is impossible with this block size type 3 Variable Block size is sampled from the BLOCK_SIZE field in the Control Channel at the beginning of every block The value sampled on BLOCK_SIZE must be such that the last symbol falls on the last row as previously described If the block size is already available external to the core selecting this option is usually more efficient than selecting rows columns for the block size type Row and column permutations are not supported for the variable block size type 0 1 2 3 4 5 6 7 8 9 X Xx Block Size 10 Legal 0 1 2 3 4 5 6 X X Xx X Xx Block Size 7 Illegal Figure 10 Legal and Illegal Block Sizes Block Size Constant Value This paramete
19. De Interleaver v7 0 System Generator for DSP Graphical User Interface The Symbol Interleaver De interleaver core is available through Xilinx System Generator for DSP a design tool that enables the use of the model based design environment Simulink for FPGA design The Symbol Inter leaver De interleaver core is one of the DSP building blocks provided in the Xilinx blockset for Simulink The core can be found in the Xilinx Blockset in the Communication section The block is called Interleaver De interleaver 7 0 See the System Generator User Manual for more information The controls in the System Generator GUI work identically to those in the CORE Generator GUI although the lay out has changed slightly See CORE Generator Graphical User Interface page 13 for detailed information about all other parameters the amount of logic in the core can sometimes be reduced The largest possible value should be used for this param eter to keep the core as small as possible COE File Format In certain cases some parameter values are passed to the CORE Generator software via a COE COEfficient file This is an ASCII text file with a single radix header followed by a number of vectors The radix can be 2 10 or 16 Each vector must be terminated by a semi colon The GUI reads the COE file and writes out one or more MIF files when the core is generated The VHDL and Verilog behavioral simulation models for the core rely on these MIF files For
20. EL_VALID Rename BLOCK_SIZE_VALID EVENT_BLOCK_SIZE_VALID Rename EVENT_TLAST_UNEXPECTED New signal EVENT_TLAST_MISSING New signal EVENT_HALTED New signal Latency Changes The latency of Symbol Interleaver De interleaver v7 0 is different compared to v6 0 in general The update process cannot account for this and guarantee equivalent performance HAS_DOUT_TREADY 0 The latency of the core increases by 1 clock cycle to that of the equivalent configuration of v6 0 HAS_DOUT_TREADY 1 The latency of the core is variable so that only the minimum possible latency can be determined The latency is a minimum of 3 cycles longer than for the equivalent configuration of v6 0 The update process cannot account for this and guarantee equivalent performance DS861 October 19 2011 www xilinx com 45 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Instructions for Minimum Change Migration Configuring the Symbol Interleaver De interleaver v7 0 to most closely mimic the behavior of v6 0 depends on the features used in v6 0 The first step is to turn off the TREADY on the Output Data Channel set has_dout_tready false Then e Handle newly mandatory features e If you use external memory and have inserted registers between that and the core set external_memory_latency to the appropriate value e ND now s_axis_data_tvalid is no longer optional and has to be driven to 1 to pass symbol data to the
21. ENCY 3 m_axis_data_tvalid m_axis_data_tdata DOUT Event Signals The Symbol Interleaver De interleaver core provides some real time non AXI signals to report information about the core s status These event signals are intended for use by reactive components such as interrupt controllers These signals are not optionally configurable from the GUI but are removed by synthesis tools if left unconnected event_tlast_missing This event signal is asserted for a single clock cycle on the last symbol of an incoming block if s_axis_data_tlast is not seen asserted with that symbol This event is only present in Rectangular mode DS861 October 19 2011 www xilinx com Product Specification wo XILINX LogiCORE IP Interleaver De Interleaver v7 0 event_tlast_unexpected This event signal is asserted on every clock cycle where s_axis_data_tlast is unexpectedly asserted That is asserted on a symbol that is not the last symbol The meaning of Last Symbol varies between Forney and Rectangular mode e Forney the symbol corresponding to the last branch e Rectangular the final symbol loaded for a block If there are multiple unexpected highs on s_axis_data_tlast then this is asserted for each of them event_halted This event is asserted on every cycle where the Symbol Interleaver De interleaver needs to write data to the Data Output Channel but cannot because the buffers in the channel are full When this occu
22. ING Output Asserted on the last symbol of an incoming block if s_axis_data_tlast is not PU asserted with that symbol This signal is only present in Rectangular mode EVENT_HALTED Asserted when the Symbol Interleaver De interleaver tries to write data to the Data Output Output Channel and it is unable to do so Only present when the XCO HAS_DOUT_TREADY is true DS861 October 19 2011 Product Specification www xilinx com 11 XILINX LogiCORE IP Interleaver De Interleaver v7 0 Schematic Symbol for Forney Convolutional Type Figure 8 illustrates the Forney Convolutional type schematic symbol s_axis_ctrl_tvalid m_axis_data_tvalid s_axis_ctrl_tready m_axis_data_tready s_axis_ctrl_tdata m_axis_data_tdata m_axis_data_tuser m_axis_data_tlast s_axis_data_tvalid s_axis_data_tready s_axis_data_tdata s_axis_data_tlast event_tlast_unexpected event_tlast_missing event_halted wr_addr wr_data rd_addr acik rd_data aresetn rd_en aclken wr_en DS861_08_081111 Figure 8 Forney Convolutional Schematic Symbol DS861 October 19 2011 www xilinx com 12 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Schematic Symbol for Rectangular Block Type Figure 9 illustrates the Rectangular Block type schematic symbol s_axis_ctrl_tvalid m_axis_data_tvalid s_axis_ctrl_tready m_axis_data_tready s_axis_ctrl_tdata m axis data tdata m_axis_data_tuser m_axis_data_tlast
23. If an illegal value is sampled on the ROW_SEL field of the Control Channel event_row_sel_valid goes low a predefined number of clock cycles later Table 9 lists the number of clock cycles from the first symbol being sampled high to event _row_sel_valid changing See Table 16 for an explanation of an illegal ROW_SEL value AX 4 Stream Considerations The conversion to AXI4 Stream interfaces brings standardization and enhances interoperability of Xilinx IP LogiCORE solutions Other than general control signals such as aclk aclken and aresetn external memory interface and event signals all inputs and outputs to the Symbol Interleaver De interleaver are conveyed via AX1 4 Stream channels A channel always consists of TVALID and TDATA plus additional ports such as TREADY TUSER and TLAST when required and optional fields Together TVALID and TREADY perform a handshake to transfer a message where the payload is TDATA TUSER and TLAST For further details on AX14 Stream interfaces see Ref 2 and Ref 3 Basic Handshake Figure 30 shows the transfer of data in an AX 4 Stream channel TVALID is driven by the source master side of the channel and TREADY is driven by the receiver slave TVALID indicates that the values in the payload fields TDATA TUSER and TLAST are valid TREADY indicates that the slave is ready to receive data When both TVALID and TREADY are true in a cycle a transfer occurs The master and slave set TVALID and TREADY res
24. Interleaver Interface Timing Waitstates do Affect Delay Multiple Configuration Timing Figure 20 shows the timing when the configuration is swapped using CONFIG_SEL The example uses maximum pipelining and has no TREADY on the Data Output Channel Therefore its latency is 6 cycles Configuration 0 has 2 branches of length 0 and 1 and configuration 1 has 3 branches of length 0 2 and 4 FDO delay in both cases is 1 symbol which is the first symbol itself s_axis_data_tready and s_axis_data_tvalid are both 1 for the duration of this example so are not shown In this example the core switches from configuration 0 to configuration 1 The new configuration value is sent on the Control Channel when DIN 15 but the configuration is not actually changed until the DIN symbol with value 17 as this is the first symbol of a new frame When the Symbol Interleaver De interleaver detects the new configuration it continues to output the configuration 0 data for Latency clock cycles as defined previously After this number of clock cycles DOUT is unknown until the first configuration 1 symbol appears on DOUT Symbols for the new frame appear after the FDO Delay plus latency as normal Because the first branch in configuration 1 is 0 FDO for configuration 1 appears directly after the 1 It is important to note that TLAST is an indication to the core that the block should end when the last branch is reached It does not specify that the block ends imme
25. RE IP Interleaver De Interleaver v7 0 References 1 Synthesis and Simulation Design Guide 2 Xilinx AXI Design Reference Guide UG761 3 AMBA 4 AXI4 Stream Protocol Version 1 0 Specification Support Xilinx provides technical support at www xilinx com support for this LogiCORE product when used as described in the product documentation Xilinx cannot guarantee timing functionality or support of product if implemented in devices that are not defined in the documentation if customized beyond that allowed in the product documentation or if changes are made to any section of the design labeled DO NOT MODIFY See the IP Release Notes Guide XTP025 for further information on this core On the first page there is a link to All DSP IP The relevant core can then be selected from the displayed list For each core there is a master Answer Record that contains the Release Notes and Known Issues list for the core being used The following information is listed for each version of the core e New Features e Bug Fixes e Known Issues Ordering Information This Xilinx LogiCORE IP product is provided under the terms of the SignOnce IP Site License To evaluate this core in hardware generate an evaluation license which can be accessed from the Xilinx IP Evaluation page After purchasing the core you will receive instructions for registering and generating a full core license The full license can be requested and ins
26. T Tx DVB T Rx ITU J 83 Annex B Mode Interleaver De interleaver Interleaver Number of Configurations 1 1 16 Number of Branches 12 12 Configurable 8 to 128 Branch Length Constant 17 17 Configurable 1 to 16 Symbol Width 8 8 7 Pipelining Maximum Maximum Maximum Optional Fields FDO RDY FDO RDY RDY Internal External Symbol RAM Internal Internal External Memory Style Automatic Automatic Automatic Spartan 6 XC6SLX75 Test cases used an xc6slx75 fgg484 with 2 speed grade device and ISE speed file version PRODUCTION 1 19 2011 07 25 Area LUT FF pairs 1 159 182 264 Block RAMs 16K 8K 3 1 0 1 0 4 2 Maximum Clock Frequency speed grades 2 1 2 Virtex 6 XC6VLX75T Test cases used an xc6vIx75t ff484 with 1 speed grade device and ISE speed file version PRODUCTION 1 15 2011 07 25 Area LUT FF pairs 1 153 169 256 Block RAMs 36K 18K 3 0 1 0 1 2 2 Maximum Clock Frequency speed grades 1 1 2 Virtex 7 xc7vx485t Test cases used an xc7vx485t ffg1157 with 1 speed grade device and ISE speed file version ADVANCED 1 02a 201 1 07 25 Area LUT FF pairs 1 148 177 285 Block RAMs 36K 18K 3 0 1 0 1 2 2 Maximum Clock Frequency speed grades 1 1 2 Kintex 7 xc7k160t Test cases used an xc7k160t fbg484 with 1 speed grade device and ISE speed file version ADVANCED 1 01 2011 07 25 Area LUT FF pairs 1 170 177 260 Block RAMs 36K 18K 3 0 1 0 1 2 2 Maximum Clock Frequency speed grades 1 1 2
27. alid is asserted as each zero or other symbol that was in the branch memory prior to the first symbol pulse is flushed out RDY is not asserted for this data If branch 0 has length 0 RDY and m_axis_data_tvalid are identical This is because the first symbol output on DOUT after the first symbol is sampled is the first symbol sampled No Rectangular mode only BLOCK_START has similar functionality to FDO in the Convolutional interleaver It is asserted high when the first symbol of a block appears on DOUT The BLOCK_START delay is dependent on the latency and the block size The BLOCK_START output is useful for synchronizing circuits downstream of the interleaver It can be used to tell those circuits when to start a new block BLOCK_START BLOCK_END No Rectangular mode only BLOCK_END is asserted high when the last symbol of a block appears on DOUT TUSER Format The fields are packed into the m_axis_data_tuser vector in the following order starting from the LSB 1 FDO 2 RDY 3 BLOCK_START 4 BLOCK_END The fields in TUSER are only present if supported by the core s configuration When a field is omitted the following fields are moved down the vector as close to bit 0 as possible That is if BLOCK_START and BLOCK_END are selected BLOCK_START is at bit 0 and BLOCK_END is at bit 1 If only BLOCK_END is selected it is at bit 0 N P ye ee ey aera a BLOCK_END i BLOCK_START i RDY FDO Op
28. alue for the variable B in Figure 1 Figure 2 and Figure 3 The value must always be specified even when using a file to define branch lengths Length of Branches Either a constant difference between branch lengths as in Figure 1 and Figure 2 or the branch lengths specified from a file as in Figure 3 Figure 11 provides an example of the file syntax in the latter case Number of Configurations If greater than 1 the core is generated with an AXI Control Channel containing the CONFIG_SEL field The param eters for each configuration are defined in a COE File Format The number of parameters defined must exactly match the number of configurations specified Architecture Controls whether look up table ROMs or logic circuits are used to compute some of the internal results in the core Which option is best depends on the other core parameters It is recommended that both options are tried This parameter has no effect on the core behavior Rectangular Block Specific Parameters Block Size Type There are three possibilities 1 Constant Block size never changes The block can be pruned block size lt row col The block size must be chosen so that the last symbol is on the last row An unpruned interleaver uses a smaller quantity of FPGA resources than a pruned one so pruning should be used only if necessary Figure 10 provides an example with three rows and four columns Using the preceding rule the only legal block sizes are 9
29. ase sensitive Default values are displayed in bold Xilinx strongly suggests that XCO parameters are not manually edited in the XCO file instead use the CORE Gen erator GUI to configure the core and perform range and parameter value checking Table 4 XCO Parameters XCO Parameter Valid Values architecture rom_based logic_based has_block_end true false block_size_constant_ Integer in the range defined in Table 3 default value is 15 value block_size_port_width Integer in the range defined in Table 3 default value is 4 block_size_type constant rows_columns variable has_block_size_valid true false has_block_start true false branch_length_constant Integer in the range defined in Table 3 default value is 1 constant_difference_between_consecutive_branches use_coe_file_to_define_branch_lengths branch_length_type coe_file_defines_branch_length_constant_for_each_configuration coe_file_defines_individual_branch_lengths_for_every_branch_in_each_configuration has_ce true false coefficient_file Path of coe file if coe file required default is blank column_permutations none use_coe_file_to_define_column_permutations col_port_width Integer in the range defined in Table 3 default value is 4 DS861 October 19 2011 www xilinx com 19 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 4 XCO Parameters Cont d
30. ck Timing The latency is the number of clock cycles from the last symbol in a block being sampled on the Data Input Channel to the first symbol from that block appearing on the Data Output Channel The latency is dependent on the block size type row and column types and whether there are any permutations All the possible values are shown in Table 6 Table 6 Rectangular Block Latency Block Size Column Row Row or Column Latency Type Type Type Permutations Clock Cycles Constant No 5 Constant Yes 7 Row Column No 5 Row Column Yes 7 Variable Constant Constant N A 7 Variable Not Constant N A 10 Variable Not Constant N A 10 Notes 1 Add two clock cycles if the Data Output Channel has a TREADY XCO DOUT_HAS_TREADY true The FDO delay or BLOCK_START delay is the delay from the first symbol of a block being sampled to the first symbol of the same block being output on the Data Output Channel This is a different symbol to the first one sam pled due to the interleaving process The BLOCK_START delay is composed of two parts a number of valid symbol pulses including the first symbol and the latency The GUI reports the BLOCK_START delay as the number of new DS861 October 19 2011 www xilinx com 27 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 symbols that must be sampled including the first symbol plus a number of clock cycles This is
31. ck memory e Automatic Allow the core to use the most appropriate style of memory for each case based on required memory depth Symbol Width The number of bits in the symbols to be processed Symbol Memory Allows the symbol memory to be specified as internal or external If external is selected then all the optional pins required for external memory access are automatically added When external memory is selected the External Symbol Memory Latency edit box becomes enabled The value entered here must match the total number of cycles of latency that have been added to the external memory interface in the system This includes both the outbound and inbound signals See External Symbol Memory for more details Type Determines whether the core is to be an interleaver or de interleaver For the Forney Convolutional type the branch lengths are incremented from branch 0 as shown in Figure 1 or dec remented from branch 0 as shown in Figure 2 If the branch lengths are specified in a file the mode is irrelevant For the Rectangular Block type this determines whether a write rows read columns or write columns read rows operation is performed Pipelining Three levels of pipelining are available Select Maximum if speed is important This might result in a slight increase in area The latency of the Convolutional type also increases slightly In general it is recommended that Maximum pipelining is used Medium and Maximum pipelini
32. ck_size_type constant rows_columns variable has_block_size_valid true false has_block_start true false branch_length_constant Integer in the range defined in Table 3 default value is 1 branch_length_type constant_difference_between_consecutive_branches use_coe_file_to_define_branch_lengths coe_file_defines_branch_length_constant_for_each_configuration coe_file_defines_individual_branch_lengths_for_every_branch_in_each_configuration has_ce true false coefficient_file Path of coe file if coe file required default is blank column_permutations none use_coe_file_to_define_column_permutations col_port_width Integer in the range defined in Table 3 default value is 4 has_col_sel_valid true false has_col_valid true false component_name ASCII text starting with a letter and based upon the following character set a z 0 9 and _ default is blank has_fdo true false memory_style automatic distributed block minimum_columns Integer in the range defined in Table 3 default value is 15 minimum_rows Integer in the range defined in Table 3 default value is 15 mode interleaver deinterleaver number_of_branches Integer in the range defined in Table 3 default value is 16 number_of_columns constant selectable variable number_of_columns_ constant_value Integer in the range defined i
33. core e RFD now s_axis_data_tready is no longer optional and has to be used in the transfer of data to the core Asserting s_axis_data_tvalid is not enough to transfer symbols to the core If s_axis_data_tready is 0 these symbols are ignored e RDY now m_axis_data_tvalid in Rectangular mode is no longer optional It must be used to control the transfer of data from the core It is no longer completely possible to just rely on latency to calculate when symbols appear e NDO now m_axis_data_tvalid in Forney mode is no longer optional It must be used to control the transfer of data from the core It is no longer completely possible to just rely on latency to calculate when symbols appear e Handle Changed Features e Ifyou previously had SCLR set to true then remember that the reset pulse is now active low and must bea minimum of two clock cycles long e Ifyou previously had SCLR set to true and CE set to true note that reset now overrides clock enable In v6 0 asserting both at the same time would not result in a reset In v7 0 asserting both at the same time results in a reset e Illegal blocks now are always aborted in Rectangular mode When the block is recognized as illegal the core treats subsequent symbols as belonging to a new block This can lead to synchronisation issues between the core and the system Xilinx recommends either not injecting illegal blocks or resetting the core using aresetn when an event_ _valid signal is see
34. d col_permute vector work in the same way The supplied COE file must be compatible with the other parameters entered in the GUI such as number of select able rows radix 10 row_select_vector 34 5 col_select_vector 4 6 5 row_permute_vector 2 0 1 3 2 0 1 0 1 2 3 4 col_permute_vector 3 1 0 2 3 1 0 2 4 5 2 1 3 0 4 Figure 16 Example Rectangular COE File with Selectable Rows and Columns Timing Latency and FDO Delay The precise definitions of latency and FDO Delay differ for the different types of interleaver de interleaver Each is described separately The following assumptions are made when defining the latency figures 1 There are no waitstates on any AXI channels 2 aclken if present is always 1 3 The core is idle 4 If the Control Channel is present a control word is sent before or coincident with the first data symbol because the Control Channel blocks the Data Input Channel otherwise DS861 October 19 2011 www xilinx com 24 Product Specification LogiCORE IP Interleaver De Interleaver v7 0 XILINX Forney Convolutional Timing The latency is the number of clock cycles from a new symbol being sampled on the Data Input Channel to a new symbol appearing on the Data Output Channel These are generally not the same symbol as they have been inter leaved or de interleaved The latency is dependent on the pipelining level selected as shown in Table 5 Table 5 Forney Co
35. diately unless the commutator is already on the last branch TLAST is stored by the core and used at the next opportunity even if it was incorrectly sent In this example s_axis_tlast is asserted one cycle early and event_tlast_unexpected is asserted as a result The last symbol here has a value of 16 even though the symbol with value 15 was marked by the user as being the last one Care must be taken to ensure that the symbol data remains in synchronisation with the branch commutator If the user had expected symbol 15 to be the last one the incoming datastream would no longer be synchronised to the core DS861 October 19 2011 www xilinx com 26 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 last symbol from configuration 0 and RDY remains asserted If the first branch for configuration 1 had been greater than 0 then RDY would have deasserted after the last symbol from configuration 0 and remained deasserted until FDO asserted aclk s_axis_ctrl_tvalid nN New configuration not used until first symbol of second frame DIN 17 First symbol for second frame oa Last symbol for first frame s_axis_data_tlast m_axis_data_tvalid m_axis_data_tdata DOUT 2 m_axis_data_tuser FDO m_axis_data_tuser RDY k na DOUT continues to output valid configuration 0 data for Latency clock cycles Figure 20 Configuration Swapping Timing Rectangular Blo
36. e dual port RAM behaves in the same way as a standard Xilinx block RAM The ports shown are the standard Xilinx block RAM ports The ENA ENB ports act as clock enables for operations on the A and B ports respectively In this case the A port is used for write operations and the B port for read operations DS861 October 19 2011 www xilinx com 30 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Interleaver Core 0 External Dual Port RAM s_axis_ctrl_tvalid m_axis_data_tvalid s_axis_ctrl_tready m_axis_data_tready s_axis_ctrl_tdata m_axis_data_tdata m_axis_data_tlast s_axis_data_tvalid s_axis_data_tready s_axis_data_tdata s_axis_data_tlast event_tlast_unexpected event_tlast_missing m_axis_data_tuser event_halted wr_addr wr_data rd_addr acik rd_data aresetn aclken CLK l DS861_22_081111 Figure 25 Connections to External Symbol RAM for Convolutional Interleaver Table 7 External Memory Pinout Table for Forney Cores Signal Direction Description RD_ADDR Output This is the read address for the external symbol RAM RD_ADDR should be connected to the RAM address bus corresponding to the port used by RD_DATA RD_ADDR must be exactly wide enough to address the required symbol memory depth The CORE Generator software calculates this automatically and generates a core with appropriately sized address buses The required address bus width is also displayed on the last
37. e event_block_size_valid output See Block Size Type page 15 for details of illegal BLOCK_SIZE values All fields should be 0 extended to the next 8 bit boundary if they do not already finish on an 8 bit boundary All field widths are variable See the CORE GUI when configuring the Symbol Interleaver De interleaver TDATA Format The Control Channel s TDATA vector is structured as shown in Figure 34 starting from the LSB L XN f 4 7 PAD CONFIG_SEL Forney Made l m l a e e o u u u u u M 1 TDATA 7 N m 77777777T FER M A aa gt i PAD I BLOCK_SIZE PAD lt eA Ipap _ ROW l l l l j ROW_SEL Rectangular Mode bee e o o e o o m o a Ie b a a l a u u u Mu J Optional fields are shown as dotted Figure 34 Control Channel TDATA s_axis_ctrl_tdata Format DS861 October 19 2011 www xilinx com 42 Product Specification XILINX Migrating to Symbol Interleaver De interleaver v7 0 from Earlier Versions XCO Parameter Changes LogiCORE IP Interleaver De Interleaver v7 0 The CORE Generator core update functionality can be used to update an existing XCO file from v6 0 to Symbol Interleaver De interleaver v7 0 but it should be noted that the update mechanism alone does not create a core compatible with v6 0 See Instructions for Minimum Change Migration Symbol Interleaver De interleaver v7 0 has additional parameters for AX 4 Stream support Table 17 shows the changes to XCO para
38. er row permutations P 0 2 2 0 1 4 5 6 7 8 9 10 11 0 1 2 3 Inter column permutations P 0 3 3 1 0 2 6 5 7 4 10 9 11 8 2 1 3 0 Output Data 6 10 2 5 9 1 7 11 3 4 8 0 Figure 5 Block Interleaving Example with Row and Column Permutations The core can be configured with fixed variable or selectable rows and columns The block size can be fixed vari able or set to always equal R C If the block size is variable or less than R C row and column permutations are not supported If the block size is less than R C the interleaver is described as pruned DS861 October 19 2011 www xilinx com 7 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Input Data 6 10 2 5 9 1 7 11 3 4 8 0 Write column wise starting with left column 6 5 7 4 10 9 11 8 2 1 3 0 Inter row permutations P 0 2 2 0 1 2 1 3 0 6 5 7 4 10 9 11 8 Inter column permutations P 0 3 3 1 0 2 0 1 2 3 4 5 6 7 8 9 10 11 Output Data 0 1 2 3 4 5 6 7 8 9 10 11 Figure 6 Block De interleaving Example with Row and Column Permutations Row permutations are not supported if the row type is variable Column permutations are not supported if the col umn type is variable Selectable
39. f rows and columns as shown in Table 1 DS861 October 19 2011 www xilinx com 4 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 1 Row and Column Indexing Scheme Ran nay 0 1 E C 2 C 1 0 1 R 2 R 1 The Rectangular Block Interleaver operates as follows 1 All the input symbols in an entire block are written row wise left to right starting with the top row 2 Inter row permutations are performed if required 3 Inter column permutations are performed if required 4 The entire block is read column wise top to bottom starting with the left column The de interleaver operates in the reverse way 1 All the input symbols in an entire block are written column wise top to bottom starting with the left column 2 Inter row permutations are performed if required 3 Inter column permutations are performed if required 4 The entire block is read row wise left to right starting with the top row An example of Rectangular Block Interleaver operation is shown in Figure 4 This example has 3 rows 4 columns and a block size of 12 The inter row permutation pattern is 2 0 1 This means row 0 is permuted to row 2 row 1 DS861 October 19 2011 www xilinx com 5 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 is permuted to row 0 and row 2 is permuted to row 1 The meaning of the permute vector differs for the
40. first control word is sent after the data showing the Control Channel blocking the Data Input Channel The second control word is sent immediately after the first showing the Control Channel not blocking the Data Input Channel Sends the first block of symbols to the Symbol Interleaver De interleaver core with no waitstates Consumes the first block of symbols from the core with no waitstates Sends the second block of symbols to the Symbol Interleaver De interleaver core with waitstates The upstream master adds random waitstates to the input symbols by de asserting s_axis_data_tvalid 5 Consumes data from the core with waitstates waitstates only when HAS_DOUT_TREADY true The downstream slave adds random waitstates to the output symbols by de asserting m_axis_data_tready Customizing the Demonstration Test Bench It is possible to modify the demonstration test bench to drive the core s inputs with different data or to perform different operations The stimuli is configured in the proc_stimuli_manager process using configuration objects which are then used by other processes to control the AXI channels The data is sent incrementally starting from 1 for each block This is hardwired in the proc_usdm process Upstream Data Master but is can be changed The clock frequency of the core can be modified by changing the CLK_PERIOD constant DS861 October 19 2011 www xilinx com 21 Product Specification XILINX LogiCORE IP Interleaver
41. h DS861 October 19 2011 www xilinx com 23 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Rectangular Block Type If row or column permutations are to be used then the row and or column permutation vectors are passed to the CORE generator software using a COE file Figure 15 shows an example COE file for the permutations used in Figure 5 radix 10 row_permute_vector 2 0 1 col_permute_vector 3 1 0 2 Figure 15 Example Rectangular COE File If the row or column type is selectable the row and or column select vectors are also passed in via the COE file These tell the core how to map the value sampled on the ROW_SEL and COL_SEL fields to a particular number of rows or columns If row or column permutations are to be used in conjunction with selectable rows or columns then it is possible to have a different permute vector for every row and column select value For example in Figure 16 there are three selectable row values If the ROW_SEL field 00 the interleaver has three rows 01 gives four rows and 10 gives five rows 11 is an illegal ROW_SEL value because a fourth value is not defined in the row_select_vector Also if the ROW_SEL field 00 the row permute vector is 2 0 1 If the ROW_SEL field 01 the vector is 3 2 0 1 and if the ROW_SEL field 10 the vector is 0 1 2 3 4 that is no row permutations The col_select_vector an
42. hen the commutator reaches the last branch In rectangular mode signals the last symbol in a block S_AXIS_CTRL_TVALID TVALID for the Control Channel Asserted by the external master to signal that it is Input able to provide data Only present when the core is configured to have control options S_AXIS_CTRL_TREADY TREADY for the Control Channel Asserted by the Symbol Output Interleaver De interleaver to signal that it is ready to accept control data Only present when the core is configured to have control options S_AXIS_CTRL_TDATA TDATA for the Control Channel Can contain the following field in Forney mode e CONFIG_SEL Can contain the following fields in Rectangular mode e ROW Input e ROW_SEL e COL e COL_SEL e BLOCK_SIZE Only present when the core is configured to have control options TVALID for the Data Output Channel Asserted by the Symbol Interleaver De interleaver to signal that it is able to provide symbol data M_AXIS_DATA_TREADY TREADY for the Data Output Channel Asserted by the external slave to signal that Input it is ready to accept data Only present when the XCO parameter HAS_DOUT_TREADY is true TDATA for the Data Output Channel Carries the processed symbol data M_AXIS_DATA_TVALID Output M_AXIS_DATA_TDATA Output DS861 October 19 2011 www xilinx com 10 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 2 Core Signal Pinout Co
43. hes and a branch length constant of 2 radix 10 number_of_branches_vector 128 128 128 64 128 32 128 16 128 8 128 128 128 128 128 128 branch_length_constant_vector 1 1 2 2 3 4 4 8 5 16 6 1 7 1 8 1 Figure 13 ITU J 83 Annex B COE File The number of elements in the number_of_branches_vector and the branch_length_constant_vector must equal the number of configurations If the number of configurations is not a power of two then out of range values on the CONFIG_SEL field input results in the core selecting configuration 0 It is possible to define the individual branch length for every branch in each configuration If this option is selected then the branch_length_constant_vector must be replaced with a branch_length_vector The number of elements in this vector must be the exact sum of all the elements of the number_of_branches_vector An example is shown in Figure 14 In this example if the CONFIG_SEL field 0 then an interleaver with branches of lengths 1 2 3 and 4 is selected If the CONFIG_SEL field 1 an interleaver with branches of 4 3 2 and 1 is selected This is one way of having a single core switch between interleaving and de interleaving If the CONFIG_SEL field 2 an interleaver with branches of 1 4 and 5 is selected radix 10 number_of_branches_vector 4 4 3 branch_length_vector 1 2 3 4 4 3 2 1 1 4 5 Figure 14 Multiple Configuration COE File Defining Each Individual Branch Lengt
44. illustrated in Figure 1 The only difference between an interleaver and a de interleaver is that branch 0 is the longest in the de interleaver and the branch length is decremented by L rather than incremented Branch B 1 has length 0 This is illustrated in Figure 2 If a file is used to specify the branch lengths it is arbitrary whether the resulting core is called an interleaver or de interleaver All that matters is that one must be the inverse of the other If a file is used each branch length is individually controllable This is illustrated in Figure 3 The file syntax is shown in Figure 11 page 22 B 1 L B 2 L B 3 L e e e e ae B 3 Vo eE oe e n r X o E L e Figure 2 Forney Convolutional De interleaver DS861 October 19 2011 www xilinx com 3 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 branch_length_vector 0 branch_length_vector 1 branch_length_vector 2 e e e e B 3 woy v branch_length_vector B 3 o B 2 vA _ branch_length_vector B 2 e B 1 4 1 1 branch_length_vector B 1 d Figure 3 Forney Convolutional Interleaver De interleaver with Branch Lengths Set by File Configuration Swapping It is possible for the core to store a number of pre defined co
45. ions for selectable rows or columns e Input validity checking e Use with Xilinx CORE Generator software and Xilinx System Generator for DSP v13 3 e Available under terms of the SignOnce IP Site License Product Specification LogiCORE IP Facts Table Core Specifics Supported Virtex 7 Kintex 7 Artix 7 Zynq 7000 Device Family Spartan 6 Virtex 6 oo ai Provided with Core Documentation Product Specification Design Files Netlist Example Design Not Provided Test Bench VHDL Constraints File Not Applicable Simulation Model VHDL behavioral model in the xilinxcorelib library VHDL UNISIM structural model Verilog UNISIM structural model Tested Design Tools Design Entry Tools CORE Generator tool 13 3 System Generator for DSP 13 3 Mentor Graphics ModelSim Cadence Incisive Enterprise Simulator IES i ion Simulation Synopsys VCS and VCS MX ISim 13 3 Synthesis Tools N A Support Provided by Xilinx Inc 1 For a complete listing of supported devices see the release notes for this core 2 For the supported version of the tools see the ISE Design Suite 13 Release Notes Guide Copyright 2011 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries Simulink is a registered trademark of The MathWorks Inc
46. l l l s_axis_data_tdata DIN l meea aeaa m_axis_data_tvalid m_axis_data_tdata DOUT i Ses fs eset es m_axis_data_tuser FDO l l l l l l I I l m_axis_data_tuser RDY i latency A 4 cycle FDO 5 ymbols latency f 4 cycles l 1 P T l Figure 17 Forney Convolutional Interleaver Interface Timing The latency of the core is not affected by waitstates on the Data Input channel Figure 18 but the FDO delay is Figure 19 DS861 October 19 2011 Product Specification www xilinx com 25 XILINX LogiCORE IP Interleaver De Interleaver v7 0 aclk s_axis_data_tvalid s_axis_data_tdata DIN m_axis_data_tvalid m_axis_data_tdata DOUT Latency 4 cycles l Figure 18 Forney Convolutional Interleaver Interface Timing Waitstates do not Affect Latency acik s_axis_data_tvalid i l l i l i i i A ED EASE ESE ES T T T l l l l l l l l ES e ED e e i a FA a a a l l l l l l l I I I l lt lt Latency 7 4 cycles l l l l l l l T T T T I s_axis_data_tdata DIN m_axis_data_tvalid m_axis_data_tdata DOUT m_axis_data_tuser FDO m_axis_data_tuser RDY FDOF5 symbols latdney of 4 fycles I l Figure 19 Forney Convolutional
47. l_width Integer in the range defined in Table 3 default value is 1 type forney rectangular has_dout_tready true false external_memory_latency 0to6 Demonstration Test Bench When the core is generated using CORE Generator a demonstration test bench is created This is a simple VHDL test bench that exercises the core The demonstration test bench source code is one VHDL file demo_tb tb_ lt component_name gt vhd in the CORE Generator output directory The source code is comprehensively commented DS861 October 19 2011 www xilinx com 20 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Using the Demonstration Test Bench The demonstration test bench instantiates the generated Symbol Interleaver De interleaver core Either the behavioral model or the netlist can be simulated within the demonstration test bench e Behavioral model Ensure that the CORE Generator project options are set to generate a behavioral model After generation this creates a behavioral model wrapper named lt component_name gt vhd Compile this file into the work library see your simulator documentation for information on how to do this e Netlist If the CORE Generator project options were set to generate a structural model a VHDL or Verilog netlist named lt component_name gt vhd or lt component_name gt v was generated If this option was not set generate a netlist using the netgen program for examp
48. le netgen sim ofmt vhdl lt component_name gt ngc lt component_name gt _netlist vhd Compile the netlist into the work library see your simulator documentation for more information on how to do this Compile the demonstration test bench into the work library Then simulate the demonstration test bench View the test bench s signals in your simulator s waveform viewer to see the operations of the test bench The Demonstration Test Bench in Detail The demonstration test bench performs the following tasks e Instantiate the core e Generate a clock signal e Drive the core s input signals to demonstrate core features see following sections for details e Provide signals showing the separate fields of AXI4 TDATA and TUSER signals The demonstration test bench drives the core s input signals to demonstrate the features and modes of operation of the core The test bench drives two blocks of incremental data into the Symbol Interleaver De interleaver core The output of the core shows the same data but in an interleaved or deinterleaved manner Alias signals are used to decode the AXI4 channels and allow easy viewing of the input and output data The test bench does not manipulate aresetn or aclken even if they are enabled The operations performed by the demonstration test bench are appropriate for the configuration of the generated core and are a subset of the following operations 1 Sends control information to the core if relevant The
49. ls in internal FPGA RAM or in external RAM This is explained in more detail in Exter nal Symbol Memory page 30 Forney Convolutional Operation Figure 1 shows the operation of a Forney Convolutional Interleaver The core operates as a series of delay line shift registers Input symbols are presented to the input commutator arm on DIN Output symbols are extracted from the output commutator arm on DOUT DIN and DOUT are fields in the AXI Data Input Channel and Data Output Channel respectively Both commutator arms start at branch 0 and advance to the next branch after the next rising clock edge After the last branch B 1 has been reached the commutator arms both rotate back to branch 0 and the process is repeated L 2 L e e a B 3 L e gt B 2 L oe B 1 L o Figure 1 Forney Convolutional Interleaver In Figure 1 the branches increase in length by a uniform amount L The core allows interleavers to be specified in this way or the branch lengths can be passed in via a file allowing each branch to be any length Although branch DS861 October 19 2011 www xilinx com 2 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 0 appears to be a zero delay connection there is still a delay of a number of clock cycles between DIN and DOUT because of the fundamental latency of the core For clarity this is not
50. lue ROW Field Width This parameter is relevant only if variable row type is selected It sets the width of the ROW field in the Control Channel ignoring padding The smallest possible value should be used to keep the core as small as possible Number of Selectable Rows If the selectable row type has been chosen this parameter defines how many valid selection values have been defined in the COE file Only add select values you need DS861 October 19 2011 www xilinx com 17 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Minimum Number of Rows This parameter is relevant only if variable row type is selected In this case the core has to potentially cope with a wide range of possible values for the number of rows If the smallest value that can actually occur is known then the amount of logic in the core can sometimes be reduced The largest possible value should be used for this param eter to keep the core as small as possible Use Row Permute File This tells the CORE Generator software that a row permute vector exists in the COE file and row permutations are to be performed Remember this is possible only for unpruned interleaver de interleavers Parameter Ranges Valid ranges for the parameters are provided in Table 3 Table 3 Parameter Ranges Parameter Min Max Notes Symbol Width 1 256 Forney Convolutional Number of Configurations 1 256 Number of Branches 2 256 1
51. meters from version 6 0 to version 7 0 Table 17 XCO Parameter Changes from v6 0 to v7 0 Version 6 0 Version 7 0 Notes architecture architecture Unchanged block_end has_block_end Rename block_size_constant_value block_size_constant_value Unchanged block_size_port_width block_size_port_width Unchanged block_size_type block_size_type Unchanged block_size_valid has_block_size_valid Rename block_start has_block_start Rename branch_length_constant branch_length_constant Unchanged branch_length_type branch_length_type Unchanged ce has_aclken Rename coefficient_file coefficient_file Unchanged column_permutations column_permutations Unchanged col_port_width col_port_width Unchanged col_sel_valid has_col_sel_valid Rename col_valid has_col_valid Rename component_name component_name Unchanged fdo has_fdo Rename memory_style memory_style Unchanged minimum_columns minimum_columns Unchanged minimum_rows minimum_rows Unchanged mode mode Unchanged nd Obsolete ndo Obsolete number_of_branches number_of_branches Unchanged number_of_columns number_of_columns Unchanged number_of_columns_constant_value number_of_columns_constant_value Unchanged number_of_columns_selectable_value number_of_columns_selectable_value Unchanged number_of_configurations number_of_configurations Unchanged number_of_rows number_of_rows Unchanged number_of_rows_constant_value number_of_
52. n Table 3 default value is 15 number_of_columns_ selectable_value Integer in the range defined in Table 3 default value is 4 number_of_ configurations Integer in the range defined in Table 3 default values is 1 number_of_rows constant selectable variable number_of_rows_ constant_value Integer in the range defined in Table 3 default value is 15 number_of_rows_ selectable_value Integer in the range defined in Table 3 default value is 4 pipelining minimum maximum medium has_rdy true false row_permutations none use_coe_file_to_define_row_permutations row_port_width Integer in the range defined in Table 3 default value is 4 has_row_sel_valid true false DS861 October 19 2011 Product Specification www xilinx com 47 XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 19 Parameter File Information Cont d XCO Parameter Valid Values has_row_valid true false has_aresetn true false symbol_memory internal external symbol_width Integer in the range defined in Table 3 default value is 1 type forney rectangular has_dout_tready true false external_memory_latency 0to6 Core Resource Utilization The area of the Forney Convolutional Interleaver increases with the number of branches the length of the branches and the symbol width Some example configurations are shown in Table 20
53. n as 0 e Handle Obsolete features e FDis no longer available The core starts a block when The first symbol is seen after a reset When the first symbol is seen after the end of a block in Rectangular mode When the first symbol is seen after the end of a block in Forney mode This is when the commutator reaches branch 0 after s_axis_data_tlast has been asserted e FD abortis no longer available Enough symbol data has to be supplied to bring a block to a natural conclusion or aresetn has to be used to reset the core In Forney mode this means blocks must now be an integer multiple of the number of branches in use Parameter Values in the XCO File Table 19 defines valid entries for the XCO parameters Parameters are not case sensitive Default values are dis played in bold Xilinx strongly suggests that XCO parameters not be manually edited in the XCO file instead use the CORE Gen erator GUI to configure the core and perform range and parameter value checking DS861 October 19 2011 www xilinx com 46 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 19 Parameter File Information XCO Parameter architecture Valid Values rom_based logic_based has_block_end true false block_size_constant_ value Integer in the range defined in Table 3 default value is 15 block_size_port_width Integer in the range defined in Table 3 default value is 4 blo
54. n in Table 3 event_col_ valid This optional output is available when a variable number of columns is selected If an illegal value is sampled on the COL field of the Control Channel event_col_valid goes low a predefined number of clock cycles later Table 9 lists the number of clock cycles from the first symbol being sampled high to event_col_valid changing See Table 3 for details of illegal COL values DS861 October 19 2011 Product Specification www xilinx com 35 XILINX LogiCORE IP Interleaver De Interleaver v7 0 event_col_sel_ valid This optional output is available when a selectable number of columns is chosen If an illegal value is sampled on the COL_SEL field of the Control Channel event_col_sel_valid goes low a predefined number of clock cycles later Table 9 lists the number of clock cycles from the first symbol being sampled high to event_col_sel_valid changing See Table 16 for an explanation of an illegal COL_SEL value event_row_valid This optional output is available when a variable number of rows is selected If an illegal value is sampled on the ROW field of the Control Channel event_row_valid goes low a predefined number of clock cycles later Table 9 lists the number of clock cycles from the first symbol being sampled high to event_row_valid changing See Table 3 for details of illegal ROW values event_row_sel_ valid This optional output is available when a selectable number of rows is chosen
55. nfigurations Each configuration can have a different number of branches and branch length constant It is even possible for each configuration to have every individual branch length defined by file The configuration can be changed at any time by sending a new CONFIG_SEL value on the AXI Control Channel This value takes effect when the next block starts The core assumes all configurations are either for an interleaver or de interleaver depending on what was selected in the GUI It is possible to switch between interleaving and de interleaving by defining the individual branch lengths for every branch of each configuration The details for each configuration are specified in a COE file See COE Files for Multiple Configurations page 23 for details The timing for a configuration swap is described in Multiple Configuration Timing page 26 Rectangular Block Operation The Rectangular Block Interleaver works by writing the input data symbols into a rectangular memory array in a certain order and then reading them out in a different mixed up order The input symbols must be grouped into blocks Unlike the Convolutional Interleaver where symbols can be continuously input the Rectangular Block Interleaver inputs one block of symbols and then outputs that same block with the symbols rearranged No new inputs can be accepted while the interleaved symbols from the previous block are being output The rectangular memory array is composed of a number o
56. ng have the effect of adding registers to certain inputs in the Convolutional type Maximum pipelining results in some additional internal registering within the core compared to Medium pipelin ing In the Rectangular Block type a number of internal circuits are pipelined to improve performance Medium and Maximum pipelining are actually identical for the Rectangular Block type Optional Pins Check the boxes of the optional pins that are required Each selected pin can result in more FPGA resources being used and can result in a reduced maximum operating frequency DS861 October 19 2011 www xilinx com 14 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Control Signals ACLKEN Input The acl ken Clock Enable input is an optional input pin When aclken is deasserted low all the synchronous inputs are ignored and the core remains in its current state If aresetn and aclken are asserted at the same time aresetn takes precedence ARESETN Input When aresetn active low reset is asserted low all the core flip flops are synchronously initialized The core remains in this state until aresetn is deasserted If aresetn and aclken are asserted at the same time aresetn takes precedence The synchronous initialization resets only the core control logic The symbol memory itself is not cleared ARESETn is an optional pin Forney Convolutional Specific Parameters Number of Branches The v
57. nt d Signal 1 0 Description M_AXIS_DATA_TUSER TUSER for the Data Output Channel Optional signal Can contain the following fields in Forney mode e FDO Output e RDY Can contain the following fields in Rectangular mode e BLOCK_START e BLOCK_END M_AXIS_DATA_TLAST TLAST for the Data Output Channel Output In Forney mode asserted every time a symbol is produced from the last branch In Rectangular mode asserted when the last symbol is produced for a block RD_ADDR Output Read address for external symbol RAM p Only present if the core is configured to have External Symbol Memory RD_DATA Input Read data value from external symbol RAM P Only present if the core is configured to have External Symbol Memory RD_EN Read enable for external symbol RAM High when reading data from external Output symbol RAM Only present if the core is configured to have External Symbol Memory WR_ADDR Output Write address for external symbol RAM p Only present if the core is configured to have External Symbol Memory WR_DATA Output Write data value for external symbol RAM p Only present if the core is configured to have External Symbol Memory WR_EN Output Write enable for external symbol RAM High when writing data to external symbol put RAM Only present if the core is configured to have External Symbol Memory EVENT_ROW_VALID 1 when the value in the Control Channel s ROW field is valid Becomes 0 if the
58. ntered in the GUI Care should be taken not to make this any larger than necessary as doing so increases the size of the core ROW_SEL is resampled at the start of each new block when the first symbol is sampled The number sampled from the ROW_SEL input tells the core which value to use from the COE file O means use the first value 1 the second and so on An illegal value on ROW_SEL is indicated on the event_row_sel_valid output An example of an illegal ROW_SEL value would be three possible numbers of rows being defined in the COE file These would be selected using a two bit ROW_SEL bus 00 01 and 10 would all be valid ROW_SEL inputs but 11 would be illegal because there is no corresponding row number for that ROW_SEL value in the COE file DS861 October 19 2011 www xilinx com 41 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 16 Control Channel TDATA Fields Cont d Field Name Description COL This optional field is automatically selected if the variable number of columns option is chosen in the GUI The width of the input is also entered in the GUI Care should be taken not to make this field any wider than necessary as this increases the size of the core COL is resampled at the start of each new block when the first symbol is sampled The number sampled from the COL input tells the core how many columns there are in the block Illegal values on COL are indicated on the e
59. nterleaver core ignores the value of the padding bits so they can be driven to any value TDATA Format The Data Input Channel s TDATA vector s_axis_data_tdata has one field DIN which is packed as follows s_axis_data_tdata MSB downto 0 7 N 7 N Lanta l PAD DIN Io Padding only required if data width Optional fields are not a multiple of 8 Value ignored by core shown as dotted Figure 31 Data Input Channel TDATA s_axis_data_tdata Format Note In Forney mode every symbol sampled on this channel causes a new symbol to be output on the Data Output Channel Data Output Channel The Data Output Channel carries symbol data that has been interleaved or deinterleaved and a selection of information flags The data is carried in TDATA and the flags in TUSER As all of these flags are individually optional the TUSER vector might not always be present In Forney mode one new symbol is output on the Data Output Channel for each input symbol sampled on the Data Input Channel The number of clock cycles between an input symbol being sampled and a new output appearing is termed the latency of the core This is not the number of cycles from a particular symbol being sampled on the Data Input Channel and the same symbol finally appearing on the Data Output Channel For the first symbol this is termed the FDO delay and is dependent on the interleaver branch lengths This delay is different for each input symbol because of the interleaving proces
60. number of additional registers inserted wr_addr wr_data rd_data DS861_23 081911 Figure 27 Calculating EXTERNAL_MEMORY_LATENCY The CORE Generator software automatically determines the required address bus width This value is also dis played on the final page of the core GUI The timing for accessing the external symbol RAM is identical to the timing for accessing a synchronous dual port block RAM inside the FPGA Figure 28 shows the timing of the dual port external RAM interface for a Convolutional Interleaver example The first write to external memory occurs at t2 when 1 is written to address 0 The first read occurs at t3 when address 1 is read This causes the first real symbol to appear on RD_DATA at t4 and as the EXTERNAL_MEMORY_LATENCY is 0 in this example and because there is no TREADY on the Data Output Channel the symbol is passed straight through to m_axis_data_tdata If TREADY had been enabled on this channel it would take a further 2 clock cycles for the data to appear The value of this symbol is shown XX as because this is a residual value left over from the previous interleave operation No write occurs at t4 because s_axis_data_tvalid was low at t1 Similarly RD_EN is low at t5 so no read occurs at that time and m_axis_data_tvalidis 0 at t6 The timing diagram does not show realistic clock to output delays as this is a function of where the final output registers are placed in the FPGA preferably in the IOBs
61. nvolutional Latency Pipelining Latency 2 Minimum 4 Medium 5 Maximum 6 Note 1 Add one clock cycle to these figures if external symbol RAM is used 2 Add two clock cycles to these figures if the Data Output Channel has a TREADY XCO DOUT_HAS_TREADY true The FDO delay is the delay from the first symbol being sampled to that symbol being output on the Data Output Channel The FDO delay is comprised of two parts a number of valid symbols including the first symbol and the latency The GUI reports the FDO delay as the number of new symbols that must be sampled including the first symbol plus latency clock cycles This is when FDO is actually asserted The number of new symbols that must be sampled is dependent on the number of branches and the length of branch 0 An example with a latency of four clock cycles is shown in Figure 17 s_axis_data_tready is permanently high in this example so is not shown When the symbol with value 1 is sampled a new symbol with value XX appears on DOUT after four clock cycles They do not have the same value because the symbols are interleaved The value XX is used to indicate symbols that are not part of the current frame for example values come from an unini tialised memory location or a symbol that was written in the previous frame The first symbol that was sampled value 1 finally appears on DOUT when FDO goes high I acik a ia p E s_axis_data_tvalid l l j
62. o store a small number of symbols Pinout Table 12 Data Output Channel Pinout Port Name Port Width Direction Description m_axis_data_tdata Variable Out Carries the symbol data See the CORE Generator GUI when configuring the Symbol Interleaver De interleaver m_axis_data_tuser Variable Out Carries additional per symbol status See the CORE Generator GUI As all status fields are optional TUSER when configuring the Symbol might not always be present Interleaver De interleaver m_axis_data_tvalid 1 Out Asserted by the Symbol Interleaver De interleaver to signal that it is able to provide symbol data a m_axis_data_tlast Out In Rectangular mode m_axis_data_tlast is asserted when the last symbol for a processed block is transmitted In Forney mode m_axis_data_tlast is asserted when a symbol is transmitted from the last branch In this mode m_axis_data_tlast bears no similarity to s_axis_data_tlast s_axis_data_tlast is asserted once per block but m_axis_data_tlast is asserted once every sweep of the commutator m_axis_data_tready 1 In Asserted by the external slave to signal that it is ready to accept data Only available when the core is configured to have a TREADY on the Data Output Channel TDATA Fields The DATA field is packed into the m_axis_data_tdata vector as follows Table 13 Data Output Channel TDATA Fields Field Name Width Padded Description DOUT 1 to 256 Yes sign e
63. ontain ROW ROW_SEL COL COL_SEL and BLOCK_SIZE although not all at the same time These fields are all optional and some are mutually exclusive ROW with ROW_SEL and COL with COL_SEL When a field is not needed for a particular core configuration it is not included in the Control Channel In the case where no fields are present the entire Control Channel is removed from the core s interface Table 16 Control Channel TDATA Fields Field Name Description CONFIG_SEL If the core is configured to have more than one configuration then CONFIG_SEL selects which configuration to use for the current block CONFIG_SEL is sampled when the first symbol is sampled More details on the use of multiple configurations are given in Configuration Swapping page 4 ROW This optional field is automatically selected if the variable number of rows option is chosen in the GUI The width of the input is also entered in the GUI Care should be taken not to make this field any wider than necessary as doing so increases the size of the core ROW is resampled at the start of each new block when the first symbol is sampled The number sampled from the ROW input tells the core how many rows are in the block Illegal values on ROW are indicated on the event_row_valid output ROW_SEL This optional field is automatically selected if the selectable number of rows option is chosen in the GUI The width of the input is determined from the number of selectable rows e
64. page of the core GUI RD_DATA Input This is the read data bus from the external symbol RAM It has the same width as the DIN field in the Data Input Channel ignoring padding RD_EN Output This is the read enable for the RAM The core asserts the RD_EN output high when there is a valid read address on RD_ADDR and it needs to read the contents of that RAM location WR_ADDR Output This is the write address for the external symbol RAM WR_ADDR should be connected to the RAM address bus corresponding to the port used by WR_DATA WR_ADDR must be the same width as RD_ADDR WR_DATA Output This is the write data bus to the external symbol RAM It has the same width as the DIN field in the Data Input Channel ignoring padding WR_EN Output This is the write enable for the external symbol RAM The core asserts the WR_EN output high when there is a valid write address on WR_ADDR and it needs to write to that RAM location The connections for a Rectangular Block Interleaver are shown in Figure 26 This is similar to the dual port case however the Rectangular Block Interleaver does not perform simultaneous reads and writes so only a single port is required The EN input acts as a clock enable for all operations If the core has an aclken input then the RAM should be enabled with the same signal The clock enable could also be sourced from inside the FPGA DS861 October 19 2011 www xilinx com 31 Product Specification
65. parameter is relevant only if variable column type is selected In this case the core has to cope potentially with a wide range of possible values for the number of columns If the smallest value that can actually occur is known then the amount of logic in the core can sometimes be reduced The largest possible value should be used for this parameter to keep the core as small as possible Number of Selectable Columns If the selectable column type has been chosen this parameter defines how many valid selection values have been defined in the COE file Only add select values you need Use Column Permute File This tells the CORE Generator software that a column permute vector exists in the COE file and column permuta tions are to be performed Remember this is only possible for unpruned interleaver de interleavers Row Type There are three possibilities 1 Constant The number of rows is always equal to the Row Constant Value parameter 2 Variable The number of rows is sampled from the ROW field in the Control Channel at the start of each new block Row permutations are not supported for the variable row type 3 Selectable The ROW_SEL field in the Control Channel is sampled at the start of each new block This value is then used to select from one of the possible values for number of rows provided in the COE file Row Constant Value This parameter is relevant only if constant row type is selected The number of rows is fixed at this va
66. pec tively for the next transfer appropriately DS861 October 19 2011 www xilinx com 36 Product Specification XILINX ACLK TVALID TREADY TDATA TLAST TUSER LogiCORE IP Interleaver De Interleaver v7 0 Figure 30 Data Transfer in an AXI4 Stream Channel AXI4 Channel Rules All of the AXI4 channels follow the same rules e All TDATA and TUSER fields are packed in little endian format That is bit 0 of a sub field is aligned to the same side as bit 0 of TDATA or TUSER e All TDATA and TUSER vectors are multiples of 8 bits After all fields in a TDATA or TUSER vector have been concatenated the overall vector is padded to bring it up to an 8 bit boundary Data Input Channel The Data Input Channel carries symbol data to be interleaved or deinterleaved The symbol data is carried in TDATA The channel contains a two element buffer to provide some system elasticity The Data Input Channel is blocked by the Control Channel if present When a symbol in the Data In Channel represents the first symbol for a block it is not processed until a new configuration is seen in the Control Channel The new configuration does not have to be different from the previous configuration Pinout Table 10 Data Input Channel Pinout Port Name s_axis_data_tdata Port Width Variable See the CORE Generator GUI when configuring the Symbol Interleaver De interleaver Direction In Description Carries the symbol da
67. r is relevant only if constant block size type is selected It must meet the constraints described in the Block Size Type BLOCK_SIZE Field Width This parameter is relevant only if variable block size type is selected It sets the width of the BLOCK_SIZE field in the Control Channel ignoring padding The smallest possible value should be used to keep the core as small as possible Column Type There are three possibilities Constant The number of columns is always equal to the Column Constant Value parameter 2 Variable The number of columns is sampled from the COL field in the Control Channel at the start of each new block Column permutations are not supported for the variable column type 3 Selectable The COL_SEL field in the Control Channel is sampled at the start of each new block This value is then used to select from one of the possible values for number of columns provided in the COE file DS861 October 19 2011 www xilinx com 16 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Column Constant Value This parameter is relevant only if constant column type is selected The number of columns is fixed at this value COL Field Width This parameter is relevant only if variable column type is selected It sets the width of the COL field in the Control Channel ignoring padding The smallest possible value should be used to keep the core as small as possible Minimum Number of Columns This
68. rows columns can be used when the number of possible values for the number of rows or columns is known and is relatively small In this mode the number of rows columns is still run time variable but chosen from a small set of predetermined values stored within the core Permutations are possible when using selectable rows or columns A different permutation vector can be stored for each row or column select value DS861 October 19 2011 www xilinx com 8 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Input Data 0 1 2 3 4 5 6 7 8 9 10 11 interleaver I Transmit 6 10 2 5 9 1 7 11 3 4 8 0 De interleaver 1 1 All parameters identical to Interleaver except for Mode Output Data 0 1 2 3 4 5 6 7 8 9 10 11 Figure 7 Block interleaver De interleaver Operation In general the most efficient core is one with constant rows columns and block size The number of optional AXI fields should be kept to a minimum For every optional field or extra feature such as row or column permutations there might be an adverse impact on area and speed More details on the available block size types and choosing the appropriate one are given in Block Size Type The core also provides outputs to check the validity of inputs such as BLOCK_SIZE see Control Channel for more information These can sometimes be useful in a receiver to detect if things
69. rows_constant_value Unchanged DS861 October 19 2011 Product Specification www xilinx com 43 XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 17 XCO Parameter Changes from v6 0 to v7 0 Cont d Version 6 0 Version 7 0 Notes number_of_rows_selectable_value number_of_rows_selectable_value Unchanged pipelining pipelining Unchanged rdy has_rdy Rename rfd Obsolete rffd Obsolete row_permutations row_permutations Unchanged row_port_width row_port_width Unchanged row_sel_valid has_row_sel_valid Rename row_valid has_row_valid Rename sclr has_aresetn Rename symbol_memory symbol_memory Unchanged symbol_width symbol_width Unchanged type type Unchanged has_dout_tready New AXI option external_memory_latency New Option Valid range from 0 to 6 For more information on this upgrade feature see the CORE Generator software documentation Port Changes Table 18 details the changes to port naming additional or deprecated ports and polarity changes from v6 0 to v7 0 Table 18 Port Changes from Version 6 0 to Version 7 0 Version 6 0 Version 7 0 Notes CLK ACLK Rename only CE ALCKEN Rename only SCLR ARESETN Renamed Polarity change now active low Minimum length now two clock cycles DIN S_AXIS_DATA_TDATA Renamed See Data Input Channel ND S_AXIS_DATA_TVALID Renamed RFD S_AXIS_DATA_TREADY No longer op
70. rs the core is halted and all activity stops until space is available in the channel s buffers The event pin is only available when HAS_DOUT_TREADY is true event_block_size_valid This output is available when the block size is not constant That is if the block size type is either variable or equal toR C If the block size type is variable event_block_size_valid signals whether a legal or illegal value is sampled on the BLOCK_SIZE field of the Control Channel If an illegal value is sampled event_block_size_valid goes low a predefined number of clock cycles later If the block size type is R C event_block_size_valid signals that the block size generated from the values sampled on ROW or ROW_SEL or on COL or COL_SEL is legal Table 9 lists the number of clock cycles from the first symbol being sampled to event_block_size_valid or any of the other _VALID outputs changing After a _VALID output has gone low it remains low until Valid Delay clock cycles after the next block is started The latency is defined in Table 6 and always equals a constant Thus the Valid Delay is always constant Table 9 Clock Cycles from First Symbol Selectable Rows or Columns Block Size Type Valid Delay clock cycles Variable latency 2 Row x Column No 3 Row x Column Yes 5 Regardless of the block size type chosen the block size must never go below the absolute minimum value give
71. rtex 6 XC6VLX75T Test cases used an xc6vlx75t ff484 with 1 speed grade device and ISE speed file version PRODUCTION 1 15 2011 07 25 Area LUT FF pairs 1 136 142 Block RAMs 36K 18K 3 0 1 0 1 Maximum Clock Frequency speed grades 1 1 2 Virtex 7 xc7vx485t Test cases used an xc7vx485t ffg1157 with 1 speed grade device and ISE speed file version ADVANCED 1 02a 201 1 07 25 Area LUT FF pairs 1 138 136 Block RAMs 36K 18K 3 0 1 0 1 330 330 Maximum Clock Frequency speed grades 1 1 2 Kintex 7 xc7k160t Test cases used an xc7k160t fbg484 with 1 speed grade device and ISE speed file version ADVANCED 1 01 2011 07 25 Area LUT FF pairs 1 136 142 Block RAMs 36K 18K 3 0 1 0 1 329 335 Maximum Clock Frequency speed grades 1 1 2 304 e Notes 1 Area and maximum clock frequencies are provided as a guide They can vary with new releases of the Xilinx implementation tools 2 Clock frequency does not take clock jitter into account and should be derated by an amount appropriate to the clock source jitter specification 3 This is the total number of block RAMs used when map was run In reality two 18k block RAM primitives can usually be packed together giving an absolute minimum total block RAM usage of block RAMs 36k block RAMs 18k 2 rounded up DS861 October 19 2011 www xilinx com 50 Product Specification XILINX LogiCO
72. s The latency is always the same regardless of branch lengths Latency and the FDO delay are described in Timing Latency and FDO Delay page 24 In Rectangular mode the core does not start to output the symbols from the block in an interleaved de interleaved fashion until all the symbols from the block have been sampled The number of clock cycles between the last input symbol in a block being sampled and the first symbol from that block appearing on DOUT is termed the latency of the core This definition differs from the one used for the Convolutional interleaver The number of cycles from the first symbol being sampled on the Data Input Channel to the first symbol of the same block finally appearing on the Data Output Channel is termed the FDO delay or BLOCK_START delay This delay is dependent on the interleaver block size The delay from an input symbol being sampled on the Data Input Channel to that same symbol finally appearing on the Data Output Channel is different for each input symbol because of the interleaving process Latency and the BLOCK_START delay are described in Timing Latency and FDO Delay page 24 DS861 October 19 2011 www xilinx com 38 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 If TREADY is disabled for this channel then it is not buffered Failure to consume symbols when TVALID is asserted means that the symbol is lost If TREADY is enabled for this channel the channel is buffered t
73. sequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http www xilinx com warranty htm IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps DS861 October 19 2011 www xilinx com 52 Product Specification
74. ta s_axis_data_tvalid 1 Asserted by the upstream master to signal that it is able to provide data s_axis_data_tlast a4 Asserted by the upstream master on the symbol corresponding to the last symbol in a block In Forney mode the last symbol of a block is deemed to be the one that enters the last branch when s_axis_data_tlast is or has been asserted For example if s_axis_data_tlast is asserted with the symbol that enters branch 3 in a 10 branch system numbered 0 to 9 symbols for branches 4 to 9 are deemed to be part of the current block and the block is not finished until the symbol for branch 9 is consumed If a new control word is waiting in the Control Channel it is not consumed until the symbol for branch 0 after s_axis_data_tlast 1 is consumed s_axis_data_tready i Out Used by the Symbol Interleaver De interleaver to signal that it is ready to accept data DS861 October 19 2011 Product Specification www xilinx com 37 XILINX LogiCORE IP Interleaver De Interleaver v7 0 TDATA Fields The DATA field is packed into the s_axis_data_tdata vector as follows Table 11 Data Input Channel TDATA Fields Field Name Width Padded Description DIN 1 to 256 Yes The symbol data to be interleaved or deinterleaved The DIN field should be extended to the next 8 bit boundary if it does not already finish on an 8 bit boundary The Symbol Interleaver De i
75. talled from the Xilinx IP Center for use with the Xilinx CORE Generator software v13 3 The CORE Generator software is bundled with the ISE Design Suite software v13 3 at no additional charge Contact your local Xilinx sales representative for pricing and availability on Xilinx LogiCORE products and soft ware Revision History The following table shows the revision history for this document Date Version Revision 10 19 11 1 0 Initial Xilinx Release for AXI interfaces Previous non AXI version is DS250 DS861 October 19 2011 www xilinx com 51 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Notice of Disclaimer The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or con
76. tion XILINX LogiCORE IP Interleaver De Interleaver v7 0 Pinout Some of the pins are optional These should be selected only if they are genuinely required as their inclusion might result in an increase in the core size Representative symbols for the Forney Convolutional type and Rectangular Block type are shown in Figure 8 and Figure 9 respectively Table 2 summarizes the signal functions They are described in more detail in AXI4 Stream Considerations Timing examples are shown in Timing Latency and FDO Delay page 24 Table 2 Core Signal Pinout Signal 1 0 Description ACLK Input Rising edge clock ALCKEN Input Active high clock enable optional If aresetn and aclken are asserted at the same time aresetn takes precedence ARESETN Active low synchronous clear optional A minimum aresetn active pulse of two Input cycles is required If aresetn and aclken are asserted at the same time aresetn takes precedence S_AXIS_DATA_TVALID TVALID for the Data Input Channel Used by the external master to signal that it is Input able to provide data S_AXIS_DATA_TREADY Output TREADY for the Data Input Channel Used by the Symbol Interleaver De interleaver PU to signal that it is ready to accept data S_AXIS_DATA_TDATA input TDATA for the Data Input Channel P Carries the unprocessed symbol data S_AXIS_DATA_TLAST TLAST for the Data Input Channel In Forney mode signals that the block ends Input w
77. tional FD Removed RFFD Removed ROW S_AXIS_CTRL_TDATA Renamed See Control Channel ROW_SEL S_AXIS_CTRL_TDATA Renamed See Control Channel COL S_AXIS_CTRL_TDATA Renamed See Control Channel COL_SEL S_AXIS_CTRL_TDATA Renamed See Control Channel BLOCK_SIZE S_AXIS_CTRL_TDATA Renamed See Control Channel CONFIG_SEL S_AXIS_CTRL_TDATA Renamed See Control Channel NEW_CONFIG S_AXIS_CTRL_TVALID Renamed DS861 October 19 2011 Product Specification www xilinx com 44 XILINX LogiCORE IP Interleaver De Interleaver v7 0 Table 18 Port Changes from Version 6 0 to Version 7 0 Cont d Version 6 0 Version 7 0 Notes S_AXIS_CTRL_TREADY New signal DOUT M_AXIS_DATA_TDATA Renamed See Data Output Channel NDO M_AXIS_DATA_TVALID Renamed M_AXIS_DATA_TREADY New signal Optional signal RDY M_AXIS_DATA_TUSER in Forney mode Renamed See Data Output Channel M_AXIS_DATA_TVALID in Rectangular mode FDO M_AXIS_DATA_TUSER Renamed See Data Output Channel BLOCK_START M_AXIS_DATA_TUSER Renamed See Data Output Channel BLOCK_END M_AXIS_DATA_TUSER Renamed See Data Output Channel RD_DATA RD_DATA No change RD_EN RD_EN No change WR_EN WR_EN No change RD_ADDR RD_ADDR No change WR_ADDR WR_ADDR No change WR_DATA WR_DATA No change ROW_VALID EVENT_ROW_VALID Rename COL_VALID EVENT_COL_VALID Rename ROW_SEL_VALID EVENT_ROW_SEL_VALID Rename COL_SEL_VALID EVENT_COL_S
78. tional fields are shown as dotted Figure 33 Data Output Channel TUSER m_axis_data_tuser Format DS861 October 19 2011 www xilinx com 40 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Control Channel The Control Channel s_axis_ctr1 contains the information needed to configure the interleaving or deinterleaving process The Control Channel blocks the first symbol for a block in the Data Input Channel That is if the core has a Control Channel the first symbol for a block remains in the Data Input Channel until a control word is received in the Control Channel Pinout Table 15 Control Channel Pinout Port Name Port Width Direction Description s_axis_ctrl_tdata Variable In Can contain the following field in Forney mode See the CORE Generator e CONFIG SEL GUI when configuring the 7 Can contain the following fields in Rectangular mode e ROW e ROW_SEL e COL e COL_SEL e BLOCK_SIZE Asserted by the external master to signal that it is able to provide data Symbol Interleaver De interleaver 3 s_axis_ctrl_tvalid s_axis_ctrl_tready 1 Out Asserted by the Symbol Interleaver De interleaver to signal that it is able to accept data TDATA Fields In Forney mode the TDATA vector consists of one field CONFIG_SEL This is optional and when it is not present the entire control channel is removed from the core s interface In Rectangular mode it can c
79. to drive an enable input external to the core It is necessary to AND it with aclken WR_ADDR Output This is the write address and is just a duplicate of RD_ADDR WR_DATA Output This is the write data bus to the external symbol RAM It has the same width as the DIN field in the Data Input Channel ignoring padding WR_EN Output This is the write enable for the external symbol RAM The core asserts the WR_EN output high when there is a valid write address on WR_ADDR and it needs to write to that RAM location All the outputs for the external RAM are registered in the core To achieve predictable timing when accessing the external RAM these registers should be mapped into IOBs using the appropriate mapper options It is possible to insert additional registers on the external memory interface if required to meet timing The same number of regis ters must be added to every output signal but they do not have to match the number on rd_data The delay in clock cycles added by the registers on the outbound path and the inbound path must be specified in the GUI s External DS861 October 19 2011 www xilinx com 32 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 Memory Latency edit box See Figure 27 for an example In this case the outbound latency is 3 and the inbound latency is 1 so EXTERNAL_MEMORY_LATENCY should be set to 4 This increases the latency of the interleaver core by the
80. tvalid was deasserted but this has no effect on the rate at which data is output on the Data Output Channel It is possible to overlap the processing of two blocks Figure 22 shows the loading of second block starting immedi ately after the first block is loaded The first two symbols values 11 and 12 are immediately taken by the core as there is space in the Data Input Channel for them However the next symbol value 13 is stalled by the core by deasserting s_axis_data_tready This is because the core is internally still processing the previous frame and cannot use these symbols yet The new control word BLOCK_SIZE 9 has also been accepted by the core but has not yet been used After a certain amount of time the core starts to accept new symbols on the Data Input Channel even though it is still unloading symbols for the previous frame The time between the last symbol of frame N being sampled and the core starting to process the first symbol of frame N 1 is always equal to the block length 2 of frame N When it has DS861 October 19 2011 www xilinx com 28 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 started processing symbols internally it accepts new symbols on the Data Input Channel by asserting s_axis_data_tready ee ee Ee ee Ee Lee eee EEE E E E E a a E S S E E E E E s_axis_ctrl_tvalid s_axis_ctrl_tdata BLOCK_SIZE o s_axis_data_tvalid Symbols for block 2
81. value Output in invalid See event_row_valid for more information Only present if the core is configured to be in Rectangular mode EVENT_COL_VALID 1 when the value in the Control Channels COL field is valid Becomes 0 if the value Output in invalid See event_col_valid for more information Only present if the core is configured to be in Rectangular mode EVENT_ROW_SEL_VALID 1 when the value in the Control Channel s ROW_SEL field is valid Becomes 0 if the Output value in invalid See event_row_sel_valid for more information Only present if the core is configured to be in Rectangular mode EVENT_COL_SEL_VALID 1 when the value in the Control Channel s COL_SEL field is valid Becomes 0 if the Output value in invalid See event_col_sel_valid for more information Only present if the core is configured to be in Rectangular mode EVENT_BLOCK_SIZE_VALID 1 when the value in the Control Channel s BLOCK_SIZE field is valid Becomes 0 if Output the value in invalid See event_block_size_valid for more information Only present if the core is configured to be in Rectangular mode EVENT_TLAST_UNEXPECTED Asserted on every clock cycle where s_axis_data_tlast is unexpectedly seen asserted that is asserted on a symbol that is not the last symbol The meaning of Output Last Symbol varies between Forney and Rectangular mode e Forney a symbol corresponding to the last branch e Rectangular the final symbol loaded for a block EVENT_TLAST_MISS
82. vent_col_valid output COL_SEL This optional field is automatically selected if the selectable number of columns option is chosen in the GUI The width of the input is determined from the number of selectable columns entered in the GUI Care should be taken not to make this any larger than necessary as this increases the size of the core COL_SEL is resampled at the start of each new block when the first symbol is sampled The number sampled from the COL_SEL input tells the core which value to use from the COE file O means use the first value 1 the second and so on The value sampled on COL_SEL must correspond to a predefined number of columns in the COE file An illegal value on COL_SEL is indicated on the event_col_sel_valid output An example of an illegal COL_SEL value would be three possible numbers of columns being defined in the COE file These would be selected using a two bit COL_SEL bus 00 01 and 10 would all be valid COL_SEL inputs but 11 would be illegal because there is no corresponding column number for that COL_SEL value in the COE file BLOCK_SIZE This optional field is automatically selected if variable block sizes are chosen in the GUI The width of the input is also entered in the GUI Take care not to make this field any wider than necessary as this increases the size of the core BLOCK_SIZE is resampled at the start of each new block when the first symbol is sampled Illegal values on BLOCK_SIZE are indicated on th
83. xtended The processed symbol data This field always has the same width as DIN The DATA field is sign extended to the next 8 bit boundary if it does not already finish on an 8 bit boundary TDATA Format The Data Output Channel s TDATA vector m_axis_data_tdata has one field DOUT which is packed as shown in Figure 32 m_axis_data_tdata MSB downto 0 7 N 7 S PAD DOUT SeS Padding only required if DATA width not a multiple of 8 Value is the sign Optional fields are extension of the data shown as dotted Figure 32 Data Output Channel TDATA m_axis_data_tdata Format DS861 October 19 2011 www xilinx com 39 Product Specification XILINX LogiCORE IP Interleaver De Interleaver v7 0 TUSER Fields The Data Output Channel carries the fields in Table 14 in its TUSER vector Table 14 Data Output Channel TUSER Fields Field Name Width Padded Description FDO 1 No Forney mode only Asserted when the first symbol in a block appears on the Data Output Channel The FDO field is useful for synchronizing circuits downstream of the interleaver It can be used to tell those circuits when to start a new block if the data is arranged in blocks RDY 1 No Forney mode only The RDY Ready field signals valid data on DOUT It is similar to m_axis_data_tvalid the difference being that RDY is not asserted until the first symbol sampled on the Data Input Channel finally appears on DOUT m_axis_data_tv

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