AXM-A70 User`s Manual
Contents
1. _ S 7 SN IS KL z PIN 34 PE PIN 68 ANSA 33 det PIN 1 PIN 35 ER PIN 1 a PIN 35 FRONT VIEW Pi GT MODEL 5028 420 ULTRA SCSI VHDCI TO SCHEMATIC SCSI 3 68 PIN CABLE ASSEMBLY SHIELDED 4502 153A Ji 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 3 3 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 65 67 68 TB1 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 20 23 24 25 26 27 28 29 30 31 32 33 34 35 96 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 63 MODEL 5025 288 TERMINATION PANEL SCHEMATIC Le ARE TIED TO J1 TTT METAL HOUSING A so PIN 68 TB2 57 z gt 22 L 4 TB2 12. AXM A75 User s Manual Multifunction I O Mezzanine Board Analog Inputs Noise and Grounding Considerations Non Isolation Considerations Differential inputs require two leads and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating It must be referenced to analog common on the AXM module and be within the normal input voltage range Shielded cable of the shortest length possible is strongly recommended The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections 3 0 PROGRAMMING INFORMATION AXM A75 Memory Map This Section provides the specific information necessary to program and operate the mezzanine board This mezzanine board is intended only for use on specific Acromag PMC XMC FPGA modules As such only a small portion of I O memory space is currently reserved for operation of the mezzanine board The remaining memory space is defined in the base board s User s Manual The AXM A75 specific memory space address map for the board is shown in Table 3 1 Note that the base address from the base PMC XMC module in memory space must be added to the ad
3. Table 3 17 DAC Offset Correction OFF ore OFS OFF ors orz OFT Gio pt 1 1 1 RE EE E RE e A LI E ofofofofi pope pepe pe KM EE No adusment o o 0 ases 1 0 0 psss Jajoo Note the LDAC bit in the control register must be written to trigger a transfer from the DAC data registers to the DAC offset register Updating DAC outputs The values written to the DAC data registers are not immediately applied to the DAC outputs The LDAC bit in the control register must be written to trigger a transfer from the DAC data registers to the DAC outputs see Table 3 4 The transfer from the data register to DAC outputs occurs simultaneously for all DAC channels 4 0 THEORY OF OPERATION Field I O Connections The field I O interface to the AXM A75 is provided through connector P1 refer to Table 2 1 Field I O signals are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 0 for 22 AXM A75 User s Manual Multifunction I O Mezzanine Board connection recommendations Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage AY A 16 16 bit 16 Digital I O e 3 CONVERT1 ani yl 16bit SCLK1 A D A2D_DATA1 j e 16 channels PEP CONVERT16 TO 1 0 ANIE 16 bi
4. e Each ADC channel includes a FIFO capable of storing 2050 samples e All enabled ADC channels are sampled simultaneously ADC sample rate can range from 1 34 Hz to 500 KHz e Control of DAC gain selection AXM A75 User s Manual ENGINEERING DESIGN KIT BOARD CONTROL SOFTWARE Multifunction I O Mezzanine Board Analog Input FIFO Status Interrupts Interrupts can be generated when an input channel s FIFO half full condition is reached or when a FIFO overflow occurs Acromag does not provide an engineering design kit specifically for the AXM A75 module However an example design is included in the Engineering Design Kit of the PMC XMC base board Refer to the PMC XMC base board s manual for further information on the available Engineering Design Kit Acromag does not provide board control software specifically for the AXM A75 series board However the AXM A75 module can be accessed via the control software for the base PMC or XMC module These products sold separately facilitate the product interface in the following operating systems Windows DLL VxWorks and Linux Refer to the PMC XMC base board s manual for further information 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Y CAUTION SENSITIVE ELECTRON DEVICES DD MIT site OR STORE NEAR ETADAD CARD CAGE CONSIDERATIONS Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is bad
5. AXM A75 User s Manual CorrectedData DAC Channels DAC Data Register Multifunction I O Mezzanine Board CountCALHI CountCALLO VoltsCALHI VoltsCALLO ActualIntercept CountCALHI ActualSlope VoltsCALHI Offset IdealZero AcualSlope ActualIntercept IdealSlope ActualSlope Of fsetCorrection Offset ActualSlope CorrectionFactor GainCorrection CorrectionFactor 2 The values calculated for OffsetCorrection and GainCorrection are stored in FLASH memory for each gain selection for each ADC channel The values are then used in the following equation to correct each input sample for offset and gain errors CountIN Of fsetCorrection GainCorrection 216 Note The average of many ADC values e g 2048 should be used when calculating new correction coefficients to reduce the measurement uncertainty There are four registers associated with each of the eight ADC channels data coarse gain correction fine gain correction and offset correction The data register is a 16 bit write read register Reading this register will retrieve the last value that was loaded into the DAC register for that channel Each of the D A channels will apply a gain and offset correction to each output word The addition and multiplication operations are done in each DAC device The gain and offset registers are set to one and zero respectively upon reset to pass uncorrected DAC values to the outputs Typical start
6. Hex D31 D16 D15 DOO Hex 8297 ADC 10 gain correction 8294 ADC 10 offset 8298 829C ADC 11 data 82A0 8247 82A4 8248_ ADCitoffst 8208 82AC 8283 ADC12data 8280 8287 8284 8288_ ADci2offset 8288 82BF 82BC 82c3 ADC13data 8200 82C7 82C4 82cB ADCH offset 82c8 82CF 82cc __ ADC14data 8200 82D7 82D4 8208_ ADC14offset 8208 82DC __ ADC15data 82E7 ge ADC15offset 8268 82EC __ ADCi6data 82F7 ADC 16 gain correction 88 ADCIGOffset 8258 82FC Dacidata 8300 829B 8307 DAC 1 fine 830B gain 8308 DAC 1 offset 830C 8313 8310 DAC 2 coarse 8317 gain 8314 DAC 2 fine 831B gain 8318 DAC 2 offset 831C __ DAC3data DAC 3 coarse 8327 gain 11 831F AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 Hex 8328 832C coarse gain DAC 4 fine DAC 4 DAc5data 8340 DAC5 coarse 6coarse gain DAC 6 fine DAC 6 Dac7data 8360 DAC 7 coarse DAC 8 fine gain 8378 DAC 8 8380 y 1FFFFC 12 AXM A75 User s Manual Multifunction I O Mezzanine Board FLASH Data Format Factory calibration constants are stored in FLASH memory The FLASH memory device is a Numonyx M25P10 Table 3 2Error Reference source not found shows the memory map of the FLASH contents All numeric constants are 32 bit values stored in little endian byte order Table 3 2 FLASH Memory Map Addr D31 D16 bis Doo Add
7. 0007 FLASH ID AXM A75 null terminated 0000 character string 000B 10 24 Volt Range Channel 1 Offset 0008 10 24 Volt Range Channel 2 Offset 000C 0013 10 24 Volt Range Channel 3 Offset 0010 0047 0044 0048 0048 004C 0087 0084 0088 0088 008F 008C 0090 00C7 00c4 00CB 00C8 00CF 00CC 00DO 0107 0104 010B 0108 010F 010C 0113 0110 0147 0144 0148 0148 014F 014C 0153 0150 13 AXM A75 User s Manual Multifunction I O Mezzanine Board 0188 018F 0193 01C7 01C4 01CB 01C8 01CF o1cc 0103 01D0 0207 0208 0208 020C 0213 0210 0227 0247 0248 0248 024C 0267 DAC Gain Channel 8 0264 Board Status and Reset Register Read Write PCIBar2 8000H This read write register is used to issue a software reset view and clear pending interrupts and to identify the attached AXM module It may also provide other functions that are defined by the base board Writing a 1 to bit 31 of this register will cause a software reset affecting both the PMC base board and the majority of AXM A75 registers Bits 15 to 13 are used for AXM identification code Read of this register reflects the interrupt pending status Readofa 1 in bits 1 or O indicates that an interrupt is pending for the corresponding interrupt Table 3 3 Board Status and Reset Register 8000H FUNCTION Software Reset Write Only 14 AXM A75 User s Manual Multifunction I O Mezzanine Board BIT FUNCTION 30 16 Reserved for
8. 6 1 Electric Fast Transient Immunity Designed to comply with IEC61000 4 4 class A Radiated Emissions Designed to comply with CISPR 16 2 3 class A Electrostatic Discharge Designed to comply with IEC6100 4 2 Level 2 Conducted Radio Frequency Interference Designed to comply with IEC6100 4 6 class A 26 AXM A75 User s Manual Multifunction I O Mezzanine Board Power Requirements 3 3 Volts 15 39 MA typical 50 mA maximum 5 Volts 15 54 mA typical 65 mA maximum 12V 15 103 MA typical 115 MA maximum A zy O EE 92 mA typical 115 mA maximum ANALOG INPUTS AS Ed oO tia ADI AD7686 Input Channels 2222224111111112 16 differential Input Signal Type Voltage Non isolated Input Ranges 10 24 5 12 2 56 and 1 28 V Input Overvoltage Protection 31V with power on 19 V with power off Input Resistance 5 300 GQ typical differential Input Bias Current 11111111 5 nA typical 40 nA maximum Common Mode Rejection Ratio 98 dB typical 60 Hz Input Channel to Input Channel Rejection Ratio 41 dB typical 100 kHz Output Channel to Input Channel Rejection Ratio 85 dB typical 1 kHz ACCUFACV ici Gain Full Scale 25 C Full Scale 0 70 C 1 0 011 0 026 2 0 013 0 029 4 0 015 0 033 8 0 018 0 040 Programmable Gain Instrumentation Amplifier Device ADI AD8251
9. RESET signals are common to both DACS Each of the analog input channels consists of a differential low pass filter followed by an instrumentation amplifier a difference amplifier and an ADC The differential low pass RC filter is intended to reduce RF interference The 3db cutoff frequency of the filter is 421 kHz differential 8 84 MHz common mode An Analog Devices AD8251 Programmable Gain Instrumentation Amplifier PGA takes as input the channel s and inputs and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the gain selection bits in the control register The gain selection affects all channels 24 AXM A75 User s Manual Multifunction I O Mezzanine Board The output from the PGA is input to a Texas Instruments INA159 level translation difference amplifier that divides its input voltage by 5 and level shifts the output by one half of the 4 096 reference voltage The output from the difference amplifier drives an Analog Devices AD7686 16 bit 500 kSPS ADC Each of the ADCs has separate clock convert and serial data connections to the FPGA allowing synchronous acquisition and simultaneous data transfer 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT
10. add in boards The dense packing of the mezzanine modules to the carrier board alone results in elevated module and carrier board temperatures and the restricted air flow within the chassis aggravates this problem Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering AXM A75 User s Manual Multifunction I O Mezzanine Board Front Panel Field I O Connector J1 The AXM A75 front panel field I O connector J1 is a 68 pin VHDCI receptacle A cable assembly and termination panel or user defined terminations can be quickly mated to the field I O connector The pin assignment for this connector is shown in Table 2 1 Table 2 1 J1 Pin Assignment in Description Number pin Description Number GND voi gt oe bos 3 po 37 bos 4 bios 38 vio 5 p 3 bos 6 bios 4 Don 8 nos 4 Don 9 nos as eD 16 voum so eo lui vs ss GND ae 10 o The sixteen differential analog input channels are labeled VINx and VINx where x is the channel number 1 to 16 Analog outputs are labeled VOUTx where x is the channel number 1 to 8 Digital input output signals are labeled DIOx where x is bit 0 to 15 Signal returns are labeled GND
11. base board AXM Identification bits Read Only 15 13 AXM EDK 001 AXM A75 011 12 2 Reserved for base board 1 FIFO overflow interrupt pending FIFO half full interrupt pending Control Register Read Write PCIBar2 8100H The control register is used to enable interrupts control amplifier gain control the FLASH chip select signal and start stop the A D converter for each channel See Table 3 4 for a description of each of the register bits Table 3 4 Control Register 8100H FUNCTION 1 FIFO overflow interrupt enable FIFO half full interrupt enable 7 B 30 Amplifier Gain 00 Gain 1 full scale input range 10 24 Volts 01 Gain 2 full scale input range 5 12 Volts 10 Gain 4 full scale input range 2 56 Volts 11 Gain 8 full scale input range 1 28 Volts FLASH Select This bit is connected directly to the select input of the serial FLASH device LDAC transfer DAC data from data registers to output registers all channels write only read zero CLR clear DAC data registers to 0x00 all channels write only read zero 24 16 15 0 Convert channel 16 1 each channel can be individually controlled 0 channel stopped 1 enable continuous conversion 15 AXM A75 User s Manual Multifunction I O Mezzanine Board Status Register 0 Read Write PCIBar2 8104H Status Register 0 provides access to the FIFO overflow and half full stat
12. up operation would include reading factory calibration constants from AXM A75 on board FLASH memory and writing the appropriate correction values for the currently selected full scale range to the coarse gain fine gain and offset registers for each channel The DAC data format is 16 bit offset binary The ideal output from the DAC for some select output codes is shown in Table 3 14 The full scale range FSR is controlled by the coarse gain selection register for 20 AXM A75 User s Manual DAC Coarse Gain Register DAC Fine Gain Register Multifunction I O Mezzanine Board each channel See Table 3 4 The FSR choices are 10 10 2564 and 10 5263 Volts Table 3 14 DAC Data Format The coarse gain register is a two bit register that allows the selection of one of three Full Scale Ranges 10 10 2564 and 10 5263 Volts as shown in Table 3 15 There is a separate coarse gain register for each channel Table 3 15 DAC Coarse Gain Selections Register Value The fine gain register is a six bit register that allows the user to adjust the gain of each DAC by 32 LSBs to 31 LSBs in 1 LSB steps as shown in Table 3 16 Table 3 16 DAC Fine Gain Selections 21 AXM A75 User s Manual Multifunction I O Mezzanine Board DAC Offset Register The offset register is an eight bit register that allows the user to adjust the offset of each DAC by 16 LSBs to 15 875 LSBs in steps of one eighth LSB as shown in Table 3 17
13. 2 3 40 86 36 PLACE MODEL SERIAL TBI LABEL HERE 0000009000090 0090000900060009000090000000 EL las Y Ss n SIDE VIEW lt 180 34 m TOP VIEW NOTE 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 21 2 23 24 25 26 27 2829 30 3 23 DIMENSIONS ARE IN INCHES 0 100 0 0 0 O O O O O O O TE O O O rr i ir O O O Ir Ir 1 MLUMETERS 35 36 97 3B 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 TERMNATION 2r HAT TIL MARKINGS 68 58 FRONT VIEW 4501 920 32 AXM A75 User s Manual Multifunction I O Mezzanine Board Certificate of Volatility Certificate of Volatility Acromag Model Manufacturer AXM A75 Acromag Inc 30765 Wixom Rd Wixom MI 48393 Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed Yes m No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes No Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 1M bits m Yes Storage of calibration Clear Flash memory by erasing o No constants for A D and all sectors of the Flash D A converters Note calibration constants can be restored by repeating calibration procedure Acromag Representative Name Title Email Office Phone Office Fax Russ Niev
14. 5 0 O input 1 output There are three registers associated with each of the sixteen ADC channels data gain correction and offset correction The data register is a 16 bit read only register Reading this register will retrieve the oldest value from the FIFO associated with that channel Each of the ADC channels will apply a gain and offset correction to each sample prior to writing the result to a FIFO The addition and multiplication operations are done in FPGA hardware using one of the FPGA s DSP blocks for each channel The gain and offset registers are set to one and zero respectively upon reset to pass uncorrected ADC values to the FIFOs Typical start up operation would include reading factory calibration constants from AXM A75 on board FLASH memory and writing the appropriate correction values for the currently 17 AXM A75 User s Manual ADC Data Format ADC Offset Register ADC Gain Register Multifunction I O Mezzanine Board selected full scale range to the gain and offset registers for each channel The output from the ADC is offset binary format as shown in Table 3 12 The full scale range 10 24 5 12 2 56 1 28 is controlled by the gain selection in the control register See Table 3 4 Table 3 12 ADC Data Format DESCRIPTION DIGITAL OUTPUT FFFF 8000 7FFF Full Scale 0000 The offset register contains a 16 bit two s complement value that is added to the value output from the ADC to co
15. 5263 V 8 uS typical full scale step to 1 LSB 10 uS maximum 5 V yS typical 2 LSB maximum 1 LSB maximum 2 mV maximum 4 995 V minimum 5 005 V maximum 10 mA typical 1 mA maximum for specified performance 200 pF maximum with Riorp ee 1000 pF maximum with Rioap 10K Q 0 3 Q maximum 2 ppm full scale range C 2 ppm full scale range C 0 015 full scale 25 C 0 029 full scale 0 70 C 29 AXM A75 User s Manual Multifunction I O Mezzanine Board 7 0 APPENDIX CABLE MODEL 5028 420 Ultra SCSI VHDCI male to SCSI 3 male Round Shielded Type Round shielded cable 34 wire pairs Ultra SCSI VHDCI male and SCSI 3 male connectors The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 288 termination panel to the board Length 2 meters 6 56 feet Cable 34 wire pairs 28 AWG foil braided shield inside a PVC jacket Connectors Ultra SCSI VHDCI and SCSI 3 68 pin male connectors with backshell Keying The connectors have a D Shell Schematic and Physical Attributes See Drawing 4502 153 Electrical Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum at 50 energized SCSI 3 connector spec s Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed 30 A
16. Acromag 4 THE LEADER IN INDUSTRIAL I O AXM A75 Multifunction I O Mezzanine Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 624 0310 Fax 248 624 9234 Copyright 2013 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 927E AXM A75 User s Manual Multifunction I O Mezzanine Board 1 0 2 0 3 0 4 0 GENERAL INFORMATION nc ei 5 KEY FEATURES comia 5 ENGINEERING DESIGN KIT aiioa aero 6 BOARD CONTROL SOFTWARE edia LE aa IL a Z EE 6 PREPARATION FOR USE wot A das 6 UNPACKING AND INSPECTION luce cecco cecco 6 CARD CAGECONSIDERATIONS gt t iii O A A A di ita 6 Front Panel Field I O Connector Jl cccccnnnnononcncninonnnonannnonononananono nono nono nnnnanno nn nc nn cnnnnnnonn nn nana cnnannnn nes 8 Analog Inputs Noise and Grounding ConsiderationS aaa aaa aaa aaa aaa aaa aa aaaaaaaa aaa azininaaa 9 None Isolation Considerations a inerenti 9 PROGRAMMING INFORMATION luce eee cc aaa aaa aaa aaa 0000000 9 AXM A75 Memoryv Map ati da ici eil e ira 9 FLASH Data Format ii E E i ri sian 13 Board Status and Reset Register Read Write PCIBar2 8000H ii 14 Control Register Read Write PCIBar2 8100H ooo aaa aaa anna aaaaaaiai zacznie 15 Status Register O Read Write PCIBar2 8104H oo ccc cccscccssec
17. NS Physical Physical Configuration Single AXM Module Stacking Height 5mm Length sza ana 38 5 mm 1 516 inches See warning below bulle GEE 73 75 mm 2 904 inches Board Thickness 1 59 mm 0 062 inches WARNING The AXM A75 length dimension exceeds the CMC I O envelope as shown in IEEE 1386 2001 Figure 4 1 and Figure 4 2 by 7 5mm limited to 31mm and is not compatible with all PMC XMC carriers The AXM A75 when plugged into a compatible Acromag PMC XMC module will work in most Acromag air cooled non processor carriers including the AcPC46xx APC PMC APCe867x 8 VPX482x models It is not compatible with the VPX481x series or any Acromag processor board that has a PMC XMC slot Contact the factory with any questions Connectors P1 FPGA Interface 162 pin receptacle 5 mm stack height high speed terminal strip Samtec QTS 075 01 L D A K J1 Field I O 68 pin VHDCI receptacle Amphenol HE11 RDA 101 3 C Environmental Operating Temperature O to 70 C Relative Humidity ua 5 95 non condensing Storage Temperature 55 C to 150 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity Designed to comply with IEC61000 4 3 class A Surge IMMUNItY Not required for signal I O per European Norm EN61000
18. PGA Linearity Error 0 005 maximum 3 27 LSB Offset Error RIP 1 0 mV typical 2 5 mV maximum Offset vs Temperature 0 6 1 5 G uV C typical G 1 2 4 8 1 2 5 G uV C maximum 1 Input channel to input channel rejection ratio was measured with a 100 KHz 1V pk pk sine wave input on an adjacent channel 2 The output channel to input channel rejection ratio was measured with all output channels driving a 10k ohm load outputting a 1 kHz 20 V pk pk sine wave Load resistors were located on a termination panel connected to a 2 meter cable 27 AXM A75 User s Manual Gain Error all gains Gain vs Temperature Difference Amplifier DIE a lina Gain Error Gain Error vs Temperature Offset Error Offset Voltage vs Temperature Reference Divider Accuracy Voltage Reference REF3240 DEVICE Accuracy Multifunction I O Mezzanine Board 0 01 typical 0 1 maximum 3 ppm C typical 10 pm C maximum TI INA159 0 005 typical 0 024 maximum 1 ppm C typical 100 HV typical 500 UV maximum 1 5 pV C typical 0 002 typical 0 024 maximum TI REF3240 0 01 typical 0 2 maximum Output Voltage Temperature Drift 4 ppm C typical Thermal Hysteresis A D Resolution Data Format No Missing Codes 7 ppm C maximum 100 ppm first cycle 25 ppm additional cycles 78 UV RMS typical ADI AD7686 16 bits str
19. XM A75 User s Manual Multifunction I O Mezzanine Board TERMINATION PANEL MODEL 5025 288 Type Termination Panel for 68 Pin SCSI 3 Cable Connection Application To connect field I O signals to the board Termination Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged 31 AXM A75 User s Manual Multifunction I O Mezzanine Board DRAWINGS GROUND SHIELD ON CABLE CONNECTS TO P1 amp P2 SHIELDED BACKSHELL P1 DI 2 METERS gt po 78 72 INCHES 4 0 0 0 INCHES P1 TOP VIEW
20. aight binary no missing codes 15 bits A D Integral Linearity Error 0 6 LSB typical 2 LSB maximum Offset Error iatialonsne lana 0 1 mV typical 10 V range 1 6 mV maximum Gain Error Temperature Drift 0 3 ppm C typical Offset Temperature Drift 0 3 ppm C typical Full Scale Error 0 5 maximum A D Conversion Time Conversion Rate Input Noise 2 uS maximum 500 kHz maximum 2 LSB rms typical 3 Software calibration eliminates these error components 4 Acromag does not temperature cycle this product before shipping to customers If the product is operated at the extremes of its temperature range the voltage reference could drift by the amount specified for first cycle 28 AXM A75 User s Manual ANALOG OUTPUTS Digital to Analog Converter Device siste Resolution aaa aaaaaaaaaaaaa Output Ranges Settling Time ii Slew Rate Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Internal Reference Short Circuit Current Load CUFrent i Capacitive Load Stability DC Output Impedance Gain AA Bipolar Zero Drift ACCUIACY escoria ani Multifunction I O Mezzanine Board ADI AD5764RB 16 bits 10 10 2564 and 10
21. dresses shown to properly access the board registers Register accesses as 32 16 and 8 bits in memory space are permitted unless otherwise indicated A detailed description of each of the registers follows after Table 3 1 Table 3 1 Memory Map PCIBar2 PCIBar2 Hex D16 D15 Hex sj WE for base PMC XMC 0000 y sd 7FFC ae Reserved for base PMC XMC Module 8004 4 Da 80FC 8103 8100 AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 PCIBar2 Status Register 0 sio StatusRegisteri ator Digitalyo 8113 Conversionfimer 8410 8117 FLASH 8114 data 8118 Digital I O Direction 8118 811F unused 811C y y 81FF 81FC ADCidata 8200 8207 ADCigaincorrecti n 8204 8208 ADCIOffset 8208 820C 813 ADC2data 8210 8217 8214 8218 ADCZoffset 8218 821F 821C ADC3data 8227 1ADC3gaincorrecioo 8224 8228 ADC3offset 8228 822C ADC4data 8237 8238 ADC4offset 8238 823C __ ADCSdata 8240 8247 8244 8248 ADCSoffset 8248 824C ADC6data 8257 ADC6gaincorrection 8254 8258 ADC6offset 8258 825C ADC7data 8260 8267 8264 8268 ADC7offset 8268 826C 8273 ADC8data 8270 8277 8274 8278 ADc8offsee 8278 827F 827C 8283 ADC9data 8280 8287 8284 8288 ADC9offset 8288 828F 828C aDctodata 8290 10 AXM A75 User s Manual Multifunction I O Mezzanine Board PCIBar2 PCIBar2
22. es Dir of Sales rnieves acromag com 248 295 0838 248 624 9234 and Marketing Revision History Release Date EGR DOC Description of Revision 19 FEB 13 JCL Initial Acromag release 29 JUL 14 JCL Added Certificate of Volatility and exception note to conversion timer section 8 JAN 15 Added support for XMC 7KxxxAX modules 29 MAY 15 Added support for XMC 7A200 04 JUNE 15 Added note about IEEE 1386 non compliance on page 4 and 26 Update Acromag Representative in Certificate of Volatility 33
23. esseeesseeeessecesseeceseeecsaeeessseceseees 16 Status Register 1 Read Write PCIBar2 8108H in 16 Digital I O Read Write PCIBar2 810CH a aaa aaa anawa aaa aaa aaa nono nonnnnonnnnncnnanonns 16 Conversion Timer Register Read Write PCIBar2 8110H eee aaa aaa aaa aaa anaaaaanaa zacina 16 FLASH Data Register Read Write PCIBar2 8114H ooo aaa aaa aaa aaa aaa aazaazwiii awa 17 Digital I O Direction Register Read Write PCIBar2 8118H aaa aaa anna aa naaaaaaiica 17 ADC Channels ita doo A calc vt ta ed haa avec ace OE ni W EEE 17 ADC Data FORM at zs O A A qc caian cancussasibadevseatscuyougpadess edusse eattedesusstesdsesizedes 18 ADE Offset Register crire eneee e Lina nie naacal 18 ADC Gaih Register iaia A ose eines ss 18 Uncalibrated ADC Performance 19 Analog Input Channel Calibration Procedure ui 19 BAGCCha nelsi suszy A A ai 20 DAC Data Register wie iii awa a ai 20 DAC Coarse Gain Register 21 DAG Fihe Gaih Register ua E l A a of ld ad 21 DAC Offset Register za dazu kia dees das ate atc deve Wait lalla lalla esa 22 Updating DAG0UthUtSuiz ai eel Ge Sic W A WO OWA EA W 22 THEORY OF OPERATION ccie moniteur EE A E A ASA 22 Field OCA alal La 22 AXM A75 User s Manual Multifunction I O Mezzanine Board 5 0 6 0 7 0 8 0 Digital Oss P St Pe TNA ARR Re 23 Analog Outputs nsoni lilla 24 Analog inpu
24. gital inputs outputs High Speed Analog Input sixteen independent 16 bit Analog to Digital Converter ADC channels provide simultaneous sampling at a maximum rate of 500 KHz The digitized output of each ADC is simultaneously input to the Field Programmable Gate Array FPGA for data collection and processing Programmable Input Voltage Range four gain selections are available that allow a bipolar input voltage range from 1 28 Volts to 10 24 Volts Analog Output eight 16 bit Digital to Analog Converter DAC channels provide simultaneous update with a maximum rate of 100 KHz Programmable Output Voltage Range three gain selections are available that allow a bipolar output voltage range from 10 Volts to 10 5263 Volts Calibration Constants factory calibration constants used to correct gain and offset errors are stored in on board FLASH memory Correction constants are stored for each channel and gain selection combination Gain and offset correction are supported for both analog input and analog output General Purpose Digital Input or Output sixteen general purpose I O signals are provided The outputs are pulled high via pull up resistors Example Design the example VHDL design provided in the base board EDK provides the following features e Control of ADC sample rate and gain selection e Gain and offset error correction is applied in FPGA hardware for analog inputs and on chip for analog outputs
25. ly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed PMC or AXM A75 User s Manual Multifunction I O Mezzanine Board XMC modules plus the AXM A75 within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The lack of air circulation within the computer chassis is a cause for some concern Most if not all computer chassis do not provide a fan for cooling of
26. nformation contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility WARNING The AXM A75 length dimension exceeds the CMC I O envelope as shown in IEEE 1386 2001 Figure 4 1 and Figure 4 2 by 7 5mm limited to 31mm and is not compatible with all PMC XMC carriers The AXM A75 when plugged into a compatible Acromag PMC XMC module will work in most air cooled Acromag non processor carriers including the AcPC46xx APC PMC APCe867x amp VPX482x models It is not compatible with the VPX481x series or any Acromag processor board that has a PMC XMC slot Contact the factory with any questions AXM A75 User s Manual Multifunction I O Mezzanine Board 1 0 GENERAL INFORMATION KEY FEATURES The AXM A75 is a high speed analog input output mezzanine board compatible with Acromag s line of re configurable PMC and XMC FPGA modules The AXM A75 has 16 differential analog inputs 8 analog outputs and 16 di
27. repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in section 2 0 PREPARATION FOR USE have been followed Replacement of a suspected faulty unit with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e Application Notes e Frequently Asked Questions FAQ s e Product Knowledge Base e Tutorials e Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab 25 AXM A75 User s Manual Multifunction I O Mezzanine Board Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 295 0310 Fax 248 624 9234 Email solutions acromag com 6 0 SPECIFICATIO
28. rrect offset errors There is a separate offset register for each channel The gain register is a 17 bit fixed point positive fractional number ranging from 0 to 1 999984 weighted as shown in Table 3 13 The 17 bit fixed point number is least significant bit justified in a 32 bit register This number is multiplied by the offset corrected ADC value 18 AXM A75 User s Manual Multifunction I O Mezzanine Board to correct for gain errors There is a separate gain register for each channel Table 3 13 Gain Register Number Format JE 1 65536 1 131072 BIT 16 15 14 13 1 12 11 10 7 Uncalibrated ADC Performance The uncalibrated analog input channel performance is affected by four error sources These are the instrumentation amplifier difference amplifier ADC reference and the ADC Each of these devices can contribute to the offset and gain error of the system These errors can be corrected by calibration Analog Input Channel Calibration Procedure Accurate calibration of the analog input channel digitized values can be accomplished by applying external precision calibration voltages The calibration voltages are used to find two points that determine the straight line characteristic of the analog channel Factory calibration constants are calculated using the following equations Gain 1 2 40r 8 20 48 Gain 10 24 IdealZero Gain 216 FullScaleRange IdealSlope FullScaleRange 19
29. t 2 uS ADC Clock Period This register must be written using a 32 bit write command The minimum sample period is 2 uS The maximum sample period is 2 1 ADC Clock Period The ADC Clock Period for the various models is shown Table 3 8 exception XMC SLX 150 1M clock period in 20 ns which results in a maximum sample rate of 420 KHz 16 AXM A75 User s Manual Multifunction I O Mezzanine Board Table 3 8 ADC Clock Period Module Clock Period PMC LXxxx 10 101 n PMC XMC SLXxxx PMC XMC VxXxxx XMC SLX 150 1M XMC 7A200 XMC 7KxxxAX Table 3 9 Conversion Timer 8110H FUNCTION 31 0 Sample Period register value ADC Clock Period FLASH Data Register Read Write PCIBar2 8114H A byte write to this address triggers a write read serial transfer to from the serial FLASH device A byte read from this address returns the data read from a previous write read serial transfer WARNING Factory calibration data is stored in FLASH Writing to FLASH could result in loss of factory calibration data SeeError Reference source not found Table 3 10 FLASH Data Register 8114H FUNCTION IT 31 8 FLASH data Digital I O Direction Register Read Write PCIBar2 8118H ADC Channels The Digital I O Direction provides an output enable for each of the 16 digital I O lines Write a 1 to a bit to enable the output Table 3 11 Digital I O 8118CH FUNCTION 31 16 15 0 Digital I O Direction 1
30. t SCL FPGA P1 _ A D A2D_DATA16 AOUT1 AOUT2 16bit _AOUTA D A lt D2A_DATA1 gt AOUT5 AOUT6 16 bit AOUT7 Quad AOUT8 D A 4 D2A_DATA2 gt Figure 1 AXM A75 Block Diagram Digital I O A block diagram of a single digital I O channel is shown in Figure 2 Digital I O This structure is replicated 16 times on the AXM A75 The signal DIG_OUT_STROBE is activated upon a write to the Digital I O register The level of DIG_IO_n is returned upon a read of the Digital I O register The signal DIG_OUT_DIR_STROBE is activated upon a write to the Digital I O Direction Register When the DIG_OUT_DIR_n signal is logic high the contents of the DIG_OUT_n flip flop will be 23 AXM A75 User s Manual DB_OUT n DIG_OUT_STROBE CLK_125MHZ DB_OUT n DIG_OUT_DIR_STROBE Analog Outputs Analog Inputs Multifunction I O Mezzanine Board driven onto the DIG_IO_n signal The level translator is a NXP GTL2010 FPGA on XMC PMC Bi 4 75K DIG_OUT_n directional DIG_IO_n Leve Translator DIG_OUT_DIR_n Figure 2 Digital I O Two Analog Devices AD5764R quad bipolar voltage output DACs are used to provide the eight analog output channels Each DAC uses its own on chip reference as its reference source Although each DAC has separate clock sync load and serial I O signals connected to the FPGA the firmware as delivered with the EDK provides access to only a single quad DAC at a time The CLR BIN2SCOMP and
31. tsp 0 ilaele abili 24 SERVICE AND REPAIR la e Ri 25 SERVICE AND REPAIR ASSISTANCE i 25 PRELIMINARY SERVICE PROCEDURE ccoo nono aaa nn nn rana cnn cnn cnn 25 WHERE TOGET HELP 000 dit AGA AAA AA A A 25 SPECIFICATIONS viii ROSA 26 Physical sicuresaf ADELE IG LE ARL LIL LI LR eed lech caps seed O ESANS 26 CONNECIOWS ae A AAA A eet AA 26 ENVIO Metalica A A ne 26 Power REQUIREMENTS cit e Len heed A e lieta de ea 27 ANALOG INPUT ivan as 27 Programmable Gain Instrumentation Amplifier i 27 Difference Amplifier szc iena ari 28 Voltage Reference REF3240 i 28 Analogito DigitalConverteri iia rare o andai co rear 28 ANALOG OUTPUTS 0 A RARE O A 29 Digital to Analog Converter i 29 APRENDO Diada aaa a 30 CABLE MODEL 5028 420 Ultra SCSI VHDCI male to SCSI 3 male Round Shielded 30 TERMINATION PANEL MODEL 5025 288 corona aaa aaa aaa aaa crnn cnn 31 DRAWINGS ae AA A E eiii 32 AXM A75 User s Manual Multifunction I O Mezzanine Board The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the i
32. us bits for each channel Table 3 5 Status Register 0 8104H BIT FUNCTION FIFO overflow interrupt pending clear channel 16 1 A 1 indicates that at least one A D sample was lost due to an attempted write to a full FIFO Write a 1 to clear the bit FIFO half full interrupt pending channel 16 1 A 1 indicates that there are at least 1024 samples in the FIFO Status Register 1 Read Write PCIBar2 8108H Status Register 1 provides access to the FIFO empty status bits for each channel Table 3 6 Status Register 1 8108H BIT FUNCTION 31 16 15 0 FIFO empty channel 16 1 A 1 indicates that the FIFO is empty Digital I O Read Write PCIBar2 810CH The Digital I O register provides access to the 16 digital I O lines Digital I O lines are pulled high via a 4 75K Ohm resistor to 5 Volts The levels of the digital I O lines are returned upon a read to this address The appropriate output enable bit must be 1 in the Digital I O Direction register to enable writing to a digital output Table 3 7 Digital I O 810CH BIT FUNCTION 31 16 Digital I O signals 15 0 Conversion Timer Register Read Write PCIBar2 8110H This read write register controls the sample period of all A D converters Sample period count ADC Clock Period Set count to zero to allow A D converters to sample at their maximum rate of 500 KHz For sample rates less than 500 KHz enter a count g
Download Pdf Manuals
Related Search