EVBUM2056 - Evaluation Board User`s Manual for High
Contents
1. ile nai MC10ELT28D MC100ELT28D Yes Yes Yes Yes Yes No Yes No www BD PIE com ON ECLSOIC8EVB LAB SETUP Power Supply Voc GND OUT1 Test Measuring Equipment OUTI Channel 1 Differential Signal Generator OUT2 Channel 2 OUT2 TRIGGER RR Td Td TRIGGER VEE GND Power Supply Figure 15 Example of Standard Lab Setup Configuration 1 1 Connect appropriate power supplies to Vcc VEE and GND For standard ECL lab setup and test a split dual power supply is required enabling the 50 Q internal impedance in the oscilloscope to be used as a termination of the ECL signals Vrr Vcc 2 0 V in split power supply setup Vrr is the system ground Vcc is 2 0 V and Vee is 3 0 V or 1 3 V see Table 15 Table 15 Power Supply Levels roes Vee Ve SNO The power supply for voltage level translating device need slight modification as indicated in Table 16 Table 16 Power Supply Levels for Translators 2 Connect a signal generator to the input SMA connectors Setup input signal according to the device data sheet 3 Connect a test measurement device on the device output SMA connectors NOTE The test measurement device must contain 50 Q termination www BD Tt tom ON ECLSOIC8EVB Table 17 Bill of Materials SMA Connector Rosenberger SMA Connector Side 32K22. Pin 1 Pin 8 Pin 2 Pin 7 R7 DUT 502 optional Pin 3 Pin 6 R6 50 Q optional J6 Pin 4 Pin 5 Vee GND Figure 11 Configuration 8 Translator Schematic Table 11 Configuration 8 e ii 157 MC10ELT22D MC100EL22D MC100LVELT22D Yes Yes No Yes No Yes No No Yes Optional Yes Optional Yes Yes MC100EPT22D www BD PIE com ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 8 Pin 6 Pin 4 Pin 5 Vee GND Figure 12 Configuration 9 Translator Schematic Unloaded Testing Condition Table 12 Configuration 9 KREEG ECO EREN CIC CI EN LS CI es EA CAE RES MC100EL23D MC100LVELT23D Yes Yes Yes Yes Yes xes Yes Yes No No Yes No Yes Yes Yes MC100EPT23D See Appendix for loaded testing condition www BD PIE com ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 8 Pin 6 Pin 4 Pin 5 Vee GND Figure 13 Configuration 10 Translator Schematic Unloaded Testing Condition Table 13 Configuration 10 MC10ELT26D MC100ELT26D No No Yes Yes Yes Yes No No No No Yes Yes ves No Yes Yes MC100EPT26D See Appendix for loaded testing condition www BD ft tom ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 8 Pin 6 optional J6 Pin 4 Pin 5 Vee GND Figure 14 Configuration 11 Translator Schematic Table 14 Configuration 11
3. MC100LVEL32D MC100LVEL33D MC10EP32D MC100EP32D MC10EP33D MC100EP33D Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No Yes www BD PIE com ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 3 Pin 6 Pin 4 Pin 5 J4 Optional Figure 8 Configuration 5 Schematic Table 8 Configuration 5 eet enz Pms eme Pns eme Pn Pme ENNE re oe re oe ue oe os ae ue EA mr os or MC10EL58D MC100EL58D No MC100LVEL58D MC10EP58D MC100EP58D See Appendix for addition or modification to the current configuration No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes www BD ft tom ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT A I optional J7 Pin 8 Pin 6 Pin 4 Pin 5 Vee GND Figure 9 Configuration 6 Translator Schematic Table 9 Configuration 6 e ae MC10ELT20D MC100EL20D No Yes Yes No No No No No Yes Optional Yes Yes MC10EPT20D MC100EPT20D www BD PIE com ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 8 Pin 6 Pin 4 Pin 5 Vee GND Figure 10 Configuration 7 Translator Schematic Unloaded Testing Condition Table 10 Configuration 7 MC10ELT21D MC100EL21D No No Yes Yes Yes Yes No No No No Yes N Ye Ye MC100EPT21D E hei See Appendix for loaded testing condition www BD Tt tom ON ECLSOIC8EVB Vec GND
4. add up to 500 Q loaded condition www BD TIt com ON ECLSOIC8EVB Appendix B Gerber Files sm 4 SOIC8 EVAL BOARD 26 MAR 2002 R04003 8 MIL ne H 19 19 pag sae GITA AD ER LO Gra ag CIMA vaan 4 aa SI Third Layer Vcc and Ground Plane Bottom Layer Figure 16 Gerber Files www BD Ft vom ON ECLSOIC8EVB ECLinPS ECLinPS Lite ECLinPS Plus and ECLinPS MAX are trademarks of Semiconductor Components Industries LLC SCILLC ON Semiconductor and O are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as componen
5. 100EP16DT This device has an option of being 50 Q terminated internally To evaluate the internal SO Q resistor of the device Configuration 2 needs to be modified 1 Remove the 50 82 chip resistors from R2 and R3 2 Short R1 and R4 to Vrr GND Option A Short R1 and R4 to Vrr GND Or Option B Place SMA connectors on J1 and J4 Place shorting barrels on J1 and J4 SMA connector MC100EP16VBD This device has an option of single ended feedback output and being driven single endedly using the Vpp To utilize the feedback option and drive it single endedly Configuration 2 needs to be modified Feedback option 1 Connect a SMA connector on J1 Drive single endedly 2 Remove the 50 Q chip resistor from R3 3 Short pin 3 and pin 4 together Option A Short R3 and R4 Or Option B Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors MC100EP16VCD This device has an option of single ended feedback output with an enable pin To utilize the feedback option and enable option Configuration 5 needs to be modified 1 Connect a SMA connector on J1 2 Remove the 50 Q chip resistor from R3 MC100EP16VSD This device has an option of varying the output swing amplitude and being driven single endedly In order to utilize these options Configuration 2 needs to be modified Output Swing Control 1 Connect a SMA connector on J1 2 Add a decoupling capacitor between J1 and Vcc 0 01 uF Drive Sin
6. 43 40ME3 http www rosenberger de Launch Gold Plated http www rosenbergerna com Johnson SMA Connector Side 142 0701 851 http www johnsoncomponents com Components Launch Gold Plated Surface Mount Test Keystone SMT Miniature Test Point 5015 http www keyelco com Points SMT Compact Test Point 5016 Thru Hole Mount 5005 5009 Compact Test Point Chip Capacitor AVC Corporation 0603 0 01 uF 10 06035C103KAT2A http www avxcorp com 0603 0 1 uF 10 06035C104KAT2A Chip Resistor Vishay Dale 0603 50 Q 1 Thick CRCW060351R1J http www vishay com Film Resistor Evaluation Board ON Semiconductor SOIC 8 Evaluation Board ECLSOIC8EVB http www onsemi com Device Samples ON Semiconductor SOIC 8 Package Device http www onsemi com Components are available through most distributors i e www newark com www digikey com www BD PIE com ON ECLSOIC8EVB Appendix A Modified Configurations MC10EL16D MC100EL16D MC100LVEL16D MC10EP16D MC100EP16D MC10EP16DF MC100EP16DF MC100EP16VAD MC100LVEP16D The devices listed above have the option of being driven single endedly by using the provided Vgg pin of the device In order to drive it single endedly Configuration 2 needs to be modified 1 Remove the 50 82 chip resistor from R3 2 Short pin 3 and pin 4 together Option A Short R3 and R4 trace pads Or Option B Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors MC10EP16D MC
7. ECLSOICSEVB Evaluation Board User s Manual for High Frequency SOIC 8 INTRODUCTION ON Semiconductor has developed an evaluation board for the devices in 8 lead SOIC package These evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 8 lead SOIC device samples The board provides a high bandwidth 50 Q controlled impedance environment The pictures in Figure 1 show the top and bottom view of the evaluation board which can be configured in several different ways depending on device under test See Table 1 Configuration List This evaluation board manual contains e Information on 8 lead SOIC Evaluation Board e Assembly Instructions e Appropriate Lab Setup e Bill of Materials This manual should be used in conjunction with the device data sheet which contains full technical details on the device specifications and operation ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL Board Lay Up The 8 lead SOIC evaluation board is implemented in four layers with split dual power supplies Figure 2 Evaluation Board Lay up For standard ECL lab setup and test a split dual power supply is essential to enable the 50 Q internal impedance in the oscilloscope as a termination for ECL devices The first layer or primary trace layer is 0 008 thick Rogers RO4003 material which is designed to have equal elec
8. al information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative www BDTIC com ON
9. and C3 and C4 are 0 1 uF SOIC8 EVAL Shen 26 MAR 2002 RO4003 8 MIL Top View Bottom View Figure 3 Evaluation Board Layout www BD TIt com ON ECLSOIC8EVB Table 1 Configuration List pedi commenta Configuration E MC10ELT20D See Figure 9 MC100ELT20D MC10ELT21D See Figure 10 MC100ELT21D MC10ELT22D See Figure 11 MC100ELT22D MC100ELT23D See Figure 12 MC10ELT26D See Figure 13 MC100ELT26D MC10ELT28D See Figure 14 MC100ELT28D NC a ereas Ia MC100EP16D MC100EP16TD MC10EP52D MC100EP52D MC10EP58D MC100EP58D MC100EP89D MC10EPT20D See Figure 9 MES MC100EPT21D MC100EPT22D MC100EPT23D MC100EPT26D MC100EPT20D Low Voltage ECLinPS Plus Configuration See Appendix for additions or modifications to the current configuration ECLinPS MAX Device MC100LVEP11D MC100LVEP16D NB6L11D See Figure 6 NB6L16D See Figure 5 www BD ft tom ON ECLSOIC8EVB Evaluation Board Assembly Instructions The 8 lead SOIC evaluation board is designed for characterizing devices in a 50 Q laboratory environment using high bandwidth equipment Each signal trace on the board has a via which has an option of termination resistor or bypassing capacitor depending on the input output configuration see Table 1 Configuration List Table 17 contains the Bill of Materials for this evaluation board Solder the Device on the Evaluation Board The soldering can be accomplished by
10. citors can improve edge rates reduce overshoot and undershoot Termination All ECL outputs need to be terminated to Vrr Vrr Vcc 2 0 V GND via a 50 Q resistor in a split power supply lab set up 0603 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver More information on termination is provided in AN8020 Solder the chip resistors to the bottom side of the board on the appropriate input of the device pins labeled R1 R2 R3 R4 R6 and R7 depending on the specific device Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given configuration Each input and output requires one SMA connector Attach all the required SMA connectors onto the board and solder the connectors to the board Please note that alignment of the signal connector pin of the SMA can influence the lab results The reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the SMA connector Validating the Assembled Board After assembling the evaluation board it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process Time Domain Reflectometry TDR is another highly recommended validation test www BD TIt com ON ECLSOIC8EVB CONFIGURATIONS Vec GND Table 4 Configuration 1 Cent Tere Tema Device si rr me pre pe p
11. e fe re oe os es EES EE WCE Moreno WCE EES ES WCE Nemo NE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Nos EEES RSE __ MC10EP08D MC100EP08D MC10EP31D MC100EP31D MC10EP35D MC100EP35D MC10EP51D MC100EP51D MC10EP52D MC100EP52D www BD PIE com ON ECLSOIC8EVB Vcc GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 3 Pin 6 Pin 4 Pin 5 Table 5 TU 2 No Yes Yes Yes Yes No Yes Yes Yes No Yes Yes Yes MC10EP16D MC100EP16D MC100LVEP160 MC10EP16TD MC100EP16TD MC100EP16VAD MC100EP16VBD MC100EP16VSD MC100EP16VTD NB6L160D See Appendix for additional or modification to the current configuration www BD PIE com ON ECLSOIC8EVB Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 3 Pin 6 Pin 4 Pin 5 Figure 6 Configuration 3 Schematic Table 6 Configuration 3 i dt EEN EEEN EEEN i CIC E LH c or CA GRES MC10EL11D MC100EL11D MC10EL12D MC100EL12D MC10EL89D MC100EL89D MC100LVEL11D MC100LVEL12D Yes No Yes No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes Yes MC10EP11D MC100EP11D MC100EP89D MC100LVEP11D NB6L11D www BD PTIE com ON ECLSOIC8EVB Vec GND Pin 1 Pin 8 Pin 2 Pin 7 DUT Pin 3 Pin 6 Pin 4 Pin 5 J4 Optional Figure 7 Configuration 4 Schematic Table 7 Configuration 4 BOL ES LS EIS ELE o CI mirra MC10EL32D MC100EL32D MC10EL33D MC100EL33D
12. gle Endedly 1 Remove the 50 Q chip resistor from R3 2 Short pin 3 and pin 4 together Option A Short R3 and R4 Or Option B Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors MC100EP16VTD This device has an option of varying the output swing amplitude and internal termination In order to utilize these options Configuration 2 needs to be modified Output Swing Control 1 Connect a SMA connector on J1 2 Add a decoupling capacitor between J1 and Vcc 0 0 1 uF Internal Termination 1 Remove the 50 chip resistors from R2 and R3 2 Short R1 and R4 to Vrr GND Option A Short R1 and R4 to Vrr GND Or Option B Place SMA connectors on J1 and J4 Place shorting barrels on J1 and J4 SMA connector MC10ELT21D MC100EL21D MC100EL23D MC10ELT26D MC100ELT26D MC100EPT21D MC100EPT23D MC100EPT26D MC100LVELT23 The TTL output data presented in the data sheet are obtained under 500 load resistor in parallel with 20 pF fixture capacitance In order to obtain comparable data as in the data sheet the evaluation board needs to be modified 1 Cut the output trace so that the 0402 size chip resistor can be placed over the cut out trace 2 Solder a 450 Q chip resistor across the cut out trace Any size chip resistor can be used The recommended size of the chip resistor is 0402 to reduce the effect of parasitic with a 17 mil trace width 450 Q in series with 50 Q instrument resistance
13. hand soldering or soldering re flow techniques Make sure pin 1 of the device is located next the white dotted mark U1 and all the pins are aligned to the footprint pads Solder the 8 lead SOIC device to the evaluation board Connecting Power and Ground Planes For standard ECL lab setup and test a split dual power supply is required enabling the 50 Q internal impedance in the oscilloscope to be used as a termination of the ECL signals Vrr Vcc 2 0 V in split power supply setup Vrr is the system ground Vcc is 2 0 V and Ver is 3 0 V or 1 3 V see Table 2 Power Supply Levels Table 2 Power Supply Levels The power supply for voltage level translating device need slight modification as indicated in Table 3 Power Supply Levels for Translators Table 3 Power Supply Levels for Translators PECL Translators 3 3V 5 0V 0 0V On the top side of the evaluation board solder the four surface mount test point clips to the pads labeled Vcc Ver and GND The Vcc clip connects directly to pin 8 of the device The Vee clip connects directly to pin 5 of the device There are two GND clip footprints which can be connected to the ground plane of the evaluation board depending on the setup configuration It is recommended to solder 0 01 uF capacitors to C1 and C2 to reduce the unwanted noise from the power supplies C3 and C4 pads are provided for 0 1 uF capacitor to further diminish the noise from the power supplies Adding capa
14. trical length on all signal traces from the device under the test DUT to the sense output The second layer is the 1 0 oz copper ground plane and a portion of the plane is the Veg power plane The FR4 dielectric material is placed between second and third layer and between third and fourth layer The third layer is also 1 0 oz copper ground plane and a portion of this layer is Vcc power plane The fourth layer is the secondary trace layer Figure 1 Top and Bottom View of the 8 lead SOIC Evaluation Board Semiconductor Compon 1 1 bWcation Order Number January 2012 RN WW e e com EVBUM2056 D ECLSOIC8EVB LAY UP DETAIL 4 LAYER SILKSCREEN TOP SIDE LZ ROGERS 4003 0 008 n 1 LAYER 2 GROUND AND VEE PLANE P1 1 OZ 77 An 777 777 Fraoosm 777 Figure 2 Evaluation Board Lay up LAYER 1 TOP SIDE 0 007 Board Layout devices and the relevant configuration that utilizes this PCB The 8 lead SOIC evaluation board was designed to be board List of components and simple schematics are located versatile and accommodate several different configurations in Figures 4 through 14 Place SMA connectors on J1 The input output and power pin layout of the evaluation through J7 50 chip resistors on R1 through R7 and chip board is shown in Figure 3 The evaluation board has at least capacitors C1 through C4 according to configuration eleven possible configurable options Table 1 list the figures C1 and C2 are 0 01 uF
15. ts in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 An Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For addition
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