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UM : uPD780228 Subseries

1. nnne nnne nennen nnn nnn 153 12 4 1 Non maskable interrupt request acknowledge operation 153 12 4 2 Maskable interrupt request acknowledge operation 12 4 3 Software interrupt request acknowledge operation 12 4 4 Mu ltipl interrUpt Servicing o ccrte ties nie tein eer nde irren 12 4 5 Interrupt request reserve eat ne i dca ects CHAPTER 13 STANDBY 022222050 163 13 1 Standby Function and Configuration 1 1 163 13 14 Standby function eee terr qi ette Me Fei 163 13 1 2 Standby function control register 2 164 13 2 Standby Function Operations 13 241 HAETZmOQO cuire Hehe to a Pr e 19 2 2 STOP Image neret eer etate ie PE Gre Pine e Po shan a E Fear RUP CHAPTER 14 RESET FUNCTION 55 IIIa dene crac eaae nasa rests cac nis 171 14 1 Reset FUNCTION 171 CHAPTER 15 uPD78F02268 u uuu 175 15 1 Memory Size Select Register U 176 15 2 Internal Expansion RAM Size Select Register u u uuu u 177 15 3 Flash Memory
2. viii LIST OF TABLES 1 2 Table No Title Page 1 1 Mask Options of Mask ROM Models 0 8 2 1 Each Pin arenes eio ee ete n DEL EG eee bl e 16 3 1 Internal ROM Capacity uuu suu usunku te deir eeu nr 22 3 2 Vector Table e E e n Ea aet 22 3 3 Special Function Registers u need e eee ei aet 33 4 1 Ort FUNCHOM ee 50 4 2 Port Configuration s ciere mete niis iuri een Ie iE IHE 51 4 3 Port Mode Register and Output Latch Setting when Alternate Function is Used 63 4 4 Comparison between Mask Options of Mask ROM Models and uPD78F0228 67 5 1 Glock Generator Config ration i iere eee pe e need deri p dene 69 5 2 Relation between CPU Clock and Minimum Instruction Execution Time 70 5 8 Maximum Time Required for Changing CPU 75 6 1 8 Bit Remote Control Timer enne 77 7 1 Configuration of 8 Bit PWM Timers urere te te i ein deed e d dnce sede dies 84 8 1 Hang up Detection Time of Watchdog Timer sss eene nnns 101 8 2 Interval Tire aa tei LO Ide cct cT I cU NL CD A 101 8 3 Configuration of Watchdog nennen nnne nennen 102
3. 12 15 Interrupt Request Reserve 13 1 Oscillation Stabilization Time Select Register 13 2 HALT Mode Clear upon Interrupt Request Generation P 13 3 HALT Mode Release by RESET Input 13 4 STOP Mode Release by Interrupt Request Generation sss 13 5 Release by STOP Mode RESET Input 14 1 Block Diagram of Reset 171 14 2 Timing of Reset Input by RESET Input 172 14 3 Timing of Reset due to Watchdog Timer 172 14 4 Timing of Reset in STOP Mode by RESET 1 22 172 15 1 Memory Size Select Register 172 15 2 Internal Expansion RAM Size Select Register 0 0 177 15 8 Communication Mode Select Format 178 15 4 Connection of Flashpro Il in 3 Wire Serial l O 180 15 5 Connection of Flashpro II in Pseudo 3 Wire Serial Mode e 180 B 1 Development 100185 ete espera cedente dede edet cca B 2 NQPACK100RB Target Connected Side Package Drawings Refernce B 3 HQPACK100RB Lid for Device Mounted Package Drawings Reference 15 4 YQPACK100RB Probe Side Package Drawings
4. HL bit CY HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 188 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Operation Group CY saddr bit CY lt CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY lt CY sfr bit CY c CY Abit CY lt CY PSW bit CY c CY HL bit CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY saddr bit CY sfr bit CY A bit CY lt CY v saddr bit CY lt CY v sfr bit CY c CY v Abit CY lt CY v PSW bit CY lt CY v HL bit CY lt CY saddr bit CY lt CY sfr bit CY c CY vA bit CY lt CY v PSW bit CY lt CY v HL bit saddr bit 1 Bit CY PSW bit manipulation CY HL bit saddr bit sfr bit A bi PSW bit sfr bit lt 1 A bit 1 PSW bit 1 HL bit lt 1 saddr bit 0 sfr bit 0 A bit 0 PSW bit 0 HL bit 0 CY 1 CY 0 mimj nmi icj nmj rnj rnmj rnmj cj nmijnmj coi inmij cjcoj nmi cij nmiceij jco j jnmi ico nmij coj co CY CY Notes 1 When the internal high speed R
5. t I TTMBn de e qp F 4i NN DEC NR NE 4 Inactive level Inactive level n 0or1 iii When CR5n FFH JUUL IUUUUL JUUL TITUL TM5n Z EEE NaNe FEE LOT A Tu HI CR5n FFH U bc L lt d ___ I INTTMSn __ LU u k nQ s euni NN TlO5n 1 i m Inactive level Active level Active level Inactive level Inactive level n Oor1 95 CHAPTER 7 8 BIT PWM TIMERS b Operation when CR5n is changed Figure 7 7 Operation Timing When CR5n Is Changed i If CR5n value is changed from N to M before overflow of TM5n Count e Mu UU UU UU TM5n 212 ot oes CR5n N TCE5n H i INTTM5n i 1 TIOSn 1 i CR5n changed M 0 1 ii If CR5n value is changed from to M after overflow of TM5n Count Dur ee E ee ee TM5n OT N ae i I i CR5n N _ 4 M 5 i i I J i INTTM5n I I i 5 po I L CR5n changed N M 0 1 iii If CR5n value is changed from to for duration of 2 clocks 00H and 01H immediately after overflow of TM5n Count e TEE DEED IEEE Tet 2 aa e X N o a TCE5n
6. AVss Ground potential for A D converter Same potential as Vss1 Positive power supply to ports Vop1 Positive power supply except ports analog block and FIP controller driver Vpp2 Positive power supply to FIP controller driver Vsso Ground potential for ports Vss Ground potential except ports and analog block V ppNote High voltage is applied to this pin when program is written verified In the normal operation mode directly connect this pin to Vss IC Internally connected Directly connect this pin to Vss Note VPP is provided to the uPD78F0228 only 11 CHAPTER 2 PIN FUNCTIONS 2 2 Pin Functions 2 2 1 POO and P01 Port 0 and P01 are used as a 2 bit I O port These pins also have external interrupt request input functions in addition to the I O port function Port 0 can be set in the following operation modes in 1 bit units 1 Port mode and P01 function as a 2 bit I O port in this mode This 2 bit port can be set in the input or output mode in 1 bit units by the port mode register 0 When used as an input port the internal pull up resistor can be connected by using the pull up resistor option register 0 PUO 2 Control mode POO and P01 functions as external interrupt request input pins INTPO and INTPO and input external interrupt requests whose valid edge can be specified t
7. c 10 431 Operation stop MOd6 nena eee ee 10 4 2 Three wire serial mode CHAPTER 11 FIP CONTROLLER DRIVER U uuu uuu 127 11 1 Function of FIP Controller Driver wee 127 11 2 Configuration of FIP Controller Driver 128 11 3 Registers Controlling FIP Controller Driver 129 Gontrol TegiSterS urhe eere e e Lc LC cero 129 11 3 2 One display period and blanking width sss 133 11 4 Display Data senes 134 11 5 Key Scan Flag and Key Scan Data a ennt nnne 135 11 521 K y scan flag eee RR RUD RERUM i 135 11 5 24 Key scan data x etiem hoe dee be n t ode det RE E asua qas ata 135 11 6 Leakage Emission of Fluorescent Indicator Panel 136 11 7 Calculation of Total Power Dissipation eese u uu uu u u uu uuu 139 12 INTERRUPT FUNCTIONS eae tuere 143 12 1 Interrupt Function IIS 143 12 2 Interrupt Sources and Configuration u u u uuu uuu T 145 12 3 Interrupt Function Control Registers U uuu uuu nnn 148 12 4 Interrupt Servicing
8. Contro 100 pin uPD78075B uPDT8075BY EMI noise reduced version of 78078 100 pin A timer was added to the uPD78054 and external interface was enhanced 100 pin z ROM less version of the 78078 100 pin uPD78001 gir uPD780018Y 7 Serial I O of the PD78078 was enhanced and the function is limited 80 pin 4 0780058 PD780058Ytet Serial of the uPD78054 was enhanced and EMI noise was reduced 80 pin EMI noise reduced version of the 4 PD78054 80 pin _ UART and D A converter were enhanced to the 2 078014 and I O was enhanced 64 pin PD780034 yPD780034Y A D converter of the 2 0780024 was enhanced 64 pin uPD780024 4PD780024Y Serial I O of the uPD78018F was added and EMI noise was reduced 64 pin uPD78014H EMI noise reduced version of uPD78018F 64 pin Low voltage 1 8 V operation version of the 78014 with larger selection of ROM and RAM capacities 64 pin An A D converter and 16 bit timer were added to the 78002 64 pin uPD780001 An A D converter was added to the uPD78002 64 pin Basic subseries for control 42 44 pin On chip UART capable of operating at low voltage 1 8 V Inverter control 64 uPD780964 A D converter of the 780924 was enhanced 64 pin uPD780924 4 On chip inverter control circuit and UART was reduced FIP drive 100 The I O and FIP C D of the 4PD78044F were enhanced Display output total 53 100
9. Za V 1 d Protrusion height S BBBBBBHHHHHHBHHBHBBH roa IHMHHHHNHNUUUUIUTERI D l Yb w x f h EX q GT m ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 21 75 0 856 a 22 75 0 896 B 14 25 0 561 b 0 5 0 020 0 65x19 12 35 0 026x0 748 0 486 0 5 0 020 D 0 65 0 026 d 4 62 0 4 60 079 7 0 0 276 1 8 0 071 20 75 0 817 f 9 45 0 372 G 28 25 1 112 9 1 85 0 073 H 17 4 0 685 h 3 7 0 146 21 75 0 856 3 9 0 154 J 0 65 29 18 85 0 026x1 142 0 742 j 0 2 0 008 K 23 9 0 941 k 1 2 0 047 L 0 65 0 026 15 25 0 600 M 0 4 0 016 m 16 25 0 640 N 6 0 0 236 n 0 5 0 020 3 1 0 3 0 039 0 25 0 010 1 5 0 059 0 5 0 020 3 R 1 5 3 R 0 059 q 6 95 0 274 R 17 15 0 675 NQPACK100RB G1E 5 10 0 0 394 12 0 0 472 U 23 65 0 931 V 15 25 0 600 w 16 25 0 640 x 0 5 0 020 Y 0 5 0 020 2 21 75 0 856 Remark Manufactured by Tokyo Eletech Corp 207 APPENDIX DEVELOPMENT TOOLS Figure B 3 HQPACK100RB Lid for Device Mounted Package Drawings Reference ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 17 4 0 685 a 2 25 0 089 B 0 65x19 12 35 0 026x0 748 0 486 b 1 6 0 063 C 0 65 0 026 c 0 25 0 0
10. 48K bytes 60K bytes 60K bytesNote High speed RAM 1024 bytes Expansion RAM 512 bytes FIP display RAM 96 bytes General purpose register 8 bits x 8 x 4 banks Minimum instruction execution time 0 4 0 8 1 6 3 2 6 4 us main system clock 5 0 MHz Instruction set 16 bit operation Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test Boolean operation BCD adjustment etc port including FIP multiplexed pins Total CMOS input CMOS N ch open drain I O P ch open drain 1 P ch open drain output 72 pins 8 pin 116 pins 16 pins 24 pins 8 pins FIP controller driver Total display output Display current 10 mA Display current 3 mA 48 pins 16 pins 32 pins A D converter 8 bit resolution x 8 channels Supply voltage AVpp 4 5 to 5 5 V Serial interface 3 wire serial mode 1 channel Timer 1 channel 2 channels 1 channel 8 bit remote control timer 8 bit PWM timer Watchdog timer Timer output 2 pins 8 bit PWM output Vectored Maskable Internal 6 external 4 interrupt source Non maskable Internal 1 Software 1 Supply voltage Vpp 4 5 to 5 5 V Package 100 pin plastic QFP 14 x 20 mm Note 48K or 60K bytes can be selected by the memory size select register IMS CHAPTER 1 GENERAL 1
11. I U 74 5 6 Changing CPU Clock 75 5 6 1 Time required to change CPU 75 5 6 2 gt GPU clock changinig procedure u u tan nt tet nee teca 76 CHAPTER 6 8 BIT REMOTE CONTROL TIMER eren nnn nnn nnne 77 6 1 Function of 8 Bit Remote Control Timer esee 77 6 2 Configuration of 8 Bit Remote Control Timer eren 77 6 3 Registers Controlling 8 Bit Remote Control Timer ree 78 6 4 Operation of 8 Bit Remote Control Timer eese 80 CHAPTER 7 8 BIT PWM TIMERS nma nn nnus manni nma nm nna tma immu nra nn 83 7 1 Functions of 8 Bit PWM Timers we 83 7 2 Configuration of 8 Bit PWM Timers 84 7 3 Registers Controlling 8 Bit PWM Timers U nennen 86 7 4 Operations of 8 Bit PWM Timers U u uu u uuu 89 7 4 1 Operation as interval timer 8 bit operation ee eee a 89 7 4 2 Operation as external event counter 92 7 4 3 Square wave 8 bit resolution output operation 93 7 4 4 8 bit PWM output operation 7 5 Notes on 8 Bit PWM Timers U U u u u u uu uu u CHAPTER 8 WATCHDOG TIMER ziazia
12. Oscillation Reset Period ME Normal Operation Normal Oper ti n Oscillation Stop are Reset Processing RESET N f l Internal I Reset Signal Hi Z PortPin 222222 lt lt e Figure 14 3 Timing of Reset due to Watchdog Timer Overflow e a VIP Oscillation Reset Period NOME Normal Operation Normal Operation Oscillation Stop Shia Reset Processing Watchdog Timer Overflow Internal Reset Signal l Hi Z PotPin 2292222 lt lt Figure 14 4 Timing of Reset in STOP Mode by RESET Input k STOP Instruction Execution Stop Status Reset Period Oscillation Normal Operation Normal Operation pe gt Oscillation Stabilization Oscillation Stop Stop Time Wait Reset Processing M I E Internal Reset Signal Delay Delay Hi Z Port Pin 1 EE 172 CHAPTER 14 RESET FUNCTION Table 14 1 Hardware Status after Reset Hardware Status after Reset Program counter PC Note 1 Contents of reset vector table 0000 0001 are set Stack pointer SP Undefined Program status word PSW 02H UndefinedNote 2 UndefinedNete 2 RAM Data memory General purpose register Port
13. 22 3 1 2 Internal data memory 23 3 1 3 Special function register SFR 23 3 1 4 Data memory addressirig ime eiae tenentes 24 3 2 Processor 28 3 201 Control registers 28 3 20 27 s General registers mi gripe tan 31 3 2 3 Special function registers SFR Special Function Register 32 3 3 Addressing of Instruction Address 35 3 31 Relative 35 3 3 2 Immediate addressing ence eee iere ned 36 3 3 3 Table indirect addressing ete ite ita 37 3 3 4 Register addressing eee ee eerie tede 38 3 4 Addressing of Operand Address 39 3 4 1 mplied addr ssing iip tse mide i n es 39 3 4 2 Register addressing iere tei eee eta de n Pd e a p HR 40 3 4 9 ot e n oe e et cients 41 3 4 4 Short direct addressing ecd 42 3 4 5 Special function register SFR addressing sss 44 3 4 6 Hegist r indirect addressing uu imeem 45 3 4 7 Based addressing usu 46 3 4 8 Based indexed 47 3 4 9 Stack addressin
14. i INTTM5n i TIO5n I 1 1 4 CR5n changed N gt 0 1 96 CHAPTER 7 8 BIT PWM TIMERS 2 Cascade 16 bit timer mode Operation as interval timer with 16 bit resolution The two PWM timers can be used as a 16 bit timer counter by setting bit 4 TMC5n4 of the 8 bit timer mode control register 5n TMC5n to 1 In this case the 16 bit timer counter operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance to the 8 bit compare register 5n CR5n Remark n 0or 1 Setting 1 Set each register TCL5n The low order timer selects the count clock The setting of the high order cascaded timer is not necessary CR5n Compare value Each compare value can be set in a range of 00H to FFH TMC5n Selects the clear amp start mode in which the timers are cleared and started on coincidence between TM5n and CR5n Low order timer TMC5n 0000xxx0B x don t care timer TMC5n 0001xxx0B don t 25 2 The counting is started when TCE5n of the high order timer is set to 1 followed by setting of TCE5n of the low order timer to 1 3 When the values of TM5n and CR5n of the cascaded timers cascade coincide INTTM5n is generated by the low order timer all the TM5n s are cleared to 00H 4 After that INTTM5n is repeatedly generated at the same interval Cautions 1 Before setting the 8 bi
15. 5 1 TOE5n FF70H TMC50 04H R W FF78H TMC51 TCE5n Controls counting by TM5n 0 Clears counter to 0 and disables counting prescaler disabled 1 Starts counting TMC5n6 Selects operation mode of TM5n 0 Clear amp start on coincidence between TM5n and CR5n 1 PWM free running mode TMC5n4 Selects single or cascade mode 0 Single mode used as low order timer Cascade mode connected to low order timer Sets status of timer output F F Does not affect Resets timer output F F to 0 Sets timer output F F to 1 Setting prohibited Other than PWM mode TMC5n6 0 PWM mode TMC5n6 1 Controls timer F F Selects active level Disables inversion High active Enables inversion Low active TOE5n Controls timer output 0 Disables output port mode 1 Enables output Remarks 1 In the PWM mode the PWM output is at the inactive level if TCE5n 0 2 When LVS5n and LVR5n are read after data has been set they 0 3 n Oor1 88 CHAPTER 7 8 BIT PWM TIMERS 7 4 Operations of 8 Bit PWM Timers 7 4 1 Operation as interval timer 8 bit operation An 8 bit PWM timer operates as an interval timer that generates an interrupt request at intervals specified by the count value set to the 8 bit compare register 5n CR5n in advance When the count value of the 8 bit counter 5n TM5n coincides with the set value of CR5n the value of TM5n is cleared to 0 and TM5n continues co
16. x 26 2 ms x 52 4 ms x 210 ms Remarks 1 fx Main system clock oscillation frequency 2 fx 5 0 MHz 107 108 CHAPTER 9 A D CONVERTER 9 1 Function of A D Converter The A D converter converts analog input signals into digital values with a resolution of 8 bits Eight analog input channels ANIO through ANI7 can be controlled The A D conversion operation can be started only by software One of the analog input channels ANIO through ANI7 is selected for A D conversion The A D conversion operation is repeatedly performed and each time it has been completed once an interrupt request INTAD is generated 9 2 Configuration of A D Converter The A D converter consists of the following hardware Table 9 1 A D Converter Configuration Analog input 8 channels ANIO through ANI7 Register Successive approximation register SAR A D conversion result register ADCRHO Control register A D converter mode register ADMO Analog input channel specification register ADSO 109 1 2 3 110 CHAPTER 9 A D CONVERTER Figure 9 1 A D Converter Block Diagram Sample amp hold circuit Voltage comparator E 2 o Successive approximation register SAR Tap selector INTAD Circuit A D conversion result register ADCRHO 0503 ADS02 ADS01 ADS00 UE 02 FRO1 FROO oloj
17. TM5n 00H 00H 00H l l l 1 l l CR5n 00H OOH TCE5n i 1 imis eam pe 5 1 l l 1 1 gt D Interval time n 0or1 CHAPTER 7 8 BIT PWM TIMERS Figure 7 4 Timing of Interval Timer Operation 2 3 c When CR5n FFH E Count clock ME E D V o 1 _ Interrupt request accepted Interrupt I ME request TlO5n accepted 1 l p zu Interval time n Oor1 d Operation when CR5n is changed M lt Count clock l l l m N 1 CR5n N i M TCE5n 1 i INTTM5n 5 u Change of CR5n TM5n overflows because lt n Oor1 91 CHAPTER 7 8 BIT PWM TIMERS Figure 7 4 Timing of Interval Timer Operation 3 3 Operation when 5 is changed gt Count clock N 1 N Mt M 00H l CR5n i 5 INTTM5n 5 4 Change of CR5n 0 1 7 4 2 Operation as external event counter The external event counter counts the number of count clock pulses input to TlO5n from an external source Each time the valid edge specified by the timer clock select register 5n TCL5n has been input to TlO5n the value
18. Port 5 N ch open drain 8 bit medium voltage I O port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor can be used by mask option in 1 bit units mask ROM models only LPD78F0228 does not have pull up resistors however Port 6 N ch open drain 8 bit medium voltage I O port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor can be used by mask option in 1 bit units mask ROM models only LPD78F0228 does not have pull up resistors however Port 7 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only 078 0228 does not have pull down resistors however FIP16 FIP23 P80 P87 Port 8 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however FIP24 FIP31 P90 P97 Port 9 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does have pull down resistors however FIP32 FIP39 P100 P107 50 Port 10 P ch open drain
19. S 2 Output latch P ch open drain 100 40 P100 to 107 s P107 FIP47 Alternate function O O Voan Mask Option Mask ROM model only LA PD78F0228 has no pull down resistor WR Port 10 write signal 62 CHAPTER 4 PORT FUNCTIONS 4 3 Port Function Control Registers The following two types of registers control the ports Port mode registers PM2 PM4 to PM6 Pull up resistor option register PUO PU2 PU4 1 Port mode registers PMO PM2 PM4 to PM6 These registers are used to set port input output in 1 bit units PMO PM2 and PM4 to PM6 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH When port pin is used as its alternate function pin set the port mode register and the output latch according to Table 4 3 Cautions 1 Pins P10 to P17 are input only pins 2 Pins P100 to P107 are output only pins 3 As port 0 has an alternate function as external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand Table 4 3 Port Mode Register and Output Latch Setting when Alternate Function is Used Pin Name Alternate Function Pin Name Alternate Function Function Name Input output Function Name Input output inpu
20. Voo AVss 21 80 P24 TIO50 P20 SCK P25 TIO51 Note Under development Cautions 1 Directly connect the IC Internally Connected pin to Vss in the normal operation mode 2 Connect the pin to 3 Connect the AVss to Vss1 Remarks 1 Whenusingthe microcontroller in an application where the noise generated from the microcontroller must be suppressed it is recommended that power be supplied to and from separate sources and that Vsso and Vss be connected to separate ground lines to improve the noise immunity 2 uPD78F0228 CHAPTER 1 GENERAL ANIO ANI7 Analog Input P90 P97 Port9 AVop Analog Power Supply P100 P107 Port10 AVss Analog Ground RESET Reset FIPO FIP47 Fluorescent Indicator Panel SCK Serial Clock IC Internally Connected Sl Serial Input INTPO INTP1 Interrupt from Peripherals SO Serial Output P01 Porto TH Timer Input P10 P17 Porti TIO50 TIO51 Timer Input Output P20 P25 Port2 Vppo Vpp2 Power Supply P40 P47 Port4 VLOAD Negative Power Supply P50 P57 Port5 VPP Programming Power Supply P60 P67 Port Vsso Vssi Ground P70 P77 Port7 1 X2 Crystal P80 P87 Port8 CHAPTER 1 GENERAL 1 5 78K 0 Series Expansion The following shows the 78K 0 Series products development Subseries name are shown inside frames L Products in mass production
21. 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock The system clock oscillator continues oscillating In this mode the current consumption cannot be decreased as in the STOP mode The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations like clock operations STOP mode STOP instruction execution sets the STOP mode In the STOP mode the main system clock oscillator stops and the whole system stops The CPU current consumption can be considerably decreased Data memory low voltage hold down to Voo 2 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure the oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory just before standby mode setting are held The input output port output latch and output buffer statuses are also held Cautions 1 When proceeding to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction 2 In order to decrease the power consumption in the A D converter c
22. 1 Port mode P70 through P77 function as an 8 bit I O port in this mode These pins are P ch open drain pins Pull down resistors can be connected to these pins of the mask ROM models by mask option The 078 0228 does not have pull down resistors 2 Control mode In this mode P70 through P77 function as the output pins of the FIP controller driver FIP 16 through FIP23 2 2 8 P80 through P87 Port 8 P80 through P87 constitute an 8 bit I O port These pins are also used as FIP controller driver output pins The following operation modes can be specified in 1 bit units 1 Port mode P80 through P87 function as an 8 bit I O port in this mode These pins are P ch open drain pins Pull down resistors can be connected to these pins of the mask ROM models by mask option The 078 0228 does not have pull down resistors 2 Control mode In this mode P80 through P87 function as the output pins of the FIP controller driver FIP24 through FIP31 13 CHAPTER 2 PIN FUNCTIONS 2 2 9 P90 through P97 Port 9 P90 through P97 constitute an 8 bit I O port These pins are also used as FIP controller driver output pins The following operation modes can be specified in 1 bit units 1 Port mode P90 through P97 function as an 8 bit I O port in this mode These pins are P ch open drain pins Pull down resistors can be connected to these pins of the mask ROM models by mask option The 078 0228 does not have pull down resistors 2 C
23. 5 High voltage output buffer that can directly drive FIP 6 FIPO through FIP15 pins are connected to pull down resistors FIP16 through FIP47 pins can be connected to pull down resistors by mask option mask ROM model only The uPD78F0228 does not have pull down resistors Of the 48 FIP output pins of the uPD780228 subseries FIP16 through FIP47 are multiplexed with port pins FIPO through FIP15 are dedicated output pins FIP16 through FIP47 can be used as port pins when FIP display is disabled by bit 7 DSPEN of the display mode register 0 DSPMO Even when FIP display is enabled the FIP output pins not used for display signal output can be used as port pins Table 11 1 FIP Output Pins and Multiplexed Port Pins FIP Pin Name Multiplexed Port Name FIP16 FIP23 P70 P77 port FIP24 FIP31 P80 P87 port FIP32 FIP39 P90 P97 port FIP40 FIP47 P100 P107 Output port 127 CHAPTER 11 FIP CONTROLLER DRIVER 11 2 Configuration of FIP Controller Driver The FIP controller driver consists of the following hardware Table 11 2 FIP Controller Driver Configuration Configuration Display 48 Control register Display mode register 0 DSPMO Display mode register 1 DSPM1 Display mode register 2 DSPM2 Figure 11 1 FIP Controller Driver Block Diagram FIPO FIP16 P70 FIP47 P107 128 CHAPTER 11 FIP CONTROLLER DRIVER 11 3 Registers Controlling FIP Controller Driver 11 3 1 Co
24. Ver 3 30 to Ver 6 2Nete 5 inch 2HD Refer to B 4 3 5 inch 2HC 5 inch 2HC IBM PC AT and compatible machines HP9000 series 300 HP UX rel 7 05B Cartridge tape QIC 24 HP9000 series 7007 HP UX rel 9 01 Digital audio tape DAT SPARCstation SunOS rel 4 1 1 EWS4800 series RISC EWS UX V rel 4 0 Cartridge tape QIC 24 Note Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software 201 APPENDIX DEVELOPMENT TOOLS B 2 Flash Memory Writing Tools Flashpro 11 part number FL PR2 Flash writer Flash writer dedicated to microcontroller with flash memory This is a product of Naito Densei Machida Mfg Co Ltd FA 100GF Flash memory writing adapter 202 Flash memory writing adapter for uPD780228 subseries and is connected to Flashpro Il This adapter is for a 100 pin plastic QFP GF 3BA type This is a product of Naito Densei Machida Mfg Co Ltd APPENDIX DEVELOPMENT TOOLS B 3 Debugging Tools B 3 1 Hardware 1E78001 R A SL Note In circuit emulator This in circuit emulator is used to debug the hardware and software when an application system using the 78K 0 series is developed It supports the integrated debugger ID78K0 This emulator is used with an emulation probe and an interface adapter to connect the host machine 1E 70000 98 IF B Interface adapter 1E 70000 98N F Interface ad
25. uu S mua Sau etta ee rtt ER Date Re qp ciun 15 4 Major Functions of Flash Memory Programming 16 1 Operand Identifiers and Description Methods sss nnne 182 A 1 Major Differences between uPD78044H 780228 and 780208 Subseries CHAPTER 1 GENERAL 1 1 Features High capacity ROM and RAM Program Memory Data Memory Mask ROM Flash memory Internal high Internal FIP display Part Number speed RAM expansion RAM RAM 0780226 48K bytes 1024 bytes 512 bytes 96 bytes uPD780228 60K bytes uPD78F0228 60K bytesNote Note 48K or 60K bytes can be selected by the memory size select register IMS e Minimum instruction execution time changeable from high speed 0 4 us to low speed 6 4 us port 72 pins e FIP controller driver Total display output pins 48 universal grid compatible Display current 10 mA 16 pins Display current 3 mA 82 pins 8 bit resolution A D converter 8 channels Supply voltage 4 5 to 5 5 V Serial interface 1 channel 3 wire serial I O mode 1 channel e Timer 4 channels 8 bit remote control timer 1 channel 8 bit PWM timer 2 channels Watchdog timer 1 channel e Vectored interrupt source 2 12 e Supply voltage 4 5 to 5 5 V 1 2 Application Fields Combined mini component audio systems separate mini component audio systems tuners cassette decks CD players and audio amplifiers 1 3 Ordering I
26. 0 1 Low level output Inversion of the timer output F F is enabled Timer output enable gt TOE5n 1 2 The count operation is started when TCE5n 1 3 The timer output F F is inverted when the values of TM5n and CR5n coincide Moreover INTTM5n is generated and 5 is cleared to 00H 4 After that the timer output F F is inverted at fixed intervals and TlO5n outputs a square wave Remark n 0 or 1 93 CHAPTER 7 8 BIT PWM TIMERS 7 4 4 8 bit PWM output operation The PWM timer performs 8 bit PWM output operation when bit 6 of the 8 bit timer mode control register 5n TMC5n is set to 1 and outputs a pulse with a duty factor determined by the value set to the 8 bit compare register 5n CR5n from the TIO5n pin Set the width of the active level of the PWM pulse to CR5n The active level can be selected by bit 1 TMC5n1 of TMC5n The count clock be selected by bits 0 through 2 TCL5n0 through TCL5n2 of the timer clock select register 5n TCL5n PWM output can be enabled or disabled by bit 0 TOE5n of TMC5n Caution CR5n can be rewritten only once in one cycle in the PWM mode Remark n 0or 1 1 Basic PWM output operation Setting 1 Set 0 to the port latch and port mode register n Set the active level width by using 8 bit compare register 5n CR5n Select the count clock by using timer clock select register 5n TCL5n Select the active level by using bit 1 TMC5n1 of TMC5n
27. 8 4 Hang up Detection Time of Watchdog Timer sss 106 8 5 Interval Time of Interval 107 9 1 A D Converter Configuration 2 5 inet rt srt Et tee da te RA shi d ta doni 109 10 1 Serial Interface Configuration irent ii netten 121 11 1 FIP Output Pins and Multiplexed Port Pins 2 eene nnne 127 11 2 FIP Controller Driver Configuration 128 12 1 Interrupt SOULCES 2008 eerte oet cec eden a dede en ee Qhuya 12 2 Various Flags Corresponding to Interrupt Request Sources 12 3 Times from Maskable Interrupt Request Generation to Interrupt Service 156 12 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 159 13 1 HALT Mode Operating 2 165 13 2 Operation after HALT Mode Release 167 13 3 STOP Mode Operating Status Dn tr a 168 13 4 Operation after STOP Mode Release 170 ix LIST OF TABLES 2 2 Table No Title Page 14 1 Hardware Status after Heset erede tied remettre eie 173 15 1 Differences between uPD78F0228 and Mask ROM Models 15 2 Set Value of Memory Size Select Register nennen 15 3 Communication Modes
28. 9 4 2 Input voltage and conversion result The analog voltage input to an analog input pin ANIO to ANI7 and the result of A D conversion A D conversion result register ADCRHO have the following relation VIN ADCRHO INT x 256 0 5 or ADCRHO 0 5 x AVDD _ ya lt ADCRH0 0 5 oe 6 256 INT Function that returns integer of value in ViN Analog input voltage AVDD Supply voltage to A D converter ADCRHO Value of A D conversion result register ADCRHO Figure 9 5 shows the relation between the input analog voltage and A D conversion result Figure 9 5 Relation between Input Analog Voltage and A D Conversion Result to opa e ee 254 4 253 e A D conversion result ADCRHO 1 522 0228 9 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input voltage AVop 116 CHAPTER 9 A D CONVERTER 9 4 3 Operation mode of A D converter Select one analog input channel from ANIO through ANI7 by the analog input channel specification register ADSO to start A D conversion The A D conversion operation can be started only by software by setting the A D converter mode register ADMO The A D conversion result is stored in the A D conversion result register ADCRHO and an interrupt request signal INTAD
29. Be sure to set bits 2 through 7 of PROH to 1 150 CHAPTER 12 INTERRUPT FUNCTIONS 4 External interrupt rising edge enable register EGP This register specifies whether the valid edges of INTPO and are specified to be the rising edge It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to OOH by RESET input Figure 12 5 External Interrupt Rising Edge Enable Register Format 0 Address At Reset R W 7 6 5 4 3 2 1 o o o o o Enables or disables specification of rising edge of INTPn as valid edge n 0 or 1 Disable Enable 5 External interrupt falling edge enable register EGN This register specifies whether the valid edges of INTPO and are specified to be the falling edge It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to OOH by RESET input Figure 12 6 External Interrupt Falling Edge Enable Register Format 1 0 Address At Reset R W 7 6 5 4 3 2 cn o o o o ee 1 Enables or disables specification of falling edge of INTPn as valid edge n 0 or 1 Disable Enable 151 6 Symbol PSW 152 CHAPTER 12 INTERRUPT FUNCTIONS Program status word PSW The program status word is a register to hold the instruction execution result and the current status for interrupt request The IE flag to
30. CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Operation Group rp word rp lt word saddrp word saddrp word sfrp word sfrp word AX saddrp AX lt saddrp 16 bit saddrp AX saddrp data AX sfrp AX lt sfrp transfer sfrp AX sfrp lt AX rp AX lt rp rp AX rp AX AX laddr16 AX lt addr16 laddr16 AX addr16 AX AX rp AX orp A byte A CY A byte saddr byte saddr CY lt saddr byte A r A CY A r lt saddr A A saddr A 16 A lt A addr16 A HL A CY A HL A HL byte A CY lt HL byte A HL B A CY lt HL B 8 bit A HL C A CY lt A HL C operation A byte A CY A byte CY saddr byte saddr CY lt saddr byte CY A r A CY A r CY lt CY saddr A CY lt A saddr CY A 16 A A addr16 A HL A CY lt HL CY A HL byte A CY A HL byte CY A HL B A CY lt HL B CY A HL C A CY lt HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Only when r
31. Describe the symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 3 gives a list of special function registers The meaning of items in the table is as follows Symbol This is a symbol to indicate an address of the special function register The symbols shown in this column are reserved words of the RA78K 0 and have already been defined in the header file called sfrbit h of the CC78K 0 These are describable as instruction operands if the RA78K 0 78 0 or SD78K 0 is used RW Indicates whether the corresponding special function register can be read or written R W Read write enable R Read only W Write only Manipulatable bit units O indicates the bit unit 1 8 or 16 bits in which the register can be manipulated indicates that the register cannot be manipulated in the indicated bit unit Atreset Indicates each register status upon RESET input CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 1 2 Address Special Function Register SFR Name Manip
32. Series resistor string The series resistor string is connected between the AVpp and AVss pins and generates a voltage to be compared with the input analog signal ANIO through ANI7 pins These are 8 channels of analog input pins of the A D converter and input analog signals to be converted Caution Make sure that the input voltages of ANIO through ANIT are within the rated range If a voltage greater than or less than AVss is input a channel even if it is within the absolute maximum rating range the converted value of the channel is undefined and in the worst case the converted values of the other channels are affected AVss pin This is the ground potential pin of the A D converter Make sure this pin is always at the same potential as the Vssi pin even when the A D converter is not used pin This is the analog power supply pin of the A D converter Make sure that this pin is always at the same potential as the pin even when the A D converter is not used In the standby mode the current flowing to the series resistor string can be lowered by stopping the conversion operation by clearing bit 7 CSO of the A D converter mode register ADMO 111 CHAPTER 9 A D CONVERTER 9 3 Registers Controlling A D Converter The following two types of registers control the A D converter A D converter mode register ADMO Analog input channel specification register ADSO 1 A D converter mode register AD
33. Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in circuit emulator Part Number Product Name uSxxxxFD78K0 PC 9800 series IBM PC AT and compatible machines Remark xxxx in the part number differs depending on the host machine and OS USxxxxFE9000 USxxxxFT9080 USXxxxF178KO 78 USXxxxFE9200 USXxxxFT9085 uSxxxxFI78K0 uSxxxxFD78K0 Host Machine Distribution Medium 5A13 PC 9800 series MS DOS 3 5 inch 2HD saio Ver 3 30 to Ver 6 2 5 inch 2HD a Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software 214 Host Machine Os Distribution Medium 7813 IBM PC AT and Refer to B 4 3 5 inch 2 0 compatible machines 5 inch 2 APPENDIX REGISTER INDEX D 1 Register Index ADCRHO ADM ADOS CR10 CR11 CR50 CR51 CSIM3 D DSPMO DSPM1 DSPM2 E EGN EGP 1 IFOH IFOL IMS 5 MKOH MKOL OSTS P PO 1 2 4 5 6 7 A D conversion result register 110 A D converter mode register 112 A D converter input select register 113 8 bit compare register 10 79 8 bit capture register 11 79 8 bit compare register 50 85 8 bit compare register 51 85 Serial operating mode register 3 123 125 Display mode register 0 129 Display mode register 1 131 Di
34. The timer starts counting when bit 7 TCE5n of TMC5n is set to 1 To stop the counting set 0 to TCE5n 2 3 4 5 Remark n 0or 1 PWM output operation 1 When the timer starts counting an inactive level is output from TlO5n as PWM output until the timer overflows 2 When the overflow occurs the active level set in 1 in Setting above is output The active level is continuously output until the CR5n and the count value of the 8 bit counter 5n TM5n coincide 8 The inactive level is output after CR5n and the count value have coincided until an overflow occurs again 4 After that 2 and 3 are repeated until the counting operation is stopped 5 PWM output is deasserted inactive when the counting operation is stopped by clearing TCE5n to 0 Remark 0 1 94 CHAPTER 7 8 BIT PWM TIMERS a Basic PWM output operation Figure 7 6 PWM Output Operation Timing i Basic operation when active level H Count clock TEE ese i EDPETT PUDE TITUL Msn O E aL CR5n N 6 _ i 07 hats H I INTTM5n E MEME 1 1 1 1 1 1 1 ik Active level Inactive level Active level 0 1 ii When CR5n 0 Count clock l J L J l l L TM5n 009 oH TA IN NaNe Tul M 00H cR amp n 00H Tcesn_ i T
35. and a stack pointer SP are control registers 1 Program counter PC PC 28 2 The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration 15 0 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 8 Program Status Word Configuration 7 0 vow D z Teese s ee Le a Interrupt enable flag IE This flag controls interrupt request acknowledge operations of CPU When IE 0 all interrupts except the non maskable interrupt are disabled DI status When IE 1 the interrupts are enabled El status At this time acknowledging interrupts is controlled with an inservice priority flag ISP and an interrupt mask flag for various interrupt sources and a priority specify flag The i
36. depending on the value of bit 7 to which the result has been already set Bit 7 1 3 4 AVpp Bit 7 0 1 4 AVDD This voltage tap is compared with the input analog voltage Depending on this result bit 6 of SAR is manipulated as follows If input analog voltage voltage tap Bit 6 1 If input analog voltage voltage tap Bit 6 0 Comparison continues like this up to bit 0 of SAR When comparison of 8 bits has been completed the valid digital result remains in SAR and its value is transferred and latched to the A D conversion result register ADCRHO At the same time an A D conversion end interrupt request INTAD is generated CHAPTER 9 A D CONVERTER Figure 9 4 Basic Operation of A D Converter Conversion time Sampling time gt Operation of A D converter Sampling A D conversion SAR Undefined ADCRHO Conversion result Conversion result INTAD The A D conversion operation is performed successively until bit 7 CSO of the A D converter mode register ADMO is reset to 0 by software If an attempt is made to write data to ADMO or analog input channel specification register ADSO during A D conversion operation the conversion operation is initialized and conversion is started from the beginning if CSO is set to 1 The value of the A D conversion result register ADCRHO is undefined when the RESET signal is input 115 CHAPTER 9 A D CONVERTER
37. is generated A D conversion by software start Converting the voltage applied to the analog input pin specified by the analog input channel specification register ADSO is started when bit 7 CSO of the A D converter mode register ADMO is set to 1 When the A D conversion has been completed the result of the conversion is stored in the A D conversion result register ADCRHO and an interrupt request INTAD is generated When the A D conversion has been started and completed once the next conversion operation is immediately started This is repeated until new data is written to ADSO If ADSO is rewritten during A D conversion the conversion under execution is stopped and conversion of the selected analog input channel is started If data with CSO being 0 is written to ADMO during A D conversion the conversion is immediately stopped Figure 9 6 A D Conversion by Software Start Rewriting ADSO Rewriting ADSO CS0 1 CS0 1 50 0 A D conversion does not remain during A D conversion Conversion result INTAD Remark 0 1 7 iius 117 CHAPTER 9 CONVERTER 9 5 Notes A D Converter 1 2 3 118 Current consumption in standby mode The A D converter is stopped in the standby mode At this time the current consumption can be reduced by stopping the conversion by clearing bit 7 CSO of the A D converter mode register ADMO to 0 Figure 9 7 shows how t
38. used as input port P50 P57 Port 5 N ch open drain 8 bit medium voltage port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull up resistors however P60 P67 Port 6 N ch open drain 8 bit medium voltage I O port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull up resistors however P70 P77 Port 7 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however FIP16 FIP23 1 Port pins 2 2 Pin Name P80 P87 CHAPTER 2 PIN FUNCTIONS Function Port 8 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however At Reset Shared with FIP24 FIP31 P90 P97 Port 9 P ch open drain 8 bit high voltage I O port Can be set in input or output mode in 1 bit units Internal pull down resistor can be used by mask optio
39. 0 Interrupt serving enabled standby mode release enabled 1 Interrupt serving disabled standby mode release disabled Cautions 1 If WDTMK flag is read when a watchdog timer is used in watchdog timer mode 1 value becomes undefined 2 Because port 0 has a dual function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Be sure to set bits 2 through 7 of MKOH to 1 149 CHAPTER 12 INTERRUPT FUNCTIONS 3 Priority specify flag registers PROL and PROH The priority specify flag is used to set the corresponding maskable interrupt priority orders PROL and PROH are set with a 1 bit or 8 bit memory manipulation instruction When PROL and PROH are used in combination as a 16 bit register PRO they are set with a 16 bit memory operation instruction RESET input sets these registers to FFH Figure 12 4 Priority Specify Flag Register Format Symbol 7 lt 6 gt 2 1 0 Address At Reset R W PROL TMPR50 CSIPR3 KSPR TMPR11 TMPR10 PPR1 PPRO WDTPR FFE8H FFH R W lt 1 gt lt 0 gt FFE9H FFH R W Priority Level Selection PROH 0 High priority level 1 Low priority level Cautions 1 When watchdog timer is used in watchdog timer mode 1 set 1 in WDTPR flag 2
40. 1 enable 0 disable ISP Flag indicating priority of interrupt currently processed 0 interrupt with high priority is processed 1 interrupt request is not acknowledged or interrupt with low priority processed 157 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 12 Interrupt Request Acknowledge Timing Minimum Time 6 Clocks y 5 Interrupt CPU Processing Instruction Instruction PSW and PC Save Jump 10 servicing Interrupt Servicing P rogram xxPR 1 8 Clocks xxPR 0 7 Clocks Remark 1 clock fcPu CPU clock CPU Figure 12 13 Interrupt Request Acknowledge Timing Maximum Time 25 Clocks 6 Clocks x 4 Interrupt CPU Processing Instruction Divide Instruction PSW and PG Save Jump scm Interrupt Servicing P rogram we TT TT TT TTT xxPR 1 33 Clocks xxPR 0 32 Clocks Remark 1 clock fcPu CPU clock 12 4 3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution Software interrupt cannot be disabled If a software interrupt request is acknowledged it is saved in the stacks program status word PSW program counter PC in that order the IE flag is resetto 0 and the contents of the vector tables 00 and 003FH are loaded into PC and branched Return from the software interrupt is possible with the RETB instruction Caution Do not use the R
41. 1 TMC1 8 bit capture registers CP10 and CP11 8 bit timer register TM1 1 Symbol TMC1 78 Timer mode control register 1 TMC1 This register enables or disables the operation of the 8 bit timer TM1 sets the count clock and detects overflow TMC1 is set by using a 1 bit or 8 bit memory manipulation instruction This register is initialized to OOH by RESET input Figure 6 2 Timer Mode Control Register 1 Format lt 7 gt lt 2 gt Address At Reset R W TCE1 Controls count operation of TM1 Clears count to 0 and stops operation Starts count operation Detects overflow of TM1 No overflow Overflow Selects count clock fx 210 4 9 kHz fx 2 9 8 kHz fx 24 313 kHz fx 23 625 kHz Caution Be sure to clear bits 3 through 6 to 0 Remarks 1 fx Main system clock oscillation frequency 2 5 0 MHz 2 3 CHAPTER 6 8 BIT REMOTE CONTROL TIMER 8 bit capture registers CP10 and CP11 These 8 bit registers capture the contents of the 8 bit timer TM1 The capture operation is performed in synchronization with the valid edge input to the TI1 pin capture trigger The contents of CP10 are retained until the next rising edge of the TI1 pin is detected The contents of CP11 are retained until the next falling edge of the TI1 pin is detected CP10 and CP11 can be read by using an 8 bit memory manipulation instruction The values of these registers are initialized
42. 5 5 V 0 5 V 35 V Y 31 dots xis 1 155 0 mW 25 11 Grids 1 16 Total power dissipation lt gt 2 lt 3 gt 115 5 17 2 3 6 50 9 155 0 342 2 mW In this example the total power dissipation do not exceed the rating of the total power dissipation so there is no problem in power dissipation However when the total power dissipation exceeds the rating of the total power dissipation it is necessary to lower the power dissipation To reduce power dissipation reduce the number of pull down resistor CHAPTER 11 FIP CONTROLLER DRIVER Figure 11 11 Relationship between Display Data Memory and FIP Output with 10 Segments 11 Digits Displayed Display data memory FA20H FA1FH FA1EH 0 1 FA1DH FA1CH FA1BH 0 0 0 0 0 0 FA1AH FA19H FA18H 0 0 0 0 1 0 0 FA17H FA16H FA15H 0 0 0 0 0 FA14H FA13H FA12H 0 0 0 0 0 FA11H FA10H 0 0 0 0 FAQEH 0 0 0 0 0 0 0 FA0BH FA09H 0 0 0 0 0 0 0 FA08H FA07H 06 0 0 FA05H FA04H FA03H 0 0 0 0 FA02H FAQ1H FA00H 0 Y Y Y FIP output pins 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O 1 i g e SUN MON TUE WED THU FRI SAT a am if Ed lel LE n gl j l Ld tel
43. 780208 SUBSERIES Change of hardware for debugging tools as follows Change of IE 780000 SL to IE 78001 R A Deletion of IE 78K0 SL EM CPU core board Change of EP 100GF SL from under development to developed Previous edition Deletion of Upgrading Your In Circuit Emulator to Emulator for 78K 0 Series p 217 Addition of APPENDIX E REVISION HISTORY The mark shows major revised points Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 800 366 9782 Fax 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1
44. No on chip pull up resistors can be used to the bits set to the output mode irrespective of PUO PU2 PU4 setting PUO PU2 and PU4 are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 4 14 Pull Up Resistor Option Register Format Symbol 7 6 5 4 3 0 Address At Reset R W 2 1 ew o o o o o o Pupu FrsoH nw PU2 o PU25 PU24 PU23 22 PU21 PU20 FF32H 00H R W PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 40 FF34H 00H R W Pmn Internal Pull up Resistor Selection m 0 n 0 1 m 2 n 0 5 4 0 7 0 Internal pull up resistor not used 1 Internal pull up resistor used 65 CHAPTER 4 PORT FUNCTIONS 4 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 4 4 1 Writing to input output port 1 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode A value is written to the output latch by a transfer instruction but since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instructi
45. PM Port mode register RD Port 2 read signal WR Port 2 write signal 54 WRru CHAPTER 4 PORT FUNCTIONS Figure 4 5 P21 to P25 Block Diagram PU21 PU25 Internal bus PU PM RD WR Output Latch P21 P25 PM21 PM25 P21 SO P22 SI r J gt x P24 TIO50 P25 TIO51 Alternate Function Pull up resistor option register Port mode register Port 2 read signal Port 2 write signal 55 4 2 4 Port 4 Port 4 is an 8 bit input output port with output latch P40 to P47 pins can specify the input mode output mode 1 bit units with the port mode register 4 PM4 When P40 to P47 pins are used as input ports an on chip pull up resistor can be connected to them in 1 bit units with a pull up resistor option register 4 PU4 56 CHAPTER 4 PORT FUNCTIONS Port 4 can drive LEDs directly RESET input sets port 4 to input mode Figure 4 6 shows a block diagram of port 4 Figure 4 6 P40 to P47 Block Diagram Vono PU40 PU47 Internal bus PU PM RD WR Output latch P40 P47 PM40 PM47 Pull up resistor option register Port mode register Port 4 read signal Port 4 write signal P40 P47 CHAPTER 4 PORT FUNCTIONS 4 2 5 Port 5 Port 5 is an 8 bit input output port with output latch Pins from 50 to 57 can specify I O mode in 1 bit units with the port mo
46. QFP 14 x 20 mm Provided 100 pin plastic QFP 14 x 20 mm 100 pin ceramic WQFN uPD78P0208 only Electrical characteristics and Refer to individual Data Sheet recommended soldering conditions Remark In addition to the above items the organization of the development tools also differ between the above subseries especially between the PROM model and flash memory model For details refer to the User s Manual of each subseries 197 198 APPENDIX DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the uPD780228 subseries Figure B 1 shows the development tools 199 APPENDIX DEVELOPMENT TOOLS Figure B 1 Development Tools Language processing software Assembler package Embedded software Real time OS and OS C compiler package Fuzzy inference development C library source file support system System simulator Integrated debugger Device file Host machine PC or EWS Interface adapter Flash memory programming preference In circuit emulator board Flash writer Probe board Flash memory writing adapter Emulation probe Flash memory containing version Conversion socket Target system 200 APPENDIX DEVELOPMENT TOOLS B 1 Language Processing Softwa
47. Select Register CHAPTER 8 WATCHDOG TIMER CHAPTER 13 STANDBY FUNCTION Change of setting of FOUT5 FOUTO and addition of notes on FIP output pins Addition of 11 7 Calculation of Total Power Dissipation CHAPTER 11 FIP CONTROLLER DRIVER Change of product name of dedicated flash writer as follows Flashpro to Falshpro Il part No FL PR2 CHAPTER 15 uPD78F0228 APPENDIX B DEVELOPMENT TOOLS Addition of APPENDIX DIFFERENCES BETWEEN 4 PD78044H 780228 AND 780208 SUBSERIES APPENDIX A DIFFERENCES BETWEEN 4 PD78044H 780228 AND 780208 SUBSERIES Change of hardware for debugging tools as follows Change of IE 780000 SL to IE 78001 R A Deletion of IE 78K0 SL EM CPU core board Change of EP 100GF SL from under development to developed Deletion of Upgrading Your In Circuit Emulator to Emulator for 78K 0 Series APPENDIX DEVELOPMENT TOOLS 217 218 Although NEC has taken all possible steps 55 0 to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philip
48. and description methods Operands are described in the column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols and are key words and are described as they are Symbols have the following meaning 4 Immediate data specification Absolute address specification Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Identifier saddr saddrp Table 16 1 Operand Identifiers and Description Methods Description Method X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX BC RP1 DE RP2 HL RP3 Special function register symbolNete Special function register symbols 16 bit manipulatable register even addresses only Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels even addresses only addr16 addr11 addr5 0000H to FFFFH Immediate data or labels Only even address
49. can branch in the entire memory space The addr11 instruction branches to an area of addresses 0800H to OFFFH Illustration In the case of CALL addr16 and BR addr16 instructions CALL or BR Low Addr High Addr In the case of CALLF addr11 instruction 7 6 4 3 0 fatotos CALLF 36 CHAPTER 3 CPU ARCHITECTURE 3 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresses 40H to 7FH andcan branch in the entire memory space Illustration 7 6 5 1 0 15 8 7 6 5 10 Effective Address 0000000000 if 0 7 Memory Table 0 Low Addr Effective Address 1 High Adar 37 CHAPTER 3 CPU ARCHITECTURE 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 38 CHAPTER 3 CPU ARCHITECTURE 3 4 Addressing of Operand Address The following various methods are available to specify the r
50. clock control register PCC Processor clock control register PCC This register selects a CPU clock and selects a division ratio PCC is set by using a 1 bit or 8 bit memory manipulation instruction Its value is set to 04H at RESET Figure 5 2 Processor Clock Control Register Format Symbol 7 6 Address AtReset R W 5 4 3 2 1 0 Selects CPU clock fcpu fx fx 2 fx 2 fx 23 fx 24 Setting prohibited Caution Be sure to clear bits 3 through 7 to 0 Remark fx Oscillation frequency of main system clock The shortest instruction of the 0780228 subseries is executed in two CPU clocks Therefore the relation between the CPU clock fceu and minimum instruction execution time is as shown in Table 5 2 Table 5 2 Relation between CPU Clock and Minimum Instruction Execution Time CPU Clock fceu Minimum Instruction Execution Time 2 fceu fx 2 5 0 MHz fx Main system clock oscillation frequency 70 CHAPTER 5 CLOCK GENERATOR 5 4 System Clock Oscillator 5 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator 5 0 MHz TYP connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin Figure 5 3 shows an external circuit of the main system clock oscillator Figure
51. display mode register 2 DSPM2 when bit 7 DSPEN of the display mode register 0 DSPMO is 1 Remarks 1 fx Main system clock oscillation frequency 2 fk 5 0 MHz CHAPTER 11 FIP CONTROLLER DRIVER 11 3 2 One display period and blanking width The FIP output signals are blanked equally at the beginning and end of the display period by the blanking width set by bits 0 through 2 FBLKO through FBLK2 of the display mode register 1 DSPM1 Figure 11 5 Blanking Width of FIP Output Signal 1 display period Tose fy 116 1 16 _ FIP output signal blanking width 1 16 1 8 1 8 En FIP output signal blanking width 2 16 FIP output signal blanking width 4 16 133 CHAPTER 11 FIP CONTROLLER DRIVER 11 4 Display Data Memory The display data memory is a 96 byte RAM area that stores data to be displayed and is mapped to addresses FAOOH through FA5FH The FIP controller reads the data stored in the display data memory independently of the CPU operation for FIP display DMA operation The area of the display data memory not used for display can be used as a normal RAM area At key scan timing all the FIP output pins are cleared to 0 and the data of the output latches of ports 7 through 10 are output to FIP16 P70 through FIP47 P107 The address location of the display data memory is as follows With 48 FIP output pins and 16 patterns The addresses of the display data memory corr
52. erased status of entire memory High speed write Writes flash memory based on write start address and number of written data number of bytes Successive write Successively writes based on information input in high speed write mode Status Used to check current operation mode and end of operation Oscillation frequency setting Erase time setting Inputs frequency information on oscillator Inputs erase time of memory Silicon signature read Outputs device name memory capacity and block information of device 179 CHAPTER 15 4PD78F0228 15 3 3 Connection of Flashpro II Connection between the Flashpro and uPD78F0228 differs depending on the selected communication mode Figures 15 4 and 15 5 show the connections in the respective mode Figure 15 4 Connection of Flashpro Il in 3 Wire Serial I O Mode Flashpro 11 078 0228 Figure 15 5 Connection of Flashpro Il Pseudo 3 Wire Serial I O Mode Flashpro Il LPD78F0228 RESET P40 serial clock P42 serial input P41 serial output Vss 180 CHAPTER 16 INSTRUCTION SET The instruction set for the 0780228 subseries is described in the following pages For the details of operations and mnemonics instruction codes of each instruction refer to 78 0 Series User s Manual Instructions U12326E 181 16 1 Legend CHAPTER 16 INSTRUCTION SET 16 1 1 Operand identifiers
53. in synchronization with the rising edge of the count clock When the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is cleared to in the following cases 1 RESET input 2 Clearing TCE5n 3 Coincidence between TM5n and CR5n in clear amp start mode Caution In the cascade mode TCE5n of the low order timer is 00H even if it is cleared Remark 0 1 8 bit compare register 5n CR5n n 0 or 1 The value set in this register is constantly compared with the count value of the 8 bit counter 5n TM5n When the two values coincide an interrupt request INTTM5n is generated in the modes other than PWM mode The value of CR5n can be set in a range of 00H to FFH and can be rewritten during count operation Caution When setting data to this register in the cascade mode be sure to stop the timer operation Remark n O0 or 1 85 CHAPTER 7 8 BIT PWM TIMERS 7 3 Registers Controlling 8 Bit PWM Timers The following two types of registers control the 8 bit PWM timers Timer clock select register 5n TCL5n n 0 or 1 8 bit timer mode control register 5n TMC5n n 0 or 1 1 Timer clock select register 5n TCL5n n 0 or 1 This register sets the count clock of the 8 bit counter 5n TM5n n 0 or 1 TCL5n is set by using an 8 bit memory manipulation instruction The value of this register is initialized to 00H by
54. or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Exceptr A Remark One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 186 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Operation Group AB A byte sadar byte A r nA lt A v byte saddr lt saddr v byte lt lt saddr lt A v saddr laddr16 A HL A lt A v addr16 A A v HL A A HL byte A A byte saddr byte A r nA A A v HL byte A A v HL A A v HL A A byte saddr saddr v byte AcAvr rervA 8 bit A saddr operation A laddr16 A HL A HL byte A HL B A HL C A byte saddr byte A lt A v saddr m mj nmj coj rnj rnmj rnmj rn A lt A v addr16 A A s HL A A amp A lt HL byte A A x HL B A A gt HL C A byte saddr byte A saddr N N N N N A addr16 A HL A A HL byte A HL B ojojo o O O oo oo j oo jojo j o coo o O N N N A HL C Notes 1 When the internal high speed RAM area is acces
55. output latch Ports 0 2 ports 4 10 2 P4 P10 00H Port read Port mode register PLR7 PLR9 PMO PM2 PM4 PM6 Undefined FFH Pull up resistor option register PUO PU2 PU4 00H Processor clock control register PCC 04H Memory size select register IMS CCHNete 3 Internal expansion RAM size select register IXS OCHNete 4 Oscillation stabilization time select register OSTS 04H 8 bit remote control timer Capture registers CP10 CP11 8 bit PWM timer Mode control register TMC1 Timer registers TM50 TM51 Compare registers CR50 CR51 Undefined Mode control registers TMC50 TMC51 04H Clock select registers TCL50 TCL51 00H Watchdog timer Clock select register WDCS 00H Mode register WDTM 00H A D converter Conversion result register ADCRHO Mode register ADMO Undefined Analog input channel specification register ADSO 00H Serial interface Shift register SIO3 Undefined Mode register CSIM3 00H FIP controller driver Display mode register 0 DSPMO 10H Display mode register 1 DSPM1 01H Display mode register 2 DSPM2 00H Interrupt External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN Request flag registers IFOL IFOH Mask flag registers MKOL MKOH Pri
56. register to hold the start address of the memory stack area Only the internal high speed RAM area FBOOH to FEFFH can be set as the stack area 15 0 Figure 3 9 Stack Pointer Configuration The SP is decremented ahead of write save to the stack memory and is incremented after read restore from the stack memory Each stack operation saves restores data as shown in Figures 3 10 and 3 11 Caution Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution 29 SP SP 2 SP 2 SP 1 SP gt SP gt SP 1 85 SP 2 30 CHAPTER 3 CPU ARCHITECTURE Figure 3 10 Data to be Saved to Stack Memory CALL CALLF and PUSH rp Instruction CALLT Instruction 5 5 3 5 5 2 BS Register Pair P 2 T ate Register Pair SP 1 PC15 to PC8 SP 1 Upper II 2 m Figure 3 11 Data to be Restored from Stack Memory POP rp Instruction RET Instruction Register Pair Lower SP gt PC7 to PCO SP gt SP 1 PC15 to PC8 SP 1 SP SP 2 SP 2 SP SP 3 Interrupt and BRK Instruction PC15 to PC8 PSW and RETB Instruction PC7 to PC0 PC15 to PC8 CHAPTER 3 CPU ARCHITECTURE 3 2 2 General registers A general register is mapped at particular addresses FEEOH to FEFFH of the data memory It consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also b
57. series Source program of mass production object MS DOS Ver 3 30 to Ver 6 2 e Distribution Medium 3 5 inch 2HD 5 inch 2HD IBM PC AT and their compatible machines Refer to B 4 3 5 inch 2HC 5 inch 2HC HP9000 series 300 HP UX rel 7 05B Cartridge tape QIC 24 HP9000 series 700 HP UX rel 9 01 Digital audio tape DAT SPARCstation SunOS rel 4 1 1 EWS4800 series RISC EWS UX V rel 4 0 Cartridge tape QIC 24 Note Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software C 1 Real time OS 2 2 APPENDIX C EMBEDDED SOFTWARE 78 0 LITRON specification subset OS Nucleus of 78 0 is supplied OS This OS performs task management event management and time management It controls the task execution sequence for task management and selects the task to be executed next Part number u SxxxxMX78K0 A A A Remark and AA Ain the part number differs depending on the host machine and OS etc LSxxxxMX78KO0 AA A Product Outline Evaluation object Use for trial product Mass production object Use for mass produced product Source program Host Machine PC 9800 series be purchased only when object for mass produced product is purchased MS DOS Ver 3 30 to Ver 6 2704 Distribution Medium 3 5 inch 2HD 5 inch 2HD IBM PC AT a
58. set maskable interrupt enable disable and the ISP flag to control multiple interrupt processing are mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions El and DI When a vectored interrupt request is acknowledged and the BRK instruction is executed the contents of the PSW is automatically saved into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The contents of the PSW is also saved into the stack with the PUSH PSW instruction It is reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 12 7 Program Status Word Configuration 7 6 At Reset 02H 5 4 3 2 1 0 eT eee pen gt Used when Normal Instruction is Executed ISP Priority of Interrupt Currently Being Received 0 High priority interrupt servicing low priority interrupt disable 1 Interrupt request not acknowledged or low priority interrupt servicing all maskable interrupts enable Interrupt Request Acknowledge Enable Disable Disable Enable CHAPTER 12 INTERRUPT FUNCTIONS 12 4 Interrupt Servicing Operations 12 4 4 Non maskable interrupt request acknowledge operation A non maskable interrupt request is unconditionally acknowledged even if in a
59. the interrupt mask flag to 1 51 CHAPTER 4 PORT FUNCTIONS Figure 4 2 00 and P01 Block Diagram Vppo WReu z PU00 PU01 WRrort Output Latch POO INTPO 00 and P01 PO1 INTP1 Internal bus and 1 Pull up resistor option register Port mode register RD Port 0 read signal WR Port 0 write signal CHAPTER 4 PORT FUNCTIONS 4 2 2 Port 1 Port 1 is an 8 bit input only port A D converter analog input is provided as an alternate function Figure 4 3 shows a block diagram of port 1 Figure 4 3 P10 to P17 Block Diagram Internal bus P10 ANIO to P17 ANI7 RD Port 1 read signal 53 CHAPTER 4 PORT FUNCTIONS 4 2 3 Port 2 Port 2 is a 6 bit input output port with output latch P20 to P25 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 When P20 to P25 pins are used as input ports an on chip pull up resistor can be connected to them in 1 bit units with a pull up resistor option register 2 PU2 Alternate functions include serial interface data input output clock input output and timer input output RESET input sets port 2 to input mode Figures 4 4 and 4 5 show block diagrams of port 2 Figure 4 4 P20 Block Diagram Vopo WRPu z Internal bus 20 5 Alternate Function PU Pull up resistor option register
60. to 00H by RESET input 8 bit timer register TM1 This 8 bit register counts the count pulse It can be read by using an 8 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input or by clearing the TCE1 bit 79 CHAPTER 6 8 BIT REMOTE CONTROL TIMER 6 4 Operation of 8 Bit Remote Control Timer The 8 bit remote control timer operates as a pulse width measuring circuit The width of a high level or low level external pulse input to the TI1 pin is measured by operating the 8 bit timer TM1 in the free running mode Detection ofthe valid edge is sampled every 2 cycles of the count clock selected by TCL1 and TCL2 and the capture operation is not performed until the valid level has been detected two times Therefore the pulse width input to the 1 pin must be 5 or more of the count clock set by TCL1 and TCL2 regardless of whether the level is high or low If the pulse width is less than 5 clocks it cannot be detected and the capture operation is not performed The value of timer register 1 TM1 is loaded to and retained in the capture registers CP10 and CP11 in synchronization with the valid edge of the pulse input to the TI1 pin as shown in Figure 6 3 Figure 6 3 shows the timing of pulse width measurement Figure 6 3 Timing of Pulse Width Measurement 1 2 1 To measure pulse width in synchronization with rising edge FFH FFH Count value of TM1 D2 0H Co
61. 0 through P107 Note The flash memory capacity is set to 60K bytes by RESET input Caution The flash memory model and mask ROM model differ in terms of noise immunity When replacing a flash memory model with a mask ROM model in the course of experimental production to mass production make a thorough evaluation with a C8 model not ES model of the mask ROM model 175 CHAPTER 15 4PD78F0228 15 1 Memory Size Select Register The uPD78F0228 can select the internal memory capacities by using the memory size select register IMS By setting IMS the memory mapping of the uPD78F0228 be made the same as that of a mask ROM model with different internal memory capacities To make the memory map of the uPD78F0228 the same as that of a mask ROM model set IMS as shown in Table 15 2 IMS is set by using an 8 bit memory manipulation instruction The value of this register is set to CCH by RESET input Figure 15 1 Memory Size Select Register Format Symbol 7 Address At Reset R W 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAMO 9 ROM3 Rome ROM ROMO FFFOH CCH R W Selects internal high speed RAM capacity 1 1024 bytes Others Setting prohibited Selects internal ROM capacity 48K bytes 60K bytes Others Setting prohibited Caution When using a mask ROM model do not set a value other than those shown in Table 15 2 to IMS Table 15 2 Set Value of Memory Size Select Register Part Number Set Val
62. 1 WDCSO Overflow time of watchdog timer interval timer 0 0 0 2 fx 819 us 0 0 1 213 1 64 ms 0 1 0 214 3 28 1 0 1 2 7 fx 26 2 ms 1 1 0 2 8 fx 52 4 ms 1 1 1 2204 210 ms Remarks 1 fx Main system clock oscillation frequency 2 5 0 MHz 104 CHAPTER 8 WATCHDOG TIMER 3 Watchdog timer mode register WDTM This register selects the operation mode of the watchdog timer and enables or disables the counting operation It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to OOH by RESET input Figure 8 4 Watchdog Timer Mode Register Format Symbol lt 7 gt 6 5 4 3 2 1 0 Address R W RUN Selects operation of watchdog timer te 1 0 Stops counting 1 Clears counter and starts counting Selects operation mode of watchdog timerNote 2 Interval timer mode Maskable interrupt request occurs when overflow occurs Watchdog timer mode 1 Non maskable interrupt request occurs when overflow occurs Watchdog timer mode 2 Reset operation is started when overflow occurs Notes 1 The RUN bit cannot be cleared to 0 by software once it has been set Therefore counting cannot be stopped after it has been started by any means other than RESET input 2 The WDTM3 and WDTM4 bits cannot be cleared to 0 by software once they have been set Caution When the RUN bit is set to 1 and the watchdog timer i
63. 10 D 6 0 0 236 d 16 57 0 652 E 23 75 0 935 e 17 57 0 692 F 7 0 0 276 f 0 5 0 020 G 0 65x29 18 85 0 026x1 142 0 742 g 3 9 0 154 H 23 9 0 941 h 2 8 0 091 30 25 1 191 i 12 0 047 J 0 65 0 026 j 34 0 122 K 3 01 0 3 00 039 k 7 4 0 291 L C 2 0 C 0 079 HQPACK100RB G0E M 3 R 2 5 3 R 0 098 N 4 02 2 4 0 087 141 0 555 P 24 07 0 948 Q 23 07 0 908 R 0 5 0 020 S 0 5 0 020 T 16 57 0 652 U 17 57 0 692 V 0 5 0 020 w 0 5 0 020 x 20 1 0 791 Y 0 2 0 008 2 1 5 0 059 Remark Manufactured by Tokyo Eletech Corp 208 APPENDIX DEVELOPMENT TOOLS Figure 4 YQPACK100RB Probe Side Package Drawings Reference ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 17 4 0 685 a 0 4 0 685 B 0 65x19 12 35 0 026 0 748 0 486 b 0 4 0 026 0 65 0 026 14 75 0 748 D 6 0 0 236 d 15 55 0 486 E 16 85 0 663 e 0 4 0 016 F 19 25 0 758 D 0 4 0 016 G 21 65 0 852 9 20 1 0 791 H 24 05 0 947 h 0 2 0 008 I 10 35 0 407 i C 1 5 C 0 059 J 12 75 0 502 j 0 3 0 012 K 15 15 0 596 k 0 25x0 3 0 010x0 012 L 17 55 0 691 I 9 0 0 354 M 23 75 0 935 m 2 2 0 087 N 0 65x29 18 85 0026 1142 0742 n 3 1 0 122 o 2
64. 16 patterns 134 11 7 Leakage Emission Because of Short Blanking Time 136 11 8 Leakage Emission Caused by GSG recen etai no ee ert veta spa ovde 11 9 Leakage Emission Caused by N 11 10 Total Power Dissipation Pr TA 40 to 85 11 11 Relationship between Display Data Memory and FIP Output with 10 Segments 11 Digits Displayed 141 vii LIST OF FIGURES 3 3 Figure No Title Page 12 1 Basic Configuration of Interrupt Function 145 12 2 Interrupt Request Flag Register 148 12 3 Interrupt Mask Flag Register Format 12 4 Priority Specify Flag Register 12 5 External Interrupt Rising Edge Enable Register Format 12 6 External Interrupt Falling Edge Enable Register Format 12 7 Program Status Word Configuration I 12 8 Flowchart of Occurrence and Acknowledge Non Maskable Interrupt 154 12 9 Non Maskable Interrupt Request Acknowledge Timing 12 10 Non Maskable Interrupt Request Acknowledge Operation 12 11 Interrupt Request Acknowledge Processing Algorithm sss 12 18 Interrupt Request Acknowledge Timing Maximum Time 7 12 12 Interrupt Request Acknowledge Timing Minimum Time sssssse na 12 14 Multiple Interrupt
65. 2 gives a listing of interrupt request flags interrupt mask flags and priority specify flag names corresponding to interrupt request sources Table 12 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Request Source NTWDT NTPO NTP1 NTTM10 NTTM11 NTKS NTCSI3 50 Interrupt Request Flag WDTIFNote PIFO PIF1 TMIF10 TMIF11 KSIF CSIIF3 TMIF50 Register Interrupt Mask Flag WDTMKNete PMKO PMK1 TMMK10 TMMK11 KSMK CSIMK3 TMMK50 Register Priority Specify Flag WDTPRNete PPRO PPR1 TMPR10 TMPR11 KSPR CSIPR3 50 Register 51 NTAD TMIF51 ADIF 51 ADMK 51 ADPR Note The WDTIF WDTMK and WDTPR flags are interrupt control flags used when the watchdog timer is used as an interval timer 147 CHAPTER 12 INTERRUPT FUNCTIONS 1 Interrupt request flag registers IFOL and IFOH The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL and IFOH are set with a 1 bit or 8 bit memory manipulation instruction When IFOL and IFOH are used in combination as a 16 bit register IFO they are set with a 16 bit memory operation instruction RESET input sets these registers to 00H Figure 12 2 Interrupt Request Fl
66. 205 for IBMi PC iere ener cereo sce ses Pee Saa Pae Eaa Ya a YAE Saa Vaa aa a Ni 206 APPENDIX C EMBEDDED SOFTWARE 0 0 ce tsccecssececcesteseeeseeceerensesteesoeseerentecteessrenerennentersorsae 211 C 1 Real time OS 2 2 212 C 2 Fuzzy Inference Development Support System u 214 APPENDIX D REGISTER INDEX nnn nennt uu u u uu uu u uu uu u tnnt 215 0 1 Regist r Index a T S a a 215 x APPENDIX E REVISION HISTORY manm usnm 217 LIST OF FIGURES 1 3 Figure No Title Page 2 1 Pin Input Output Circuit Mist be ede ka 17 3 1 Memory Map uPD780226 uu u pt et rte teg tede ree bed deitas 19 3 2 Memory Map uPD780228 ird rte etr queant e e P Detur 20 3 3 M mory Map uPD78E0228B irent rete egets age id ce d dte diced 21 3 4 Addressing of Data Memory 0780226 25 3 5 Addressing of Data Memory 0780228 26 3 6 Addressing of Data Memory 78 0228 2 27 3 7 Program Counter
67. 3 9 0 941 3 7 0 146 30 25 1 191 2 5 0 098 Q 0 65 0 026 q 0 25 0 010 R 7 0 0 276 14 75 0 581 S 0 25 0 010 s 15 55 0 612 T 3 1 0 3 0 039 t 0 4 0 016 U C 2 0 0 079 u 7 4 0 291 3 R 2 5 3 R 0 098 3 9 0 154 w 4 02 2 4 00 087 w 23 0 091 x 14 1 0 555 x 1 2 0 047 Y 21 25 0 837 YQPACK100RB G0E 2 22 05 0 868 Remark Manufactured by Tokyo Eletech Corp 209 210 APPENDIX EMBEDDED SOFTWARE For efficient program development and maintenance of the PD780228 subseries the following embedded software products are available 211 C 1 Real time OS 1 2 APPENDIX C EMBEDDED SOFTWARE RX78K 0 RX78K 0 is a real time OS which is based on the specification Real time OS Supplied with the RX78K 0 nucleus and a tool to prepare multiple information tables configurator Used in combination with optional assembler package RA78K 0 and device file DF780228 Part Number uSxxxxRX78013 A A A A Caution When purchasing the 78 0 fill in the purchase application form in advance and sign the User Agreement Remark and A A A in the part number differs depending on host machine and OS etc LSxxxxRX78013 A A A A Evaluation object Product Outline Maximum Number for Use in Mass Production Do not use for mass produced product Mass production object 100 000 1 000 000 10 000 000 212 Source program Host Machine PC 9800
68. 5 3 External Circuit of Main System Clock Oscillator a Crystal or ceramic oscillation b External clock External clock 1 uPD74HCUO4 2 Crystal or ceramic resonator Cautions 1 The STOP mode cannot be set when the external clock is input This is because the X2 pin is pulled up by 2 When using a main system clock oscillator carry out wiring in the broken line area in Figure 5 3 as follows to prevent any effects from wiring capacities Minimize the wiring length Donotallow wiring to intersect with other signal conductors Do not allow wiring to come near abruptly changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vssi Do not ground to any ground pattern where high current is present Do not fetch signals from the oscillator Figure 5 4 shows examples of resonator having bad connection 71 CHAPTER 5 CLOCK GENERATOR Figure 5 4 Examples of Resonator with Bad Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines amp PORTn 0 2 4 10 c High alternating current close to d Current flowing through ground line signal lines of oscillator circuit potentials at points A B and C change High current igh current 72 CHAPTER 5 CLOCK GENERATOR Figure 5 4 Examples of Resonator with Bad Connection 2 2 e Signal extracted 5 4 2 Divid
69. 8 Mask Option The mask ROM models uPD780226 and 780228 have mask options By specifying the mask options when placing an order for these models the pull up and pull down resistors shown in Table 1 1 can be connected If these mask options are used when pull up and pull down resistors are necessary the number of components can be decreased and the mounting area can be reduced Table 1 1 shows the mask options available for the uPD780228 subseries Table 1 1 Mask Options of Mask ROM Models P50 P57 P60 P67 Pull up resistors can be connected in 1 bit units P70 FIP16 P77 FIP23 Pull down resistors can be connected in 1 bit units P80 FIP24 P87 FIP31 P90 FIP32 P97 FIP39 100 40 107 47 CHAPTER 2 PIN FUNCTIONS 2 1 Pin Function List 1 Port pins 1 2 Pin Name 1 Function Port 0 2 bit I O port Can be set in input or output mode in 1 bit units Internal pull up resistor can be used via software when this port is used as input port At Reset Shared with P10 P17 Port 1 8 bit input port ANIO ANI7 P20 P25 Port 2 6 bit 1 port Can be set in input or output mode in 1 bit units Internal pull up resistor can be used via software when this port is used as input port SCK P40 P47 Port 4 8 bit I O port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor be used via software when this port is
70. 8 bit high voltage output port Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however FIP40 FIP47 CHAPTER 4 PORT FUNCTIONS 4 2 Port Configuration A port consists of the following hardware Table 4 2 Port Configuration Item Configuration Control register Port mode register PMm m 0 2 4 6 Pull up resistor option register PUn n 0 2 4 Port Total 72 8 inputs 8 outputs 56 inputs outputs Pull up resistor Mask ROM model Total 32 software control 16 mask option control 16 uPD78F0228 Total 16 Pull down resistor Mask ROM product Total 32 mask option control 32 uPD78F0228 None 4 2 1 Port 0 Port 0 is a 2 bit input output port with output latch POO and 01 pins can specify the input mode output mode 1 bit units with the port mode register 0 When and P01 pins are used as input ports an on chip pull up resistor can be connected to them in 1 bit units with a pull up resistor option register 0 PUO Alternate functions include external interrupt request input RESET input sets port 0 to input mode Figure 4 2 shows a block diagram of port 0 Caution Because port 0 also serves for external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set
71. A P LY LLL cele 0 1 2 3 4 5 6 7 8 9 10 141 142 CHAPTER 12 INTERRUPT FUNCTIONS 12 1 Interrupt Function Types The following three types of interrupt functions are used 1 Non maskable interrupt 2 3 This interrupt is acknowledged unconditionally even in a disabled state It does not undergo interrupt priority control and is given top priority over all other interrupt requests It generates a standby release signal One interrupt request source from the watchdog timer is incorporated as a non maskable interrupt Maskable interrupts These interrupts undergo mask control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PROL and PROH Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 12 1 A standby release signal is generated Four external interrupt request sources and six internal interrupt request sources are incorporated as maskable interrupts Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction It is acknowledged even ina disabled state The software interrupt does not undergo interrupt priority control 143 CHAPTER 12 INTERRUPT FUNCTIONS 12 2 Interrupt Sources and Conf
72. ALT instruction The operating status in the HALT mode is described below Table 13 1 HALT Mode Operating Status Item Operating status Clock Generator Oscillation enabled Clock supply to the CPU stops CPU Operation stop Port output latch Status before HALT instruction execution is held 8 bit remote control timer Operation enabled 8 bit PWM timer Watchdog timer A D converter Serial interface FIP controller driver Operation disabled External interrupt request Operation enabled 165 CHAPTER 13 STANDBY FUNCTION 2 HALT mode clear The HALT mode can be cleared with the following three types of sources a Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode If interrupt request acknowledge is enabled vectored interrupt service is carried out If disabled the next address instruction is executed Figure 13 2 HALT Mode Clear upon Interrupt Request Generation HALT Instruction Standby Release Signal HALT Mode Operating Mode Mode gt Operating Clock Oscillation Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt r
73. AM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 189 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Operation Group SP 1 lt PC 3 H laddr16 SP 2 lt PC 3 L PC lt adadr16 SP e SP 2 SP 1 lt PC 2 H laddr11 SP 2 lt PC 2 L PC15 11 00001 10 0 lt addr11 SP lt SP 2 SP 1 PC 1 SP 2 PC 1 L Call addr5 PCH 00000000 addr5 1 PCL 00000000 addr5 SP lt SP 2 SP 1 lt PSW SP 2 lt PC 1 SP 3 PC 1 L PCH lt 003FH PCL lt 003EH SP SP 3 IE 0 PCH lt SP 1 PCL SP SP SP 2 PCH lt SP 1 PCL lt SP PSW lt SP 2 SP SP 3 NMIS 0 PCH lt SP 1 PCL lt SP PSW lt SP 2 SP lt SP 3 SP 1 lt PSW SP lt SP 1 SP 1 e SP 2 lt SP SP 2 PSW lt SP SP lt SP 1 lt SP 1 rp lt SP SP SP 2 SP word SP word SP AX SP AX AX SP AX lt SP laddr16 PC lt addr16 x return rp Unconditional branch addr16 PC lt PC 2 jdisp8 AX PCH A PCLe X addr16 PC PC 2 jdisp8 if CY 1 ad
74. CONVERTER Noise measures To maintain the 8 bit resolution care must be exercised that no noise is superimposed on the AVop and ANIO through ANI7 pins The higher the output impedance of the analog input source the heavier the influence of noise To suppress noise connecting external C as shown in Figure 9 8 is recommended Figure 9 8 Processing of Analog Input Pin Clamp with diode with low Vr 0 3 V or less if there is possibility that noise greater than AVop and less than AVss is superimposed C 100 1000 pF ANIO through ANI7 The analog input pins ANIO through ANI7 are multiplexed with port pins P10 through P17 When one of ANIO through ANI7 is selected for A D conversion do not execute an instruction that inputs data to the port during the conversion If such an instruction is executed the conversion resolution may drop When a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion the expected A D conversion value may not be obtained because of coupling noise Therefore do not apply a pulse to the pins adjacent to the analog input pins during A D conversion Input impedance of AVpp A series resistor string with a resistance of about 24 7 kQ is connected between the AVpp and AVss pins If the output impedance of the reference voltage source is high therefore the impedance is virtually connected in parallel with the resistor string between the and AVss pins incr
75. Configuration 2 28 3 8 Program Status Word Configuration 2 L nea 28 3 9 Stack Pointer Configuration eee atten ee pen a ee e detis 29 3 10 ata to be Saved to Stack Memory L 30 3 11 Data to be Restored from Stack Memory 30 3 12 General Register Configuration iet ene n ded nid e dex nere asua 31 4 1 IM cp esto eta el tiie a lea 49 4 2 POO and P01 Block DISgrar eie rtt mide eager iae i er tie ine e ke dent 52 4 3 P10 to P 17 Block Diagram reete erede e de De e ete D Eee tis a ETE Rn 53 4 4 P20 sioe DI Te rz em 54 4 5 21 10 25 cette tet eer ree nq ta tae een e e decide 55 4 6 P40 to p47 BlockDiagram is e enm PRO E i ets 56 4 7 B50 to P57 Block Diagram ca mas e TERIS irate e 57 4 8 P56 to P58 Block Diagram 2 so n tpe ce enti em e e e dr car tei re tec a eene 58 4 9 P70 to P77 BIOCk DIAagratm 2 perte ie ne e ere i rte Dara etl 59 4 10 P80 to P87 Block Diagrami ua one neuter ptite 60 4 11 P90 to P97 Block Diagram ei rere t ee rette n dep eterne 61 4 12 P100 to P107 Block Diagram treten teer ted ne tet ie dan 62 4 13 Port Mode Register Format Ge ae ti o rede e edid 64 4 14 Pull Up Resistor Option Register 65 5 1 Block Diagram o
76. E U11802J Assembly Language U11801E 011801 Structured Assembly U11789E U11789J Language CC78K Series C Compiler Operation EEU 1280 EEU 656 Language EEU 1284 EEU 655 CC78KO C Compiler Operation U11517E U11517J Language U11518E U11518J CC78K Series Library Source File U12322J CC78K Compiler Application Note Programming Know how EEA 1208 EEA 618 IE 78001 R A Planned Planned 78 0 51 01 Planned IE 780228 SL EM4 Planned Planned EP 100GF SL Planned Planned SM78KO System Simulator Windows Base Reference U10181E U10181J SM78K Series System Simulator External Components User U10092E U10092J Open Interface Specifications 78 0 Integrated Debugger EWS base Reference 011151 ID78K0 Integrated Debugger base Reference U11539E U11539J 1D78K0 Integrated Debugger Windows base Guide U11649E U11649J Caution The contents of the above documents are subject to change without notice Be sure to use the latest edition for designing e Documents related to embedded software User s Manual Document Name Document Number English Japanese 78K 0 Series Real time OS Fundamental U11537J Installation U11536J 78K 0 Series OS 78 0 Fundamental U12257J Fuzzy Knowledge Data Creation Tool EEU 1438 EEU 829 78 0 78K Il 87AD Series Fuzzy Inference Development Support System Translator EEU 1444 EEU 862 78K 0 Series Fuzz
77. ETI instruction for returning from the software interrupt 158 CHAPTER 12 INTERRUPT FUNCTIONS 12 4 4 Multiple interrupt servicing Acknowledging another interrupt while one interrupt is processed is called multiple interrupts A multiple interrupt is not generated unless acknowledge of the interrupt request is enabled IE 1 except the non maskable interrupt When an interrupt request is acknowledged the other interrupt requests are disabled IE 0 To enable a multiple interrupt therefore the IE flag must be set to 1 by executing the El instruction during interrupt servicing and the interrupt must be enabled Even in the El status a multiple interrupt may not be enabled In such a case it is controlled according to the priority of the interrupt An interrupt has two types of priorities default priority and programmable priority The multiple interrupt is controlled by the programmable priority In the El status if an interrupt request having the same as or higher priority than that of the interrupt currently processed is generated and it is acknowledged as the multiple interrupt If an interrupt request with a priority lower than that of the interrupt currently processed is generated the multiple interrupt is not acknowledged If an interrupt is disabled or if a multiple interrupt is not acknowledged because it has a low priority the interrupt is kept pending After the processing of the current interrupt has been completed and after
78. F0228 has no pull down resistor In addition FIP controller driver output is provided as an alternate function RESET input sets port 7 to input mode Figure 4 9 shows a block diagram of port 7 Figure 4 9 P70 to P77 Block Diagram Port read PLR70 PLR77 Output latch P70 P77 Alternate function Internal bus P70 FIP16 P77 FIP23 L 0770 O Mask Option Mask ROM model only uPD78F0228 has pull down resistor RD Port 7 read signal WR Port 7 write signal 59 CHAPTER 4 PORT FUNCTIONS 4 2 8 Port 8 Port 8 is an 8 bit input output port with output latch When using this port as an output port the value assigned to the output latch P80 through P87 is output When it is used as an input port set the output latch P80 through P87 to 0 and read the port read PLR80 through PLR87 On chip pull down resistors can be connected in 1 bit units with the mask option The uPD78F0228 has no pull down resistor In addition FIP controller driver output is provided as an alternate function RESET input sets port 8 to input mode Figure 4 10 shows a block diagram of port 8 Figure 4 10 P80 to P87 Block Diagram C Port read PLR80 PLR87 Output latch P80 P87 Alternate function Internal bus P80 FIP24 P87 FIP31 oo O Mask Option Mask ROM model only 78 0228 has pull down resist
79. F0228 has no pull up resistor Port 6 can drive LEDs directly RESET input sets port 6 to input mode Figure 4 8 shows a block diagram of port 6 Caution Low level input leak current in P60 to P67 pins differs depending on the following conditions Mask ROM model O When pull up resistors are contained always 3 Max O When pull up resistors are not contained 1 clock interval when read instruction is executed to port 6 P6 and port mode register 6 PM6 200 uA Max Other than above 3 Max Flash memory model 1clock interval when read instruction is executed to port 6 P6 and port mode register 6 PM6 200 uA Max Other than above 3 uA Max Figure 4 8 P60 to P67 Block Diagram Mask Option Mask ROM model _ 78 0228 has no Selector pull up resistor gt i P60 P67 Output latch P60 P67 Internal bus 60 to PM67 PM Port mode register RD Port 6 read signal WR Port 6 write signal 58 CHAPTER 4 PORT FUNCTIONS 4 2 7 Port 7 Port 7 is an 8 bit input output port with output latch When using this port as an output port the value assigned to the output latch P70 through P77 is output When it is used as an input port set the output latch P70 through P77 to 0 and read the port read PLR70 through PLR77 On chip pull down resistors can be connected in 1 bit units with the mask option The uPD78
80. LK2 FBLK1 FBLKO FPAT4 2 FPAT1 FPATO FF91H 01H R W Blanking width of FIP output signal Number of display patterns o Q c Ns A 12 13 14 15 0 16 Others Setting prohibited ocoj ojojojojojojojoj joj joijo jo Caution Do not write data to the display mode register 1 DSPM1 when bit 7 DSPEN of the display mode register 0 DSPMO is 1 131 CHAPTER 11 FIP CONTROLLER DRIVER 3 Display mode register 2 DSPM2 Symbol 5 4 3 2 1 0 o 132 DSPM2 performs the following setting It also indicates the status of the display timing key scan Insertion of key scan timing Display cycle TDSP DSPMe is set by using a 1 bit or 8 bit memory manipulation instruction However only bit 7 KSF can be read by a 1 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input Figure 11 4 Display Mode Register Format T7 6 Address R W KSF Status of key scan cycle 0 Other than key scan cycle 1 Key scan cycle KSM Selects insertion of key scan cycle 1 0 Not inserted Inserted Display cycle 2 fx 819 2 us 2 fx 409 6 us 2 9 fx 204 8 us Setting prohibited Cautions 1 Be sure to set bits 2 through 5 to 0 2 Do not write data to the
81. MO This register specifies the conversion time of the input analog signal to be converted and starts or stops the conversion operation It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input Figure 9 2 A D Converter Mode Register Format Symbol 7 6 Address At Reset R W 5 4 3 2 1 0 cso o Few o o o AW 50 Control A D conversion operation 0 Stops conversion 1 Enables conversion Selects A D conversion timeNoete 1 fx 5 0 MHz fx 4 19 MHz 144 fx 28 8 us 144 fx 34 4 us 120 fx 24 us 120 fx 28 6 us 96 fx 19 2 us 96 fx 22 9 us 72 fx 14 4 us 72 fx 17 2 us 60 fx setting prohibitedNote 2 60 fx 14 3 us 1 48 fx setting prohibitedNote 2 48 fx setting prohibitedNote 2 Others Setting prohibited Notes 1 Make sure that the A D conversion time is 14 us or longer 2 These settings are prohibited because the A D conversion time is less than 14 us Caution The conversion result is undefined immediately after bit 7 CS0 has been set Remark fx Main system clock oscillation frequency 112 CHAPTER 9 A D CONVERTER 2 Analog input channel specification register ADSO This register specifies a port that inputs the analog voltage to be converted It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initial
82. Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Lid Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 719 2377 Fax 02 719 5951 NEC do Brasil S A Sao Paulo SP Brasil Tel 011 889 1680 Fax 011 889 1689 J96 8 Readers Purpose Organization PREFACE This manual has been prepared for user engineers who understand the functions of theu PD780228 subseries and design and develop its application systems and programs This manual is intended for the users to understand the functions described in the Organization section below The uPD780228 subseries manual is separated into two parts this manual and Instructions common to the 78K 0 series uPD780228 Subseries 78K 0 Series User s Manual User s Manual This manua
83. Programming ua ass 173 15 31 Selecting communication mode nee tette reden 173 15 3 2 Function of flash memory 179 15 3 3 Connection of Flashpro 180 CHAPTER 16 INSTRUCTION SET U a ua a a 181 16 1 Legend sassa 182 16 1 1 Operand identifiers and description methods 182 16 1 2 Description of operation column 16 1 3 Description of flag operation column 16 2 Operation List 16 3 Instructions Listed by Addressing Type APPENDIX A DIFFERENCES BETWEEN 4 PD78044H 780228 AND 780208 SUBSERIES 197 APPENDIX B DEVELOPMENT TOOLS 199 B 1 Language Processing Software 201 B 2 Flash Memory Writing Tools 22 4 4 4 1 1 202 B 3 Debugging Tools Bas bo bardWaret oe dd aen 203 B 3 2 5S OftWaIO Werde aged pede nee Ee ede Renee deua sassa Q 204 Bid
84. RESET input Figure 7 2 Format of Timer Clock Select Register Symbol 7 Address At Reset R W Brien TRE TOLSma TOLS TOLSo FF79H TCL51 0 fx 22 1 25 MHz fx 24 313 kHz fx 28 78 1 kHz fx 28 19 5 kHz 1x 210 4 9 kHz Cautions 1 When rewriting the data of TCL5n once stop the timer operation 2 Be sure to clear bits 3 through 7 to 0 Remarks 1 The setting by TCL5n2 through TCL5n0 except that for the low order timer is invalid in the cascade mode 2 n Oor1 3 fx Main system clock oscillation frequency 4 fx 5 0 MHz 86 CHAPTER 7 8 BIT PWM TIMERS 2 8 bit timer mode control register 5n TMC5n n 0 or 1 TMC85n sets has the following six functions lt gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt Controls count operation of 8 bit counter 5n 5 n 0 or 1 Selects operation mode of 8 bit counter 5n TM5n n 0 or 1 Selects single or cascade mode Sets status of timer output F F flip flop Controls timer F F or selects active level in PWM free running mode Controls timer output 5 is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to 04H by RESET input 87 CHAPTER 7 8 BIT PWM TIMERS Figure 7 3 Format of 8 Bit Timer Control Register 5n Symbol lt 7 gt 6 5 4 lt 3 gt lt 2 gt 1 0 Address At Reset R W TMC5n 5 TMC5n6 o 5 LVS5n LVR5n
85. ROM Models and 78 0228 Pin Name Mask Option of Mask ROM Model 78 0228 50 57 Pull up resistor be connected Pull up resistor is not provided P60 P67 in 1 bit units P70 FIP16 P77 FIP23 Pull down resistor can be connected Pull down resistor is not provided P80 FIP24 P87 FIP31 in 1 bit units P90 FIP32 P97 FIP39 P100 FIP40 P107 FIP47 68 CHAPTER 5 CLOCK GENERATOR 5 1 Clock Generator Functions The clock generator generates clock to be supplied to the CPU and peripheral hardware The following type of system clock oscillators is available Main system clock oscillator This circuit oscillates at frequencies of 5 0 MHz Oscillation can be stopped by executing the STOP instruction 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Generator Configuration Control register Processor clock control register PCC Oscillator Main system clock oscillator Clock Generation Circuit Block Diagram mam Clock to peripheral hardware Standby _ CPU clock fceu control circuit Figure 5 1 Main system Prescaler fx Selector Selector Processor clock control register ES Internal bus 69 CHAPTER 5 CLOCK GENERATOR 5 3 Register Controlling Clock Generation Circuit The clock generation circuit is controlled by the processor
86. SUBW CMPW PUSH POP INCW DECW Second Operand I laddr16 First Operand M OVWNote sfrp saddrp laddr16 SP Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand sfr bit saddr bit PSW bit HL bit addr16 First Operand sfr bit saddr bit PSW bit HL bit 194 CHAPTER 16 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand laddr16 laddri1 addr5 addr16 First Operand Basic instruction CALLT Compound instruciton 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 195 196 APPENDIX A DIFFERENCES BETWEEN 7804 780228 AND 780208 SUBSERIES Table A 1 shows the major differences between the uPD78044H 780228 and 780208 subseries Table A 1 Major Differences between uPD78044H 780226 and 780208 Subseries Er Part Number PROM or flash memory model uPD78044H Subseries uPD78P048B PROM 0780228 Subseries uPD78F0228 flash memory uPD780208 Subseries uPD78P0208 PROM Supply voltage 2 7 to 5 5 V Voo 4 5 to 5 5 V Voo 2 7 to 5 5 V Internal ROM size Internal expansion RAM size LPD78044H 32K bytes LPD78045H 40K b
87. SW PSW A e MOV1 PSW bit CY MOV1 CY PSW bit e AND1 CY PSW bit OR1 CY PSW bit e XOR1 CY PSW bit SET1 PSW bit e CLR1 PSW bit RETB RETI PUSH PSW PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 El DI Manipulation instructions for IFOL IFOH MKOL MKOH PROL PROH and INTMO registers Caution The BRK instruction is not included in the above list of instructions The software interrupt that is started by execution of the BRK instruction however clears the IE flag to 0 Therefore even if a maskable interrupt request is generated while the BRK instruction is being executed the interrupt request is not accepted However a non maskable interrupt request is accepted Figure 12 15 shows the timing at which an interrupt request is reserved Figure 12 15 Interrupt Request Reserve 5 PSW and PC Save Jump to Interrupt Servicing CPU Processing Instruction N Instruction M Interrupt Servicing Program xxIF Remarks 1 Instruction N Interrupt request reserve instruction 2 Instruction M Instruction except interrupt request reserve instructions 3 Operation of xxIF interrupt request is not effected by xxPR priority level value 162 CHAPTER 13 STANDBY FUNCTION 13 1 Standby Function and Configuration 13 1 1 Standby function The standby function is intended to decrease the power consumption of the system The following two modes are available
88. The following two operations are available to generate the reset signal 1 External reset input with RESET pin 2 Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status as shown in Table 14 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 21 fx The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 216 fx see Figures 14 2 to 14 4 Cautions 1 For an external reset input a low level for 10 us or more to the RESET pin 2 When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pin becomes high impedance Figure 14 1 Block Diagram of Reset Function RESET Reset Control Circuit Count Clock Watchdog Timer Reset Signal Interrupt Function 171 CHAPTER 14 RESET FUNCTION Figure 14 2 Timing of Reset Input by RESET Input
89. User s Manual 780228 Subseries 8 bit Single chip Microcontroller uPD780226 uPD780228 uPD78F0228 Document No U12012EJ2VOUMOO 2nd edition Date Published June 1997 N Printed in Japan Corporation 1997 Printed in Japan NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behav
90. a edoae aa asra Ee Aa daga Aea daea as 101 8 1 Function of Watchdog Timer 101 8 2 Configuration of Watchdog Timer s snin a ed aaas 102 8 3 Registers Controlling Watchdog Timer eese u uuu u 103 8 4 Operation of Watchdog Timer 106 8 4 1 Operation as watchdog 8 106 8 4 2 Operation as interval timer CHAPTER 9 A D CONVERTER 9 1 Function of A D Converter 9 2 Configuration of A D Converter U U nnne nnn nnns nnne 109 9 3 Registers Controlling A D Converter eese nnn nnn 112 9 4 Operation of A D Converter III I asss 114 9 4 1 Basic operation of A D converter 114 9 4 2 Input voltage and conversion 116 9 4 3 Operation mode of A D converter 117 9 5 Notes On A D Converter uuu 118 CHAPTER 10 SERIAL INTEREAGE niei ette idee rti 121 10 1 Function of Serial Interface sten nnne 121 10 2 Configuration of Serial Interface U eene u nnne nnne nnne 121 10 3 Registers Controlling Serial Interface u uu uu nennen 123 10 4 Operation of Serial Interface
91. abled Serial function port function Transfer operation mode flag Operation mode Transfer start trigger SO output Transmission or transmission SIO3 write Normal output reception mode Reception mode SIO3 read Fixed to low level Selects clock External clock input to SCK pin fx 23 625 kHz fx 24 313 kHz 25 156 kHz Note The pins connected to SI SO and SCK can be used as port pins when CSIE3 0 when the SIO3 operation is stopped Remarks 1 fx Main system clock oscillation frequency 2 fx 5 0 MHz 125 CHAPTER 10 SERIAL INTERFACE 2 Communication operation In the three wire serial I O mode data is transmitted or received in 8 bit units Each bit of the data is transmitted or received in synchronization with the serial clock The shift operation of the serial I O shift register 3 5103 is performed in synchronization with the falling of the serial clock SCK The transmit data is retained by the SO latch and output from the SO pin At the rising edge of SCK the receive data input to the SI pin is latched to SIO3 When transfer of 8 bit data has been completed SIO3 automatically stops its operation and an interrupt request flag CSIIF3 is set Figure 10 3 Timing in Three Wire Serial I O Mode SCK 1 2 3 4 5 6 7 8 si X Di Die X Dis X Di4 pis X Dit Dio L 1 50 007 X DOs f pos po4 Dos po2 1 l CSIIF3 Transfer completed T
92. ag Register Format Symbol lt gt lt 6 gt 5 4 lt 3 gt lt 2 gt 1 0 Address At Reset R W IFOL TMIF50 CSIIF3 KSIF TMIF11 TMIF10 PIF1 PIFO WDTIF FFEOH 00H R W 4 3 2 lt 1 gt lt 7 6 5 0 gt EGUEREE SES ADIF TMIF51 FFE1H 00H R W Interrupt Request Flag 0 No interrupt request signal 1 Interrupt request signal is generated Interrupt request state Cautions 1 WDTIF flag is R W enabled only when a watchdog timer is used as an interval timer If a watchdog timer is used in watchdog timer mode 1 set WDTIF flag to 0 2 Be sure to set bits 2 through 7 of to 0 148 CHAPTER 12 INTERRUPT FUNCTIONS 2 Interrupt mask flag registers MKOL and MKOH The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MKOL and MKOH are set with a 1 bit or 8 bit memory manipulation instruction When MKOL and MKOH are used in combination as a 16 bit register MKO they are set with a 16 bit memory operation instruction RESET input sets these registers to FFH Figure 12 3 Interrupt Mask Flag Register Format Symbol lt 7 gt lt 6 lt 4 lt 3 lt 0 gt Address At Reset R W gt lt 5 gt gt gt lt 2 gt lt gt MKOL TMMK50 CSIMK3 KSMK 11 10 PMK1 PMKO WDTMK FFE4H FFH R W 7 6 5 4 3 2 lt 1 gt lt 0 gt FFE5H FFH R W Interrupt Serving and Standby Mode Control
93. ain system clock oscillation frequency 2 fx 5 0 MHz 106 CHAPTER 8 WATCHDOG TIMER 8 4 2 Operation as interval timer The watchdog timer operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance if bit 4 WDTM4 of the watchdog timer mode register WDTM is cleared to 0 The count clock interval time can be selected by bits 0 through 2 WDCSO through WDCS2 of the watchdog timer clock select register WDCS By setting bit 7 RUN of WDTM to 1 the watchdog timer starts interval timer operation While the watchdog timer is operating as an interval timer the interrupt mask flag TMMK4 and priority specification flag TMPR4 are valid and a maskable interrupt INTWDT can be generated The default priority of INTWDT is the highest of all the maskable interrupts The interval timer continues operating in the HALT mode but stops in the STOP mode Therefore set RUN and clear the interval timer before executing the STOP instruction to set the STOP mode Cautions 1 If bit 4 WDTM4 of WDTM has been set to 1 once to select the watchdog timer mode the interval timer mode cannot be set unless the RESET signal is input 2 The interval time immediately after WDTM has been set may be up to 0 5 shorter than the set time Table 8 5 Interval Time of Interval Timer Interval Time x 819 us 1 64 ms x 3 28 ms x 6 55 ms 13 1 ms x x
94. apped to this area The special function registers SFRs are mapped to the area from addresses FFOOH to FF1FH If the SFR area FFOOH to FF1FH where short direct addressing is applied ports which are frequently accessed in a program and a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Refer to Illustration on the next page Operand format saddr Label or FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data even address only CHAPTER 3 CPU ARCHITECTURE Description example MOV 50H when setting saddr to FE30H and immediate data to 50H Operation code 0 0 1 1 OPcode 0 0 1 1 0 0 O0 30H saddr to offset 0 1 0 1 0 0 0 0 50H immediate data Illustration OP code saddr offset Short Direct Memory 15 8 0 essen TTT ae id When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is to 1FH 1 43 CHAPTER 3 CPU ARCHITECTURE 3 4 5 Special function register SFR addressing Function The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte
95. apter Adapter necessary for using the PC 9800 series excluding the notebook type as the host machine of the IE 78001 R A Adapter and cable necessary for using a PC 9800 series notebook type computer as the host machine of the IE 78001 R A This adapter cannot be connected unless the connector of the expansion bus of the notebook type computer is of 110 pin type 70000 Interface adapter Adapter necessary for using an IBM PC AT or compatible machine as the host machine of the IE 78001 R A IE 78K0 SL P01Note board This board is used to emulate device specific hardware It is used with an in circuit emulator and probe board IE 780228 SL EM4Note Probe board This board is used to set mask option and converts pin connector EP 100GF SL Emulation probe NQPACK100RB conversion socket YQPACK100RB conversion adapter This probe connects an in circuit emulator and the target system It is for a 100 pin plastic QFP GF 3BA type A 100 pin conversion socket NQPACK100RB and a conversion adapter YQPACK100RB which facilitates development of the target system are also supplied This conversion socket is used to connect the board of the target system that is designed to mount 100 plastic GF 3BA type and the EP100GF SL To connect the EP 100GF SL this socket is used with YOPACK100RB Instead of connecting EP 100GF SL a device can be mounted This is a conversion adapt
96. area 0000H 0000H 19 20 CHAPTER 3 CPU ARCHITECTURE Figure 3 2 Memory uPD780228 4 Special function registers SFR 256 x 8 bits General purpose registers 32 x 8 bits Internal high speed RAM 1024 x 8 bits FB0OH FAFFH EFFFH Cannot be used FA60H Program area Data memory FASER space FIP display RAM 1000H 96 x 8 bits OFFFH FA00H F9FFH CALLF entry area Cannot be used 6903 0800H F7FFH 07FFH Internal expansion RAM 512 x 8 bits Program area F600H F5FFH 0080H Cannot be used 007FH F000H EFFFH CALLT table area 0040H Program memory Internal ROM 003FH space 61440 x 8 bits Vector table area Y 0000H 0000H CHAPTER 3 CPU ARCHITECTURE Figure 3 3 Memory Map uPD78F0228 Special function registers SFR 256 x 8 bits General purpose registers 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH FAFFH EFFFH Cannot be used FA6 0H Program area 5 Data memory space FIP display RAM 1000H 96 x 8 bits OFFFH 00 F9FFH CALLF entry area Cannot be used F800H 0800H F7FFH 07FFH Internal expansion RAM 512 x 8 bits Program area F600H F5FFH 0080H Cannot be used 007FH F000H EFFFH CALLT table area 0040H Program memory Flash memory 003 61440 x 8 bits Vector table area 1 0000H 0000H 21 CHAPTER 3 CPU ARCHITECTURE 3 1 1 In
97. atchdog Timer The following three types of registers control the watchdog timer Oscillation stabilization time select register OSTS Watchdog timer clock select register WDCS Watchdog timer mode register WDTM 1 Oscillation stabilization time select register OSTS This register selects the oscillation stabilization time during which oscillation is stabilized after the RESET signal has been deasserted or the STOP mode has been released This register is set by using a 1 bit or 8 bit memory manipulation instruction Its value is set to 04H by RESET input Figure 8 2 Oscillation Stabilization Time Select Register Format Symbol 7 6 Address AtReset R W 5 4 3 2 1 0 Selects oscillation stabilization time at STOP mode release 211 fx 410 us 2 3 fx 1 64 ms 2 4 fx 3 28 ms 215 fx 6 55 ms 216 fx 13 1 ms Others Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 fk 5 0 MHz 103 CHAPTER 8 WATCHDOG TIMER 2 Watchdog timer clock select register WDCS This register selects the overflow time of the watchdog timer or interval timer It is set by using an 8 bit manipulation instruction The value of this register is initialized to OOH by RESET input Figure 8 3 Watchdog Timer Clock Select Register Format Symbol 7 6 Address At Reset R W 5 4 3 2 1 0 wocs o o e 2 rr WDCS2 WDCS
98. cally according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 Series User s Manual Instructions U12326E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In the relative addressing modes execution branches in a relative range of 128 to 127 from the first address of the next instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration 15 of the instruction after the BR instruction 15 8 7 6 jdisp8 15 WE E When S 0 all bits of are 0 When S 1 all bits of w are 1 35 CHAPTER 3 CPU ARCHITECTURE 3 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR laddr16 or CALLF addr11 instruction is executed The CALL addr16 and BR laddr16 instruction
99. ck is used for the main system clock 2 Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below 168 Table 13 3 STOP Mode Operating Status Item Operating status Clock Generator Oscillation stop CPU Operation stop Output output latch Status before STOP mode setting is held 8 bit remot e control timer Operation stop 8 bit PWM timer Watchdog A D converter imer Serial interi ace Operation enabled only when external input clock is selected as serial clock FIP contro er driver Operation disabled External in errupt request Operation enabled CHAPTER 13 STANDBY FUNCTION 2 STOP mode release The STOP mode can be cleared with the following two types of sources a Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt reque
100. ct register 50 86 Timer clock select register 51 86 8 bit counter 50 85 8 bit counter 51 85 Timer mode control register 1 79 8 bit timer mode control register 50 87 8 bit timer mode control register 51 87 Watchdog timer clock select register 104 Watchdog timer mode register 105 APPENDIX REVISION HISTORY This table shows the revision history of this manual The column under the heading Chapter indicates the chapter of the preceding edition in which a revision has been made Edition 2nd edition Major Revision from Previous Edition Change of uPD780226 and 780228 from under development to developed Chapter Throughout Change of I O circuit types of ports 7 8 9 and 10 of mask ROM model as follows Ports 7 8 and 9 Type 15 D to Type 15 F Port 10 Type 14 D to Type 14 F CHAPTER 2 PIN FUNCTIONS Addition of internal expansion RAM size select register IXS CHAPTER 3 CPU ARCHITECTURE CHAPTER 14 RESET FUNCTION CHAPTER 15 uPD78F0228 Correction of block diagrams of ports 7 8 9 and 10 CHAPTER 4 PORT FUNCTIONS Change of notes on inputting external clock Change of count clock value by setting of TLC2 and TCL1 in Figure 6 2 Timer Mode Control Register 1 Format CHAPTER 5 CLOCK GENERATOR CHAPTER 6 8 BIT REMOTE CONTROL TIMER Change of oscillation stabilization time by setting of OSTS2 OSTSO in Format of Oscillation Stabilization Time
101. ction Address The uPD780288 subseries has many addressing modes to improve the operability when a memory area to be manipulated during instruction execution is addressed The special function registers SFR and general purpose registers can be addressed in accordance with their functions All the 64K bytes of the data memory 0000H through FFFFH can be also addressed Figures 3 4 through 3 6 illustrates how the data memory is addressed For details on each addressing mode refer to 3 4 Addressing of Operand Address 24 CHAPTER 3 CPU ARCHITECTURE Figure 3 4 Addressing of Data Memory uPD780226 FFFF Special function registers SFR SFR addressing 256 x 8 bits dcn Pn Rane ERI AP 3 FF1F FF00 Y FEFF General purpose registers 32 x 8 bits FEEO FEDF Internal high speed RAM 1024 x 8 bits 5 25 2 lt Gu cut n uc FE1FH FBOOH FAFFH Cannot be used FA60H BASEN FIP display RAM FA00H 96 x 8 bits F9FFH Cannot be used F800H F7FFH Internal expansion RAM 512 x 8 bits F600H F5FFH Cannot be used C000H BFFFH Internal ROM 49152 x 8 bits 0000H Register addressing Y Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing 25 26 FFFFH F600H F5FFH F000H EFFFH 0000H CHAPTER 3 CPU ARCHITECTURE Figure 3 5 Addre
102. d value is restored 183 16 2 Operation List Instruction Group 8 bit data transfer Mnemonic Operands byte INSTRUCTION SET Operation r lt byte saddr byte sfr byte saddr lt byte sfr byte A r Acr nA lt saddr lt saddr A sfr lt sfr sfr A sfr A A laddr16 lt addr16 laddr16 addr16 A PSW stbyte PSW lt byte A PSW A PSW PSW A PSW A A DE A lt DE DEJ A DE A A HL HL A HL A A HL byte A lt HL byte HL byte A HL byte A A lt HL B HL B A HL B A A HL C A lt HL HL C A HL C r Aer lt gt saddr A e sfr A A A sfr A laddr16 addr16 A DE A DE A HL A e HL A HL byte A HL byte e HL Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Exceptr A Remark One instruction clock cycle is one cycle of the CPU clock selected by the processor clock control register PCC 184
103. de register 5 PM5 On chip pull up resistors can be connected in 1 bit units with the mask option in case of mask ROM model The uPD78F0228 has no pull up resistor Port 5 can drive LEDs directly RESET input sets port 5 to input mode Figure 4 7 shows a block diagram of port 5 Caution Low level input leak current in P50 to P57 pins differs depending on the following conditions Mask ROM model O When pull up resistors are contained always 3 Max O When pull up resistors are not contained 1clock interval when read instruction is executed to port 5 P5 and port mode register 5 PM5 200 uA Max Other than above 3 Max Flash memory model 1clock interval when read instruction is executed to port 5 P5 and port mode register 5 PM5 200 uA Max Other than above 3 uA Max Figure 4 7 P50 to P57 Block Diagram Mask Option Mask ROM model a has no Selector pull up resistor gt i 50 57 Output latch P50 P57 Internal bus 50 to PM57 PM Port mode register RD Port 5 read signal WR Port 5 write signal 57 CHAPTER 4 PORT FUNCTIONS 4 2 6 Port 6 Port 6 is an 8 bit input output port with output latch Pins from 60 to 67 can specify I O mode in 1 bit units with the port mode register 6 PM6 On chip pull up resistors can be connected in 1 bit units with the mask option in case of mask ROM model The u PD78
104. dr16 PC PC 2 jdisp8 if CY 0 addr16 PC PC 2 jdisp8 if Z 1 addr16 PC lt PC 2 jdisp8 if Z 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock selected by the processor clock control register PCC 190 Instruction Group Conditional branch Mnemonic Operands saddr bit addr16 CHAPTER 16 INSTRUCTION SET Operation PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 PC c PC 4 jdisp8 if sfr bit 1 A bit addr16 PC PC 3 jdisp8 if A bit 1 PSW bit addr16 HL bit addr16 PC lt PC 3 jdisp8 if PSW bit 1 PC lt 3 jdisp8 if HL bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 0 sfr bit addr16 PC lt PC 4 jdisp8 if sfr bit 0 A bit addr16 PC lt PC 3 jdisp8 if A bit 0 PSW bit addr16 PC lt PC 4 jdisp8 if PSW bit 0 HL bit addr16 OTR wo RITA Lolo O PC PC 3 jdisp8 if HL bit 0 saddr bit addr16 PC amp PC 4 jdisp8 if saddr bit 1 hen reset saddr bit sfr bit addr16 PC c PC 4 jdisp8 if sfr bit 1 hen reset sfr bit A bit addr16 PC PC 3 jdisp8 i he
105. ds x 10 segments Blanking width 1 16 when FBLKO FBLK2 000B Maximum current at the grid pin is 10 mA Maximum current at the segment pin is 3 mA At the key scan timing FIP output pin is OFF FIP output voltage grid 2 V voltage drop of 2 V segments 0 5 V voltage drop of 0 5 V Fluorescant display control voltage VLoap 35 V Mask option pull down resistor 25 139 140 CHAPTER 11 FIP CONTROLLER DRIVER By placing the above conditions in calculation lt 1 gt to lt 3 gt the total dissipation can be worked out lt 1 gt CPU power dissipation 5 5 V x 21 0 mA 115 5 mW lt 2 gt Output pin power dissipation Grid x Lotal current value of each grid 4 _ Blanking width The no of grids 1 10 mA x 11 Grids 1 x 1 11 Grids 1 16 Total segment current value of illuminated dots z 2V 17 2 mW Segment Voo x 1 Blanking width The no of grids 1 3 mA x 31 Dots 1 x x T 0 5 V 3 6 mW 11 Grids 1 16 lt 3 gt Pull down resistor power dissipation 2 i Grid The no of grids x 1 Blanking width Pull down resistor value no grids 1 2wN 2 i 55V 2V 35 V x 11 Grids xf 1 50 9 mW 25 11 Grids 1 16 Segment x The no of illuminated dots 1 Blanking width Pull down resistor value The no of grids 1 lt Tad 2
106. e differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function FIP and IEBus are trademarks of NEC Corporation MS DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of IBM Corporation HP9000 Series 300 HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsystems Inc NEWS and NEWS OS are trademarks of SONY Corporation OSF Motif i
107. e serial operation mode register 3 CSIMS CSIMG is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input Symbol lt 7 gt 6 Address AtReset R W 5 4 3 2 1 0 CSIM3 CSIE3 olol ofo MODE0 SCL31 SCL30 FF86H 00H R W Enables or disables operation of SIO3 Shift register operation Serial counter Port Disabled Cleared Port functionNete Enabled Count operation enabled Serial function port function Note The pins connected to SI SO and SCK can be used as port pins when CSIE3 0 when the SIO3 operation is stopped 124 CHAPTER 10 SERIAL INTERFACE 10 4 2 serial I O mode three wire serial I O mode is useful for connecting a peripheral I O or display controller having a clocked serial interface Communication is established by using three lines serial clock SCK serial output SO and serial input SI 1 Register setting The three wire serial I O mode is set by the serial operation mode register CSIM3 It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input Symbol lt 7 gt 6 2 1 0 Address AtReset R W 5 4 3 CSIM3 CSIE3 EIE GEN 0 MODEO SCL31 SCL30 FF86H 00H R W nables or disables operation of SIO3 Shift register operation Serial counter Port Disabled Cleared Port functionNete Enabled Count operation en
108. e used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Figure 3 12 General Register Configuration a Absolute Name 16 Bit Processing 8 Bit Processing FEFFH FEF8H RP2 FEFOH FEE8H RPO FEEOH 15 0 b Function Name 16 Bit Processing 8 Bit Processing FEFFH HL FEF8H DE FEFOH BC FEE8H AX FEEOH 15 0 31 CHAPTER CPU ARCHITECTURE 3 2 3 Special function registers SFR Special Function Register Unlike a general register each special function register has special functions Itis allocated in the FFOOH to FFFFH area The special function register can be manipulated like the general register with the operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 depend on the special function register type 32 Each manipulation bit unit can be specified as follows 1 bit manipulation
109. e used with this software 204 APPENDIX DEVELOPMENT TOOLS B 3 2 Software 2 2 ID78KO The ID78KO is a control program to debug the 78 0 series Integrated Debugger The 78 0 uses Windows on personal computers and OSF Motif EWS as graphical interface and presents the appearance and operatability conforming to these platforms The ID78KO has enhanced debugging function supporting C language and the trace result can be displayed by using the window integration function that interlocks source program disassemble display and memory display to the trace result In addition debugging efficiency for programs using real time OS can be enhanced by incorporating extension modules such as task debugger and system performance analyzer Used in combination with optional device file DF780228 Part Number uSxxxxID78K0 Remark xxxx in the part number differs depending on the host machine and OS used uSxxxxID78K0 Host Machine OS Distribution Medium PC 9800 Series MS DOS 3 5 inch 2HD Ver 3 30 to Ver 6 2Note t Windows Ver 3 1 IBM PC AT and their Refer to B 4 3 5 inch 2HC compatible machines Windows Japanese version IBM PC AT and their 3 5 inch 2HC compatible machines Windows English version HP9000 series 700 HP UX rel 9 01 Digital audio tape DAT SPARCstation SunOS rel 4 1 1 Cartridge tape QIC 24 3 5 inch 2 NEWS RISC NEWS OS 6 1x 1 4 inch CGMT 3 5 i
110. easing the error of the reference voltage Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the contents of the analog input channel specification register ADSO are changed If the analog input pin is changed during A D conversion therefore the A D conversion result of the old analog input may be written to ADSO immediately before ADSO is rewritten and consequently the conversion end interrupt flag may be set If ADIF is read immediately after ADSO has been rewritten ADIF may be set despite that the A D conversion of the new analog input has not been completed Before resuming A D conversion that has been stopped clear ADIF 119 CHAPTER 9 A D CONVERTER Figure 9 9 A D Conversion End Interrupt Request Generation Timing ADSO rewriting ADSO rewriting ADIF is set but conversion of ANIn conversion starts ANIm conversion starts ANIm is not completed A D conversion ADCRHO Remark 0 1 7 m 0 1 7 8 AVbob pin The AVop pin supplies power to the analog circuit It also supplies power to the input circuit of ANIO through ANI7 Therefore apply the same potential as that of the Vpbp pin to this pin as shown in Figure 9 10 in an application where a backup power supply is used Figure 9 10 Processing of AVpp Pin num Main power supply capacitor 120 CHAPTER 10 SERIAL INTERFACE 10 1 Function of Serial Interface The serial interface has the followi
111. ed by using the 2 byte call instruction CALLF 22 CHAPTER 3 CPU ARCHITECTURE 3 1 2 Internal data memory space The uPD780228 subseries has the following RAM 1 Internal high speed RAM This RAM consists of addresses FBOOH through FEFFH or 1024 x 8 bits Of these addresses FEEOH through FEFFH constitute a 32 byte area to which four banks of general purpose registers with each bank consisting of eight 8 bit registers are allocated The internal high speed RAM can be also used as a stack memory 2 Internal expansion RAM An internal expansion RAM is allocated to 512 byte area of F600H through F7FFH 3 FIP display RAM An FIP display RAM is allocated to a 96 byte area of through F5FH This RAM be also used as a normal RAM 3 1 3 Special function register SFR area Special function registers SFR are allocated to the area FFOOH through FFFFH as on chip peripheral hardware refer to Table 3 3 Special Function Registers in 3 2 3 Special function register SFR Caution Do not access an address to which no SFR is allocated 23 CHAPTER 3 CPU ARCHITECTURE 3 1 4 Data memory addressing Specifying the address of the instruction to be executed next or specifying an address of the register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is addressed by the program counter PC for details refer to 3 3 Addressing of Instru
112. egister and memory addressing which undergo manipulation during instruction execution 3 4 1 Implied addressing Function The register which functions as an accumulator A and AX in the general register is automatically tacitly addressed Of the uPD780228 subseries instruction words the following instructions employs implied addressing Instruction Register to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values subject to decimal adjustment ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing 39 CHAPTER 3 CPU ARCHITECTURE 3 4 2 Register addressing Function This addressing accesses a general register as an operand The general register accessed is specified by the register bank select flags RBSO and RBS1 and register specify code Rn or RPn in an instruction code Register addressing is carried out when an instruction with the following operand format is executed Whe
113. eight High digits on the left and low digits on the right Active low representations xxx top bar over pin or signal name Note Description of Note in the text Caution Information requiring particular attention Remark Additional explanatory material Numeral representations Binary XXXX or xxxxB Decimal XXXX Hexadecimal xxxxH Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such e Documents related to devices Document Name Document Number English Japanese uPD780228 Subseries User s Manual This manual U12012J uPD780226 780228 Data Sheet U11797E U11797J uPD78F0228 Preliminary Product Information U11971E U11971J 78K 0 Series Instruction Table 010903 78 0 Series Instruction Set U10904J 78K 0 Series Users Manual Instructions U12326E U12326J 78K 0 Series Application Note Fundamental 11 U10121E U10121J Caution The contents of the above documents are subject to change without notice Be sure to use the latest edition for designing Documents related to development tools User s Manual Document Name Document Number English Japanese RA78K Series Assembler Package Operation EEU 1399 EEU 809 Language EEU 1404 EEU 815 RA78K Series Structured Assembler Preprocessor EEU 1402 EEU 817 RA78K0 Assembler Package Operation U11802
114. en it is not used For the configuration of each type of the I O circuit refer to Figure 2 1 Table 2 1 I O Circuit Type of Each Pin Pin Name Circuit Type Recommended Connections of Unused Pin POO INTPO Individually connect to Vsso via resistor PO1 INTP1 P10 ANIO P17 ANI7 P20 SCK Individually connect to Vooo or Vsso via resistor P21 SO P22 SI P23 TI1 P24 TIO50 P25 TIO51 P40 P47 Mask ROM model P50 P57 Individually connect to Vono via resistor P60 P67 P70 FIP16 P77 FIP23 Individually connect to Vooo or Vsso via resistor P80 FIP24 P87 FIP31 P90 FIP32 P97 FIP39 P100 FIP40 P107 FIP47 Output Directly connect to Vss uUPD78F0228 P50 P57 Individually connect to Vooo via resistor P60 P67 P70 FIP16 P77 FIP23 Individually connect to Vooo or Vsso via resistor P80 FIP24 P87 FIP31 P90 FIP32 P97 FIP39 100 40 107 47 Output VPP Directly connect to Vss FIPO FIP15 Output Individually connect to Vsso via resistor RESET Input Connect to AVss Connect to Vss1 16 CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin Input Output Circuit List 1 2 P ch H T VREF Threshold voltage Schmitt Triggered Input with Hysteresis Characteristics Type 13 J Pull up g
115. end to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M7 96 5 Major Revisions in This Edition Page Description Throughout Change of 0780226 and 780228 from under development to developed p 16 2 3 I O Circuits of Pins and Connections of Unused Pins Change of I O circuit types of ports 7 8 9 and 10 of mask ROM model as follows Ports 7 8 and 9 type 15 D to type 15 F Port 10 type 14 D to type 14 F p 33 173 175 177 Addition of internal expansion RAM size select register 5 p 59 62 Correction of block diagrams of ports 7 8 9 and 10 5 4 1 Main system clock oscillator Change of notes on inputting external clock p 78 Change of count clock value by setting of TCL2 and TCL1 in Figure 6 2 Timer Mode Control Register 1 Format p 103 164 Change of oscillation stabilization time by setting of OSTS2 OSTSO in Format of Oscillation Stabilization Time Select Register p 130 Figure 11 2 Display Mode Register 0 Format Change of setting of FOUT5 FOUTO and addition of notes on FIP output pins p 139 Addition of 11 7 Calculation of Total Power Dissipation p 173 175 202 Change of product name of dedicated flash writer as follows Flashpro to Falshpro II part No FL PR2 Addition of APPENDIX A DIFFERENCES BETWEEN uPD78044H 780228 AND
116. equest The HALT mode is cleared and vectored interrupt service is carried out whether interrupt request acknowledge is enabled or disabled 166 CHAPTER 13 STANDBY FUNCTION c Clear upon RESET input As is the case with normal reset operation a program is executed after branch to the reset vector address Figure 13 3 HALT Mode Release by RESET Input HALT Wait Instruction 216 13 1 ms RESET NEM Signal Oscillation Operating Reset Stabilization Operating Mode HALT Mode Period Wait Status Mode Oscillation Clock Oscillation ult stop J Oscillation Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 5 0 MHz Table 13 2 Operation after HALT Mode Release Release Source Operation Maskable interrupt request Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution HALT mode hold Non maskable interrupt request Interrupt service execution RESET input Reset processing x Don t care 167 CHAPTER 13 STANDBY FUNCTION 13 2 2 STOP mode 1 STOP mode set and operating status The STOP Cautions mode is set by executing the STOP instruction 1 When the STOP mode is set X2 pin is internally pulled up to Vpp to suppress the leakage at the crystal oscillator Thus do not use the STOP mode in a system where an external clo
117. equest is acknowledged only once even if it occurs two times or more 155 CHAPTER 12 INTERRUPT FUNCTIONS 12 4 2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask Mk flag is cleared to 0 A vectored interrupt request is acknowledged in an interrupt enable state with IE flag set to 1 However a low priority interrupt request is not acknowledged during high priority interrupt service with ISP flag reset to 0 Wait times from maskable interrupt request generation to interrupt servicing are shown in Table 12 3 For the timing to acknowledge an interrupt request refer to Figures 12 12 and 12 13 Table 12 3 Times from Maskable Interrupt Request Generation to Interrupt Service Tine iners Tie acca When xxPR 1 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock CPU clock fcPu If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are assigned the same priority by the interrupt priority specify flag the one with the higher default priority is acknowledged first Any reserved interrupt requests are acknowledged when they become acknowledgeable Figure 12 11 s
118. er 4 TIO50 and 51 Capture trigger input pin of the 8 bit PWM timers and timer output pin 2 2 4 P40 through P47 Port 4 P40 through 47 constitute an 8 bit I O port This port can be set in the input or output mode in 1 bit units by using the port mode register 4 PM4 When it is used as an input port the internal pull up resistor can be connected by using the pull up resistor option register 4 PU4 This port can directly drive an LED 2 2 5 P50 through P57 Port 5 P50 through 57 constitute an 8 bit I O port This port can be set in the input or output mode in 1 bit units by using the port mode register 5 PM5 P50 through P57 are N ch open drain pins Pull up resistors can be connected to these pins of the mask ROM models by mask option 078 0228 does not have pull up resistors This port can directly drive an LED 2 2 6 P60 through P67 Port 6 P60 through 67 constitute an 8 bit I O port This port can be set in the input or output mode in 1 bit units by using the port mode register 6 PM6 P60 through P67 are N ch open drain pins Pull up resistors can be connected to these pins of the mask ROM models by mask option 078 0228 does not have pull up resistors This port can directly drive an LED 2 2 7 P70 through P77 Port 7 P70 through P77 constitute an 8 bit I O port These pins are also used as FIP controller driver output pins The following operation modes can be specified in 1 bit units
119. er The divider divides the main system clock oscillator output fx and generates various clocks 73 CHAPTER 5 CLOCK GENERATOR 5 5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode Main system clock fx e CPU clock fcpu Clock to peripheral hardware The function and operation of the clock generator circuit are determined by the processor clock control register PCC as follows a Upon generation of RESET signal the lowest speed mode of the main system clock 6 4 us when operated at 5 0 MHz is selected PCC 04H Main system clock oscillation stops while low level is applied to RESET pin b One of the five 0 4 us 0 8 us 1 6 us 3 2 us and 6 4 us when operated at 5 0 MHz CPU clock stages can be selected by setting the PCC c Two standby modes the STOP and HALT modes are available d main system clock is divided and supplied to the peripheral hardware Therefore the peripheral hardware also stops if the main system clock is stopped Except external input clock operation 74 CHAPTER 5 CLOCK GENERATOR 5 6 Changing CPU Clock 5 6 1 Time required to change CPU clock The CPU clock can be changed by using bits 0 through 2 PCCO through PCC2 of the processor clock control register PCC Actually the clock is not changed immediately after PCC has been rewritten and the CPU operates with t
120. er used to connect the NQPACK100RB and EP 100GF SL HQPACK100RB This is a lid used when a device is mounted to the NQPACK100RB Note Under development Remarks 1 NQPACK100RB YQPACK100RB and HQPACK100RB are products of Tokyo Eletech Corp 03 5295 1661 Consult NEC distributor when purchasing these products 2 NQPACK100RB YQPACK100RB and HQPACK100RB are available in one unit 203 APPENDIX DEVELOPMENT TOOLS B 3 2 Software 1 2 5 78 0 Debugs program at C source level or assembler level while simulating operation of target system System simulator on host machine SM78K0 runs on Windows By using the SM78KO the logic and performance of an application can be verified independently of hardware development even when the in circuit emulator is not used This enhances development efficiency and improves software quality Used in combination with optional device file DF780228 Part Number 78 0 Remark xxxx in the part number differs depending on the host machine and OS used Lu SxxxxSM78K0 Host Machine Distribution Medium PC 9800 series MS DOS 3 5 inch 2HD Ver 3 30 to Ver 6 2Note Windows Ver 3 0 to Ver 3 1 IBM PC AT and Refer to B 4 3 5 inch 2HC compatible machines Windows Japanese version IBM PC AT and compatible machines Windows English version Note Although MS DOS Ver 5 0 and above have a task swap function this function cannot b
121. es for 16 bit data transfer instructions 0800H to OFFFH Immediate data or labels 0040H to 007FH Immediate data or labels even addresses only word byte bit 16 bit immediate data or label 8 bit immediate data or label 3 bit immediate data or label RBO to RB3 Note FFDOH to FFDFH are not addressable Remark For special function register symbols refer to Table 3 3 Special Function Register List 182 CHAPTER 16 INSTRUCTION SET 16 1 2 Description of operation column PSW addr16 jdisp8 A register 8 bit accumulator X register B register C register D register Eregister H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 16 1 3 Description of flag operation column Blank 0 1 x R Unchanged Cleared to 0 Set to 1 Set cleared according to the result Previously save
122. esponding to the data output at each display timing TO through T15 as shown in Figure 11 6 for example TO FAOOH through FAOSH T1 FAO6H through FAOBH When 48 FIP output pins FIPO through FIP47 are used one block of display data consists of 6 bytes FIP output pins 0 FIPO through 47 FIP47 correspond to one block of display data sequentially starting from the least significant bit toward the most significant bit Figure 11 6 Relation between Address Location of Display Data Memory and FIP Output with 48 FIP output pins and 16 patterns Display timing Tks Address FA5AH FASFH 5 FH 5EH 5DH 5CH 5BH 5AH T15 La FA54H FA59H 59H 58H 57H 56H 55H 54H T14 FA12H FA17H 17H 16H 15H 14H 13H 12H T3 t FA0CH FA11H 11H 10H 0 0DH 0 CH T2 t FA06H FA0BH 0BH OAH 09H 08H 07H 06H Ti FA00H FA05H 05H 04H 03H 02H 01H 00H TO 47 40 Fide FIP output pins 134 CHAPTER 11 FIP CONTROLLER DRIVER 11 5 Key Scan Flag and Key Scan Data 11 5 1 Key scan flag The key scan flag KSF is set to 1 during key scan timing and is automatically reset to 0 at display timing KSF is mapped to bit 7 of the display mode register 2 DSPM2 and can be tested in 1 bit units It cannot be written however By testing KSF it can be determined whether key scan timing is in progress and whether key input data is correct can be checked Whether key scan timing is inserted
123. et processing Interrupt request generation WDT interrupt servicing Interrupt request reserve Interrupt control register unaccessed Interrupt service start WDTM Watchdog timer mode register WDT Watchdog timer Figure 12 9 Non Maskable Interrupt Request Acknowledge Timing 3 PSW and PC Save Jump t CPU Processing Instruction Instruction interit Sondang Interrupt Servicing Program An interrupt request generated during this period is acknowledged at the timing indicated by WDTIF Watchdog timer interrupt request flag 154 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 10 Non Maskable Interrupt Request Acknowledge Operation a If a new non maskable interrupt request is generated during non maskable interrupt servicing program execution Main Routine d ____ NMI Request 1 Execution NMPHeguestslo NMI Request 2 Reserve NMI Request 2 1 Instruction Execution Reserved NMI Request 2 Processing Z b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main Routine NMI Request lt 1 gt Execution NMI Request 2 Reserve NMI Request 1 NMI Request 2 gt NMI Request 3 Reserve NMI Request 3 N 1 Instruction Execution Reserved NMI Request 2 Processing Zt NMI request lt 3 gt is not acknowledged NMI r
124. f Clock Generation Circuit 2 69 5 2 Processor Clock Control Register Format 70 5 3 External Circuit of Main System Clock Oscillator esses 71 5 4 Examples of Resonator with Bad Connection 72 5 5 Changing CPU GloGle a n eec e da e qe e b aaa det setas 76 6 1 Block Diagram of 8 Bit Remote Control Timer 77 6 2 Timer Mode Control Register 1 78 6 3 Timing of Pulse Width Measurement sse nennen 80 7 1 8 Bit PWM Timers Block Diagram 84 7 2 Format of Timer Clock Select Register 86 7 3 Format of 8 Bit Timer Control Register 5 88 vi LIST OF FIGURES 2 3 Figure No Title Page 7 4 Timing of Interval Timer Operation 90 7 5 Timing of External Event Counter Operation with rising edge specified 92 7 6 PWM Output Operation Timing 7 7 Operation Timing When CR5n Is Changed 7 8 16 Bit Resolution Cascade 98 7 9 Start Timing of 8 Bit Counter 5n 5 2 2 99 7 10 Timing after Changing Compare Register Value during Timer Count 99 8 1 Watchdog Timer Block Diagram s 102 8 2 Oscillation Stabilization Time Select Register Format 103 8 3 Watchdog Time
125. g uinea tune tenet Rete nte e sta 47 CHAPTER 4 PORT 6 Ra sm aa 49 4 1 lt 42 49 4 2 Port Configuration 4 2 1 4 2 2 4 2 3 4 2 4 4 2 5 4 2 6 4 2 7 4 2 8 4 2 9 420250 10 aR ead eie iens 62 4 3 Port Function Control Registers 1 eene nnnnnnnnn nnne 63 4 4 Function Operations I UYUNI aar Es ce erre nae iep tanis inii 66 4 4 1 Writing to input output port 66 4 4 2 Reading from input output 66 4 4 3 Operations on input output 66 4 5 Selecting Mask Option uu III LLA saa cect seursecedacesedvecrecesdecasessetoereaseeoeds 67 CHAPTER 5 CLOCK QGENERATOR u uN S u ua niae panis ant 5 1 Clock Generator Functions 5 2 Clock Generator Configuration 69 5 3 Register Controlling Clock Generation Circuit 1 1 1 70 5 4 System Clock Oscillatop 2 2 KS Decio SS ua 71 5 4 4 Main system clock oscillator 5 4 2 I P DP 73 5 5 Clock Generator Operations
126. h uPD78018F 78014 uPD780001 uPD78002 78083 1ch UART 1ch uPD780964 2ch UART 2ch uPD780924 uPD780208 32K 60K 0780228 48K 60K 78044 32K 48K uUPD78044F 16K 40K 780308 48K 60K 3ch time division UART 1ch uPD78064 32K 2ch UART 1ch uPD78064 16K 32K uPD78098B 40K 60K Sch UART ich uPD78098 32K 60K uPD780973 24K 32K 2ch UART 1ch uPD780805 40K 60K uPD78P0914 32K Note 10 bit timer 1 channel CHAPTER 1 GENERAL 1 6 Block Diagram PO1 CONTROLLER TIMER 1 10 17 TM1 PORT2 P20 P25 IMS TIO50 P24 TM50 PORT4 P40 P47 e A em K TAE GORE 5 50 57 TIO51 P25 51 PORT6 P60 P67 WATCHDOG TIMER PORT7 P70 P77 SCK P20 SERIAL INTERFACE PORT8 P80 P87 SO P 1 SI P22 S103 RAM PORT9 P90 P97 inue 5277 10 100 107 ANWIPTT A D CONVERTER A D1 AVss FIP CONTROLLER DRIVER 00 INTERRUPT INTP1 PO1 SYSTEM Vopo Vsso IC Vsst VPP Vop2 Remarks 1 The internal ROM capacity differs depending on the model 2 uPD78F0228 1 7 Functional Outline bxc Part Number Internal memory ROM CHAPTER 1 GENERAL uPD780226 uPD780228 uUPD78F0228 Mask ROM Flash memory
127. he current consumption can be reduced in the standby mode Figure 9 7 Example of Reducing Current Consumption in Standby Mode Pch lt cso Series resistor string AVss Input range of ANIO to ANI7 Make sure that the input voltages of ANIO through ANI7 are within the rated range If a voltage greater than or less than AVss is input to a channel even if it is within the absolute maximum rating range the converted value of the channel is undefined and in the worst case the converted values of the other channels are affected Conflicting operation 1 Conflict between writing and reading A D conversion result register ADCRHO on completion of conversion Reading ADRCHO takes precedence After ADCRHO has been read a new conversion result is written to ADCRHO 2 Conflict between writing ADCRHO and input of external trigger signal on completion of conversion An external trigger signal is not accepted during A D conversion Therefore the external trigger signal is not accepted while ADCRHO is written 3 Conflict between writing ADCRHO and writing A D converter mode register ADMO or writing analog input channel specification register ADSO on completion of conversion Writing ADMO or ADSO takes precedence ADCRHO is not written Nor is the conversion end interrupt request signal INTAD generated 4 Reference voltage input O 5 6 7 CHAPTER 9 A D
128. he fluorescent indicator panel has a capacitance between the grid and segment as indicated by Csc in the figure and the timing signal is raised via Cse If the voltage of the timing signal rises beyond the cutoff voltage Ex as shown in Figure 11 9 leakage emission occurs This whisker like voltage changes with the values of Cse and internal pull down resistor RL The greater the value of Csc and the greater the value of Rt the higher this voltage increasing the possibility of the occurrence of leakage emission The value of differs depending on the display area of the fluorescent indicator panel The larger the area the higher the Csc Therefore the value of the pull down resistor differs depending on the size of the fluorescent indicator panel in order to prevent leakage emission Because the value of the pull down resistor that can be connected by mask option is relatively high the leakage emission may not be suppressed by the internal pull down resistor alone In case sufficient display quality cannot be obtained deepen the back bias increase Ex attach a filter to the fluorescent indicator panel or connect an external pull down resistor of several 10 to the timing signal pin The likelihood of leakage emission caused by Cse occuring changes depending on the duty cycle of the whisker voltage vis a vis the total display cycle The fewer the number of display digits the less likelihood of occurrence of leakage emission L
129. he highest speed the contents of the processor clock control register PCC are rewritten and the CPU operates at the highest speed CHAPTER 6 8 BIT REMOTE CONTROL TIMER 6 1 Function of 8 Bit Remote Control Timer The 8 bit remote control timer has a pulse width measurement function with a resolution of 8 bits Pulse width is measured from a difference in count value when the valid edge has been detected while the timer operates in the free running mode 6 2 Configuration of 8 Bit Remote Control Timer The 8 bit remote control timer consists of the following hardware Table 6 1 8 Bit Remote Control Timer Configuration Item Configuration Timer register 8 bit timer TM1 Register 8 bit capture register x 2 CP10 and CP11 Control register Timer mode control register 1 TMC1 Figure 6 1 Block Diagram of 8 Bit Remote Control Timer Internal bus INTTM10 Noise rejection Rising edge detection 8 bit capture register 1 23 CP10 fx 2 fx 23 28 fx 29 Selector INTTM11 Noise rejection Falling edge detection 8 bit capture register CP11 Internal bus Timer mode control register 1 77 CHAPTER 6 8 BIT REMOTE CONTROL TIMER 6 3 Registers Controlling 8 Bit Remote Control Timer The following three types of registers control the 8 bit remote control timer Timer mode control register
130. he old clock until the specified number of instructions refer to Table 5 3 has been executed after PCC was changed Table 5 3 Maximum Time Required for Changing CPU Clock Set Value before Change Set Value after Change 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 8 instructions 4 instructions 4 instructions 2 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction Se Remark The time required to execute one instruction is equal to the minimum instruction execution time with the CPU clock before change 75 CHAPTER 5 CLOCK GENERATOR 5 6 2 CPU clock changing procedure The CPU clock is changed in the following procedure 76 1 Figure 5 5 Changing CPU Clock Voo 7 RESET i CPU clock Slowest Fastest T operation 13 1 ms at 5 0 MHz Internal reset operation The GPU is reset if the RESET pin is made low after power application The reset is cleared and the main system clock starts oscillating if the RESET pin is later made high At this time it is automatically ensured that oscillation stabilization time 2 6 fx elapses After that the CPU starts executing instructions at the slowest speed of the main system clock 6 4 us at 5 0 MHz After sufficient time has elapsed during which the voltage rises to the level at which the CPU can operate at t
131. he register bank specified by the register bank select flags RBSO and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format mw Description example 46 MOV A HL 10H When setting byte to 10H Operation code 1T 70 ST do 0 CHAPTER 3 CPU ARCHITECTURE 3 4 8 Based indexed addressing Function This addressing addresses the memory by adding the contents of the HL register pair which is used as a base register to the contents of the B or C register specified in the instruction word and by using the result of the addition The HL B and C registers to be accessed are registers in the register bank specified by the register bank select flags RBSO and RBS1 The addition is performed by extending the contents of the B or C register to 16 bits as a positive number A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format THB HL Description example In the case of MOV A HL B Operation code 15705 3 07 0 0 d 3 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an inter
132. hows interrupt request acknowledge algorithms If a maskable interrupt request is acknowledged the contents are saved in the stacks in the order of program status word PSW program counter PC the IE flag is reset to 0 and the acknowledged interrupt request priority specify flag contents are transferred to the ISP flag Further the vector table data determined for each interrupt request is loaded into PC and branched Restore from the interrupt is possible with the RETI instruction 156 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 11 Interrupt Request Acknowledge Processing Algorithm Start No Interrupt Request Yes Generation Yes Interrupt request reserve Yes High Priority 0 Low Priority Any high priority interrupt request among simultaneously generated xxPR 0 interrupts 2 Yes simultaneously generated xxPR 0 interrupt requests Yes Interrupt request reserve Interrupt request reserve simultaneously generated high priority interrupt requests Yes Interrupt request reserve Yes Interrupt request reserve gt Yes Interrupt request reserve Vectored interrupt servicing Yes Interrupt request reserve Vectored interrupt servicing xxIF Interrupt request flag xxMK Interrupt mask flag xxPR Priority specify flag IE Flag that controls maskable interrupt request acknowledge
133. hpro and by means of serial communication Select one of the communication modes listed in Table 15 3 to write the flash memory To select a communication mode use the format shown in Figure 15 3 Each communication mode is selected by the number of Vp p pulses shown in Table 15 3 Table 15 3 Communication Modes Communication Mode Number of Channels 3 wire serial I O Pseudo 3 wire serial I ONote Pin Used SCK P20 SO P21 SI P22 P40 serial clock 1 0 P41 serial data output P42 serial data input Note Execute serial transfer by controlling the ports by software Number of Vp p Pulses Caution Be sure to select a communication mode with the number of Vp p pulses shown in Table 15 3 Figure 15 3 Communication Mode Select Format 10V Vee Voo Vss Voo RESET Vss 178 VPP pulses U i Flash memory writing mode i i CHAPTER 15 4PD78F0228 15 3 2 Function of flash memory programming By transmitting receiving commands data in the selected communication mode operations of the flash memory such as writing are performed Table 15 14 lists the major functions of the flash memory programming Table 15 4 Major Functions of Flash Memory Programming Function Description Reset Used to stop writing or detect communication synchronization Batch verify Compares all memory contents with input data Batch erase Erases all memory contents Batch blank check Checks
134. iguration A total of 12 non maskable maskable and software interrupts are incorporated in the interrupt sources see Table 12 1 Table 12 1 Interrupt Sources Interrupt Default Interrupt Source Internal Vector Basic Table Configuration Type PriorityNote 1 Trigger External Address TypeNote Non INTWDT Overflow of watchdog timer Internal maskable with watchdog timer mode 1 selected Maskable INTWDT Overflow of watchdog timer with internal timer mode selected Detection of pin input edge External Detection of timer input edge Key scan timing from FIP controller driver Internal End of transfer of serial interface Coincidence of 8 bit timer TM50 Coincidence of 8 bit timer TM51 End of A D conversion Software Execution of BRK instruction Notes 1 Iftwo or more maskable interrupt requests are simultaneously generated they are controlled according to the default priority 0 indicates the highest priority and 9 indicates the lowest 2 A through E under the heading Basic Configuration Type correspond to A through E in Figure 12 1 144 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt Internal Bus Vector Table Address Generator Interrupt Priority Control Request Circuit Standby 7 Release Signal B Internal mas
135. imimimimimimimim O O O O O O OJ O O OI OP O O O OI OP O O O O O OI OP O OI OP O O O O O OO O OOO O O O O O O O O O OI OP O O O OOP OOO Serial operation mode register 3 CSIM3 33 CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 2 2 Address Special Function Register SFR Name Manipulatable Bit Units At Reset 1 bit 8 bits 16 bits Display mode register 0 Display mode register 1 Display mode register 2 Interrupt request flag register OL Interrupt request flag register Interrupt mask flag register OL Interrupt mask flag register OH Priority specification flag register OL O O O O O O O O O Priority specification flag register 0H CCHNote 1 OCHNote 2 00H 04H Memory size select register Internal expansion RAM size select register Watchdog timer mode register Oscillation stabilization time select register mimimimimimimimimimimimimim Processor clock control register Notes 1 Be sure to set the value of this register to when the uPD780228 is used 2 After reset be sure to set this bit to OBH 34 CHAPTER 3 CPU ARCHITECTURE 3 3 Addressing of Instruction Address An instruction address is determined by program counter PC contents Program counter PC contents are normally incremented 1 for each byte automati
136. inco eee a ES EC M TERT EDU 8 2 1 FUNCTION LiSt euria 2 2 Pin F ctiongs 1L 2 2 1 SP00 and POT POort 0 nire teri nO ce a EE ua IER 2 2 2 P10 through P17 Port 1 2 2 8 20 through P25 Port 2 2 2 4 P40 through P47 Port 4 2 2 5 P50 through P57 Port 5 2 2 6 P60 through P67 Port 6 2 27 P70 through P77 Port 7 2 2 8 P80 through P87 Port 8 2 2 9 P90 through P97 Port 9 2 2 10 P100 thtough P107 Port T0 iiie reete Et t HE 14 2 2 11 FIPO through FIP15 D MIORD 2 213 AN DD a ue D a ar E ERE N AAIE pa 2 214 ANVSS HE a e ERR t E EN ere Eee 14 2 2 15 RESET jacta bon patet SUN E Da 14 2 216 2 ien ea ne 14 2217 Mpbothrough MDD2 veces reine re hi eaa dee hn 15 2 2 18 550 MSS o ere a Ha ete d e di er eto neni vr 15 2 2 19 Ver 78 0228 only 215 2 2 20 IC Mask ROM productonly ald 2 3 Circuits of Pins and Connections of Unused Pins 16 CHAPTER 3 CPU ARCHITECTURES eriam kite ient ee amen tae 19 3 1 Memory Space 19 3 1 1 Internal program memory
137. ister 3 Format Symbol lt 7 gt 6 Address AtReset R W 5 4 3 2 1 0 CSIM3 CSIE3 Ps ee EI 0 MODE0 SCL31 SCL30 FF86H 00H R W nables or disables operation of SIO3 Shift register operation Serial counter Port Disabled Cleared Port function te Enabled Count operation enabled Serial function port function Transfer operation mode flag Operation mode Transfer start trigger SO output Transmission or transmission SIO3 write Normal output reception mode Reception mode SIO3 read Fixed to low level Selects clock External clock input to SCK pin fx 23 625 kHz fx 24 313 kHz 25 156 kHz Note The pins connected to SI SO and SCK can be used as port pins when CSIE3 0 when the SIO3 operation is stopped Remarks 1 fx Main system clock oscillation frequency 2 fx 5 0 MHz 123 CHAPTER 10 SERIAL INTERFACE 10 4 Operation of Serial Interface The serial interface operates in the following two modes Operation stop mode Three wire serial I O mode 10 4 1 Operation stop mode In the operation stop mode the power consumption can be reduced because serial transfer is not executed Because the serial I O shift register 3 SIO3 does not perform the shift operation this register can be used as a normal 8 bit register In this mode the P20 SCK P21 SO and P22 SI pins can be used as normal I O port pins 1 Register setting The operation stop mode is set by th
138. ister converts parallel data to serial data to perform serial transmission reception shift operation in synchronization with the serial clock SIO3 is set by using an 8 bit memory manipulation instruction The serial operation is started by writing data to or reading data from SIO3 when bit 7 CSIE3 of the serial operation mode register 3 CSIM3 is 1 During transmission the data written to SIO3 is output to the serial output line SO During reception the data is read to SIO3 from the serial input line SI The contents of this register are undefined when the RESET signal is input Caution Do not access SIO3 during transmission except when triggering the transmission reading SIO3 is prohibited when bit 2 MODEO of CSIMG 0 and writing is prohibited when MODEO z 1 2 Serial clock counter This counter counts the serial clock output or input during transmission reception to check that 8 bit data has been transmitted received 122 CHAPTER 10 SERIAL INTERFACE 10 3 Registers Controlling Serial Interface The serial interface is controlled by the serial operation mode register 3 CSIMS Serial operation mode register 3 CSIM3 This register selects the serial clock and operation mode of the serial interface and enables or disables the operation It is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is initialized to OOH by RESET input Figure 10 2 Serial Operation Mode Reg
139. ized to OOH by RESET input Symbol 7 Figure 9 3 Analog Input Channel Specification Register Format 6 Address At Reset R W 5 4 3 2 1 0 o o ADSO3 ADSO2 501 500 RW ADS03 0502 ADSO1 ADSOO Specifies analog input channel 0 0 0 0 ANIO 0 1 ANI1 0 0 0 0 0 1 0 0 ANI2 ANI3 0 ANI4 0 0 ANI6 0 ANI7 Others 1 1 1 0 0 1 1 0 1 1 1 Setting prohibited 113 CHAPTER 9 CONVERTER 9 4 Operation of A D Converter 9 4 1 Basic operation of A D converter 5 6 114 Select one channel for A D conversion by using the analog input channel specification register ADSO The sample amp hold circuit samples the voltage input to the selected analog input channel The sample amp hold circuit enters the hold status after it has performed sampling for fixed time and holds the input analog voltage until the A D conversion is completed Bit 7 of the successive approximation register SAR is set The tap selector sets the voltage tap of the series resistor string to 1 2 AVpp The voltage comparator compares the voltage difference between the voltage of the series resistor string and voltage tap If the input analog voltage is greater than 1 2 AVpp the MSB of SAR remains set If it is less than 1 2 MSB is reset Bit 6 of SAR is automatically set and the next comparison is performed The voltage tap of the series resistor string is selected as follows
140. kable interrupt Internal Bus Vector Table Address Generator Interrupt Request Standby Release Signal C External maskable interrupt INTPO Internal Bus External interrupt rise fall edge enable register EGP EGN Edge Detector Vector Table Address Generator Priority Control Circuit Interrupt Request Standby Release Signal 145 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt INTTM10 INTTM11 Internal Bus Priority Control Vector Table LEY Address Circuit Generator Standby Release Signal Interrupt Edge Request Detector E Software interrupt Internal Bus Interrupt Priority Control Vector Table Request g Circuit Address Generator IF Interrupt request flag IE Interrupt enabled flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag 146 12 12 3 Interrupt Function Control Registers INTERRUPT FUNCTIONS The following six types of registers are used to control the interrupt functions Interrupt request flag register IFOL and IFOH Interrupt mask flag register MKOL and MKOH Priority specify flag register PROL and PROH External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN Program status word PSW Table 12
141. l Instructions Pin functions CPU functions Internal block functions Instruction set Interrupts Explanation of each instruction Miscellaneous on chip peripheral functions How to Read This Manual Before reading this manual you must have general knowledge of electric and logic circuits and microcomputer O When you want to understand the functions in general Read this manual in the order of the contents How to interpret the register format For the circled bit number the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 already defined in the header file named sfrbit h When confirming the details of the register whose register name is known Refer to APPENDIX D REGISTER INDEX When you want to know the differences between the uPD78044H subseries and the PD780208 subseries Refer to APPENDIX A DIFFERENCES BETWEEN yuPD78044H 780228 AND 780208 SUBSERIES When you want to know the details of the w PD780228 subseries instruction funcion Refer to 78K 0 Series User s Manual Instruction U12326E When you want to know the electrical characteristics of the 780288 subseries Refer to uPD780226 780228 Data Sheet U11797E separately available When you want to know the application examples of each function of the PD780228 subseries Refer to 78K 0 Series Application Note Fundamental Il U10121E separately available Legend Data representation w
142. lear bit 7 CSO in the A D converter mode register ADMO to 0 and stop A D conversion operation before executing a HALT or STOP instruction 163 CHAPTER 13 STANDBY FUNCTION 13 1 2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with a 1 bit 8 bit memory manipulation instruction RESET input sets OSTS to 04H Therefore when the STOP mode is cleared with RESET input the time until it is cleared is 216 fx Figure 13 1 Oscillation Stabilization Time Select Register Format Symbol 7 0 Address AtReset R W Te mmm me ma Selection of oscillation stabilization 211 fx 410 us 23 fx 1 64 ms 214 fx 3 28 ms 25 fx 6 55 ms 2 6 fx 13 1 ms Others Setting prohibited Caution The wait time after STOP mode clear does not include the time see below from STOP mode clear to clock oscillation start regardless of clearance by RESET input or by interrupt request generation STOP Mode Clear X1 Pin Voltage Waveform 8 Vss Remarks 1 fx Main system clock frequency 2 Values in parentheses apply to operation with fx 5 0 MHz 164 CHAPTER 13 STANDBY FUNCTION 13 2 Standby Function Operations 13 2 1 HALT mode 1 HALT mode set and operating status The HALT mode is set by executing the H
143. n an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format r X A C B E D L H rp AX BC DE HL and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names RO to R7 and RPO Description example MOV A C when selecting C register as r Operation code 0 1 1 1 0 INCW DE when selecting DE register pair as rp Operation code 100001 0 0 L L Register specify code Register specify code 40 CHAPTER 3 CPU ARCHITECTURE 3 4 3 Direct addressing Function This addressing directly addresses the memory indicated by the immediate data in an instruction word Operand format addr16 Label or 16 bit immediate data Description example MOV A OFEOOH when setting laddr16 to Operation code 1 1 1 1 0 OPcode 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 10 FFH Illustration OP code addr16 lower addr16 higher Memory 41 CHAPTER 3 CPU ARCHITECTURE 3 4 4 Short direct addressing 42 Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space to which this addressing is applied is the 256 byte space of addresses FE20H to FF1FH Addresses FE20H to FEFFH constitute a part of the SFR area and the internal high speed RAM is m
144. n in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however FIP32 FIP39 P100 P107 10 Output Port 10 P ch open drain 8 bit high voltage output port Internal pull down resistor can be used by mask option in 1 bit units mask ROM models only uPD78F0228 does not have pull down resistors however Output FIP40 FIP47 CHAPTER 2 PIN FUNCTIONS 2 Pins other than port pins Pin Name Function Valid edge rising falling or both rising and falling can be specified External interrupt request input At Reset Shared with 1 Serial clock input output of serial interface P20 Serial data output of serial interface P21 Serial data input of serial interface P22 Timer input of 8 bit remote control timer TM1 P23 Capture trigger input timer output of 8 bit PWM timer TM50 P24 Capture trigger input timer output of 8 bit PWM timer TM51 P25 FIPO FIP15 FIP16 FIP23 FIP24 FIP31 FIP32 FIP39 40 47 High voltage high current output of FIP controller driver P70 P77 P80 P87 P90 P97 P100 P107 VLoap Pull down resistor connection of FIP controller driver RESET System reset input x1 2 Crystal connection for main system clock oscillation ANIO ANI7 Analog input for A D converter AV op Analog power to A D converter Same potential as
145. n interrupt acknowledge disable state It does not undergo interrupt priority control and has highest priority over all other interrupts If a non maskable interrupt request is acknowledged the contents are saved in the stacks PSW and PC in that order the IE and ISP flags are reset to 0 and the vector table contents are loaded into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution only one non maskable interrupt request is acknowledged after termination of the non maskable interrupt service program execution Figure 12 8 shows the flowchart illustrating how the non maskable interrupt request occurs and is acknowledged Figure 12 9 shows the acknowledge timing of the non maskable interrupt Figure 12 10 shows acknowledge operation of multiple non maskable interrupts 153 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 8 Flowchart of Occurrence and Acknowledge Non Maskable Interrupt WDTM4 1 with watchdog timer mode selected Interval timer Overflow in WDT WDTMS 0 with non maskable interrupt selected Res
146. n reset A bit PSW bit addr16 PC lt PC 4 jdisp8 if PSW bit 1 hen reset PSW bit HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 hen reset HL bit B addr16 B lt B 1 then PC lt PC 2 jdisp8 if B 0 C addr16 C C 1 then PC c PC 2 jdisp8 if C 0 saddr addr16 saddr lt saddr 1 then PC c PC 3 jdisp8 if saddr 0 CPU control RBn RBS1 0 n No Operation IE 1 Enable Interrupt IE lt 0 Disable Interrupt Set HALT Mode Set STOP Mode Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 191 CHAPTER 16 INSTRUCTION SET 16 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ 192 Second Operand CHAPTER 16 INSTRUCTION SET laddr16 HL byte HL B HL C addr16 laddr16 PSW DE HL HL byte HL B HL C x C Note Exceptr A 193 CHAPTER 16 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW
147. nch 2HC EWS4800 series RISC EWS UX V rel 4 0 Cartridge tape QIC 24 Note Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software 205 APPENDIX DEVELOPMENT TOOLS B 4 OS for IBM PC The following OSs for the IBM PC are supported To operate 5 78 0 ID78K 0 and FE9200 refer to C 2 Fuzzy Inference Development Support System Windows Ver 3 0 to Ver 3 1 is necessary Version Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote IBM DOSTM J5 02 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 vNete to 6 2 VNote Note Only English mode is supported Caution Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software 206 APPENDIX DEVELOPMENT TOOLS PACKAGE DRAWINGS OF NQPACK100RB HQPACK100RB AND YQPACK100RB Figure B 2 NQPACK100RB Target Connected Side Package Drawings Reference R je gt NY Tm N Y E 5 ES Mz 5 A EB
148. nd their compatible machines Refer to B 4 3 5 inch 2HC 5 inch 2HC HP9000 series 300 HP UX rel 7 05B Cartridge tape QIC 24 HP9000 series 700 HP UX rel 9 01 Digital audio tape DAT SPARCstation EWS4800 series RISC SunOS rel 4 1 1 EWS UX V rel 4 0 Cartridge tape QIC 24 Note Although MS DOS Ver 5 0 and above have a task swap function this function cannot be used with this software 213 APPENDIX EMBEDDED SOFTWARE C 2 Fuzzy Inference Development Support System FE9000 FE9200 Fuzzy Knowledge Data Preparation Tool Program supporting input of fuzzy knowledge data fuzzy rule and membership function editing edit and evaluation simulation FE9200 operations on Windows Part Number Product Name uSxxxxFE9000 PC 9800 series LA SxxxxFE9200 PC AT and compatible machines FT9080 FT9085 Translator Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to the assembler source program for the RA78K 0 Part Number Product Name uSxxxxFT9080 PC 9800 series LSxxxxFT9085 PC AT and compatible machines FI78KO Fuzzy Inference Module Program executing fuzzy inference Fuzzy inference is executed by linking fuzzy knowledge data converted by translator Part Number Product Name uSxxxxFl78KO PC 9800 series IBM PC AT and compatible machines FD78K0 Fuzzy Inference Debugger
149. nformation Part Number Package Internal ROM 780226 100 pin plastic 14 x 20 mm Mask ROM HPD780228GF xxx 3BA 100 pin plastic QFP 14 x 20 mm Mask ROM uPD78F0228GF 3BANete 100 pin plastic QFP 14 x 20 mm Flash memory Note Under development Remark indicates a ROM code number CHAPTER 1 GENERAL 1 4 Pin Configuration Top View 100 pin plastic QFP 14 x 20 mm LuPD780226GF xxx 3BA 780228GF xxx 3BA 78F0228GF 3BA Note P71 FIP17 O P72 FIP18 P73 FIP19 10099 98 97 96 95 94 93 92 91 9089 88 87 86 85 84 83 82 819 P60 O 1 P61 O 2 O 62 3 P74 FIP20 P63 O 4 P75 FIP21 P64 O 5 P76 FIP22 P65 6 P77 FIP23 P66 O 7 P80 FIP24 P67 O 8 P81 FIP25 P50 P82 FIP26 P51 O P83 FIP27 P52 O P84 FIP28 P53 P85 FIP29 P54 O P86 FIP30 P55 P87 FIP31 P56 O P90 FIP32 P57 P91 FIP33 IC VeP O P92 FIP34 Vsso O P93 FIP35 Vooo O P94 FIP36 P40 O P95 FIP37 P41 O O P96 FIP38 P42 O O P97 FIP39 P43 O P100 FIP40 P44 P101 FIP41 P45 O 102 42 P46 O P103 FIP43 P47 P104 FIP44 POO INTPO P105 FIP45 PO1 INTP1 O P106 FIP46 RESET 107 47 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4950 x10 Vssi AVop 00 10 20 30 40 50 6 O 7 10 11 12 P13 AN P14 AN P15 AN P16 AN x20 P17 AN 22 51 P23 TH
150. ng two modes Operation stop mode Three wire serial I O mode 1 Operation stop mode This mode is used when serial transfer is not performed 2 Three wire serial I O mode with MSB first In this mode 8 bit data is transferred by using three lines serial clock SCK serial output SO and serial input SI Because simultaneous transmission reception operation can be performed in the three wire serial I O mode the processing time of data transfer can be shortened The first bit of the 8 bit data to be transferred is fixed to the MSB The three wire serial I O mode is useful when connecting peripheral I Os or display controller having a clocked serial interface 10 2 Configuration of Serial Interface The serial interface consists of the following hardware Table 10 1 Serial Interface Configuration Register Serial I O shift register 3 5103 Control register Serial operation mode register 3 CSIM3 121 CHAPTER 10 SERIAL INTERFACE Figure 10 1 Serial Interface Block Diagram Internal bus Serial operation SIO3 write mode register 3 o o o gt MODEO Serial I O shift register 3 SIO3 i SO P21 MODEO 1 Sampling circuit SI P22 6 Serial clock counter Clock selector INTCSI3 fx 23 fx 25 1 Serial I O shift register 3 5103 This 8 bit reg
151. nterrupt enable flag is also reset to 0 when the DI instruction or an interrupt request has been acknowledged and is set to 1 when the EI instruction has been executed b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases CHAPTER 3 CPU ARCHITECTURE 3 SP c d f Register bank select flags RBSO and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When ISP 0 the vectored interrupt request specified by the priority specify flag registers PROL and PROH refer to 12 3 3 Priority specify flag registers PROL and PROH to have a low priority is disabled Whether an interrupt request is actually acknowledged is controlled by the status of the interrupt enable flag IE Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution Stack pointer SP This is a 16 bit
152. ntrol registers The following three types of registers control the FIP controller driver Display mode register 0 DSPMO Display mode register 1 DSPM1 Display mode register 2 DSPM2 1 Display mode register 0 DSPMO DSPMO performs the following setting Enables or disables display Number of FIP output pins DSPMO Is set by using a 1 bit or 8 bit memory manipulation instruction The value of this register is set to 10H by RESET input 129 CHAPTER 11 FIP CONTROLLER DRIVER Figure 11 2 Display Mode Register 0 Format Symbol lt 7 gt Address At Reset R W DSPMO SE FOUT4 FOUT3 FOUT2 FOUT1 FOUTO FF90H 10 R W DSPEN Enables or disables FIP Disables Enables Number of FIP output pins 17 24 25 32 33 40 41 48 Others Setting prohibited Cautions 1 Be sure to set bit 6 to 0 2 Do not write data to the bits other than DSPEN when bit 7 DSPEN 1 3 sure to set the output latch of the multiplexed port of a pin used for FIP output to 0 130 CHAPTER 11 FIP CONTROLLER DRIVER 2 Display mode register 1 DSPM1 DSPM1 performs the following setting Blanking width of FIP output signal Number of display patterns DSPM1 is set by using an 8 bit memory manipulation instruction The value of this register is set to 01H by RESET input Figure 11 3 Display Mode Register 1 Format Symbol 7 Address At Reset R W 6 5 4 3 2 1 0 DSPM1 FB
153. o Analog input channel A D converter mode specification register register Internal bus Successive approximation register SAR This register compares the voltage value of the input analog signal with the value of the voltage tap compare voltage from the series resistor string and holds the result of the comparison starting from the most significant bit MSB When the comparison result has been retained to this register up to the least significant bit LSB i e when the A D conversion has been completed the contents of this register are transferred to the A D conversion result register ADCRHO A D conversion result register ADCRHO This register holds the result of the A D conversion Each time the A D conversion has been completed the conversion result is loaded to this register from the successive approximation register SAR ADCRHO is read by using 8 bit memory manipulation instruction The value of this register is initialized to 00H by RESET input Sample amp hold circuit The sample amp hold circuit samples the analog input signals sent from the input circuit one by one and sends them to the voltage comparator It also holds the voltage value of the sampled analog input signal during A D conversion 4 5 6 7 8 CHAPTER 9 A D CONVERTER Voltage comparator The voltage comparator compares the analog input signal with the output voltage of the series resistor string
154. o be the rising edge falling edge or both the rising and falling edges 2 2 2 P10 through P17 Port 1 P10 through P17 constitute an 8 bit input port port 1 This port is also used to input analog signals to the internal A D converter The following operation modes can be specified in 1 bit units 1 Port mode Port 1 functions as an 8 bit input port in this mode 2 Control mode P10 through P17 function as analog input pins ANIO through ANI7 of the A D converter 2 2 3 P20 through P25 Port 2 P20 through P25 constitute a 6 bit I O port port 2 These pins also have functions to input output data of the serial interface clock and timer signals The following operation modes can be specified in 1 bit units 1 Port mode In this mode P20 through P25 function as a 6 bit I O port This port can be set in the input or output mode in 1 bit units by using the port mode register 2 PM2 When the port is used as an input port the internal pull up resistor can be used if so specified by the pull up resistor option register 2 PU2 2 Control mode In this mode P20 through P25 are used to input output serial interface data clock and timer signal and input timers capture trigger signals SI SO These are I O pins of the serial data of the serial interface b SCK This is an I O pin of the serial clock of the serial interface 12 CHAPTER 2 PIN FUNCTIONS c TH Timer input pin of the 8 bit remote control tim
155. of TM5n is incremented The edge can be selected from rising or falling If the measured value of TM5n coincides with the value of the 8 bit compare register 5n CR5n 5 is cleared to 0 and an interrupt request signal INTTM5n is generated After that INTTM5n is generated each time the value of TM5n coincides with the value of CR5n Remark n 0or 1 Figure 7 5 Timing of External Event Counter Operation with rising edge specified oe AER c mi RT P C 2 B E 0 18 count valie A OOH X 01H X 02H X 03HX 04 X 05HX N Xoon X01H 03H Y CR5n N INTTM5n s 0 1 92 CHAPTER 7 8 BIT PWM TIMERS 7 4 3 Square wave 8 bit resolution output operation Asquare wave of any frequency can be output at intervals specified by the value set in advance to the 8 bit compare register 5n CR5n If the bit 0 TOE5n of the 8 bit timer mode control register 5n TMC5n is set 1 the output status of TlO5n is inverted at intervals specified by the count value set in advance to CR5n In this way a square wave of any frequency duty 5096 can be output Remark n 0or 1 Setting 1 Set each register Set 0 to port latch and port mode register TCL5n CR5n TMC5n Selects count clock Compare value Clear amp start mode in which 5 is cleared and started when its value coincides with that of CR5n LVS5n LVR5n Status setting of timer output F F 1 0 High level output
156. on although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input output port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 66 CHAPTER 4 PORT FUNCTIONS 4 5 Selecting Mask Option The mask ROM models have the following mask options The uPD78F0228 does not have mask options Table 4 4 Comparison between Mask Options of Mask
157. one instruction of the main processing has been executed the pending interrupt is acknowledged Multiple interrupts are not acknowledged while the non maskable interrupt is processed Table 12 4 shows interrupt requests enabled for multiple interrupts Figure 12 14 shows multiple interrupt examples Table 12 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Request Non maskable Maskable Interrupt Request Interrupt Request Interrupt being Serviced Non maskable interrupt Maskable interrupt Software interrupt Remarks 1 O Multiple interrupt enable x Multiple interrupt disable 2 ISP and IE are flags included in PSW ISP 0 High priority interrupt servicing ISP 1 Interrupt request is not acknowledged or low priority interrupt servicing IE20 Interrupt request acknowledge disabled IE 1 Interrupt request acknowledge enabled 3 xxPR is a flag included in PROL and PROH xxPR 0 High priority flag xxPR 1 Low priority flag 159 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12 14 Multiple Interrupt Examples Example 1 Two multiple interrupts are generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing RETI Two interrupt requests INTyy and INTzz are acknowledged and multiple interrupts are generated while interrupt INTxx request is processed Before each interrupt request is acknowledged the EI inst
158. ontrol mode In this mode P90 through P97 function as the output pins of the FIP controller driver FIP32 through FIP39 2 2 10 P100 through P107 Port 10 P100 through P107 constitute an 8 bit output port These pins are also used as FIP controller driver output pins The following operation modes can be specified in 1 bit units 1 Port mode P100 through P107 function as an 8 bit output port in this mode These pins are P ch open drain pins Pull down resistors can be connected to these pins of the mask ROM models by mask option The 078 0228 does not have pull down resistors 2 Control mode In this mode P100 through P107 function as the output pins of the FIP controller driver FIP40 through FIP47 2 2 11 FIPO through FIP15 These are the output pins of the FIP controller driver 2 2 12 Vioap This pin connects a pull down resistor to the FIP controller driver 2 2 13 AVpp This pin supply an analog voltage to the A D converter Always keep this pin at the same potential as the pin even when the A D converter is not used 2 2 14 AVss This is the ground pin of the A D converter Always keep this pin at the same potential as the Vss pin even when the A D converter is not used 2 2 15 RESET This pin inputs an active low system reset signal 2 2 16 X1 and X2 These pins connect a crystal resonator for main system clock oscillation To supply an external clock input it to X1 and input a signal reverse to that inpu
159. or RD Port 8 read signal WR Port 8 write signal 60 CHAPTER 4 PORT FUNCTIONS 4 2 9 Port9 Port 9 is an 8 bit input output port with output latch When using this port as an output port the value assigned to the output latch P90 through P97 is output When it is used as an input port set the output latch P90 through P97 to 0 and read the port read PLR90 through PLR97 On chip pull down resistors can be connected in 1 bit units with the mask option The u PD78F0228 has no pull down resistor In addition FIP controller driver output is provided as an alternate function RESET input sets port 9 to input mode Figure 4 11 shows a block diagram of port 9 Figure 4 11 P90 to P97 Block Diagram Port read PLR90 PLR97 Output latch P90 P97 Alternate function Internal bus P90 FIP32 9 P97 FIP39 __o 0 0 Mask Option Mask ROM model only 78 0228 has no pull down resistor RD Port 9 read signal WR Port 9 write signal 61 CHAPTER 4 PORT FUNCTIONS 4 2 10 Port 10 Port 10 is an 8 bit output only port On chip pull down resistors be connected in 1 bit units with the mask option in case of mask ROM model The uPD78F0228 has no pull down resistor In addition FIP controller driver segment digit output is provided as an alternate function Figure 4 12 shows a block diagram of port 10 Figure 4 12 P100 to P107 Block Diagram
160. or RESET signal can be generated Table 8 1 Hang up Detection Time of Watchdog Timer Hang up Detection Time fx 5 0 MHz Hang up Detection Time fx 5 0 MHz 212 x 1 fx 216 x 1 fx 213 x 1 fx 217 x 1 fx 21 x 1 fx 218 x 1 fx 215 x 1 fx 220 x 1 fx fx Main system clock oscillation frequency 2 Interval timer mode In this mode the watchdog timer generates an interrupt request at fixed time intervals Table 8 2 Interval Time Interval Time fx 2 5 0 MHz Interval Time fx 2 5 0 MHz 212 x 1 fx 216 x 1 fx 213 x 1 fx 217 x 1 fx 214 x 1 fx 218 x 1 fx 215 x 1 fx 220 x 1 fx fx Main system clock oscillation frequency 101 CHAPTER 8 WATCHDOG TIMER 8 2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware Table 8 3 Configuration of Watchdog Timer Configuration Control register Oscillation stabilization time select register OSTS Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 8 1 Watchdog Timer Block Diagram Clock Divided 427 input Divider clock Output INTWDT control select circuit circuit Divided mode select circuit St Oscillation stabilization Watchdog timer time select register clock select register control circuit o RESET o WDT mode signal Watchdog timer mode register Internal bus 102 CHAPTER 8 WATCHDOG TIMER 8 3 Registers Controlling W
161. or not can be selected by using the key scan timing insertion specification flag KSM bit 6 of the display mode register 2 DSPM2 11 5 2 Key scan data Data stored to ports 7 through 10 are output from the FIP16 through FIP47 pins during key scan timing Caution If scanning is performed in such a manner that both a segment and a digit turn ON during key scan timing the display may flicker 135 CHAPTER 11 FIP CONTROLLER DRIVER 11 6 Leakage Emission of Fluorescent Indicator Panel Leakage emission may take place when a fluorescent indicator panel is driven by the uPD780228 subseries The possible causes of this leakage emission are as follows 1 Short blanking time Figure 11 7 shows the signal waveforms of a 2 digit display where the first digit TO lights and the second digit remains dark If the blanking time is too short as shown in this figure the T1 signal rises before the segment signal is deasserted causing leakage emission Generally the blanking time must be about 20 us Determine the set value of the display mode register 1 DSPM1 taking this into consideration Figure 11 7 Leakage Emission Because of Short Blanking Time Blanking width TO T1 Leakage emission occurs 136 CHAPTER 11 FIP CONTROLLER DRIVER 2 Segment grid capacitance of fluorescent indicator panel Even if a sufficiently long blanking time is ensured as shown in Figure 11 9 leakage emission may still occur This is because t
162. ority specification flag registers PROL PROH Notes 1 Of the hardware units only the contents of the PC are undefined during reset input or oscillation stabilization time wait The statuses of the other hardware units are the same as those after reset 2 The status after reset is retained in the standby mode 3 Be sure to set when using the uPD780228 4 After reset be sure to set this bit to OBH 173 174 CHAPTER 15 uPD78F0228 The uPD78F0228 has a flash memory to which a program can be written or whose contents can be erased with the device mounted on the PC board of the target system Table 15 1 shows the differences between the flash memory model uPD78F0228 and mask ROM models uPD780226 and 780228 Table 15 1 Differences between uPD78F0228 and Mask ROM Models 78 0228 Mask ROM Models Internal ROM structure Flash memory Mask ROM Internal ROM capacity 60K bytes uUPD780226 48K bytes LP D780228 60K bytes Changing internal ROM capacity by memory PossibleNote Impossible size select register IMS Internal expansion RAM size select register IXS Provided Not provided IC pin Not provided Provided VPP pin Provided Not provided Mask option of connecting pull up resistors Not provided Provided to P50 through P57 and P60 through P67 Mask option of connecting pull down resistors Not provided Provided to P70 through P77 P80 through P87 P90 through P97 and P10
163. owering the display luminance also has an effect of suppressing the leakage emission Figure 11 8 Leakage Emission Caused by Csc uPD780228 5V Voo T t 1L E t I9 FIP 1 TO Segment grid filament R R Ek Vioap Ex Cutoff voltage R Internal pull down resistor 137 138 CHAPTER 11 FIP CONTROLLER DRIVER Figure 11 9 Leakage Emission Caused Csc TO T1 S0 CHAPTER 11 FIP CONTROLLER DRIVER 11 7 Calculation of Total Power Dissipation The following three power dissipation are available for the 780208 subseries The sum of the three power dissipation should be less than the total power dissipation Pr refer to Figure 11 10 80 or less of ratings is recommended lt gt CPU power dissipation Calculate MAX x Ipp MAX 2 Output pin power dissipation Power dissipation when maximum current flows into each FIP output pin 3 Pull down resistor power dissipation Power dissipation by pull down resistor incorporated in FIP output pin Figure 11 10 Total Power Dissipation Pr TA 40 to 85 800 600 400 200 Total power dissipation Pr mW 40 0 40 80 Temperature C The following is how to calculate total power dissipation for the example in Figure 11 11 Example Assume the following conditions Vpp 5 5 V 5 0 MHz oscillation Supply current 21 0 mA FIP output 11 gri
164. p BC DE or HL 4 Exceptr A Remark One instruction clock cycle is one cycle of the CPU clock selected by the processor clock control register PCC 185 CHAPTER 16 INSTRUCTION SET Instruction Operands Operation Group A byte A CY A byte saddr byte saddr lt saddr byte A r A CY A r CY r A A saddr A CY lt A saddr A addr16 A CY A addr16 A HL A CY lt HL A HL byte A CY lt A HL byte A CY A HL B A HL C A CY A HL C A byte A CY A byte CY saddr byte saddr CY lt saddr byte CY A r A CY A r CY nA CY r A CY 8 bit A saddr A CY A saddr C operation A laddr16 8 A CY A addr16 C A HL A CY A HL CY A HL byte A CY A HL byte CY A A CY A HL A HL C A CY A HL C C A byte A A byte saddr byte saddr saddr byte saddr lt A saddr A 16 lt A addr16 A HL A lt HL A HL byte lt A HL byte A A HL A HL C A HL Notes 1 When the internal high speed RAM area is accessed
165. pin The I O and FIP of the uPD78044H were enhanced Display output total 48 78K 0 80 pin An N ch open drain I O was added to the PD78044F Display output total 34 Series L 80 pin Basic subseries for driving FIP Display output total 34 LCD drive 100 pin The SIO of the uPD78064 was enhanced and ROM RAM capacity increased 100 pin EMl noise reduced version of the 78064 100 pin Basic subseries for driving LCDs On chip UART IEBus supported E 80 pin EMI noise reduced version of the 78098 L 80 pin An IEBus controller was added to the 78054 Meter control 80 i General purpose version of automobile meter driving controller of theu PD780805 1 100 On chip automobile meter driving controller driver 64 pin On chip PWM output LV digital code decoder and Hsync counter Note Under planning CHAPTER 1 GENERAL The following lists the main functional differences between subseries products Functi Timer bit 10 bit 8 bi i unction ROM 8 bit 10 bit 8 bit Serial Interface rd Subseries Name Capacity 16 bit Watch A D A D D A Expansion uPD78075B 32K 40K 3ch UART 1ch uPD78078 48 60 uPD78070A uPD780018 48K 60K 2ch time division 3 wire 1ch uPD780058 24K 60K 3ch time division UART 1ch uPD78058F 48K 60K UART 1ch uPD78054 16K 60K uPD780034 8K 32K Sch UART 1ch uPD780024 time division 3 wire 1ch uPD78014H 2c
166. pines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 65 250 3583 Fax 1 800 729 9288 1 408 588 6130 NEC Electronics Europe GmbH ectronics Hong Kong Ltd Corporation Technical Documentation Dept Seoul Branch Semiconductor Solution Engineering Division Fax 49 211 6503 274 Fax 02 528 4411 Technical Information Support Dept Fax 044 548 7900 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 889 1689 Fax 02 719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Acceptable Clarity Technical Accuracy Organization
167. put 2 Mode in which two timers are cascaded 16 bit resolution cascade mode When the two PWM timers are cascaded they operate as a 16 bit timer event counter In this mode the following functions can be used Interval timer with 16 bit resolution External event counter with 16 bit resolution Square output with 16 bit resolution 83 CHAPTER 7 8 BIT PWM TIMERS 7 2 Configuration of 8 Bit PWM Timers The 8 bit PWM timers consist of the following hardware Table 7 1 Configuration of 8 Bit PWM Timers Item Configuration Timer register 8 bit counter 5n TM5n Register 8 bit compare register 5n CR5n Timer output 5 Control registers Timer clock select register 5n TCL5n 8 bit timer mode control register 5n TMC5n Figure 7 1 8 Bit PWM Timers Block Diagram Internal bus 8 bit compare register 5n CR5n Coincidence 8 bit counter 5n OVF TM5n Clear INTTM5n Mask circuit 50 24 51 25 Selector Selector 219 TIO50 P24 6 TIO51 P25 8 bit timer mode control register 5n C Timer clock select register 5n Internal bus 0 1 84 1 2 CHAPTER 7 8 BIT PWM TIMERS 8 bit counter 5n TM5n n 0 or 1 TM5n is an 8 bit read only register that counts the count pulse The value of this counter is incremented
168. r Clock Select Register 104 8 4 Watchdog Timer Mode Register Format 9 1 A D Converter Block 110 9 2 A D Converter Mode Register Format 112 9 3 Analog Input Channel Specification Register Format 113 9 4 Basic Operation of A D 115 9 5 Relation between Input Analog Voltage and A D Conversion Result 2116 9 6 A D Conversion by Software 117 9 7 Example of Reducing Current Consumption in Standby 118 9 8 Processing of Analog Input Pin 119 9 9 A D Conversion End Interrupt Request Generation Timing 120 9 10 Processing o AVBD PID iind ceti d en eie icem 120 10 1 Serial Interface Block 122 10 2 Format of Serial Operation Mode Register 0 123 10 3 Timing in Three Wire Serial I O Mode 11 1 FIP Controller Driver Block gt 128 11 2 Display Mode Register 0 Format 11 3 Display Mode Register 1 Format rtp ennt 11 4 Display Mode Register Format ente ee ttp edicere e ede ee tid ei pa a iade tas 11 5 Blanking Width of FIP Output Signal 11 6 Relation between Address Location of Display Data Memory and FIP Output with 48 FIP output pins and
169. ransfer is started at falling edge of SCK 3 Transfer start 126 Serial transfer is started when data is assigned to or read from the serial I O shift register 5103 if the following two conditions are satisfied Operation control bit of SIO3 CSIE3 1 If the internal serial clock is stopped or SCK is high after 8 bit serial transfer Transmission or transmission reception mode Transfer is started if SIO3 is written when CSIE3 1 and MODEO 0 Reception mode Transfer is started if SIO3 is read when CSIE3 1 and MODEO 1 Caution Transfer is not started even if CSIE3 is set to 1 after data has been written to SIO3 Serial transfer is automatically stopped and an interrupt request flag CSIIF3 is set when 8 bit transfer has been completed CHAPTER 11 FIP CONTROLLER DRIVER 11 1 Function of FIP Controller Driver The FIP controller driver of the u PD780228 subseries has the following functions 1 Can output display signals DMA operation by automatically reading display data 2 The pins not used for FIP display can be used as I O port or output port pins FIP 16 through FIP47 pins only 3 Luminance can be adjusted 8 steps by display mode register 1 DSPM1 4 Hardware for key scan application Generates an interrupt signal INTKS indicating key scan timing Timing in which key scan data is output can be detected by key scan flag KSF Whether key scan timing is inserted or not can be selected
170. re RA78K 0 Assembler package This is a program to convert a program written in mnemonics into an object code executable with a microcontroller Further this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization Used in combination with optional device file DF780228 Part Number 78 0 CC78K 0 C Compiler package This is a program to convert a program written in C language into an object code executable with a microcontroller Used in combination with optional assembler package RA78K 0 and device file DF780228 Part Number 78 0 DF780228Note 1 2 Device file This is a file containning the information inherent to the device Used in combination with optional RA78K 0 CC78K 0 5 78 0 or 78 0 Part Number uSxxxxDF780228 CC78K 0 L C Library source file A function source program configurating object library included in C compiler CC78K 0 Necessary for changing object library included in CC78K 0 according to customer s specifications Part Number uSxxxxCC78K0 L Notes 1 The DF780228 can be used for any of the RA78K 0 CC78K 0 SM78KO and ID78KO products 2 Under development Remark xxxx in the part number differs depending on the host machine and OS used LA SxxxxRA78KO0 USxxxxCC78K0 USxxxxDF780228 LSxxxxCC78K0 L Host Machine Distribution Medium PC 9800 series
171. ruction is always issued and the interrupt request is enabled Example 2 Multiple interrupt is not generated because of its priority Main Processing INTxx INTyy Servicing Servicing INTyy PR 1 INTyy that occurs while INTxx is processed is not acknowledged and a multiple interrupt is not generated because the priority of INTyy is lower than that of INTxx INTyy is reserved and is acknowledged after one instruction of the main processing has been executed PR 0 High priority interrupt PR 1 Low priority interrupt IE 0 Interrupt acknowledge disabled 160 CHAPTER 12 INTERRUPT FUNCTIONS Example 3 Multiple interrupt is not generated because an interrupt is not processed Main Processing INTxx INTyy Servicing Servicing Because interrupts are not enabled the El instruction is not issued in interrupt processing interrupt request INTyy is not accepted and therefore the interrupt is not nested INTyy request is kept pending and is accepted after main processing 1 instruction has been executed PR 0 High priority level IE 0 Disables accepting interrupt request 161 CHAPTER 12 INTERRUPT FUNCTIONS 12 4 5 Interrupt request reserve Some instructions keep the acceptance of an interrupt request if one occurs pending until execution of the next instruction is completed These instructions that keep interrupt requests pending are listed below MOV PSW byte MOV A P
172. rupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Operation code 1 07 51 1 0 1 47 48 CHAPTER 4 PORT FUNCTIONS 4 1 Port Functions The uPD780228 subseries incorporates eight input ports eight output ports and 56 input output ports Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as built in hardware input output pins Figure 4 1 Port Types Port 0 Port 6 Port 7 Port 1 Port 2 Port 8 Port 9 Port 4 Port 10 Port 5 49 10 17 CHAPTER 4 PORT FUNCTIONS Table 4 1 Port Function Function Port 0 2 bit I O port Can be set in input or output mode in 1 bit units Internal pull up resistor can be used via software when this port is used as input port Port 1 8 bit input port Shared with ANIO ANI7 P20 P25 Port 2 6 bit I O port Can be set in input or output mode in 1 bit units Internal pull up resistor can be used via software when this port is used as input port SCK P40 P47 P50 P57 P60 P67 P70 P77 Port 4 8 bit I O port Can be set in input or output mode in 1 bit units Can directly drive LED Internal pull up resistor can be used via software when this port is used as input port
173. s a trademark of Open Software Foundation Inc TRON is an abbreviation of The Real time Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed uPD78F0228GF 3BA The customer must judge the need for license u PD780226GF xxx 3BA 780228GF xxx 3BA The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the po
174. s cleared the actual overflow time is up to 0 5 shorter than the set time Remark x don t care 105 CHAPTER 8 WATCHDOG TIMER 8 4 Operation of Watchdog Timer 8 4 1 Operation as watchdog timer The watchdog timer operates to detect a program hang up when bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 The count clock of the watchdog timer hang up detection time interval can be selected by bits 0 through 2 WDCSO through WDCS2 of the watchdog timer clock select register WDCS By setting bit 7 RUN of WDTM the watchdog timer starts the count operation If RUN is set to 1 again within the specified hang up detection time interval after the counting operation has been started the watchdog timer is cleared and starts the count operation again If RUN is not set to 1 and the hang up detection time is exceeded the system is reset or the non maskable interrupt request is generated depending on the value of bit WDTMS of WDTM The watchdog timer continues its operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 and clear the watchdog timer before executing the STOP instruction to set the STOP mode Caution The actual hang up detection time may be up to 0 5 shorter than the set time Table 8 4 Hang up Detection Time of Watchdog Timer 0 1 1 215 1 6 55 ms 1 0 0 216 fx 13 1 ms 1 1 x 26 2 ms x 52 4 ms x 210 ms Remarks 1 fx M
175. sed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Exceptr A Remark One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 187 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Operation Group AX word AX CY AX word 16 bit AX word AX CY AX word operation AX word AX word Multiply AX A x X divide AX Quotient Remainder AX rer 1 saddr saddr 1 Increase mere decrease saddr lt saddr 1 rp rp 1 e rp 1 CY A7 Ao Am 1 Am x 1 CY Ao Az 1 Am x 1 CY lt Ao lt CY 1 Am x 1 CY lt CY 1 Am x 1 Rotation lt HL 3 0 lt HL 7 4 lt 0 HL 3 0 lt HL z 4 0 lt HL 7 4 HL 3 0 0 1 7 4 lt HL 3 0 Decimal Adjust Accumulator after BCD Addition correction Decimal Adjust Accumulator after Subtract CY saddr bit CY lt saddr bit CY sfr bit CY lt sfr bit CY A bit CY lt A bit CY PSW bit CY PSW bit CY HL bit CY lt HL bit saddr bit CY saddr bit CY str bit CY sfr bit CY A bit CY A bit CY PSW bit CY PSW bit CY
176. spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with short direct addressing Operand format sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PMO A when selecting PMO FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 O 20H sfr to offset Illustration OP code sfr offset SFR Effective address 44 CHAPTER 3 CPU ARCHITECTURE 3 4 6 Register indirect addressing Function The addressing addresses the memory with the contents of a register pair specified as an operand The register pair to be accessed is specified by the register bank select flags RBSO and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format mm 7 Description example MOV A DE when selecting DE as register pair Operation code D 305 2 205 01 Illustration Memory address specified by register pair DE Contents of addressed memory are transferred 45 CHAPTER 3 CPU ARCHITECTURE 3 4 7 Based addressing Function This addressing addresses the memory by adding 8 bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition The HL register pair to be accessed is in t
177. splay mode register 2 132 External interrupt falling edge enable register 151 External interrupt rising edge enable register 151 Interrupt request flag register OH 148 Interrupt request flag register OL 148 Internal memory size select register 176 Internal expansion RAM size select register 177 Interrupt mask flag register OH 149 Interrupt mask flag register OL 149 Oscillation stabilization time select register 103 Port 0 51 Port 1 53 Port 2 54 Port 4 55 Port 5 56 Port 6 58 Port 7 59 215 5 W 216 9 10 PLR7 PLR8 PLR9 PCC PMO PM2 PM4 PM5 PM6 PROH PROL PSW PUO PU2 PU4 SIO3 TCL50 TCL51 TM50 51 TMC1 TMC50 TMC51 WDCS WDTM APPENDIX D REGISTER INDEX Port 8 60 Port 9 61 Port 10 62 Port read 7 59 Port read 8 60 Port read 9 61 Processor clock control register 70 Port mode register 0 64 Port mode register 2 64 Port mode register 4 64 Port mode register 5 64 Port mode register 6 64 Priority specify flag register OH 150 Priority specify flag register OL 150 Program status word 28 152 Pull up resistor option register 0 65 Pull up resistor option register 2 65 Pull up resistor option register 4 65 Serial I O shift register 1 122 Timer clock sele
178. ssibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based ona customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers int
179. ssing of Data Memory uPD780228 Special function registers SFR 256 x 8 bits addressing General purpose registers 32 x 8 bits ister addressing Internal high speed RAM 1024 x 8 bits Short d irect addressing Cannot be used FIP display RAM 96 x 8 bits Cannot be used Internal expansion RAM 512 x 8 bits Cannot be used Internal ROM 61440 x 8 bits Direct addressing Register indirect addressing Based addressing Based indexed addressing FFFFH F600H F5FFH F000H EFFFH 0000H CHAPTER 3 CPU ARCHITECTURE Figure 3 6 Addressing of Data Memory uPD78F0228 Special function registers SFR 256 x 8 bits addressing General purpose registers 32 x 8 bits ster addressing Internal high speed RAM 1024 x 8 bits Short d irect addressing Cannot be used FIP display RAM 96 x 8 bits Cannot be used Internal expansion RAM 512 x 8 bits Cannot be used Flash memory 61440 x 8 bits Direct addressing Register indirect addressing Based addressing Based indexed addressing 27 CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers uPD780228 subseries units incorporate the following processor registers 3 2 1 Control registers The control registers control the program sequence statuses and stack memory A program counter PC a program status word PSW
180. st acknowledge is disabled the next address instruction is executed Figure 13 4 STOP Mode Release by Interrupt Request Generation STOP Instruction Wait Time set by OSTS m Standby Y Release Signal Operating Oscillation Stabilization Operating Mode STOP Mode Wait Status Mode Oscillation Clock Oscillation Stop Oscillation Remark broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 169 b Release by RESET input CHAPTER 13 STANDBY FUNCTION The STOP mode is cleared and after the lapse of oscillation stabilization time reset operation is carried out Figure 13 5 Release by STOP Mode RESET Input Wait STO 2161341 ms Instruction Y RESET Signal Oscillation Operating Reset Stabilization Operating Mode STOP Mode Period Wait Status Mode Clock Oscillation Oscillation Stop Oscillation Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 5 0 MHz Table 13 4 Operation after STOP Mode Release Release Source Maskable interrupt request Operation Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution STOP mode hold RESET input x Don t care 170 Reset processing CHAPTER 14 RESET FUNCTION 14 1 Reset Function
181. t Output disable enable O IN OUT IN OUT Output disable Input enable Type 8 Type 13 K Medium voltage input buffer Pull up 0 IN OUT enable Do data output disable J gt n on IN OUT Output disable Medium voltage input buffer 17 14 CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin Input Output Circuit List 2 2 Type 15 F 1 bur gt Option Vioap 14 F OUT i O Voan 18 CHAPTER 3 CPU ARCHITECTURE 3 1 Memory Space Each model in the PD780228 subseries can access a memory space of 64K bytes Figures 3 1 through 3 3 show the memory map Figure 3 1 Memory Map uPD780226 Special function registers SFR 256 x 8 bits General purpose registers 32 x 8 bits Internal high speed RAM 1024 x 8 bits FBOOH FAFFH BFFFH Cannot be used FA60H Program area Data memory zu Space FIP display RAM 1000H 96 x 8 bits OFFFH FA00H F9FFH CALLF entry area Cannot be used F800H 0800H F7FFH 07FFH Internal expansion RAM 512 x 8 bits Program area F600H F5FFH 0080H Cannot be used 007FH C000H BFFFH CALLT table area 0040H Program memory Internal ROM 003FH Space 49152 x 8 bits Vector table
182. t compare register 5n CR5n be sure to stop the timer operation 2 Even when the timers are cascaded if the count value of the high order timer coincides with the value of CR5n INTT5n of the high order timer is generated unless masked Be sure to mask and disable the interrupt of the high order timer 3 Set TCE5n of the high order timer first and then that of the low order timer 4 The counting can be restarted or stopped by setting 1 or 0 to TCE5n of only the low order timer Remark n 0 or 1 97 98 CHAPTER 7 8 BIT PWM TIMERS Figure 7 8 shows an example of the timing in the 16 bit resolution cascade mode Figure 7 8 16 Bit Resolution Cascade Mode Count das COC eee eee eee 50 ToT TESIWHT 777 TESDURT 777 TFFATOORTOTHT LA TO 51 CR50 N CR51 50 51 50 _ pc TIO50 Interval time 1 1 i i Operation enabled Interrupt request Operation Count starts generated stopped Level inverted Counter cleared CHAPTER 7 8 BIT PWM TIMERS 7 5 Notes on 8 Bit PWM Timers 1 Error on starting timer The time until the coincidence signal is generated after the timer has been started includes an error of up to 1 clock because the 8 bit counter n TM5n n 0 or 1 is started in asynchronization with the count pulse Figure 7 9 Start Timing of 8 Bit Counter 5n TM5n Count pulse 5 count val
183. t input input input output Output input Input output Note setting of PMxx varies depending on the clock selected by bits 1 and 0 SCL31 and SCL30 of the serial operation mode register CSIMS Internal clock SCL31 SCL30 00 0 External clock SCL31 SCL30 00 1 Remark x Don t care PMxx Port mode register Pxx Port output latch 63 CHAPTER 4 PORT FUNCTIONS Figure 4 13 Port Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address At Reset R W PMO 1 1 1 1 1 1 1 00 FF20H FFH R W PM2 1 1 PM25 24 PM23 PM22 21 PM20 FF22H FFH R W PM4 47 46 45 44 PM43 42 PM41 PM40 FF24H FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 F25H FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R W Pmn Pin Input Output Mode Selection 0 0 1 m 2 0 5 4 6 0 7 Output mode output buffer ON Input mode output buffer OFF CHAPTER 4 PORT FUNCTIONS 2 Pull up resistor option registers PUO PU2 PU4 This register is used to set whether or not to use an internal pull up resistor of pins at ports 0 2 4 in 1 bit units A pull up resistor is internally used at bits which are set to the input mode at a bit where on chip pull up resistor use has been specified with PUO PU2 and PU4
184. t to X1 to X2 14 CHAPTER 2 PIN FUNCTIONS 2 2 17 through Vpp2 supplies a positive voltage to the ports supplies a positive voltage to the internal function blocks other than the ports analog block and FIP controller driver Vpp2 supplies a positive voltage to the FIP controller driver 2 2 18 Vsso and Vssi Vsso is the ground pin for the ports Vssi is the ground pin for the internal function blocks other than the ports and analog block 2 2 19 VPP uPD78F0228 only A high voltage is applied to this pin when the flash memory programming mode is used and when a program is written or verified Directly connect this pin to Vss in the normal operation mode 2 2 20 IC Mask ROM product only The IC Internally Connected pin sets a test mode in which theuPD780226 and 780228 are tested before shipment Usually connect the IC pin directly to Vss with as short a wiring length as possible If there is a potential difference between the IC and Vss pins because the wiring length between the IC and Vss pin is too long or external noise is superimposed on the IC pin your program may not run correctly O Directly connect the IC pin to the Vss Vss1_ IC NS Keep the wiring length as short as possible 15 CHAPTER 2 PIN FUNCTIONS 2 3 I O Circuits of Pins and Connections of Unused Pins Table 2 1 shows the I O circuit types of the respective pins and the recommended connections of each pin wh
185. ternal program memory space The internal program memory space stores programs and table data Usually this space is accessed by program counter PC Each model in the 0780228 subseries has an internal ROM or flash memory of the following capacity Table 3 1 Internal ROM Capacity Part Number Internal ROM uPD780228 Structure Capacity uPD780226 Mask ROM 49152 x 8 bits 61440 x 8 bits uPD78F0228 Flash memory The following areas are allocated to the internal program memory space 1 Vector table area A 64 byte area of addresses 0000H through 003FH is reserved as a vector table area Program start addresses to which execution is to branch when the RESET signal is input or when an interrupt request is generated are stored in this area Of a 16 bit address the low order 8 bits are stored to an even address and the high order 8 bits are stored to an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request RESET Input Vector Table Address Interrupt Request INTKS INTWDT INTCSIS INTPO 50 51 10 INTAD INTTM11 2 CALLT instruction table area BRK The 64 byte area 0040H through 007FH can be used to store the subroutine entry addresses of the 1 byte call instruction CALLT 3 CALLF instruction entry area From an area of 0800H through OFFFH a subroutine can be directly call
186. ue OOH 04H T Timer starts 0 1 2 Operation after changing compare register during timer count operation If the value to which the current value of the 8 bit compare register 5n CR5n is changed is less than the value of the 8 bit timer register 5n the timer continues counting overflows and restarts counting from 0 If the new value of CR5n M is less than the old value N the timer must be restarted after CR5n has been changed Remark n O0 or 1 Figure 7 10 Timing after Changing Compare Register Value during Timer Count Operation Count pulse Ix CR5n N X 71 M 5 count value __ 02H N gt X gt M 0 1 Caution Except when 5 input is selected be sure to clear TCE5n to 0 to set the stop status n 0 or 1 3 Reading TM5n during timer operation Because the selected clock is temporarily stopped when TM5n n 0 or 1 is read during operation select clock with a long high low level 99 100 CHAPTER 8 WATCHDOG TIMER 8 1 Function of Watchdog Timer The watchdog timer has the following functions Watchdog timer Interval timer Selection of oscillation stabilization time Caution Select whether the watchdog timer is used in the watchdog timer mode or interval timer mode by using the watchdog timer mode register WDTM 1 Watchdog timer mode In this mode the watchdog timer detects a program hang up On detection of hang up the non maskable interrupt
187. ue of IMS 780226 CCH uPD780228 CFH 176 CHAPTER 15 4PD78F0228 15 2 Internal Expansion RAM Size Select Register The internal expansion RAM size select register IXS specifies the internal expansion RAM capacity IXS is set by using an 8 bit memory manipulation instruction The value of this register is set to OCH by RESET input Caution sure to set OBH to IXS in the initial settings of the program Because XS is set to at RESET be sure to set the register to OBH again after reset Figure 15 2 Internal Expansion RAM Size Select Register Format Symbol 7 Address At Reset R W IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAMO Selects internal expansion RAM capacity 512 bytes Others Setting prohibited IXS is not provided on the uPD780226 and 780228 However the operation is not affected even if an instruction that writes data to IXS is executed on the uPD780226 and 780228 177 CHAPTER 15 4PD78F0228 15 3 Flash Memory Programming The flash memory can be written with the device mounted on the target system on board To write the flash memory connect a dedicated flash writer Flashpro Il part number FL PR2 to the host machine and target system The flash memory can be also written on a flash memory writing adapter connected to the Flashpro Il Remark Flashpro Il is a product of Naito Densei Machida Mfg Co Ltd 15 3 1 Selecting communication mode The flash memory is written by using the Flas
188. ulatable Bit Units At Reset 1 bit 8 bits 16 bits Port 0 PO Port 1 1 Port 2 P2 Port 4 P4 Port 5 PS Port 6 P6 7 8 9 7 8 9 Port 10 P10 Port read 7 PLR7 Port read 8 PLR8 Port read 9 PLR9 8 bit capture register 10 CP10 Undefined O O O O O O O OJO O O OO 00H 8 bit capture register 11 CP11 8 bit compare register 50 CR50 Undefined 8 bit compare register 51 CR51 8 bit counter 50 TMS 50 8 bit counter 51 TM51 00H A D conversion result register ADCRHO Undefined Serial I O shift register SIO3 Port mode register 0 PMO Port mode register 2 PM2 Port mode register 4 PM4 Port mode register 5 PM5 Port mode register 6 6 Pull up resistor option register 0 PUO Pull up resistor option register 2 PU2 Pull up resistor option register 4 PU4 Watchdog timer clock select register WDCS External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN Timer mode control register 1 TMC1 8 bit timer mode control register 50 TMC50 Timer clock select register 50 TCL50 8 bit timer mode control register 51 TMC51 Timer clock select register 51 TCL51 A D converter mode register ADMO Analog input channel specification register ADSO mimimimimimimimimimimimimimimimimimimimimimimimimimimimimimimim
189. unt starts Capture Capture 1 Capture Capture 1 I ital V V V V 1 OVF1 i ES 10 t Cleared by software Remark 10 01 DO x 1 fcount t1 100H D1 D2 x 1 fcount fcount Count clock frequency set by TCL1 and TCL2 80 CHAPTER 6 8 BIT REMOTE CONTROL TIMER Figure 6 3 Timing of Pulse Width Measurement 2 2 2 Measure pulse width in synchronization with both rising and falling edges FFH FFH Count value of TM1 D2 D3 D1 T Count starts Capture Capture 1 V V V V X gt X 95 I i OVF1 051 t Cleared by software Remark 10 01 DO x 1 fcount t1 100H D2 03 x 1 fcount fcount Count clock frequency set by TCL1 and TCL2 81 82 CHAPTER 7 8 BIT PWM TIMERS 7 1 Functions of 8 Bit PWM Timers The 8 bit PWM timers have the following two operation modes Mode in which only 8 bit timer TM5n 0 or 1 is used single mode Mode in which the two 8 bit PWM timers are cascaded 16 bit resolution cascade mode These two modes are explained next 1 Mode in which only a TM5n 0 or 1 is used single mode In this mode the 8 bit PWM timer operates as an 8 bit timer event counter In this mode the following functions can be used Interval timer External event counter Square wave output e PWM out
190. unting At the same time an interrupt request signal INTTM5n is generated The count clock of TM5n can be selected by using the bits 0 through 2 TCL5n0 through TCL5n2 of the timer clock select register 5n TCL5n Remark n 0or 1 Setting 1 Set the registers TCL5n Selects count clock CR5n Compare value TMC5n Selects clear amp start mode in which TM5n is cleared and started when its value coincides with CR5n TMC5n 0000xxx0B x don t care 2 The count operation is started when TCE5n 1 3 When the values of TM5n and CR5n coincide INTTM5n is generated TM5n is cleared to 00H 4 After that INTTM5n is generated at fixed intervals To stop the count operation clear TCE5n 0 Remark n 0 or 1 89 90 CHAPTER 7 8 BIT PWM TIMERS Figure 7 4 Timing of Interval Timer Operation 1 3 a Basic operation ot ol me Count clock a l i TM5n count value cy X_N N XooH Xo1H X Count starts Clear Clear CR5n N N N N Toes st oo iUe a INTTM5n zc oce cad xp el Interrupt request accepted Interrupt request accepted TlO5n E es 5 1 i Interval time Interval time Interval time Remarks 1 Interval time n 1 x t N 00H to FFH 2 0 1 b When CR5n 00H ie Site Wt Count clock i 1 l 1 1
191. y Inference Development Support System Fuzzy Inference Module EEU 1441 EEU 858 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU 1458 EEU 921 e Other related documents Document Name Document Number English Japanese IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J Electrostatic Discharge ESD Test 539 Guide to Quality Assurance for Semiconductor Devices MEI 1202 11893 Microcomputer Product Guide By third party U11416J Caution The contents of the above documents are subject to change without notice Be sure to use the latest edition for designing CHAPTER 1 GENERAL 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 CHAPTER 2 PIN FUNCTIONS TABLE OF CONTENTS lg uir c M ApplicationiFields u IIS eaea EI PRNa CP no cdam 1 Ordering Information Pin Configuration Top View uu uuu uu nennen nnns aaa aE 2 78K 0 Series Expansion Block Diagram a a Un Fa T Era uda nuno RE idt hri pncier nr mom 7 Mask troie oie tes c
192. ytes LPD78046H 48K bytes 780 048 60K bytes LPD78P048B only 1024 bytes LPD780226 48K bytes 0780228 60K bytes 78 0228 60K bytes 512 bytes uPD780204 uPD780205 uPD780206 48K bytes uPD780208 60K bytes LPD78P0208 60K bytes 1 PD780206 780208 and 78P0208 only 1024 bytes 32K bytes 40K bytes Internal buffer RAM size LPD78P048B only 64 bytes None 64 bytes FIP display RAM size CPU clock 48 bytes Main system clock or subsystem clock selectable 96 bytes Main system clock only 80 bytes Main system clock or subsystem clock selectable port 68 pins 72 pins 74 pins Total of FIP display output pins 34 pins 48 pins 53 pins Serial interface 1 channel 2 channels Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels 1 channel Watchdog timer 1 channel Watch timer 8 bit remote control timer 1 channel 8 bit PWM timer 2 channels Watchdog timer 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels 1 channel Watchdog timer 1 channel Watch timer Clock output Provided Provided Buzzer output Provided Provided Vectored interrupt Internal 10 11 source External 4 4 Test input Package Provided 80 pin plastic 14 x 20 mm 80 pin ceramic WQFN uPD78P048B only 100 pin plastic

UM : uPD780228 Subseries

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