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VT1802

1. 13 V4 HI is 73 V Vou HI Pon State 0 Channel 0 Vou HI is 28 V D8 12 1 1 Vou HI is 73 V Vou HI Pon state 0 D7 DS Unused Writing to these registers has no effect Read back value is what is written Channel 0 Vou LO is ground D4 60 49 1 Vou LO is 2 5 V Vou LO Pon State 0 Channel 0 Vou LO is ground D3 48 37 1 Vou LO is 2 5 V Vou LO Pon State 0 Channel 9 Vou LO is ground D2 36 25 1 Von LO is 2 5 V V LO Pon state 0 Channel 0 Vou LO is ground DI 24 13 1 Vou LO is 2 5 V Vou LO Pon state 0 Channel 0 Vou LO is ground DO 12 1 1 Vou LO is 42 5 V Von LO Pon State 0 Section 1 Channel Output Hardware Revision Register Read Only ADDR A24 A32 Offset 0x202 D15 D8 Unused Always reads as 0016 Hardware This code is incremented each time hardware changes are made to the VT1802 D7 DO Revision module Channel Output FPGA Code 36 VT1802 Programming www vxitech com Section 1 Channel Monitor Output Status Register Read Only ADDR A24 A32 Offset 0x428 0x42A 0x42C 0x42E 0x430 D15 D12 Unused All bits are always 0 Channel Output Status bits A 1 indicates that the channel is currently outputting or is experiencing a Vou HI condition A 0 indicates that the channel is currently outputting or is experiencing a V LO condition a To create the Channel Output Status bits the channel s output voltage is compared 48 37 to a thre
2. ion 2 Channel Monitor Output Threshold Voltage Register Read amp Write ADDR A24 A32 Offset 0xE04 0xE06 0xE08 0xE0A 0xE0C D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel Output Threshold Voltage bits The value written to these bits set the threshold voltage that will be used to indicate the channel s Output Status If the channel s output voltage 1s above the threshold set then the channel s Output Status bit will indicate a 1 If the channel s output voltage is below the threshold set then the channel s Output Status bit will indicate a 0 See the Channel Output Status Register description above podeis The actual V HI and Vou LO of the channel is set by the Voltage Level Control ud bits for the associated channel See the Voltage Level Control register above nde a 0x000 Channel Output Threshold set to 0 V minimum 108 97 OxFFF Channel Output Threshold set to approx 75 V maximum 96 85 Pon state 0x000 84 73 72 61 Example Set register 0x208 to a value of 0x802 The threshold voltage for channels 36 thru 25 is set to 0x802 0xFFF 75 2050 4095 75 0 500 75 37 5 V Note Each channel s output status comparator has about 4 0 V of hysteresis Section 2 Channel Monitor Hardware Revision Register Read Only ADDR A24 A32 Offset 0xE0E D15 DS Unused Always reads as 0016 Hardware This code is incre
3. E Technology VT1802 120 CHANNEL SINGLE ENDED 60 CHANNEL DIFFERENTIAL 28 V 73 V VO CURRENT DRIVER USER S MANUAL P N 82 0106 000 Rev February 13 2007 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 949 955 1894 VXI Technology Inc www vxitech com TABLE OF CONTENTS INTRODUCTION Certification cda olla til eb lest nad e lo 5 ATTAT REI OTATTE e 5 Eimitation 0f Warranty sent elei Dto nO BORA RI iin bite tS 5 Restricted Rights Leste Doct I eO BUR UO Di ate 5 DECLARATION QF CONFORMITY moyin fr rete eee na e oe FN SNO eee aa Ea E Ee po ee E at 6 Terris and Symbols 2 sanctio Oo eee ptis einbauen 7 Ein REL o O Eo o lt hee Lead Nast anol ns o o id dnd 7 SECTION A O 11 INTRODUCTION angie tto pie eee MR I re Nel eta ea otto en o etis eine 11 OVA e oO ent pi dial i ieri ii 11 VI1802 Specificanons a guilala inni lea ae ir UL Les Ti E 12 SECTION rete 13 PREPARATION FOR USE siria ee aria 13 Introduction anioni a eat enna i 13 Calculating System Power and Cooling Requirements i 13 Setting the Chassis Backplane JUMPErs crono nono E nr nn rA ron naar EEEE E rnnnnnnnns 13 Switch Settings curtir 14 Setting the Logical Address aee tette e e erg te a aeq Vete qr iaia wa tede 14 Selecting the Extended Memory Space ener enne 16 II OE ERRE RANA NS A 17 MODULE USE AND OPERATION rina ea ara 17 OVER to e dal E S 17 Backplane I
4. Output Control Function Bank Setup Register 0x22 0x24 Read amp Write D15 D8 Always write 0x00 D7 DO Register 0x22 sets the banks starting from Bankl to Bank5 for Channel Output Control Function on Motherboard Register 0x24 sets the banks starting from Bank6 to Bank10 for Channel Output Control Function on Daughterboard Used in Trace Mode ONLY VT1802 Programming 29 VXI Technology Inc Command Trigger Control Register 0x26 Read amp Write D15 External Trigger 1 1 Write a 1 to this bit to enable External Trigger 1 to control the transfer Enable of data from the input buffer to the output buffer 0 Write a 0 to disable this trigger Pon state 0 D14 External Trigger 2 1 Write a 1 to this bit to enable External Trigger 2 to control the transfer Enable of data from the input buffer to the output buffer 0 Write a 0 to disable this trigger Pon state 0 D13 Backplane 1 Write a 1 to this bit to enable the VT1802 to execute user command if TTLO 7 Trigger any bit TTLTRIGO 7 change edge as defined below 0 Write a 0 to disable this trigger Pon State 0 D12 Software Trigger 1 Write a 1 to this bit to enable the VT1802 to execute user command if Enable Software Trigger bit D9 is set 0 Write a 0 to disable this trigger Pon state 1 D11 External Trig 1 Write a 1 to this bit set the external triggers to EXT TRIG1 AND EXT Cont
5. VT1802 Module Use and Operation 21 gt qe LET Oo DID an Technology EXT TRIG 1 EXT TRIG 2 Pin A32 A1 TZ P3 IO p J il Or Ko o o S cf FIGURE 2 3 CONNECTOR LOCATION ASSIGNMENTS VXI Technology Inc Pin E32 Pin E1 22 VT1802 Module Use and Operation www vxitech com TABLE 2 1 FRONT PANEL SIGNAL ASSIGNMENTS SIGNAL SIGNAL SIGNAL SIGNAL 1 CHNII16 1 CHN117 1 CHN118 1 CHN119 1 CHN120 2 CHNI11 2 CHN112 2 CHN113 2 CHN114 2 CHN115 3 CHN106 3 CHN107 3 CHN108 3 CHN109 3 CHN110 4 GND 4 GND 4 GND 4 GND 4 GND 5 CHNI01 5 CHN102 5 CHN103 5 CHN104 5 CHN105 6 CHN96 6 CHN97 6 CHN98 6 CHN99 6 CHN100 7 CHN91 7 CHN92 7 CHN93 7 CHN94 7 CHN95 8 GND 8 GND 8 GND 8 GND 8 GND 9 CHN56 9 CHNS57 9 CHNS58 9 CHNS59 9 CHN60 10 CHNS1 10 CHN52 10 CHN53 10 CHN54 10 CHNS5 11 CHN46 11 CHN47 11 CHN48 11 CHN49 11 CHN50 12 GND 12 GND 12 GND 12 GND 12 GND 13 CHN41 13 CHN42 13 CHN43 13 CHN44 13 CHN45 14 CHN36 14 CHN37 14 CHN38 14 CHN39 14 CHN40 15 CHN31 15 CHN32 15 CHN33 15 CHN34 15 CHN35 16 GND 16 GND 16 GND 16 GND 16 GND 17 GND 17 GND 17 GND 17 GND 17 GND 18 CHN26 18 CHN27 18 CHN28 18 CHN29 18 CHN30 19 CHN21 19 CHN22 19 CHN23 19 CHN24
6. enabled 0 disabled If the LOOP ENABLE bit is set and the end of active trace RAM is reached this bit will not be reset Reserved Registers 0x3C Read amp Write D15 DO Unused Writing to these registers has no effect Read back value is register dependent Trigger Advance Register 0x3E Write Only D15 DO Unused The act of writing to this location causes a Trace Advance event to occur in the module The specific data written to these bits has no effect VT1802 Programming 33 VXI Technology Inc DESCRIPTION OF VT1802 MODULE REGISTERS A24 A32 EXTENDED MEMORY The VT1802 contains 2 identical sections 60 channels per section Each section is assigned 2 kB 2048 bytes of memory as shown in the VT1802 Configuration Register Map for A24 A32 address space The following describes these registers Section 1 Channel Output Enable Register Read amp Write ADDR A24 A32 Offset 0x000 0x004 0x008 0x00C 0x010 D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel Select bits By setting these bits the associated channel is turned on enabled These bits are cleared by an over current event on a per channel basis The corresponding bits in the Over current registers can be used to identify channels that have experienced an over current event See Over current Register Channel definition below Once a cha
7. regData 0x0000 regSele vtvm1802_PIN_ENAB REG for i 0 i lt 5 i Il disable all banks tmpBank outBank i Il setup the pin bank iStatus vtvm1802_setBankData instHndl tmpBank vtvm1802 PIN ENAB REG regData ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed iStatus vtvm1802 setBankData instHndl tmpBank vtvm1802 PIN HILO REG regData ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed gStatus dpyUpd1802 mainHndl MAIN RDPY EVENT_COMMIT VI NULL 0 0 Delay dlyTime break return 0 ezine see dz cies ris Riese ate aio lai ce eels l dpyUpd1802 refresh instrument display II int CVICALLBACK dpyUpd1802 int panel int control int event void cbD int eD1 int eD2 ViStatus iStatus VI SUCCESS Vilnt16 pinBank pinChan regMask regSele Il pdS tate Vilnt16 enaData regData rbkData ochData oclData int pinE nab regEnab rbkE nab ochEnab oclEnab int gStatus frsBank i j Il IclCtrl int ledEnab ledHiLo ledRdbk ledOchi ledOclo switch event case EVENT COMMIT getF rsBnk amp frsBank regSele z vtvm1802 PIN ENAB REG Il display the enables ledEnab MAIN BIPE 1 ledHiLo MAIN BIPL 1 ledR dbk 2 MAIN BIRB 1 ledOchi MAIN B1OH 1 ledOclo MAIN BIOL 1 for i 20 i 5 i Il do 5 pin banks pinBank frsBank i Il pin bank numbers are 1 based Il read the registers iStatus vivm1802 getBankData instHndl pinB
8. which are configured as outputs and will toggle when Trace Advance condition occurs in the module D15 corresponds to TTLTRIG7 D14 to TTLTRIG6 and D8 to TTLTRIGO Setting a bit to a 1 enables the trigger line setting a bit to 0 disables the corresponding line All bits are set to 0 when either a soft or a hard reset is received by the module D7 DO Sets the TTLTRIG line or lines which are configured as inputs and will cause a Trace Advance event to occur in the module D7 corresponds to TTLTRIG7 D6 to TTLTRIG6 and DO to TTLTRIGO Setting a bit to a 1 enables the trigger line setting a bit to 0 disables the corresponding line All enabled TTLTRIG lines are OR d together to allow more than one TTLTRIG line to cause a Trace Advance event to occur All bits are set to 0 when the module receives either a soft or a hard reset VT1802 Programming VXI Technology Inc Over current Trigger Select amp Power Enable Register 0x36 Read Write D15 D8 Sets the TTLTRIG line or lines which are configured as outputs and will toggle when either bank 1 to 60 or 61 to 120 Over current Event conditions occur in the module D15 corresponds to TTLTRIG7 D14 to TTLTRIG6 and D8 to TTLTRIGO Setting a bit to a 1 enables the trigger line setting a bit to 0 disables the corresponding line All bits are set to 0 when either a soft or a hard reset is received by the module D7 D4 Unu
9. 19 CHN25 20 CHNI6 20 CHN17 20 CHNI8 20 CHNI9 20 CHN20 21 GND 21 GND 21 GND 21 GND 21 GND 22 CHNII 22 CHNI2 22 CHN13 22 CHN14 22 CHNI5 23 CHN6 23 CHN7 23 CHN8 23 CHN9 23 CHNIO 24 CHNI 24 CHN2 24 CHN3 24 CHN4 24 CHNS 25 GND 25 GND 25 GND 25 GND 25 GND 26 CHN86 26 CHN87 26 CHN88 26 CHN89 26 CHN90 27 CHN81 27 CHN82 27 CHN83 27 CHN84 27 CHN85 28 CHN76 28 CHN77 28 CHN78 28 CHN79 28 CHN80 29 GND 29 GND 29 GND 29 GND 29 GND 30 CHN71 30 CHN72 30 CHN73 30 CHN74 30 CHN75 31 CHN66 31 CHN67 31 CHN68 31 CHN69 31 CHN70 32 CHN61 32 CHN62 32 CHN63 32 CHN64 32 CHN65 VT1802 Module Use and Operation 23 VXI Technology Inc 24 VT1802 Module Use and Operation www vxitech com SECTION 4 PROGRAMMING INTRODUCTION VT1802 modules are VXIbus register based devices for high speed data retrieval Register based programming is a series of reads and writes directly to the module s registers this includes accesses to the modules RAM This eliminates the time for command parsing thus increasing speed ADDRESSING The VXI Technology switching modules utilize either the A24 or A32 space set via the DIP switches on the bottom of the VT1802 module see page 16 of the shared memory architecture To read or write to a module register a register address needs to be specified This is done by using the offset value assigned by the resource manager and multiplying it by 256 or 64 k to get the
10. D10 Function Enabled D13 is for Channel Output Monitor Function Section 2 Daughterboard D12 is for Channel Output Control Function Section 2 Daughterboard D11 is for Channel Output Monitor Function Section 1 Motherboard D10 is for Channel Output Control Function Section 1 Motherboard Set to 0 to enabled the function Set to a 1 if not used These bits are set to 0000 at power on D9 D8 Unused Must be set to 00 D7 D4 Function used in D7 is for Channel Output Monitor Function Section 2 Daughterboard trace mode D6 is for Channel Output Control Function Section 2 Daughterboard D5 is for Channel Output Monitor Function Section 1 Motherboard D4 is for Channel Output Control Function Section 1 Motherboard Set to 1 if Function is used in trace mode set to 0 if not in trace mode At power on all bits are set to 0 For standard VT1802 trace mode only D6 and D4 are set active Note D7 and D4 are for Channel Output Monitor Controls which should not be used in trace mode Setting D7 and D4 bits to 1 could produce very unexpected results while running in trace mode D3 D2 Unused Data written to these bits have no effect The value written is read back DI LOOP ENABLE 1 enabled 0 disabled If enabled the trace resumes at the start of active RAM and continues from there If disabled the trace stops at the end of active RAM and clears the TRACE ENABLE bit DO TRACE ENABLE 1
11. Write nono nonnnonnrnnnninninos 33 Reserved Registers 0x3C Read amp WTrIte ener ener enne 33 Trigger Advance Register Ox3E Write Only sess enne nennen nennen 33 Description of VT1802 Module Registers A24 A32 Extended Memory sese 34 Section 1 Channel Output Enable Register Read amp Wirite essen 34 Section 1 Channel Output Level Select Register Read amp Write sss 34 Section 1 Channel Over current Status LO Register Read ONIY sse 35 Section 1 Channel Over current Status HI Register Read ONlY sse 35 Section Voltage Level Control Register Read amp Write sse 36 Section 1 Channel Output Hardware Revision Register Read Only n 36 Section 1 Channel Monitor Output Status Register Read Only n 37 Section 1 Channel Monitor Output Threshold Voltage Register Read amp Write 37 Section 1 Channel Monitor Hardware Revision Register Read Only n 38 Section 2 Channel Output Enable Register Read amp Write 38 Section 2 Channel Output Level Select Register Read amp Write sss 38 Section 2 Channel Over current Status LO Register Read ONlY i 39 Section 2 Channel Over current Status HI Reg
12. a channel can be set to ON OFF or HI LO respectively Each channel is additionally capable of Output Enable Output Selection and Output Level Readback 18 VT1802 Module Use and Operation www vxitech com 73V OFF o OC HI WEE 3 LO O OC LO 4 Overcurrent Detect READBACKC Comparator LEVEL 4 HI LO 1 LEVEL 7 12 bit DAC HI ES 12 4 Blocks 1 5 F R O N T P HI A LO N 1 E LEVEL L 12 bit DAC HI LO 12 Blocks 6 10 FIGURE 2 2 VT1802 BLOCK DIAGRAM VT1802 Module Use and Operation VXI Technology Inc MODES OF OPERATION Two different modes of operation are available on the VT1802 These modes are described below Mode Explanation Example Single ended The channel can be If a bank is set to 73 V 28 V the channel will source up to configured to source current 1 mA 140 mA controlled by load AO Boman tati sekiu 2 5 MENO the channel wall sink upto 1 mA 140 mA controlled by load Differential Two channels of the same If bank 2 is set to 28 V and GND then channel 13 can be 28 V voltage are used but set to and connected to
13. amp Write essere eene nnns 29 Subclass Register 0x 1E Read Only sse enne enne nennen nene nennen enn 29 LED Control NVM Access Register 0x20 Read Only eene 29 LED Control NVM Access Register 0x20 Write Only nennen 29 Output Control Function Bank Setup Register 0x22 0x24 Read amp Write sss 29 Command Trigger Control Register 0x26 Read amp Write sss 30 VT1802 Preface 3 VXI Technology Inc Trace RAM Restart High Register 0x28 Read amp Write 31 Trace RAM Restart Low Register 0x2A Read amp Write ccoo nonnnonnnnnnrnnnonnnnos 31 Trace RAM End High Register 0x2C Read amp WTrite eee 31 Trace RAM End Low Register 0x2E Read amp Write ccoo nconnnon nono nonnnnnnnnnrnnnnns 31 Trace RAM Start Address HIGH Register 0x30 Read amp Write 31 Trace RAM Start Address LOW Register 0x32 Read amp WErite 31 Trace Advance Trigger Select Register 0x34 Write Only rca ncon nono nonnnnnos 31 Over current Trigger Select amp Power Enable Register 0x36 Read Write n 32 TTL Trigger Polarity Register 0x38 Write Only ccoo nono ronnronrnnnanninss 32 Trace RAM Control Register 0x3A Read amp
14. base address in A24 or A32 address space respectively A24 Base Address Offset value 0x0100 or 256 A32 Base Address Offset value 0x10000 or 65 536 The A24 or A32 offset value assigned by the resource manager can also be accessed by reading the A16 Offset Register To address the A16 Offset Register use the following formula A16 Base Address Logical Address 64 0xC000 or 49 152 then A16 Offset Register Address A16 Base Address 6 See A16 Memory Map on page 26 and the A24 A32 address space allocation on page 34 VT1802 Programming 25 VXI Technology Inc TABLE 3 1 VT1802 REGISTER MAP A16 OFFSET WRITE FUNCTION READ FUNCTION Ox3E Trace Advance Reserved 0x3C Reserved Reserved 0x3A Trace RAM Control Trace RAM Control 0x38 TTL Trigger Polarity Reserved Over current Trigger Select amp 0x36 Power Enable Reserved 0x34 Trace Advance Trigger Select Reserved 0x32 Trace RAM Start Address LOW Trace RAM Start Address LOW 0x30 Trace RAM Start Address HIGH Trace RAM Start Address HIGH Trace RAM End LOW Trace RAM End LOW Trace RAM End HIGH Trace RAM End HIGH Trace RAM Restart LOW Trace RAM Restart LOW Trace RAM Restart HIGH Trace RAM Restart HIGH Command Trigger Control Command Trigger Control Output Control Function Bank Setup Output Control Function Bank Setup Output Control Function Bank Setup Output Control Function Bank Setup LED Control NVM Access LED Control NVM Acce
15. eD1 int eD2 ViStatus iS tatus Vilnt16 tmpBank regData regSele pwrCtrl VilntL6 inpBank outBank inpData outData ViReal64 ctVolts dlyTime int gStatus i j switch event case EVENT COMMIT pwrCtrl zvtum1802 LOG1 PWR 28V Il Il pwrCtrl vtum1802 LOG1 PWR 73V ctVolts pwrCtrl vtvm1802 LOG1 PWR 73V 36 5 14 0 dlyTime z 0 1 outBank z 1 Il inpBank 2 regData 0x0000 regSele vtvm1802_PIN_ENAB REG for i 0 i lt 5 i Il tmpBank outBank i Il iStatus vtvm1802_setBankData instHndl tmpBank regSele regData ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed all banks disabled turn on the power iStatus vtum1802 setPowerCtrl instHndl pwrCtrl Il ifliStatus VI SUCCESS essageP opup ERROR setPowerCtrl failed iStatus vtvm1802 setBankLevel instHndl inpBank 0 pwrCtrl Il ifliStatus VI SUCCESS iStatus vtvm1802 setBankLevel instHndl outBank 0 pwrC trl Il ifliStatus VI SUCCESS iStatus vtvm1802_setCompLevel instH ndl inpBank ctVolts Il if iStatus VI SUCCESS Il MessageP opup ERROR setCompLevel failed input bank iStatus vtum1802 setCompLevel instHndl outBank ctVolts Il ifliStatus VI SUCCESS MessageP opup ERROR setCompLevel failed output bank regSele vtvm1802 PIN HILO REG forli 20 i 5 i Il tmpBank i 1 Il iStatus vtvm1802 setBankData instHndl
16. of the instrument will be jeopardized and permanent damage may occur Damage found to have occurred due to inadequate cooling could also void the warranty of the module SETTING THE CHASSIS BACKPLANE JUMPERS Please refer to the chassis operation manual for further details on setting the backplane jumpers VT1802 Preparation for Use 13 VXI Technology Inc SWITCH SETTINGS The VT1802 has three configurable switches all located at the top of the unit near the rear connectors The two rotary dials S1 and S2 located closest to the rear of the interface card set the logical address LA for the module while the two position DIP switch S3 sets the extended memory space for the module to either A24 or A32 Figure 1 1 below shows the location of these switches and the following paragraphs explain how they are configured zi LA Logical Address Switches Ma Vai S1 S2 Expanded Memory DIP Switch Ss 4 a gt la A a Re we f f KOREA Rear of Module FIGURE 1 1 SWITCH LOCATIONS Setting the Logical Address The LA of the VT1802 is set by two rotary switches with each switch labeled with positions 0 through F S the switch closer to the front panel of the module is the least significant bit LS or Front and 2 the switch located towards the back of the module is the most significant bit MS or Back To set the LA simply rotate the pointer to the desired value For example to set
17. read of the channel s Over current bit may be required to determine whether the channel has experienced an over current event or not Section 2 Channel Output Level Select Register Read amp Write ADDR A24 A32 Offset 0x802 0x806 0x80A 0x80E 0x812 D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel bits By setting these bits the associated channel is set HI or LO These Channels bits are not affected by an over current event The actual Vou HI and Vp LO of the 120 109 channel is set by the Voltage Level Control for the associated channel See page 40 108 97 for more information on the Voltage Level Control register D11 DO 96 85 84 73 0 Channel output LO 72 61 1 Channel output HI Pon state 0 38 VT1802 Programming www vxitech com Section 2 Channel Over current Status LO Register Read Only ADDR A24 A32 Offset 0x814 0x818 0x81C 0x820 0x824 D15 D12 Unused All bits are always 0 Channel Over current LO Status bits A 1 indicates that a V LO Over current Event has occurred A 0 indicates no Over current Event has occurred An over current event will set the appropriate Over current Status bit and will also disable the associated channel s Channel Select bit Once disabled the channel may again be enabled by setting the channel s Channel Select bit to 1 See the n Rr Channel Select Register descri
18. terms and symbols trace advance input slope bit x trace advance output slope Dit sse 32 trace advance trigger select register iii 3 TRACE ENABLE bit z trace RAM address HIGH register i 31 trace RAM address LOW register ine 3 trace RAM control register trace RAM end high register trace RAM end low register T trace RAM start high register esses trace RAM start low register seen Trigger Advance register TIL trig polarity bit ebat tee neces ETL trigger polarity register eei nere y version number register WwW WANE Se AS warranty WBBE aee OR AS VXI Technology Inc 48 VT1802 Index
19. the LA to 25 first convert the decimal number to the hexadecimal value of 19 Next set the back switch to 1 and the front switch to 9 See Figure 1 2 Here are a couple of conversion examples 14 VT1802 Preparation for Use www vxitech com Example 1 LA Divide decimal by 16 MS LS 25 25 16 w 9 remaining Divide the decimal value by 16 to get the MS and the LS 0001 1001 The 1 is the MS and the remainder of 9 is the LS 1 9 Convert to hexadecimal Set the back switch to 1 and the front switch to 9 BACK FRONT 45 45 A E V2 6 oo AY Je a f Me TOO 9958 FIGURE 1 2 LOGICAL ADDRESS EXAMPLE 1 Here is another way of looking at the conversion LA back switch x 16 front switch LA 1x 16 9 LA 716 79 LA 25 Example 2 LA Divide decimal by 16 MS LS 200 200 16 12 w 8 remaining Divide by 16 1100 1000 Convert to MS and LS C 8 Convert to hexadecimal Set the back switch to C and the front switch to 8 BACK FRONT 45 45 aun veges a S co e AN wS AN qoe qo FIGURE 1 3 LOGICAL ADDRESS EXAMPLE 2 Set the address switches to FF factory default for dynamic configuration Upon power up the resource manager will assign a logical address See Section F Dynamic Configuration in the VXIbus Specification for further information VT1802 Preparation for Use 15 VXI Technology Inc There is only one logi
20. tmpBank regSele regData ifliStatus VI SUCCESS essageP opup ERROR setBankLevel failed input bank logic 1 level comment out the one you don t want our test board is bank 1 bank 2 disable all banks setup the pin bank power on set logic 1 level set logic 1 level MessagePopup ERROR setBankLevel failed output bank logic 1 level Set comparator threshold for the input and output banks make all outputs low the pin bank numbers are 1 based VT1802 Programming 43 VXI Technology Inc MessagePopup ERROR setBankData failed clear Hi Lo reg gStatus dpyUpd1802 mainHndl MAIN_RDPY EVENT_COMMIT VI NULL 0 0 Delay dlyTime regData OxOF FF Il enable output bank regSele vivm1802 PIN ENAB REG Il select bank enable register iStatus vtvm1802_setBankData instHndl outBank regSele regData ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed enable output bank regData 0x0000 Il disable input bank iStatus vtvm1802_setBankData instHndl inpBank regSele regData ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed disable input bank outData 0x0001 Il we re going to walk a 1 for j 0 j lt 12 j i Il write the data to the Hi Lo register iStatus vtvm1802_setBankData instHndl outBank vtvm1802 PIN ifliStatus VI SUCCESS MessageP opup ERROR setBankData failed gStatus dpyUpd1802
21. 2 5 V Vout LO Pon state 0 Channel 0 Vou LO is ground D2 96 85 1 Von LO is 2 5 V V LO Pon state 0 Channel 0 Vou LO is ground DI Vou 63 1 Vou LO is 2 5 V Vou LO Pon State 0 Channel 0 Vou LO is ground DO 72 61 1 Vou LO is 2 5 V Vou LO Pon State 0 Section 2 Channel Output Hardware Revision Register Read Only ADDR A24 A32 Offset 0xA02 D15 D8 Unused Always reads as 0016 Hardware This code is incremented each time hardware changes are made to the VT1802 D7 DO Revision module Channel Output FPGA Code 40 VT1802 Programming www vxitech com Section 2 Channel Monitor Output Status Register Read Only ADDR A24 A32 Offset 0xC28 0xC2A 0xC2C 0xC2E 0xC30 D15 DI2 Unused All bits are always 0 Channel Output Status bits A 1 indicates that the channel is currently outputting or is experiencing a Vou HI condition A 0 indicates that the channel is currently outputting or is experiencing a Vu LO condition n ir To create the Channel Output Status bits the channel s output voltage is compared 108 97 to a threshold reference voltage that is set in the Channel Output Threshold D11 DO 96 85 Voltage register See the Channel Output Threshold Voltage register description 84 73 below 72 61 These bits may be used to monitor for the proper operation of the module s output channels Note Each channel s output status comparator has about 4 0 V of hysteresis
22. Register definitions on page 34 D8 Over current Error An Over current event either HI or LO has occurred on a channel between 1 Detected and 60 The OC registers for this bank must be queried to identify the Channels 1 thru 60 channel s that indicated an Over current Event The Over current event will reset the affected channel effectively shutting it off To turn the channel on again its Select bit must be re set See the A24 A32 Channel Select Register definitions on page 34 D7 DO Reserved Always reads back as FFFF j Note This status register may be used in a polled fashion rather than allowing the events above to generate an Interrupt A read of this register will clear any active bits Bits that are not set or are about to be set are not affected by a read of this register 28 VT1802 Programming www vxitech com Interrupt Control Register 0x1C Read amp Write D15 Scan Function 0 Enabled done mask bit 1 Disabled D14 D10 Reserved Writes to these bits have no effect D9 Over current Error 0 Enabled Event 1 Disabled Channels 61 through 120 D8 Over current Error 0 Enabled Event 1 Disabled Channels 1 thru 60 D7 IR ENA 0 Writing a 0 to this bit enables interrupter capabilities 1 Writing a to this bit disables interrupter capabilities D6 IH ENA The module has no interrupt handler capability therefore writing a 1 or 0 has no effect A 1 is a
23. Required Memory 2 MB set to 216 for A24 2 MB set to Ais for A32 Status Register 0x04 Read Only A24 A32 Active Indicates that A24 A32 memory space access is enabled Indicates that A24 A32 memory space access is locked out D14 MODID i Indicates that the module is not selected by the MODID line 0 Indicates that the module is selected by the MODID line D13 D4 Reserved These bits always read as 11 1111 1111 D3 Ready This bit always reads as 1 D2 Passed This bit always reads as 1 DI DO Reserved These bits always read as 11 Control Register 0x04 Write Only A24 A32 Enable 1 Write a 1 to this bit to enable A24 A32 memory access 0 To disable access D14 D2 Reserved Writes to these bits have no effect DI Sysfail Inhibit Write a 1 to this bit to prevent the module from asserting the SYSFAIL line DO Reset 1 Write a 1 to this bit to force the registers on the VT1802 interface into a reset state 0 Write a 0 to release this soft reset state Note This does not reset output channels on the module Offset Register 0x06 Read amp Write sid D15 DO A24 A32 Memory Offset The value written to this 16 bit register multiplied by 256 sets the base address of the A24 memory space used by the module The value written to this 16 bit register multiplied by 65 536 sets the base address of the A32 memory space used by the module A r
24. able RAM to be divided into multiple traces Trace RAM Restart Low Register 0x2A Read amp Write D15 DO Sets the 16 least significant bits of the starting address of the Trace RAM allowing the available RAM to be divided into multiple traces Trace RAM End High Register 0x2C Read amp Write D15 D4 Unused Data written to these bits have no effect and always read back as 1 D3 DO Sets the four most significant bits of the ending address of the Trace RAM allowing the available RAM to be divided into multiple traces Trace RAM End Low Register 0x2E Read amp Write D15 DO Sets the 16 least significant bits of the ending address of the Trace RAM allowing the available RAM to be divided into multiple traces Trace RAM Start Address HIGH Register 0x30 Read amp Write D15 D4 Unused Data written to these bits have no effect and always read back as 1 D3 DO Sets and reads back the four most significant bits of the current address of the Trace RAM allowing the current trace RAM address to be queried and changed Trace RAM Start Address LOW Register 0x32 Read amp Write D15 DO Sets and reads back the sixteen least significant bits of the current address of the Trace RAM allowing the current trace RAM address to be queried and changed Trace Advance Trigger Select Register 0x34 Write Only D15 D8 Sets the TTLTRIG line or lines
25. ank vtvm1802 PIN ENAB REG amp enaData iStatus vivm1802 getBankData instHndl pinBank vtvm1802 PIN HILO REG amp regData iStatus vivm1802 getBankData instHndl pinBank vtum1802 PIN RDBK REG amp rbkData iStatus vivm1802 getBankData instHndl pinBank vtvm1802 PIN OCHI REG amp ochData iStatus vivm1802 getBankData instHndl pinBank vtvm1802 PIN OCLO REG amp oclData regMask 1 VT1802 Programming 45 VXI Technology Inc for j 20 j 12 j pinChan j 1 pinEnab enaData amp regMask regMask 1 0 regEnab regData amp regMask regMask 1 0 rbkEnab rbkData amp regMask regMask 1 0 ochEnab ochData regMask regMask 1 0 oclEnab oclData regMask regMask 1 0 gStatus SetCtriVal mainHndl ledE nab pinEnab gStatus SetCtriVal mainHndl ledHiLo regE nab gStatus SetCtriVal mainHndl ledRdbk rbkEnab gStatus SetCtriVal mainHndl ledOchi ochEnab gStatus SetCtriVal mainHndl ledOclo oclEnab if pinEnab gStatus SetCtrlAttribute mainHndl ledHiLo ATTR_OFF_COLOR VAL BLUE gStatus SetCtrlAttribute mainHndl ledHiLo ATTR_ON_COLOR VAL RED else gStatus SetCtriAttribute mainHndl ledHiLo ATTR_OFF_COLOR VAL LT GRAY if ochE nab oclEnab Il if overload its open regardless of cmd state gStatus SetCtrlAttribute mainHndl ledHiLo ATTR ON COLOR VAL LT GRAY else gStatus SetCtrlAttribute mainHndl ledH
26. ave been designed to comply with the relevant sections of the specifications listed above as well as complying with all essential requirements of the Low Voltage Directive February 2007 amp Cu lt P Y Steve Mauga QA Manager 6 VT1802 Preface www vxitech com GENERAL SAFETY INSTRUCTIONS Review the following safety precautions to avoid bodily injury and or damage to the product These precautions must be observed during all phases of operation or service of this product Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the product Service should only be performed by qualified personnel TERMS AND SYMBOLS These terms may appear in this manual WARNING Indicates that a procedure or condition may cause bodily injury or death CAUTION Indicates that a procedure or condition could possibly cause damage to equipment or loss of data These symbols may appear on the product ATTENTION Important safety instructions Frame or chassis ground Indicates that the product was manufactured after August 13 2005 This mark is placed in accordance with EN 50419 Marking of electrical and electronic equipment in accordance with Article 11 2 of Directive 2002 96 EC WEEE End of life product can be returned to VTI by obtaining an RMA number Fees for take back and recycling will apply if not prohibite
27. bit 33 LSB least significant bit iii 14 15 M Manufacturer s ID bits nette tees 27 MESSAGE DASE zu eese eee E Due PRETI one rb RES 25 minor hardware version number 28 model code bits MODID bit module installation module use and operation sse 17 modules installed bits 5 modules used in trace mode bits een 33 MSB most significant bit iii 14 15 N NVM access T gister escono iii pia 26 29 O Offset Topsites 27 open trigger select register sese 32 Openbus active event true bit 28 over current error event bit 29 over current event output slope bit in 32 P polled fashion iui Raso 28 PoWeliziizila anale OH EP In an seis 13 VT1802 Programming 47 R e M 25 27 required memory bits c eee entend 27 Ieserved Ieglster i rl i LAGO Reserved register r st DIU s een Oa REED ente restricted rights legend sss serene S S scan function done mask bit iii setting the chassis backplane jumpers m setting the logical address sse Software trigger DIU cuni ria software trigger bits software trigger enable bit specifications Status register nano mm e e e rre subclass A Ree MERI eee Ee support resources x SWitchi Settitigs ida RUPEE E ORIG SAA REPRE T
28. bits 37 41 channel over current HI status bits e channel over current LO status bits me channelselect bits t doesent ERBEN ERR command parsifig iier areali control register pem itsdas D declaration of conformity essere Delay registers ott acid description of registers A16 device Class bits coil REG device type Tegisteh RR OR ERE bees dynamic configuration iii E error LED control Bits jc cnica noia 29 extended memory device Dits ie 29 Extended Memory Space eee aee external trig control bit gt external trigger 1 enable bit eee eere 30 external trigger 2 enable bit leali 30 F firmware version number iii 28 front panel connector location assignments 21 front panel signal assignments eee 23 H handler IRO ine bits oii ce et e 29 hardware revision code bits sss 36 38 40 41 I ID TASA IH ENAA Dl RM ao interrupt control register a interrupt status Teglster oie mE eie interrupter IRQ line bits cis estet ettet renes IR ENA bit us ROME o en en ect credant L LEDS a RE 21 limitation Of warranty 5 logical address logical address Bits s eon eni eara p een 27 logical address register sse 27 LOOP ENABLE
29. cal address per VT1802 base unit Address assignments for individual modules are handled through the A24 A32 address space allocation see Description of VT1802 Module Registers A24 A32 Extended Memory for more information Selecting the Extended Memory Space The extended memory space of VT1802 base units is set by a DIP switch that is located on the top edge of the interface card see Figure 1 1 Position 1 located to the left on the DIP switch selects between A24 and A32 memory address space In the UP position the VT1802 will request A24 space In the DOWN position factory default the VT1802 will request A32 space Position 2 1s not currently used The selection of the address space should be based upon the memory allocation requirements of the system that the VT1802 module will be installed The amount of memory allocated to a VT1802 module is independent of the address space selected 16 VT1802 Preparation for Use www vxitech com SECTION 3 MODULE USE AND OPERATION OVERVIEW The VT1802 is a current driver module providing 10 banks of 12 channels 120 channels from two constant voltage sources Each bank of twelve channels may be configured as a current source or a current sink of different voltages under software program control The channels can be used in either single ended of differential mode The VT1802 contains two identical sections with five banks 60 channels a piece The control funct
30. channel 24 set at GND via a proper load or pu v Bank 7 can be set to 73 V and 2 5 V then channel 73 can be 73 V Aa NV or e us and connected to channel 84 set at 2 5 V via a proper load or where one is used as the current source and one is All channels from bank x set at either 28 V 73 V and connected used as a current sink to all channels from bank Y set at either GND 2 5 V It is recommended that the latter example be used in practice for ease of use and to reduce the likelihood of making an incorrect wiring connection Note the user must provide the appropriate load to avoid over current TRIGGER OPERATION The VT1802 can be controlled via software The user can issue commands to execute several functions select channel level Select Bank Voltage Over current Status etc Two operations Channel Output Enable and Channel Output Level Select are used to engage the VT1802 when entered or via triggers supplied by any of the three following sources 1 External Trigger the VT1802 has two front panel connectors They allow for 5 V TTL level triggering and OR or AND operation can be selected 2 Backplane TTLO 7 Trigger There are eight backplane TTL trigger signals These triggers are edge triggering and can be selected falling or rising edge triggering 3 Software Trigger The priority of triggering is as following EXT TRIGGERS BACKPLANE TTLO 7 Trigger Software Trigger If all or many triggers are
31. chantability and fitness for a particular purpose RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the Government is subject to restrictions as set forth in subdivision b 3 11 of the Rights in Technical Data and Computer Software clause in DFARS 252 227 7013 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 U S A VT1802 Preface 5 VXI Technology Inc DECLARATION OF CONFORMITY Declaration of Conformity According to ISO IEC Guide 22 and EN 45014 MANUFACTURER S NAME VXI Technology Inc MANUFACTURER S ADDRESS 2031 Main Street Irvine California 92614 6509 PRODUCT NAME 120 single ended 60 differential channel current driver MODEL NUMBER S VT1802 PRODUCT OPTIONS AII PRODUCT CONFIGURATIONS All VXI Technology Inc declares that the aforementioned products conform to the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 366 EEC inclusive 93 68 EEC and carries the CE mark accordingly The products have been designed and manufactured according to the following specifications SAFETY EN61010 2001 EMC EN61326 1997 w A1 98 Class A CISPR 22 1997 Class A VCCI April 2000 Class A ICES 003 Class A ANSI C63 4 1992 AS NZS 3548 w A1 amp A2 97 Class A FCC Part 15 Subpart B Class A EN 61010 1 2001 The products were installed into a C size VXI mainframe chassis and tested in a typical configuration I hereby declare that the aforementioned products h
32. d by national law D4 y gt WARNINGS Follow these precautions to avoid injury or damage to the product Use Proper Power Cord To avoid hazard only use the power cord specified for this product Use Proper Power Source To avoid electrical overload electric shock or fire hazard do not use a power source that applies other than the specified voltage Use Proper Fuse To avoid fire hazard only use the type and rating fuse specified for this product VT1802 Preface 7 VXI Technology Inc WARNINGS CONT Avoid Electric Shock To avoid electric shock or fire hazard do not operate this product with the covers removed Do not connect or disconnect any cable probes test leads etc while they are connected to a voltage source Remove all power and unplug unit before performing any service Service should only be performed by qualified personnel Ground the Product This product is grounded through the grounding conductor of the power cord To avoid electric shock the grounding conductor must be connected to earth ground Operating Conditions To avoid injury electric shock or fire hazard Do not operate in wet or damp conditions Do not operate in an explosive atmosphere Operate or store only in specified temperature range Provide proper clearance for product ventilation to prevent overheating DO NOT operate if any damage to this product is suspected Product should be inspected or serviced only by qualified personne
33. each of any warranty concerning these goods shall be repair or replacement of defective parts or a refund of the purchase price to be determined at the option of VTI For warranty service or repair this product must be returned to a VXI Technology authorized service center The product shall be shipped prepaid to VTI and VTI shall prepay all returns of the product to the buyer However the buyer shall pay all shipping charges duties and taxes for products returned to VTI from another country VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming when properly installed on that product VTI does not however warrant that the operation of the product or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The warranty shall not apply to defects resulting from improper or inadequate maintenance by the buyer buyer supplied products or interfacing unauthorized modification or misuse operation outside the environmental specifications for the product or improper site preparation or maintenance VXI Technology Inc shall not be liable for injury to property other than the goods themselves Other than the limited warranty stated above VXI Technology Inc makes no other warranties express or implied with respect to the quality of product beyond the description of the goods on the face of the contract VTI specifically disclaims the implied warranties of mer
34. ead from this register reflects the previously written value Because of the required memory size bits DA DO are disregarded on writes and always read back as 0 Upon receiving a hard reset all bits in this register are set to 0 A soft reset does not affect the value in this register VT1802 Programming VXI Technology Inc Reserved Register 0x08 Read Only D15 DO Unused Always read back as FFFF Reserved Register 0x0A Read Only D15 DO Unused Always read back as FFFF1g Reserved Register 0x0C Read Only D15 DO Unused Always read back as FFFF 16 Version Number Register 0x0E Read Only D15 D8 Firmware Version Not applicable reads back as 0016 Number D7 DO Hardware Version This code is incremented each time hardware changes are made to the Number VT1802 module VXI Interface FPGA Scan Function The latest scan list updated is complete done D14 D10 Unused These bits are always read back as 0 s D9 Over current Error An Over current event either HI or LO has occurred on a channel between Detected 61 and 120 The OC registers for this bank must be queried to identify the Channels 61 thru channel s that indicated an Over current Event 120 The Over current event will reset the affected channel effectively shutting it off To turn the channel on again its Select bit must be re set See the A24 A32 Channel Select
35. enabled the highest priority will take precedent The rest will be ignored In a trigger mode the user first must set up the desired triggers by accessing the Command Trigger Control Register see page 30 When the VT1802 is already in the trigger mode any change to the Channel Output Enable and Channel Output Level Select will not be executed until 1 Both EXT TRIGI and EXT TRIG2 go to a TTL high level for AND setting or 2 Either EXT TRIGI or EXT TRIG2 goes to a TTL high level for OR setting or 3 Any falling rising edge on Backplane TTLO 7 Triggers line for TTL Trigger setting and External Trigger is not enabled or 4 Software trigger bit in the Trigger Control Register is set All other functions are not affected by triggering 20 VT1802 Module Use and Operation www vxitech com Channel output can be monitored via a comparator and a read back register The level of the comparator is set in a DAC in each bank The DAC setting must take hysteresis and component variation into account CALCULATING HYSTERESIS The following equation is used to calculate hysteresis for the VT1802 Vut 20 21 VxVdac 75 21 V Vit 20 21 V x Vdac where Vut upper threshold limit Vit lower threshold limit Vdac is the output of the DAC set by the user LEVEL Vdac range 0 V 75 V Vdac resolution 75 4095 18 3 mV Component variation error is 3 for Vdac hence Vut and Vit have a 3 error as well The
36. er channel OVER CURRENT PROTECTION Per channel 12 VT1802 Introduction www vxitech com SECTION 2 PREPARATION FOR USE INTRODUCTION When the VT1802 is unpacked from its shipping carton the contents should include the following items 1 VT1802 module 1 VT1802 User s Manual this manual All components should be immediately inspected for damage upon receipt of the unit The chassis should be checked to ensure that it is capable of providing adequate power and cooling for the VT1802 Once the chassis is found adequate the VT1802 s logical addresses and the backplane jumpers of the chassis should be configured prior to the VT1802 s installation After the VT1802 is assessed to be in good condition it may be installed into an appropriate C size or D size VXIbus chassis in any slot other than slot zero CALCULATING SYSTEM POWER AND COOLING REQUIREMENTS It is imperative that the chassis provide adequate power and cooling for this module Referring to the chassis operation manual confirm that the power budget for the system the chassis and all modules installed therein is not exceeded and that the cooling system can provide adequate airflow at the specified backpressure It should be noted that if the chassis cannot provide adequate power to the module the instrument might not perform to specification or possibly not operate at all In addition if adequate cooling is not provided the reliability
37. has occurred A 0 indicates no Over current Event has occurred An over current event will set the appropriate Over current Status bit and will also disable the associated channel s Channel Select bit Once disabled the channel may again be enabled by setting the channel s Channel Select bit to 1 See the Channels n 60 49 Channel Select Register description above D11 DO pe J i The bits contained in these registers provide status only and do not affect the 24 13 operation of the associated channels A read of these registers will clear the Over 12 1 current Status bits in the associated register to 0 Removing the over current condition does not reset these bits Once set the bits are not cleared except until there is a read of the associated register A recurrent over current event will again disable the associated channel by resetting the channel s Channel Select bit It will also set the Channel Over current Status bit If the status bit had not been cleared it will remain a 1 Section 1 Channel Over current Status HI Register Read Only ADDR A24 A32 Offset 0x016 0x01A 0x01E 0x022 0x026 D15 D12 Unused All bits are always 0 Channel Over current HI Status bits A 1 indicates that a V HI Over current Event has occurred A 0 indicates no over current event has occurred An over current event will set the appropriate Over current Status bit and will also disable the a
38. hysteresis voltage is 3 6 V for the whole range Please note that due to hysteresis as Vdac is set to 0 the upper limit threshold Vut will be 3 6 V MODULE INSTALLATION Before installing a VT1802 module make sure that the mainframe is powered down Insert the module into the chassis by orienting the module so that the card guides of the module can be inserted into the slot of the chassis Position the module so that it fits into the chassis slot groove Once the module is properly aligned push the module back and firmly insert it into the backplane connector FRONT PANEL CONNECTOR LOCATION ASSIGNMENTS The Figure 2 3 illustrates the physical location assignments for each connector on the front panel of the module This view depicts all connectors for both the VT1802 The module s front panel LEDs may be monitored for an indication the VXI module s operation The function of the LEDs is as follows LED Name Function Power Illuminates green when power is applied to the module Not illuminated when there is no power to the chassis This LED is not programmable Error Not illuminated under normal operating conditions Illuminates red if an Error condition occurs This LED is programmable Fail Illuminates green under normal operating conditions Illuminates red if an ac fail condition occurs This LED is programmable Access This LED flashes green when data is accesses or written to the VT1802 s registers
39. iLo ATTR ON COLOR VAL GREEN ledEnab 1 Il next enab led control ledHiLo 1 Il next hilo ledR dbk 1 Il next rdbk ledOchi 1 Il nextochi ledOclo 1 Il next oclo regMask lt lt 1 Il shift the register mask DisplayP anel mainHndl break return 0 46 VT1802 Programming www vxitech com INDEX Numerics 28 V power supply enable bit ii 32 28 V power supply status bit essere 32 7 73 V power supply enable bit sss 32 713 V power supply status bit iii 32 A AIG address Space ene ee liano 27 ATO register descriptions ote eene ee es 27 A24 A32 extended memory sss 34 A24 A32 active bit A24 A32 enable bit A24 A32 memory offset bits essere 27 address space s Address Space bits ritenta rio N 27 addressing rn e RR A IRINA 25 B backplane JUMP liana n eee cian backplane TTLO 7 trigger bit M board X Y used address register sss 29 C calculating system power and cooling requirements 13 cause status Dit coat ii 28 certification X channel 49 60 Vout HI bits etes 36 channel 61 120 Vout HI bits ie 40 channel 61 120 Vout LO bits sese 40 Channel bits 34 38 channel output status bits 37 41 channel output threshold voltage
40. ions divided into three sections Backplane Interface Output Control Enable Channel Output Select Channel Level Select Bank Voltage Over current Status Output Monitor Output Threshold Voltage Channel Output Level Status Readback See Figure 2 1 illustrates these divisions VT1802 Module Use and Operation 17 VXI Technology Inc Output Control 60 channels 5 banks Output Monitor SMIP Power Supply Backplane Interface Control Output Control 60 channels 5 banks Output Monitor FP Trigger FIGURE 2 1 BASIC OPERATION DIAGRAM Each section is further divided into five 12 channel banks see Figure 2 2 Each bank of 12 channels is set to either 73 V HI and 2 5 V LO or 28 V HI and GND LO Each individual channel can be set to either HI LO or OFF If a user for example sets bank 2 to 73 V then channels 13 24 can be either 73 V 2 5 V or off Similarly if the user sets bank 6 to 28 V then channels 61 72 can be either 28 V GND or off Each channel is capable of sourcing sinking up to 140 mA at 28 V The maximum for the 73 V line is 1 mA It is imperative to keep this in mind when operating the VT1802 Should an over current condition I gt 140 mA occur the channel is shut off and an over current event is registered for that channel By accessing the ENABLE and LEVEL registers via the soft front panel
41. ister Read ONlY sse 39 Section 2 Voltage Level Control Register Read amp Write sse 40 Section 2 Channel Output Hardware Revision Register Read Only 40 Section 2 Channel Monitor Output Status Register Read Only sse 41 Section 2 Channel Monitor Output Threshold Voltage Register Read amp Write 41 Section 2 Channel Monitor Hardware Revision Register Read Only n 41 Using the Code iran iii e t EA ee ee Rede eA RS 42 Wrap Around Test Exat ple tassi la te a e ee ee ie etd 42 INDEX de SPUR 47 VT1802 Preface www vxitech com CERTIFICATION VXI Technology Inc VTI certifies that this product met its published specifications at the time of shipment from the factory VTI further certifies that its calibration measurements are traceable to the United States National Institute of Standards and Technology formerly National Bureau of Standards to the extent allowed by that organization s calibration facility and to the calibration facilities of other International Standards Organization members WARRANTY The product referred to herein is warranted against defects in material and workmanship for a period of three years from the receipt date of the product at customer s facility The sole and exclusive remedy for br
42. l Improper Use The operator of this instrument is advised that if the equipment is used in a manner not specified in this manual the protection provided by the equipment may be impaired Conformity is checked by inspection 8 VT1802 Preface www vxitech com SUPPORT RESOURCES Support resources for this product are available on the Internet and at VXI Technology customer support centers VXI Technology World Headquarters VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 Phone 949 955 1894 Fax 949 955 3041 VXI Technology Cleveland Instrument Division 5425 Warner Road Suite 13 Valley View OH 44125 Phone 216 447 8950 Fax 216 447 8951 VXI Technology Lake Stevens Instrument Division VXI Technology Inc 1924 203 Bickford Snohomish WA 98290 Phone 425 212 2285 Fax 425 212 2289 Technical Support Phone 949 955 1894 Fax 949 955 3041 E mail support vxitech com Visit http www vxitech com for worldwide support sites and service plan information VT1802 Preface 9 VXI Technology Inc 10 VT1802 Preface www vxitech com SECTION 1 INTRODUCTION OVERVIEW The VT1802 is a high performance high voltage I O module with ten groups of 12 channels for a total of 120 channels per module Each group of channels may be configured as an input or output under program control Individual channels can be set to tri state mode In the outpu
43. ll clear the Over 84 73 WE f iis 22 61 current Status bits in the associated register to 0 Removing the over current condition does not reset these bits Once set the bits are not cleared except until there is a read of the associated register A recurrent over current event will again disable the associated channel by resetting the channels Channel Select bit It will also set the Channel Over current Status bit If the status bit had not been cleared it will remain a 1 VT1802 Programming 39 VXI Technology Inc Section 2 Voltage Level Control Register Read amp Write ADDR A24 A32 Offset 0x A00 D15 D13 Unused Writing to these bits has no effect Read back value is what was written Channel 0 Vo HI is 28 V D12 120 109 1 Vou Hl is 73 V Vou HI Pon state 0 Channel 0 Vo HI is 28 V D11 108 97 Vou HI is 73 V Vou HI Pon State 0 Channel 0 Vo HI is 28 V D10 96 85 1 Vou HI is 73 V Vou HI Pon state 0 Channel 0 Von HI is 28 V D9 84 63 2 Vou HI is 73 V Vou HI Pon state 0 Channel 0 Von HI is 28 V D8 72 61 1 Vou HI is 73 V Vou HI Pon state 0 D7 D5 Unused Writing to these registers has no effect Read back value is what is written Channel 0 Vou LO is ground D4 120 109 1 V LO is 2 5 V Vou LO Pon State 0 Channel 0 Vou LO is ground D3 108 97 2 Vou LO is
44. lways read back for this bit DS D3 Interrupter IRQ The complement of the value programmed into these three bits reflects the Line selected IRQ line used by the module A value of 011 would select IRQ4 a value of 000 would select IRQ7 and a value of 111 would disconnect the IRQ lines D2 DO Handler IRQ Line The module has no interrupt handler capability therefore writing to these bits has no effect A 111 is always read back for these bits Note that all bits in this register are set to 1 upon receipt of a hard or soft reset Subclass Register 0x1E Read Only D15 VXIbus Extended Always reads as 1 Device D14 DO Extended Memory Always reads as 7FFD ge Device LED Control NVM Access Register 0x20 Read Only D15 D9 Unused All bits are always 1 D8 Error LED Control Reads back the value of ERROR LED D7 Dl Unused All bits are always 1 DO Reads back the serial data stream from the on board EEPROM device LED Control NVM Access Register 0x20 Write Only D15 D9 Unused Data written to these bits have no effect D8 Error LED Control 1 Write a 1 to this bit to enable the front panel ERROR LED 0 Write a 0 to this bit to disable the front panel ERROR LED D7 D2 Unused Data written to these bits have no effect DI Serial clock for module should be a logic 1 when not used DO Serial data input must be a logic 1 when not used
45. mainHndl MAIN RDPY EVENT COMMIT VI NULL 0 0 Delay dlyTime Il check what we wrote to the Hi Lo register iStatus vivm1802 getBankData instHndl outBank vtvm1802 PIN H ifliStatus VI SUCCESS MessageP opup ERROR getBankData failed ifinpData outData MessageP opup ERROR Output bank read data not equal to write data gStatus dpyUpd1802 mainHndl MAIN RDPY EVENT COMMIT VI NULL 0 0 Delay dlyTime Il now read the data from the output bank readback register iStatus vivm1802 getBankData instHndl outBank vtum1802_PIN_RDBK_REG amp inpData ifliStatus VI SUCCESS MessageP opup ERROR getBankData failed ifinpData outData MessageP opup ERROR Output bank readback data not equal to output bank write data gStatus dpyUpd1802 mainHndl MAIN RDPY EVENT COMMIT VI NULL 0 0 Delay dlyTime Il now read the data from the input bank readback register iStatus vivm1802 getBankData instHndl inpBank vtvm1802 PIN RDBK REG amp inpData ifliStatus VI SUCCESS MessageP opup ERROR getBankData failed ifinpData outData MessageP opup ERROR Input bank readback data not equal to output bank write data x ILO REG outData LO REG amp inpData gStatus dpyUpd1802 mainHndl MAIN RDPY EVENT COMMIT VI NULL 0 0 Delay dlyTime outData lt lt 1 VT1802 Programming www vxitech com outBank 1 Il our test board is bank 1 bank 2 inpBank 2
46. mented each time hardware changes are made to the VT1802 D7 DO Revision module Channel Monitor FPGA Code VT1802 Programming 4l VXI Technology Inc UsING THE CODE Wrap Around Test Example The following pages provide sample code for performing a wrap around self test A block diagram is also provided to show how the VT1802 should be configured and wired to perform this test All Channels is Channel X Sending 12 ch All Channels PS Ly Measuring 12 ch Channel Y FIGURE 3 1 WRAP AROUND SELF TEST DIAGRAM Required Settings for Measuring Bank e Channel Output DISABLED e Channel Output Level set preferably to LOW and Bank Voltage Level set to 0 V 28 V i e 0 V to avoid sourcing current if the Channel Output is mistakenly changed to ENABLE e Onthe Measuring Bank the DAC settings can be varied to measure the voltage from the sending channel Hysteresis must be taken into account Refer to page 21 for hysteresis calculations Note there is only 1 DAC per bank The Sending Bank settings can be set the same as for normal Output operation e Channel Output ENABLED e Bank Voltage Level 0 V 28 V or 2 5 V 73 V e Channel Level HI or LOW The following pages provide code for the wrap around test 42 VT1802 Programming www vxitech com int CVICALLBACK wrapTest1802 int panel int control int event void cbD int
47. nnel has experienced an over current event the 60 49 Channel Select bit must again be set to a 1 to allow the channel to source its 48 37 programmed output voltage D11 DO 36 25 24 13 0 Channel disabled 12 1 1 Channel enabled Select Pon state 0 NOTE If a Channel fails to operate properly or as expected then a read of the channel s Over current bit may be required to determine whether the channel has experienced an over current event or not Section 1 Channel Output Level Select Register Read amp Write ADDR A24 A32 Offset 0x002 0x006 0x00A 0x00E 0x012 D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel bits By setting these bits the associated channel is set HI or LO These Channels bits are not affected by an over current event The actual Vou HI and Vp LO of the 60 49 channel is set by the Voltage Level Control for the associated channel See page 36 48 37 for more information on the Voltage Level Control register 36 25 24 13 0 Channel output LO 12 1 1 Channel output HI Pon state 0 D11 DO 34 VT1802 Programming www vxitech com Section 1 Channel Over current Status LO Register Read Only ADDR A24 A32 Offset 0x014 0x018 0x01C 0x020 0x024 D15 D12 Unused All bits are always 0 Channel Over current LO Status bits A 1 indicates that a V LO Over current Event
48. nterface sa 17 Modes of Operation een aee tie e PN co dst Lele esee e ua ER SERE Ne ie diee ee 20 Trigger Operation A teta e Re RG LE ac eee tee Lenola 20 Calculating Hysteresis niei Recta ect e La REN CU HERR e EUER M e Ce OR ee Ge ai ana 21 Module Installation 2 2 eer rne een de 21 Front Panel Connector Location Assignments eere en nnne 21 SECTION 4 ete ena eenedn 25 PROGRAMMING wis i RHEINE ERO NR REMO dI E RO ae e ENEMY 25 Introduction RN 25 Pur dre A H A 25 Description of Registers Alt ee eet IE RE RR TEE ME I D UO RR TE COR RECO E ERE Tes 27 ID Register 0x00 Read OnNlY e 27 Logical Address Register 0x00 Write ONlY i 27 Device Type Register 0x02 Read Only ener enne ener nnn nnns 27 Status Register 0x04 Read Only sees esee e e eH E e e even 27 Control Register 0x04 Write ONlY ii 27 Offset Register 0x06 Read amp WErIte enne enne enne nnne nennen 27 Reserved Register 0x08 Read OnlY i 28 Reserved Register 0x0A Read Only nennen eren ener nnne nennen 28 Reserved Register 0x0C Read Only sse eene 28 Version Number Register 0xOE Read Only sse ener nnns 28 Interrupt Status Register 0x1A Read Only sse ener enne 28 Interrupt Control Register 0x 1C Read
49. ption above D11 DO p EC The bits contained in these registers provide status only and do not affect the operation of the associated channels A read of these registers will clear the Over 84 73 oe Ges 72 6 current Status bits in the associated register to 0 Removing the over current condition does not reset these bits Once set the bits are not cleared except until there is a read of the associated register A recurrent over current event will again disable the associated channel by resetting the channel s Channel Select bit It will also set the Channel Over current Status bit If the status bit had not been cleared it will remain a 1 Section 2 Channel Over current Status HI Register Read Only ADDR A2A A32 Offset 0x816 0x81A 0x81E 0x822 0x826 D15 D12 Unused All bits are always 0 Channel Over current HI Status bits A 1 indicates that a V HI Over current Event has occurred A 0 indicates no over current event has occurred An over current event will set the appropriate Over current Status bit and will also disable the associated channel s Channel Select bit Once disabled the channel may again be enabled by setting the channel s Channel Select bit to 1 See the D Channel Select Register description above D11 DO E i The bits contained in these registers provide status only and do not affect the operation of the associated channels A read of these registers wi
50. rol TRIG2 0 Write a 0 to this bit set the external triggers to EXT TRIGI OR EXT TRIG2 Pon state 0 For this bit s operation to be properly executed both EXT TRIGI and EXT TRIG2 must be enabled When only one is enabled this bit will be ignored D10 TTL Trig Polarity 0 sets the falling edge active 1 sets the rising edge active Pon state 0 D9 Software Trigger 1 Write a 1 to trigger command execution 0 Write a 0 to halt command execution Pon state 0 D8 Unused Data written to this bit have no effect and always read back as 1 D7 0 Software Trigger Sets the TTLTRIG line or lines which are configured as inputs and will trigger the VT1802 to execute command from user D7 corresponds to TTLTRIG7 D6 to TTLTRIG6 and DO to TTLTRIGO Setting a bit to a 1 enables the trigger line setting a bit to 0 disables the corresponding line All enabled TTLTRIG lines are OR d together to allow more than one TTLTRIG line to cause a Command Execution Trigger event to occur All bits are set to 0 when the module receives either a soft or a hard reset Note This is different from the setup of register 0x34 30 VT1802 Programming www vxitech com Trace RAM Restart High Register 0x28 Read amp Write D15 D4 Unused Data written to these bits have no effect and always read back as 1 D3 DO Sets the four most significant bits of the starting address of the Trace RAM allowing the avail
51. sed Data written to these bit have no effect D3 73 V Power Supply 1 The 73 V on board power supply is ON Status 0 The 73 V on board power supply is OFF D2 28 V Power Supply 1 The 28 V on board power supply is ON Status 0 The 28 V on board power supply is OFF DI 73 V Power Supply 1 Write a 1 to this bit to enable the 73 V on board power supply Enable 0 Write a 0 to this bit to disable the 73 V on board power supply Pon state 0 Note This bit must be set in order for the module s outputs to function properly DO 28 V Power Supply 1 Write a 1 to this bit to enable the 28 V on board power supply Enable 0 Write a 0 to this bit to disable the 28 V on board power supply Pon state 0 Note This bit must be set in order for the module s outputs to function properly TTL Trigger Polarity Register 0x38 Write Only D15 D3 Unused Data written to these bits have no effect D2 Over current Event 0 sets the falling edge active 1 sets the rising edge active Output Slope DI Trace Advance 0 advances on the falling edge 1 advances on the rising edge Input Slope DO Trace Advance 0 sets the falling edge active 1 sets the rising edge active Output Slope Note A hard or a soft reset sets D3 DO to 0 s 32 VT1802 Programming www vxitech com Trace RAM Control Register 0x3A Read amp Write D15 D14 Unused Must be set to 11 Set to 11 at power on D13
52. shold reference voltage that is set in the Channel Output Threshold D11 DO 36 25 Voltage register See the Channel Output Threshold Voltage register description 24 13 below 12 1 These bits may be used to monitor for the proper operation of the module s output channels NOTE Each channel s output status comparator has about 4 0 V of hysteresis Section 1 Channel Monitor Output Threshold Voltage Register Read amp Write ADDR A24 A32 Offset 0x604 0x606 0x608 0x60A 0x60C D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel Output Threshold Voltage bits The value written to these bits set the threshold voltage that will be used to indicate the channel s Output Status If the channel s output voltage is above the threshold set then the channel s Output Status bit will indicate a 1 If the channel s output voltage is below the threshold set then the channel s Output Status bit will indicate a 0 See the Channel Output Status Register description above a The actual Vo HI and Vou LO of the channel is set by the Voltage Level Control t bits for the associated channel See the Voltage Level Control register above vatem cos 0x000 Channel Output Threshold set to 0 V minimum 48 37 OxFFF Channel Output Threshold set to approx 75 V maximum 36 25 Pon state 0x000 24 13 2 1 Example Set register 0x208 to a value of 0x802 The thre
53. shold voltage for channels 36 thru 25 is set to 0x802 0xFFF 75 2050 4095 75 0 500 75 37 5 volts Note Each channel s output status comparator has about 4 0 V of hysteresis VT1802 Programming 37 VXI Technology Inc Section 1 Channel Monitor Hardware Revision Register Read Only ADDR A24 A32 Offset 0x60E D15 D8 Unused Always reads as 0016 Hardware This code is incremented each time hardware changes are made to the VT1802 D7 DO Revision module Channel Monitor FPGA Code Section 2 Channel Output Enable Register Read amp Write ADDR A24 A32 Offset 0x800 0x804 0x808 0x80C 0x8 10 D15 D12 Unused Writing to these bits has no effect Read back value is what was written Channel Select bits By setting these bits the associated channel is turned on enabled These bits are cleared by an over current event on a per channel basis The corresponding bits in the Over current registers can be used to identify channels that have experienced an over current event See Over current Register Channel definition below Once a channel has experienced an over current event the 120 109 Channel Select bit must again be set to a 1 to allow the channel to source its 108 97 programmed output voltage D11 DO 96 85 84 73 0 Channel disabled 72 61 1 Channel enabled Select Pon State 0 NOTE If a Channel fails to operate properly or as expected then a
54. ss Reserved Subclass Register Interrupt Control Interrupt Control Reserved Interrupt Status Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version Number Reserved Reserved Reserved Reserved Reserved Reserved Offset Register Offset Register Control Register Status Register Reserved Device Type Register LA Register ID Register If the VXIplug amp play drivers are being used these registers normally do not need to be accessed 26 VT1802 Programming www vxitech com DESCRIPTION OF REGISTERS A16 The following describes the registers shown in the VT1802 Register Map for A16 address space ID Register 0x00 Read Only D11 DO Manufacturer s ID VXI Technology Inc set to F4B 5 D13 D12 Address Space A16 A24 00 A16 A32 01 D15 DI4 Device Class Extended register based device set to 01 Logical Address Register 0x00 Write Only D7 DO Logical Address Sets the new logical address in a dynamically configured module When set for dynamic configuration set to FF 6 a soft reset will not alter the configured logical address while a hard reset will set the register back to FF D15 D8 Reserved Writing to this range has no effect Device Type Register 0x02 Read Only D11 DO Model Code Model 296 set to 12816 D15 D12
55. ssociated channel s Channel Select bit Once disabled the channel may again be enabled by setting the channel s Channel Select bit to 1 See the Channels HAE 60 49 Channel Select register description above DI11 DO i The bits contained in these registers provide status only and do not affect the 24 13 operation of the associated channels A read of these registers will clear the Over 12 1 current Status bits in the associated register to 0 Removing the over current condition does not reset these bits Once set the bits are not cleared except until there is a read of the associated register A recurrent over current event will again disable the associated channel by resetting the channel s Channel Select bit It will also set the Channel Over current Status bit If the status bit had not been cleared it will remain a 1 VT1802 Programming VXI Technology Inc Section 1 Voltage Level Control Register Read amp Write ADDR A24 A32 Offset 0x200 D15 D13 Unused Writing to these bits has no effect Read back value is what was written Channel 0 Vou HI is 28 V D12 60 49 2 V HI is 73 V Vout HI Pon state 0 Channel 0 Vou HI is 28 V D11 48 37 1 V4 HI is 73 V Vou HI Pon state 0 Channel 0 Vo HI is 28 V D10 36 25 1 V4 HI is 73 V Vou HI Pon state 0 Channel 0 Vo HI is 28 V D9 24
56. t mode each group can be configured with either 28 V or 73 V levels Logic programmability high low is on a per channel basis Two level sensitive trigger inputs provide the flexibility to set external input conditions that must be met before a channel is enabled The VT1802 is an ideal module for multiple channel I O applications which require the capability to source up to 140 mA per channel Each channel has built in over current protection ensuring that the board will not be damaged if its specifications are exceeded VT1802 Introduction 11 VXI Technology Inc VT1802 SPECIFICATIONS CHANNELS 120 single ended 60 differential VOLTAGE LEVELS 28 V dc 0 V or 28 V 41 0 V 73 V dc 2 5 V or 73 V 41 0 V CURRENT 28 V dc 140 mA maximum 73 V dc 1 0 mA maximum MAXIMUM LOAD 28 V dc 140 mA 84 channels and 73 V dc 1 mA 24 channels RISE FALL TIME 28 V dc ms 73 V dc 2 ms TRIGGER INPUTS External Triggers Two simultaneous TTL High State 2 4 V minimum Cannot exceed 5 V Low State 0 4 V maximum Must be greater than 0 V Internal Triggers Software Triggers Eight VXI backplane TTL triggers Via the soft front panel LOGIC PROGRAMMABILITY individual channel AMPLITUDE PROGRAMMABILITY 12 channels group CONNECTOR TYPES Current Driver 160 pin connector Power 2 pin D sub connector COOLING Worst Case 150 W TRI STATE P

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