Field Programmable Gate Array
Contents
1. the loop till all the control bits are transfered TOUCH CLKr lt High end else state touch 8 d3 8 d4 if count 500 5 touch clk neg begin state touch 8 d5 TOUCH CLKr lt High touch x1data count dat bit 1 b1 lt TOUCH MISO end else state touch 8 d4 8 d5 begin state touch 8 d6 count dat lt count dat bit 1 b1 end 8 d6 if count dat bit 8 DO begin state touch 8 d7 TOUCH CLKr lt low end else if count 500ns touch clk pos begin TOUCH CLKr lt low state touch 8 d4 end else state touch 8 d6 Read Data wait negedge clk 8 d7 begin state touch 8 d8 spi clk flag lt spi clk close Close the spi Clock TOUCH lt High end 8 d8 if count 2us 8 d99 begin state touch 8 d9 count 2us flag lt count 2us close end else begin state touch 8 d8 count 2us flag lt count 2us open end begin state touch 8 d10 spi clk flag lt spi clk open start spi clk 50ns or 2Mhz frequency TOUCH CsSr lt low count cmd bit lt 8 d9 to count MOSI control register bits count dat bit lt 8 d12 end 8 d10 Write control bits if count 500ns touch clk pos wait posedge clk begin state touch 8 d11 TOUCH CLKr lt low TOUCH MOSIr lt touch cmd y count cmd bit 2 b10 count cmd bit lt count cmd bit 1 b1 end else state touch 8 d10 8 d11 if cou2. The master pulls SS down to indicate to the slave that communication is starting SPI can easily achieve a few Mbps mega bits per seconds That means it can be used for uncompressed audio or compressed video ig 1 Single master sing CODE module spi CLK RSTn TOUCH_CS TOUCH_IRQ TOUCH BY TOUCH CLK TOUCH MISO TOUCH MOSI test y input CLK 50 Mhz input RSTn assign switch input TOUCH BY output TOUCH CS make gnd input TOUCH IRQ inout TOUCH IRO penirq output TOUCH CLK ads clock input TOUCH MISO from ads data output TOUCH MOSI to ads control register output 3 0 test reg TOUCH CSr reg TOUCH CLKr reg TOUCH MOSIr check Check the errer reg 7 0 count irq reg IRQ FLAG always posedge CLK or negedge RSTn if IRSTn begin count lt 8 dO IRQ FLAG lt 10 end else if count 8 d20 begin count lt 840 IRQ FLAG lt 1 b1 end else count_irq lt count irq 1 b1 assign TOUCH_IRQ IRQ FLAG 1 BZ 1 bO reg 7 0 count_500ns parameter T500ns 8 d24 25 20ns 500ns 0 5us reg spi_clk_flag define spi_clk_open 181 define spi_clk_close 1 bO K K K K K K K K K K K K K k k K always posedge CLK or negedge RSTn if RSTn
3. count 500ns lt 8 d0 else if count 500ns T500ns spi flag count 500ns lt 8 d0 else if spi clk flag count 500ns lt count 500ns 1 b1 reg 7 0 count 2us reg count 2us flag define count 2us open 191 define count 2us close 1 dO always posedge CLK negedge RSTn if IRSTn count 2us lt 840 else if count 2us 8 d99 Icount 2us flag count 2us lt 840 else if count 2us flag count 2us lt count 2us 1 b1 else count 2us count 2us define touch clk pos 892 define touch clk neg T500ns 2 define High 151 define low 1 bO parameter touch cmd x 8 1001 0000 x pos parameter touch_cmd_y 8 b1101_0000 Y_POS reg 15 0 state_touch reg 7 0 count cmd bit reg 7 0 count dat bit check reg 11 0 touch x1data reg 11 0 touch x2data reg 7 0 count sample always posedge CLK negedge RSTn if IRSTn begin state touch lt 8 00 spi clk flag lt spi clk close count cmd bit lt 840 c
4. lt count 2us open end endcase assign TOUCH CLK TOUCH CLKr assign TOUCH CS TOUCH CSr assign TOUCH_MOSI TOUCH_MOSIr assign test touch x1data 3 0 display the data collected fourth place endmodule FUTURE IMPROVEMENTS The touch screen can be mounted on a LCD module Thus the LCD Touch screen module can be used to develop further applications such as drawing pad
5. receive one bit per clock cycle else wire OversamplingTick BaudTickGen ClkFrequency Baud Oversampling tickgen clk clk enable 1 b1 tick OversamplingTick synchronize RxD to our clk domain reg 1 0 RxD_sync 2 b11 always posedge clk if OversamplingTick RxD_sync lt RxD sync 0 RxD and filter it reg 1 0 Filter_cnt 2 b11 reg RxD_bit 1 b1 always posedge clk if OversamplingTick begin if RxD_sync 1 1 b1 amp amp Filter_cnt 2 b11 Filter cnt lt Filter cnt 191 else if RxD_sync 1 1 bO amp amp Filter_cnt 2 b00 Filter cnt lt Filter cnt 191 if Filter_cnt 2 b11 RxD bit lt 1 b1 else if Filter_cnt 2 b00 RxD bit lt 160 end and decide when is the good time to sample the RxD line function integer log2 input integer v begin log2 0 while v gt gt log2 log2 log2 1 end endfunction localparam 120 log2 Oversampling reg 120 2 0 OversamplingCnt 0 always posedge clk if OversamplingTick OversamplingCnt lt RxD_state 0 190 OversamplingCnt 191 wire sampleNow OversamplingTick amp amp OversamplingCnt Oversampling 2 1 endif now we can accumulate the RxD bits in a shift register always posedge clk case RxD_state 4 b0000 if RxD_bit RxD_state lt ifdef SIMULATION 4 b1000 else 4 b0001 endif start bit found 4 b0001 if sampleNow RxD_state lt 4 b1000 sync start bit to sampleNow 4 b1000 if sampleNow R
6. the bottom layer The controller converts the Again the controller converts voltage to a number data and O m the voltage to a number data sends it to the host computer and sends it to the host computer TOUCH SCREEN CONTROLLER ADS7843 FPGA is a digital device hence it can process only digital input and gives digital output The output of a Resistive touchscreen is analog Hence to convert the analog output to digital an analog to digital converter touch screen controller is used Texas instrument s ADS7843 touch screen controller is used for this PIN CONFIGURATION SPECIFICATION 4 WIRE TOUCH SCREEN INTERFACE RATIOMETRIC CONVERSION SINGLE SUPPLY 2 7V to 5V UP TO 125kHz CONVERSION RATE SERIAL INTERFACE PROGRAMMABLE 8 OR 12 BIT RESOLUTION 2 AUXILIARY ANALOG INPUTS FULL POWER DOWN CONTROL SPI BUS INTERFACE SPI can be used as a simple and efficient way of communication between FPGAs and other chips It is synchronous It is serial It is full duplex It is not plug and play There is one and only one master and one or more slaves A clock is generated by the master and one bit of data is transferred each time the clock toggles Because SPI is synchronous and full duplex every time the clock toggles two bits are actually transmitted one in each direction MOSI is the master output while MISO is the slave output FPGA is the master and ADC is the slave in this case
7. INTERFACING TOUCH SCREEN WITH FPGA SUBMITTED TO INNOVATION CELL INDIAN INSTITUTE OF TECHNOLOGY BOMBAY SUBMITTED BY AEISHWARYA BAVISKAR ELECTRICAL AND ELECTRONICS ENGINEERING VNIT NAGPUR JENIL SAVLA ELECTRICAL AND ELECTRONICS ENGINEERING VNIT NAGPUR We would like to thanks Prof R K Singh and Prof 5 N Merchant for giving us opportunity for this project We would like to extend our sincere thanks to EbrahimAttarwala for his Guidance and support in completion of this project We would like to express my deepest appreciation to all those who provided me the possibility to complete this project We are highly indebted to innovation cell IIT Bombay for their guidance and constant supervision as well as for providing necessary information regarding the project amp also for their support in completing the project INTRODUCTION WHAT IS FPGA DE21 150 BOARD QUARTUS II GETTING STARTED WITH FPGA EXPERIMENTAL SETUP TOUCH SCREEN SPI SERIAL INTERFACE CODE 1 2 3 4 5 6 7 8 9 THE MAIN GOAL OF THIS PROJECT IS TO INTERFACE A TOUCH SCREEN WITH THE FPGA RESISTIVE FOUR WIRE TOUCH SCREEN IS USED FOR THE SAME TEXAS INSTRUMENT S ADS7843 SERVES AS A TOUCH SCREEN CONTROLLER WHICH CONVERTS ANALOG SIGNALS FROM TOUCH SCREEN TO DIGITAL SIGNAL THAT LATER IS PROVIDED AS AN INPUT TO THE FPGA PROGRAMMING OF THE FPGA IS DONE IN VERILOG HDL LANGUAGE THE BOARD IS PROVIDED WITH AN INDE
8. PENDENT PROGRAMMING PLATFORM QUARTUS II THE SERIAL COMMUNICATION IS ESTABLISHED BETWEEN THE FPGA AND THE ADC USING SPI SERIAL BUS INTERFACE WHAT IS AN FPGA Field Programmable Gate Arrays FPGAs are semiconductor devices that are based around a matrix of configurable logic blocks CLBs connected via programmable interconnects FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing Basic elements of FPGA gt Configurable logic blocks CLBs gt Configurable input output blocks gt Two layer metal network of vertical and horizontal lines for interconnecting the CLBs and FPGAs THE DE2I 150 BOARD Intel Atom N2600 w 4USB Host Pons VGA Out Gigabit Ethernet RS 232 Video jn VGA Out USB Blaster Programming Mace Switch USB Blaster Controller Chipset HSMC Connector Expansion Header with Protection Diodes Altera Cyclone IV FPGA GX Ernomot LED Gigabit Ethernet imal Chipset 1 Bios Flash 12 DDR2 SODIMM Sot BAME SDRAM gt 2 2M5 SSRAM x2 Accaler maler 412V Fan Connector LCD 16x2 Module IR Receiver SMA Ext Clock Qut M E 4 Supply Connector 4 SMA Ext Clock In Reset Button De E Fi t SD Card Siot gt 18 Red LEDs 18 Skde Switches 7 Segment Displays Green LEDs 4 Push buttons G4MB FLASH Mon Figure 1 1 The DE2i 150 board top view FPGA SPECIFICATIONS FEATURED DEVICES Cyclone IV EPACGX150DF31 d
9. evice 720 M9K memory blocks 6 480 Kbits embedded memory FPGA CONFIGURATION JTAG and AS mode configuration EPCS64 serial configuration device On board USB Blaster circuitry MEMORY DEVICES 128MB 32Mx32bit SDRAM 4MB 1Mx32 SSRAM 64MB 4Mx16 Flash with 16 bit mode CONNECTORS Ethernet 10 100 1000 Mbps ports High Speed Mezzanine Card HSMC 40 pin expansion port VGA out connector VGA DAC high speed triple DACs DB serial connector for RS 232 port with flow control CLOCK Three 50MHz oscillator clock inputs DISPLAY 16x2 LCD module 18 slide switches and 4 push buttons switches 18 red and 9 green LEDs Eight 7 segment displays QUARTUS II Quartus is a software tool produced by Altera for analysis and synthesis of HDL designs which enables the developer to compile their designs perform timing analysis examine RTL diagrams simulate a design s reaction to different stimuli and configure the target device with the programmer Its features include e Animplementation of VHDL and Verilog for hardware description e Visual edition of logic circuits e Vector waveform simulation We have used Quartus 12 1 and coding is done in Verilog To start working on your refer the user manual and the getting started guide which helps through the initial steps in quartus II Verilog tutorials www hdlexpress com by Kirk Weedman Books referred Verilog HDL programming by Samir Palnitkar http d1 a
10. le Acc lt Acc AccWidth 1 0 Inc AccWidth 0 else Acc lt Inc AccWidth 0 assign tick Acc AccWidth endmodule The above three modules are basic modules for serial communication Then you can write your own code to perform serial communication as you want For example for swapping the given stream of serial bytes below is a code module processor clk rxReady rxData txBusy txStart txData input clk input 7 0 rxData input rxReady input txBusy output reg txStart output reg 7 0 txData localparam READ 0 SOLVING 1 WRITE1 2 WRITE2 3 localparam LEN 10 localparam LENMAX LEN 1 integer ioCount reg 7 0 data O LENMAX integer state initial begin txStart 0 state READ end always posedge clk begin case state READ begin if rxReady begin data ioCount rxData if ioCount LENMAX begin ioCount 0 state SOLVING end else begin ioCount ioCount 1 end end end SOLVING begin integer i for i 0 i lt LEN 2 i i 1 begin reg 7 0 swap swap data i data i data LENMAX i data LENMAX i swap end state WRITE1 end WRITE1 begin if txBusy begin txData data ioCount txStart 1 state WRITE2 end end WRITE2 begin txStart 0 if ioCount LENMAX begin ioCount ioCount 1 state WRITE1 end else begin ioCount 0 state READ end end endcase end endmodule For more reference http www fpga4fun com SerialInte
11. mobbs com bbs upload782111 files 33 ourdev 585395BQ8J9A pdf You can start with some basic codes once a project is made in quartus http www terasic com tw cgi bin page archive pl Language English amp No 529 GETTING STARTED WITH THE FPGA IMPLEMENTING LOGIC GATES ON FPGA USING BLOCK DIAGRAM FILE A block diagram file is an easy way to get started Various logic gates and simple ICs such as encoders multiplexers are available ready to use in the library Here is an implementation of NAND gate https www youtube com watch v auQ7wpVH 0Q BINARY UP COUNTER USING ON BOARD LEDS AND PUSH BUTTONS There are 18 red and 7 green leds mounted on the board along with four push buttons and 18 slider switches Here is a code to access some of the leds and push buttons module countertest KEY LEDR input 1 0 KEY output 7 0 LEDR counter counter1 KEY 0 KEY 1 LEDR 7 0 endmodule module counter C CLR Q input C CLR output 7 0 Q reg 7 0 tmp always posedge C or posedge CLR begin if CLR tmp 8 b00000000 else tmp tmp 8 b00000001 end assign Q tmp endmodule ACCESSING INTERNAL CLOCK TO BLINK ONBOARD LEDS module clock_test CLOCK_50 LEDR input CLOCK 50 output 17 0 LEDR reg 17 0 tmp always posedge CLOCK 50 begin tmp lt tmp 1 b1 increment counter end assign LEDR lt tmp endmodule USING THE GPIO PINS TO MAKE AND GATE module andgate input 1 input 2 GPIO input input 1 in
12. nt cmd bit 8 DO count cmd bit 0 indicates that all the control bits are transfered now conversion can be achievec begin TOUCH MOSIr lt 190 TOUCH CLKr lt lt low if count 2us 8 d99 begin state touch 8 d12 count 2us flag lt count 2us close count dat bit 8 d12 spi clk flag spi clk open end else begin state touch 8 d11 count 2us flag lt count 2us open spi clk flag lt spi clk close end end else if count 500ns touch clk neg begin state touch lt 8910 to run the loop till the control bits are transfered TOUCH_CLKr lt High end else state_touch lt 8 d11 8 d12 if count 500ns touch_clk_neg begin state touch 8 d13 TOUCH CLKr High touch x2data count dat bit 1 b1 lt TOUCH MISO end else state touch 8 d12 8 d13 begin state touch 8 d14 count dat bit lt count dat bit 1 b1 end 8 d14 if count dat bit 8 DO begin state touch 8 d15 TOUCH CLKr lt lt low end else if count 500ns touch clk pos begin TOUCH CLKr lt low state touch 8 d12 end else state touch 8 d14 Read Data wait negedge clk 8 d15 begin state touch 8 d16 spi clk flag lt spi clk close Close the spi Clock TOUCH CSr lt High end 8 d16 if count 2us 8 d99 begin state touch lt 890 count 2us flag lt count 2us close end else begin state touch 8 d16 count 2us flag
13. ount sample lt 840 end else case state touch 890 if ITOUCH IRQ PENIRQ pulls low when a touch event occurs begin state touch 8 d1 count sample lt 840 TOUCH CSr lt lt spi flag lt spi clk close count 2us flag lt count 2us close TOUCH CLKr lt low end else begin state touch lt 8 d0 TOUCH CSr lt High TOUCH CLKr lt lt low end 8 d1 begin state touch 8 d2 spi flag lt 5 clk open start spi clk 50ns or 2Mhz frequency TOUCH CSr lt low slave select count cmd bit lt 8 d9 to count MOSI control register bits count dat bit 8 d12 end 8 d2 Write control bits if count 500ns touch clk pos wait posedge clk begin state touch 8 d3 TOUCH CLKr lt lt low TOUCH MOSIr lt touch cmd x count cmd bit 2 b10 count cmd bit lt count cmd bit 1 b1 end else state touch 8 d2 8 d3 if count cmd bit 8 DO count cmd bit 0 indicates that all the control bits are transfered now conversion can be achievec begin TOUCH MOSIr lt 140 TOUCH CLKr lt lt low if count 2us 8 d99 begin state touch 8 d4 count 2us flag lt count_2us_close count dat bit 8 d12 spi clk flag spi clk open end else begin state touch 8 d3 count 2us flag lt count 2us open spi clk flag lt spi clk close end end else if count 500ns touch clk neg begin state touch lt 8 d2
14. put input 2 output 0 0 GPIO wire and temp assign and temp input 1 amp input 2 assign GPIO 0 and temp endmodule SERIAL COMMUNICATION IN FPGA e USART SERIAL receiver module async receiver input clk input RxD output reg RxD data ready 0 output reg 7 0 RxD data 0 data received valid only for one clock cycle when data ready is asserted We also detect if a gap occurs in the received stream of characters That can be useful if multiple characters are sent in burst so that multiple characters can be treated as a packet output RxD idle asserted when no data has been received for a while output reg RxD_endofpacket 0 asserted for one clock cycle when a packet has been detected i e idle is going high b parameter ClkFrequency 25000000 25MHz parameter Baud 115200 parameter Oversampling lt 8 needs to be a power of 2 we oversample the RxD line at a fixed rate to capture each RxD data bit at the right time 8 times oversampling by default use 16 for higher quality reception generate if ClkFrequency lt Baud Oversampling ASSERTION_ERROR PARAMETER_OUT_OF_RANGE Frequency too low for current Baud rate and oversampling if Oversampling lt 8 Oversampling amp Oversampling 1 0 ASSERTION ERROR PARAMETER_OUT_OF_RANGE Invalid oversampling value endgenerate reg 3 0 RxD_state 0 ifdef SIMULATION wire RxD_bit RxD wire sampleNow 1 b1
15. rface html http www sparxeng com blog software talking rs 232 with cyclone ii fpga part 1 http www sparxeng com blog software talking rs 232 with cyclone ii fpga part 2 http www sparxeng com blog software communicating with your cyclone ii fpga over serial port part 3 number crunching EXPERIMENTAL SETUP 4 Wire Resistive Touchscreen Touchscreen controller RESISTIVE TOUCH SCREEN A touch screen is a 2 dimensional sensing device that is constructed of 2 sheets of material separated slightly by spacers A common construction is a sheet of glass providing a stable bottom layer and a sheet of Polyethylene PET as a flexible top layer The 2 sheets are coated with a resistive substance usually a metal compound called Indium Tin Oxide ITO The ITO is thinly and uniformly sputtered onto both the glass and the PET layer Tiny bumps called spacer dots are then added to the glass side on top of the resistive ITO coating to keep the PET film from sagging causing an accidental or false touch When the PET film is pressed down the two resistive surfaces meet The position of this meeting a touch can be read by a touch screen controller circuit Capturing the X Touch Capturing the Y Touch To get the X To get the Y touch position the controller sets Pin1 to 5 and Pin3 to GND 0V Pin2 is left unconnected The controller uses Pin4 to read the voltage where the top layer meets
16. rt signal tells it to start sending bits input start The bits of data to send reg 7 0 data LLL Serial port clock generator Generate a 9600 baud clock signal for the serial port by dividing the 50Mhz clock by 5208 reg 14 0 clockdiv Count from 0 5207 then reset back to zero always posedge clk begin if clockdiv 434 clockdiv lt 0 else clockdiv lt clockdiv 1 end The serclock is a short pulse each time we are reset wire serclock clockdiv 0 LLL Serial port state machine Only start the state machine when start is set Only advance to the next state when serclock is set reg 3 0 state always posedge clk begin case state 4100000 if start state lt 4450001 4 b0001 if serclock state lt 4400010 Start bit 4 b0010 if serclock state lt 4 b0011 BitO 4 b0011 if serclock state lt 4 b0100 Bit 1 4 b0100 if serclock state lt 4 b0101 Bit 2 4 b0101 if serclock state lt 4 b0110 Bit 4 b0110 if serclock state lt 4 b0111 4 4 b0111 if serclock state lt 4 b1000 Bit 5 4 b1000 if serclock state lt 4 b1001 Bit6 4 b1001 if serclock state lt 4 b1010 Bit 7 4 b1010 if serclock state lt 4 b1111 Stop bit default state lt 4 b0000 Undefined skip to stop endcase end WII T BT B B B B Serial port data Ensure that the serial port has the correct data on it in each sta
17. te reg outbit always posedge clk begin case state 4 b0000 outbit lt 1 idle 4 b0001 outbit lt 0 Start bit 4 b0010 outbit data 0 Bit 0 4 b0011 outbit lt data 1 Bit 1 4 b0100 outbit lt data 2 Bit 2 4 b0101 outbit lt data 3 Bit 3 4 b0110 outbit lt data 4 Bit 4 4 b0111 outbit lt data 5 Bit 5 4 b1000 outbit lt data 6 Bit6 4 b1001 outbit lt data 7 Bit 7 4 b1010 outbit lt 1 Stop bit default outbit lt 1 Bad state output idle endcase end Output register to pin assign ser outbit Test by outputting a letter d always posedge clk begin start 1 end endmodule UART BAUD RATE GENERATOR module BaudTickGen input clk enable output tick generate a tick at the specified baud rate oversampling parameter ClkFrequency 25000000 parameter Baud 115200 parameter Oversampling 1 function integer log2 input integer v begin log2 0 while v gt gt log2 log2 log2 1 end endfunction localparam AccWidth log2 ClkFrequency Baud 8 2 max timing error over a byte reg AccWidth 0 Acc 0 localparam ShiftLimiter log2 Baud Oversampling gt gt 31 AccWidth this makes sure Inc calculation doesn t overflow localparam Inc Baud Oversampling lt lt AccWidth ShiftLimiter ClkFrequency gt gt ShiftLimiter 1 ClkFrequency gt gt ShiftLimiter always posedge clk if enab
18. xD_state lt 4 b1001 bit O 4 b1001 if sampleNow RxD_state lt 4 b1010 bit 1 4 b1010 if sampleNow RxD_state lt 4 b1011 bit 2 4 b1011 if sampleNow RxD_state lt 4 b1100 bit 4 b1100 if sampleNow RxD_state lt 4 b1101 bit 4 4 b1101 if sampleNow RxD_state lt 4 b1110 bit 5 4 b1110 if sampleNow RxD_state lt 4 b1111 bit 6 4 b1111 if sampleNow RxD_state lt 4 b0010 bit 7 4 b0010 if sampleNow RxD_state lt 4 b0000 stop bit default RxD_state lt 4 b0000 endcase always posedge clk if sampleNow amp amp 31 data lt RxD 7 11 reg data error 0 always posedge clk begin RxD_data_ready lt sampleNow amp amp RxD_state 4 b0010 amp amp RxD_bit make sure a stop bit is received RxD_data_error lt sampleNow amp amp RxD_state 4 b0010 amp amp RxD_bit error if a stop bit is not received end reg 120 1 0 GapCnt 0 always posedge clk if RxD_state 0 GapCnt lt 0 else if OversamplingTick amp GapCnt log2 Oversampling 1 GapCnt lt GapCnt 1 h1 assign RxD_idle GapCnt I20 1 always posedge clk RxD_endofpacket lt OversamplingTick amp GapCnt Il20 1 amp amp GapCnt I20 0 endmodule e USART SERIAL TRANSMITTER Serial port demo program Assumptions 50Mhz clock rate module serial data clk ser start input clk output ser input 7 0 data Sta
Download Pdf Manuals
Related Search