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Roland Promars MRS-2 ServiceManual

1. 4 2 CLEAR 2 42 TEHE _ 1840492 TRUTH TABLE QUAD EXCLUSIVE OR GATE Yop TC4016 QUAD BILATRAAL BWITOH BLOCK DIAGRAM Impedance Between IOUT U AN a Pb ma 2 PELLET os erando gt 0 SEMICONDUCTOR DIAGRAMS i 7445175 QUADRUPLE D TYPE FLIP FLOP JAN 31 1980 TC4051BP SINGLE 8 CHANNEL MULTIPLEXER DEMULTI PLEXER TC4082BP DIFFERENTIAL 4 CHANNEL MULTIPLEXER DEMULTIPLEXRR SN74LS174 b tvbe FLIP FLOP Y CHO CHa amp VDD 8 b CHE b Y 00MMON COMMON Y OH3 OH 1 o X CHO CHS 5 CHS INHIBIT o X CH3 INHIBIT o 4 VEE 4 BB o o B GND 9 TRUTH TABLE 18599 CHANNEL 4 O QUADRUPLE 2 NPUT INHIBIT Cc a 40618 POSITIVE NAND GATES ee 1 am ay fam RS 1 2 11 02 Sass 9 X irrelevant Lu s sx ux 1v oz f transition from low to high LOL 1 T 12 T Qu the aval of Q batoro the indicted stacy atate La fefefe ena Input conditions were established gt e or 11 1 147178
2. ee JAN 31 1980 eSPECIFICATIONS eKEYBOARD 37 keys 3octaves F F eVCO VOLTAGE CONTROLLED OSCILLATOR X2 VCO RANGE 16 8 4 WAVEFORM 21 PULSE WIDTH 50 40 20 10 VCF VOLTAGE CGNTROLLED FILTER HPF CUTOFF 40Hz 5kHz LPF CUTOFF 20Hz 20kHz ENVELOPE GENERATOR 1 EACH FOR VCF VCA ATTACK TIME 0 6ms 3sec DECAY TIME 14ms 10sec SUSTAIN LEVEL 0 100 RELEASE TIME 14ms 10sec MRS 2 SERVICE NOTES 5 AND OUTPUTS eLFO Low Frequency Oscillator WAVEFORM V U N N LFO RATE 0 1Hz more than 80Hz eDELAY BEND SECTION DELAY TIME 0 10sec eTUNING MASTER TUNING greater than 1 semitone VCO 2 TUNING greatr than 1 octave VCO 2 TUNING greater than 1 octave eCONTROLLER SECTION PORTAMENTO 0 3sec OUTPUT LEVEL selectc H OdBm 6dBm L 12dBn HEADPHONE jack ster 8 2 HEADPHONE LEVEL sector H M L BEND CONTROL IN with BEND SENSITIVIT control at 10 VCO approx 2v 8va VCO approx 2v 8va VCF approx 1 v 8va approx 1v 2 2d3 CV OUT jack 1v 8 val GATE OUT jack 10v CV IN jack 1v 8va GATE IN jack greater 10v GENERAL VCO greater than 1 octave VCF greater than 2 octaves resonance pitch greater than 6dB 1248 Knob No 56 Panel No 265D 072 265D 016 056 Side Panel No 7OB 083 070B D SUGL Noc c
3. 5 5 E to MOTHER BOARD 1 422 2 29C BIS Y ici to MOTHER BOARD A27 A24 ED 22 i A25 4 control sign 2 SC 828 25K 30A GR 191508 K 25 5 v 10812 Pin 7 158 mar if GATE ON NOISE 024 Emitter sl BAGE 1 4558 QO e lt NUS UR Padi coo 5 TOTUM T Tx Wm voa euer unen cen oom ovem R 7 Dep Aen Pee TIERE E JAN 31 1980 At EEE gt e 5 m UD 9 98 For the 148 200 5 8 of MODULE BOARD Assy 181 2920 CI p 4 pomes only L J L 5 VCO d R 104 TC4069UBP 2 O Sie see z 1619 GUPPIX PROMARS PLASTIC PACKAGE 4 cot te 26 0432 Th MC 1486 1 P eee NE diem opel TD T cl 29274 5 Contro Voltage ics 4 40 si JB 5 F 45 d 1 Discharge y E T YCC e EU vco
4. d CE TRAIG POSS SUBTEACTOR vov a t 9 20 4001 05 To m 1620 11111111 2 VCO Q Bosi 11 20 MODULE 21 25 MODULE CONTRE Board N2 No 8 No 9 107 e me cf em n us xt ee aes ES e ce ee uot Poe cn ab 8 d BH i 8 HH I AA By TT 4 8 7 mn LFO LFO SELECT DECODER A CPu RESET Se o aD bs S SS S D A lt gt SS 1 A 12 _ MOTHER BOARD 1 Mob wE Mod All Sliders on the PROGRAMMABLE section are set at VCF ENV EL MOTHER BOARD OP 104B Etch mask 052 364B FO RATE S y CMOS multiplexers enable pulses 0 1111 TT 17 CUTOFF IMPORTANT Figures in TP colum in the table to immediate ri at top of the other tables refer to test points layout below The following applies l For sliders voltage will vary within the rang as the designated slider is being moved 2 For switches the output will be a logical O 0V 415V 15V 45V 0V 45V depending on
5. t oT ee Don t Care DON T CARE D DATA TEHDIT 2 ul gu t BOARD 162 x E 4 1 VCF ENV cd mumonR MULTIPLEXER DECAY CLK Ium T 080 2 7 COMPAR 5 HHL umL HEAD CONT IN PRON 5 MODULE CONTROL BOARD VCO 9 BOARD MODULE BOARD 8 44 pg YO0 2 A TUNS B TUNE MASTER TUNE to PANEL Jt 3t to BENDER BOARD 2 Ct Control du i KEY Cv BOARD Wwe M KEY BOARDO HOLD GATEQur TEIN 1 tSv TRAG PGE SUBTEACTOR Multiplexer enable pulse quM 400 52 5 VIEW LC 12 t i d 5 WR to Contre Beard F lt 57 EJ et i 21 lt gt x alo 7 1 T RE c 23 1 T 18 511384 a m 3 48 Lu esc tels Y iC 9 10 BB 5 Io
6. DONO to M quus 0 108 rNO USE 4 2 73 4016 A 8 5 4 d NO 518 see el gt j sop ge BENDER BEND cont IN Cs ME do KEY CV Bender Board BENDER BOARD H i didi 0P 107 10 021 Headphone TRANS poss ee ARN ay Control 10 102 Ea oer PCB 237 pei TOWN e M nnn pPo58 Sw 162 1 1 3 Ql 2501815 9 4 Joy 9 1 8 M i n 02 28A1015Y 42 1 LFO Modulation 181588 1599 ven 2 BEND SENS 152 009A PCB 052 439A bneloR Sl ACES S20 J4d 151568 eee 25 1015 Y 2561815 Y d R 30 5 VCO 9FABOARD Assy PCB 052 439A Polystyrene Film c ecttor 8 Ec CRB MFR 6 MF VR JAN 31 1980 91 od 181555 28 1015 K 2861815 x 36 i R24 IM 5 b 6louT FSET NULL Connection Diagram View 2 een 8 1 p 42 6 2 T4 eek E ico Dotted lines and pa
7. depending on the lever position TEST POINTS N 00 E 02 check both the existing board for existance or absence of Q15 5 19 for modification Be GOs oo oo ss sia i Componentes on foil side C48 C49 5 Connector amn 1 2 EIL A6 A10 A14 Guar eu A2 4 LAE 2276 37 7 j ge E Y j A18 2 E 2 lt lt connections to Power Supply Board El MOTHER BOARD 13 BENDER BOARD OP 107B 149 107B Mi C Q ODULc CONT afte UM p 9977 Lert cae Tea hee ee Tn SRLS APN eee ee c MASTER TUNE 2 3 E a YN PI r E i 2 il x 9 lt 4 n 4 7 at View from foil side pue 5 CONTROL BOARD A a OP 109A 149 109A View from foil side eg qu 2 iu rd x 2 gt H M 5 a E DUCI arf 2 D 2 5 E 3 m Gea e Eb d iE g nc 4 m 4 ae 23 bp Rep a aa va P P its lt x he z m A ae
8. EP 39 4 84 8 h i TOP VIEW UR BEEN Sos js 4 DNH19 he 1 9 FEMME LOPE lt ENVELOPE 123 4 160 ERATOR GENERATOR WAVE FORM SELECTOR 8 00 4016 233 t PEE P gt Capacitors on the C R80 BET foil side 0 1047 M eame z 033 034 035 and Y 91 me 1000 100 nect to 101 20 126 CCELI HE Lp Ts ej Rie RIS E e 060 a al 1 ami eh _ 5565 j ES 4 2 161588 i 5 BULL to MOTHER BOARD 48 12 16 20 to MOTHER BOARD 47 11 15 19 25 1015 Y to OTHER BOARD A6 10 14 18 to MOTHER BOARD A5 9 13 17 K 5 1815 2 Po 97 Film Capacttor NOTE RI53 8 154 are 25K30A eR bs PROMARS 2 Resonance cae MFR 008958 he 020 em MF VR ex R O in MOD U LE B OA RD OPSTOD compatible OP 105E 20 31 1980 MODULE BOARD ES A of 0 aS 7 dat 2 78147 Aste Haste TAS a e 6 lt O I o Ad 4 Dw si 42 g ar LON e i ri A 3 a a Eh
9. use the IO when 41 065 066 No 66 065 252 No 232 specified in the circuit diagram 055 003 Rechargeable Batt Ty 4N 100AAS 065 143 No 143
10. Studing A conversion theory on the Mother Board by observing the converter output wveform is very helpful in understanding the operation of microcomputer 8048 01 1 The omputer 8048 012 reads Sliders set positions through A D 2 The omputer reads between A D and D A conversions Panel switches status 3 In Mual Mode at CP15 final of A D and D A outputs are equal in level Thisieans that Panel Data are fed into Synthesizer Modules as they are Hower in other modes A D and D A show different values because they are t of relation to each other D A converter transforms digital data fromhe memory 4 Durii D A conversion sliders data being D A converted from 6 bit fornat and itch data from 2 bit format are held latched and output to the syntsizer modules Slider Switch Slider Switch Reading Reading Reading Reading lt VOF ATTACK This slider LEVEL is set positions iat 3 A D 1 D A output 1 MEnable pulse 105 106 Slr read pulse CP11 CP12 NP E CP 9 DMEnable pulse 1031 71032 TRA Data Latch Gapulse 11 1012 Srs and Switches CP16 or CP17 D Hold pulse Signals Flow Diagram on the Mother Board PANEL Pots data 16 pot 101 8 Digital Data Latch ICs 7 8 108 11 12 ICs31 32 EET Level Shift Q5 Q14 to
11. Allow at least five minutes for warmup m 1 Connect digital voltmeter to 1 N 1 Y 2 Adjust 1 for 15 0410mV i f 5 Check other voltages they must be i 5 0x250mV and 15 0 750mv GROUND 1 Connect scope to TP 5 on 0 104 9 C o JAN 31 1880 I 5 VCO FREQUENCY and WIDTH Switch to A or B before adjusting VCO 9 Board to OP 104 2 key 2 Connect and set instruments as above MODULE BOARD OP 105 1 While depressing A2 key Adjust P 7 for 1 2 Lissajous figure 2 While depressing AO key adjust P 6 for 2 1 Lissajous figure 2 O key To disconnect VOO 1 signal path N Pull the housing off the PCB Reverse it and plug in the right pin only O Set VCO 2 TUNE switch to A TUNE B TUNE Q Adjust P 6 and P 7 on VCO 9 Board following the steps in OP 105 9 DAADA QD 1161 MODULE BOARD 69 69 65 63 G2 D 99 43480 08 TP 4 immers Jumper GHOUND 3 0 3 MOTHER BOARD 104 8 VCO WAVEFORM Pulse width 50 i feat Point on OP 104 OP 105 Set P 8 s respectively VCO 9 for 50 duty ratio with C1 key holding down 7 VCF FREQUENCY arid WIDTH DELAY BEND NOTE Due to the digital control character istics of this VCF if CUTOFF FREQ knob is moved steadily and slowly the r
12. DMPX amp HOLD circuits 2 The lower 2 bits data DBO are fed in time sequence to the input pin of each respective address data latch 4099 1011 IC12 The two 4099s latch them in separate 7 groups under the control signals from 8048 012 to pins 4 5 6 7 15V The outputs of 14 kinds go into the level shift ircuit following 13 4099 where they are shifted into levels each suitable for the Control Signal purpose to each Section surrounding 03 014 Lei Shift Circuits 3 Of the 14 those of VCO WAVE 1 and LFO WAVE 1 are fed to the Wave form selector IC19 IC20 and LFO Select Decoder 1035 1034 to receive each respective decoding VCO RANGE 1 Range 1 input go into Transpose Subtractor where the contents of the 2 bit data of RANGE 1 are converted when the Transpose Input is __ Range 0 turned to I Refer to Table 20 output for what conversion is meant on this transpose In effect Transpose by the Subtractor it is to go down by 1 octave on VCO range as shown by arrows Thus the Switch con trol signals in 14 kinds be come to control the Module Boards after passing through these circuits as above Ls IC20 4010 transpose IC21 4001 Tmspose Subtractor OTHERS Reset Circuit The circuit is to protect 8048 012 from running pro gram inadvertently When RESET pin 4 is turned to Lj it makes 8048 012 to reset back to the initial s
13. 111 149311 PS 52 146 052 100V VCO 9 Contrl1 Board PS 53 OP 134 14 134 146 053 ndi VCO 9 52 009 54 146 054 220 240V Module OP 105 19 105 Module ontrol Board 106 149 06 LEVEI Switch Board II OP 113 149 113 LEVEL Switch Board I OP 112 149 112 Mother Board OP 104 149 104 When ordering PCB suffix an alphabetical letter to the part numbe refferring to the Parts List and PCB Wiring Layout Jack HLJO102 01 040 6 pes 009 025 Hinge No 3 115 003 Music Rack Hder No 219B 064 19B cJ Roland Chassis No 242E Switch SSBO2532 061 2428 001 271 Jack HLJ 235 070 Stereo 001 0 JAN 31 1980 KEYBOARD PARTS KEY SPRING 7 KEY HOLDER 7 064 083 CHASSIS GUIDE BUSHING 064 056 SIDE ANGLE 7 068 016 Y ACTUATOR RUBBER 107 052 CONNECTOR 2146 KEY ASSEMBLY IVORY 106 015 G IVORY 106 016 IVORY 106 017 C D ACTUATOR 102 003 CONTACT LEAF SPACER IVORY 106 019 071 001 073 051 BUS BAR HOLDER 064 057 BUS BAR CONTACT LEAF PRINTEO CIRCUIT BOARD HOLOER RESISTOR 6P 064 051 7P 064 052 RESISTOR 070 052 071 34 052 066 052 067 100 1 4W 1 CRB1 4FX 8 142 4 070 052 052 066 052 067 100 1 4W 1 1 4 052 067 100 1 64 070 052 Cc 052 066 052 067 100 1 44 1 CRBI A
14. 54 is the first to be checked and adjusted Also repairing or replacing 2 3 PS Board forces readjustment of some associated PCBs CV 3 0 104 VCO 9 and FO Cl HE 02 12 05 OP 105 KEY CV BOARD Replacing a PCB other ihan Power Supply Board involves readjustment of its own 3 1 While depressing Cl and 2 keys VCO 9 _ CONTROL alternately adjust P 3 so that 052 468 Connect digital voltmeter CoV zQ1V 1 00V 3mV CONTROL BOARD B CONTROL BOARD C to the hot terminal on 2 Hold down Cl key and adjust P 2 CV OUTPUT jack 110 111 052 528 to provide 2 0042nV 2 Check octave keys for errors 02 3 00 3mV 05 4 004 3mV 052 442 LEVEL SWITCH BOARD 3 LEO WAVEFORM M MODULE BOARD 14151121 P E SUPPLY BOARD P 105 052 314 18 52 53 53 104 MODULE CONTROL BOARD MOTHER BOARD 22 440 Conhect oscilloscope to TP 4 on Mother Board OP 104 see next gt l djust P 4 for slope straightness Numbers Q 2 5 etc in above figure show adjusting trimmer potentiometera wrong good and are independent of designations in individual circuit diagram E In this adjustment trimmer pots are abbreviated as P xx 4 Trimer QD Y 1 DC VOLTAGE 15 POWER SUPPLY BOARD N PS 52 53 54 S 4
15. D A Conversion Analog Data Hold Digital Data Hold KCV and GATE generation These are however now produced by the computer s internal circuits and the synthesizer circuits are under fully voltage controlled programed and or given by the computer with self contained transconductance amps or analog switches etc 8048 012 Flow Chart However the circuit and function themselves of VCO VCF VCA etc of the synthesizer s main circuits are just as the same as before with those on the conventional synthesizer 21 JP 4 PROMARS 16 bits bits 6 bits 0 10 feats sa Ip 1 DESCRIPTION F 77731 Control SW Mother Board Block Diagram 1 Scanning of all the switches on the Control Panle such as Memory Write SW Manual SW Compu Memory SW Pre Set Selection SW etc 2 Converting the Analog signals obtanined from Sliders and Switches of the Programmable Section on the Control Panel into 8 bit digital data A D conversion This data reading is repeated 16 divided times to complete them all 3 Storing these A D converted data of the POTs and SWs into memory for use afterward upon retrieval 4 Converting back again these digital data 2 Manual Switc into analog voltage D A conversion to send UN ee 00e them out into Synthesizer Modules All these functions stated above are perform ed under the control of 8048 012 Functions of 804
16. Panel bender no 268B 082 0698 Side Panel no 69B right 083 0708 Side Panel left 111 024 Foot collar no 24 black 0480 CA25 115 003 Hinge no 3 064 2198 Music Rack Holder no 219B 004 011 Keyboard Assy SK 132G 091 0174 Endblock 17 right 065 52 Blind H52 KNOB BUTTON 016 033 Knob no 33 slider 016 056 Knob no 56 rotary small 016 057 Knob no 57 rotary large 016 009 Button no 9 1 016 085 Button no 85 white 016 086 Button no 86 red 016 087 Button no 87 green 016 088 Button no 88 yellow 016 089 Button no 89 blue SWITCH Push 001 250 BUF J2 interloak 001 225 SUF 12 MEMO WRIT M PROTCT 001 226 SUF 12A HOLD 001 215 SDG5P 501 1 power 100V 001 216 BSDG5P 501 2 117V 001 217 SDG5P 502 220 240V Lever 001 237 LBC 42M 18K PW NOISE etc 001 238 LBC 22M 18K TUNE PORTA etc 001 182 001 205 001 271 001 228 001 224 001 234 PCB 149 1048 149 105D 149 105 149 106C 149 10 7B 149 108C 149 1094 149 110D 149 1118 149 112 149 113 149 1544 152 003B 152 0094 146 052F 146 05 3F 146 054F 052 195 052 307 JACK 009 002 009 045 009 025 Slide SSB 022 ANGE SUB on off SSB 023 988 02332 EVEL SQPR 2412P IO WAVE PW Rotary SRM 1043K15 700 WAVEFORM SRM 1034K15 VCO RANGE OP 104B Mother Bord 052 5648 OP 105D Module Bord PCB 052 314D 1058 compatib e with OP 105D OP 106C Module Coitrol PCB 052 235C OP 107B Bender 4 PCB 052 441B O
17. gt om mm f gom e On P ET PS OS PS P Hl gem 71 225 Switch SUF J2 001 250 all diodes 181588 YR7 R10 p Na D 46294 j Cin zw tr 2 am 2412 001 228 2 18 001 237 Misa C gt j 5854 029 555 11 12 NTROL SOARD Cb 27 5046 09 5046 0104 View from foil side JAN 41 1980 4150 715v 0 2 TUNE 0 2 ON OFF amp d Es oe oes E ENVELOPE ECIUM WAVEFORM _ RATE RANGE PW WAVE FORM ___ one 9 9 p Control Board Contro Board B Assy SUB E 49 lt y Pe 3 0604 Pou yan Ny tl zi 19 A B 93 18 OP 109 3 22 m S i Rien 47 vRi S SOKB 8 3 47K 3 gt 4 k EE Ra RM 83 e 4 nu 7 Q 6 x Ol SIS 18 212 48 181588 EE 25183518 AHRR MODULE CONTROL BOARD 09 RosorR to HE BOARD 73 MOTHER EE T to MOTHER BOARD to MOTHER BOARD A4 821 K esce 4 25K OP 112 te Ev CONT P qn uu T Ls ie 334 to
18. 020 181 pPC51010 E 064 230 No 230 Control Board Panel 017 128 28 596 020 032 1A 26HC i 017 110 2801815 179 021 pPD8048C 12 017 135 s 28D234 Y 020 141 SN74LS175N CONNECTOR 017 140 250880 020 054 1511 010 177 PICD 9P T1 Mother Board male 017 016 28K3OATM GR 020 100 11082 010 178 PICD 98 TL1 Module Module cont 9 female 017 056 412 dual FET 020 059 20819 020 160 BA662A a afer Terminal pin 020 096 _ 846628 Erect Right Angle non BA662S factory selected 010 182 5045 024 2 pin 010 192 5046 02 018 018 1N4003 010 183 5045 03 3 pin 010 193 5046 03A 010 18 045 04A 2 059 For there are factory sijlected 010 ope DOJO OAA 018 082 02 rectifier bridge 010 195 5046 054 018 092 RD BA662s painted in particuler colors 010 186 5045 06 6 pin 010 196 5046 06 7 2 1 zener according to the electrical jharac 010 187 2045 07 7 010 197 5046 0 018 015 507 1000 thermistor 010 188 5045 8 019 022 GL 3AR1 LED power memory Wh the 662 P th 010 189 5045 09A 9 pin 010 199 5046 09 019 020 GL 3AR2 LED LFO VCA ee ee 010 190 5045 10 10 pin 010 200 5046 10 same color and when ordering idenote color as well 6628 Although some equivalent ICs are inter COVER changeable however due to character 048 046 Heat Sink No 46 065 065 65 065 190 No 190 18510
19. 1 3 a 59 u 22 u ae N w lo wm gt gt H O A sc Sale 4 35 3le lt omo e n 6 a amp 5 5 gt lt 5 l 3 p 5 5 5 a 2 g NEM 2 014 o 6 Zena gt d CERE 5985 58 5252 d c 5333 NA o LI lt ea a jew e D a QUO D gt P Q 8983 aaa 245953 h H o 1 i gt gt Ai meee 21525 8 853 oO Q 9 1 1 1 A Ay 0 0 M OO N aro o 30 7 oof N 30 TE 9 e HOO aoe 1131 862 QOr gt o d A A 2570 z 53 3 USS doo 90 4450 O oss 312 lt af LO Wd _ ee x 5 So o Ort OO P N OSP qe 9 4111 A M ED 388 eo 5 S Bads 6 m moo O 3 JAN 31 1980 ADJUSTMENT 2 KEY and WIDTH Because certain circuits of PROMARS are voltage controlled Power Supply Board TUNE WIDTH PS 52 53
20. 106C 149 106C PCB 052 235C Moving the D or R Dl D6 Cathodes sliders from bottom to will increase the frequency by 1 104049 Outputs approximately 1000 E 4 Y 2 as LB D H 4 1 2295 a 7 5 4 1 C ETE 4 z1 PUE iE 472 tae 27 sv 2 vex a FAN p 5 7 Li he z E a AES 4 atte AA 2 JAN 31 1980 CONTROL to Centre Board F 31 to Bender Board 2 b Control Board A G 1 _ 4 _ 35182 EERE 918 151 8 CONTROL BOARD Assy 0 106 8855583 IT _ 5 7 o OO o52 235 we 2 ENV CLK Generator C s PW Controller e A 022 747 LOK 10 81 6 5 6K qm 14 i MAE i P gt a aene mc 9 MEQUE mE J ot i 2 2 15 6 fom du 5 4 D n 4 M 3 2 F k 45 3 58 STET as ES 7 1 POSITION to 9n 3 r TC4069UBP ONLY C9 10 16 1 ET 8728 22 21 Q27 25 828 144514444820 of PE Selected for 14 T Notse Generator 51812 77 18 82 85115 85 81 212253 lt 1225
21. 279 ECQS1102KZ polyatyrene JAN 31 1980 j HOLDER FUSE FUSEHOLDER 1 O6 H H 008 026 8640001 1A prim 100 117V 2 4 t Maa qs T 008 063 T500mA prim 220 240 7 020 040 14011 064 185 No 185 Module Module Cont 9 left 008 028 5640002 2A 100 117V 008 070 CEE sec 220 240 020 085 14016 064 186 186 Module Module Cont VCO 9 Mother Board 020 076 MC14024 064 187 No 187 Power Switch 012 003 758 clip fe 020 093 014025 B 064 203 No 203 Bender Panel Bender Board 020 015 MC14049 064 204 No 204 Bender Panel Bender Board 022 104DN Power transformer 100V 020 090 MC14051 064 205 No 205 Bender Unit 022 10400 Power transformer 117V 020 091 MC14052 064 210 No 210 Bender Panel Bender Board 022 104CD Power transformer 220 240V 020 177 MC14070 064 219 No 219 Music Rack Panel 022 94 Coil 24 333 020 178 014099 064 226 No 226 End Block 020 084 040690 only 064 227 227 Side Panel 020 031 2300 064 231 No 231 Control Board Panel SEMICONDUCTOR 020 106 7805DC 064 252 232 Bender Panel Keyboard i 020 108 781500 064 235 No 233 Battery 020 097 4558 064 239 No 239 Mother Board Chassis 28A1015 Y 020 101 pbOTA10 064 249 No 249 Push Switch 11 022 258434 0
22. 3 7 TRESS IS aE i c Knob No 57 016 057 Power consumption 20w Overall size 765 w x40dd x 162 h mm Weight 14kg Accessories 2 5m conection cord Knob No 33 016 033 Side Pane No 69B 082 069B PROMARS am 121 177 RE ih tei eo eee il COTA UPR OD ROO Dn A pes mma Keyboard assy SK 132G 004 011 Buttons No 9 Black 016 009 No 86 Red 016 086 No 85 White 016 085 No 87 Green No 89 Blue 016 089 No 88 Yellow 016 088 Ie Roland Printed in Japan 1 Power switch DISASSEMBLY SDG5P 501 1 001 215 100V SDG5P 501 2 001 216 117V SDG5P 502 001 217 220 240V Button No 9 016 009 55 RETR 5 Removal Screws 2 025252 Ren 1 Front Upper panel 2 Bender Control Block 2 3 3 3 Keyboard Holder No 203B 064 203 Holder No 205B 064 205B Holder No 204B 064 204 Foot collar 80480 CA25 1 111 024 Knobs No 56 Panel 2688 Felt No 27 016 056 072 268B 101 027 ER ir a Holder No 232A 064 2224 Bender Board OP 107 149 107 Key CV Board CV 3 Nylon Rivet Bender 152 003 NRP 335 4pcs Unit PB 4 122 001 029 022 MRS 2 Control Board F OP 108 149 108 Control Board B OP 110 149 110 Control Board A OP 109 149 109 Control Board Power Supply Board OP
23. 8 012 Tone color setting controller These operations of 8048 012 are shown in the flow chart The 8048 012 repeats such flow chart cycle The following numbers refer to those in flow chart l When the power is turned on 8048 012 Starts its reading and puts into memory the data of the positions it reads of Memory Write Switch Manual Switch Compu Memory Selection Switch and Preset Selection Switch 2 The 8048 012 takes in at first the voltage data of one of the Slider pots on the Control Panel and converts it into 6 bit digital data At the same time it reads out the Switch Position on the Control Panel and converts it too into 2 bit digital data The two data thus obtained are combined to make a total 8 bit data These are held there for a while 5 If the MANUAL Switch was OFF at step 1 the program proceeds to step 4 or if ON to 7 During this process the data obtained in step 2 is maintained 4 When the Memory Write Switch was OFF at step l the program goes to step 5 if ON to to 6 The step 2 data is still maintained 5 Based on the data being held in step 2 the 8048 012 accesses to either RAM Random Access Memory when a switch in Compu Memory was pushed in or ROM Read Only Memory when one of Preset Switches was in It then reads out from the address corresponding to the switch depressed the data to give control to the Synthesizer Modules 6 Based on the data in step 1 i
24. 8178 and 8178 Juni LB wow nong Don t Care a TC 4052BP BAG E 431 TO4001P QUAD 8 INPUT POSITIVE OATB Dual In Line Paskago ane i n PD5101C E TC4025P TRIPLE 3 INPUT POSITIVE NOR GATE PIN CONFIGURATION LOGIC SYMBOL GROUND 1 GROUND o m VoD TCe001P VDD 7 026 INPUT 2 1001907 A 22 n e 9 v 4 S 8ALANCE 4 5 y Aa to 2 3 9 10 view ENa 0 BLOOK DIAGRAM eo 7 10 TLO82 TLOT72 18 Vggi8 4 9 101112134 28 1 LM355 TC4011P QUAD 2 INPUT POSITIVE NAND GATE e 4558C B 9 8 LATOHEB8 14 13 12 11 10 6 4 9 Connection Diagram Top View TRUTH TABLE Reon 8 184 o B as as ue ae a se eevee Titty gt gt gt gt 1 L iire 1 TC40153P 1 5 13 1 ese SSR a sem ly 51 J uf ufau ly 4 1 5 1 1 1 1 1 1 eg s 1 1 1 1 1 i s 1 1 1 1 1 1 5 gt 2 5 or 1 1 1 2121 51 1
25. CA ENV GEN etc perpral circuits ref to the General Bloc Diagram when Compu Phonic Synthesizer is composed of the Conventional Synthesizer Synthesizer Control Circuits with PD838048 Control Panel 2 1 Control Section Switches and Sliders Sliders and switches on the control panel are now not for the production of the synthe sizer control signals directly such as the production of the time constants ON OFF switch ing etc They now serve only to letting the computer know of their positions or the states as they are put on the Control Panel 2 2 Voltage Controlled Synthesizer Circuits Such parameters as the time constant ON OFF switching or their signal levels etc have so far been produced on the control panel there are Sliders and switches to obtain directly of such VCO VCF VCA as its central point and the synthesizer circuits which are fully controlled by Synth voltage Circuit Switch Reading Panel Data Reading A D Conversion Timbre setting Computer Control Pane Programmable Section Compu Memory Data Buttons Preset emory 2 Buttons gt 1 1 amp GATE Key assign Diode Matrix Computer In JP 4 the Poly JP 4 only Assign Mode Phonic Synthesizer Switch 8048 is adopted on its key assigner circuits too
26. DULATION Test Point 3 on OP 104 1 Adjust P 13 on OP 105 so that moving ENVELOPE MOD between O and 10 produces no frequency change fest Point 10 on 106 Cohnect scope ground to 0 2 on OP 104 1 Set P 20 on OP 106 for 150mVpp 10 Test Point TP 3 on OP 104 Uf 4 1 49 8 25 0 150 JAN 31 1980 LFO VCF MODULATION Test Point TP 11 on OP 106 see section 20 Grounding Point Ground 3 G 3 on OP 104 eo ES l Set P 19 on OP 106 for 48 LFO MODULATION 1 With C2 key held down push BEND MOD extremely right and set P 18 on OP 106 for 100 modulation a 1 m Ill fest Point TP 11 on OP 106 Ground Point 0 2 on OP 104 Attack Time is defined the time from a keying to a sudden frequency drop 1 Depress C2 key and adjust P 23 on OP 106 5 4 86 80 that Attack time becomes 3 sec 4 control Measuring A tanlb tima her ban shee key ON 1 Test Point 11 on OP 106 Ground Point 6 3 on 0 104 17 VCF ENVELOPE DECAY Test Point TP 11 on OP 106 Grounding Point 0 2 on OP 104 1 Adjust P 21 on OP 106 so that frequency lowers to 1 10 of its initial value in 4 sec after depressing C2 key 18 VCF ENVELOPE RELEASE 72227201 1205 1 Adjust 22 on 106 so that frequency lowers to 1 10 of its in
27. E Y Ret 1 lt s 3 ag 3 pite TAR Y E M LI d E d 2 1 3 E EU aue 4 E gr F x 5 lt lt 5 m E 4 9 87 55 5 i eat si 3 2 oat ig b Ea bo 2 cx un 32 D 2 LEVEL SW BOARDS IPHONES OUTPUT OP 112A 1 Y349 112A 149 113 PCB 052 443A SSB 02332 001 271 0 134 EVH LWAD25B15 030 951 SWs LBC 23M 18K 001 238 _ CONTROL OP 109 VR3 EVA V17C16C26 029 370 VR4 EVA V23C16B54 029 426 345 LBC 42 18K 001 237 2 3 25 18 001 238 544 5 120 42 18 001 237 VMIORBlOC2MAK2O0 LBC 42M 18K 001 237 107 028 756 CONTROL B 941 5 SQPR 2412P 001 228 SW2 388 022 001 182 SW3 SRM 1054 K15 001 234 884 7 SW6 SRM 1043 K15 001 224 All Pots EVA V17C16B54 029 355 9 CONTROL BOARL OP 134A 149 1344 Wiew trom foil side CONTROL C SW1 SQPR 2412P 001 228 542 LBC 42M 18K 001 237 All Pots EVA V17C16B54 029 355 a 0 JULY 31 1979 CONTROL BOARD F c 5046 094 5046 054 Etch mask 052 237C m 149 108C a m
28. FX SH 2 57 _ SK132H 070 052 1 006 052 066 0 2 067 100 4w 1 _ aes 070 052 071 006 052 066 052 067 1 SK 132 B 070 052 071 006 052 066 1K 1 4W 27 SELECTED SK191 B 070 058 071H04 052 081 0 052 082 052 066 052 067 100 1 44 14 CRB1 4FX 052 067 100 1 4W 1 CRAL 4FX MRS 2 27 8 1520 070 052 071 006 052 066 052 067 100 iwk1 CRBiFX RS 101 61 SK 161 A 070 05 8 071 007 052 081 052 082 85 202 qe SK 161 A 070 058 071 007 052 081 052 082 E EC NE MEM RS 505 49 192 070058 1 071H043 y 052 081 052082 EP 10 61 5 162 070 058 071 007 20 61 SK 162 A 070 058 071 007 i m EP 30 61 SK 162B 070 058 071 007 052 081 052 082 JAN 31 1980 Funcion of 16 pots i 0 CIRCUIT DESCRIPTION 1 Operational Principle In the conventional synthesizer the circuits In t Mother Board VCO VCF VCA etc are directly controlled inclled are the What is Compu Phonic Synthesizer Features of Gompu Phonie from the control panel Control Synth Circuit 2 Hardware readig the following Panel VCO VCF VCA micrzomputer 8048 In the compu phonic synthesizer it is the 012 14 its computer that comes in between and provides control voltages suitable to those VCO VCF V
29. P 108C Control PCB 052 237C OP 109A Control A PCB 052 4424 OP 110D Control PCB 052 239D OP 111B Control 0 052 328 OP 112A Level SW 1 I PCB 052 4434 OP 115A Level SW II PCB 052 4424 OP 134A 0 9 Conirol Board PCB 052 468A CV 3B KCV Board PCB 052 440B VCO 9A 0 2 Board 052 439A PS 52F Power Supply Board PCB 052 327F 100V PS 53F Power Supply Board PCB 052 327F 117V PS 54F Power Supply Board 052 327 220 240V LED Mounting Board or or power switch LJ 039 1 6 or HLJ 0235 01 070 HLJ 0102a01 g tereo MRS 2 POTENTIOMETER Rotary 029 022 PB 4 Bender unit assy 028 756 VMLORB1OC K20 2 028 762 VMIORB10C K20 50KB 028 992 EVHDOAK15 50KB BRILLIANCE 028 1109 EVHB8AK15 SOKA VOLUME 028 1118 15 SOKB M TUNE 030 951 EVHLWAD25B15 50KB A B TUNE Slide 029 255 EVAV17C16B54 50KB 029 370 EVAV17C16C 26 2MC 029 426 BVAV23C16B54 50KB Trimmer 030 469 SR 19R 47KB horizontal 030 471 SR 19R 100KB 050 660 SR 29R 4 7 erect 030 662 SR 29R 10KB 030 666 SR 29R 47KB 030 668 SR 29R 100KB 030 493 CR 19R 4 7KB horizontal blue 030 505 CR 19R 470KB 030 689 89PR 20K helical 030 688 500 ohm helical RESISTOR CRBiFX 4W 1 044 909 2K 044 846 100K 044 844 6 8K 044 849 180K 044 905 18K 044 926 1M 044 887 20K CAPACITOR 035 091 ECQF2334MZ polypropyrene 055 278 ECQS1681KZ polystyrene 035
30. Synthesizer Modules gt Indicate Data Flows from the Control Panel Will be output to the Synthesizer Modules only in Manual Mode Show Data to from the Memories in Compu Memory and Preset Modes Will not be output to the Synthesizer Modules in Manual Mode Common lines for the data from the Control Panel and the Memories vin uu i DESCIIPTION DEIGNATION B 1 Dga Bus 2 3 4 5 6 7 P10 POR 1 12 15 14 15 16 17 P20 POR 2 21 22 23 24 25 26 27 1 XTA 2 RESIT T1 RD WR ALE Top View TOO XTAL XTAL 2 o RESET INT C EA RD PSEN WRO ALE O DB DB DB DB DB DB o DB o NO ceo 00 a ts 13 14 15 16 17 18 19 27 28 29 30 31 32 33 34 21 22 23 24 35 36 31 38 39 10 11 JAN 31 1980 es Switches Data 8114 Lieu te cdm ae and Panel T Switches Data Sliders Scanning during RAM Data address I O address 4051 103 106 1031 1032 4099 1011 1012 5101 102 select 28 08 y baap P ct 5 Switch Scan Data Reading Da 8048 012 Logical Symbol Inputs for internal Clock Oscillator Reset pulse input Comparator output signal input during A D conversion Memory read timing signal output Mem
31. again The same process continues through the lesser significant bits as on step 3 6 on figure Signals on Comparator Input pins Output OV t L H L H LiH 1 Decision LU 1 D A Converter DB7 input data DB6 DB5 DB4 DB3 DB2 X irrelevant DBO comaring data Input Data Comparison Each time the D A output approaches successively nearest to the A D input voltage And finaly when 8048 completes them all for DB7 to DB2 for bits it has decided the data on the nearest approximation to be equal to that of input of the A D converter Memory Here provided on this Compu Phonic Synthesizer are CMOS RAM IC2 5101 for memory of the tone color timbre data to be used on Compu and ROM which resides in 8048 012 for ase on PRESET mode 8 bits ACCESS to 5101 Memory Address 18175 WR DB7 4 DB3 0 RD 1 1 8048 012 R timing signal Address Latch Enable 8XH Chip Enable signal 8048 012 outputs from Port 1 the address data to turn the Chip Enable CE1 to L on 5101 Then 8048 012 outputs the pulses from ALE pin to make LS175 IC7 IC8 latch the data and define the memory address upon 5101 while the memory address being defined by 15175 8048 012 outputs onto DBO to DB3 the data to be written These data are then written onto 5101 by turning WR to L and are read by 8048 through DBO to DB4 when RD is L The digital data on th
32. e Control panel are 8 bits format However when made access to 5101 they are divided into 2 by 8048 012 Because 5101 han dles 4 bit quantities 2101 is backed up by the NiCd battery for pro tection of its memory The NiCd battery will be fully recharged for more than 48 hours The memory on 5101 are also protected for an hour by the electrolytic capacitor 1000mfd 6 5V just in case when the battery is removed for replacement or other CIRCUIT DESCRIPTION 15V 5V x 5 EMEN 1 3 gt M 8 EXTERNAE DATA MEMORY READ FROM EXTERNAL DATA MEMORY DCSupply for 5101 5101 READ WRITE CYCLE GENERATION of CONTROL SIGNALS to MODULE BOARD S The cotrol data that were A D converted to kinds of analog voltages and 14 kinds of binary 8 bit igital data are re converted to 16 signals before they are sent to the Module Board s 1 Th 8048 O12 reads out these DMPX here is to separate digtal data of 16 bytes suc the input data into 16 at 0 cesively from RAM or ROM Upper the control signals from 6 tts DB7 to DB2 among them 8048 012 1631 32 pins 6 arenade to analog voltage thru 9 10 11 They are held at D iconverter are put TLO82 1022 through 1029 to sirle line in time sequence and be sent out to the Module aresent to l output analog de Controller and the Module pypxl 15 muliplexer DMPX IC21 1C32 4051 Board Control Signal
33. erator Tne are two Envelope Gerators one each for VChnd Tne are basically the cinits to voltage control RA IC2lb th ime or the level of A Attack m 1022 D R Since the signals S m ENV araow in the pulse forn 1 MEE TLog2 94 beg voltage pulse con verd on the Module Con trcBoard the A D and R corols are to be achieved by trolling the number Sustain Control pulses IC25 ofilses a given time 4001 Notthat these pulses here aref so narrow width that itiy easily be lost of sig from screen on the oscloscope if the pulse intvals were extended a lite long ICzis the flip flop which inverts itself on is a pulse arrival thus making C20 to charge arring at the attack level IC24 is the gate discharge accordingly se ting the pulse for each of D and by ie timing of the flip flop 1022 is the aneg switch which turns on only when there GATE TP constan On such charge discharge envelopes are devel oped The envelopes from C20 are fed through buffer 1021 to obtaine low output impedance MODULE CONTROLLER Mode Controller Board is to control those on The Module Controller perform Mode Board as follows P S these functions by converting the control Signals fed from the 0 modulation Mother Board or those fed from the Bender F modulation Board into such signals to suit for controlling modulation the modules neration of the clock signals to control He
34. es if the antilog current is doubled IC5b watches this to keep the balance at this pin 6 And if losing the balance it sends an additional voltage onto VCO to make it regain the balance These are the process how to output the frequency which is antilog proportional to the input voltage The pulse output here is of so nar row width as yet It is necessary therefore to provide further wave conversion IC6 is a frequency divider IC7 is a multiplexer to make selection from those divided frequency C IC5a aR 14052 NAAN Sawtooth 86 out 1058 generates sawtooth waveform synchro nized to that of the selected frequency The amplitude of the sawtooth waveform is kept constant by choosing either of R18 R24 by the multiplexer IC7 regardless of any change made at the tone feet On PROMARS it has a VCO 9 Board for its 2nd VCO This Board is in effect just as the same that the VCO section is only taken out from the Module Board stated herein CIROIT uu DESRIPTION JAN 31 1980 2 CF and its Peripherals is not much different from those IC18 is the electronic potentiometer to control theconventional synthesizer ICll is the the depth of the cutoff frequency modulation hig pass filter 1012 1015 are the low pass IC19 pins 5 6 7 is the cutoff frequency con filers 1017 is the circuit for setting Q trol mixer Q8 and Q9 are the antilog current forthe low pass filters generation circuit 3 Envelope Gen
35. esonating VCF will produce frequencies in a series of Steps If CUTOFF FREQ is set ata point exactly between two of these stepa the re sulting frequency will be unstable as it jumps up and down between these two steps The knob must be set at a point near p HE 11 del C5 me e a L Place at or B and disconnect VCO 1 signal see section 5 during VCO 9 adjustment CUTOFF FREQ where VCF output frequency locks positively on one frequency or the other Test Point TP 5 on OP 104 1 While depressing Fl and F2 keys alter nately adjust P 11 on OP 105 to display two figures of 2 1 period Reset KEY FOLLOW at O 2 Adjust 12 on OP 15 for 880Hz by displaying Lissajous figure etc 3 Oheok F1 F2 for deviations in stop 1 23 F MHS 2 JAN 31 198 t uyt Test Point 3 0 104 1 While modulating the VCA with BEND MOD lever adjust P 14 on OP 105 to minimize click sound Test Point 3 on OP 104 l While depressing a key adjust P 10 on OP 105 so Trimmerpot that VCF just begings oscillation 151211 10 Approx 800mVpp sine with RESONANCE set at 8 9 VCF m BALANCE d spp 4 Acer na DELAY BEND Test Point TP 5 on OP 104 1 While depressing down C2 key adjust P 15 on OP 105 for 1 2Vpp aD id VCO MO
36. itial value in 4 sec after C2 key is released The amplitude decreases as ita frequency lowering Increase scope vertical sensitivity accordingly 16 VCA ENVELOPE ATTACK Test Point 11 OP 106 Grounding Point 6 5 104 4 32 24 AT gt a ia Test Point TP 11 OP 106 Grounding Point G 3 on UP 104 f bf control voltage key release _ MRS 2 JAN 31 1980 20 VCA ENVELOPE DECAY E STRING VOLCE Test Point 11 106 Grounding Point 0 3 en OP 104 1 While pushing BEND MOD lever extremely left adjust P 17 on OP 106 so that s und ratio of STRING and VOLCE becomes 1 1 1 in amplitude N Test Point TP 11 on OP 106 Grounding Point 0 3 on 104 1 Adjust P 24 on 106 so that amplitude decreases to 1 10 in 5 after pressing C2 key 23 NOISE LEVEL 21 VCA ENVELOPE RELEASE Test Point 9 OP 106 Grounding Point 0 3 on OP 104 1 Adjust P 16 on 106 for 5 Test Point 11 en OP 106 Grounding Point 0 3 on 104 1 Adjust P 25 on OP 106 so that amplitude decreases to 1 10 in 5 sec after releasing key release JAN 31 1980 PARTS LIST 061 242E Chassis case no 242E 072 265D Panel top no 265D 072 2688
37. n all other DB1 DB7 They are out on the data bus and latched on IC7 108 7418175 by the pulses from pin ALE Address Latch Enable to be out put onto DO D6 of TSET Next 8048 012 reads the Port 2 P20 P27 If it finds here that the P20 alone L while all otheres on H then it can know of that the 8 1 is on The above process is repeated to go over all of DBO to DB7 but four of them are connected to switches MEMORY WRITE Switch 881 18 so wired that it is only enabled when Compu Memory se lection switch is ON with the PROTECTION Switch SW21 being depressed at the same time see circuit diagram CONTROL BOARD F DESCRIPTION Reading of CONTROL PANEL The PROGRAMMABLE SECTION The 808 012 reads the patching on the Control Panel and caverts them into digital data of 16 bytes lbyte 8 bits Of th Control Panel the section named PROGRAMMABLE consits of 16 pots and 14 switches these 16 pots produe 16 different kinds of analog voltage varying betwea OV to 5V The 14 SWs on the other hand produe binary digital data of H or L given by 5V o 0V respectively The 16 analog voltages that come n parallel to each other are re arranged thru the analog multiplexer MPX 105 106 4051 to be put on a ingle line in time sequence Theseoutputs of the MPX go into the A D con verte will be described later to become 6 bitdata of 16 kinds The 1 binary data of the switches are also re arraned into 2 g
38. nificant bits 109 1010 serve as an inverter making the input to follow negative logic The output is 57 maximum therefore when it receives the input LLLLLLXX or OV minimum when HHHHHHXX RISE XX are for those least significant bits that are A D Converter Comparator Output made nil JAN 31 1980 Numbers 1 6 below in this section refer to those at top in figure right The 8048 012 tries at first putting DB7 to L thus making the digital data at first to LHHHHHXX tentatively These are latched 15175 by the pulse from ALE pin then out onto the D A converter On the one hand 8048 012 reads the output level of the comparator IC15 311 through pin It makes comparison between these two of the A D input and of D A converted output to LHHHHHXX 2 5V If the A D input is to be as shown in figure amp straight line a little over 2 5V the comparator finds that the D A converted output LHHHHHXX 2 5V is less than that of A D input It is to instruct 8048 to decide that the L pre viously put on tentative base can be firm 80 that L is to remain on DB7 hereafter Now 8048 turns to DB6 in putting here again L tentatively to output LLHHHHXX With this data the D A output becomes high er than the A D input as in step 2 on figure It makes the output of the com parator 511 turn to H That means that 8048 has now to decide that DB6 in L is too large so it must be reset back to H
39. ory Write timing signal output DB Data latch pulse output 48 the is 8 bit parallel computer fabricated single Wc 5V silicon chip Tne 8048 contains amp o TI 1K x 8 ROM program memory 27 I O P27 lines an 8 bit timer counter and O 1720 clock circuits 22 Used the Compu Phonic Synthe o pln Sizers are pPD8048 012 and uPD 116 8048 011 JP 4 only versions in o which programs and data dedicated 31 o PH P D8048C to the Compu Phonics are stored S Pi in the program memories o PH Voo 5V O PROG o 123 o P22 120 JAN 1980 MRS 2 Control Board F CO 9 Control Control Board C 111 PCB 328 Control Board 110 PIB 329 Control Board A 109 PCB 442 1 3 9 1 HI A P 5 ly B ower Supply Board 1 91 1 91109 1 0 100V PS 52 PCB 27 pont ec 117 PS 93 PCB 327 x an A32 Mother Beard 104 Module Board 105 5015 PCB 364 Module Control Board 26 es 4 2 L OP 106 PCB 235 Y lax sc x E kev Board CV 3 PCB 440 INTERCONNECTION DIAGRAM 4 7 BINARY COUNTER CLOCK TC4024P CLEAR TRUTH TABLE BUTPUPT BTATR Advance to Next State Q5 Q4
40. ranthesises with numbers show original CV 3A circuit arrange CV HOLD 23k 30 2 KEY TRIG tps ak 9 Qt 819 3122 8 I 150 de uy 16 55 1c 3 400 4 eonen 21 9 b ais 100k 10k 74 3 Circuit B o TATE Board One of the diodes keeps 102 outpit 6 higher in the case figure im mediately right or lower than IN and C10 charging discharging rate is speeded up along curve B Once voltage across C10 reaches te CV IN feedback resistor 3 3K wil KCV BOARD 61 38 152 0038 052 4408 8 850730 and higher 0825 4408 iS 0 T iR MALA Denm 7 LC Ens iu NC E RIT BELLO oe rome 5 t E ay pen ER 5 Ki 131 4 1 it a o 5 bu M Wu u 5 S aye ED ie lig m m IMPROVEENTS on CV 3 1 PORTAMENTO with derial number 850370 CV 3B With Oirouit in th figure right 0 charges close to CV IN relailvely fast but will not charge up to the exact CV N for a while theoretically indefi P SEER QUOD GEE GEESE gt GEE XD oS EN 2244 4444 nitely CV 3A 152 003A PCB 052 440 S N
41. re also included are the Noise Generator and V GEN LFO Delay Circuit toff frequency of HPF lse width modulation of VCO JAN 31 1980 rd rd rn c dada FH 43032 5 48 c5 r4 cb 48 o amp 5 5 5 gt 02 gt 5 ua d ete 3 5 PR 14 Switches 16 Sliders Lo Lo NOISE x Enable pulse 105 104 pin 6 MPX output 105 pin 3 4 NC output IC4 pin 3 NC eM set at except VCF ATTACK at 3 v P All sliders on the PROGRAMMABLE are MAX N MPX output IC5 IC6 pin 3 CP Io ea 106 24 1 MPX IC5 Enable pulse pin 6 D A Converter output IC14 pin 1 1 41311 ea 8 02 02 E RROA 5 5 SEESSSSSSRE RB SEE gt CIRCUIT DESCRIPTION MOTHER BOARD TIMING DIAGRAM in MANUAL MODE SLIDER SWITCH READ HOLD A D amp D A CONVERSIONS MPX and DMPX Figure blow is part of CP9 11 l2 17 and 15 at the left showing functions and timags of A D D A conversions and the Switch reading
42. roups of 7 kinds total 14 with each roup entering each respective MPX IC3 IC4 wherethey are made to 2 bit data and be output fron here in time sequence as above These 6 bit 2 bit data are combined to become an 8 bitdata That is to say that the patching firstmade on the Control Panel are become to be repreented by all digital data of 16 bytes in all refer to Memory Map on page 13 JAN 51 1960 3 bits Control 9 10 11 Multiplexer IC5 1C6 4051 can be regarded as the same to rotary switch provided with one more switch on itself as shown above Port 1 of 8048 outputs both the Address signal Control A B C Pins 9 10 11 which also serves as switch for 4051 itself for INPUT OUTPUT Address data and Chip Enable Signal INH Pin 6 There are 4 of 4051 Pins 9 10 11 of all four are connected through the same lines D A and A D Conversion l D A Converter OUTPUT The D A Converter used on the Mother Board is the one called R 2R type The converter here is only making use of higher significant 6 bits among those of 8 bits given here leaving the least significant 2 bits unused 2 A D Converter The A D Converter on the Mother Board is referred to as Successive Approximation Type Converter which Analog make use of the D A converter and a comparator To proceed on with conversion 8048 012 starts deciding the data at first for the most significant bit then down to those lesser sig
43. t writes the data held in step 2 to RAM selecting the address over there which is corresponding to the switch position on the COMPU MEMORY 588 eese ALE 5048 012 11 P20 P27 SHEER Be signals AERE signals 4 bits 148 91 94 Memory 1 Address ue DB Data Latch Timing 7 The 8048 divides the 8 bit data data in step 2 or data retrieved in step 5 into two formats 2 bit switch data and 6 bit slider data The 6 bit data then proceeds to D A conversion Those two signals of analog converted voltage and of switches are fed to the Module Boards 8 The 8048 checks to see whether it completed all 16 cycles to read out all data divided into 16 at the previous stage If all are completed it goes back to step 1 If not to 2 Switch Reading The 8048 012 scans the matrix made of the diodes and Switches on the Control Board F to find out which switch is depressed among those of WRITE through MEMORY PROTECT 1 Diode Switch Matrix On the Control Board F Switches each accompanying diode are grouped into 4 blocks consisting of 2 to 8 switches These blocks are then connected through the data bus to DBO DB3 DB4 DB6 on 8048 012 The blocks are also routed through to the pins of 20 27 on Port 2 of 8048 012 They are then making amp matrix refer to the Circuit Diagram Control Board F 2 To Scan the Switches The 8048 012 outputs L onto DBO alone and o
44. tate This is also connected to 8048 011 through the com mon line 8048 011 JP 4 only MODULE BOARDS r4 power on power off 1K 10K 1 50 Reset Circuit Included here are VCO VCF VCA and 2 ENV GENERATORS 1 VCO and its Peripherals ICla pin 1 2 and 3 makes the vibrato voltage VCO CONT and keyboard key voltage KCV KCV 1014 1 mixed and sends them out onto MIX the antilog transistor IC2 VCO which outputs antilog current from pin 9 This antilog current is then compared at the Comparator IC5b pin 5 6 7 with the current flowing in from pin 6 of IC4 thru R118 The output of the comparator IC5b is made to control the VCO generator oscillation 1 17711 frequency produced from 164 VCO OUT Gate IC Here however the 20103 has to make the oscilla tion in such frequency that it always keeps the differ ence at zero in values be Divide ANNO LLEI 1 16 tween the current Ig from 1i IC2 V Iexp i T constant J eee f I feedback loop 1 2 e Rectangular out 1 8 i QO a pin 6 of 104 and the 1106 111111 FV converter ak 2 current I exp from the anti T constant log IC2 The VCO outputs are in the pulse form of the constant width converted by the one shot multivibrator 103 555 It is therefore necessary to double the number of puls
45. th vcF R and 016 QD QD UM As es pL 4 PD wes 200 L E C 6 bit Data 94 a dA J 1 or 2 bit In replacing the Mother board check both the exi and the new replacement board for existance or ab If different see pagej9 modificat rrr f 8 Tuaana annm A ENN SAN ee LI Pm is t H J b p e Le F 4 E EEEE S f a 1 1 1 1 1 1 1 1 s E 4 a Ri 7 b on 13 27 E 9 r fe E M gt HE ova a 4 a amwe gt m 4 pwd 2 BEA i 9 Ns 3 p 55 4 4 5 Lu hy quom me 38 E 4 2 3 EE i 1 3 3 2 h E 2 4 4 59 4 d 2 m UTC RAT m WA CINQ 2 2 SLIDER VCO MOD 21 VCF MOD 22 ENV A 19 VCF ENV D 18 VCE ENV R 15 VCA ENV 17 VCA D 16 VCA ENV R le to immediate right and figures 28 VCF ENV MOD er to test points shown in the PCB iplies ary within the range of OV to 45V being moved LL be amp logical O 1ow or 1 high
46. up to 850729 085 340V PORTAMENTO TIME MRS 2 Improvements on CV 3 cont d 2 Shifting TRIG GEN only This relieves the following When keys on MRS 2 are _ played in legato with the CV and GATE IN OUT jacks being connected to a CSQ 100 tones corresponding to the subsequent keys can fade away along with the first key a envelope remarka ble example is Preset PIANO This is because Gate retrigger pulse 4 being blocked with CSQ 100 circuits does not exist at GATE IN failling to re set envelope generator for in dividual keying that follows to the first keying in sequence After modification MRS 2 has no de trimental effects on sequencers other than CSQ 100 The modification was conducted on MRS 2 with serial number 840630 besides produots bearing the following numbers have been modified before shipment J cv ou ITRIG GEN KEY GATE care pr SYNTH 1 CV IN MODULE di 4 A GATE IN OV 3A original KEY ov KEY GATE SYNTH HPORTAMENTO CV IN MODULE TRIG GEN 4 M variations modification PCB R11 shifted from 830568 830599 810260 810279 8305 33 8305 34 830547 830548 830552 830554 foil scraped off 830600 830617 830528 830529 830540 830545 830556 830557 830619 830621 052 440A MRS 2 JAN 31 1980 MODULE CONTROL OP

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