2011 - BTS SE Sembat
Contents
1. nsa BeuuoJe 3 ebessydiue ap ja abeAoyau ap sapuewwoy n uupiqin np aifep L ap JSULOHILO euu u3S GL 1 6Schema fonctionnel du second degr FP1 programmable s lective Fs1 4 Fs1 5 Amplification a gain O X E al LN Amplification V3 Redressement synchrone Fs1 6 V4 Contr le de phase Fst 7 Z G n ration d un signal 9 Emission IR de r f rence Fs1 3 psi 1 Fs1 2 74 Contr le du Compensation courant Integration Fs1 8 Amplification continue a gain programmable Fei O gt V6 gain DC mission IR Remarque les fonctions secondaires Fs1 5 Fs1 9 ne seront pas tudi es e Sortie FO Fs1 1 G n ration d un signal de r f rence signal binaire de fr quence FO Fs1 2 a d finir Fs1 3 Emission IR voir BAN19 La compensation contr le le courant de la DEL mettrice D1 donc l intensit du flux lumineux mis en commandant le transistor T4 en r gime lin aire partir de la mesure du flux lumineux traversant la cuve de mesure et de l cart entre la valeur mesur e et une valeur de consigne Par ailleurs le flux lumineux mis est hach par le transistor T5 partir du signal de commande de d coupage Z Enfin le signal Zivenat du microcontr leur P2 5 permet de limiter le courant dans la DEL mettrice pendant la phase de d marrage de la compensation le transistor T3 tant alors satur Entr es Z S2. 5 Si O SCH O LU LLI Y D E W 7 gt LU 0 m Session 2011 Documents reponse 11SEE4EL1 Q9 Ca Contr le du courant G n ration d un signal Flux IR de r f rence Emission IR Fs1 3 Fei Q10 Q11 Abr viations B Bloqu P Passant A Allum e E Eteinte Modele Modele equivalent equivalent Etat de la DEL IR DE1 Q17 Mod le quivalent BTS Syst mes lectroniques preuve U41 lectronique Page BR2 sur 6 7 Session 2011 Q20 Remarque le sigle horl repr sente Horloge d but P1 5 S lection du bo tier data 1 Impulsion d horloge Front descendant la valeur vaut elle 10K horl Fin memorisation BTS Syst mes Electroniques Session 2011 i I Epreuve U41 Electronique Page BR3 sur 6 een Q23 AC SWEEP ANALYSIS Q27 V2 mV 160 160 e ep geg ee en A o pe e em ee e em ee pp e e ege oe e em e ae s em em e e m eg o oe e ee e e em m e em a e aam ee ee eg ease ee pe eege esoe WN ll wn wm m m mae ce wre w zen tr mm m m m m m m m ir m mm mm m rm me Q28 2 weem L Rep re schema Reference Type Capacit en octets BTS Syst mes lectroniques Session 2011 e i f Epreuve U41 Electronique Page BR4 sur 6 Q30 P1 0 HORL H wen a e e e a o o o a a e e ew e e e e ss e a g
3. CD4504BT July 1999 Features QML Class T Per MIL PRF 38535 Radiation Performance Gamma Dose y 1 x 10 RAD Si SEP Effective LET gt 75 MEV gm cm independence of Power Supply Sequence Considerations Veco Can Exceed Vop Input Signals can Exceed Both Voc and Von Up and Down Level Shifting Capability Shiftabie Input Threshold for Either CMOS or TTL Compatibility 100 Tested for Quiescent Current at 20V 5V 10V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics Pinouts CD4504BT SBDIP CDIP2 T16 TOP VIEW CD45048T FLATPACK CDFP4 16 TOP VIEW Vee 1e Von Agut 2 FOUT AIN 3 Fin Bout 4 SELECT Bin 5 Eout Court 6 En Cin 7 Dour Vss 8 Diy Philips Semiconductors Product specification Schottky barrier diodes BYV10 series DESCRIPTION The BYV10 20 to BYV10 40 types are Schottky barrier diodes fabricated in planar technology and encapsulated in SOD81 hermetically sealed glass packages incorporating ImplotecTM technology FEATURES Low switching losses Fast recovery time Guard ring protected Hermetically sealed leaded glass package 1 implotec is a trademark of Philips APPLICATIONS Low power switched mode power supplies Rectifying e Polarity protection MANI IS Sa AA E Fig 1 Simplified outline SOD81 and symbol LIMITING VALUES In accordance with the Absoiute Maximum Rating System IEC 134 SYMBOL PARAMET
4. STATE READ x n O BTS Syst mes Electroniques Epreuve U41 Electronique Documentation Page BANS sur 20 10 0 SERIAL PORT The serial port on the S0C196KB has one synchronous and 3 asynchronous modes The asynchronous modes are full duplex meaning they can transmit and receive at the same time The receiver is double buffered so that the reception of a second byte can begin before the first byte has been read The transmitter on the 80CIS6KB is also double buffered allowing continuous transmis sions The port is functionally compatible with the seri al port on the MCS 51 family of microcontrollers al though the software controlling the ports is different Data to and from the serial port is transferred through SBUF RX and SBUF TX both located at O7H SBUF TX holds data ready for transmission and SBUF RX contains data received by the serial port SBUF TX and SBUF RX can be read and can be written in Window 15 Mode 0 the synchronous shift register mode is de signed to expand 1 0 over a serial fine Mode 1 is the standard 8 bit data asynchroncus mode used for normal serial communications Modes 2 and 3 are 9 bit data asynchronous modes typically used for interprocessor communications Mode 2 provides momtoring of a communication line for a 1 in the 9th bit position before causing an interrupt Mode 3 causes interrupts indepen dant of the Sth bit value 10 1 Serial Port Status and Control Contro
5. l I Bv F Se oT IT F SDV MMISICCE i A18 L 2 ISK SVL Session 2011 F k STE Cis 10 0 x e A al EPROM A A d AIL 5V Cil CIJ MR4aTda 4 GP i HESET d Bal 1 11SEE4EL1 BTS Syst mes Electroniques Epreuve U41 Electronique Documentation LEV CI EF Wa074B07 3 2 2 2 GP2 TE d Bes d ges DM saze Ua s3281 Ue S3281 Ue s3281 le L I 1 1 El m E 1 Ril g lt SV Page BAN20 sur 20 eg nya een at A RRR ATA aT EE ho A Ta
6. ralement pas ces normes et doivent donc tre trait es avant distribution Par ailleurs chaque eau poss de des caract ristiques propres Une analyse de l eau brute est indispensable afin d adapter le traitement la qualit de l eau En cas de pollution accidentelle il faut pouvoir arr ter le pompage de l eau brute afin de ne pas contaminer les r serves en eau potable Une station d alerte r pond ce besoin et constitue un syst me de surveillance automatique de la qualit de l eau L objet technique tudi est un turbidim tre Cet appareil mesure en continu la turbidit de l eau brute au sein de la station d alerte La turbidit est d finie comme l expression de la diffusion et de l absorption par opposition la transmission de la lumi re au travers d un chantillon d eau Elle est provoqu e par la pr sence de particules en suspension collo des algues microorganismes argile Le taux de lumi re diffus et absorb est proportionnel la concentration en particules dans la solution La turbidit est un indicateur relativement fiable de la puret d une S o solution et s exprime en Nephelometric Turbidity Units NTU E d TURBILIGH ee E Hans Cette mesure de la turbidit permet d optimiser la dur e de la filtration e de l eau brute Des seuils de turbidit ont t fix s pour modifier cette a dur e de filtration en cas de d passement BTS Syst mes Electroniques Session 2011 Epreuve U41
7. sp nbii uunu nop EE JSIABlO sed SUBISUODS ap sisies Lild SUOJy9U S uono l p 9948 ebnoieijui sed ansa PO irei pen pm mm wa w rw a cs a rf w ac war s ww a s SAHLAWICICNNL spanoj XNE U op Inas euwy anbibojoiq 2HANOB JSINSIN spinol xne ep aouesaid By 18199180 soinqieooipAy p I l I I I I l l l l l l l i I i I l l l l l l l J nasA euy I I I l l i I l l l I I I l i I l _J 21 2u1H10 090 JO d sounquesoipAy p eyyuenb ej ISINSSM nbegluouutup p eyjuenb ej JSINSSN bio nes ep supiqiny p Jounsey Sd yu ru 1leil 2p uone1s eun p JUOLUe US SANA un p nea sesAjeuy 9HI9 E P uone s EI SP 1SV3 uutue BeId E U jj uuo uoy s jeuy L 1avsadstll dns 9y aBed nbliuono l3d LYN saneidy KEE sanbiu01 98 7 sewajshs Sig Gd seubisuoy a euuo oalipiq INSJeuJplO 31195 UOISSILSUEIL saule y s nsa SOLE SIN2 8 pd4 SHPIqIN A ej ap auueAow oka JINS 2A E ap nep Ina1siBaJua un sejjanes SIDA UOISSIUISUBJ SKURA GUN Viste SUONBUUOJU PHP IQs 9dy SUOHE WOU 9 pIqini AOS S9J ansin sap oPeuoily p ap abeideo suoneunojuj 0 97 NG OY sulg uopesueduioy 10 ed4 abeuuojeja sinajer Beuuo e 3 saubisuoy gI UOISSIWIG UOUSSISIDIU U OIIO ana ed ET SUEP uolliueuo SP ju euu uuonipuoo U IDIUuo9 lt
8. 5 V a Sofiware controlled clock calibration for nigh accuracy applications a Self contained battery and crystal in the CAPHAT DIP package W Packaging includes a 23 leac SOIC and SNAPHAT top lo be ordered separately m SOIC package provides direct connection for a sraphat top which contains ihe battery and crystal m Pin and function compatible wh 091643 and JEDEC standard 8 K x 8 SRAMs B RoHS compliant Lead free second level interconneci SHAPHAT SH battery orystal BTS Syst mes Electroniques Epreuve U41 Electronique Documentation Page BAN sur 20 11SEER4EL1 August 1986 AY national Semiconductor NM93C06 C46 C56 C66 256 1024 2048 4096 Bit Serial EEPROM MICROWIRE Bus interface General Description Features The NM93C06 C46 C56 C66 devices are 256 1024 8 Device status during programming mode 2048 4036 bits respectively of CMOS non volatile electri Typical active current of 200 uA Typical standby cally erasable memory divided into 16 64 128 256 16 bit current of 10 pA registers They are fabricated using National Semiconduc No erase required before write tar s floating gate CMOS process for high reliability and low e Reliable CMOS floating gate technology engl Ca dee See are SSC D s 4 5V to 5 5V operation in all modes SC en packages for small space considera a MICROWIRE compatible serial 1 0 Self ti i nts The EEPROM Interfacing is MICROWIRE compatible for ol ed programming cy
9. 8 LD PDIP TOP VIEW Block Diagram X9C102 X9CT03 X9C104 X9C503 Je 20 2009 Features Solid State Potentiometer Three Wire Serial Interface 100 Wiper Tap Points Wiper Position Stored in Non volatile Memory and Recalled on Power up 99 Resistive Elements Temperature Compensated End to End Resistance 20 Terminal Voltages 5Y Low Power CMOS Vec DM Active Current 3mA max Standby Currant 7S0uA max High Reliability Endurance 100 000 Data Changes per Bit Register Data Retention 100 years X9C102 k X9C103 10k X9C503 50k X9C104 100k f3 Packages 8 Ld SOIC 8 Ld PDIP Pb Free Available ROHS Compiiant HU L s e a lt a sg m w R w ss mes U D SI e A INC UPIDOWN ED HVH ae COUNTER Veco SUPPLY VOLTAGE UP DOWN U D INCREMENT INC DEVICE cs SELECT Vss GROUND STORE AND RECALL GENERAL Vec CONTROL GND Session 2011 NON VOLATILE MEMORY CIRCUITRY 1 E x HUNORED TRANSFER T RESISTOR DECODER GATES 1 ARRAY a 4 DETAILED X3C102 X9C103 X9C104 X9C503 AC Timing Diagram MI NOTE NOTE MEREFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE Vw OUTPUT DUE TO A CHANGE IN THE WIPER POSITION Pin Descriptions Ry NH and R V The high VrH RH and low V R terminals of the ISLX9C102 X90103 X9C104 X9C503 are equival
10. Electronique Page A1 sur 7 11SEE4EL1 Analyse Fonctionnelle 1 2Principe et proc d de la mesure Principe de mesure La mesure de la turbidit peut tre effectu e de deux mani res e soit par la mesure de la lumi re qui traverse le liquide en ligne droite C est la turbidim trie Cette m thode est appliqu e seulement aux liquides dont la coloration ne change pas e soit par la mesure de la lumi re diffus e par les particules en suspension dans un axe diff rent de celui de la source de lumi re En effet les particules en suspension et elles seules r fl chissent la lumi re dans toutes les directions Ce principe de mesure est appel N ph lom trie du grec NEPHELE lt nuage La coloration du liquide n entra ne aucune diffusion de lumi re mais seulement une att nuation de celle ci Il faut alors r guler l intensit de la lumi re mise en fonction de la coloration Lorsque la coloration est importante il faut donc augmenter l intensit de la lumi re C est ce second principe qui est utilis dans le turbidim tre Turbilight Proc d de mesure Un faisceau infrarouge de fr quence FO issu d une DEL va traverser une cuve de mesure qui contient l chantillon L intensit de la lumi re diffus e est mesur e a 90 degr s du rayon incident par un r cepteur puis amplifi e lectroniquement partir de l intensit diffus e par l chantillon et d une r f rence de turbidit connue t
11. Package Designator North America FAMILY DATA lpp LIMITS category MS Dee Family Specifications Session 2011 11SEE4EL1 Timing component limitations The oscillator frequency is mainly determined by RC provided R lt lt R2 and R2C2 lt lt RC The function of R2 is to minimize ihe influence of the forward voltage across the input protection diodes on the frequency The stray capacitance C2 shouid be kept as small as possibie In consideration of accuracy C must be larger than the inherent stray capacitance R must be larger than the LOCMOS ON resistance in series with t which typically is 5009 at Voo 5 V 309 at von 10 V and 2002 at Vos 15 V The recommended values far these components to maintain agreement with ihe typical oscilation jermuia are C z 100 pF up to any practical value 10 KG z R 1 MQ Typical crystal oscillator circuit In Fig 5 R2 is the power liming resister For starting and maintaining osciilafion a minimum transconductance is necessary BTS Syst mes Electroniques Epreuve U41 Electronique 1224430 MR from logic HEF 40608 mhz C2 100pF L 72844313 Fig 5 External component connection for crystal oscillator Page DANZ sur 20 Documentation S D LY 7 Data Sheet ce CMOS Hex Voltage Level Shifter for TTL to CMOS or CMOS to CMOS Operation intersil s Satellite Applications Flow SAF devices are fully tested and guaranteed to 100kR
12. READY BUSY status of the chip if CS is brought high after the tcs interval Write AH WRALL The WRALL instruction will simultaneously program all reg isters with the data pattern specified in the instruction As in the WRITE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after the tes interval Write Disable WDS To protect against accidental data disturb the WDS instruc tion disables ali programming modes and should follow all programming operations Execution of a READ instruction is independent of both the WEN and WDS instructions NOTE The NSC CMOS EEPROMs do sol require an ERASE or ERASE ALL operation prior lo the WRITE and WRITE ALL instructions The ERASE and ERASE ALL instructions are inciuded to maintain compaubtiity wilh earlier lechnology EEPROMs instruction Set for the NM93C06 and NM93C46 instruction SB Op Code Comments READ A5 A0 Hess Reads data stored in memory at specified address WEN i O EE ee 11XXXX P ss Enable all programming modes ERASE A5 A0 SE Erase selected register WRITE q oi As A D15 DO Writes selected register ERAL OA TOXAXX w a dl Erases ail registers WRALL q om oixxxx D15 D0 Writes all registers WDS DE OOXXXX BRE Disables all programming modes sch f sech f k Note Address bis AS and Ad become Don t Care for ihe NVIS3C05 Session 2011 11SEE4EL1 WRITE TRI STATE DO TV eech TRI
13. _1 50mA i i Spectral Haltwidth P 50mA Halt Intensity A ngle i ASUMA _ L 50m Apct5mA Cut off Frequency 3db from TMH 2 i Response Time leznm tr tf Pulse Forward Voltage las 500mA_ i Veu i Max BTS Syst mes Electroniques Epreuve U41 Electronique Page BAND sur 20 REGER MICROCHIP 2 C2 256K 32K x 8 CMOS EPROM FEATURES gt High speed performence 90 ns access time available CMOS Technology for iow power consumption 20 mA Active current 106 nA Standby current Factory programming available e Autc insertion compatble plastic packages Auto iD aids automated programming Separate chip enable and output enable controls High speed express programming aigorithm Organized 32K x 8 JEDEC standard pinouts 26 pin Dual in iine package 32 pin PLCC Package 28 pin SOIC package 28 pin Thin Smal Qutine Package TSOP 28 pin Very Small Outline Package VSOP Tape and reel Data Retention gt 200 years Available for the following temperature ranges Corrmercal CC toro industrial 40 C to 85 C Automotive 40 C to 125 C DESCRIPTION The Microchip Technology Inc 270255 is a CMOS 255K bit elecirically Programmable Read Only Memory EPROM The device is organized as 32K words by 5 bits 82K bytes Accessing individual bytes from an address transition or from power up chip enable pin gaing low is accomplished in less than S
14. dans la centrale de contr le si la mesure de la turbidit de l eau brute d passe les seuils D crire bri vement le processus de mesure utilis dans le turbidim tre Turbilight Expliquer comment une forte coloration de l eau boue petite pollution ne perturbe pas la fiabilit de la mesure indiquer la gamme de mesure maximale et la pr cision du turbidim tre Turbilight PARTIE B Captage de la turbidit FP1 mission IR 1 Emission infrarouge FS1 3 Voir sch ma structurel BAN19 On donne ci contre les chronogrammes des signaux Fo rep re 1 et Z rep re 2 Q7 Q8 Q9 Q10 Q11 Session 2011 11SEE4EL1 Tek Arr t F nm lt lt G l E on rs L r L Ch2 Fr quence 5kH ia D Poor EECH 4 K di he 1 25 A partir des chronogrammes ci contre et de eege ities la documentation technique BAN2 calculer perece Pe u EUR la fr quence du quartz du circuit CI7 Indiquer le r le de la fonction Fs1 2 Justifier sa pr sence od m Entourer sur le sch ma structurel doc r ponse BR1 la structure qui remplie ce r le EC a SAP Jes RE 1 I d l U H a me m lt lt et H 1 3 E a meme Kb TL 5 00 V RR 5 00 Y TIM 200us A Chi s 2 50 v 16 Jun 2010 a 000005 22 23 17 Nommer la fonction Fs1 2 dans le sch ma fonctionnel doc r ponse BR2 D terminer les tats des transistors T3 et T5
15. due to temperature drift etc The state of U D may be changed while CS remains LOW This allows the host system to enable the device and then Mode Selection Wiper Down AAA LI VVHV een Store Wiper Position Standby Current No Store Return to Standby Wiper Up not recommended Wiper Down not recommended l Symbol Table WAVEFORM INPUTS OUTPUTS T Must be Will be steady steady May change Will change from Low to from Low to High High May change Wil change from High to from High to Low Low Don t Care Changing L Changes State Not Allowed Known N A Center Line is High Impedance Basic Configurations of Electronic Potentiometers Session 2011 DNK5306X Fhrough hole IRED 03 Hish Speed High Total Output Power Type Absolute Maximum Ratings Ta 25 C _ Power Dissipation i Forward Current i tr i 100 mA Pulse Forward C urrent Es i lerm i 1 009 mA X eeh a eee Derating j 4 le i 1 33 mA ae 7 r SE Ap ed Seah hy A d La au Naa ege tate ate teas he d sp egener die awe o ee is Ta 23 C or higher Abry 133 i mA Reverse Voltage Ve 5 Y Operating Temperature I Tor Pp 38 G Storage Temperature Tots i 30 100 A O e 1 TS Measurement GE Pulse Width 0 vine Duty 1 100 MIN 13 Forward Yoltage SOMA Reverse Current Va 5V E Radiant Intensity I 50mA Total Output Power k n x Peak Wavelength
16. en fonction des niveaux de tensions pr sents en Z et Z1 dans le document r ponse BR2 Compl ter le tableau document r ponse BR2 e en dessinant les mod les quivalents des deux transistors e en donnant l tat de la DEL IR DE1 lorsque T4 conduit BTS Syst mes lectroniques preuve U41 lectronique Page B1 sur 5 DEER Tek Ex c D clench Q12 A partir du chronogramme ci contre issu du point test Pt1 image du courant dans la DEL DET avec Ice la tension au point Z1 gale 12V calculer la ocios ai valeur du courant maximal dans la DEL D I re Indiquer si cette valeur est compatible avec les M EENEG caract ristiques de la DEL documentation tt ee ee technique BANG Justifier votre r ponse I 2 amp TE oe Q13 Pr ciser le r le de la structure compos e de ti E E o sss R62 R63 C57 C55 Justifier sa pr sence a EE Q14 D terminer la valeur moyenne de la tension sur L La E BS O O l entr e P0 2 du microcontr leur EE es ss Ds se yg Fe wg ey lesten fex 2 Compensation name La compensation FP7 contr le le courant dans la DEL mettrice D I donc l intensit du flux lumineux traversant le liquide mesurer en commandant le transistor T4 en r gime lin aire a partir de la mesure du flux lumineux transmis travers la cuve de mesure 180 et de l cart de la valeur mesur e par rapport une valeur de consigne La mesure du flux lumineux est assur e par la photodiode de co
17. given a convenience of single power supply The typical charge pump noise of 20mV at 850kHz should be taken in consideration when designing an application circuit Page BANS sur 20 X9C102 X9C103 X9C 104 X9C503 Instructions and Programming The INC U D and CS inputs control the movement of the wiper along the resistor array With CS set LOW the device is selected and enabled to respond to the U D and INC inputs HIGH to LOW transitions on INC will increment or decrement depending on the state of the U D input a 7 bit counter The output of this counter is decoded to select one of one hundred wiper positions along the resistive array The value of the counter is stored in non volatile memory whenever CS transitions HiGH while the INC input is also HIGH The system may select the X9Cxxx move the wiper and deselect the device without having to store the latest wiper position in non volatile memory After the wiper movement is performed as previously described and once the new position is reached the system must keep INC LOW while taking CS HIGH The new wiper position will be maintained until changed by the system or until a power down up cycle recalled the previously stored data This procedure allows the system to always power up to a pre set value stored in non volatile memory then during system operation minor adjustments could be made The adjustments might be based on user preference i e system parameter changes
18. in this mode It consists of a start bit 0 9 data bits LSB first and a stop bit ii When transmit ting the Sth bit can be set to a one by setting the TBS bit in the control register before writing to SBUF TX The TBS bit is cleared on every transmission so it must be set prior to writing to SBUF EX During recep tion the serial port interrupt and the Receive Interrupt will not occur unless the 9th bit being received IS set This provides an easy way to have selective reception on a data ink Parity cannot be enabied in this mode MODE 3 Mode 3 is the asynchronous Sth bit mode The data frame for this mode is identical to that of Mode 2 The transmission differences between Mode 3 and Mode 2 are that parity can be enabled PEN 1 and cause the Oth data bit to take the even parity value The TBS bit can still be used if parity is not enabled PEN 0 When in Made 3 a reception always causes an inter rupt regardless of the state of the 9th bit The 9th bit is stored if PEN 0 and can be read in bit RBS if PEN then RB8 becomes the Receive Panty Error RPE flag BTS Syst mes Electroniques Epreuve U41 Electronique Page BAN13 sur 20 EE E DESCRIPTION MB3773 generates the reset signal to protect an arbitrary system when the power supply voltage momentarily is intercepted or decreased It is IC for the power supply voltage watch and Power on reset is generated at the normal return of the power supply M
19. minimale et maximale Q24 A partir des r sultats de simulation indiquer les principales caract ristiques amplification maximale fr quence centrale bande passante de la fonction FS1 4 Sur l appareil en fonctionnement plage 0 10 NTU et pour une turbidit T 8 NTU on a relev les chronogrammes ci contre Q25 En d duire la valeur de lamplification V zae o a CAN N E V of AALE L TEE Q26 Calculer la valeur de r glage de RX e A Get o E correspondant a cette amplification V1 ee A En ein rep re 1 E U V2 repere 2 Aerch ons E i Ci Q27 A partir de la r ponse en fr quence ci contre de la fonction FS1 5 et du chronogramme donn sur le document r ponse BR4 tracer sur le document r ponse BR4 le chronogramme de V3 f t correspondant cette valeur de r glage FREQUENCY RESPONSE D D U 1 t D i Session 2011 BTS Syst mes Electroniques Epreuve U41 Electronique Page B3 sur 5 ee PARTIE C Etude de la fonction FP2 Cette fonction est remplie par un microcontr leur 16 bits de type 80C196KB CI5 associ aux composants C8 CI2 C13 Cl4 CI6 C110 Sch ma structurel page BAN20 1 M morisation et gestion du temps La m morisation est assur e par plusieurs circuits e la m morisation du programme et des constantes par CI8 de r f rence 27C256 e Ja m morisation des donn es et des variables par CI3 de r f rence MK48T08 e la m
20. morisation des donn es de configuration de l appareil par CI10 de r f rence 93C06 La gestion du temps par l horloge temps r el interne au circuit CI3 de r f rence MK48T08 Q28 Compl ter le document r ponse BR4 dans lequel vous pr ciserez pour chaque m moire son type et sa capacite en octets La documentation du composant pr sente rapidement le bus Microwire pages GANG et BAND Q29 La communication de cette m moire avec le microcontr leur se fait avec un bus Microwire citer deux autres types de bus utilis s pour les liaisons entres circuits int gr s A partir des chronogrammes donn s document r ponse BR5 r pondre aux questions suivantes Q30 Entourer et annoter sur les chronogrammes un Start bit SB un Op code une adresse et une donn e Q31 Donner le r le de la r sistance R10 Q32 On donne le contenu de la m moire document r ponse BRS lire sur le chronogramme concern la valeur m moris e puis l entourer dans le document r ponse Q33 On d sire effacer le contenu de l adresse 13 valeur d cimale tracer sur le document r ponse BRS les chronogrammes correspondants 2 Etude de la fonction FP5 L appareil peut tre raccord un ordinateur pour le traitement des donn es La liaison est de type s rie utilisant une boucle de courant Caract ristiques de la liaison e vitesse 9600bauds Du de start 8bits de donn es pas de parit 1 bit de stop e au repos signal de 20mA pa
21. 0 10 ms 1 5 Normalized 1 0 0 5 Ros on Drain to Source On Resistance VDS 25V 20us PULSE WIDTH R Vas 10V me 5 8 7 g 9 0 ep 40 20 O 20 40 60 80 100 120 140 160 189 Vgs Gate to Source Voltage V Ty Junction Temperature C Fig 3 Typical Transfer Characteristics Fig 4 Normalized On Resistance Vs Temperature BTS Syst mes Electroniques session 2011 Epreuve U41 Electronique Page BAN4 sur 20 EES TS ial 7 Data Sheet Digitally Controlled Potentiometer XDCP The X9C102 X9C 103 X9C 104 X9C503 are Intersils digilally controlled XDCP potentiometers The device consists of a resisior array wiper switches a control section and non volatile memory The wiper position is controlled by a three wire interface The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network Between each elemeni and at either end are tap points accessible to the wiper terminal The position of the wiper element is controlled by the CS U D and INC inputs The position of the wiper can be stored in non volatile memory and then be recalied upon a subsequent power up operation The device can be used as a three terminal potentiorneter or as a two terminal variable resistor in a wide variety of applications ranging frorn control to signal processing to parameter adjustment Pinout X9C102 X9C103 X9C104 X9C503 8 LD SOIC
22. 0 ns This very high speed device allows the mos sophisticaled micro processors 10 run at Tull speed without the need for WAIT states CMOS design and processing enables this part to be used in systems where reduced power consumption and seiiability are requirements A complete family of packages is offered to provide the most fexidility in appiications For surface mount appii cations PLCC SOIC VSOP or TSOP packaging is available Tape and reel packaging is aiso available for PLCGC or SOIC packages Session 2011 PACKAGE TYPES segura UN Si RU RRB B DI he si CUD OO ven k m ak sch un CS DIP SOIC Exa i d Ei H p G DUEL C BHRR 2 Q c GE EL Ta E 1000 x oF de an ch st M SIB OIR 3 lt Q C EO Q Q W DDODbhODDLDOLOODD BREQOP SE gedet Ge H RA A 8TO 8 d Gi j Oe x 4 M48108Y M48T18 5 V 64 Kbit 8 Kb x 8 TIMEKEEPER SRAM Features s Integrated ultra low power SRAM real time clock power fail contrat circuit and battery BYTEWIDE RAM like clock access m BCD coded year month day date hours minutes and secands m Typical clock accuracy of 1 minute a month at 25 C omer y PODIF2S PC g Automatic power iail chip deselect and write battarvorysiai protection EE a Write protect Veep Power fail deseleci voltage M48T08 Veg 475 to 5 5 V 4 5 V Vpgp 4 75 V M48T1S TOBY Veg 4 5 to 5 5 V 4 2 V lt Maer S 4
23. 34ES S y C12 O 22pF D CD4054 LO 4060 D L DESIGN TITLE EMISSION IR cO e Y SAEZ CREA HET EA AT EGRET VA AS EDESA FTE NIE ZRII DEE CEET EE e e EE SEN t AK2 ASS L d Riga CS RESET i Al 93773 3Kq d DO 0 IL ci Pa a Jour63v POLE PAL ay WE 5V na HS I Ges D2 ch 180 BYVI 2gA 2 HS D LG D i av 5Y C2 RES 1412 ISBNF Cis 80C196 13 12 j GU l avt CB T o SDV BVL Session 2011 11SEE4EL1 SV AEN 5V cla i 1712 RG de uN 22K i ET 2 0 a U U C ADA 1275 i I AR U DX 578 AGL 4 a O O LU 5 F A D Q inte cla gt SS S H L 36112 ho EPROM D_A AQ B 9 AAD on ZA 5V B A I FS Cil A Din a wet Ba Ain e Bl AS IBONF UV B2 ag 23 53 q A 54 S aln A C3 En Ou SR 44 sd ne A GONE IN 6 A U Y ul D a D bR az 2 HS A a AG V AD E E A L ASL AB T AS LO cia 2A d Gaz AB ha p AOL a MKAaTaa S 39 p 45Y Ro n b A 1 P AQUA A 5 pazo n C na BS cLKO 57 5V 2 7 ei j 2 HESET H ESE 53291 8MHZ 1 1 C4 BTS Syst mes Electroniques Epreuve U41 Electronique Documentation CI GP W87447 NL Page BAN20 sur 20 5V SY S v T GC I 3 ISHMFESV E Du I n2 I BYVI ZZA e 200195 R gem E 1 va Se baakt GE 58178 47QNF S A l B G 32 21 cia B 3 ADSGO 12 C 2 mAT S 186 NF Ce i Qi TI 2 aw BVL SMHZ cs
24. 83773 sends the microprocessor the reset signal when decreasing more than the voltage which the power supply of the system specified and the computer data is protected from an accidental deletion In addition the watchdog timer for the operation diagnosis of the system is built into and various microprocessor systems can provide the fail safe function lf MB3773 does not receive the clock pulse from the processor for an specified period MB3773 generates the reset signal E FEATURES Precision voltage detection Ve 4 2 V 2 5 Detection threshold voltage has hysteresis function Low voltage output for reset signal We 0 8 V Typ Precision reference voltage output Va 1 245 V 1 5 e With built in watchdog timer of edge trigger input External parts are few 1 piece in capacity The reset signal outputs the positive and negative both theories reason E PACKAGES ni KZ LE A DIP 8P M01 FPT 8P M01 SIP 8P M03 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields However itis advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit FUJITSU Session 2011 BTS Syst mes Electroniques Epreuve U41 Electronique 11SEF4EL1 amp PIN ASSIGNMENT TOP VIEW DIP 8P M01 FPT 8P NO1 t SIP 3P ND3 m ABSOLUTE MAXIMUM RATINGS Pa
25. AD total dose These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead time needs of large volume satellite manufacturers while maintaining a high level of reliability CD4504BT Hex Voltage Level Shifter consists of six circuits which shift input signals from the Vcc logic level to the Vop logic level To shift TTL signals to CMOS logic levels the SELECT input is at the Vec HIGH logic state When the SELECT input is at a LOW logic state each circuit translates signals from one CMOS level to another Specifications Specifications far Rad Hard QML devices are controlled by the Defense Supply Center in Columbus DSCC The SMD numbers listed below must be used when ordering Detailed Electrical Specifications for the CD4504BT are contained in SMD 5962 96665 A hot link is provided from our website for downloading www intersil com spacedefense newsafclasst asp intersi s Quality Management Plan QM Plan listing all Class T screening operations is also available on our website www intersil com quality manuals asp Ordering Information ORDERING PART NUMBER NUMBER CD4504B0TR 55 to 125 CD4504BKTR 55 to 125 NOTE Minimum order quantity for T is 150 units through distribution or 450 units direct S962R9666501TEC 5962R9666501TXC Vec Vop s Veco PIN 1 rrucmos Vss PIN 8 Session 2011 LEVEL OUT SHIFTER 2 4 6 10 12 15
26. BAN7 MKTO8 BAN7 93C06 BAN8 BAN9 80C196KB BAN10 a BAN13 MB3773 BAN14 BAN17 Turbilight RS232 BAN18 Sch ma structurel mission IR BAN19 Sch ma structurel UC BAN20 BTS Syst mes Electroniques Session 2011 f Epreuve U41 Electronique Page BAN1 sur 20 TISEE4EL Philips Semiconductors Product specification 14 stage ripple carry binary counter divider and oscillator DESCRIPTION The HEF4060B s a 14 stage rippie carry binary counterdivider and oscifiaior with thres osciliator terminais RS Rys and Cyg ten buffered cutputs O to O and O11 lo O43 and an overriding asynehrenous master reset input MIR The oscillator configuration allows design of either RC or crystal oscillator circuits The oscitlator may 7284432 Fig 2 Pinning diagram HEF4060B Mei be replaced by an external ciock signal at input RS The counter advances on the negafive going transition of RS HIGH level on MR reseis ihe counter Os lo Og and O4 to Oya LOW independent of other inpul conditions Schmitt trigger action in the clock input makes the circuit highty toleran to slower clock rise and fail times 72844371 MR master reset RS clack inpuVoscillater pin Rre ascillaior pin Cre external capacitor cannactian Og1o Oa counter outputs O to Gea HEFAGSOBP N 16 2ad DIL plastic SOT38 1 HEF4060BD F 16 ead DIL ceramic cardia SOT74 HEF4CSOBT D 18 lead SO plastic SOT109 1 j
27. BREVET DE TECHNICIEN S UPERIEUR SYSTEMES ELECTRONIQUES EPREUVE E4 Etude d un Systeme Technique Unite E4 1 ELECTRONIQUE Dur e 4 heures coefficient 4 Tout document interdit Calculatrice fonctionnement autonome autoris e Circulaire 99 186 du 16 11 99 Ce sujet comporte A Analyse fonctionnelle du syst me A1 A7 B Sujet Questionnaire B1 B5 Documents r ponse BR1 BRG Documentation BAN1 a BAN20 Etude d un Syst me Technique 11SEE4EL1 E 41 ELECTRONIQUE Session 2011 ANALYSE FONCTIONNELLE Pr sentation du syst me Station d alerte support de l tude 1 1Mise en situation Dans les pays industrialis s les probl mes de s curit constituent une pr occupation majeure Pour le distributeur d eau cette pr occupation se traduit par la n cessit de fournir a ses abonn s une eau en tout point conforme aux normes de potabilit en vigueur Par d finition une eau potable est une eau agr able boire et sans danger pour le consommateur La l gislation pr cise cette d finition par des normes de potabilit concernant e la teneur en organismes parasites ou pathog nes e la coloration e la turbidit lt 2NTU e la min ralisation lt 2g l e la teneur en m taux lourds plomb cuivre mangan se e la teneur en produits chimiques toxiques arsenic cyanures fluorures Les eaux auxquelles l on a recours pour lalimentation publique ne r pondent g n
28. Detection voltage are Va and Va a Tra reduction method b Standard usage Notes lt RESET is the only output that can be used e Standard Tex Tac and Ter value can be found using the following formulas Formulas Ter ms 100 x CT uF Two ms 100 x Cr uF l Ter ms 16 CT uF MB3773 Logic circuit e The above formulas become standard values in determining Ter Two and Tue Reset hold time is compared below between the reduction circuit and the standard circuit EXAMPLE 2 5V Supply Voltage Monitoring external fine tuning type C 0 1 uF SES Ter reduction circuit Standard circuit EE ma masma iD 1 6 ms 2 0 ms Notes e Vs detection voltage can be adjusted externally Based on selecting Ri and R values that are sufficiently lower than the resistance of the IC s internal voltage divider the detection voltage can be set according to the resistance ratio of R and F See the table below R kO R kQ BTS Syst mes Electroniques Session 2011 l Page BAN17 sur Epreuve U41 Electronique 20 RESTES 1 l TURBILIGHT ORDINATEUR RECEPTEUR DE COURANT EMETTEUR DE COURANT 7 R cepteur RX Ent Le 1 y 4 4 e t 501 d i t 1 i U A A D SD sos i Grd 20ers ax Gi Or R cepteur TX t TURAILIGHT ORDINATEUR EMETTEUR DE COURANT RECEPTEUR DE COURANT 8 R cepteur oe Zi Max a E L L CD AE WS SE Em
29. ER CONDITIONS UNIT Mast repetitive peak reverse voltage BYV 10 20 BYV 10 30 f BYV10 4D E 40 average forward current CECI E A storage temperature REE ee EE AAA E Note 1 Refer to SOD81 standard mounting conditions gt ELECTRICAL CHARACTERISTICS Tams 25 C unless otherwise specified SYMBOL PARAMETER CONDITIONS TYP MAX Ve forward voltage le 0 1 i 390 ie ea SR ROE Va VRRiimax note 1 Note Va 0 V f 1 MHz 1 Pulsed test tp 300 us 0 02 reverse current diode capacitance THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Note 1 Refer to SOD81 standard mounting conditions BTS Syst mes Electroniques Epreuve U41 Electronique Page BAN3 sur 20 11SEE4EL1 Documentation PD 9 1672A International TER Rectifier IRFZ34E HEXFET Power MOSFET e Advanced Process Technology Ultra Low On Resistance i Vpss 60V e Dynamic dv dt Rating e 175 C Operating Temperature e Fast Switching Eer e Ease of Paralleling Description ID 28A Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on resistance per silicon area This benefit combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for provides the designer with an extremely efficient device for use in a wide variety of ap
30. a tension d alimentation du microcontr leur et surveille le bon d roulement du programme En cas d anomalie une r initialisation du microcontr leur est effectu e Q38 Calculer le temps au bout duquel le circuit CI2 effectue un reset du microcontr leur en cas d anomalie logicielle Q39 Donner les seuils de d clenchement du reset en cas d anomalie sur la tension d alimentation du microcontr leur Q40 Compl ter le chronogramme document r ponse BR7 BTS Syst mes lectroniques Session 2011 i l Epreuve U41 Electronique Page B5 sur 5 SERET DOCUMENTS REPONSE Q8 Y MATEO A RETA NEO DORA TEE Se 20 02 JAIL L jo L 3S9 Vd 0107 80 70 ER T 090 EH y50900 Jdzz KS LO S3bvez38l z lt lt Izd ez lt lt Za IN Se x lt sd osal e E es V V 2 LZ Z Y de a 3U02 2001 ka SSO 169 By i v V NL v 198 e ZL AS ci mg DT pana gt td xD Kd yor P gt ZOd egy Eng ee Eat ET GGH ory a Y mn S3vEZ IM GL A f yot 30L i K uonesu dtuo3s pono oud A n 6vy Ly SES 893 AL l d gt R AL tao e Dron ed _ gt 8 1Z10 T 095 trag ES S OL re ES u vl L La Ly 05 Een FG di EH i WOL 954 d E 9g SLL ply 0 693 one 99 x0L We Sal SOEGHNO ZE 6 9 SE z 130 Z7 ola sz End lt pL E i y OZOLAAE 154 L AZL 6G 7 NN L AS 2001 Zso E ME EE SSI E e DOE EA A Sl Page BR1 sur 6 4 Epreuve U41 Electronique D 7 DL
31. al Port Modes MODE 0 Mode 0 is a synchronous mode which is commonly used for shift register based I O expansion In this BTS Syst mes Electroniques Epreuve U41 Electronique 20 Page BAN12 sur Session 2011 EE mode the TXD pin outputs a set of 8 pulses while the RXD pin either transmits or receives data Data is transferred amp bits at a time with the LSB first A dia gram of the relative timing of these signals is shown in Figure 10 2 Note that this is the only mode which uses RXD as an output Mode 0 Timings In Mode 0 the TXD pin sends out a clock train while the RXD pin transmits or receives the data Figure 10 2 shows the waveforms and timing In this mode the serial port expands the 1 0 capability of the 80C196KB by simply adding shift registers A schematic of a typical circuit is shown in Figure 10 3 This circuit inveris the data coming in so it must be reinverted in software MODE 1 Mode 1 is the standard asynchronous communications mode The data frame used in this mode is shown in Figure 16 4 It consists of 10 bits a start bit 0 8 data bits LSB first and a stop bit 1 If parity is enabled by setting SPCON 2 an even parity bit is sent instead of the Sth data bit and parity is checked on reception Session 2011 MODE 2 Mode 2 is the asynchronous 9th bit recognition mode This mode is commonly used with Mode 3 for muiti processor communications Figure 16 4 shows the data frame used
32. alonnage pour la plage de mesure utilis e l appareil va calculer la turbidit de l chantillon Les r f rences d talonnage sont des liquides purs eau de Volvic 0 06NTU ou des suspensions stables de Formazine de turbidit connue Une mesure a 180 degr s est galement effectu e pour compenser l att nuation due au vieillissement de la DEL et la couleur de l eau Flux lumineux diffuse image de la turbidit R cepteur Amplification d tection Synchrone Com pansation A Flux lumineux Transmis fonction de la coloration circulation d eau BTS Syst mes Electroniques Session 2011 Epreuve U41 Electronique Page A2 sur 7 11SEE4EL1 Analyse Fonctionnelle v T ah r i e Session 2011 1 3 Caract ristiques du Turbilight PRINCIPLE amp BACKGROUND FEATURES The SERES environnement TURBILIGHT is dedi cated to the continuous measurement of low turbidities in water using the nephelometric method The excellent performances demonstrated by the TURBILIGHT rely on its characteristics e Resolution Le the ability of an instrument to detect any measured value variation 0 01 NTU resolution for a 30 s integration time 0 001 NTU resolution for a 2 mn integration time no idle time e Repeatability that corresponds to the variation be tween two separate measurements made on the same sample repeatability of 1 of full range e Accuracy that depen
33. charge after that if the clock is normally input operation repeats 4 and 5 when the clock is cut off operation repeats 6 and 7 8 When Vcc falls on Vs 4 2 V reset is output C is rapidly discharged of at the same time 9 When Vcc goes up to Vsx the charge with C is started When Vec is momentarily low After falling Va or less Vcc the time to going up is the standard value of the Vcc input pulse width in Vsx or more After the charge of Cris discharged the charge is started if itis T or more 192 10 7 40 1 106 10 19 Cr terminal capacitance C uF Cr terminal capacitance Cr uF 7 terminal capacitance Cr iF Watch dog times watching time Two ms Reset time Tym ms Rising reset hold time Ter ms 10 Reset of the output is released after Ter after Vec becomes Vsx or more and the watch dog timer starts After that when Vcc becomes Vz or less 8 to 10 is repeated 11 While power supply is off when Vcc becomes Vs or less reset is output 12 The reset output is maintained until Vcc becomes 0 8 V when Vcc falls on 0 V BTS Syst mes Electroniques Page BAN16 sur Session 2011 preuve U41 Electronique 20 11SEE4EL1 Documentation S APPLICATION CIRCUIT EXAMPLE 1 Monitoring 5V Supply Voltage and Watchdog Timer EXAMPLE 9 Reducing Reset Hold Time VCC 5V O Vee 5 V MB3773 Logic circuit MB3773 Logic circuit Logic circuit Notes Supply voltage is monitored using Vs s
34. cle a 40 years dala retention simple interface to standard microcontrollers and micro processors There are 7 instructions lhat control these de m Endurance 106 data changes vices Read Erase Write Enable Erase Erase All Write Packages available 8 pin SO 8 pin DIP 8 pin TSSOP Write All and Erase Write Disable The ready busy status is available on the DO pin during programming Block Diagram INSTRUCTION DECODER CONTRO LOGIC AND CLOCK GENERATORS INSTRUCTION REGISTER ADDRESS REGISTER DECODER t OF 16 64 129 256 HIGH VOLTAGE GENERATOR AHD PROGRAM TIMER EEPROM ARRAY 15 64 128 256 x 16 READ WRITE AMPS DATA It QUT REGISTER 15 BITS BATA QUT SUFFER TL D 10751 1 IRLSTATE ia mgiloren trademark of Maione Semizonducter Deporin AROROMIRETA e y tradarmark of Masional Sosa crductor Corporation P4968 Mancadl Sarvcseductot Corporaor TL D 1575 SP Prag ir U S A hG A ven national com S9BLIOIUI SNG AHIMOHOIN HOHd13 IEUSS H4 960b 8r0c tc01 962 999 969 9 9 909E 6NN Connection Diagrams Pin Names JL Chipset a Serial Data Clock D Bang Data input D Serial Data Output Dual In Line Package N 8 Pin SO M8 and 8 Pin TSSOP MT8 TL DB 15751 2 Top View See NS Package Number NOBE MO8A and MTCO8 Absolute Maximum Ratings Note If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distrib
35. ds on the exactness of calibra tion and reapeatability upon factory calibration accuracy is range Due to the uncertainty around calibration on site resolution is in fact the most important parameter in an auto controlled operation Base line background noise is lt 0 001 NTU e Perfect linearity of the signal without interference for high turbidity values on O 10 NTU range Drift no drift over a 2 week period with 50 NTU suspended particles 1 of full z CS E OTL E LA K ben at gt ee Lu Ge t 53 3 D S SNS E CS E Sie lt e 11SEE4EL1 Epreuve U41 Electronique Analyse Fonctionnelle e Conforms to ISO 7027 NF EN 27027 standards e Nephelometric measurement e R source LED at 850 nm 20 nm Life time exceeding 3 years e Collimated incident beam e 90 measuring angle with a reduced optical path to prevent interferent reflections e Compensation of light source ageing and of water colour achieved via a measurement at 180 Convenient installation operation and service e Compact portable device e 230 VAC or 24 VDC power supply standard e Automatic cleaning of cell walls at programmable frequency e Routine calibration once every 6 months Continuous follow up of the quality of e drinking water e surface water Low medium ranges from 0 2 to 0 1000 NTU Set Krees gt anne siene environnement el kin US LT trs tr Se ae za ies ae Z 7 Sacra k BTS S
36. ected register to the logical 1 state CS is brought low following the loading of the last address bit This falling edge of the CS pin initiates the self timed programming cycle The DO pin indicates the READY BUSY status of the chip if CS is brought high after the tos interval DO logical D indicates that programming is still in progress DO logicat 1 indicates that the register at ihe address specified in the instruction has been erased and the part is ready for an other instruction Write WRITE The WRITE instruction is followed by 16 bits of data to be written into the specified address After the last bit of data is put on the data in D pin CS must be brought low before the next rising edge of the SK clock This falling edge of CS initiates the self timed programming cycle The DO pin indi cates the READY BUSY status of the chip if CS is brought high after the tes interval DO logical 0 indicates that programming is still in progress DO logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the in struction and the part is ready for another instruction Erase All ERAL The ERAL instruction will simultaneously program all regis ters in the memory array and set each bil lo the logical 1 State The Erase All cycle is identical to the ERASE cycle except for the different op code As in the ERASE mode the DO pin indicates the
37. ent to the fixed terminals of a mechanical potentiometer The minimum voltage is 5V and the maximum is 5V The terminology of V Ry and V R references the relative position of the terminal in relation to wiper movement direction selected by the U D input and not the voltagz potential on the terminal Pad Mia VuwlRw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer The position of the wiper within the array is determined by the control inputs The wiper terminal series resistance is typically 400 Up Down U D I The UD input controls the direction of the wiper movement and whether the counter is incremented or decremented Increment INC The INC input is negative edge triggered Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on th UID input Chip Select CS e The device is selected when the CS input is LOW The current counter value is stored in non volatile memory when CS is retumed HIGH while the INC input is also HIGH After the store operation is complete the ISLX9C102 X90103 X8C104 X9C503 device will be placed in the low power standby mode until the device is selected once again BTS Syst mes Electroniques Epreuve U41 Electronique EE Principles of Operation There are three sections of the X9C102 X9C 103 ISL9C104 and ISL9C503 the input control counter and decode section the no
38. etteur UN E 5 3 R cepteur EEN g RO Tag safis sansa murg ds gaeren miera ws atas am parent aa bof p i eed CHR Y 49 2002 H ise en car touche AH A TED tue Pores T0 32 MANY BPS E TTT LLULLU OT A S TTA SCOT 1 ci MASH Premier re diffusion ERS Bot ci TA Dese e Ups ine Dato i D sicuation V rifie Rey TURBILIGHT ccs a a re ee ld O RACCORDEMENTS E Tel ES 193 42 VF 37 ax 33 40 ih 42 Tt 30 30 A well seres ranta cam ch Page 12 BTS Syst mes Electroniques Epreuve U41 Electronique Session 2011 Page BAN18 sur 20 TISEE4EL Ki ZS EENEG as SEN ENNEN Po a O SE BEE EE A l G WIR RES ACA See A E a 10nF CO O m gt 5V TI NO G A q Z lt Di Se 1 R57 BYV1020 A 1 eme 10k s P0 3 DE1 CI22 lt D2 a NZ DNK5306 BYV1020 2 Vmesure C59 sone 2 R67 12VVY Fa G i ee R74 ST14 i ee Je S 3 R56 40M IT l 50 R54 o cp Vcomp E E Des R1 T4 Ol lt o ES s J R71 O0 4 y 10k i BD645 4 ee CI21 B 2 560 A 312 0 i vn 06 T CRTA b E ce AD648 UTK Ok Y L1 R49 E R68 A2V T 5 photodiode compensation N 40k V T5 5 Que IRFZ34ES 5 Oo Q Ref oe R46 R55 S cares Ee R62 R63 St D 0 10k P3 10k Pi lt d CT 12V Tk 1K LO 5V 2k R61 A IER C57 C55 470nF 470nF FO z Z1 R7 A N T 7 PES z q T3 IL 400 iL is E XTAL P2 7 gt gt z3 P2 6 gt gt 22 IRFZ
39. ignal rectangulaire de rapport cyclique Y et de fr quence FO qui sera utilis pour le d coupage du flux IR et servira de r f rence pour la d tection synchrone Z1 signal de commande envoy par l unit centrale pour limiter le courant dans le DEL durant la phase de d marrage de la compensation Compensation signal analogique permettant la commande en r gime lin aire de TA Sortie mission IR Flux IR mis de rapport cyclique et de fr quence FO dont l amplitude est contr l e par la compensation Fs1 4 amplification gain programmable Entr es V1 tension alternative de fr quence FO poss dant une composante continue dont l amplitude est proportionnelle a la turbidit Gain Sortie V2 Session 2011 11SEE4EL1 AC signal binaire permettant de modifier le gain tension alternative de fr quence FO BTS Syst mes Electroniques Epreuve U41 Electronique Page A7 sur 7 Analyse Fonctionnelle SUJET Les trois parties du sujet sont ind pendantes Les r ponses aux questions sont rendre sur feuilles d examen Les documents r ponse sont a rendre dans tous les cas avec votre copie m me si vous n y avez pas r pondu Partie A Analyse fonctionnelle Q1 Q2 Q3 Q4 Q5 Q6 Pr ciser l int r t d une station d alerte Citer les diff rents appareils qui permettent d valuer l tat de pollution de l eau avant traitement Citer le param tre de nettoyage qui sera modifi
40. l of the serial port is done through the Serial Port Control SP CON register shown in Figure 10 L Writing to location 11H accesses SP__CON while Session 2011 11SEE4EL1 BTS Syst mes Electroniques preuve U41 Electronique Documentation reading it accesses SP__STAT The upper 3 bits of SD CON must be written es Os for future compatibil ity On the SOCIS6KB the SP__STAT register contains new bits to indicate receive Overrun Error OE Fram ing Error FE and Transmitter Empty TXE The bits which were also present on the 8096BH are the Transmit Interrupt TD bit the Receive Interrupt RE bit and the Received Bit RBS or Receive Parity Error RPE bit SP__STAT is read only in Window D and is shown in Figure 10 1 In all modes the RI flag is set after the last data bit is sampled approximately in the middle of a bit time Data is held in the receive shift register until the last data bit is received then the data byte is loaded inte SBUF RX The receiver on the 80CI96KB also checks for a vahd stop bit If a stop bit is not found within the appropriate time the Framing Error FE bit is set Since the receiver is double buffered reception on a second data byte can begin before the first byte is read However if data in the shift register is ioaded inte SBUF RX before the previcus byte is read the Over flow Error OE bit is set Regardless the data in SBUF RX will always be the latest byte received it wili
41. leared when SP__STAT read The RI and TI status bits can be set by writing to SP__STAT in window 15 bur they will not cause an interrept Read ing of SP__CON in Window 15 will read the last value written Whenever the TXD pin is used for the serial port it must be enabled by setting IOC 5 toa i 1 0 control register 1 can be read in window 15 to deter mine the setting STARTING TRANSMISSIONS AND RECEPTIONS In Mode 0 if REN 0 writing to SBUF TX will start a transmission Causing a rismg edge on REN or clearing RI with REN 1 will start reception Set ting REN 0 will stop a reception in progress and inhibit further receptions To avoid a partial or com plete undesired reception REN must be set to zero be fore RE is cleared This can be handled in an interrupt environment by using software flags or in straight line code by using the Interrupt Pending register to signal the completion of a reception In the asynchronous modes writing to SBUF TX Starts a transmission fallme edge on RAD will begin o reception if REN is set to L New data placed in SBUF TX is held and will not be transmitted until the end of the step bit has been sent In all modes the RI flag is set after the last data bit ts sanipled approximately in the middle of the bit time Also for all modes the TI flag is set after the fast data bit either Sth or 9th is sent also in the middle of the bit time The flags clear when SP STAT is read but do
42. lue Error A maximum baud rate of 730 Kbaud is available in the asynchronous modes with 12 MHz on XTALI The synchronous mode has a maximum rate of 3 0 Mbaud with a 12 MHz clock Location OEH is the Baud Regis ter It is loaded sequentially in two bytes with the low byte being loaded first This register may not be loaded with zero in serial port Mode O 10 2 Serial Port Interrupis The serial port generates one of three possible inter rupts Transmit Interrupt TI 2030H Receive Inter rupt RI 2032H and SERIAL 200CH When the RI bit gets set an interrupt is generated through either 200CH or 2032H depending on which interrupt is en abled INT__MASK1 1 controls the serial port receive interrupt through location 2032H and INT__MASK 6 controls serial port interrupts through location 200CH The 8096BH shared the TI and RI interrupts on the SERIAL interrupt vector On the 80C196KB these in terrupts share both the serial interrupt vector and have their own interrupt vectors When the TI bit is set it can cause an interrupt through the vectors at locations 200CH or 2030 Interrupt through location 2030 is determined by INT _ MASK 1 0 Interrupts through the serial interrupt is controlled by the same bit as the RI interrupt NT__ MASK 6 The user should not mask off the serial port interrupt when using the double buffered feature of the transmitter as it could cause a missed count in the number of bytes being transmitted 10 3 Seri
43. mpensation puis mesur e par le convertisseur A N broche P0 3 du microcontr leur La mesure du courant moyen dans la DEL D I est assur e par l entr e P0 2 du microcontr leur partir du sch ma structurel BAN19 Q15 Donner la relation liant Vmesure Vcomp en consid rant que le condensateur C52 se comporte comme un circuit ouvert Q16 D terminer le r le des diodes D9 et D10 3 Amplification gain programmable FS1 4 C39 Session 2011 BTS Syst mes Electroniques Epreuve U41 Electronique Page B2 sur 5 TISEEAELI Q17 En utilisant la documentation BANS BANG dessiner sur le document r ponse BR2 le mod le quivalent du circuit en pointill constitu de U1 et de R20 que l on nommera Rx Q18 Si le compteur interne U1 a la valeur 96 pr ciser alors la valeur que prend la r sistance Ru Q19 Donner l expression de R en fonction de la valeur N du compteur interne a U1 Q20 Ce composant U1 tant command par le microcontr leur compl ter l algorigramme document r ponse BR3 qui permettra de faire varier sa valeur de 50kQ 10kQ Q21 On supposera qu la fr quence de travail Cs se comporte comme un court circuit et C comme un circuit ouvert tablir la relation V2 f V1 Q22 Indique le r le de Rx On donne les r sultats de simulation de la r ponse en fr quence document r ponse BR4 de la fonction Fs1 4 Q23 Indiquer sur le graphe quelles valeurs de Rx correspondent les courbes
44. n volatile memory and the resistor array The input control section operates just like an up down counter The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output Under the proper conditions the contents of the counter can be stored in non volatile memory and retained for future use The resistor array is comprised of 99 individual resistors connected in series At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper The wiper when at either fixed terminal acts like its mechanical equivalent and does not move beyond the last position That is the counter does not wrap around when clocked to either extreme The electronic switches on the device operate in a make before break mode when the wiper changes tap positions Hf the wiper is moved several positions multiple taps are connected io the wiper for Hw INC to VnlRyy change The Ryora value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions When the device is powered down the last wiper position stored will be maintained in the non volatile memory When power is restored the contents of the memory are recalled and the wiper is reset to the value last stored The internal charge pump allows a wide range of voltages from 5V to SV applied to XDCP terminais yet
45. nev er be a combination of the two bytes The RI FE and OE flags are cleared when SP__STAT is read Howev er RE does not have to be cleared for the serial port te receive data Page BAN10 sur 20 SP__CON TBS Sets the ninth data bit for transmission Cleared after each transmission Not valid if parity is enabled REN Enables the receiver PEN Enables the Parity function even parity a M2 M1 Sets the mode Mode 00 Model 01 Mode2 10 Mode3 i Zb STAT RB amp Set if the 9th data bit is high en reception parity disabled RPE Set if parity is enabled and a parity error occurred RI Set after the last data bit is sampled TI Set at the beginning of the STOP bit transmission FE Set if no STOP bit ts found at the end of a reception TXE Set if two bytes can be transmitted QE Set if the receiver buffer is overwritten Figure 10 1 Serial Port Controi and Status Registers Session 2011 The Transmitter Empty TXE bit is set if the transmit buffer is empty and ready to take up to two characters TXE gets cleared as soon as a byte is written to SBUP Two bytes may be written consecutively to SBUF if TXE is set One byte may be written if TE alone is sel By definition if FXE has just been set a transmission has completed and TI will be set The TI bit is reset when the CPU reads the SP__STAT registers The TBS bit is cleared after each transmission and both TI and RI are c
46. nge 0 001 NTU for full range 0 5 NTU 1 full range Manual using 2 standard solutions slope and zero once every 6 months 50 I h approx 6 bars maximum 4 C minimum 40 C maximum basic unit with automatic system using a piston operated wiper at 10 min or user configured frequency L line alphanumerical 8 characters 0 20 mA or 4 20 mA 500 ohms RS232 current loop by interface converter option JBUS RS485 signal option 2 thresholds per dry contact relay programmable analyser failure 230V AC 50 Hz or 24V DC 25W 110 V AC GO Hz option NF ENG10004 2 CE 801 2 NF ENG10004 4 CEl 801 4 NF C 46 022 CEI 801 3 NF EN55022 Steel epoxy IPG5 housing 300 x 340 x 150 mm Hx Lx W Weight 6 5 kg Low Tel 33 014 42 97 37 37 EE Fax 33 014 42973030 fm s D L Som seres france seres france com S be K Kn Simen d www serestrance com VITOR EINEN L Emall BTS Syst mes Electroniques Page A4 sur 7 Ans gy 96ed a 9uuonouoy as jeuy enbiuo 99 3 Lpn sAnaldy senbuo1 0a 3 s ui ls S S19 LGL L LOZ uolss s P Fr rem mn emp Kn Fe rz em mam Fr SE em RE pg rt Fran Pez eem De See rrna Een zen pa vng Wong Pen Fe Pap po Soen Gran aer pm AS pg oe DOM Fam DONNE me D rag Da s N u w ss mas ben nat w 9114 BANDS ej SUED INS W ep uolinueuo SP 1jyu uu uuonipuoo Glia s ns sinNajeaA sep eHbeudiyy alos uosielj ued UOHESIUNLLULUOSD Elid ANSJONUCDOIDILU Jed alipiqun e
47. not have to be clear for the port to receive or trans mit The serial port interrupt bit is set as a logical OR of the RI and TI bits Note that changing modes will reset the Serial Port and abort any transmission or re ception in progress on the channel BTS Syst mes Electroniques Epreuve U41 Electronique 20 Page BAN11 sur TTSEE4EL BAUD RATES Baud rates are generated based on either the T2CLK pin or NTALI pin The values used are different than those used for the SOS6BH because the SOC196KB uses a divide by 2 clock instead of a divide bv 3 clock to generate the internal timings Baud rates are calculated using the following formulas where BAUD REG is the value loaded into the baud rate register Asynchronous Modes 1 2 and 3 XTAL1 T2CLK BAUD REG 1 Q0R Baud Rate 16 Baud Rate 8 Synchronous Mode 9 SAUD REG ATALI Ss __T2CEK Baud Rate 2 Saud Rate The most significant bit in the baud register value is set to a one to select XTALI as the source If it is a zero the T2CLE pin becomes the source The following ta ble shows some typical baud rate values BAUD RATES AND BAUD REGISTER VALUES ATAL1 Fret uency Rate 8 0 MHz 10 0 MHz 12 0 MHz 1666 0 02 2082 0 02 2498 0 00 416 0 08 520 0 031 624 0 00 207 0 15 259 0 16 312 0 16 103 0 16 129 0 16 155 0 16 511016 9470 16 7110 16 25 0 16 32 1 40 38 0 16 Baud Register Va
48. plications The TO 220 package is universally preferred for all commercial industrial applications at power dissipation levels to approximately 50 watts The low thermal resistance and low package cost of the TO 220 contribute to its wide acceptance throughout the industry Absolute Maximum Ratings ver 9 9 T 25 C la Tc 100 C Di Pp Te 25 C Power Dissipation a AA Voss Gate to Source Voliage Single Pulse Avalanche Energy 97 CS Avalanche Current ec ele E Repetitive Avalanche Energy Pe ee ee E S Ls vidt Peak Diode Recovery dv di G TO 220AB Units E I Ip Drain to Source Current A Pp A Soldering Temperature for 10 Seconds 300 1 6mm from case Mounting torque 6 32 or M3 srew 10 ibf in 1 1Nem Case to Sink Fiat Greased Surface Junction to Ambient PE A International IRFZ34E TR Rectifier 1000 4000 TE 15 me 49V RRE IOC gt Za TICCI m UN ARE RON DNS PE lt lt 75V J i III st 5 0 5 E 25 G 100 100 SV O CH 3 RTE CT 9 2 z siwa do AE LI S D E E eo E A CAA e E T e EE EE Ee e SV 7H Ze nea Lo L a LATIN LO a mes Amien pmt ag TT Lus S C EE O A Vos Drain to Source Voltage V Vos Drain to Source Voltage V Fig 1 Typical Output Characteristics Fig 2 Typical Output Characteristics 100 eee TTT DID OTT OT Uert EE SR HEE UL eA CAMA MATO 2
49. r e e es ns n e gp rn ep e pg an s H e n ll n gt IL x ll n sl tof tt P HI H d H H D H a Y a a L L 4 H H a H H H H D a e l i i ven DI i i DATA A v n D H H t H 1 De Z e ALA ar mg rome in go ra aa H servo E ss D H H e i eo Z pt es II D D D P P E P CH Ch DOY ch2 5 00 Y V IE 5 00V chal 5 00 V T 3 000 Teo e rt Zur C8 06 D8 1 FA OA A 62 6 AA 1E On 3C gA Z DC BR 04 02 20 03 64 GG ES 03 GA 89 64 BB HORL 3 I t L DATA BTS Syst mes lectroniques preuve U41 lectronique Page BR5 sur 6 EE Session 2011 r Q36 Tek Prevu ee Lee ERE TE SE aeai t a a A al RTA a a n m BR SCH Torere r a H SZ A e gt o ZS e o S o sz u o r a ae 1 1 00ms 3 u Ta Chi Z 2340 G Q37 unsigned char Init_Serial unsigned char c BAUD_REG Ox configure timer for the correct baud rate SP CON Ob Set Serial IO to receive and normal modei Q40 Valim 5V DV qv 1s 25 3s 4s 5s 6s S DS BTS Syst mes lectroniques preuve U41 lectronique Page BR6 sur 6 een Session 2011 sommaire 4060 BAN2 CD4504 BAN3 BYV10 BAN3 IRFZ34E BAN4 X9C104 BAN5a BAN6 DNK5306x BAN6 27C256
50. rameter Supply voltage Vee Input voltage Vex RESET RESET Supply voltage Power dissipation Ta lt 85 C Storage temperature WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings Page BAN14 sur 20 m BLOCK DIAGRAM e MB3773 Basic Operation Reference AMP Logic Circuit RESET RESET CK Ter ms 1000 Cr uF Te ms 100 Cr uF Tag ms 20 Cr uF IB A Example Cr 0 1 uF Tar ms 100 ms Teo ms 10 ms Tor ms 2 ms RESET RESET S FUNCTIONAL DESCRIPTIONS Comp S is comparator including hysteresis it compare the reference voltage and the voltage of Vs so that when p To the voltage of Vs terminal falis below approximately 1 23 V reset signal outputs 2 GEN instantaneous breaks or drops in the power can be detected as abnormal conditions by the MB3773 within a C 2 us interval However because momentary breaks or drops of this duration do not cause problems in actual systems in some cases a delayed trigger function can be created by connecting capacitors to the Vs terminal Comp O is comparator for turning on off the output and compare the voltage of the Cr terminal and the threshold voltage Because the RESET RESET outputs have built in pull up circuit there is no need to connect to externai pull up resistor when connec
51. requency BTS Syst mes lectroniques Session 2011 preuve U41 lectronique Page BAN8 sur 20 ISERE Functional Description The NM93C06 C46 C56 C56 devices have 7 instructions as described below Note that the MSB of any instruction is a 1 and is viewed as a start bit in the interface sequence For the COS and C46 the next 8 bits carry the op code and the 6 bit address for register selection For the C56 and C68 the next 10 bits carry the op code and the 8 bit address for register selection All Data in signals are clocked into the device on the low to high SK transition Read READ The READ instruction outputs serial data on the DO pin After a READ instruction is received the instruction and ad drass are decoded followed by data transfer from the se lected memory register into a 16 bit serial out shift register A dummy bit logical 0 precedes the 16 bit data output string Output data changes are initiated by a low to high transition of the SK clock Erase Write Enable WEN When Vcc is applied to the part it powers up in the Erase Write Disable WDS state Therefore all programming modes must be preceded by an Erase Write Enable WEN instruction Once an Erase Write Enable instruction is exe cuted programming remains enabled until an Erase Write Disable WDS instruction is executed or Vcc is completely removed from the part Erase ERASE The ERASE instruction will program ail bits in the sel
52. s de transmission BTS Syst mes Electroniques Session 2011 f Epreuve U41 Electronique Page B4 sur 5 See Rappel de la trame s rie ae LAO Ono 1 po qO 0 y l Repos Start Do Di D2 Ds D4 Ds De D7 STOP Repos K D but de Fin de transmission D transmission Etude du g n rateur de courant 240 Caract ristiques du 2N2906 gt Vce max 40V Vbe 0 6V Hfe 100 HLPM3000 gt Vf 1 9V 20mA Q34 Etablir la relation le f Vf Vbe R85 puis en d duire le courant boucle gt SB2 Q35 En vous aidant de la page12 du manuel d utilisation BAN18 proposer une m thode simple pour tester la liaison en l absence d ordinateur sachant que le turbilight gt envoie r guli rement des donn es Iboucle Q36 Rep rer sur le chronogramme image du courant de boucle document r ponse BRE les intervalles de temps correspondants aux e bit de start e 8 bits de donn es bit de stop Pr ciser la valeur transmise La vitesse de transmission est programm e l aide du registre BAUD REG en vous aidant de la documentation BAN 10 13 Q37 D terminer la valeur qu il faut mettre dans le registre BAUD REG pour obtenir la vitesse de 9600 bauds Compl ter la fonction d initialisation de la transmission s rie document r ponse DREI pour les valeurs des registres BAUD_REG et SP_CON en mode r ception Le circuit Cl2 MB3773 documentation technique page BAN14 17 contr le l
53. t of the output is released Reset hold time Ter ms 1000 x C UE After releasing reset the discharge of C starts and watch dog timer operation starts Ter is not influenced by the CK input Watch dog timer walching time Tvo ms Reset time Tur ms 4 C changes from the discharge into the charge if the clock Negative edge is input to the CK terminal while discharging Cr 5 C changes from the charge into the discharge when the voltage of C reaches a constant threshold 1 4 V 4 and 5 are repeated while a normal clock is input by the logic system EE Temperature Ta C 6 When the clock is cut off gets and the voltage of Cr falls on threshold 0 4 V of reset on RESET goes Cr terminal capacitance Low and RESET goes High ve Cr terminal capacitance Cr terminal capacitance Discharge time of Cr until reset is output Two is watch dog timer monitoring time Watchdog timer watching time vs Reset time vs Rising reset hold time Twe ms 100 gt Cr uF fat watch deg timer Because the charging time of C is added at accurate time from stop of the clock and getting to the output of reset of the clock Twa becomes maximum Tac Twe by minimum Te 7 Reset time in operating watch dog timer Tue is charging time where the voltage of C goes up to off threshold 1 4 V for reset Twa ms 20 x Cr uP Reset of the output is released after Cr reaches an off threshold for reset and Cr starts the dis
54. ted to a high impedance load such as CMOS logic IC It corresponds to 500 KO at Vcc 5 V when the voltage of the CK terminal changes from the high level into RESET the Low level pulse generator is sent to the watch dog timer by generating the pulse momentarily at the time of drop from the threshold level When power supply voltages fall more than detecting voltages the watch dog timer becomes a interdiction The Reference amplifier is a op amp to output the reference voltage d s comparator is put up outside two or more power supply voltage monitor and overvoltage monitor can be oi CG GS 5 Sn Bus 5 an 112 one lf it uses a comparator of the open collector output and the output of the comparator is connected with the Vs terminal of MB3773 without the pull up resistor it is possible to voltage monitor with reset hold time BTS Syst mes Electroniques Page BAN 15 sur s Session 201 preuve U41 lectronique 20 TISEE4ELi B OPERATION SEQUENCE Reset time vs Watchdog timer watching time 1 When Vcc rises to about 0 8 V RESET goes Low and RESET goes High Temperature vs Temperature At watch deg mer The pull up current of approximately 1 uA Vcc 0 8 V is output from RESET 2 When Vcc rises to Ves 4 3V the charge with Cr starts At this time the output is being reset 3 When C begins charging RESET goes High and RESET goes Low After Tea rese
55. utors for availability and specifications Ambient Storage Temperature 65 C to 150 C Operating Conditions Ambient Operating Temperature NM93C06 NM93C66 NM93CO6E NMS83C65E NM93C06V NM93C66V OC to 70 C 40 C to 85 C 40 C to 125 C All input or Output Voltages 6 5V to 0 3V Power Supply Voo 4 5V to 5 5V with Respect to Ground Lead Temp Soldering 10 sec 300 C ESD Rating 2000V DC and AC Electrical Characteristics vog 5 0V 10 unless otherwise specified Note Throuqhot this tabla H refars to temperature range 55 C to 125 C noi package Symbol Part Number loca Operating Current NM93C06 NMY93C66 CS Vip SK 1 MHz NM93CO6E V NM93SCE5E V SK 1 MH locas Standby Current NM93C06 NM93C66 CS Vu NM93COSE V NMS3C65E V hL Input Leakage Vin OV to Voc SS ek lol Output Leakage Note 3 u Vit Input Low Voltage a 1 y Vin input High Voltage ei Vo Output Low Voltage oL 2 1 m V VoH1 Output High Voltage lon 400 LA 2 4 V VoLz Output Low Voltage lol 10uA 0 2 y Vou2 Output High Voltage H Vcc 0 2 Eg x Conditions aa E gt lou 10 pA NM93C06 NM93C66 Note 4 NM93C056E V NM93C66E V iSKH SK High Time NM93C06 INM93C66 250 z NM93COSE V NM93C66E V 300 Lee SK Setup Time SK must be ai Vu for 50 ns tars before CS goes high SC E tos Minimum CS NM93C06 NMS3C66 Note 2 250 E Ge Low Time NMS3COGE V NMS3C66E V 250 fsk SK Clock F
56. yst mes Electroniques Page A3 sur 7 Session 2011 11SEE4EL1 TURBILIGHT ANALYTICAL METHOD The TURBILIGHT operates on the principle of nephelometry that consists in measuring light diffused at an angle of 90 degrees to that of an incident light beam The resulting signal is strictly proportional to the concentra tion of diffusing particles and to the water turbidity The zero is true There is no signal if the measuring vessel contains turbidity free water The measuring vessel is pressurized to eliminate air bub bles interferences TECHNICAL SPECIFICATIONS Measuring ranges Measuring units Measurement Response time Accuracy Resolution Repeatability Calibration Hydraulic supply Sample temperature Cleaning Display Output signal Alarms Electric power supply EMC certified Dimensions amp weight SERES environnement BGO rue Louis de Broglie La Duranne BP 20087 13793 Aix en Provence Cedex 3 France preuve U41 lectronique Analyse Fonctionnelle Measuring cell at 90 Compensation cell at 180 Projector LED Measuring vessel O 2 NTU OS NTU 0 10 NTU 0 20 NTU 0 50 NTU 0 100 NTU Medium 100 NTU 0 250 NTU 0 500 NTU O 750 NTU 0 1000 NTU Ranges are user configurable and selectable NTU or FTU others on request continuous initial response few seconds 90 of value within less than 30 seconds 1 full ra
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