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ModelSim User's Manual

1. OK Cancel ModelSim User s Manual v6 3g 273 May 2008 Waveform Analysis Creating and Managing Breakpoints 274 ModelSim User s Manual v6 3g May 2008 Chapter 10 Debugging with the Dataflow Window This chapter discusses how to use the Dataflow window for tracing signal values browsing the physical connectivity of your design and performing post simulation debugging operations Dataflow Window Overview The Dataflow window allows you to explore the physical connectivity of your design Note 3 OEM versions of ModelSim have limited Dataflow functionality Many of the features described below will operate differently The window will show only one process and its attached signals or one signal and its attached processes as displayed in Figure 10 1 Figure 10 1 The Dataflow Window undocked ModelSim z dataflow File Edit View Navigate Trace Tools Window amp X aod i BANC AR be 5 X 3e 3 9 AGA QAQA B mi INITIAL 58 addr_r data r m nwa strb_r verbose a ld 4 k Dataflow Usage Flow The Dataflow window can be used to debug the design currently being simulated or to perform post simulation debugging of a design ModelSim is able to create a database for use with post ModelSim User s Manual v6 3g 275 May 2008 Debugging with the Dataflow Window Dataflow Usage Flow simulation debugging The database is created at desi
2. When you create or modify a symlib file you must generate a file index This index is how the Nlview widget finds and extracts symbols from the file To generate the index select Tools Create symlib index Dataflow window and specify the symlib file The file will be rewritten with a correct up to date index Current vs Post Simulation Command Output ModelSim includes drivers and readers commands that can be invoked from the command line to provide information about signals displayed in the Dataflow window In live simulation mode the drivers and readers commands will provide both topological information and signal values In post simulation mode however these commands will provide only topological information Driver and reader values are not saved in the post simulation debug database Window vs Pane In this chapter we use the terms window and pane Window is used when referring to the entire Dataflow window whether docked in the Main window MDI frame or undocked Pane is used when referring to either the dataflow pane or the wave viewer pane as shown in Figure 10 7 ModelSim User s Manual v6 3g 285 May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference Figure 10 7 Dataflow Window and Panes Dataflow window ET CEN m File Edit View Add Trace Tools Window INITIAL 11 RASSIGNIS SASSIGNES areg a ASSIGNE ZASSIGN S dja d
3. 04 426 Troubleshooting a Missing DPI Import Function ssleleeeeeeeeeees 426 Simplified Import of FLI PLI C Library Functions 0 0 0 00 000 426 Use Model for Locked Work Libraries 427 Making Verilog Function Calls from non DPI C Models 004 428 Calling C C Functions Defined in PLI Shared Objects from DPI Code 428 Compiling and Linking C Applications for PLI VPI DPI 000 5 429 Widows Platforms C osa si ogee bx Ex ue ERR EE ERE E REEL MEE HR 429 Compiling and Linking C Applications for PLI VPI DPI 0 431 Windows Platforms CA concede gadadnd ope edeWieew sad ahoghad oedeoeee ds 432 Specifying Application Files to Load 0 0 cece eee eee 433 PLY Pl ile IOSCHBE aura oua one doe RE IEERU ES EOS ERROR E Rd be e a edo aree 433 DPI File Loading 2 uc kecie RR EE RYE GUu t EXDCHR DRE PS Ka ER Ra DR RE 433 Loading Shared Objects with Global Symbol Visibility 0 434 12 ModelSim User s Manual v6 3g May 2008 Table of Contents PLIBXIHIBE cs aaa boc eae PO RIA ee See ee E Re CEP Ree ee Eee ERE ete 434 VPLEXaMPlE suas exa RA SEREXSRTPRENSESBG ee RA SEN eee ee 435 DP ESSmple uo acca a ddcpedes Swe REO ELE CEDAT RES ME SE eae REI ETE 436 The PLI Callback reason Argument uses esheetaeexheerbrrRRO EG E ER ERR TERR 437 The sizeti Callback Function 24234 E3 RET ER AU REVIENS EREC RED eRI XE EK 43
4. Design VHDL Verilog Libraries SDF Others all Path i work Library C Tutorial examples tutorials mixed compare work i sv_std Library MODEL_TECH sv_std vital2000 Library MODEL_TECH vital2000 f ieee Library MODEL TECH ieee i modelsim lib Library MODEL TECH modelsim lib Hi std Library MODEL_TECH std i std developerskit Library MODEL TECH std developerskit i synopsys Library MODEL TECH synopsys din rE Design Unit s Resolution default w ptimization v Enable optimization Optimization Options Cancel a Amm mmc 2 Specify a name in the Simulation Configuration Name field 3 Specify the folder in which you want to place the configuration see Organizing Projects with Folders 4 Select one or more design unit s Use the Control and or Shift keys to select more than one design unit The design unit names appear in the Simulate field when you select them 5 Use the other tabs in the dialog to specify any required simulation options Click OK and the simulation configuration is added to the Project tab 122 ModelSim User s Manual v6 3g May 2008 Projects Organizing Projects with Folders Figure 4 14 Simulation Configuration in the Project Tab Folder VHDL 3 06 07 04 07 35 46 PM VHDL 2 06 07 04 07 36 26 PM Folder Verilog 06 07 04 07 36 21 PM Verilog 06 07 04 07 35 56 PM Simulation Doubl
5. If the input and output ports are omitted in the SDF then all path delays are matched in the cell e DEVICE is matched to primitives or specify path delays Table 12 5 Matching SDF DEVICE to Verilog DEVICE y 5 and ul y a b DEVICE y 5 a gt y 0 b gt y 0 If the SDF cell instance is a primitive instance then that primitive s delay is annotated If it is a module instance then all specify path delays are annotated that drive the output port specified in the DEVICE construct all path delays are annotated if the output port is omitted If the module contains no path delays then all primitives that drive the specified output port are annotated or all primitives that drive any output port if the output port is omitted SETUP is matched to setup and setuphold Table 12 6 Matching SDF SETUP to Verilog SETUP d posedge clk 5 setup d posedge clk 0 SETUP d posedge clk 5 setuphold posedge clk d 0 0 e HOLD is matched to hold and setuphold Table 12 7 Matching SDF HOLD to Verilog HOLD d posedge clk 5 hold posedge clk d 0 HOLD d posedge clk 5 setuphold posedge clk d 0 0 ModelSim User s Manual v6 3g 321 May 2008 Standard Delay Format SDF Timing Annotation sdf_annotate e SETUPHOLD is matched to setup hold and setuphold Table 12 8 Matching SDF SETUPHOLD to Verilog CNN RN SETUPHOLD d posedge clk 5 5 setup d
6. 00 002 cee neue 279 Tracing Events Causality e 06cccatenherdidewhde RERE ENEE Ee see ee Sere ee 281 Tracing the Source of an Unknown State StX 2 llle 281 Finding Objects by Name in the Dataflow Window 0 000 eee eee ee 283 Dataflow Conca R m 284 Symbol Mapping ue dees iere RR Obese uL PECES ERR REPE que R Ohlsen ees 284 Current vs Post Simulation Command Output ssns esasan aeaaeae 285 Window vs Pane 2s oe RE RR LKEREI dU EG AE SG dE ava es E desde 285 Dataflow Window Graphic Interface Reference 0 cece eee eee ene 286 What Can I View in the Dataflow Window 0 0 cece eee eee 287 How is the Dataflow Window Linked to Other Windows 0000 287 How Can I Print and Save the Display 2 0 02 2 cece ee eee 287 How Do I Configure Window Options 0 0 0 c cece ee eens 289 How Do I Zoom and Pan the Display rios eu4V eek re RV I REC gea ice 290 Chapter 11 Signal SPY 52er cna Pa Rusa d quee so9b4Gus ease sane daons eee endo CERE SERE E E d a 293 Designed for Testbench S au s mes es 2089 XX E ae AEN S desc VY rb Bees 293 disable signal Spy esos o ne uke se ewes GOR a eae ou ete Goes CEN E P a woe knees 295 enable signal SDY saa ketePesabetRsta9 ema eerdh e aSeeate EA DX C RE LEX a 297 it Signal dryer sesia de di ek eee ee ee sh eee Re E eh eee ek ee EP 299 it SI Bal Spy does qacue eR EUR IAN VERSUM heat DA es Qr pee ee essere ES ERE 303 SUCI E RRR
7. 0000 5 167 Converting an Integer Into a bit_vector 1 2 0 0 cece cee eee eens 167 6 ModelSim User s Manual v6 3g May 2008 Table of Contents Chapter 7 Verilog and SystemVerilog Simulation 0 cee cece ccc e cece cere ee ees 169 lernmmology nad klcti eeeeRPb riasin k PERPE C E Taqa eeu dude d dbi ees 169 Basic Verilog FLOW 4 da ae menangan miaa id Rehd mme PNEU d RR eI S Pepe d 169 Compiling Verilog Files i t ERR REG RH RR seen ease ebeqa pigs 169 Creatine n Working Libfary ere coses Rxr es epEREC SERMO eR ERI RES ENS 170 Invoking the Verilog Compiler seeeeeeeeeee III 170 Incremental Compilation 3 cesa bh wq TAE P RECO CO I D ERA a Rp 171 Lara OS ARS CPP 173 SystemVerilog Multi File Compilation Issues llle 175 Verilog XL Compatible Compiler Arguments 176 Verilog XL uselib Compiler Directive lt 2 2 2 ssecssd padewaset deere RER ERES 177 Verilog Configurations ss ea ware oO uce ao wee pate a ea ow ae ee ale ies OR race ERN 180 Verilog Generate Statements 4 0 44 c0 page ce bead aero GEG ae OR EGE ER REA RR n 181 Simulating Verilog Designs 2 vos 2s o cede ESk sehen u Ex aae SERE EE RE C pad aria 182 Simulator Resolution Limit Verilog 0 0 cece eee eee 182 Event Ordering in Verilog Designs 2 012024 o0ce04e eset EPRREAERR REGE ARRAS REIR E es 185 Debugging Event Order Issues 5 52 2 ieee chee E RE laa a ches E PEE 188 Debugging Signal Segmentation Violations
8. The ModelSim User s Manual focuses primarily on the GUI mode of operation However this section provides an introduction to the Command line and Batch modes Command Line Mode In command line mode ModelSim executes any startup command specified by the Startup variable in the modelsim ini file If vsim is invoked with the do command string option a DO file macro is called A DO file executed in this manner will override any startup command in the modelsim ini file During simulation a transcript file is created containing any messages to stdout A transcript file created in command line mode may be used as a DO file if you invoke the transcript on command after the design loads see the example below The transcript on command writes all of the commands you invoke to the transcript file For example the following series of commands results in a transcript file that can be used for command input if top is re simulated remove the quit f command from the transcript file if you want to remain in the simulator ModelSim User s Manual v6 3g 29 May 2008 Introduction What is an Object vsim c top library and design loading messages then execute transcript on force clk 1 50 0 100 repeat 100 run 500 run 85000 quit f Rename transcript files that you intend to use as DO files They will be overwritten the next time you run vsim if you don t rename them Also simulator messages are already commented out but any m
9. Example VHDL Simulation Util Package Description The time value represented as a real with respect to the simulator resolution Description The value of the physical type time If the simulator resolution is set to ps and you enter the following function realval z to real 12 99 ns then the value returned to realval would be 12990 0 If you wanted the returned value to be in units of nanoseconds ns instead you would use the get resolution function to recalculate the value realval 1e 9 to real 12 99 ns get resolution If you wanted the returned value to be in units of femtoseconds fs you would enter the function this way realval 1e 15 to real 12 99 ns get resolution to time The to time utility converts a real value into a time value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you converted 5 9 to a time and the simulator resolution was 1 ps then the time value would be rounded to 6 ps Syntax timeval to time realval ModelSim User s Manual v6 3g May 2008 157 VHDL Simulation Modeling Memory Returns Name Type Description timeval time The real value represented as a physical type time with respect to the simulator resolution Arguments Name Type Description realval real The value of the type real Related functions e get resolution to real Exa
10. Figure 10 9 The Print Dialog Cn 0 Poo Properties Name Status Ready Type HP LaserJet 5L Where LPT1 Comment Print to file Print range Copies All Number of copies 1 C Pages from o ta o C Selection DER sp Cancel 288 ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference Configure Page Setup With the dataflow pane in the Dataflow window active select File gt Page setup to open the Dataflow Page Setup dialog Figure 10 10 You can also open this dialog by clicking the Setup button in the Print Postscript dialog Figure 10 8 This dialog allows you to configure page view highlight color mode orientation and paper options Figure 10 10 The Dataflow Page Setup Dialog Dataflow Page Setup x view r Highlight C Full off Current View C On Color Mode Orientation C Color Portrait C Invert Color A Landscape Mono z F Paper Font Helvetica 7 OK Cancel How Do I Configure Window Options You can configure several options that determine how the Dataflow window behaves The settings affect only the current session Select Tools gt Options to open the Dataflow Options dialog box ModelSim User s Manual v6 3g 289 May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference Fi
11. o svGetArrElemPtr svGetArrElemPtrl1 svGetArrElemPtr2 and svGetArrElemPtr3 e F 11 5 Access to elements via canonical representation The tool does not support any of the functions defined in this section and will produce a message stating that it is Not implemented e F 11 6 Access to scalar elements The tool does not support any of the functions defined in this section and will produce a message stating that it is Not implemented Verilog XL Compatible Routines The following PLI routines are not defined in IEEE Std 1364 but ModelSim Verilog provides them for compatibility with Verilog XL char acc decompile exp handle condition This routine provides similar functionality to the Verilog XL acc decompile expr routine The condition argument must be a handle obtained from the acc handle condition routine The value returned by acc decompile exp is the string representation of the condition expression char tf dumpfilename void This routine returns the name of the VCD file void tf dumpflush void A call to this routine flushes the VCD file buffer same effect as calling dumpflush in the Verilog code int tf getlongsimtime int aof hightime 444 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI 64 bit Support for PLI This routine gets the current simulation time as a 64 bit integer The low order bits are returned by the routine while the high order bits are stored in the aof_hightime argumen
12. 422 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI DPI Use Flow vlog dut v gcc shared Bsymbolic o imports so imports c vsim sv lib imports top do do files The sv lib option specifies the shared library name without an extension A file extension is added by the tool as appropriate to your platform For a list of file extensions accepted by platform see DPI File Loading You can also use the command line options sv root and sv liblist to control the process for loading imported functions and tasks These options are defined in the IEEE Std P1800 2005 LRM DPI Use Flow Correct use of ModelSim DPI depends on the flow presented in this section ModelSim User s Manual v6 3g 423 May 2008 Verilog PLI VPI DPI DPI Use Flow 424 Figure C 1 DPI Use Flow Diagram Step 1 Create header dpiheader h Step 2 Include header Step 1 5 Required for Windows only vsim dpiexportobj exportobj lt exportobj gt C compiler mtipli lib O compiled user code Id link loader linker Step 3 Compile and load link C code lt test gt so shared object vsim Step 4 Simulate vsim sv lib lt test gt Run vlog to generate a dpiheader h file This file defines the interface between C and ModelSim for exported and imported tasks and functions Though the dpiheader h is a user convenience file rather than a requirement including dpiheader h in your C code c
13. Compiling Verilog Files The first time you compile a design there is a two step process 1 Create a working library with vlib or select File gt New gt Library 2 Compile the design using vlog or select Compile Compile ModelSim User s Manual v6 3g 169 May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files Creating a Working Library Before you can compile your design you must create a library in which to store the compilation results Use the vlib command or select File gt New gt Library to create a new library For example vlib work This creates a library named work By default compilation results are stored in the work library The work library is actually a subdirectory named work This subdirectory contains a special file named info Do not create libraries using UNIX commands always use the vlib command See Design Libraries for additional information on working with libraries Invoking the Verilog Compiler The Verilog compiler vlog compiles Verilog source code into retargetable executable code The library format is compatible across all supported platforms and you can simulate your design on any platform without having to recompile your design As the design compiles the resulting object code for modules and UDPs is generated into a library As noted above the compiler places results into the work library by default You can specify an alternate library with the work argume
14. timescale 1 ns 1 ns module testbench initial begin signal force testbench uut blkl reset 1 0 3 1 signal force testbench uut blkl reset 0 40 3 200000 1 end endmodule signal force Example This example forces reset to a 1 from time 0 ns to 40 ns At 40 ns reset is forced to a 0 2 ms after the second signal force call was executed If you want to skip parameters so that you can specify subsequent parameters you need to use the keyword open as a placeholder for the skipped parameter s The first signal force ModelSim User s Manual v6 3g 309 May 2008 Signal Spy signal_force procedure illustrates this where an open for the cancel_period parameter means that the default value of 1 ms is used 310 library IEEE modelsim_lib use IEEE std logic 1164 a11 use modelsim lib util all entity testbench is end architecture only of testbench is begin force process process begin signal force testbench uut blkl reset 1 signal force testbench uut blkl reset 0 1 wait end process force process end 0 ns freeze open 1 40 ns freeze 2 ms ModelSim User s Manual v6 3g May 2008 Signal Spy signal_release signal_release This reference section describes the following e VHDL Procedure signal_release e Verilog Task signal_release e SystemC Function signal_release The signal_release call releases any fo
15. RR RRRRRRRR IRR 51 Tist WOW icici estes segue ae e et et e aed e sll See a uk Bid ql o s a ed bee o Use 53 ModelSim User s Manual v6 3g 3 May 2008 Table of Contents Displaying the List WIndOW 22 s 2seerede2kees a PE E ARR REF CRI ERES REE AES 23 Viewing Data in the List Window lt i cc0x2 5keoeeceg endothe dks Sones E OEEA MS 53 GUT Elements of the List WIndOW icisuessececece e ER nearne 54 Locals Widow ox 22014 Ex IRR E REReCS QU Enne Ed pul a EDB EE 56 Displaying the Locals Window Li 2sueseskieterue e e eR ERR ERU EEC REG heaves aie 56 Viewing Data m the Locals Window i44ssaedxecRRES EE E AXE eX Rae er E XH 56 GUI Elements of the Locals Window casae RR RR hn 57 Memory PANGS C 58 Associative Arrays in Verilog SystemVerilog 0 cece 59 Viewing Single and Multidimensional Memories 0000 c eee eee eee 59 Viewing Packed Arrays i22ces pa DRE RR EG Rac Ex da REA E as ER Ado ERE 60 Viewing Memory CODents osc ed rh ener dea E RERO ei dee obs aneendecider enc 60 Saving Memory Formats ina DO File llle 61 Direct Address Navigation e idis cRERFI RR RRPERT Mee bene eee SEES Sees SEES 61 Splitting the Memory Contents Pane 22 cos esos ens bees RR ERE eek RR ee es 61 Objects PANG renren peser nea eben EACH OS RE UP IC de RCM eee PEL 62 Filt ring the Objects Lists sedens esineen PUE RERUM K a REEL DERE 62 Filtering by INAHmie 62 008 sous RGu KRE FK ERETRI REX RR E quies Dax PR RC R UR RE 62 Filt ring
16. Search for Signal Value Value FAIL C Search for Expression Expression Builder Search Options Search Forward 1 Match Count Search Reverse Stop Search Search Results Status Doe Time One option of note is Search for Expression The expression can involve more than one signal but is limited to signals currently in the window Expressions can include constants variables and DO files See Expression Syntax for more information Using the Expression Builder for Expression Searches The Expression Builder is a feature of the Wave and List Signal Search dialog boxes and the List trigger properties dialog box You can use it to create a search expression that follows the GUI expression format To display the Expression Builder dialog box do the following 1 Choose Edit gt Signal Search from the main menu This displays the Wave Signal Search dialog box 2 Select Search for Expression 3 Click the Builder button This displays the Expression Builder dialog box shown in Figure 9 18 248 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Searching in the Wave and List Windows Figure 9 18 Expression Builder Dialog Box Expression Builder Expression Builder Insert Signal event rising falling AND oR o 1 xw su x z lt E su sa nja 7 Gear Save Test __OK_ Cancel You click the buttons
17. These commands behave as follows e TraceX TraceX Delay TraceX steps back to the last driver of an X value TraceX Delay works similarly but it steps back in time to the last driver of an X value TraceX should be used for RTL designs TraceX Delay should be used for gate level netlists with back annotated delays e ChaseX ChaseX Delay ChaseX jumps through a design from output to input following X values ChaseX Delay acts the same as ChaseX but also moves backwards in time to the point where the output value transitions to X ChaseX should be used for RTL designs ChaseX Delay should be used for gate level netlists with back annotated delays Finding Objects by Name in the Dataflow Window Select Edit gt Find from the menu bar or click the Find icon in the toolbar to search for signal net or register names or an instance of a component This opens the Find in Dataflow dialog Figure 10 6 Figure 10 6 Find in Dataflow Dialog Findin Dataflow NAM 6 Find Find Type Find Next Any Exact Instance Match case Find All C Signal Zoom to Close With the Find in Dataflow dialog you can limit the search by type to instances or signals You select Exact to find an item that exactly matches the entry you ve typed in the Find field The Match case selection will enforce case sensitive matching of your entry And the Zoom to selection will zoom in to the item in the Find field The Fi
18. llle 190 Negative Timing Check Limits sius essc su acta segdneek sae REEREEERPE MEER oe 192 Verilog XL Compatible Simulator Arguments 0 0 0 0 eee eee eee 201 Using Escaped RIentlHiets unus eR er er t Rack PER 4484 see es Ea PER ES RN RE 201 Cell LIDFafIBS xa due hex spe EXU E AH REC ee Zee VI PES qa Keep e Edd eique ees 202 SDF Timing Annotation is uses dub AR EATER PEE RENE aREEA AE PEE Pp RS 203 Delay MOGES PT PP r C M 203 System asks and Functions os nasce ek rs ood see RR eee es EORR AC ae o s COR 204 IEEE Std 1364 System Tasks and Functions 0 0 ee eee eee eee ee 204 SystemVerilog System Tasks and Functions 0 0 c eee eee eee eee 207 System Tasks and Functions Specific to the Tool 20 0 cece eee eee 208 Verilog XL Compatible System Tasks and Functions 0 0000 eese 212 Compiler Diteclives sse 2d ogee oeaGa be Geeee deeds OEE KR CR EWE DEE ORME ORS 215 IEEE Std 1364 Compiler Direcvives o4 24d x hax FPEM RYE eeaee G4 EAR ESSERE 215 Verilog XL Compatible Compiler Directives 0 0 cece eee eee eee 216 Verilog PLI VPI and SystemVerilog DPI 0 0 eee eee eee eee 217 Chapter 8 Recording Simulation Results With Datasets ccc cece cece e cree eee eee 219 Saving a Simulation to a WLF File 1 2 0 eee eee 220 WLP File Parameter OVerview s Lis dels p exe x y sake P ERG x RE ER REC E RE 221 Limiting the WLF
19. location map file used by ModelSim tools to find source files based on easily reallocated soft paths default file name is mgc location map pref tcl contains defaults for fonts colors prompts window positions and other simulator window characteristics modelsim UNIX or contains last working directory project file printer Windows registry defaults and other user customized GUI characteristics modelsim tcl contains user customized settings for fonts colors prompts other GUI characteristics maintained for backwards compatibility with older versions see The modelsim tcl File lt project_name gt mpf if available loads last project file which is specified in the registry Windows or HOME modelsim UNIX see What are Projects for details on project settings ModelSim User s Manual v6 3g 467 May 2008 System Initialization Environment Variables Accessed During Startup Environment Variables Accessed During Startup The table below describes the environment variables that are read during startup They are listed in the order in which they are accessed For more information on environment variables see Environment Variables Table F 2 Environment Variables Accessed During Startup Environment variable MODEL_TECH Purpose set by ModelSim to the directory in which the binary executables reside e g modeltech lt platform gt MODEL_TECH_OVERRIDE provides an alternative director
20. top top sigl1 0 lseif enable sig 0 disable signal spy top uut instl sigl1 top top sigl 0 end if end process spy enable disable end init signal spy Example In this example the value of top uut inst1 sig is mirrored onto top top_sig A message is issued to the transcript The ability to control the mirroring of values is turned on and the init signal spy is initially enabled The mirroring of values will be disabled when enable reg transitions to a 0 and enabled when enable reg transitions to a l module top reg top sigl reg enable reg initial begin S init signal spy top uut instl sigl top top sig1 1 1 end always posedg nable_reg begin Senable signal spy top uut instl sigl top top sig1 0 end ModelSim User s Manual v6 3g 305 May 2008 Signal Spy init_signal_spy always negedg nable_reg begin Sdisable_signal_spy top uut instl sigl top top_sig1 0 end endmodule 306 ModelSim User s Manual v6 3g May 2008 Signal Spy signal_force signal_ force This reference section describes the following e VHDL Procedure signal_force e Verilog Task signal_force e SystemC Function signal_force The signal_force call forces the value specified onto an existing VHDL signal Verilog register or net or SystemC signal called the dest_object This allows you to force signals registers or nets at any level of the des
21. vcd off filename fdumpoff vcd on filename fdumpon Using VCD Commands with SystemC VCD commands are supported for the following SystemC signals sc_signal lt T gt sc_signal_resolved sc_signal_rv lt N gt VCD commands are supported for the following SystemC signal ports 334 ModelSim User s Manual v6 3g May 2008 sc_in lt T gt sc_out lt T gt sc_inout lt T gt sc_in_resolved sc_out_resolved sc_inout_resolved sc in rv N sc out rv N sc inout rv N T can be any of types shown in Table 13 4 Value Change Dump VCD Files VCD File from Source To Output Table 13 4 SystemC Types unsigned char sc int unsigned short sc uint unsigned int unsigned long float sc bigint sc biguint unsigned long long double sc signed enum sc unsigned sc logic sc bit sc bv Unsupported types are the SystemC fixed point types class structures and unions Compressing Files with VCD Tasks ModelSim can produce compressed VCD files using the gzip compression algorithm Since we cannot change the syntax of the system tasks we act on the extension of the output file name If you specify a gz extension on the filename ModelSim will compress the output VCD File from Source To Output The following example shows the VHDL source a set of simulator commands and the resulting VCD output ModelSim User s Manual v6 3g
22. 0 data in lt to unsigned 7 i data in length addr lt to unsigned 1 i addr length inaddr lt to unsigned 1 i inaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 data in lt to unsigned 3 data_in length addr lt to unsigned 2 i addr length inaddr lt to unsigned 2 i inaddr lengtnh WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 data in lt to unsigned 30330 data in length addr lt to unsigned 3 i addr length inaddr lt to unsigned 3 i inaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 we lt 0 addr lt to_unsigned i addr length outaddr lt to_unsigned i outaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 addr lt to unsigned 1 i addr length outaddr lt to unsigned 1 i outaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 addr lt to unsigned 2 i addr length outaddr to unsigned 2 i outaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk 0 addr lt to_unsigned 3 i addr lengtnh outaddr lt to unsigned 3 i outaddr length WAIT UNTIL clk EVENT AND clk 0O WAIT UNTIL clk EVENT AND clk 0 END LOOP ASSERT false REPORT End of Simulation ModelSim User s Manual v6 3g May 2008 VHDL Simulation Affecting Performance by Ca
23. May 2008 Error and Warning Messages Miscellaneous Messages Table B 2 Exit Codes Exit code Description 101 GUI Tk initialization failure 102 GUI IncrTk initialization failure X11 display error Interrupt SIGINT Illegal instruction SIGILL Trace trap SIGTRAP Abort SIGABRT Floating point exception SIGFPE Bus error SIGBUS Segmentation violation SIGSEGV Write on a pipe with no reader SIGPIPE Alarm clock SIGALRM Software termination signal from kill SIGTERM User defined signal 1 SIGUSR1 User defined signal 2 SIGUSR2 Child status change SIGCHLD Exceeded CPU limit SIGXCPU Exceeded file size limit SIGXFSZ Miscellaneous Messages This section describes miscellaneous messages which may be associated with ModelSim Compilation of DPI Export TFs Error Fatal vsim 3740 Can t locate a C compiler for compilation of DPI export tasks functions e Description ModelSim was unable to locate a C compiler to compile the DPI exported tasks or functions in your design e Suggested Action Make sure that a C compiler is visible from where you are running the simulation ModelSim User s Manual v6 3g 411 May 2008 Error and Warning Messages Miscellaneous Messages Empty port name warning WARNING 8 lt path file_name gt empty port name in port list Description ModelSim reports these warnings if you use the lint
24. ModelSim User s Manual Software Version 6 3g May 2008 1991 2008 Mentor Graphics Corporation All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT
25. Two processes writing to the same variable at the same time e READ WRITE One process reading a variable at the same time it is being written to by another process ModelSim calls this a READ WRITE hazard if it executed the read first e WRITE READ Same as a READ WRITE hazard except that ModelSim executed the write first vsim issues an error message when it detects a hazard The message pinpoints the variable and the two processes involved You can have the simulator break on the statement where the hazard is detected by setting the break on assertion level to Error To enable hazard detection you must invoke vlog with the hazards argument when you compile your source code and you must also invoke vsim with the hazards argument when you simulate Note Enabling hazards implicitly enables the compat argument As a result using this argument may affect your simulation results Hazard Detection and Optimization Levels In certain cases hazard detection results are affected by the optimization level used in the simulation Some optimizations change the read write operations performed on a variable if the transformation is determined to yield equivalent results Since the hazard detection algorithm doesn t know whether or not the read write operations can affect the simulation results the optimizations can result in different hazard detection results Generally the optimizations reduce the number of false hazards by eliminat
26. Veriuser pliapp1 so pliapp2 so pliappn so e Asa list in the PLIOBJS environment variable setenv PLIOBJS pliapp1 so pliapp2 so pliappn so e Asa pli argument to the simulator multiple arguments are allowed pli pliapp1 so pli pliapp2 so pli pliappn so The various methods of specifying PLI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases 420 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Registering VPI Applications Registering VPI Applications Each VPI application must register its system tasks and functions and its callbacks with the simulator To accomplish this one or more user created registration routines must be called at simulation startup Each registration routine should make one or more calls to vpi_register_systf to register user defined system tasks and functions and vpi_register_cb to register callbacks The registration routines must be placed in a table named vlog_startup_routines so that the simulator can find them The table must be terminated with a 0 entry Example C 1 VPI Application Registration PLI_INT32 MyFuncCalltf PLI_BYTE8 user_data PLI_INT32 MyFuncCompiletf PLI_BYTE8 user_data PLI_INT32 MyFuncSizetf PLI_BYTE8 user_data z PLI INT32 MyEndOfCompCB p cb data cb data p PLI INT32 MyStartOfSimCB p cb data cb data
27. Zoom Mouse Mode Zoom Mode The left mouse button then offers 3 zoom options by clicking and dragging in different directions e Down Right or Down Left Zoom Area In Up Right Zoom Out e Up Left Zoom Fit Also note the following about zooming with the mouse e The zoom amount is displayed at the mouse cursor A zoom operation must be more than 10 pixels to activate e You can enter zoom mode temporarily by holding the lt Ctrl gt key down while in select mode e With the mouse in the Select Mode the middle mouse button will perform the above Zoom operations Saving Zoom Range and Scroll Position with Bookmarks Bookmarks save a particular zoom range and scroll position This lets you return easily to a specific view later You save the bookmark with a name and then access the named bookmark from the Bookmark menu Bookmarks are saved in the Wave format file see Adding Objects with a Window Format File and are restored when the format file is read ModelSim User s Manual v6 3g 245 May 2008 Waveform Analysis Zooming the Wave Window Display Managing Bookmarks The table below summarizes actions you can take with bookmarks Add bookmark Table 9 4 Actions for Bookmarks Menu commands Wave window docked Add gt Wave gt Bookmark Menu commands Wave window undocked Add gt Bookmark Command bookmark add wave View bookmark Wave gt Bookmarks gt lt bookmark_name gt View
28. ftest sm dat delta est sm outof ftest sm addr ftest sm clk ftest sm out wire 680000 0 0 205 0 0 206 z 50 690000 0 0 zos ol 206 z 50 691000 1 0 zos ol 206 z 51 691000 2 0 zos ol 206 206 51 695000 0 80 206 0 1 206 206 51 700000 0380 206 00 206 206 1 709000 1380 206 0 0 206 207 51 710000 0 80 206 0 1 206 207 51 711000 1 80 206 0 1 206 207 51 711000 2 80 206 0 1 206 z 51 715000 0 0 206 0 1 206 z 51 164 lines In addition to the List Signal Properties dialog box you can also change the radix e Change the default radix for the current simulation using Simulate gt Runtime Options Main window e Change the default radix for the current simulation using the radix command e Change the default radix permanently by editing the DefaultRadix variable in the modelsim ini file Saving the Window Format By default all Wave and List window information is forgotten once you close the windows If you want to restore the windows to a previously configured layout you must save a window format file Follow these steps 1 Add the objects you want to the Wave or List window 2 Edit and format the objects to create the view you want 3 Save the format to a file by selecting File gt Save gt Format To use the format file start with a blank Wave or List window and run the DO file in one of two ways e Invoke the do command from the command line VSIM gt do lt my_format_file gt Mod
29. 00110100 00111010 01000000 01000110 01001100 01010010 00101001 00101111 00110101 00111011 01000001 01000111 01001101 01010011 00101001 00101111 00110101 00111011 01000001 01000111 01001101 01010011 00101010 00110000 00110110 00111100 01000010 01001000 01001110 01010100 00101010 00110000 00110110 00111100 01000010 01001000 01001110 01010100 00101011 00110001 00110111 00111101 01000011 01001001 01001111 01010101 00101011 00110001 00110111 00111101 01000011 01001001 01001111 01010101 00101100 00110010 00111000 00111110 01000100 01001010 01010000 01010110 00101100 00110010 00111000 00111110 01000100 01001010 01010000 01010110 00101101 00110011 00111001 00111111 01000101 01001011 01010001 01010111 00101101 00110011 00111001 00111111 01000101 01001011 01010001 01010111 ModelSim User s Manual v6 3g May 2008 61 Graphical User Interface Objects Pane Objects Pane The Objects pane shows the names and current values of declared data objects in the current region selected in the structure tabs of the Workspace Data objects include signals nets registers constants and variables not declared in a process generics parameters Clicking an entry in the window highlights that object in the Dataflow and Wave windows Double clicking an entry highlights that object in a Source editor window opening a Source editor window if one is no
30. 4 bl amp amp i lt 7 28 begin 29 increment i val i carry 30 carry val i amp carry 31 end 32 end 23 endfunction 34 35 gt always B posedge clk or posedge reset 36 if reset 37 count tpd_reset_to count S8 h00 38 else 39 count lt tpd clk to count increment count an JT Ih counter v The breakpoints are toggles Click the left mouse button on the red breakpoint marker to disable the breakpoint A disabled breakpoint will appear as a black ball Click the marker again to enable it Right click the breakpoint marker to open a context menu that allows you to Enable Disable Remove or Edit the breakpoint create the colored diamond click again to disable or enable the breakpoint 272 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Creating and Managing Breakpoints Modifying a File Line Breakpoint You can modify a file line breakpoint by selecting Tools gt Breakpoints from the Main menus This will open the Modify Breakpoints dialog Figure 9 35 which displays a list of all breakpoints in the design When you select a file line breakpoint from the list and click the Modify button the File Breakpoint dialog Figure 9 38 opens allowing you to modify the breakpoint Figure 9 38 File Breakpoint Dialog Box File Breakpoint x File C Tutorialfexamples tutorials verilog Browse Line Instance Name 36 Condition Breakpoint Commands
31. ABCDEFGH I signal breakpoints edit 270 signal groups in wave window 256 Signal Segmentation Violations debugging 190 Signal Spy 156 303 disable 295 enable 297 signal_force 307 signal_force 156 307 signal_release 311 signal_release 156 311 signals combining into a user defined bus 263 Dataflow window displaying in 50 275 driving in the hierarchy 299 filtering in the Objects window 62 hierarchy driving in 299 referencing in 156 303 releasing anywhere in 311 releasing in 156 311 sampling at a clock change 268 transitions searching for 244 types selecting which to view 62 values of displaying in Objects window 62 forcing anywhere in the hierarchy 156 307 saving as binary log file 219 virtual 230 waveforms viewing 84 SIGSEGV fatal error message 191 SIGSEGV error 190 simulating batch mode 29 command line mode 29 comparing simulations 219 default run length 396 iteration limit 396 saving dataflow display as a Postscript file 287 saving options in a project 121 486 JKLMNOPQRSTUVWX YZ saving simulations 219 saving waveform as a Postscript file 262 Verilog 182 delay modes 203 hazard detection 189 resolution limit 182 XL compatible simulator options 201 VHDL 144 viewing results in List pane 53 viewing results in List window 237 VITAL packages 154 simulating the design overview 28 simulation basic steps for 25 Simulation Configuration creating 121 simul
32. Also allows constant propagation and VHDL subprogram inlining e 4 Allows all optimizations in 2 and 3 and allows optimizations that may remove major regions of code by changing assignments to built ins or removing unused signals It also changes Verilog gates to continuous assignments Allows VHDL subprogram inlining e Default 3 DatasetSeparator This variable specifies the dataset separator for fully rooted contexts for example sim top The argument to DatasetSeparator must not be the same character as PathSeparator e Value Range any character except those with special meaning such as V etc e Default DefaultForceKind This variable defines the kind of force used when not otherwise specified e Value Range freeze drive or deposit e Default drive for resolved signals freeze for unresolved signals 382 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables DefaultRadix This variable specifies a numeric radix may be specified as a name or number For example you can specify binary as binary or 2 or octal as octal or 8 e Value Range symbolic binary octal decimal unsigned hexadecimal ascii e Default symbolic DefaultRestartOptions This variable sets the default behavior for the restart command e Value Range one or more of force noassertions nobreakpoint nofcovers nolist nolog nowave e Default commented out
33. Deleting or Ungrouping a Wave Group If a wave group is selected and cut or deleted the entire group and all its contents will be removed from the Wave window Likewise the delete wave command will remove the entire group if the group name is specified If a wave group is selected and the Wave Ungroup menu item is selected the group will be removed and all of its contents will remain in the Wave window in existing order Adding Items to an Existing Wave Group There are three ways to add items to an existing wave group Using the drag and drop capability to move items outside of the group or from other windows within ModelSim into the group The insertion indicator will show the position the item will be dropped into the group If the cursor is moved over the lower portion of the group item name a box will be drawn around the group name indicating the item will be dropped into the last position in the group 2 The cut copy paste functions may be used to paste items into a group 3 Use the add wave group command The following example adds two more signals to an existing group called mygroup add wave group mygroup sig4 sig5 Removing Items from an Existing Wave Group You can use any of the following methods to remove an item from a wave group Use the drag and drop capability to move an item outside of the group 2 Use menu or icon selections to cut or delete an item or items from the group 3 Use the delete wave comma
34. HA sv_std Library MODE H vital2000 Library MODE f ieee Library MODE i modelsim_lib Library MODE H std Library MODE i std_developerskit Library MODE i synopsys Library MODE H veros Library MODE a n Library EE ModelSim User s Manual v6 3g 459 May 2008 Setting GUI Preferences Navigating the Graphic User Interface Moving Panes When you see a double bar at the top edge of a pane it means you can modify the pane position Figure E 3 GUI Double Bar Workspace 3 a H of Click and drag the pane handle in the middle of a double bar your mouse pointer will change to a four headed arrow when it is in the correct location to reposition the pane inside the parent window As you move the mouse to various parts of the main window a gray outline will show you valid locations to drop the pane Or drag the pane outside of the parent window and when you let go of the mouse button the pane becomes a free floating window Docking and Undocking Panes You can undock a pane by clicking the undock button in the heading of a pane Figure E 4 GUI Undock Button gi To redock a floating pane click on the pane handle at the top of the window and drag it back into the parent window or click the dock icon Figure E 5 GUI Dock Button i You can expand panes to fill the entire Main window by clicking the zoom icon in the heading of the pane Zooming Pane
35. List Window Keyboard Shortcuts Key UNIX and Windows Left Arrow Action scroll listing left selects and highlights the item to the left of the currently selected item Right Arrow scroll listing right selects and highlights the item to the right of the currently selected item Up Arrow scroll listing up Down Arrow scroll listing down Page Up Ctrl Up Arrow Page Down Ctrl Down Arrow scroll listing up by page scroll listing down by page Tab Shift Tab searches forward down to the next transition on the selected signal searches backward up to the previous transition on the selected signal Shift Left Arrow Shift Right Arrow Ctrl f Windows Ctrl s UNIX ModelSim User s Manual v6 3g May 2008 extends selection left right opens the Find dialog box to find the specified item label within the list display 453 Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts The following mouse actions and keystrokes can be used in the Wave window Table D 5 Wave Window Mouse Shortcuts Mouse action Result Ctrl Click left mouse button zoom area in and drag Ctrl Click left mouse button and drag zoom out and drag Ctrl Click left mouse button M zoom fit Click left mouse button and drag moves closest cursor Ctrl Click left mouse button on a scrolls window t
36. SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 Telephone 503 685 7000 Toll Free Telephone 800 592 2210 Website www mentor com TRADEMARKS The trademarks logos and service marks Marks used herein are the property of Mentor Graphics Corporation or other third parties No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third party owner The use herein of a third party Mark is not an attempt to indicate Mentor Graphics as a source of a product but is intended to indicate a product from or associat
37. Tcl and Macros DO Files Macros DO Files Example 14 7 Tcl Used to Specify Compiler Arguments set Files list set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x set lappend Files 1 shift eval vcom 93 explicit noaccel Files Example 14 8 is an enhanced version of the last one The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type Note that the macro assumes your VHDL files have a vhd file extension Example 14 8 Tcl Used to Specify Compiler Arguments Enhanced set vhdFiles list set vFiles list set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x if string match vhd 1 lappend vhdFiles 1 else lappend vFiles 1 shift if llength vhdFiles gt 0 eval vcom 93 explicit noaccel vhdFiles if llength S vFiles gt 0 eval vlog vFiles Macros DO Files ModelSim macros also called DO files are simply scripts that contain ModelSim and optionally Tcl commands You invoke these scripts with the Tools TCL Execute Macro menu selection or the do command Creating DO Files You can create DO files like any other Tcl script by typing the required commands in any editor and saving the file Alternatively you can save the transcript as a DO file see Saving the Transcript File All event watching commands e g onbreak onerror etc mu
38. The new operator performs three distinct operations 1 it allocates storage for an object of type C 2 itcalls the new method in the class or uses a default method if the class doesn t define new and 3 it assigns the handle of the newly constructed object to obj If the object handle obj is not initialized with new there will be nothing to reference The variable will be set to the value null and the SIGSEGV fatal error will occur To debug a SIGSEGV error first look in the transcript Figure 7 1 shows an example of a SIGSEGV error message in the Transcript pane 190 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Figure 7 1 Fatal Signal Segmentation Violation SIGSEGV Loading work top VSIM 11 gt run all Fatal SIGSEGY Bad pointer access Time Ons Iteration 0 Process top INITIAL 19 File C Tutorial SIGSEGY example top sy t Fatal error in Module top at C Tutorial SIGSEGY example top sv line 19 Filename and line number ToM see where SIGSEGY occurred fA Transcript al gt The Fatal error message identifies the filename and line number where the code violation occurred in this example the file is top sv and the line number is 38 ModelSim sets the active scope to the location where the error occurred In the Active Processes window the current process is highlighted Figure 7 2 Figure 7 2 Curren
39. Waveform Analysis Combining Objects into Buses O 0 a X b X cin U sum X cout U Q0 1 a 0 b 1 cin 0 e TSSI writes a file in standard TSSI format see also the write tssi command 00000000000000010000000010 0 2 3 00000000000000010 010 4 100 00000001000000010000000010 You can also save List window output using the write list command Combining Objects into Buses You can combine signals in the Wave or List window into buses A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value A virtual compare signal the result of a comparison simulation is not supported for combination with any other signal To combine signals into a bus use one of the following methods e Select two or more signals in the Wave or List window and then choose Tools gt Combine Signals from the menu bar A virtual signal that is the result of a comparison simulation is not supported for combining with any other signal e Use the virtual signal command at the Main window command prompt In the illustration below three signals have been combined to form a new bus called Bus1 Note that the component signals are listed in the order in which they were selected in the Wave window Also note that the value of the bus is made up of the values of its component signals arranged in a specific order ModelSim User s Manual v6 3g 263 May 2008 Waveform Analysis Co
40. cell define module dff q d clear preset clock output q input d clear preset clock reg q pragma protect data method aes128 cbc pragma protect author IP Provider author info Widget 5 v3 2 pragma protect key keyown r MTI key method rsa pragma protect key_keynam pragma protect begin include diff v include prim v include top v pragma protect end always posedge clock q d endmodule ndcelldefin MGC DVT MTI In both examples the code to be encrypted follows the pragma protect begin expression and ends with the pragma protect end expression In Example 3 2 the entire contents of diff v prim v and top v will be encrypted 106 ModelSim User s Manual v6 3g May 2008 Protecting Your Source Code Creating an Encryption Envelope Protect Pragma Expressions The protection envelope contains a number of pragma protect expressions The following pragma protect expressions are expected when creating an encryption envelope e data method defines the encryption algorithm that will be used to encrypt the designated source text ModelSim the following encryption algorithms des cbc 3des cbc aes128 cbc aes256 cbc blowfish cbc cast128 cbc and rsa e key keyowner designates the owner of the encryption key key keyname specifies the keyowner s key name key method specifies an encryption algorit
41. e VHDL objects signals aliases generics constants and variables e Verilog objects nets registers variables named events and module parameters e Virtual objects virtual signals and virtual functions The address of an object if one can be obtained is displayed in the title in parentheses as shown in Figure 2 32 Items displayed in red are values that have changed during the previous Run command You can change the radix of displayed values by selecting an item right clicking to open a popup context menu then selecting Properties Figure 2 32 Watch Pane ipi xi File Edit View Add Tools Window Iram tb dprami mem 0x7e778820 0 00111000 1 00111001 2 00111010 3 00011001 4 00000011 5 2 01111010 6 00101110 7 00101111 8 00110000 9 00110001 10 00110010 11 00110011 12 00110100 13 00110101 14 00110110 Iram tb outaddr 0x7e773018 0100 15 00110111 Items are displayed in a scrollable hierarchical list such as in Figure 2 33 where extended SystemVerilog classes hierarchically display their super members ModelSim User s Manual v6 3g 81 May 2008 Graphical User Interface Watch Pane Figure 2 33 Scrollable Hierarchical Display 215 x File Edit view Add Tools Window Itop scorebd af 0x7e8b1290 ftop stim request_Fifo 0x7e8b0710 super super Javm pkg avm named super avm
42. e pathname with an environment variable a Tip A softname is a term for a pathname that uses location mapping with MGC LOCATION MAP The soft pathname looks like a pathname containing an environment variable it locates the source using the location map rather than the environment To convert the pathname to a softname for projects using location mapping follow these steps 1 Right click anywhere within the Project tab and select Project Settings 2 Enable the Convert pathnames to softnames within the Location map area of the Project Settings dialog box Figure 4 19 ModelSim User s Manual v6 3g 127 May 2008 Projects Accessing Projects from the Command Line Once enabled all pathnames currently in the project and any that are added later are then converted to softnames During conversion if there is no softname in the mgc location map matching the entry the pathname is converted in to a full hardened pathname A pathname is hardened by removing the environment variable or the relative portion of the path If this happens any existing pathnames that are either relative or use environment variables are also changed either to softnames if possible or to hardened pathnames if not For more information on location mapping and pathnames see Using Location Mapping Accessing Projects from the Command Line Generally projects are used from within the ModelSim GUI However standalone tools will use the project file if they ar
43. file logical name must be a string expression In newer versions of the 1076 spec syntax for a file declaration is file identifier list subtype indication file open information where file open information is open file open kind expression is file logical name You can specify a full or relative path as the file logical name for example VHDL 87 Normally if a file is declared within an architecture process or package the file is opened when you start the simulator and is closed when you exit from it If a file is declared in a subprogram the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram Alternatively the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim ini file Also the number of concurrently ModelSim User s Manual v6 3g 149 May 2008 VHDL Simulation TextlO Implementation Issues open files can be controlled by the ConcurrentFileLimit variable These variables help you manage a large number of files during simulation See Simulator Variables for more details Using STD INPUT and STD OUTPUT Within the Tool The standard VHDL 87 TextIO package contains the following file declarations file input TEXT is in STD INPUT file output TEXT is out STD OUTPUT Updated versions of the TextIO package contain these file declarations file input TEXT open read mode is STD INPUT file
44. gt Bookmarks gt lt bookmark_name gt bookmark goto wave Delete bookmark Wave gt Bookmarks gt Bookmarks gt lt select bookmark then Delete gt Adding Bookmarks To add a bookmark follow these steps View gt Bookmarks gt Bookmarks gt lt select bookmark then Delete gt bookmark delete wave 1 Zoom the Wave window as you see fit using one of the techniques discussed in Zooming the Wave Window Display 2 Ifthe Wave window is docked select Add gt Wave gt Bookmark If the Wave window is undocked select Add gt Bookmark Figure 9 15 Bookmark Properties Dialog Bookmark Properties wave 3 Bookmark Name bookmark m Zoom Range o ns to 315 ns Top Index r v Save zoom range with bookmark Ok Cancel 3 Give the bookmark a name and click OK 246 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Searching in the Wave and List Windows Editing Bookmarks Once a bookmark exists you can change its properties by selecting Wave gt Bookmarks gt Bookmarks if the Wave window is docked or by selecting Tools gt Bookmarks if the Wave window is undocked Searching in the Wave and List Windows The Wave and List windows provide two methods for locating objects e Finding signal names Select Edit gt Find or use the find command to search for the name of a signal e Search for values or transitions Select Edit
45. iu oeder cadre bRES HERR E EE a aa i aa LERRA RR cH ER RS d 139 Creating a Design Library for VHDL lees 139 Invoking the VHDL Compiler 55 22932532 ep wue RE ES e PETERS DEAS Fue PX E 140 Dependency Checking c uas xag ap EdE a se SERES E CEST SERES es 140 Range and Index Checking 2 iseaxkieiderntetideesse cider BER Faq ER PE P qM 140 Subprogram Inline usos ates px e Qa eer eu RENTE E RU d pud exei ei 140 Differences Between Language Versions 141 Simulating VHDL Designs sid 2di44de2cessee hese eres aneekee RR ENERGIE REG ds 144 Simulator Resolution Lamit VHDL 2 2 zu etebeskRete3 sa dds R44 RR KR ace n 144 Defa ult sni PEPPER 145 Delta Delays uis eec Ee tiag e ERA T EUR DER DU ERE ES QE DEEP quU eed essed 146 Using the lex PScRIBP i 2 d5s2su 3o ES EIyadx D MERI EE ERE PXERE PERS SUE REY 149 Syntax for File Declaration 2 20ah cedatecasayetanees RE E xu RR Ede x Rs 149 Using STD INPUT and STD OUTPUT Within the Tool 150 TextIO Implementation ISSues 24 uer REX ERR RE RE RE RR Rx IRR RES 150 Writing Strings and Agesregates isescrur dee RE RE PA ERE xg EGRE E E EA ae 150 Reading and Writing Hexadecimal Numbers llleleeeleeeeeeeeeen 151 Dangling Poulter 2o2 xot e3 e QUERIES nre raa CQ AT CADRE RS Rad URP D RAP quads 151 The ENDLINE Function 0 audien erm nih ed REN TU ra ra Rar Ex ae ER 152 The ENDFILE BUnchOn 22 252 ckeeeedeleeeen SSeS Ree See eee E E e eee RE RES 152 Using Alter
46. memory process cs variable address natural begin if rising edge cs then address sulv to natural add in if mwrite 1 then ram address data in end if data out lt ram address end if end process memory illustrates a second process using the shared variable initialize process do init variable address natural begin if rising edge do init then for address in 0 to nwords 1 loop ram address data in end loop end if end process initialize end architecture style 93 architecture style 87 of memory is begin memory process cs variable ram ram type variable address natural 160 ModelSim User s Manual v6 3g May 2008 begin if rising_edge cs then address sulv to natural add in if mwrite 1 then ram address data in end if data out lt ram address end if end process end style 87 architecture bad style 87 of memory is Signal ram ram type begin memory process cs variable address natural 0 begin if rising edge cs then address sulv to natural add in if mwrite 1 then ram address lt data in data out data in else data out lt ram address end if end if end process end bad style 87 VHDL Simulation Modeling Memory library ieee use ieee std logic 1164 all package conversions is function sulv to natural x std ulogic vector natural function natural
47. none warning This variable changes the severity of the listed message numbers to warning Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default none msgmode This variable controls where the simulator outputs elaboration and runtime messages Refer to the section Message Viewer Tab for more information e Value Range tran transcript only wlf wlf file only both e Default both displaymsgmode This variable controls where the simulator outputs system task messages Refer to the section Message Viewer Tab for more information and vsim for information about displaymsgmode The display system tasks displayed with this functionality include display strobe monitor write as well as the analogous file I O tasks that write to STDOUT such as fwrite or fdisplay e Value Range tran transcript only wlf wlf file only both e Default tran Commonly Used INI Variables Several of the more commonly used modelsim ini variables are further explained below ModelSim User s Manual v6 3g 399 May 2008 Simulator Variables Simulator Control Variables Common Environment Variables You can use environment variables in your initialization files Use a dollar sign before the environment variable name For example Library work SHOME work_lib test lib STESTNUM work vsim IgnoreNote SIGNORE_ASSERTS IgnoreWarning SIGNORE_ASS
48. posedge clk 0 SETUPHOLD d posedge clk 5 5 hold posedge clk d 0 SETUPHOLD d posedge clk 5 5 setuphold posedge clk d 0 0 RECOVERY is matched to recovery Table 12 9 Matching SDF RECOVERY to Verilog SOR RN RECOVERY negedge reset posedge clk recovery negedge reset posedge clk 0 5 e REMOVAL is matched to removal Table 12 10 Matching SDF REMOVAL to Verilog pp Vg 0 REMOVAL negedge reset posedge clk removal negedge reset posedge clk 0 5 e RECREM is matched to recovery removal and recrem Table 12 11 Matching SDF RECREM to Verilog Verilog RECREM negedge reset posedge clk recovery negedge reset posedge clk 0 5 5 RECREM negedge reset posedge clk removal negedge reset posedge clk 0 5 5 RECREM negedge reset posedge clk recrem negedge reset posedge clk 0 5 5 e SKEW is matched to skew Table 12 12 Matching SDF SKEW to Verilog SKEW posedge clk1 posedge clk2 5 skew posedge clk1 posedge clk2 0 322 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation sdf_annotate e WIDTH is matched to width Table 12 13 Matching SDF WIDTH to Verilog SDF Verilog WIDTH posedge clk 5 width posedge clk 0 e PERIOD is matched to period Table 12 14 Matching SDF PERIOD to Verilog SDF Verilog PERIOD posedge clk 5 period posedge c
49. sv_std 4 vital2000 Library MODEL_TECH vital2000 i ieee Library MODEL_TECH ieee 4 modelsim lib Library MODEL TECH modelsim lib i std Library MODEL_TECH std kd aW ud dacslanarclit ihram i Ei SaaS SS eee 2 Design Unit s Resolution work test counter default Optimization Enable optimization Optimization Options OK Cancel A new tab named sim appears that shows the structure of the active simulation Figure 4 11 sts 4 11 Structure Tab of the a D c sgt Design unit type rm test counter Module counter Module 7 A increment counter Function acc full At this point you are ready to run the simulation and analyze your results You often do this by adding signals to the Wave window and running the simulation for a given period of time See the ModelSim Tutorial for examples ModelSim User s Manual v6 3g 119 May 2008 Projects The Project Tab Other Basic Project Operations Open an Existing Project If you previously exited ModelSim with a project open ModelSim automatically will open that same project upon startup You can open a different project by selecting File gt Open and choosing Project Files from the Files of type drop down Close a Project Right click in the Project tab and select Close Project This closes the Project tab but leaves the Library tab open in the workspace Note that you cannot close a project while a simulation is in progre
50. that have a delay value of zero These MIPDs are inserted in response to the v2k_int_delay argument to the vsim command In general the simulator automatically removes all zero delay MIPDs However if you have sdf_annotate calls in your design that are not getting executed the zero delay MIPDs are not removed Adding the sdf_done task after your last sdf_annotate removes any zero delay MIPDs that have been created Verilog XL Compatible System Tasks and Functions ModelSim supports a number of Verilog XL specific system tasks and functions Supported Tasks and Functions Mentioned in IEEE Std 1364 The following supported system tasks and functions though not part of the IEEE standard are described in an annex of the IEEE Std 1364 countdrivers getpattern sreadmemb sreadmemh Supported Tasks and Functions Not Described in IEEE Std 1364 The following system tasks are also provided for compatibility with Verilog XL though they are not described in the IEEE Std 1364 deposit variable value 212 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions This system task sets a Verilog register or net to the specified value variable is the register or net to be changed value is the new value for the register or net The value remains until there is a subsequent driver transaction or another deposit task for the same register or net This system task operates identi
51. this behavior will not occur This can cause designs to simulate differently and provide different results Simulator Resolution Limit VHDL The simulator internally represents time as a 64 bit integer in units equivalent to the smallest unit of simulation time also known as the simulator resolution limit The default resolution limit is set to the value specified by the Resolution variable in the modelsim ini file You can view the current resolution by invoking the report command with the simulator state option Note In Verilog this representation of time units is referred to as precision or timescale 144 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Simulating VHDL Designs Overriding the Resolution To override the default resolution of ModelSim specify a value for the t option of the vsim command line or select a different Simulator Resolution in the Simulate dialog box Available values of simulator resolution are 1 fs 10 fs 100 fs 1 ps 10 ps 100 ps ns 10 ns 100 ns us 10 us 100 us ms 10 ms 100 ms 1s 10s 100s For example the following command sets resolution to 10 ps vsim t 10ps topmod Note that you need to take care in specifying a resolution value larger than a delay value in your design delay values in that design unit are rounded to the closest multiple of the resolution In the example above a delay of 4 ps would be rounded down to 0 ps Choosing the Resolution for
52. 00000000 ZZZZZ 20 0 0 1 1 00000000 zzzzzzzzzzzzzzzz O 1 1 00000000 ZZZZZ 20 _ 1 Mo 1 1 00000000 zzzzzzzzzzzzzzzz O 1 1 00000000 22222 25 0 001 00000000 ZZZZZZZZZZzzzzzz O 1 1 00000000 IMID 216lines gt gie s Displaying the List Window e Select View gt List e Use the command view list Viewing Data in the List Window You can add information to the List window by right clicking on signals and objects in the Objects window or the Structure tab of the Workspace window and selecting Add to List You can also use the add list command ModelSim User s Manual v6 3g 53 May 2008 Graphical User Interface List Window Selecting Multiple Signals To create a larger group of signals and assign a new name to this group do the following 1 Select a group of signals o Shift click on signal columns to select a range of signals o Control click on signal columns to select a group of specific signals 2 Select List Combine Signals 3 Complete the Combine Selected Signals dialog box o Name Specify the name you want to appear as the name of the new signal o Order of Indexes Specify the order of the new signal as ascending or descending o Remove selected signals after combining Specify whether the grouped signals should remain in the List window This process creates virtual signals For more information refer to the section Virtual Signals GUI Elements of the List Window This section describes the
53. 1 wire Supscope Se Senddefinitions end 0 Sdump 0 Od 0 0 0 amp 0 0 0 O O 0 end 100 1 150 0 200 1 vars Sdumpoff x x xi x xX X amp x x x x xt X ModelSim User s Manual v6 3g May 2008 o9 i Tox 8 MO O Q9 9 Q0 Q Q OQ nd shifter mod Send clk Send reset Send data in Send 8 OrFRNWA UO I Send Send Send Send Send Send Send Send Send Value Change Dump VCD Files VCD File from Source To Output 337 Value Change Dump VCD Files VCD File from Source To Output Send 300 Sdumpon 1 Oo 1 end 500 550 600 1750 800 338 ModelSim User s Manual v6 3g May 2008 Value Change Dump VCD Files VCD to WLF 0 amp 0 0 1200 Sdumpall 1 os 0 0 amp 0 0 0 O O 0 Send VCD to WLF The ModelSim vcd2wlf command is a utility that translates a vcd file into a wif file that can be displayed in ModelSim using the vsim view argument This command only works on VCD files containing positive time values Capturing Port Driver Data Some ASIC vendors toolkits read a VCD file format that provides details on port drivers This information can be used for example to drive a tester For more information on a specific toolkit
54. 117 order changing in projects 116 properties in projects 125 range checking in VHDL 140 Verilog 170 incremental compilation 171 XL uselib compiler directive 177 XL compatible options 176 VHDL 139 140 VITAL packages 154 compiling C code gcc 430 component default binding rules 145 Compressing files VCD tasks 335 ConcurrentFileLimit ini file variable 381 configuration simulator state variable 403 configurations Verilog 180 connectivity exploring 278 Constraint algorithm negative timing checks 195 context menus Library tab 132 Convergence delay solution 195 convert real to time 157 convert time to real 156 CoverCells ini file variable 371 382 476 CoverCountAll ini file variable 381 CppOptions ini file variable sccom 380 create debug database 276 cursors adding deleting locking naming 241 link to Dataflow window 287 measuring time with 239 trace events with 281 Wave window 239 customizing via preference variables 461 D deltas explained 146 database post sim debug 276 Dataflow post sim debug database create 276 post sim debug flow 276 Dataflow window 50 275 extended mode 275 pan 290 zoom 290 see also windows Dataflow window dataflow bsm file 284 Dataset Browser 225 Dataset Snapshot 227 datasets 219 managing 225 opening 223 restrict dataset prefix display 227 view structure 224 DatasetSeparator ini file variable 382 debug database crea
55. 3 Delivering IP with protect Compiler Directives 000 101 Figure 4 1 Create Project Dialog 0 0 0 eects 113 Figure 4 2 Project Tab in Workspace Pane 20 0c eee eee ee ee nee 113 Figure 4 3 Add items to the Project Dialog 0 0 0 eee eee eee ee 114 Figure 4 4 Create Project File Dialot 2 csceruse cede ehecd dees nd cance anes ARS qe RA 115 Figure 4 5 Add file to Project Dialog 200 54 osker rre RE ER RR REA ERES 115 Figure 4 6 Right click Compile Menu in Project Tab of Workspace 116 Figure 4 7 Click Plus Sign to Show Design Hierarchy 0 000 000 eee eee 116 Figure 4 8 Setting Compile Order 2 0 eee eee eee teens 117 Figure 4 9 Grouping Piles i2 2246erssenabe eeeeeny Genser eG See ARP RERO AP ERES 118 Figure 4 10 Start Simulation Dialog 0 0 0 2c eect eee nee 119 Figure 4 11 Structure Tab of the Workspace 0 cece eee eee 119 Figure 4 12 Project Displayed in Workspace 2 225 64eesesse es re Rn 120 Figure 4 13 Add Simulation Configuration Dialog 0 0 00 ee eee eee 122 Figure 4 14 Simulation Configuration in the Project Tab 00000000005 123 Figure 4 15 Add Polder Dialog inset es ead ad a Guee vn hood gee ERR RU RE Ra GRE 123 Figure 4 16 Specifying a Project Folder 0 0 ee eee eee eens 124 Figure 4 17 Project Compiler Settings Dialog llle 125 Figure 4 18 Sp
56. ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright C 1996 2000 Julian R Seward All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 The origin of this software must not be misrepresented you must not claim that you wrote the original software If you use this software in a product an acknowledgment in the product documentation would be appreciated but is not required 3 Altered source versions must be plainly marked as such and must not be misrepresented as being the original software 4 The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGEN
57. ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU GPL v 2 install directory2 docs legal gnu gpl 2 0 pdf This software application may include MinGW GNU diffutils third party software portions of which are licensed under the GNU Free Documentation License v 1 1 To obtain original source code of MinGW GNU diffutils or modifications made if any send a request to request sourcecode mentor com Software distributed under the Free Documentation License is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU Free Documentation License install directory docs legal gnu free doc 1 1 pdf This software application may include MinGW GNU diffutils third party software portions of which are licensed under the GNU Library General Public License v 2 To obtain original source code of MinGW GNU diffutils or modifications made if any send a request to request sourcecode mentor com Software distributed under the Library General Public License is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See
58. Another predefined library is work the library where a design unit is stored after it is compiled as described earlier There is no limit to the number of libraries that can be referenced but only one library is modified during compilation Alternate IEEE Libraries Supplied The installation directory may contain two or more versions of the IEEE library e ieeepure Contains only IEEE approved packages accelerated for ModelSim e ieee Contains precompiled Synopsys and IEEE arithmetic packages which have been accelerated by Model Technology including math complex math real numeric bit numeric std std logic 1164 std logic misc std logic textio std logic arith std logic signed std logic unsigned vital primitives and vital timing You can select which library to use by changing the mapping in the modelsim ini file The modelsim ini file in the installation directory defaults to the ieee library Regenerating Your Design Libraries Depending on your current ModelSim version you may need to regenerate your design libraries before running a simulation Check the installation README file to see if your libraries require an update You can regenerate your design libraries using the Refresh command from the Library tab context menu refer to Managing Library Contents or by using the refresh argument to vcom and vlog From the command line you would use vcom with the refresh argument to update VHDL design units in a library
59. C unknown input driving unknown and output driving low c unknown input driving unknown and output driving high f unknown input and output three stated ModelSim User s Manual v6 3g May 2008 Value Change Dump VCD Files Capturing Port Driver Data Driver Strength The recorded 0 and 1 strength values are based on Verilog strengths Table 13 7 Driver Strength Minis VHDL std logic mappings small medium weak large pull WR DL strong Oa G Care Identifier Code The lt identifier_code gt is an integer preceded by lt that starts at zero and is incremented for each port in the order the ports are specified Also the variable type recorded in the VCD header is port Resolving Values The resolved values written to the VCD file depend on which options you specify when creating the file Default Behavior By default ModelSim generates output according to IEEE 1364 2005 The standard states that the values 0 both input and output are active with value 0 and 1 both input and output are active with value 1 are conflict states The standard then defines two strength ranges e Strong strengths 7 6 and 5 e Weak strengths 4 3 2 1 The rules for resolving values are as follows e If the input and output are driving the same value with the same range of strength the resolved value is 0 or 1 and the strength is the stronger of the two e If the input is driving a stron
60. DelayFileOpen This variable instructs the tool to open VHDL387 files on first read or write else open files when elaborated e Value Range 0 1 e Default off 0 DumpportsCollapse This variable collapses vectors VCD id entries in dumpports output e Value Range 0 1 e Default collapsed 1 ErrorFile This variable specifies an alternative file for storing error messages By default error messages are output to the file specified by the TranscriptFile variable in the modelsim ini file refer to Creating a Transcript File If the ErrorFile variable is specified all error messages will be stored in the specified file not in the transcript e Value Range any valid filename Default filename error log GenerateFormat This variable controls the format of a generate statement label Do not enclose the argument in quotation marks ModelSim User s Manual v6 3g 383 May 2008 Simulator Variables Simulator Control Variables e Value Range Any non quoted string containing at a minimum a s followed by a d e Default cs ocd GenerousldentifierParsing Controls parsing of identifiers input to the simulator If this variable is on value 1 either VHDL extended identifiers or Verilog escaped identifier syntax may be used for objects of either language kind This provides backward compatibility with older do files which often contain pure VHDL extended identifier syntax even for escaped identifiers in Verilo
61. Display Options dialog box which allows you to further control which messages appear in the Message Viewer tab Related GUI Features e The Messages Bar in the Wave window provides indicators as to when a message occurred Message Viewer Display Options Dialog Box This dialog box allows you to control display options for the message viewer tab of the transcript window e Hierarchy Selection This field allows you to control the appearance of message hierarchy if any o Display with Hierarchy enables or disables a hierarchical view of messages o First by Then by specifies the organization order of the hierarchy if enabled e Time Range Allows you to filter which messages appear according to simulation time The default is to display messages for the complete simulation time e Displayed Objects Allows you to filter which messages appear according to the values in the Objects column The default is to display all messages regardless of the values in the Objects column The Objects in the list text entry box allows you to specify filter strings where each string must be on a new line Message Viewer Filter Dialog Box This dialog box allows you to create filter rules that specify which messages should be shown in the message viewer It contains a series of dropdown and text entry boxes for creating the filter rules and supports the addition of additional rule rows to create logical groupings From left to right
62. ERR ARR REX ERES QU rre ax KE 37 Table 2 3 Icon Shapes and Design Object Types 0 0 0 cece eee eee nee 37 Table 2 4 Commands for Tab Groups 0 0 00 cece eee eee eee ene 43 Table 2 5 Information Displayed in Status Bar 0 0 00 cece eee 44 Table 2 6 Main Window Toolbar Buttons 0 0 00 cece eee 45 Table 2 7 Dataflow Window Toolbar 0 0 cece eee eee eens 51 Table 2 8 Memori og 294 Jones isu ex E OR Dee aD RM e ae wd He acd 59 Table 2 9 Message Viewer Tasks osos daos sedo eX T eh ax x ober eager ees 77 Table 2 10 Icons and Actions 3 03 esiceriecaveradeeisdesrerededasneesSernxd 89 Table 2 11 Wave Window Toolbar Buttons and Menu Selections 93 Table 3 1 Compile Options for the nodebug Compiling 00 0000 104 Table 7 1 Example Modules With and Without Timescale Directive 183 Table 7 2 Evaluation 1 of always Statements 0 0 ce eee eee eee 186 Table 7 3 Evaluation 2 of always Statement 20 0 cee eee eee 187 Table 7 4 IEEE Std 1364 System Tasks and Functions 1 000 5 205 Table 7 5 IEEE Std 1364 System Tasks and Functions 2 0 000000 205 Table 7 6 IBEE Std 1364 System Tasks 2 22oosooe sse o e RRERR EE RT EE 206 Table 7 7 IEEE Std 1364 File VO Tasks eeeeeeeeeee III 206 Table 7 8 System Verilog System Tasks and Functions 1 0 0000 e eee 207 Table
63. Event Queues with Blocking or Non Blocking Assignments The only control you have over event order is to assign an event to a particular queue You do this by using blocking or non blocking assignments Blocking Assignments Blocking assignments place an event in the active inactive or future queues depending on what type of delay they have e ablocking assignment without a delay goes in the active queue e a blocking assignment with an explicit delay of 0 goes in the inactive queue e a blocking assignment with a non zero delay goes in the future queue ModelSim User s Manual v6 3g 187 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Non Blocking Assignments A non blocking assignment goes into either the non blocking assignment update event queue or the future non blocking assignment update event queue Non blocking assignments with no delays and those with explicit zero delays are treated the same Non blocking assignments should be used only for outputs of flip flops This insures that all outputs of flip flops do not change until after all flip flops have been evaluated Attempting to use non blocking assignments in combinational logic paths to remove race conditions may only cause more problems In the preceding example changing all statements to non blocking assignments would not remove the race condition This includes using non blocking assignments in the generation of gated clocks The following
64. File Size scusa RE GR RR he RR Re REESE E suns dad ados 222 Opemn Dalasels ORT 223 Viewing Dataset Structure uere ex me acese vasi px Buse odee ever sx ea CE ees 224 Structure Tab Columns sse ER sere seen neer SEES Dew She eee bees ee ESPERE RR ds 225 Managing Multiple Datasets sacs iR EexNEREKRRRELAT RR A RERATRG GR EERI SEE REXESRA 225 GU ETT M E 225 Command Lgs eque cod a suu oS ecd hase ci be ER Peu Rhe i ERE PES tee es 225 Restricting the Dataset Prefix Display 0 0 cece e 226 Saving at Intervals with Dataset Snapshot 0 0 00 cece eee ene 227 ModelSim User s Manual v6 3g 7 May 2008 Table of Contents Collapsing Time and Delia SIeps 2 RE nee ees coe ens euver eee enee eas ERES 228 Virtual OBIBOIS rarae inntar oie xS RT PENGCESRGH EAE AGENCE A SEM SEE PEERS 220 Virtual SIBDHIS Su ones xe ted er niet mea Oea EEE I REPRE PA DQRE DOR nq RES 230 Virtual EIOS eoa seniis d VERE S QE Orta EXE ER OSsQUERERI EE PPS esp PARE 231 Virtual ROgiollS d oi a eq RER VI d RI ERIGI NE EAM PECES RENE EI dE E E ER 232 Virtual TV 8S o osayasoteseop a we apa xa seco DV asap SUR Resp Red ed ao a Res 232 Chapter 9 Waveform ADA VSIS 42e RACER RA ORO ACA Ohba a Kees Saye A end arenas 233 Objects You am VIEW a ead oid er bee bare aah ede ea RE ICE ower ee CA eR cee end 233 Wave Window Overview a ose od ex am xav ped ex tease ec uarie eaae 233 Last Window DVeryIeW casses ERA Iu RI RR CR
65. For example to annotate maximum timing values from the SDF file myasic sdf to an instance u under a top level named testbench invoke the simulator as follows vsim sdfmax testbench u1 myasic sdf testbench If the instance name is omitted then the SDF file is applied to the top level This is usually incorrect because in most cases the model is instantiated under a testbench or within a larger system level simulation In fact the design can have several models each having its own SDF file In this case specify an SDF file for each instance For example ModelSim User s Manual v6 3g 315 May 2008 Standard Delay Format SDF Timing Annotation Specifying SDF Files for Simulation vsim sdfmax system u1 asic1 sdf sdfmax system u2 asic2 sdf system SDF Specification with the GUI As an alternative to the command line options you can specify SDF files in the Start Simulation dialog box under the SDF tab Figure 12 1 SDF Tab in Start Simulation Dialog x Design VHDL Verilog Libraries SDF Others d m SDF Files Add Modify Delete SDF Options Multi Source delay Disable SDF wamings vi Reduce SDF errors to warnings LUE Cancel You can access this dialog by invoking the simulator without any arguments or by selecting Simulate gt Start Simulation See the Graphical User Interface chapter for a description of this dialog For Verilog designs you can als
66. GUI 133 hierarchically 400 search rules 134 modelsim lib 155 moving 134 multiple libraries with common modules 174 naming 132 predefined 135 refreshing library images 136 resource libraries 129 std library 135 Synopsys 136 Verilog 173 VHDL library clause 135 working libraries 129 working vs resource 26 working with contents of 131 library map file Verilog configurations 180 library mapping overview 27 library maps Verilog 2001 180 library simulator state variable 403 library definition 26 LibrarySearchPath ini file variable 372 480 License ini file variable 385 licensing License variable in ini file 385 Limiting WLF file 222 List pane see also pane List pane List window 53 237 setting triggers 267 see also windows List window LM LICENSE FILE environment variable 365 loading the design overview 28 local variables modifying with change command 205 Locals window 56 see also windows Locals window location maps referencing source files 405 locations maps specifying source files with 405 lock message 412 locking cursors 241 log file overview 219 see also WLF files long simulations saving at intervals 227 M MacroNestingLevel simulator state variable 403 macros DO files 357 creating from a saved transcript 74 depth of nesting simulator state variable 403 error handling 361 parameters as a simulator state variable n 403 passing 358 total number pa
67. LICENSE AGREEMENT Agreement This is a legal agreement concerning the use of Software between you the end user as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries collectively Mentor Graphics Except for license agreements related to the subject matter of this license agreement which are physically signed by you and an authorized representative of Mentor Graphics this Agreement and the applicable quotation contain the parties entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid GRANT OF LICENSE The software programs including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your
68. Layouts ES mi xj Specify a Layout to Use When no design loaded NoDesign v When a design is loaded Simulate v When a design is loaded with coverage enabled Coverage v IV Save Window Layout Automatically OK Cancel 3 Select a layout for each mode 4 Click OK The layout assignment is saved to the modelsim file Registry on Windows 458 ModelSim User s Manual v6 3g May 2008 Setting GUI Preferences Navigating the Graphic User Interface Automatic Saving of Layouts By default any changes you make to a layout are saved automatically when you exit the tool or when you change modes For example if you load a design with code coverage rearrange some windows and then quit the simulation the changes are saved to whatever layout was assigned to the load with coverage mode To disable automatic saving of layouts select Layout Configure and uncheck Save Window Layout Automatically Resetting Layouts to Their Defaults You can reset the layouts for the three modes to their original defaults Select Layout Reset This command does not delete custom layouts Navigating the Graphic User Interface This section discusses how to rearrange various elements of the GUI Manipulating Panes Window panes e g Workspace can be positioned at various places within the parent window or they can be dragged out undocked of the parent window altogether Figure E 2 GUI Window Pane
69. MTI USELIB DIR environment variable see Environment Variables e A directory named mti uselibs that is created in the current working directory The following code fragment and compiler invocation show how two different modules that have the same name can be instantiated within the same design module top uselib dir h vendorA libext v NAND2 ul n1 n2 n3 uselib dir h vendorB libext v NAND2 u2 n4 n5 n6 endmodule vlog compile uselibs top This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries ModelSim User s Manual v6 3g 179 May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files uselib is Persistent As mentioned above the appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved This may result in unexpected consequences For example consider the following compile command vlog compile uselibs dut v srtr v Assume that dut v contains a uselib directive Since srtr v is compiled after dut v the uselib directive is still in effect When srtr is loaded it is using the uselib directive from dut v to decide where to locate modules If this is not what you intend then you need to put an empty uselib at the end of dut v to close the previous uselib statement Verilog Configurations The Verilog 2001 specification added configurations Configurations specify how a design is assemble
70. May 2008 335 Value Change Dump VCD Files VCD File from Source To Output VHDL Source Code The design is a simple shifter device represented by the following VHDL source code library IEEE use IEEE STD LOGIC 1164 a11 entity SHIFTER MOD is port CLK RESET data in IN STD LOGIC Q INOUT STD LOGIC VECTOR 8 downto 0 END SHIFTER MOD architecture RTL of SHIFTER MOD is begin process CLK RESET begin if RESET 1 then Q lt others gt 0 elsif CLK event and CLK 1 then Q lt Q Q left 1 downto 0 amp data in end if end process end VCD Simulator Commands At simulator time zero the designer executes the following commands vcd file output vcd vcd add r force reset 1 0 force data in 0 0 force clk 0 0 run 100 force clk 1 0 0 50 repeat 100 run 100 vcd off force reset 0 0 force data in 1 0 run 100 vcd on run 850 force reset 1 0 run 50 vcd checkpoint quit sim VCD Output The VCD file created as a result of the preceding scenario would be called output vcd The following pages show how it would look 336 ModelSim User s Manual v6 3g May 2008 Sdate Thu Sep 18 11 07 43 2003 Send Svers ion ModelSim Version 6 1 Send Stimescale in Send S scope module var var var Svar Svar Svar Svar Svar Svar Svar Svar Svar wire 1 wire 1 wir wire 1 wire 1 wire 1 wire 1 wire 1 wire 1 wire 1 wire
71. ModelSim offers a number of options for disabling timing checks on a global or individual basis The table below provides a summary of those options See the command and argument descriptions in the Reference Manual for more details Table 12 21 Disabling Timing Checks Command and argument Effect vlog notimingchecks disables timing check system tasks for all instances in the specified Verilog design vlog nospecify disables specify path delays and timing checks for all instances in the specified Verilog design vsim no_neg_tchk disables negative timing check limits by setting them to zero for all instances in the specified design vsim no_ notifier vsim no_tchk_msg disables the toggling of the notifier register argument of the timing check system tasks for all instances in the specified design disables error messages issued by timing check system tasks when timing check violations occur for all instances in the specified design vsim notimingchecks vsim nospecify Troubleshooting disables Verilog and VITAL timing checks for all instances in the specified design sets generic TimingChecksOn to FALSE for all VHDL Vital models with the Vital levelO or Vital levell attribute Setting this generic to FALSE disables the actual calls to the timing checks along with anything else that is present in the model s timing check block disables specify path delays and timing checks for all instance
72. ModelSim to generate better error messages Subprogram Inlining ModelSim attempts to inline subprograms at compile time to improve simulation performance This happens automatically and should be largely transparent However you can disable automatic inlining two ways 140 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Compiling VHDL Files Invoke vcom with the O0 or O1 argument Use the mti_inhibit_inline attribute as described below Single stepping through a simulation varies slightly depending on whether inlining occurred When single stepping to a subprogram call that has not been inlined the simulator stops first at the line of the call and then proceeds to the line of the first executable statement in the called subprogram If the called subprogram has been inlined the simulator does not first stop at the subprogram call but stops immediately at the line of the first executable statement mti_inhibit_inline Attribute You can disable inlining for individual design units a package architecture or entity or subprograms with the mti_inhibit_inline attribute Follow these rules to use the attribute Declare the attribute within the design unit s scope as follows attribute mti_inhibit_inline boolean Assign the value true to the attribute for the appropriate scope For example to inhibit inlining for a particular function e g foo add the following attribute assignment attribute mti_inhibit_i
73. Note There is an internal limit to the number of ports that can be listed with the vcd dumpports command If that limit is reached use the vcd add command with the dumpports option to name additional ports By default ModelSim uses strength ranges for resolving conflicts as specified by IEEE 1364 2005 You can ignore strength ranges using the no_strength_range argument to the vcd dumpports command See Resolving Values for more details Case Sensitivity VHDL is not case sensitive so ModelSim converts all signal names to lower case when it produces a VCD file Conversely Verilog designs are case sensitive so ModelSim maintains case when it produces a VCD file Using Extended VCD as Stimulus You can use an extended VCD file as stimulus to re simulate your design There are two ways to do this 1 Simulate the top level of a design unit with the input values from an extended VCD file 2 Specify one or more instances in a design to be replaced with the output values from the associated VCD file 330 ModelSim User s Manual v6 3g May 2008 Value Change Dump VCD Files Using Extended VCD as Stimulus Simulating with Input Values from a VCD File When simulating with inputs from an extended VCD file you can simulate only one design unit at a time In other words you can apply the VCD file inputs only to the top level of the design unit for which you captured port data The general procedure includes two steps 1 Creat
74. OF SUCH DAMAGE Copyright c 1999 Kungliga Tekniska H gskolan Royal Institute of Technology Stockholm Sweden All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 Neither the name of KTH nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE E
75. RST 40 50 notifier dCLK dRST setuphold negedge RST D 1 1 notifier dRST dD ModelSim User s Manual v6 3g 197 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs 0 10 20 30 40 45 RST violation VVVVAVAVVAVAAVAN D violation XXXXXXXXXX CLK Tn D violation XX RST As illustrated earlier to solve timing checks on CLK delays of 20 and 31 time units were necessary on dD and dCLK repectively Rising Falling dCLK 3l 31 dD 20 20 dRST 0 0 The simulator s intermediate delay solution is 0 10 2123 30 40 45 RST violation VVVVVVAVVVVAVAVAN D violation XXXXXXXXXX CLK D violation XX RST But this is not consistent with the timing check specified between RST and D The falling RST signal can be delayed by additional 10 but that is still not enough for the delay solution to converge Rising Falling dCLK 31 31 dD 20 20 dRST 0 10 198 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs 0 10 21 23 30 40 55 RST violation AAAA D violation XXXXXXXXXX CLK D violation XX RST As stated above if a delay solution cannot be determined with the specified timing check limits the smallest negative setup recovery limit is zeroed and the calculation of delays repeated If no negative setup recovery limits exist then the smallest negative hold removal limit is zeroed This process is repeated until
76. Simulate Add Tools Window Help Figure 2 4 Main Window OSB reo Atal SHRM fi wa OP ey Bl ome A OX Workspace HAR Design unit Designu Gr tamtb Ab clock driver spram3 spram MA dprami BIMPLICIT wIRE data SIMPLICIT WIRE outa SIMPLICIT WIRE nad IMPLICIT WIRE we D OSIMPLICIT wIRE cIk OBIMPLICIT WIRE cIk SJMPLICIT WIRE data RIMPLICIT wWIRE addi ram tb ram tb ram tb sp syn ram sp syn ram sp syn ram sp syn ra Mdp syn ra ram tb ram tb ram tb ram tb ram tb ram tb ram tb Statemer Statemer Module Module Module Module Module Process Process Process Process Process Process Process Process v gt Mep Bon Ee a Objects E IT RAA inaddr data dpl ddr ir Transcript vsim worl Loading Loading Loading Loading IVSIM 3 ram tb ork ram tb ork Ssp_syn_ramertl Ork Nsp syn ram 3D ork Ndp syn ram ri l Now Ong Deta 0 V Workspace tabs organize design elements in a hierarchical tree structu re The Transcript pane sim ram tb reports status and provides a command line interface The Objects pane displays data objects in the current scope Notice some of the elements that appear 40 Multiple document interface MDI pane Workspace tabs organize and display design objec
77. Source Code e Verilog and VHDL IP vendors or IP users may use the vlog nodebug or vcom nodebug command respectively to protect entire files Delivering IP Code with Undefined Macros The vencrypt utility enables IP vendors to deliver Verilog and SystemVerilog IP code that contains undefined macros and directives The resulting encrypted IP code can then be used in a wide range of EDA tools and design flows The recommended vencrypt usage flow is shown in Figure 3 1 Figure 3 1 vencrypt Usage Flow create Verilog or SystemVerilog IP with user definable macros create encryption envelopes to protect selected regions of code IP vendor vencrypt creates vp or svp file deliver encrypted IP vp or svp file define macros compile encrypted IP with vlog simulate user 1 The IP vendor creates Verilog or SystemVerilog IP that contains undefined macros and directives 2 The IP vendor creates encryption envelopes with pragma protect expressions to protect selected regions of code or entire files see Protect Pragma Expressions 3 TheIP vendor uses ModelSim s vencrypt utility to encrypt Verilog and SystemVerilog IP code contained within encryption envelopes The resulting code is not pre processed before encryption so macros and other directives are unchanged 98 ModelSim User s Manual v6 3g May 2008 Protecting Your Source Code Usage Models for Protecting Source Code The vencrypt utilit
78. T2150 500000 0 ooooo000 TOTIS 510000 0 ooooo000 Lr 0 511000 1 1 ooo00000 yah jn 515000 0 40000000 520000 0 40000000 187 0 n oooooooo000O00000O0O0O000000 529000 1 40000000 187 0 o000000000000000000000000 164 T E m Adding Objects to the Wave or List Window You can add objects to the Wave or List window in several ways ModelSim User s Manual v6 3g 237 May 2008 Waveform Analysis Adding Objects to the Wave or List Window Adding Objects with Drag and Drop You can drag and drop objects into the Wave or List window from the Workspace Active Processes Memory Objects Source or Locals panes You can also drag objects from the Wave window to the List window and vice versa Select the objects in the first window then drop them into the Wave window Depending on what you select all objects or any portion of the design can be added Adding Objects with Menu Selections The Add menu in the Main windows let you add objects to the Wave window List window or Log file You can also add objects using right click context menus For example if you want to add all signals in a design to the Wave window you can do one of the following e Right click a design unit in a structure view i e the sim tab of the Workspace pane and select Add gt Add All Signals to Wave from the popup context menu e Right click anywhere in the Objects pane and select Add to Wave gt Signals in Design from the popup context menu Adding Ob
79. THE POSSIBILITY OF SUCH DAMAGE THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT THIS SOFTWARE IS PROVIDED ON AN AS IS BASIS AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE SUPPORT UPDATES ENHANCEMENTS OR MODIFICATIONS GOVERNMENT USE If you are acquiring this software on behalf of the U S government the Government shall have only Restricted Rights in the software and related documentation as defined in the Federal Acquisition Regulations FARs in Clause 52 227 19 c 2 If you are acquiring the software on behalf of the Department of Defense the software shall be classified as Commercial Computer Software and the Government shall have only Restricted Rights as defined in Clause 252 227 7013 c 1 of DFARs Notwithstanding the foregoing the authors grant the U S Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license 1995 1997 Roger E Critchlow Jr The authors hereby grant permission to use copy modify distribute and license this software and its documentation for any purpose provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions No written agreement license or royalty fee is required
80. The association between the disable signal spy call and the init signal spy call is based on specifying the same src object and dest object arguments to both The disable signal spy call can only affect init signal spy calls that had their control state argument set to 0 or 1 By default this command uses a backslash V as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file VHDL Syntax disable signal spy src object dest object lt verbose gt Verilog Syntax disable signal spy src object dest object lt verbose gt SystemC Syntax disable signal spy src object dest object lt verbose gt Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal Verilog register net or SystemC signal This path should match the path that was specified in the init signal spy call that you wish to disable dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal Verilog register net or SystemC signal This path should match the path that was specified in the init signal spy call that you wish to disable verbose Optional integer Specifies whether you want a message reported in the transcript stating that a disable occurred and the simulation time that it
81. VSIM prompt on sc stop or finish 388 RTL level design busses reconstructing 230 RunLength ini file variable 390 Runtime Options dialog 395 m saveLines preference variable 75 saving simulation options in a project 121 waveforms 219 sc stop behavior customizing 388 scaling fonts 37 SDF disabling timing checks 326 errors and warnings 316 instance specification 315 interconnect delays 325 mixed VHDL and Verilog designs 325 specification with the GUI 316 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I troubleshooting 326 Verilog sdf_annotate system task 319 optional conditions 324 optional edge specifications 323 rounded timing values 325 SDF to Verilog construct matching 320 VHDL resolving errors 318 SDF to VHDL generic matching 317 SDF DEVICE matching to Verilog constructs 321 SDF GLOBALPATHPULSE matching to Verilog constructs 321 SDF HOLD matching to Verilog constructs 321 SDF INTERCONNECT matching to Verilog constructs 320 SDF IOPATH matching to Verilog constructs 320 SDF NOCHANGE matching to Verilog constructs 323 SDF PATHPULSE matching to Verilog constructs 321 SDF PERIOD matching to Verilog constructs 323 SDF PORT matching to Verilog constructs 320 SDF RECOVERY matching to Verilog constructs 322 SDF RECREM matching to Verilog constructs 322 SDF REMOVAL matching to Verilog constructs 322 SDF SETUPHOLD matching to Verilog constructs 322 SDF SKEW matching to Veri
82. Vendor Defined Macros IP vendors may use protect pragmas to protect Verilog and SystemVerilog code containing vendor defined macros and directives The resulting encrypted IP code can be delivered to IP customers for use in a wide range of EDA tools and design flows The recommended usage flow is shown in Figure 3 2 Figure 3 2 Delivering IP Code with Vendor Defined Macros create Verilog or SystemVerilog IP with vendor defined macros create encryption envelopes to protect regions of code IP vendor vlog protect creates vp or svp file deliver encrypted IP vp or svp file user 1 The IP vendor creates Verilog or SystemVerilog IP that contains vendor defined macros and directives 2 The IP vendor creates encryption envelopes with pragma protect expressions to protect regions of code or entire files See Protect Pragma Expressions 3 The IP vendor uses the vlog protect command to encrypt IP code contained within encryption envelopes The pragma protect expressions are ignored unless the protect argument is used with vlog 100 ModelSim User s Manual v6 3g May 2008 4 5 Protecting Your Source Code Usage Models for Protecting Source Code The vlog protect command produces a vp or a svp extension to distinguish it from other non encrypted Verilog and SystemVerilog files respectively The file extension may be changed for use with simulators other than ModelSim The original file exten
83. a copy or modification of this software and in all copies of the supporting documentation for such software THIS SOFTWARE IS BEING PROVIDED AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY IN PARTICULAR THE AUTHOR MAKES NO REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE Copyright C 1993 DJ Delorie All rights reserved Redistribution and use in source and binary forms is permitted provided that the above copyright notice and following paragraph are duplicated in all such forms This file is distributed WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE Copyright c 1993 Intel Corporation Intel hereby grants you permission to copy modify and distribute this software and its documentation Intel grants this permission provided that the above copyright notice appears in all copies and that both the copyright notice and this permission notice appear in supporting documentation In addition Intel grants this permission provided that you prominently mark as not part of the original any modifications made to this software or documentation and that the name of Intel Corporation not be used in advertising or publicity pertaining to distribution of the software or the documentation without specific written prior permission Intel Corporation provides this AS IS WITHOUT ANY WARRANTY EXPRESS OR IMPLI
84. a value less than the simulator resolution will be rounded to the nearest resolution unit no special warning will be issued e Verilog memories arrays of registers are not supported init_signal_driver Example This example creates a local clock c k0 and connects it to two clocks within the design hierarchy The b k1 clk will match local c k0 and a message will be displayed The bIk2 clk will match the local c k0 but be delayed by 100 ps For the second call to work the bIk2 clk must be a VHDL based signal because if it were a Verilog net a 100 ps inertial delay would consume the 40 ps clock period Verilog nets are limited to only inertial delays and thus the setting of 1 transport delay would be ignored timescale 1 ps 1 ps module testbench reg clk0 initial begin Clk0 1 forever begin 20 clk0 clk0 end end initial begin init signal driver clk0 testbench uut blk1l clk 1 init signal driver clk0 testbench uut blk2 clk 100 1 end endmodule ModelSim User s Manual v6 3g 301 May 2008 Signal Spy init_signal_driver init_signal_driver Example This example creates a local clock c k0 and connects it to two clocks within the design hierarchy The b k1 clk will match local c kO and a message will be displayed The open entries allow the default delay and delay type while setting the verbose parameter to a 1 The blk2 clk will ma
85. and 6 ns Negative limit s set to zero The delayed clk and delayed data arguments are provided to ease the modeling of devices that may have negative timing constraints The model s logic should reference the delayed clk and delayed data nets in place of the normal c k and data nets This ensures that the correct data is latched in the presence of negative constraints The simulator automatically calculates the delays for delayed clk and delayed data such that the correct data is latched as long as a timing constraint has not been violated See Using Delayed Inputs for Timing Checks for more information Optional arguments not included in the task must be indicated as null arguments by using commas For example setuphold posedge CLK D 2 4 tcheck cond The setuphold task does not specify notifier or tstamp_cond but does include a tcheck cond argument Notice that there are no commas after the tcheck cond argument Using one or more commas after the last argument results in an error ModelSim User s Manual v6 3g 193 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Note Do not condition a setuphold timing check using the tstamp_cond or tcheck_cond arguments and a conditioned event If this is attempted only the parameters in the tstamp_cond or tcheck_cond arguments will be effective and a warning will be issued recrem Syntax recrem control event data event recovery limit removal
86. as conditions to Mentor Graphics obligations under this section you must a notify Mentor Graphics promptly in writing of the action b provide Mentor Graphics all reasonable information and assistance to defend or settle the action and c grant Mentor Graphics sole authority and control of the defense or settlement of the action 9 2 If an infringement claim is made Mentor Graphics may at its option and expense a replace or modify Software so that it becomes noninfringing b procure for you the right to continue using Software or c require the return of Software and refund to you any license fee paid less a reasonable allowance for use 9 3 Mentor Graphics has no liability to you if infringement is based upon a the combination of Software with any product not furnished by Mentor Graphics b the modification of Software other than by Mentor Graphics c the use of other than a current unaltered release of Software d the use of Software as part of an infringing process e a product that you make use or sell f any Beta Code contained in Software g any Software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers or h infringement by you that is deemed willful In the case of h you shall reimburse Mentor Graphics for its attorney fees and other costs related to the action upon a final judgment 9 4 THIS SECTION IS SUBJECT TO SECTION 6 ABOVE AND STATES THE EN
87. been compiled File Attributes Archive OK Cancel When setting options on a group of files keep in mind the following e If two or more files have different settings for the same option the checkbox in the dialog will be grayed out If you change the option you cannot change it back to a multi state setting without cancelling out of the dialog Once you click OK ModelSim will set the option the same for all selected files e If you select a combination of VHDL and Verilog files the options you set on the VHDL and Verilog tabs apply only to those file types 126 ModelSim User s Manual v6 3g May 2008 Projects Specifying File Properties and Project Settings Project Settings To modify project settings right click anywhere within the Project tab and select Project Settings Figure 4 19 Project Settings Dialog Project Settings x Compile Output Display compiler output IV Save compile report Location map Convert pathnames to softnames Additional Properties JV Restore open source files when opening a project JV Automatically close all source files when closing a project r Double click Behavior File Type VHDL Action Edit vw Custom OK Cancel Converting Pathnames to Softnames for Location Mapping If you are using location mapping you can convert the following into a soft pathname e arelative pathname e full pathname
88. bottom of the Main window When you select a design unit in a dataset s structure tab that dataset becomes active automatically Alternatively you can use the Dataset Browser or the environment command to change the active dataset Design regions and signal names can be fully specified over multiple WLF files by using the dataset name as a prefix in the path For example sim top alu out view top alu out golden top alu out Dataset prefixes are not required unless more than one dataset is open and you want to refer to something outside the active dataset When more than one dataset is open ModelSim will automatically prefix names in the Wave and List windows with the dataset name You can change this default by selecting Tools gt Window Preferences Wave and List windows ModelSim also remembers a current context within each open dataset You can toggle between the current context of each dataset using the environment command specifying the dataset without a path For example env foo sets the active dataset to foo and the current context to the context last specified for foo The context is then applied to any unlocked windows The current context of the current dataset usually referred to as just current context is used for finding objects specified without a path The Objects pane can be locked to a specific context of a dataset Being locked to a dataset means that the pane will update only when the content of tha
89. button relocate the cursor Click and drag the left mouse button select an area Shift click the left mouse button extend selection Double click the left mouse button select a word Double click and drag the left mouse button select a group of words Ctrl click the left mouse button move insertion cursor without changing the selection Click the left mouse button on a previous copy and paste previous command string to ModelSim or VSIM prompt current prompt Click the middle mouse button paste selection to the clipboard Click and drag the middle mouse button scroll the window Table D 3 Keyboard Shortcuts Left Arrow move cursor left or right one character Right Arrow 450 ModelSim User s Manual v6 3g May 2008 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table D 3 Keyboard Shortcuts cont Keystrokes UNIX and Windows Ctrl Left Arrow Ctrl Right Arrow move cursor left or right one word Shift Any Arrow extend text selection Ctrl Shift Left Arrow Ctrl Shift Right Arrow extend text selection by one word Up Arrow Down Arrow Transcript Pane scroll through command history Source Window move cursor one line up or down Ctrl Up Arrow Ctrl Down Arrow Transcript Pane moves cursor to first or last line Source Window moves cursor up or down one paragraph Ctrl Home move cursor to the beginning of
90. by Signal Vy ped dcpe oes EXER E Ea aC ROSEO Ea eed abad epp Eds 63 Source WindOW 4e gwapR a b s at Eri eE paid x E paces RR xa A EdURE any 63 Opening Source Pues o bouem rh ro ed bo EE naaa AE ERR ac Eee Por SOR Rd 64 Displaying Multiple Source Files 0 0 0 0 eee eh 65 Dragging and Dropping Objects into the Wave and List Windows 65 Setting your Context by Navigating Source Files 0 0 0 0 cece eee eee ee 65 Using Language Templates 2 326 eq ROI PER MES cade cede ei Eae E daas 67 Setting File Line Breakpoints with the GUI 0 0 00 eee eee eee eee 69 Adding File Line Breakpoints with the bp Command 0 0 0 0 00 000 70 Modifying File Line Breakpoints 0 0 0 cece eee ee ree 70 Checking Object Values and Descriptions 0 0 c cece eee ee 72 Marking Lines with Bookmarks 0 0 0 cece eee e 72 Customizing the Source Window 0 0 cece en 12 Transcript WiNdOW secc does RITE ganone anaa e ERU a a a E Capp A 13 Transcript Tab 22i222a eeiidessepidiere iaraa akai R Ru HE EAE eek 14 Message Viewer Tab 2 404 229224 pacer ec m cores e aie a ON a PEE a a ete ide 76 Watch Pane coes cinsi tect ig op uenra a EEEE S RE RR OE xe bese E S OD ee 80 Adding Objects to the Watch Pane 2 24 vx koa ben nnana 82 Expanding Objects to Show Individual Bits llle 82 Grouping and Unerouping Objects 2c 1s lt secans rre pe anes RR hecsburenc 83 Saving and Reloading
91. can be used to define responses to timing violations e The tstamp_cond argument is optional It conditions the data event for the setup check and the c k event for the hold check This alternate method of conditioning precludes specifying conditions in the c k event and data event arguments e The tcheck_cond argument is optional It conditions the data event for the hold check and the c k event for the setup check This alternate method of conditioning precludes specifying conditions in the c k event and data event arguments e The delayed_clk argument is optional It is a net that is continuously assigned the value of the net specified in the c k event The delay is determined by the simulator and may be non zero depending on all the timing check limits e The delayed_data argument is optional It is a net that is continuously assigned the value of the net specified in the data event The delay is determined by the simulator and may be non zero depending on all the timing check limits You can specify negative times for either the setup limit or the hold limit but the sum of the two arguments must be zero or greater If this condition is not met ModelSim zeroes the negative limit during elaboration or SDF annotation To see messages about this kind of problem use the ntc warn argument with the vsim command A typical warning looks like the following Warning vsim 3616 cells v x Instance dff0 Bad setuphold constraints 5 ns
92. current interactive scope The equivalent simulator command is show Compiler Directives ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364 some Verilog XL compiler directives and some that are proprietary Many of the compiler directives such as timescale take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a resetall directive The effect of compiler directives spans source files so the order of source files on the compilation command line could be significant For example if you have a file that defines some common macros for the entire design then you might need to place it first in the list of files to be compiled The resetall directive affects only the following directives by resetting them back to their default settings this information is not provided in the IEEE Std 1364 celldefine default decay time default nettype delay mode distributed delay mode path delay mode unit delay mode zero protect timescale unconnected drive uselib ModelSim Verilog implicitly defines the following macro define MODEL TECH IEEE Std 1364 Compiler Directives The following compiler directives are described in detail in the IEEE Std 1364 ModelSim User s Manual v6 3g 215 May 2008 Verilog and SystemVerilog Simulation Compiler Directives celldefine default nettype defin
93. denote paths that are determined by an environment variable except MTI LIB DIR which is determined by a Tcl variable 1 Determines the path to the executable directory modeltech lt platform gt Sets MODEL TECH to this path unless MODEL TECH OVERRIDE exists in which case MODEL TECH is set to the same value as MODEL TECH OVERRIDE 2 Finds the modelsim ini file by evaluating the following conditions use MODELSIM which defines the location of a modelsim ini file if it exists else e use MGC_PWD modelsim ini else e use modelsim ini else e use MODEL_TECH modelsim ini else e use MODEL_TECH modelsim ini else e use MGC HOMEVlib modelsim ini else e set path to modelsim ini even though the file doesn t exist 3 Finds the location map file by evaluating the following conditions e use MGC LOCATION MAP if it exists if this variable is set to no map ModelSim skips initialization of the location map else ModelSim User s Manual v6 3g 469 May 2008 System Initialization Initialization Sequence 10 11 12 13 470 e use mgc_location_map if it exists else e use HOME mgc mgc_location_map else e use HOME mgc_location_map else e use MGC HOMEYyetc mgc location map else e use MGC HOMEYys5shared etc mgc location map else e use MODEL TECHymgc location map else e use MODEL TECH mgc location map else e use no map Reads various variables from the vsim sec
94. display using Edit Regenerate an optimal layout Zoom In zoom in by a factor of two from current view Zoom Out zoom out by a factor of two from current view Zoom Full zoom out to show all components in the window Stop Drawing halt any drawing currently happening in the window Show Wave display the embedded wave viewer View Show Wave gER pane 52 ModelSim User s Manual v6 3g May 2008 Graphical User Interface List Window List Window The List window displays a textual representation of waveforms which you can configure to show events and delta events for the signals or objects you have added to the window You can view the following object types in the List window e VHDL signals aliases process variables and shared variables e Verilog nets registers and variables e Virtuals Virtual signals and functions Figure 2 11 List Window Ea list EP EXC ns ESIE top paddry top pdatay top saddry m delta top prw top sru top pstrbz ftop sstrby ftop prdyy top srdy 0 0 U U U UUUUUUUU UUUUUUUUUUUUUUUU U U U UUUUUUUU UUUUU U U U UUUUUUUU UUUUUUUUUUUUUUUU U U U UUUUUUUU UUUUU 0 2 U U U UUUUUUUU UUJUUUUUUUUUUUUUU U U U UUUUUUUU UUUUU 5 0 011 00000000 ZZZZZZZZZZZZZZZZ 0 1 1 00000000 ZZZZZ 5 l 011 00000000 ZZZZZZZZZZZZZZzz 0 1 1 00000000 ZZZZZ 5 2 011 00000000 ZZZZZZZZZZZZZZZZ 0 1 l1 00000000 ZZZZZ 5 3 011 00000000 ZZZZZZZZZZZZZZzz 0 1 1
95. e If you omit the sizetf function then a return width of 32 is assumed e The sizetf function should return 0 if the system function return value is of Verilog type real e The sizetf function should return 32 if the system function return value is of Verilog type integer PLI Object Handles Many of the object handles returned by the PLI ACC routines are pointers to objects that naturally exist in the simulation data structures and the handles to these objects are valid throughout the simulation even after the acc close routine is called However some of the objects are created on demand and the handles to these objects become invalid after acc close is called The following object types are created on demand in ModelSim Verilog 438 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Third Party PLI Applications accOperator acc_handle_condition accWirePath acc_handle_path accTerminal acc_handle_terminal acc_next_cell_load acc_next_driver and acc_next_load accPathTerminal acc_next_input and acc_next_output accTchkTerminal acc_handle_tchkarg1 and acc_handle_tchkarg2 accPartSelect acc_handle_conn acc_handle_pathin and acc_handle_pathout If your PLI application uses these types of objects then it is important to call acc_close to free the memory allocated for these objects when the application is done using them If your PLI application places value change callbacks on accRegBit or accTerm
96. e Select a waveform and select Show Drivers from the shortcut menu e Double click a waveform edge you can enable disable this option in the display properties dialog see Setting Wave Window Display Preferences This operation opens the Dataflow window and displays the drivers of the signal selected in the Wave window The Wave pane in the Dataflow window also opens to show the selected signal with a cursor at the selected time The Dataflow window shows the signal s values at the current cursor position Sorting a Group of Objects in the Wave Window Select View gt Sort to sort the objects in the pathname and values panes Creating and Managing Breakpoints ModelSim supports both signal 1 e when conditions and file line breakpoints Breakpoints can be set from multiple locations in the GUI or from the command line Signal Breakpoints Signal breakpoints when conditions instruct ModelSim to perform actions when the specified conditions are met For example you can break on a signal value or at a specific ModelSim User s Manual v6 3g 269 May 2008 Waveform Analysis Creating and Managing Breakpoints simulator time see the when command for additional details When a breakpoint is hit a message in the Main window transcript identifies the signal that caused the breakpoint Setting Signal Breakpoints with the when Command Use the when command to set a signal breakpoint from the VSIM gt prompt For example when e
97. e Value Range 0 e Default off 0 Quiet This variable turns off loading messages e Value Range 0 1 e Default off 0 Show_BadOptionWarning This variable instructs the tool to generate a warning whenever an unknown plus argument is encountered e Value Range 0 e Default off 0 Show_Lint This variable instructs the tool to display lint warning messages ModelSim User s Manual v6 3g 373 May 2008 Simulator Variables Simulator Control Variables e Value Range 0 1 e Default off 0 Show_WarnCantDoCoverage This variable instructs the tool to display warning messages when the simulator encounters constructs which code coverage cannot handle e Value Range 0 1 e Default on 1 Show_WarnMatchCadence This variable instructs the tool to display warning messages about non LRM compliance in order to match Cadence behavior e Value Range 0 1 e Default on 1 Show_source This variable instructs the tool to show any source line containing an error e Value Range 0 e Default off 0 vlog95compat This variable instructs the tool to disable System Verilog and Verilog 2001 support making the compiler compatible with IEEE Std 1364 1995 e Value Range 0 e Default off 0 VHDL Compiler Control Variables You can find these variables under the heading vcom AmsStandard Specifies whether vcom adds the declaration of REAL VECTOR to the STANDARD package This is useful for
98. each filter rule is made up of the following e Add and Remove buttons either add a rule filter row below the current row or remove that rule filter row Logic field specifies a logical argument for combining adjacent rules Your choices are AND OR NAND and NOR This field is greyed out for the first rule filter row e Open Parenthesis field controls rule groupings by specifying if necessary any open parentheses The up and down arrows increase or decrease the number of parentheses in the field ModelSim User s Manual v6 3g 79 May 2008 Graphical User Interface Watch Pane e Column field specifies that your filter value applies to a specific column of the Message Viewer Inclusion field specifies whether the Column field should or should not contain a given value o Fortext based filter values your choices are Contains Doesn t Contain or Exact o For numeric and time based filter values your choices are lt lt gt and gt e Case Sensitivity field specifies whether your filter rule should treat your filter value as Case Sensitive or Case Insensitive This field only applies to text based filter values e Filter Value field specifies the filter value associated with your filter rule e Time Unit field specifies the time unit Your choices are fs ps ns us ms This field only applies to the Time selection from the Column field e Closed Parenthesis field contr
99. enumerated type the value pane lists the actual values of the enumerated type of that object For the other radixes binary octal decimal unsigned hexadecimal or ASCII the object value is converted to an appropriate representation in that radix Note When the symbolic radix is chosen for SystemVerilog reg and integer types the values are treated as binary When the symbolic radix is chosen for SystemVerilog bit and int types the values are considered to be decimal Aside from the Wave Signal Properties dialog there are three other ways to change the radix e Change the default radix for the current simulation using Simulate gt Runtime Options Main window e Change the default radix for the current simulation using the radix command ModelSim User s Manual v6 3g 253 May 2008 Waveform Analysis Formatting the Wave Window e Change the default radix permanently by editing the DefaultRadix variable in the modelsim ini file Dividing the Wave Window Dividers serve as a visual aid for debugging allowing you to separate signals and waveforms for easier viewing In the graphic below a bus is separated from the two signals above it with a divider called Bus Figure 9 24 Separate Signals with Wave Window Dividers P wave default BAS 2 0 xj Ele Edt View Add Format Tools Window 4 test_counter clk 4 fest counter reset I Bus g est counter count 7 6 5 4 3 2 t 0 4 4
100. fetch type acc fetch type str acc fetch value ModelSim User s Manual v6 3g May 2008 acc free acc handle by name acc handle calling mod m acc handle condition acc handle conn acc handle hiconn acc handle interactive scope acc handle loconn acc handle modpath acc handle notifier acc handle object acc handle parent acc handle path acc handle pathin acc handle pathout acc handle port acc handle scope acc handle simulated net acc handle tchk acc handle tchkargl acc handle tchkarg2 acc handle terminal acc handle tfarg acc handle itfarg acc handle tfinst acc initialize Verilog PLI VPI DPI IEEE Std 1364 ACC Routines Table C 4 Supported ACC Routines acc_next acc_next_bit acc_next_cell acc_next_cell_load acc_next_child acc_next_driver acc_next_hiconn acc_next_input acc_next_load acc_next_loconn acc_next_modpath acc_next_net acc_next_output acc_next_parameter acc_next_port acc_next_portout acc_next_primitive acc_next_scope acc_next_specparam acc_next_tchk acc_next_terminal acc_next_topmod acc_object_in_typelist acc_object_of_type acc_product_type acc_product_version acc_release_object acc_replace_delays acc_replace_pulsere acc_reset_buffer acc_set_interactive_scope acc_set_pulsere acc_set_scope acc_set_value acc_vcl_add acc_vcl_delete acc_version 441 Verilog PLI VPI DPI IEEE Std 1364 ACC Routines acc_fetch_paramval cannot be used on 64 bit platforms to fetch a st
101. files can be used as macros DO files Refer to the do command for more information 74 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Transcript Window Changing the Number of Lines Saved in the Transcript Window By default the Transcript window retains the last 5000 lines of output from the transcript You can change this default by selecting Transcript gt Saved Lines Setting this variable to 0 instructs the tool to retain all lines of the transcript Disabling Creation of the Transcript File You can disable the creation of the transcript file by using the following ModelSim command immediately after ModelSim starts transcript file GUI Elements of the Transcript Pane This section describes the GUI elements specific to the Transcript tab Automatic Command Help When you start typing a command at the prompt a dropdown box appears which lists the available commands matching what has been typed so far You may use the Up and Down arrow keys or the mouse to select the desired command When a unique command has been entered the command usage is presented in the drop down box You can toggle this feature on and off by selecting Help Command Completion Transcript Menu Items e Adjust Font Scaling Displays the Adjust Scaling dialog box which allows you to adjust how fonts appear for your display environment Directions are available in the dialog box e Transcript File Allows you to chang
102. files given on the command line into one compilation unit You can invoke vlog in MFCU mode as follows e Fora specific compilation with the mfcu argument to vlog e For all compilations by setting the variable MultiFileCompilationUnit 1 in the modelsim ini file By using either of these methods you allow declarations in unit scope to remain in effect throughout the compilation of all files In case you have made MFCU the default behavior by setting MultiFileCompilationUnit 1 in your modelsim ini file it is possible to override the default behavior on specific compilations by using the sfcu argument to vlog Macro Definitions and Compiler Directives in Compilation Unit Scope According to the SystemVerilog IEEE Std p1800 2005 LRM the visibility of macro definitions and compiler directives span the lifetime of a single compilation unit By default this means the definitions of macros and settings of compiler directives terminate at the end of each source file They do not carry forward from one file to another except when a module interface or package declaration begins in one file and ends in another file In that case the compilation unit spans from the file containing the beginning of the definition to the file containing the end of the definition See Declarations in Compilation Unit Scope for instructions on how to control vlog s handling of compilation units Note hn Compiler directives revert to their default va
103. gt Signal Search to locate transitions or signal values The search feature is not available in all versions of ModelSim Finding Signal Names The Find command is used to locate a signal name or value in the Wave or List window When you select Edit gt Find the Find dialog appears Figure 9 16 Find Signals by Name or Value CS 5 Find Find Next Field Direction 4 Close Name Down Exact C Value C Up v Auto Wrap One option of note is the Exact checkbox Check Exact if you only want to find objects that match your search exactly For example searching for clk without Exact will find top clk and clk1 There are two differences between the Wave and List windows as it relates to the Find feature e Inthe Wave window you can specify a value to search for in the values pane e The find operation works only within the active pane in the Wave window Searching for Values or Transitions Available in some versions of ModelSim the Search command lets you search for transitions or values on selected signals When you select Edit gt Signal Search the Signal Search dialog Figure 9 17 appears ModelSim User s Manual v6 3g 247 May 2008 Waveform Analysis Searching in the Wave and List Windows Figure 9 17 Wave Signal Search Dialog Wave Signal Search window wave x Signal Name s Jtop mydut assert dut pic Search Type C Any Transition C Rising Edge C Falling Edge
104. header file just the header block that starts the encryption The pragma protect end expression is implied by the end of the file The IP vendor delivers encrypted IP with undefined macros and directives The IP user defines macros and directives The IP user compiles the design with vlog Dt dev X Simulation can be performed with ModelSim or other simulation tools Using Public Encryption Keys In ModelSim the vencrypt utility will recognize the Mentor Graphics public key in the following pragmas pragma protect key keyowner MTI key method rsa pragma protect key keyname MGC DVT MTI But if users want to encrypt for third party EDA tools other public keys need to be specified with the key public key directive as follows pragma protect key keyowner Acme key keyname AcmeKeyName pragma protect key public key MIGfMA0GCSqGSIb3DOEBAQUAAAGNADCBiOKBgQC38SzR8u6xw1MKRDOPrZOyOMAX ModelSim User s Manual v6 3g 99 May 2008 Protecting Your Source Code Usage Models for Protecting Source Code ID 1BTN7D12b125 tbKUCQkKVMo6ZkCnt1WZ wT22X715aTkagn6vpAXR8XQBu3 santchVulnr2plOxelGVm5tt4jCgCfrOBWNfHXWLwEOyBXR9tzvaatCWbOWpSlUN 5eqoflisn8Hj2ToOdQIDAQAB This defines a new key named AcmeKeyName with a key owner of Acme The data block following key_public_key directive is an example of a base64 encoded version of a public key that should be provided by a tool vendor Delivering IP Code with
105. hereby granted without fee provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation and that the name of M I T not be used in advertising or publicity pertaining to distribution of the software without specific written prior permission M I T makes no representations about the suitability of this software for any purpose It is provided as is without express or implied warranty Copyright 1987 1988 by Digital Equipment Corporation Maynard Massachusetts All Rights Reserved Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation and that the name of Digital not be used in advertising or publicity pertaining to distribution of the software without specific written prior permission DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS IN NO EVENT SHALL DIGITAL BE LIABLE FOR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTIOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFT
106. hierarchy from within a VHDL architecture or Verilog or SystemC module e g a testbench Note Destination SystemC signals are not supported The init signal driver procedure drives the value onto the destination signal just as if the signals were directly connected in the HDL code Any existing or subsequent drive or force of the destination signal by some other means will be considered with the init signal driver value in the resolution of the signal By default this command uses a backslash V as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file Call only once The init signal driver procedure creates a persistent relationship between the source and destination signals Hence you need to call init signal driver only once for a particular pair of signals Once init signal driver is called any change on the source signal will be driven on the destination signal until the end of the simulation For VHDL we recommend that you place all init signal driver calls in a VHDL process You need to code the VHDL process correctly so that it is executed only once The VHDL process should not be sensitive to any signals and should contain only init signal driver calls and a simple wait statement The process will execute once and then wait forever See the example below For Verilog we recommend that you place all Sinit signal driver calls in a Verilog initial block See the ex
107. http www ieee org VITAL source code The source code for VITAL packages is provided in the directories install dir vhdl src vital22b vital95 vital2000 VITAL Packages VITAL 1995 accelerated packages are pre compiled into the ieee library in the installation directory VITAL 2000 accelerated packages are pre compiled into the vital2000 library If you need to use the newer library you either need to change the ieee library mapping or add a use clause to your VHDL code to access the VITAL 2000 packages To change the ieee library mapping issue the following command vmap ieee lt modeltech gt vital2000 Or alternatively add use clauses to your code ModelSim User s Manual v6 3g 153 May 2008 VHDL Simulation VITAL Compliance LIBRARY vital2000 USE vital2000 vital_primitives all USE vital2000 vital_timing all USE vital2000 vital_memory all Note that if your design uses two libraries one that depends on vital95 and one that depends on vital2000 then you will have to change the references in the source code to vital2000 Changing the library mapping will not work VITAL Compliance A simulator is VITAL compliant if it implements the SDF mapping and if it correctly simulates designs using the VITAL packages as outlined in the VITAL Model Development Specification ModelSim is compliant with the IEEE 1076 4 VITAL ASIC Modeling Specification In addition ModelSim accelerates the VITAL_Ti
108. in ModelSim Verilog but have equivalent simulator commands input filename This system task reads commands from the specified filename The equivalent simulator command is do lt filename gt list hierarchical_name This system task lists the source code for the specified scope The equivalent functionality is provided by selecting a module in the structure pane of the Workspace The corresponding source code is displayed in a Source window reset This system task resets the simulation back to its time 0 state The equivalent simulator command is restart restart filename This system task sets the simulation to the state specified by filename saved in a previous call to save The equivalent simulator command is restore lt filename gt save filename This system task saves the current simulation state to the file specified by filename The equivalent simulator command is checkpoint lt filename gt scope hierarchical_name This system task sets the interactive scope to the scope specified by hierarchical_name The equivalent simulator command is environment lt pathname gt showscopes 214 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiler Directives This system task displays a list of scopes defined in the current interactive scope The equivalent simulator command is show showvars This system task displays a list of registers and nets defined in the
109. in the Expression Builder dialog box to create a GUI expression Each button generates a corresponding element of Expression Syntax and is displayed in the Expression field In addition you can use the Insert Signal button to create an expression from signals you select from the associated Wave or List window For example instead of typing in a signal name you can select signals in a Wave or List window and then click Insert Signal This displays the Select Signal for Expression dialog box shown in Figure 9 19 Figure 9 19 Selecting Signals for Expression Builder Select Signal for Expression Signals List only Select Signals C List All Signals im test counter count Note that the buttons in this dialog box allow you to determine the display of signals you want to put into an expression e List only Select Signals list only those signals that are currently selected in the parent window ModelSim User s Manual v6 3g 249 May 2008 Waveform Analysis Formatting the Wave Window e List All Signals list all signals currently available in the parent window Once you have selected the signals you want displayed in the Expression Builder click OK Saving an Expression to a Tcl Variable Clicking the Save button will save the expression to a Tcl variable Once saved this variable can be used in place of the expression For example say you save an expression to the variable foo Here are some operations you could
110. integer types the values are treated as binary When the symbolic radix is chosen for SystemVerilog bit and int types the values are considered to be decimal The data in this pane is similar to that shown in the Objects Pane except that the values change dynamically whenever a cursor in the waveform pane is moved Figure 2 39 Values Pane ModelSim User s Manual v6 3g 87 May 2008 Graphical User Interface Wave Window Waveform Pane The waveform pane displays the waveforms that correspond to the displayed signal pathnames It also displays up to 20 cursors Signal values can be displayed in analog step analog interpolated analog backstep literal logic and event formats The radix of each signal can be set individually by right click the signal and select Radix gt format where the default radix is logic If you rest your mouse pointer on a signal in the waveform pane a popup displays with information about the signal You can toggle this popup on and off in the Wave Window Properties dialog actus 2 40 Waveforms Pane Cursor Pane The Cursor Pane displays cursor names cursor values and the cursor locations on the timeline This pane also includes a toolbox that gives you quick access to cursor and timeline features and configurations See Measuring Time with Cursors in the Wave Window for more information Figure 2 41 Cursor Pane Now Cursor 1 200 ns Cursor 2 On the left side of the Cursor Pane
111. internal business purposes c for the license term and d on the computer hardware and at the site authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and programs which vary depending on Software license fees paid or services purchased apply to the following a relocation of Software b use of Software which may be limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be technically implemented through the use of authorization codes or similar devices and c support services provided including eligibility to receive telephone support updates modifications and revisions EMBEDDED SOFTWARE If you purchased a license to use embedded software development ESD Software if applicable Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate incorporate or embed copies of Mentor Graphics real time operating systems or other embedded software pro
112. licenses exclude msimhdlmix and hdlmix exclude MTI licenses noqueue do not wait in license queue if no licenses are available noslvhdl exclude qhsimvh and vsim noslvlog exclude qhsimvl and vsimvlog only use PLUS license only use VLOG license only use VHDL license e Default search all licenses ModelSim User s Manual v6 3g 385 May 2008 Simulator Variables Simulator Control Variables MaxReportRhsCrossProducts This variable specifies a limit on number of Cross bin products which are listed against a Cross when a XML or UCDB report is generated The warning reports when any instance of unusually high number of Cross bin product and truncation of Cross bin product list for a Cross e Value Range positive integer e Default 1000 MaxValueLen This variable controls the length in characters of all values in the GUI You can set this variable interactively in the GUI refer to Setting Simulator Control Variables With The GUI e Value Range 0 or positive integer where zero 0 sets means the length is unlimited e Default 30000 MessageFormat This variable defines the format of VHDL assertion messages as well as normal error messages e Value Range Table A 3 MessageFormat Variable Accepted Values Variable Description S severity level PR report message time of assertion delta instance or region pathname if available instance pathname with proces
113. light blue for Verilog and SystemVerilog green for SystemC magenta for PSL Setting Fonts You may need to adjust font settings to accommodate the aspect ratios of wide screen and double screen displays or to handle launching ModelSim from an X session Font Scaling To change font scaling select the Transcript window then Transcript Adjust Font Scaling You ll need a ruler to complete the instructions in the lower right corner of the dialog When you have entered the pixel and inches information click OK to close the dialog Then restart ModelSim to see the change This is a one time setting you shouldn t have to set it again unless ModelSim User s Manual v6 3g 37 May 2008 Graphical User Interface User Defined Radices you change display resolution or the hardware monitor or video card The font scaling applies to Windows and UNIX operating systems On UNIX systems the font scaling is stored based on the DISPLAY environment variable User Defined Radices A user definable radix is used to map bit patterns to a set of enumeration labels After defining a new radix the radix will be available for use in the List Watch and Wave windows or with the examine command There are four commands used to manage user defined radices e radix define radix names e radix list e radix delete The radix define command is used to create or modify a radix It must include a radix name and a definition body which consist
114. messages bar located at the top of the Wave window contains indicators pointing to the times at which a message was output from the simulator Figure 2 45 Wave Window Message Bar gal wave default Messages The message indicators the down pointing arrows are color coded as follows e Red indicates an error or an assertion failure e Yellow indicates a warning e Green indicates a note e Grey indicates any other type of message You can use the Message bar in the following ways e Move the cursor to the next message You can do this in two ways o Click on the word Messages in the message bar to cycle the cursor to the next message after the current cursor location o Click anywhere in the message bar then use Tab or Shift Tab to cycle the cursor between error messages either forward or backward respectively e Display the Message Viewer Tab Double click anywhere amongst the message indicators e Display in the Message Viewer tab the message entry related to a specific indicator Double click on any message indicator ModelSim User s Manual v6 3g 91 May 2008 Graphical User Interface Wave Window This function only works if you are using the Message Viewer in flat mode To display your messages in flat mode a Right click in the Message viewer and select Display Options b Inthe Message Viewer Display Options dialog box deselect Display with Hierarchy Objects Yo
115. method of conditioning precludes specifying conditions in the control event and data event arguments The delayed ctrl argument is optional It is a net that is continuously assigned the value of the net specified in the control event The delay is determined by the simulator and may be non zero depending on all the timing check limits The delayed data argument is optional It is a net that is continuously assigned the value of the net specified in the data event The delay is determined by the simulator and may be non zero depending on all the timing check limits ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs You can specify negative times for either the recovery_limit or the removal_limit but the sum of the two arguments must be zero or greater If this condition is not met ModelSim zeroes the negative limit during elaboration or SDF annotation To see messages about this kind of problem use the ntc_warn argument with the vsim command The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that may have negative timing constraints The model s logic should reference the delayed_clk and delayed_data nets in place of the normal control and data nets This ensures that the correct data is latched in the presence of negative constraints The simulator automatically calculates the delays for delayed_clk and delayed_data such that the correct data is la
116. numerioc std ALL ENTITY sp syn ram protected IS GENERIC data width positive 8 addr width positive 3 PORT inclk IN std logic outclk IN std logic we IN std logic addr IN unsigned addr width 1 DOWNTO 0 data in IN std logic vector data width 1 DOWNTO 0 data out OUT std logic vector data width 1 DOWNTO 0 END sp syn ram protecteg ARCHITECTURE intarch OF sp syn ram protected IS TYPE mem type IS PROTECTED PROCEDURE write data IN std logic vector data width 1 downto 0 addr IN unsigned addr width 1 DOWNTO 0 IMPURE FUNCTION read addr IN unsigned addr width 1 DOWNTO 0 RETURN std logic vector END PROTECTED mem type TYPE mem type IS PROTECTED BODY TYPE mem array IS ARRAY 0 TO 2 addr width 1 OF std logic vector data width 1 DOWNTO 0 VARIABLE mem mem array PROCEDURE write data IN std logic vector data width 1 downto 0 addr IN unsigned addr width 1 DOWNTO 0 IS BEGIN mem to integer addr data END IMPURE FUNCTION read addr IN unsigned addr width 1 DOWNTO 0 RETURN std logic vector IS BEGIN return mem to integer addr END END PROTECTED BODY mem type ModelSim User s Manual v6 3g 163 May 2008 VHDL Simulation Modeling Memory 164 SHARED VARIABLE memory mem_type BEGIN ASSERT data_width lt 32 REPORT Illegal data width detected SEVERITY failure control_proc PROCESS inclk o
117. object models Table C 1 VPI Compatibility Considerations Simulator Compatibility plicompatdefault When your VPI and HDL are written based on the 2001 standard be sure to specify as an argument to vsim plicompatdefault 2001 When your VPI and HDL are written based on the 2005 standard you do not need to specify any additional information to vsim because this is the default behavior New SystemVerilog objects in the HDL will be completely invisible to the application This may be problematic for example for a delay calculator which will not see SystemVerilog objects with delay on a net It is possible to write a 2005 VPI that is backwards compatible with 2001 behavior by using mode neutral techniques The simulator will reject 2005 requests if it is running in 2001 mode so there may be VPI failures You should only use this setup if there are other VPI libraries in use for which it is absolutely necessary to run the simulator in 2001 mode This combination is not recommended when the simulator is capable of supporting the 2005 constructs This combination is not recommended You should change the plicompatdefault argument to 2001 This combination is most likely to result in errors generated from the VPI as it encounters objects in the HDL that it does not understand This combination should function without issues as SystemVerilog is a superset of Verilog All that is happening here
118. occurred 0 Does not report a message Default Reports a message ModelSim User s Manual v6 3g 295 May 2008 Signal Spy disable_signal_spy Related procedures init_signal_spy enable_signal_spy Example See init signal spy Example or Sinit signal spy Example 296 ModelSim User s Manual v6 3g May 2008 Signal Spy enable_signal_spy enable_signal_ spy This reference section describes the following e VHDL Procedure enable_signal_spy e Verilog Task enable_signal_spy e SystemC Function enable signal spy The enable_signal_spy call enables the associated init_signal_spy call The association between the enable_signal_spy call and the init_signal_spy call is based on specifying the same src_object and dest_object arguments to both The enable_signal_spy call can only affect init signal spy calls that had their control state argument set to 0 or 1 By default this command uses a backslash V as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file VHDL Syntax enable signal spy src object dest object lt verbose gt Verilog Syntax S enable signal spy src object dest object lt verbose gt SystemC Syntax enable signal spy src object dest object lt verbose gt Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with
119. oooo000000000000000000001 1 al al ojojo ooo S 2 Working with Markers The table below summarizes actions you can take with markers Table 9 3 Actions for Time Markers Add marker Select a line and then select Edit Add Marker Delete marker Select a tagged line and then select Edit gt Delete Marker Goto marker Select View Goto time Zooming the Wave Window Display Zooming lets you change the simulation range in the waveform pane You can zoom using the context menu toolbar buttons mouse keyboard or commands Zooming with the Menu Toolbar and Mouse You can access Zoom commands from the View menu in the Wave window when it is undocked from the Wave Zoom menu selections in the Main window when the Wave window is docked or by clicking the right mouse button in the waveform pane of the Wave window 244 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Zooming the Wave Window Display These zoom buttons are available on the toolbar Zoom In 2x Zoom Out 2x zoom in by a factor of two zoom out by a factor of two from the current view from current view Zoom In on Active Cursor Zoom Full centers the active cursor in zoom out to view the full the waveform display and range of the simulation from zooms in time 0 to the current time Zoom Mode EL change mouse pointer to zoom mode see below To zoom with the mouse first enter zoom mode by selecting View
120. output TEXT open write mode is STD OUTPUT STD INPUT is a file logical name that refers to characters that are entered interactively from the keyboard and STD OUTPUT refers to text that is displayed on the screen In ModelSim reading from the STD INPUT file allows you to enter text into the current buffer from a prompt in the Transcript pane The lines written to the STD OUTPUT file appear in the Transcript TextlO Implementation Issues Writing Strings and Aggregates A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT VECTOR For example the VHDL procedure WRITE L hello will cause the following error ERROR Subprogram WRITE is ambiguous In the TextIO package the WRITE procedure is overloaded for the types STRING and BIT VECTOR These lines are reproduced here procedure WRITE L inout LINE VALUE in BIT VECTOR JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 procedure WRITE L inout LINE VALUE in STRING JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 The error occurs because the argument hello could be interpreted as a string or a bit vector but the compiler is not allowed to determine the argument type until it knows which function is being called 150 ModelSim User s Manual v6 3g May 2008 VHDL Simulation TextlO Implementation Issues The following procedure call also gener
121. p void RegisterMySystfs void vpiHandle tmpH S cb data callback S vpi systf data systf data systf data type vpiSysFunc systf data sysfunctype vpiSizedFunc systf data tfname Smyfunc systf_data calltf MyFuncCalltf systf_data compiletf MyFuncCompiletf systf_data sizetf MyFuncSizetf systf_data user_data 0 tmpH vpi_register_systf amp systf_data vpi_free_object tmpH callback reason cbEndOfCompile callback cb rtn MyEndOfCompCB callback user data 0 tmpH vpi register cb amp callback vpi free object tmpH callback reason cbStartOfSimulation callback cb rtn MyStartOfSimCB callback user data 0 tmpH vpi register cb amp callback vpi free object tmpH ModelSim User s Manual v6 3g 421 May 2008 Verilog PLI VPI DPI Registering DPI Applications void vlog_startup_routines RegisterMySystfs 0 last entry must be 0 Loading VPI applications into the simulator is the same as described in Registering PLI Applications Using PLI and VPI Together PLI and VPI applications can co exist in the same application object file In such cases the applications are loaded at startup as follows e If an init_usertfs function exists then it is executed and only those system tasks and functions registered by calls to mti RegisterUserTF will be defined e If an init_usertfs function does not exist bu
122. permitted provided that the above copyright notice and this paragraph are duplicated in all such forms and that any documentation advertising materials and other materials related to such distribution and use acknowledge that the software was developed by the University of California Berkeley The name of the University may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE Copyright c 1984 2000 S L Moshier Permission to use copy modify and distribute this software for any purpose without fee is hereby granted provided that this entire notice is included in all copies of any software which is or includes a copy or modification of this software and in all copies of the supporting documentation for such software THIS SOFTWARE IS BEING PROVIDED AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY IN PARTICULAR THE AUTHOR MAKES NO REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE Copyright c 1991 by AT amp T Permission to use copy modify and distribute this software for any purpose without fee is hereby granted provided that this entire notice is included in all copies of any software which is or includes
123. pulse msg no risefall delaynets tno show cancelled e nosdfwarn nowarn lt mnemonic gt se_e lt percent gt se e style ondetect pulse e style onevent S S S pulse int e percent pulse int r percent pul tsdf nocheck celltype tsdf verbose tshow cancelled e ttransport int delays ttransport path delays ttypdelays Using Escaped ldentifiers ModelSim recognizes and maintains Verilog escaped identifier syntax Prior to version 6 3 Verilog escaped identifiers were converted to VHDL style extended identifiers with a backslash at the end of the identifier Verilog escaped identifiers then appeared as VHDL extended identifiers in tool output and command line interface CLI commands For example a Verilog escaped identifier like the following top dut 03 had to be displayed as follows top dut 03 ModelSim User s Manual v6 3g May 2008 201 Verilog and SystemVerilog Simulation Cell Libraries Starting in version 6 3 all object names inside the simulator appear identical to their names in original HDL source files Sometimes in mixed language designs hierarchical identifiers might refer to both VHDL extended identifiers and Verilog escaped identifiers in the same fullpath For example top VHDL ext Vlog ext bottom assuming the PathSeparator variable is set to or top WHDL ext Vlog ext bottom assuming the PathSeparator variable is set to Any fullpath t
124. refer to the ASIC vendor s documentation In ModelSim use the vcd dumpports command to create a VCD file that captures port driver data Each time an external or internal port driver changes values a new value change is recorded in the VCD file with the following format p state 0 strength 1 strength identifier code ModelSim User s Manual v6 3g 339 May 2008 Value Change Dump VCD Files Capturing Port Driver Data Driver States The driver states are recorded as TSSI states if the direction is known as detailed in this table Table 13 5 Driver States Input testfixture Output dut U high H high N unknown X unknown Z tri state T tri state d low two or more 1 low two or more drivers active drivers active u high twoormore h high two or drivers active more drivers active If the direction is unknown the state will be recorded as one of the following 340 Table 13 6 State When Direction is Unknown Unknown direction O low both input and output are driving low 1 high both input and output are driving high unknown both input and output are driving unknown F three state input and output unconnected A unknown input driving low and output driving high a unknown input driving low and output driving unknown B unknown input driving high and output driving low b unknown input driving high and output driving unknown
125. reference to the calling block to a VHDL signal Verilog register net or SystemC signal This path should match the path that was specified in the init signal spy call that you wish to enable dest object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal Verilog register net or SystemC signal This path should match the path that was specified in the init signal spy call that you wish to enable verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the transcript stating that an enable occurred and the simulation time that it occurred 0 Does not report a message Default Reports a message ModelSim User s Manual v6 3g 297 May 2008 Signal Spy enable_signal_spy Related tasks init_signal_spy disable_signal_spy Example See init_signal_spy Example or init_signal_spy Example 298 ModelSim User s Manual v6 3g May 2008 Signal Spy init_signal_driver init signal driver This reference section describes the following e VHDL Procedure init signal driver e Verilog Task S init signal driver e SystemC Function init signal driver The init signal driver call drives the value of a VHDL signal Verilog net or SystemC called the src object onto an existing VHDL signal or Verilog net called the dest object This allows you to drive signals or nets at any level of the design
126. s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables o In GUI mode a dialog box pops up and asks for user confirmation on whether to quit the simulation e stop Causes the simulation to stay loaded in memory This can make some post simulation tasks easier e exit The simulation exits without asking for any confirmation e Default ask Exits in batch mode prompts user in GUI mode PathSeparator This variable specifies the character used for hierarchical boundaries of HDL modules This variable does not affect file system paths The argument to PathSeparator must not be the same character as DatasetSeparator This variable is used by the vsim and vopt commands Note 2222222222222 When creating a virtual bus the PathSeparator variable must be set to either a period or a forward slash For more information on creating virtual buses refer to the section Combining Objects into Buses e Value Range any character except those with special meaning such as V etc e Default PliCompatDefault This variable specifies the VPI object model behavior within vsim e Value Range o latest This is equivalent to the 2005 argument This is the default behavior if you do not specify this switch or if you specify the switch without an argument o 2005 Instructs vsim to use the object models as defined in IEEE Std 1800 2005 and IEEE Std 1364 2005 You can also use 05 a
127. specified window Wave List Log Dataflow You can access this feature from the Add menu of the Main window the right click menu of the Locals window or the Add menu of the undocked Locals window Change Displays the Change Selected Variable Dialog Box which allows you to alter the value of the object You can access this feature from the Locals menu of the Main window or the right click menu in the Locals window Change Selected Variable Dialog Box This dialog box allows you to change the value of the object you selected When you click Change the tool executes the change command on the object ModelSim User s Manual v6 3g 57 May 2008 Graphical User Interface Memory Panes Figure 2 13 Change Selected Variable Dialog Box Change Selected ariable ES Variable Name top c cache_inst3 line__43 addr_size Value a Change Cancel The Change Selected Variable dialog is prepopulated with the following information about the object you had selected in the Locals window e Variable Name contains the complete name of the object e Value contains the current value of the object When you change the value of the object you can enter any value that is valid for the variable An array value must be specified as a string without surrounding quotation marks To modify the values in a record you need to change each field separately Memory Panes The Main window lists all memories in your design in t
128. tab in the Workspace pane provides access to design units configurations modules packages entitiesarchitectures in a library Various information about the design units is displayed in columns to the right of the design unit name Figure 5 2 Design Unit Information in the Workspace Workspace E FG x CTE RN ESNE EH work Library C modeltech examples mixedHDL work j cache Module C modeltech examples mixedHDL cach E cache set Entity C modeltech examplessmisedHDL set AJ memory Module C modeltech examples mixedHDL mem 1J Proc Module C modeltech examples mixedHDL proc v iP std logic util Package C modeltech examplessmixedHDL util EHE top Entity C modeltech examplessmixedHDL top Al only Architecture vital2000 Library MODEL_TECH vital2000 ieee Library MODEL_TECH ieee modelsim lib Library MODEL TECH modelsim lib tJ i LL ert Tees 3 2 Library The Library tab has a context menu with various commands that you access by clicking your right mouse button Windows 2nd button UNIX 3rd button in the Library tab The context menu includes the following commands e Simulate Loads the selected design unit and opens structure and Files tabs in the workspace Related command line command is vsim e Edit Opens the selected design unit in the Source window or if a library is selected opens the Edit Library Mapping dialog refer to Library Mappings with th
129. test Hest HANDH24 Ed t dau nu AND 23 test trb pm You can clear this highlighting using the Edit Erase highlight command or by clicking the Erase highlight icon in the toolbar Exploring Designs with the Embedded Wave Viewer Another way of exploring your design is to use the Dataflow window s embedded wave viewer This viewer closely resembles in appearance and operation the stand alone Wave window see Waveform Analysis for more information The wave viewer is opened using the View Show Wave menu selection or by clicking the Show Wave icon One common scenario is to place signals in the wave viewer and the Dataflow panes run the design for some amount of time and then use time cursors to investigate value changes In other Words as you place and move cursors in the wave viewer pane see Measuring Time with Cursors in the Wave Window for details the signal values update in the Dataflow pane ModelSim User s Manual v6 3g 279 May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Figure 10 4 Wave Viewer Displays Inputs and Outputs of Selected Process dataflow default default n File Edit View Add Trace Tools Window R StOtest NAND SO Inputs 4 jtop c clk top c pstrb 4 jtop c prw E top c hit gm op c paddr Inouts fi P op c setsel Outputs E top c oen E op c wen 4 jtop c prdy r Now St S
130. that will be applied For the VHDL init signal driver Procedure The value must be either mti inertial default mti transport For the Verilog Sinit signal driver Task The value must be either 0 inertial default transport For the SystemC init signal driver Function The value must be either 0 inertial default transport verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src object is driving the dest object 0 Does not report a message Default Reports a message ModelSim User s Manual v6 3g May 2008 Signal Spy init_signal_driver Related procedures init_signal_spy signal_force signal_release Limitations e For the VHDL init_signal_driver procedure when driving a Verilog net the only delay_type allowed is inertial If you set the delay type to mti_transport the setting will be ignored and the delay type will be mti_inertial e For the Verilog init_signal_driver task when driving a Verilog net the only delay_type allowed is inertial If you set the delay type to 1 transport the setting will be ignored and the delay type will be inertial e For the SystemC init_signal_driver function when driving a Verilog net the only delay type allowed is inertial If you set the delay type to 1 transport the setting will be ignored and the delay type will be inertial e Any delays that are set to
131. the calling code on the vsim command line after you place the gblso argument for the called code This is because vsim loads the files in the specified order and you must load called code before calling code in all cases Circular references aren t possible to achieve If you have that kind of condition you are better off combining the two shared objects into a single one For more information about this topic please refer to the section Loading Shared Objects with Global Symbol Visibility 428 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI The following platform specific instructions show you how to compile and link your PLI VPI DPI C applications so that they can be loaded by ModelSim Various native C C compilers are supported on different platforms The gcc compiler is supported on all platforms The following PLI VPI DPI routines are declared in the include files located in the ModelSim install dir include directory e acc user h declares the ACC routines e veriuser h declares the TF routines e vpi user h declares the VPI routines e svdpi h declares DPI routines The following instructions assume that the PLI VPI or DPI application is in a single source file For multiple source files compile each file as specified in the instructions and link all of the resulting object files t
132. the docs tcl_help_html TclCmd directory in your QuestaSim installation Cell Libraries Model Technology passed the ASIC Council s Verilog test suite and achieved the Library Tested and Approved designation from Si2 Labs This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to 202 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Cell Libraries achieving full ASIC vendor support As a consequence many ASIC and FPGA vendors Verilog cell libraries are compatible with ModelSim Verilog The cell models generally contain Verilog specify blocks that describe the path delays and timing constraints for the cells See section 14 in the IEEE Std 1364 2005 for details on specify blocks and section 15 for details on timing constraints ModelSim Verilog fully implements specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog XL compatible extensions SDF Timing Annotation ModelSim Verilog supports timing annotation from Standard Delay Format SDF files See Standard Delay Format SDF Timing Annotation for details Delay Modes Verilog models may contain both distributed delays and path delays The delays on primitives UDPs and continuous assignments are the distributed delays whereas the port to port delays specified in specify blocks are the path delays These delays interact to determin
133. the Legal Directory for the text of the GNU Library General Public License install directory docs legal gnu library gpl 2 0 pdf This software application may include MinGW GNU diffutils third party software portions of which are licensed under the GNU Lesser General Public License v 2 1 To obtain original source code of MinGW GNU diffutils or modifications made if any send a request to request sourcecode mentor com Software distributed under the LGPL is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU Lesser General Public License install directory docs legal gnu lgpl 2 1 pdf Copyright c 1982 1986 1992 1993 The Regents of the University of California Copyright c 1983 Regents of the University of California Copyright c 1983 1989 1993 The Regents of the University of California Copyright c 1987 1993 1994 1996 The Regents of the University of California All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice th
134. the design in the Dataflow window and the associated signals are added to the Wave window move a cursor in the Wave window and the values update in the Dataflow window Source Window select an object in the Dataflow window and the Source window updates if that object is in a different source file How Can I Print and Save the Display You can print the Dataflow window display from a saved eps file in the UNIX realm or by simple menu selections in Windows The Dataflow Page Setup dialog allows you to configure the display for printing Saving a eps File and Printing the Dataflow Display from UNIX With the dataflow pane in the Dataflow window active select File Print Postscript to setup and print the Dataflow display in UNIX or save the waveform as a eps file on any platform Figure 10 8 ModelSim User s Manual v6 3g 287 May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference Figure 10 8 The Print Postscript Dialog Print Postscript Printer Print command lp dp wj SEES C Eile name dataflowps Browse Paper Paper size Letter vi BorderwWidth 04 Font Helvetica wi DK Cancel Printing from the Dataflow Display on Windows Platforms With the dataflow pane in the Dataflow window active select File Print to print the Dataflow display or to save the display to a file Figure 10 9
135. the entry Filters are stored relative to the region selected in the Structure window If you re select a region that had a filter applied that filter is restored This allows you to apply different filters to different regions Filtering by Signal Type The View Filter menu selection allows you to specify which signal types to display in the Objects window Multiple options can be selected Source Window Source files display by default in the MDI frame of the Main window The Source window can be undocked from the Main window by clicking the Undock icon in the window header or by using the view undock source command You can edit source files as well as set breakpoints step through design files and view code coverage statistics By default the Source window displays your source code with line numbers You may also see the following graphic elements ModelSim User s Manual v6 3g 63 May 2008 Graphical User Interface Source Window e Redline numbers denote executable lines where you can set a breakpoint e Blue arrow denotes the currently active line or a process that you have selected in the Process Window e Red ball in BP breakpoint column denotes file line breakpoints gray ball denotes breakpoints that are currently disabled e Blue ball in BP column denotes line bookmarks Language Templates pane displays Using Language Templates Figure 2 20 Figure 2 20 Source Window Showing Language T
136. the same library To do this you must compile the design with the 32 bit version and then refresh the design with the 64 bit version For example Using the 32 bit version of ModelSim vlog novopt file1 v file2 v work asic_lib Next using the 64 bit version of ModelSim vlog novopt work asic_lib refresh This allows you to use either version without having to do a refresh Do not compile the design with one version and then recompile it with the other If you do this ModelSim will remove the first module because it could be stale Importing FPGA Libraries ModelSim includes an import wizard for referencing and using vendor FPGA libraries The wizard scans for and enforces dependencies in the libraries and determines the correct mappings and target directories STE EEE The FPGA libraries you import must be pre compiled Most FPGA vendors supply pre compiled libraries configured for use with ModelSim ModelSim User s Manual v6 3g 137 May 2008 Design Libraries Protecting Source Code To import an FPGA library select File gt Import gt Library Figure 5 4 Import Library Wizard The Import Library Wizard will step you through the tasks necessary to reference and use a library library can be either an existing Model Technology library or an FPGA library that you received from an FPGA vendor If the library was received from an FPGA vendor it must be a precompiled library Please ente
137. the text Ctrl End move cursor to the end of the text Backspace Ctrl h UNIX only Delete Ctrl d UNIX only delete character to the left delete character to the right Esc Windows only cancel Alt activate or inactivate menu bar mode Alt F4 close active window Home Ctrl a UNIX only Ctrl b move cursor to the beginning of the line move cursor left Ctrl d delete character to the right End Ctrl e move cursor to the end of the line Ctrl f UNIX Right Arrow Windows move cursor right one character Ctrl k Ctrl n delete to the end of line move cursor one line down Source window only under Windows Ctrl o UNIX only insert a new line character at the cursor Ctrl p ModelSim User s Manual v6 3g May 2008 move cursor one line up Source window only under Windows 451 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table D 3 Keyboard Shortcuts cont Keystrokes UNIX and Windows Ctrl s UNIX Ctrl f Windows find Ctrl t reverse the order of the two characters on either side of the cursor Ctrl u delete line Page Down Ctrl v UNIX only move cursor down one screen Ctrl w UNIX Ctrl x Windows cut the selection Ctrl s Ctrl x UNIX Only Ctrl y UNIX Ctrl v Windows paste the selectio
138. to sulv n bits natural std ulogic vector end conversions package body conversions is function sulv to natural x std ulogic vector natural is variable n natural 0 variable failure boolean false begin assert x high x low 1 lt 31 report Range of sulv to natural argument exceeds natural range severity error for i in x range loop n ie n 2 case x i is ModelSim User s Manual v6 3g May 2008 161 VHDL Simulation Modeling Memory 162 when 1 H gt n n 1 when O L gt null when others gt failure true end case end loop assert not failure report sulv_to_natural cannot convert indefinite std_ulogic_vector severity error if failure then return 0 else return n end if end sulv to natural function natural to sulv n bits natural return std ulogic vector is variable x others gt 0 variable tempn natural n begin for i in x reverse range loop if tempn mod 2 1 then x 1 2 TL end if tempn tempn 2 end loop return x end natural to sulv end conversions std ulogic vector bits 1 downto 0 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Modeling Memory VHDLO2 example Source Sp syn ram protected vhd Component VHDL synchronous single port RAM Remarks Various VHDL examples random access memory RAM LIBRARY ieee USE ieee std logic 1164 ALL USE ieee
139. to whom the Software is furnished to do so provided that the above copyright notice s and this permission notice appear in all copies of the Software and that both the above copyright notice s and this permission notice appear in supporting documentation THE SOFTWARE IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTIOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE Except as contained in this notice the name of a copyright holder shall not be used in advertising or otherwise to promote the sale use or other dealings in this Software without prior written authorization of the copyright holder This software may include ZLib third party software that may be subject to the following copyright 1997 Christian Michelsen Research AS Advanced Computing Fantoftvegen 38 5036 BERGEN Norway http www cmr no Permission to use copy modify distribute and sell this software and its documentation for any purpose is hereby granted without fee provided that the above copyrigh
140. typically only disable compression for troubleshooting purposes The corresponding modelsim ini variables are WLFCompress for compression and WLFDeleteOnQuit for WLF file deletion e Design Hierarchy Specifies whether to save all design hierarchy in the WLF file or only regions containing logged signals The corresponding modelsim ini variable is WLFSaveAllRegions Message System Variables The message system variables located under the msg system heading help you identify and troubleshoot problems while using the application See also Message System error This variable changes the severity of the listed message numbers to error Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default none fatal This variable changes the severity of the listed message numbers to fatal Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default none note This variable changes the severity of the listed message numbers to note Refer to Changing Message Severity Level for more information e Value Range list of message numbers 398 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables e Default none suppress This variable suppresses the listed message numbers Refer to Changing Message Severity Level for more information e Value Range list of message numbers e Default
141. under the heading vsim in the modelsim ini file AssertFile This variable specifies an alternative file for storing VHDLassertion messages By default assertion messages are output to the file specified by the TranscriptFile variable in the modelsim ini file refer to Creating a Transcript File If the AssertFile variable is specified all assertion messages will be stored in the specified file not in the transcript e Value Range any valid filename Default filename assert log AssertionDebug This variable specifies that SVA assertion passes are reported e Value Range 0 1 e Default off 0 380 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables BreakOnAssertion This variable defines the severity of VHDL assertions that cause a simulation break It also controls any messages in the source code that use assertion_failure_ For example since most runtime messages use some form of assertion_failure_ any runtime error will cause the simulation to break if the user sets BreakOnAssertion to 2 e Value Range 0 note 1 warning 2 error 3 failure 4 fatal e Default 3 failure CheckPlusargs This variable defines the simulator s behavior when encountering unrecognized plusargs e Value Range 0 ignores 1 issues warning simulates while ignoring 2 issues error exits e Default 0 ignores CheckpointCompressMode This variable specifies that checkpoint files
142. use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1993 Intel Corporation Intel hereby grants you permission to copy modify and distribute this software and its documentation Intel grants this permission provide
143. v6 3g May 2008 Verilog and SystemVerilog Simulation Verilog PLI VPI and SystemVerilog DPI accelerate autoexpand vectornets disable portfaults enable portfaults expand vectornets noaccelerate noexpand vectornets noremove gatenames noremove_netnames nosuppress faults remove gatenames remove netnames suppress faults The following Verilog XL compiler directives produce warning messages in ModelSim Verilog These are not implemented in ModelSim Verilog and any code containing these directives may behave differently in ModelSim Verilog than in Verilog XL default trireg strength signed unsigned Verilog PLI VPI and SystemVerilog DPI ModelSim supports the use of the Verilog PLI Programming Language Interface and VPI Verilog Procedural Interface and the SystemVerilog DPI Direct Programming Interface These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface For more information on the ModelSim implementation see Verilog PLI VPI DPI ModelSim User s Manual v6 3g 217 May 2008 Verilog and SystemVerilog Simulation Verilog PLI VPI and SystemVerilog DPI 218 ModelSim User s Manual v6 3g May 2008 Chapter 8 Recording Simulation Results With Datasets This chapter describes how to save the results of a ModelSim simulation and use them in your simulation flow In general any previously recorded simulation data
144. vlog nodebug pli prevents the use of PLI functions to interrogate the module for information vlog nodebug ports pli combines the functions of nodebug ports and nodebug pli Don t use the ports option on a design without hierarchy or on the top level of a hierarchical design If you do no ports will be visible for simulation Rather compile all lower portions of the design with nodebug ports first then compile the top level with nodebug alone 104 ModelSim User s Manual v6 3g May 2008 Protecting Your Source Code Creating an Encryption Envelope Design units or modules compiled with nodebug can only instantiate design units or modules that are also compiled nodebug Creating an Encryption Envelope Encryption envelopes specify a region of Verilog source code to be encrypted These regions are delimited by protection pragmas that specify the encryption algorithm key and envelope attributes The encryption envelope may be configured two ways e The encryption envelope contains the textual design data to be encrypted Example 3 1 e The encryption envelope contains include compiler directives that point to files containing the textual design data to be encrypted Example 3 2 Note Source code that incorporates include compiler directives cannot be used in vencrypt usage flow Example 3 1 Encryption Envelope Contains IP Code to be Protected module test_dff4 output 3 0 q output err parameter
145. window 279 Wave window 84 233 docking and undocking 85 234 in the Dataflow window 279 saving layout 261 timeline display clock cycles 251 see also windows Wave window waveform logfile overview 219 see also WLF files waveforms 219 optimize viewing of 394 viewing 84 WaveSignalNameWidth ini file variable 393 where command 369 WIDTH matching to Verilog 323 windows Active Processes pane 47 Dataflow window 50 275 toolbar 51 zooming 290 List window 53 237 display properties of 259 formatting HDL items 259 saving data to a file 262 setting triggers 264 267 Locals window 56 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ Main window 40 status bar 44 text editing 450 time and delta display 44 toolbar 45 Memory window 58 monitor 80 Objects window 62 Signals window VHDL and Verilog items viewed in 62 Source window 63 text editing 450 viewing HDL source code 63 Variables window VHDL and Verilog items viewed in 56 Wave window 84 233 adding HDL items to 237 cursor measurements 239 display preferences 250 display range zoom changing 244 format file saving 261 path elements changing 393 time cursors 239 zooming 244 WLF file limiting 222 WLF file parameters cache size 222 collapse mode 222 compression 222 delete on quit 222 filename 221 optimization 222 overview 221 size limit 221 time limit 221 WLF files collapsing events 228 optimizing wav
146. you change the working directory within ModelSim the tool reads the library vcom and vlog sections of the local modelsim ini file When you make changes in the compiler or simulator options dialog or use the vmap command the tool updates the appropriate sections of the file The pref tcl file references the default ini file via the GetPrivateProfileString Tcl command The ini file that is read will be the default file defined at the time pref tcl is loaded ModelSim User s Manual v6 3g 471 May 2008 System Initialization Initialization Sequence 472 ModelSim User s Manual v6 3g May 2008 ABCDEFGHIJKLMNOPQRSTUVWXYZ Symbols comment character 348 disable signal spy 295 Senable signal spy 297 finish behavior customizing 388 unit scope visibility in SV declarations 175 Ani control variables AssertFile 380 AssertionDebug 380 AssertionFormat deprecated see MessageFormat 34 AssertionFormatBreak deprecated see MessageFormatBreak 34 AssertionFormatFail deprecated see MessageFormatFail 34 AssertionFormatFatal deprecated see MessageFormatFatal 34 AssertionFormatNote deprecated see MessageFormatNote 34 AssertionFormatWarning deprecated see MessageFormatWarning 34 BreakOnAssertion 381 CheckPlusargs 381 CheckpointCompressMode 381 CommandHistory 381 ConcurrentFileLimit 381 CoverCountAll 381 DatasetSeparator 382 DefaultForceKind 382 DefaultRadix 383 DefaultRestartOption
147. you must explicitly print the results For example vsim do run 20 echo simstats quit f c top Command History Shortcuts You can review the simulator command history or reuse previously entered commands with the following shortcuts at the ModelSim VSIM prompt Table D 1 Command History Shortcuts repeats the last command repeats command number n n is the VSIM prompt number e g for this prompt VSIM 12 gt n 12 repeats the most recent command starting with abc ModelSim User s Manual v6 3g 449 May 2008 Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts Table D 1 Command History Shortcuts cont xyz ab replaces xyz in the last command with ab up arrow and down scrolls through the command history arrow keys click on prompt left click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor his or history shows the last few commands up to 50 are kept Main and Source Window Mouse and Keyboard Shortcuts The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Table D 2 Mouse Shortcuts Mouse UNIX and Windows Result Click the left mouse
148. your source files you must create a library in which to store the compilation results Use vlib to create a new library For example vlib work This creates a library named work By default compilation results are stored in the work library The work library is actually a subdirectory named work This subdirectory contains a special file named info Do not create libraries using UNIX MS Windows or DOS commands always use the vlib command See Design Libraries for additional information on working with libraries ModelSim User s Manual v6 3g 139 May 2008 VHDL Simulation Compiling VHDL Files Invoking the VHDL Compiler ModelSim compiles one or more VHDL design units with a single invocation of vcom the VHDL compiler The design units are compiled in the order that they appear on the command line For VHDL the order of compilation is important you must compile any entities or configurations before an architecture that references them You can simulate a design containing units written with 1076 1987 1076 1993 and 1076 2002 versions of VHDL To do so you will need to compile units from each VHDL version separately The vcom command compiles using 1076 2002 rules by default use the 87 or 93 argument to vcom to compile units written with version 1076 1987 or 1076 1993 respectively You can also change the default by modifying the VHDL93 variable in the modelsim ini file see Simulator Control Variables for more info
149. 08 Waveform Analysis Configuring New Line Triggering in the List Window 3 Select the signal in the List window that you want to be the enable signal by clicking on its name in the header area of the List window 4 Click Insert Selected Signal and then rising in the Expression Builder 5 Click OK to close the Expression Builder You should see the name of the signal plus rising added to the Expression entry box of the Modify Display Properties dialog box 6 Click OK to close the dialog If you already have simulation data in the List window the display should immediately switch to showing only those cycles for which the gating signal is rising If that isn t quite what you want you can go back to the expression builder and play with it until you get it the way you want it If you want the enable signal to work like a One Shot that would display all values for the next say 10 ns after the rising edge of enable then set the On Duration value to 10 ns Trigger Gating Example Using Commands The following commands show the gating portion of a trigger configuration statement configure list usegating 1 configure list gateduration 100 configure list gateexpr test_delta iom_dd rising See the configure command for more details Sampling Signals at a Clock Change You easily can sample signals at a clock change using the add list command with the notrigger argument The notrigger argument disables triggering the disp
150. 10 3 2 01101011 4 2 01101100 5 01101101 6 01101110 r ma amas To ungroup them right click the group and select Ungroup Saving and Reloading Format Files You can save a format file a DO file actually that will redraw the contents of the Watch pane Right click anywhere in the pane and select Save Format The default name of the format file is watch do Once you have saved the file you can reload it by right clicking and selecting Load Format Wave Window The Wave window like the List window allows you to view the results of your simulation In the Wave window however you can see the results as waveforms and their values The Wave window opens by default in the MDI frame of the Main window as shown below The window can be undocked from the main window by clicking the Undock button in the window header or by using the view undock wave command The preference variable 84 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Wave Window PrefMain ViewUnDocked wave can be used to control this default behavior Setting this variable will open the Wave window undocked each time you start ModelSim Figure 2 36 Wave Window Undock Button Undock button gl F e Edt wew Compile Smaise Add Wave Tools Layout Window Help OSS t PODS MF 5 v tall BK OE ee mise SAAB 99 Moss MUM E yy Lea RA micis Boe Annes LE he d wigo 2 221 8 i xh insta
151. 12 redirecting 392 sensitivity list warning 412 suppressing warnings from arithmetic packages 401 Tcl init error 413 too few port connections 413 turning off assertion messages 401 VSIM license lost 414 warning suppressing 408 metavalue detected warning 412 MGC LOCATION MAP env variable 405 MGC LOCATION MAP variable 365 MinGW gcc 430 432 missing DPI import function 426 MODEL TECH environment variable 365 MODEL TECH TCL environment variable 365 modeling memory in VHDL 158 MODELSIM environment variable 366 modelsim ini found by the tool 469 default to VHDL93 402 delay file opening with 402 environment variables in 400 force command default setting 401 hierarchical library mapping 400 opening VHDL files 402 restart command defaults setting 402 startup file specifying with 401 transcript file created from 400 turning off arithmetic package warnings 401 turning off assertion messages 401 modelsim tcl 465 modelsim lib 155 path to 370 MODELSIM PREFERENCES variable 366 464 MODELSIM TCL environment variable 366 modes of operation 29 Modified field Project tab 121 481 ABCDEFGH I modify breakpoints 70 270 273 modifying local variables 205 modules handling multiple common names 174 Monitor window grouping ungrouping objects 83 monitor window 80 mouse shortcuts Main window 450 Source window 450 Wave window 454 mpf file 111 loading from the command line 128 order of acc
152. 1995 and VITAL 2000 IEEE 1076 4 2000 Assumptions We assume that you are familiar with the use of your operating system and its graphical interface We also assume that you have a working knowledge of the design languages Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support that goal ModelSim User s Manual v6 3g 31 May 2008 Introduction Sections In This Document Finally we assume that you have worked the appropriate lessons in the ModelSim Tutorial and are familiar with the basic functionality of ModelSim The ModelSim Tutorial is available from the ModelSim Help menu Sections In This Document In addition to this introduction you will find the following major sections in this document 32 Chapter 4 Projects This chapter discusses ModelSim projects a container for design files and their associated simulation properties Chapter 5 Design Libraries To simulate an HDL design using ModelSim you need to know how to create compile maintain and delete design libraries as described in this chapter Chapter 6 VHDL Simulation This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment Chapter 7 Verilog and SystemVerilog Simulation This chapter is an overview of compilation and simulation for Verilog and SystemVerilog within the ModelSim environment Chapter 8 Recording Simulatio
153. 1n8A pragma protect end protected In this example the pragma protect data method expression designates the encryption algorithm used to encrypt IP code The key for this encryption algorithm is also encrypted In this cases the key is encrypted with the RSA public key The key is recorded in the key block of the protected envelope The encrypted IP code is recorded in the data block of the envelope ModelSim allows more than one key block to be included so that a single protected envelope can be decrypted by tools from different users ModelSim User s Manual v6 3g 109 May 2008 Protecting Your Source Code Compiling a Design with vlog protect 110 ModelSim User s Manual v6 3g May 2008 Chapter 4 Projects Projects simplify the process of compiling and simulating a design and are a great tool for getting started with ModelSim What are Projects Projects are collection entities for designs under specification or test At a minimum projects have a root directory a work library and metadata which are stored in a mpf file located in a project s root directory The metadata include compiler switch settings compile order and file mappings Projects may also include e Source files or references to source files e other files such as READMES or other project documentation e local libraries e references to global libraries e Simulation Configurations see Creating a Simulation Configuration e Folde
154. 273 Figure 10 1 The Dataflow Window undocked ModelSim 04 275 Figure 10 2 Dataflow Debugging Usage Flow 0 0 cece eee ee 276 Figure 10 3 Green Highlighting Shows Your Path Through the Design 279 Figure 10 4 Wave Viewer Displays Inputs and Outputs of Selected Process 280 Figure 10 5 Unknown States Shown as Red Lines in Wave Window 282 Figure 10 6 Find in Dataflow Dialog 0 0 0 cece eee BA 283 Figure 10 7 Dataflow Window and Panes seseleeee eee 286 Figure 10 8 The Print Postscript Dialog 0 0 0 0 eee eee ee eee 288 Figure 10 9 The Print Dialog iu esae echt oie ee es RE ee todos ee eee eee 288 18 ModelSim User s Manual v6 3g May 2008 List of Figures Figure 10 10 The Dataflow Page Setup Dialog 0 0 0 cee eee eee 289 Figure 10 11 Configuring Dataflow Options 0 0 eee ee eee 290 Figure 12 1 SDF Tab in Start Simulation Dialog 0 0 0 0 00 e eee eee 316 Figure A 1 Runtime Options Dialog Defaults Tab 0 00 0 eee eee 396 Figure A 2 Runtime Options Dialog Box Assertions Tab 0000005 397 Figure A 3 Runtime Options Dialog Box WLF Files Tab 00 397 Figure C 1 DPI Use Flow Diagram 2z5soeu og REEXTRG4 RR RR REDE RE PESE ear 424 Figure E 1 Save Current Window Layout Dialog Box 0 0 0 0 eee ee eee 458 Figure E 2 G
155. 3 cewietaden tod eadersne cuter ene atennde PH 130 Working with Design Libraries 1252s ee RR rry ya x RERO T ENS 130 Creating a Library 42s ex ERES DIE RERUS DEC RES RA qU REPARARE ER P Rae KE 131 Managing Library Contents 2 04 25 444424 25452404 RYE aa ESI e xS RE edd s 131 Assigning a Logical Name to a Design Library 0 0 0 eee ee eee 132 Moving a AMERY eee cames etai aa od erdum red ESAE RE dd pidas 134 Setting Up Libraries for Group Use slssseseleeeeee eens 134 Sp cifying Resource Libraries ss 25045 eU Exp epE ROS uU X EXd eR PUR E eUE EE 135 Verilog Resource Libraries vous sor ER coke ene eeu RENERRSR RE EET RISE ER ES 135 VHDL Resource Libraries 2ideasnccReruca era ceca pot Aue SOET h ast ease 135 Predetited LIDESEIBS issu ceu RREEu AER E sh ieee RD ER CEP eek RIDERE 135 Alternate IEEE Libraries Supplied 4 242222 ee RE RR REPRE RE E RES 136 Regenerating Your Design Libraries i2 essa da QN RP RR Sede ER 136 Maintaining 32 and 64 bit Versions in the Same Library 004 137 Importing FPGA Libraries eua ea oro brig o e se CERE Pa EY INTER E eek EORR d ees ees 137 ModelSim User s Manual v6 3g 5 May 2008 Table of Contents Protecting Source Code se geb RE eae RSEN aes Poe EP RP REPERI E 138 Chapter 6 VHDL SunuldfiOHt s s eR RERE S ES ER E REN DORERE deeds behest dee ceeds eee 139 Basic VHDL FlOW 156b ke9ekke RR d bee RE RR RE P RE bee erekas beans dS 139 Compiling VHDL Pies
156. 4 ram_tb spram4 mem has been expanded to show all the individual bit values Notice the arrow that ties the array to the individual bit display 82 ModelSim User s Manual v6 3g May 2008 Figure 2 34 Expanded Array Cs Hox File Edit View Add Tools Window fram_tb spram4 mem 0x7e778368 0 1 1 4 0 XXXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXXX 2 xxxxxxxxxxxxxxxx 3 xxxxxxxxxxxxxxxx 4 xxxxxxxxxxxxxxxx 5 xxxxxxxxxxxxxxxx 6 xxxxxxxxxxxxxxxx 7 xxxxxxxxxxxxxxxx 8 x xoooooooooooxx 9 x ooooooooooooxx 10 xxxxxxxxxxxxxxxx 11 xxxxxxxxxxxxxxxx 12 xxxxxxxxxxxxxxxx 13 xxxxxxxxxxxxxxxx Grouping and Ungrouping Objects You can group objects in the Watch pane so they display and move together Select the objects then right click one of the objects and choose Group In Figure 2 35 two different sets of objects have been grouped together ModelSim User s Manual v6 3g May 2008 Graphical User Interface Watch Pane 83 Graphical User Interface Wave Window Figure 2 35 Grouping Objects in the Watch Pane RI lolx File Edit View Add Tools Window 1 ts 1 33 S i x 5 x60 me Wa i v iH qf e P IR IR irpo Iram tbjclk 0x7e772Fb8 jram tb spram4 mem 0x7e778368 0 1 1 2 1 2 2 1 Iram tb we 0x7e772fb0 3 2 4 iram tb dprami mem 0x7e778820 0 01101000 1 01101001 2 011010
157. 4 7 To insert a divider follow these steps 1 Select the signal above which you want to place the divider 2 If the Wave pane is docked in MDI frame of the Main window select Add gt Wave gt Divider from the Main window menu bar If the Wave window stands alone undocked from the Main window select Add gt Divider from the Wave window menu bar 3 Specify the divider name in the Wave Divider Properties dialog The default name is New Divider Unnamed dividers are permitted Simply delete New Divider in the Divider Name field to create an unnamed divider 4 Specify the divider height default height is 17 pixels and then click OK 254 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Formatting the Wave Window You can also insert dividers with the divider argument to the add wave command Working with Dividers The table below summarizes several actions you can take with dividers Table 9 5 Actions for Dividers Action Method Move a divider Click and drag the divider to the desired location Change a divider s Right click the divider and select Divider Properties name or size Delete a divider Right click the divider and select Delete Splitting Wave Window Panes The pathnames values and waveforms panes of the Wave window display can be split to accommodate signals from one or more datasets For more information on viewing multiple simulations see Recording Simulation R
158. 7 9 System Verilog System Tasks and Functions 2 0 0 00 e eee eee 207 Table 7 10 SystemVerilog System Tasks and Functions 4 00000 5 208 Table 7 11 Tool Specific Verilog System Tasks and Functions 4 208 Table 8 1 WLF File Parameters 1 2 ace k RR RR ERG HER a RE WR RC ERR es 221 Table 8 2 Structure Tab Columns 3 sco bep Xx ee Ead d exe Boo eaa Ieee e RA EE EOS 225 Table 8 3 vsim Arguments for Collapsing Time and Delta Steps 229 Table 9 1 Cursor and Timeline Toolbox Icons and Actions 0 0000 ee ee 239 Table 9 2 Actions TOF Cursors ees oua ore amp RERAHHR RU eR C OR RD ou ea deen es 241 Table 9 3 Actions Tor Time Markers 52 4 X Ra RE ERR ree nade bees 244 Table 9 4 Actions Tor Bookmarks 260645404600 405544004904 REI RR ERR o 246 Table 9 5 Actions for Dividers 5i oosa sob Rr ERRARE nag WEG RA ERE RS 255 Table 9 6 Triggering Options 2122 ei exa he Rei Son 9 E RS eee HR E E qs 266 Table 10 1 Icon and Menu Selections for Exploring Design Connectivity 278 ModelSim User s Manual v6 3g 20 May 2008 List of Tables Table 10 2 Dataflow Window Links to Other Windows and Panes 287 Table 11 1 Signal Spy Reference Comparison 0 0 c eee eee ee eee 293 Table 12 1 Matching SDF to VHDL Generics 0 0 cee eee eee ee 317 Table 12 2 Matching SDF IOPATH to Verilog 1 22 cscsus rr RR RR RES 320 Table 12 3 Match
159. 71 Messag 3071 Not enough arguments are being passed to the specified system task or function Changing Message Severity Level You can suppress or change the severity of notes warnings and errors that come from vcom vlog and vsim You cannot change the severity of or suppress Fatal or Internal messages There are three ways to modify the severity of or suppress notes warnings and errors e Use the error fatal note suppress and warning arguments to vcom vlog or vsim See the command descriptions in the Reference Manual for details on those arguments e Use the suppress command e Seta permanent default in the msg system section of the modelsim ini file See Simulator Control Variables for more information Suppressing Warning Messages You can suppress some warning messages For example you may receive warning messages about unbound components about which you are not concerned Suppressing VCOM Warning Messages Use the nowarn category number argument with the vcom command to suppress a specific warning message For example vcom nowarn 1 suppresses unbound component warning messages Alternatively warnings may be disabled for all compiles via the Main window Compile Compile Options menu selectons orthe modelsim ini file see Verilog Compiler Control Variables The warning message category numbers are 408 ModelSim User s Manual v6 3g May 2008 Error and Warning Messages Su
160. 75 400 file name specifed in modelsim ini 400 saving 74 using as a DO file 74 Transcript window changing buffer size 75 changing line count 75 TranscriptFile ini file variable 392 triggers in the List window 267 triggers in the List window setting 264 troubleshooting DPI missing import funtion 426 TSSI in VCD files 340 type converting real to time 157 converting time to real 156 Type field Project tab 120 types virtual 232 s D ns UnbufferedOutput ini file variable 392 ungrouping in wave window 258 ungrouping objects Monitor window 83 unit delay mode 204 unknowns tracing 281 usage models encrypting IP code 97 vencrypt utility 97 use clause specifying a library 135 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I use flow DPI 423 user defined bus 229 263 user defined radix 38 definition body 38 UserTimeUnit ini file variable 392 util package 155 Vy values of HDL items 72 variables 395 environment 363 expanding environment variables 363 LM LICENSE FILE 365 precedence between ini and tcl 402 setting environment variables 364 simulator state variables current settings report 363 iteration number 403 name of entity or module as a variable 403 resolution 403 simulation time 403 values of displaying in Objects window 62 saving as binary log file 219 VCD files capturing port driver data 339 case sensitivity 330 creating 329 dumpport
161. 8 PEFObje ct Handles usos ede tan E cee eed Xx ES HEU P Cad EPOR PEE SAUDI 438 Third Party PLI Applications cssc ker Re E RR ER RR Ra xx RE Pd REG 439 Support Tor VHDL Objects iacere can eO PC CR P PORSCHE RR CHR Pn RS 439 IEEE Std 1364 ACC Routines isis eo esae RR x HR REA REO ex au eee aude RON 441 TREE Sul L364 TF ROUUHGS uuu y rac ae n p e ac ee d qi eos ODER o e e 443 SystemVerilog DPI Access Routines l lseeeeeeeeeeeeee ee 443 Verilog XL Compatible Routines oo ek CR ERRREXRW NE RC APR PU IRA SX QR RTA MG ES 444 64 bit Support for PLI ys sace ee pare are a ey RERO toca SR dto o aon ee 445 Using 64 bit ModelSim with 32 bit Applications ssssssss sasarane 445 PLI VPI Tracing 0 2 haee RE E EERSEESEARPREANQECEOERTRSAAPEAMEN RE een ee dA Shera 445 The Purpose of Tracing Files uesesas cesta terc PE IATXWUE PeRAPeXaQ eA EXER 445 lite qu ci PRIM rr 445 Debugging PLI VPI DPI Application Code 0 0 cece eee 446 Appendix D Command and Keyboard Shortcuts 0 cece cece cece cece eee e cree eeees 449 Command SHGUCINS C IETTIPTmETT 449 Command History Shortcuts oce se ra REXWCREECREQERI ERRARE ARS 449 Main and Source Window Mouse and Keyboard Shortcuts llle 450 List Window Keyboard Shortcuts use PERERRREPERYRA RR RWRSC REPEAT RERER A 453 Wave Window Mouse and Keyboard Shortcuts 0 cece eee eee 454 Appendix E Settme GUI Preferences so oz4er 9 RP Er RERBA PRERAESUA PEERS
162. 9 Capt rnng Port Driver Data ia 04 add eO OR RR tsino ar dee EREE TERUR ISO e ES 339 Driver States ed PC HT 340 Driver Sent oe ee eena n beep Ee er EEN EA 341 Identifier Cod 24252534042 Coen sh M RERARIGR Geese AEEA BARAER E RERE TES 341 Resolving Values c iuoqua d vedx RU RECK PEE ceded rE TE A ATE bici E 341 10 ModelSim User s Manual v6 3g May 2008 Table of Contents Chapter 14 Tel and Macros DO Files se se eee ci ig nnm Fe oe tm Ais ewan ee Fie ee wie ee Sis cere 345 Tel Feat tesz 2 csdscmaXRiebev het e RRTAGG X TER TAGGCe D aTaqaceq ra dr E REad Reed 345 Tel ilg m 345 Tel Commands eyed Rcx RECO REP RR UR Ub REOR YR Ge RU kd RR d wg 345 Jor Command Synta oS At hose lie sov REX SQL PER E Eee IN EE S SEES 346 If Command Syntax ood eres RRRERR REGHEEER EG RARE RE RAE E ER RPM E RE 349 Command Substitution 52 4sdees decr ERR EIE REIR WE Rer sqad Fe castes he 349 Command SeDAOE vs ss seg oca erg quet eR ed gabe sati dead exar e arg CR 350 Multiple Line Commands x vede ERO ERU EAMERRP AX Karo RARE Ed 350 Evaluation Ordet cius ines e Sab REESE RU ad rex xai Rates Pad eie de 350 Tcl Relational Expression Evaluation 0 0 00 cee cece 350 Variable Substitution os or oe dace epi exem dew sea seats eee ae rar 351 System Commands irre ls er Race oe bana REG AG KG EP RGUCR RE E Ra CR s 391 List Processing 2 USS tease ees ese ba sees bees ei dade PE Rae pps ed dae dos 352 Simulator Tcl Com
163. AMAGE THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT THIS SOFTWARE IS PROVIDED ON AN AS IS BASIS AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE SUPPORT UPDATES ENHANCEMENTS OR MODIFICATIONS GOVERNMENT USE If you are acquiring this software on behalf of the U S government the Government shall have only Restricted Rights in the software and related documentation as defined in the Federal Acquisition Regulations FARs in Clause 52 227 19 c 2 If you are acquiring the software on behalf of the Department of Defense the software shall be classified as Commercial Computer Software and the Government shall have only Restricted Rights as defined in Clause 252 227 7013 c 1 of DFARs Notwithstanding the foregoing the authors grant the U S Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license 1987 by Digital Equipment Corporation Maynard Massachusetts and the Massachusetts Institute of Technology Cambridge Massachusetts All Rights Reserved Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyrig
164. AR OR nme wt 5 QI terim mdi E AQQQ Medes n Ye Ap ones VS ee ied x E Instance unt wt a tee top fast Modde d wyabas subdut fast Module FL heltat Modde Roplerydat assert__0 Ropjmydutiassert__1 hopjmydutlaconrt 2 Roplerydut acsert_ 3 kopimydutasset 4 kopjmydutlaeont d pta kopimydutiessert dt plas kopinydutlacsert dut pib hopimydutlaesert de ptc Roplmydutiassert__dut_pid kopjmydutlaesett dut ple LES rq Now PILEEELEEEE HA Mc 54 Sy Error 53 PR Asserbon faled 150 ne PR Asserbon faled 200 ns PR Assertion faled 250 ns FR Assertion faled 250m Pep mydatfassert dat pif PL enabled enabled 0 7 3 f Assertion faded 250m 3 feeimdatassert dut pia pa enabled enabisd 9 1 Figure 9 2 is an example of a Wave window that is undocked from the MDI frame To dock the Wave window in the Main window click the Dock button When the Wave window is undocked all menus and icons associated with Wave window functions will appear in the menu and toolbar areas 234 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Wave Window Overview Figure 9 2 Docking the Wave Window F wave default lBl xi File Edit View Add Format Tools Window Dock button Messages jtop mydut assert 0 jtop mydut assert 1 jtop mydut assert 2 jtop mydut assert 3 jtop mydut assert 4 jtop mydut assert dut pia jtopjmydut assert dut piaa jtop mydut assert dut
165. As noted in some cases you can suppress the warning using nowarn level e Type conversion between array types where the element subtypes of the arrays do not have identical constraints e Extended identifier terminates at newline character Oxa e Extended identifier contains non graphic character 0x x e Extended identifier s contains no graphic characters 414 ModelSim User s Manual v6 3g May 2008 Error and Warning Messages Enforcing Strict 1076 Compliance Extended identifier s did not terminate with backslash character An abstract literal and an identifier must have a separator between them This is for forming physical literals which comprise an optional numeric literal followed by a separator followed by an identifier the unit name Warning is level 4 which means nowarn 4 will suppress it In VHDL 1993 or 2002 a subprogram parameter was declared using VHDL 1987 syntax which means that it was a class VARIABLE parameter of a file type which is the only way to do it in VHDL 1987 and is illegal in later VHDLs Warning is level 10 Shared variables must be of a protected type Applies to VHDL 2002 only Expressions evaluated during elaboration cannot depend on signal values Warning is level 9 Non standard use of output port s in PSL expression Warning is level 11 Non standard use of linkage port s in PSL expression Warning is level 11 Type mark of type conversion expre
166. Australian National University 2001 Donal K Fellows 2002 ActiveState Corporation 2000 Ajuba Solutions All rights reserved 1998 2000 by Scriptics Corporation All rights reserved 2001 Apple Computer Inc 1990 1993 The Regents of the University of California All rights reserved 1994 1998 Sun Microsystems Inc All rights reserved This software is copyrighted by the Regents of the University of California Sun Microsystems Inc and other parties The following terms apply to all files associated with the software unless explicitly disclaimed in individual files The authors hereby grant permission to use copy modify distribute and license this software and its documentation for any purpose provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions No written agreement license or royalty fee is required for any of the authorized uses Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here provided that the new terms are clearly indicated on the first page of each file where they apply IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE ITS DOCUMENTATION OR ANY DERIVATIVES THEREOF EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH D
167. CE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright 1989 Software Research Associates Inc Tokyo Japan Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation and that the name of Software Research Associates not be used in advertising or publicity pertaining to distribution of the software without specific written prior permission Software Research Associates makes no representations about the suitability of this software for any purpose It is provided as is without express or implied warranty SOFTWARE RESEARCH ASSOCIATES DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS IN NO EVENT SHALL SOFTWARE RESEARCH ASSOCIATES BE LIABLE FOR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTIOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE Copyright 1991 by the Massachusetts Institute of Technology Permission to use copy modify distribute and sell this software and its documentation for any purpose is
168. CLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR TH
169. CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE Copyright c 1999 Citrus Project All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1998 Todd C Miller lt Todd Miller courtesan com gt All rights reserved Redistribution and
170. California All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this software must display the following acknowledgement This product includes software developed by the University of California Berkeley and its contributors 4 Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHE
171. DENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1994 Hewlett Packard Company Permission to use copy modify distribute and sell this software and its documentation for any purpose is hereby granted without fee provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation Hewlett Packard Company makes no representations about the suitability of this software for any purpose It is provided as is without express or implied warranty Copyright c 1996 Silicon Graphics Computer Systems Inc Permission to use copy modify distribute and sell this software and its documentation for any purpose is hereby granted without fee provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation Silicon Graphics makes no representations about the suitability of this software for any purpose It is provided as is without express or implied warranty This software application may inc
172. E IARET RARE APR a E 49 Figure 2 10 Dataflow Window ModelSim sseseeeleeeeeeeeeee 50 Figure 2 11 List WimdOW uae bu EISE RRARE eC RERRPERR A RES E RE Ad A P EE 53 Figure 2 12 Locals Window 2940264004 og dama aeaa iaa a ka aa a a e d aa Y ESSE 56 Figure 2 13 Change Selected Variable Dialog Box slseseleleeeeeees 58 Pipure 2 14 Memory PAIS S odes a aeoe nenea a a E a a RN a eee 58 Figure 2 15 Viewing Multiple Memories esaxda esse ex EA RAE EX aud aes 60 Figure 2 16 Split Screen View of Memory Contents 61 Figure 2 17 Objects Panes lt 22s s Jee e Ea E dO ERE E Ragas Pa RIA eee E 62 Figure 2 18 Objects Filter iocos ec kee eheed aes PR ee Sada eae E X REP EY bee ad 62 Figure 2 19 Filtering the Objects List by Name 02 0 eee eee 63 Figure 2 20 Source Window Showing Language Templates 005 64 Figure 2 21 Displaying Multiple Source Files 2 0 0 0 0 0 cece eee eee 65 Figure 2 22 Setting Context from Source Files llle 66 Figure 2 23 Language Templates s ni eaesereketkirc4 PRI RP E I RC cade eset IHE S A 67 Figure 2 24 Create New Design Wizard 2 25422 spose ix seed Paws cave REEE 68 Figure 2 25 Inserting Module Statement from Verilog Language Template 68 Figure 2 26 Language Template Context Menus 0 0c ee eee eee eee 69 Figure 2 27 Breakpoint in the Source Window 0 0 eee eee ee eee 69 Figure 2 28 Modifying Existing Brea
173. E SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER THE PROVISIONS OF THIS SECTION 6 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY THE PROVISIONS OF THIS SECTION 7 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT INDEMNIFICATION YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS 10 11 12 13 14 DESCRIBED IN SECTION 7 THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT INFRINGEMENT 9 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States Canada Japan or member state of the European Patent Office Mentor Graphics will pay any costs and damages finally awarded against you that are attributable to the infringement action You understand and agree that
174. EAR PE RE T EE CREE 457 Customizing the Simulator GUI Layout 13er ce a RR E RRURE4S X RrikREP 3 hs 457 Layouts and Modes of Operation 0 0 cece eee ee eee eee eee nee 457 Custom Layouts s esque yan peers pO RESUCRRA RE eae ee ee deen Eee ee eeee xd 457 Automatic Saving of Layouts oa acdndesudadatecked eu dad adadas NEASAGszASAZK ES 459 Resetting Layouts to Their Delaults 22242 cena nd RPR O REPRE A EUROPEE 459 Navigating the Graphic User Interface 0 0 0 ccc cee eens 459 Manipulating Panes 4 pr px RR S OICRESESRqa deen bones REFER ba 459 Coluranar Information Display 2 0c2sc9ceseeees R4 REPRE RE RR EE ERES EP ERE 461 Quick Access Toolbars e seta ER Sa e URP eg es Oe US CHEERS 461 simulator GULPreletefieeR c uiu sce mes SUR SA DRE RE nA HEIDE t dchd do Rd 461 Setting Preference Variables from the GUI 20 0 ccc cece 462 Savine GUI Preferentes S 620s s2tu dens eareesdge ced POE EXNeeEIE PPP S OEERIMS 464 The m delsim tel PI e os ees ex ERR ens E ER Edn E ERERERE eee Seer ERES 465 Appendix F Systemi Ima dO soa exe e 0b 6 qoem pP ERU oe ig aig aea e ORE oe NOR 4 953 467 Piles Accessed During Startup ia ausema 644 cho et RR bb or Rae RE ECKE nee ER Res 467 Environment Variables Accessed During Startup llllelllleeeeeeees 468 Enttialrzattol SEQUENCE s sad vs eos ehe RS idee Idle ee eda eid aed 469 ModelSim User s Manual v6 3g 13 May 2008 Table of Contents Index Third Party Infor
175. ED INCLUDING WITHOUT LIMITATION ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE Intel makes no guarantee or representations regarding the use of or the results of the use of the software and documentation in terms of correctness accuracy reliability currentness or otherwise and you rely on the software documentation and results solely at your own risk IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE LOSS OF BUSINESS LOSS OF PROFITS INDIRECT INCIDENTAL SPECIAL OR CONSEQUENTIAL DAMAGES OF ANY KIND IN NO EVENT SHALL INTEL S TOTAL LIABILITY EXCEED THE SUM PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER Copyright c 1994 Cygnus Support Copyright c 1995 1996 Cygnus Support All rights reserved Redistribution and use in source and binary forms are permitted provided that the above copyright notice and this paragraph are duplicated in all such forms and that any documentation advertising materials and other materials related to such distribution and use acknowledge that the software was developed at Cygnus Support Inc Cygnus Support Inc may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Copyright c 1994 Winning Strategies Inc All rights rese
176. ER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Unless otherwise stated in each remaining newlib file the remaining files in the newlib subdirectory default to the following copyright It should be noted that Red Hat Incorporated now owns copyrights belonging to Cygnus Solutions and Cygnus Support Copyright c 1994 1997 2001 2002 2003 2004 Red Hat Incorporated All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT INDIRECT INCI
177. ERRETRNORTTETRRCRC rcm 307 Sigil release nd o6 ee he renton ee IP qe RUE IUURC PS qoe C Ad qute dq aS 311 ModelSim User s Manual v6 3g 9 May 2008 Table of Contents Chapter 12 Standard Delay Format SDF Timing Annotation eee 315 Specifying SDF Files for Simulation 00 c cece eee ene 315 Instance Specifications ss ess sede nna RC ge es LOS PERDU ey RR eed OA SS 315 SDF Specification with the GUI isasoeuen e RR Ry e e ey RR yas 316 Briers and Warnings ss ess escivepsespEU REX Pe ORE Rex eI d uasa d e S USES 316 VHDL VITAL SDE i suada cud TER AU EN bdo CROCI GR GI eH CR d 317 SDF to VHDL Generic Matching avoue Perebc4 t REX EAE XRPCRRC ers 317 ROSODHBE BEFODSA e vau ioe ore d adr pude gi ende d hace e Cd Ped ev Wr pa eoe aa 318 Verlos P RMMICCP errem 318 SOE annotate cosirer hn ace ences ead ois dn cer dup a rad ad o on eee 319 SDF to Verilog Construct Matching chad o he tax DERE E REY XR RTRPEN UESTRAE eed 320 Optional Edge Specifications 0 ccc eee cece cece ence nee eeens 323 Optional Conditions senene be Race y OSEE AG R3 EP RGUC RE RN pa eR ds 324 Rounder Timing Values ii vcesstcasd Acre es RE Sad RQ NEM EAE PST XU SE S 325 SDF for Mixed VHDL and Verilog Designs llle 325 Interconn ct Deldys ece vea aerd enan EAR Leere a Pe RA RE a esc Rn Reel a 325 Disabling Timing Checks 12 24 Lakskc9 RR raeur 326 Troubleshooting secun xac odd Sone a REV A DURS
178. ERTS IgnoreError 0 IgnoreFailure 0 There is one environment variable MODEL_TECH that you cannot and should not set MODEL_TECH is a special variable set by Model Technology software Its value is the name of the directory from which the VCOM or VLOG compilers or VSIM simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries Hierarchical Library Mapping By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search only the library section of the initialization file specified by the others clause For example Library asic_lib cae asic_lib work my_work others install_dir modeltech modelsim ini Since the file referred to by the others clause may itself contain an others clause you can use this feature to chain a set of hierarchical INI files for library mappings Creating a Transcript File A feature in the system initialization file allows you to keep a record of everything that occurs in the transcript error messages assertions commands command outputs etc To do this set the value for the TranscriptFile line in the modelsim ini file to the name of the file in which you would like to record the ModelSim history Save the command window contents to this file TranscriptFile trnscrpt You can disable the creation of the tra
179. Error ini file variable 384 IgnoreFailure ini file variable 384 IgnoreNote ini file variable 384 IgnoreVitalErrors ini file variable 376 IgnoreWarning ini file variable 385 importing FPGA libraries 137 Incremental ini file variable 372 incremental compilation automatic 173 manual 172 with Verilog 171 index checking 140 init signal driver 299 init signal driver 299 init signal spy 303 init signal spy 156 303 init usertfs function 419 initialization sequence 469 inlining VHDL subprograms 140 input ports matching to INTERCONNECT 320 matching to PORT 320 INTERCONNECT matching to input ports 320 interconnect delays 325 IOPATH matching to specify path delays 320 IP code encrypt 97 public keys 99 undefined macros 98 vendor defined macros 100 encryption usage models 97 using protect pragmas 97 vencrypt usage models 97 iteration limit infinite zero delay loops 148 IterationLimit ini file variable 385 K keyboard shortcuts 479 ABCDEFGHIJKLMNOPQRSTUVWXYZ List window 453 Main window 450 Source window 450 Wave window 454 keywords SystemVerilog 170 ep L work 174 language templates 67 language versions VHDL 141 libraries 64 bit and 32 bit in same library 137 creating 131 design libraries creating 131 design library types 129 design units 129 group use setting up 134 IEEE 136 importing FPGA libraries 137 mapping from the command line 133 from the
180. F It is important to use the correct language version for VITAL VITAL2000 must be compiled with VHDL 93 or VHDL 2002 VITAL95 must be compiled with VHDL 87 A typical error message that indicates the need to compile under language version VHDL 87 is VITALPathDelay DefaultDelay parameter must be locally static Purity of NOW In VHDL 93 the function now is impure Consequently any function that invokes now must also be declared to be impure Such calls to now occur in VITAL A typical error message Cannot call impure function now from inside pure function Y name Yom Files File syntax and usage changed between VHDL 87 and VHDL 93 In many cases vcom issues a warning and continues Using 1076 1987 syntax for file declaration In addition when files are passed as parameters the following warning message is produced Subprogram parameter name is declared using VHDL 1987 syntax This message often involves calls to endfile lt name gt where name is a file parameter Files and packages Each package header and body should be compiled with the same language version Common problems in this area involve files as parameters and the size of type CHARACTER For example consider a package header and body with a procedure that has a file parameter procedure procl out file out std textio text If you compile the package header with VHDL 87 and the body with VHDL 93 or VHDL 2002 you will get a
181. Format Files 0 0 cece eee eee eee eens 84 Wave WIISOW a ot2ttcekndea Sees ee eau ene GSEs eee SEs eee POR eset eee ERI ES 84 Waye WIDJOW Panes ec con doveegeetecwse shana twee bhior ipa ionni rik E see ds 86 Objects You Can View in the Wave Window 0c cece ee eee eee nee 92 Wave Window Toolbar sess 2642 400 640a0c4e0de4ugedetandoobaceougelecets 93 Chapter 3 Protecting Your Source Code 5 o aoo hr ee ERR RR ER PEERS 97 Usage Models for Protecting Source Code 4 cock err RE ERG GC ERO XR REA EA 97 Delivering IP Code with Undefined Macros 0 0 e cece eee eee 98 4 ModelSim User s Manual v6 3g May 2008 Table of Contents Delivering IP Code with Vendor Defined Macros lesse eese 100 Delivering Protected IP with protect Compiler Directives 0000 101 Protecting Source Code Using nodebug iude rexeti bete 4k 3k X4 t Pax nese becaxd 104 Creating an Encryption Envelope 1 422 229 9 oss exa p erERE ERR ERE REIR 105 Protect Pragma Expressions 25x u ha EXE Poe eevee EG UP ERAKQOTENC REI heaves ak 107 Compiling a Design with vlog 4ptOleet iic 2s6e aces Rouen 4pE EFE ORE RENE EE E ERES 108 Chapter 4 luu er d Seean 111 Mat are Projects 2 odeur dE ROSE PRI EUR CA qe C RC P bed ERES I PNE 111 What are the Benefits of Projects 4i seuaoceswen m Rx Rr ev Xd e CER Rx ach RN 111 Project Conversion Between Versions 112 Getting Started with Project
182. GUI elements specific to the List window Column Descriptions The window is divided into two adjustable columns which allow you to scroll horizontally through the listing on the right while keeping time and delta visible on the left e The left column shows the time and any deltas that exist for a given time e The right column contains the data for the signals and objects you have added for each time shown in the left column The top portion of the window contains the names of the signals The bottom portion shows the signal values for the related time Note The display of time values in the left column is limited to 10 characters Any time value of more than 10 characters is replaced with the following too narrow Markers The markers in the List window are analogous to cursors in the Wave window You can add delete and move markers in the List window similarly to the Wave window You will notice two different types of markers e Active Marker The most recently selected marker shows as a black highlight 54 ModelSim User s Manual v6 3g May 2008 Graphical User Interface List Window e Non active Marker Any markers you have added that are not active are shown with a green border You can manipulate the markers in the following ways e Setting a marker When you click in the right hand portion of the List window you will highlight a given time black horizontal highlight and a given signal o
183. Graphical User Interface Navigating in the Main Window Figure 2 6 Organizing Files in Tab Groups amp C madeltech examples memory verilog dp syn ram 4 ln 00000000 00010001100101000 E l Copyright Model Technology 00000001 OOOO00000000000111 oo000002 OooOoOooooOoOOOOOO0011 00000003 00111011001111010 OO000004 xxxxxxxxxxxxxxxxx OOOO000S xxxxxxxxxxxxxxxxx Corporation company Z004 2 3 4 timescale lns lns 5 module idp syn ram rtl 6 8 fiparameter data width 8 00000006 xxxxxxxxxxxxxxxxx parameter addr width 3 00000007 XxXXXXXXXXXXXXXXXX input addr width 1 0 i 00000008 xxxxxxxXXxxxxxxxxx 9 input addr width 1 0 o 00000009 xxxxxxxxxxxxxxxxx 10 input data width 1 0 d o000000a xxxxxxxxxxxxxxxxx 11 input i O000000b XXXXXXXXXXXXXXXXX lz input o 0000000c xxxxxxxxxxXxxxXxxx Ii So mpi Y RECA Tren nem nf The commands for creating and organizing tab groups are accessed by right clicking on any window tab The table below describes the commands associated with tab groups Table 2 4 Commands for Tab Groups Command Description New Tab Group Creates a new tab group containing the selected tab Move Next Group Moves the selected tab to the next group in the MDI Move Prev Group Moves the selected tab to the previous group in the MDI View gt Vertical Arranges tab groups top to bottom vertical or Horizontal right to left horiz
184. HDL code library modelsim lib use modelsim lib util all The Verilog tasks and SystemC functions are available as built in System Tasks and Functions Table 11 1 Signal Spy Reference Comparison Refer to VHDL procedures Verilog system tasks SystemC function disable signal spy disable signal spy disable signal spy disable signal spy enable signal spy enable signal spy enable signal spy enable signal spy init signal driver init signal driver init signal driver init signal driver init signal spy init signal spy Sinit signal spy init signal spy signal force signal force signal force signal force signal release signal release signal release signal release Designed for Testbenches Signal Spy limits the portability of your code HDL code with Signal Spy procedures or tasks works only in Questa and Modelsim We therefore recommend using Signal Spy only in ModelSim User s Manual v6 3g 293 May 2008 Signal Spy testbenches where portability is less of a concern and the need for such a tool is more applicable 294 ModelSim User s Manual v6 3g May 2008 Signal Spy disable_signal_spy disable signal spy This reference section describes the following e VHDL Procedure disable signal spy e Verilog Task disable signal spy e SystemC Function disable signal spy The disable signal spy call disables the associated init signal spy
185. IRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTIOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 1990 David Koblas Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation This software is provided as is without express or implied warranty 1998 Hutchison Avenue Software Corporation Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation This software is provided AS IS The Hutchison Avenue Software Corporation disclaims all warranties either express or implied including but not limited to implied warranties of merchantability and fitness for a particular purpose with respect to this code and accompanying documentation 2001 Apple Computer Inc The following terms apply to all files originating from Apple Computer Inc Apple and associated with the software unless explicitly disclaimed in individual
186. ISE MUERE RE REPE e PE EE ME 237 Adding Objects to the Wave or List Window 0 0 cece eee eee nee 237 Adding Objects with Drag and Drop 2 130046 te Rx RERREWeRXY RP4 a RESEEYaG ne 238 Adding Objects with Menu Selections 0 0 cee cece eee eee eens 238 Adding Objects with aCommand 0 cece eee ene ene 238 Adding Objects with a Window Format File 1 2 2 nananana cece eee 238 Measuring Time with Cursors in the Wave Window 0 cee eee eee eee 239 Cursor and Timeline Toolbox ia eon ekenee prd RE IeREREREREERR E RE nc ERA RP RO d 239 Working with Cursors isse he RE RR ERREUR ROGA RODEO ES REOR ERROR Oe awe 241 Understanding Cursor BehavioE 320 9 x kaa TERRE ERR HRUA RA ESR ESS 242 Jumping to a Signal Transition esi i eR R4 RRE EE RR RESAOESe Ser ER 243 Setting Time Markers in the List Window eleleeeee eee 243 Working with Markers 4 asa ea acc ROC e ox e e oC ROC Roe ROLE e e LRL qoe acre es 244 Zooming the Wave Window Display lesser 244 Zooming with the Menu Toolbar and Mouse lseleeeeeeeeeeee 244 Saving Zoom Range and Scroll Position with Bookmarks 0000 245 Searching in the Wave and List Windows 0 0 c cece eee eee eee eh 247 Finding Signal Names olecuu ieee RR RR RPG rH ERA ERA qur HR XR aa Rd 247 Searching Tor Values or DERDSIDIONS slg as ue ov ET Gea SS RSH AES oS dea 247 Using the Expression Builder for Expre
187. Jee BeN p test sm into p est sm outof 4 jtest sm rst 34 test sm clk 1 test sm rd O test_sm vr_ 4 jtest sm clk 4 4 33 downto 2 test sm i 4 4 18800 ps to 23200 ps Now 750 ns Delta 2 Virtual Signals Virtual signals are aliases for combinations or subelements of signals written to the WLF file by the simulation kernel They can be displayed in the Objects List and Wave windows accessed by the examine command and set using the force command You can create virtual signals using the Tools gt Combine Signals Wave and List windows menu selections or by using the virtual signal command Once created virtual signals can be dragged and dropped from the Objects pane to the Wave and List windows Virtual signals are automatically attached to the design region in the hierarchy that corresponds to the nearest common ancestor of all the elements of the virtual signal The virtual signal command has an install lt region gt option to specify where the virtual signal should be installed This can be used to install the virtual signal in a user defined region in order to reconstruct the original RTL hierarchy when simulating and driving a post synthesis gate level implementation A virtual signal can be used to reconstruct RTL level design buses that were broken down during synthesis The virtual hide command can be used to hide the display of the broken down bits if you don t want them clutt
188. L_TECH vital2000 others This variable points to another modelsim ini file whose library path variables will also be read the pathname must include modelsim ini only one others variable can be specified in any modelsim ini file e Value Range any valid path may include environment variables Default none Verilog Compiler Control Variables You can find these variables under the heading vlog in the modelsim ini file CoverCells This variable when on enables code coverage of Verilog modules defined by celldefine and endcelldefine compiler directives or compiled with the v or y arguments to the vlog command e Value Range 0 1 e Default 0 code coverage off ModelSim User s Manual v6 3g 371 May 2008 Simulator Variables Simulator Control Variables DisableOpt This variable when on disables all optimizations enacted by the compiler same as the O0 argument to vlog e Value Range 0 1 e Default off 0 GenerateLooplterationMax This variable specifies the maximum number of iterations permitted for a generate loop restricting this permits the implementation to recognize infinite generate loops e Value Range natural integer 2 0 Default 100000 GenerateRecursionDepthMax This variable specifies the maximum depth permitted for a recursive generate instantiation restricting this permits the implementation to recognize infinite recursions e Value Range natural integer 2 0 e Def
189. Libraries Verilog Resource Libraries ModelSim supports separate compilation of distinct portions of a Verilog design The vlog compiler is used to compile one or more source files into a specified library The library thus contains pre compiled modules and UDPs that are referenced by the simulator as it loads the design Resource libraries are specified differently for Verilog and VHDL For Verilog you use either the L or Lf argument to vlog Refer to Library Usage for more information The LibrarySearchPath variable in the modelsim ini file in the vlog section can be used to define a space separated list of resource library paths This is identical behavior with the L argument for the vlog command LibrarySearchPath lt path gt libl lt path gt lib2 lt path gt 1ib3 The default for LibrarySearchPath is MODEL_TECH avm VHDL Resource Libraries Within a VHDL source file you use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit t does not extend to the next design unit in the file Note that the library clause is not used to specify the working library into which the design unit is placed after compilation The vcom command adds compiled design units to the curren
190. NU Free Documentation License install directory2 docs legal gnu free doc 1 1 pdf e This software application may include MinGW gcc third party software portions of which are licensed under the GNU Library General Public License v 2 To obtain original source code of MinGW gcc or modifications made if any send a request to request sourcecode mentor com Software distributed under the Library General Public License is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU Library General Public License install directory docs legal gnu library gpl 2 0 pdf This software application may include MinGW gcc third party software portions of which are licensed under the GNU Lesser General Public License v 2 1 To obtain original source code of MinGW gcc or modifications made if any send a request to request sourcecode mentor com Software distributed under the LGPL is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU Lesser General Public License install directory docs legal gnu lgpl 2 1 pdf Copyright c 1982 1986 1992 1993 The Regents of the University of
191. O Files Tcl Examples Arithmetic Table 14 7 Tcl Time Arithmetic Commands Command Description addTime lt time gt lt time gt add time divTime lt time gt lt time gt 64 bit integer divide mulTime lt time gt lt time gt 64 bit integer multiply subTime lt time gt lt time gt subtract time Tcl Examples Example 14 1 uses the Tcl while loop to copy a list from variable a to variable b reversing the order of the elements along the way Example 14 1 Tcl while Loop set b list set i expr llength a 1 while i gt 0 lappend b lindex Sa i incr i 1 Example 14 2 uses the Tcl for command to copy a list from variable a to variable b reversing the order of the elements along the way Example 14 2 Tcl for Command set b list for set i expr llength a 1 i gt 0 incr i 1 lappend b lindex Sa i Example 14 3 uses the Tcl foreach command to copy a list from variable a to variable b reversing the order of the elements along the way the foreach command iterates over all of the elements of a list Example 14 3 Tcl foreach Command set b list foreach i a set b linsert b 0 i Example 14 4 shows a list reversal as above this time aborting on a particular element using the Tcl break command ModelSim User s Manual v6 3g 355 May 2008 Tcl and Macros DO Files Tcl Examples Example 14 4 Tcl break Command set b list fo
192. Precedence Note that some variables can be set in a modelsim file Registry in Windows or a ini file A variable set in the modelsim file takes precedence over the same variable set in a ini file For example assume you have the following line in your modelsim ini file TranscriptFile transcript And assume you have the following line in your modelsim file set PrefMain file 402 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator State Variables In this case the setting in the modelsim file overrides that in the modelsim ini file and a transcript file will not be produced Simulator State Variables Unlike other variables that must be explicitly set simulator state variables return a value relative to the current simulation Simulator state variables can be useful in commands especially when used within ModelSim DO files macros The variables are referenced in commands by prefixing the name with a dollar sign argc This variable returns the total number of parameters passed to the current macro architecture This variable returns the name of the top level architecture currently being simulated for a configuration or Verilog module this variable returns an empty string configuration This variable returns the name of the top level configuration currently being simulated returns an empty string if no configuration delta This variable returns the number of the current simulato
193. Quit wlfdeleteonquit WLFDeleteOnQuit 0l1 0 wlfnodeleteonquit WLF Cache Size Wlfcachesize n WLFCacheSize n 0 no reader cache WLF Sim Cache Size wlfsimcachesize n WLFSimCacheSize n 0 no reader cache WLF Collapse Mode wlfnocollapse WLFCollapseModel OI112 1 wlfcollapsedelta wlfcollapsetime 1 These parameters can also be set using the dataset config command e WLF Filename Specify the name of the WLF file e WLF Size Limit Limit the size of a WLF file to n megabytes by truncating from the front of the file as necessary e WLF Time Limit Limit the size of a WLF file to lt t gt time by truncating from the front of the file as necessary ModelSim User s Manual v6 3g 221 May 2008 Recording Simulation Results With Datasets Saving a Simulation to a WLF File e WLF Compression Compress the data in the WLF file e WLF Optimization Write additional data to the WLF file to improve draw performance at large zoom ranges Optimization results in approximately 15 larger WLF files Disabling WLF optimization also prevents ModelSim from reading a previously generated WLF file that contains optimized data e WLF Delete on Quit Delete the WLF file automatically when the simulation exits Valid for current simulation dataset vsim wlf only e WLF Cache Size Specify the size in megabytes of the WLF reader cache WLF reader cache size is zero b
194. R IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE OpenSSL PROJECT OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE This software application may include modified Expat 2 0 third party software that may be subject to the following copyright s Copyright c 1998 1999 2000 Thai Open Source Software Center Ltd and Clark Cooper Copyright c 2001 2002 2003 2004 2005 2006 Expat maintainers Permission is hereby granted free of charge to any person obtaining a copy of this software and associated documentation files the Software to deal in the Software without restriction including without limitation the rights to use copy modify merge publish distribute sublicense and or sell copies of the Software and to permit persons to whom the Software is furnished to do so subject to the following conditions The above copyright notice and this permission notice shall be included in all copies or sub
195. RES 262 Saving List Window Data to a File leeeeeeeeeeeeee ne 262 Combining Objects into Buses 9o3 12v Rx deo eee bees ER P PERC REY I EE 263 Configuring New Line Triggering in the List Window 0 0 0 2 ee ee eee 264 Using Gating Expressions to Control Triggering 0 00 0 eee eee eee ee 267 Sampling Signals at a Clock Change 0 cece eee eee eens 268 Miscellaneous Vasks iua cuenca ehe ea 3 LER bI CERE EDUC ER eqs ed c 269 Examining Waveform Values 0 0 c eee eet eee teen eens 269 Displaying Drivers of the Selected Waveform 0 0 0 ce eee eee eee 269 Sorting a Group of Objects in the Wave Window 2 0 cee eee eee eee eee 269 Creating and Managing Breakpoints 0 0 cece eee ee eA 269 Signal Breakpoints 232 x ne zu rex e tear epi aee d oun eeu tease gees i qol once 269 File Line BreakpoinfSa c v he REPE ERR 2 SEE 54 eed hee eee SER E MC 272 Chapter 10 Debugging with the Dataflow Window ccc cece cece cece eee rnnt 275 Dataflow Window OvervieW 0 cece eee tenet n ent e ene 275 Dataflow Usage m 275 Post Simulation Debug Flow Details 0 0 0 0 cee eee ee eee 276 Common Tasks for Dataflow Debugging 0 0 eee eee 277 Adding Objects to the Dataflow Window 0 0 cece eee e 278 Exploring the Connectivity of the Design 0 0 0 cece eee eee 278 Exploring Designs with the Embedded Wave Viewer
196. RU REIN E oe RAUS oe M 326 Specifying the Wrong InstatiGe uas sucacwsacexo nunana 326 Mistaking a Component or Module Name for an Instance Label 327 Forgetting to Specify the Instance 2 5 6csses care nnan nee ar hk RR RE ERR 327 Chapter 13 Value Change Dump V CD EIlle 444 sx4 RERO DOES RI PPP ERR PO E LR x 329 Creatine d VOD PIG s pes su ceto pRS RE SUR EERE SG AREE E Pee Reb ER dg has 329 Flow for Four State VCD File sseleeeeeee III 329 Flow for Extended VCD File ora oom Fey ESCAPE RIDE b ee P E AA 330 Case Sensitivity 4 gic 485 epu ow D ooo d ge n ER e te or d a NO ANC SL YQ EROR Se 330 Using Extended VCD as SUmul S sscRRERATexEERRR e RR RWCRRERT RCCREEERAS 330 Simulating with Input Values from a VCD File 0 0 0 eee eee eee 331 Replacing Instances with Output Values from a VCD File 0004 332 VCD Commands and VCD Tasks 4 iis d4dyieesewg eb REX DEEERV A RR M ERSRER YE T REN 333 Using VCD Commands with SystemC vus dae ER anana CER CERA XE UPPER 334 Compressing Piles with VCD Tasks 2 02 2sced0edeshs445e oer eee sehen E Ex 335 VCD File from Source To O tpul idsd ese pu M x E kR ER Ra bees dd idR RE 335 VHDL Source 006 eses ses ect hee ees pot uc hi AE E RHE a a a pare and 336 VCD Simulator Commands 22 229 kk RR RR RR REG ORE REX REED RES 336 VCD OUP s 22 905 qe Ps reo P QE a a ei doo S He eg Rl decide ix 336 VCD t WLE i vzavael4d x ade eR RR ER AXE E Le d ades cdd ARLES 33
197. SCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1999 2000 Konstantin Chuguev All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMEN
198. SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE e This software application may include MinGW gcc third party software MinGW gcc is licensed under the GNU GPL v 2 To obtain original source code of MinGW gcc or modifications made if any send a request to request_sourcecode mentor com Software distributed under the GPL is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU GPL v 2 lt install_directory gt docs legal gnu_gpl_2 0 pdf e This software application may include MinGW gcc third party software portions of which are licensed under the GNU Free Documentation License v 1 1 To obtain original source code of MinGW gcc or modifications made if any send a request to request sourcecode mentor com Software distributed under the Free Documentation License is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the G
199. Steps vsim argument effect modelsim ini setting wlfnocollapse All events for each logged signal are WLFCollapseMode 0 recorded to the WLF file in the exact order they occur in the simulation wlfcollapsedelta Each logged signal which has events during a WLFCollapseMode 1 simulation delta has its final value recorded to the WLF file when the delta has expired Default wlfcollapsetime Same as delta collapsing but at the timestep WLFCollapseMode 2 granularity When a run completes that includes single stepping or hitting a breakpoint all events are flushed to the WLF file regardless of the time collapse mode It s possible that single stepping through part of a simulation may yield a slightly different WLF file than just running over that piece of code If particular detail is required in debugging you should disable time collapsing Virtual Objects Virtual objects are signal like or region like objects created in the GUI that do not exist in the ModelSim simulation kernel ModelSim supports the following kinds of virtual objects e Virtual Signals e Virtual Functions e Virtual Regions e Virtual Types Virtual objects are indicated by an orange diamond as illustrated by bus in Figure 8 6 ModelSim User s Manual v6 3g 229 May 2008 Recording Simulation Results With Datasets Virtual Objects Figure 8 6 Virtual Objects Indicated by Orange Diamond 15x File Edit view Add Format Tools Window
200. T OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 2003 Artem B Bityuckiy SoftMine Corporation Rights transferred to Franklin Electronic Publishers Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETH
201. THER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1987 Regents of the University of California All rights reserved Redistribution and use in source and binary forms are permitted provided that the above copyright notice and this paragraph are duplicated in all such forms and that any documentation advertising materials and other materials related to such distribution and use acknowledge that the software was developed by the University of California Berkeley The name of the University may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE Copyright c 1991 by AT amp T Permission to use copy modify and distribute this software for any purpose without fee is hereby granted provided that this entire notice is included in all copies of any software which is or includes a copy or modification of this software and in all copies of the supporting documentation for such software THIS SOFTWARE IS BEING PROVIDED AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY IN PARTICULAR NEITHER THE AUTHOR NOR AT amp T MAKES ANY REPRESENTATION OR WARRANTY OF AN
202. TIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will immediately terminate upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1 2 or 4 For any other material breach under this Agreement Mentor Graphics may terminate this Agreement upon 30 days written notice if you are in material breach and fail to cure such breach within the 30 day notice period If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States governme
203. The system searches for the mapping of a logical name in the following order First the system looks for a modelsim ini file If the system doesn t find a modelsim ini file or if the specified logical name does not e exist in the modelsim ini file the system searches the current working directory for a subdirectory that matches the logical name An error is generated by the compiler if you specify a logical name that does not resolve to an existing directory Moving a Library Individual design units in a design library cannot be moved An entire design library can be moved however by using standard operating system commands for moving a directory or an archive Setting Up Libraries for Group Use By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the tool does not find a mapping in the modelsim ini file then it will search the library section of the initialization file specified by the others clause For example library asic_lib work my_work usr modeltech modelsim ini cae asic lib others You can specify only one others clause in the library section of a given modelsim ini file The others clause only instructs the tool to look in the specified modelsim ini file for a library it does not load any other part of the specified file ModelSim User s Manual v6 3g May 2008 134 Design Libraries Specifying Resource Libraries Specifying Resource
204. UI Window Pane 2022454 424 o4e0sn8e bene A RRERGAES d ERIPAREd Aa RE RE 459 Figure E 3 GUE Double Bar 252i RR ER RR RR RA RR EE RYE RE 460 Figure E 4 GUI Undock Button os edu eda px ERES dene Rb a er Re E ARR 460 Figure E 5 GUI Dock BUHONIL dues whewbbeE A der eR dE E dare Ep be 460 Figure E 6 GUI Zoom BUllOl cu ber er Retibcdu RE ARP er RO tREQea PETRI ES ed 460 Figure E 7 GUI Unzoom Button edes Ererenreek 4 ERERRESWE RENT RARE E XR eee 461 Figure E 8 Toolbar Manipulation sleleseeeeee II 461 Figure E 9 Change Text Fonts for Selected Window eseleleeeeeeees 463 Figure E 10 Making Global Font Changes 0 0 eese 463 Figure E 11 Preferences Dialog Box By Name Tab 0 0 0 0 0 eee eee 464 ModelSim User s Manual v6 3g 19 May 2008 List of Tables Table 1 1 Simulation Tasks ModelSim ceo be cadena beeen eee ve esas 25 Table 1 7 Use Modes 14 14g e564 aG edge eke X VEGA Lae eae Whew RU OR CR Gage KS 29 Table 1 3 Definition of Object by Language sseleeee ee 31 Table 1 4 Text C OlVelill olus ebacsx 2a exe RE RATE GG EEG a e RES EA RS 33 Table 1 5 Deprecated Commands 2 42224 epe ES RR RRERWEERR E ER RI RE ERA dre 34 Table 1 6 Deprecated Command Arguments 0 0 ee eee 34 Table 1 7 Deprecated modelsim ini Variables llle 34 Table 2 1 GUI Windows and Panes ew vr hme wr SERRE RR IR RR 36 Table 2 2 Design Object Icons lese R RR DR
205. VEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 2000 2001 Alexey Zelkin phantom FreeBSD org gt All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright C 1997 by Andrey A Chernov Moscow Russia All rights reserved Redistribution and use in source and bi
206. VHDL You should specify the coarsest value for time resolution that does not result in undesired rounding of your delay times The resolution value should not be unnecessarily small because it decreases the maximum simulation time limit and can cause longer simulations Default Binding By default ModelSim performs binding when you load the design with vsim The advantage of this default binding at load time is that it provides more flexibility for compile order Namely VHDL entities don t necessarily have to be compiled before other entities architectures that instantiate them However you can force ModelSim to perform default binding at compile time instead This may allow you to catch design errors e g entities with incorrect port lists earlier in the flow Use one of these two methods to change when default binding occurs e Specify the bindAtCompile argument to vcom e Set the BindAtCompile variable in the modelsim ini to 1 true Default Binding Rules When searching for a VHDL entity to bind with ModelSim searches the currently visible libraries for an entity with the same name as the component ModelSim does this because IEEE 1076 1987 contained a flaw that made it almost impossible for an entity to be directly visible if ModelSim User s Manual v6 3g 145 May 2008 VHDL Simulation Simulating VHDL Designs it had the same name as the component In short if a component was declared in an architecture any like named enti
207. Value Range 0 1 e Default 1 on Only for Linux or Solaris systems with more than one processor Setting Simulator Control Variables With The GUI Changes made in the Runtime Options dialog are written to the active modelsim ini file if it is writable and affect the current session as well as all future sessions If the file is read only the changes affect only the current session The Runtime Options dialog is accessible by selecting Simulate Runtime Options in the Main window The dialog contains three tabs Defaults Assertions and WLF Files The Defaults tab includes these options ModelSim User s Manual v6 3g 395 May 2008 Simulator Variables Simulator Control Variables Figure A 1 Runtime Options Dialog Defaults Tab Runtime Options E 215 xl Defaults Assertions WLF Files gt Default Radix Suppress Warnings C Seid From Synopsys Packages m ES From lEEE Numeric Std Packages C Binary c e i Default Run Default Force Type ecima C C Unsigned C im C Hexadecimal erie c epos C ASCII 5000 Default based on type OK Cancel Apply e Default Radix Sets the default radix for the current simulation run You can also use the radix command to set the same temporary default The chosen radix is used for all commands force examine change are examples and for displayed values in the Objects Locals Dataflow List and Wave windows The corresponding modelsim ini var
208. Verilog Syntax init signal spy src object dest object verbose control state SystemC Syntax init signal spy src object dest object lt verbose gt control state ModelSim User s Manual v6 3g 303 May 2008 Signal Spy init_signal_spy Returns Nothing Arguments src object Required string A full hierarchical path or relative downward path with reference to the calling block to a VHDL signal or Verilog register net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog register Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the src_object s value is mirrored onto the dest_object 0 Does not report a message Default Reports a message e control state Optional integer Possible values are 1 0 or 1 Specifies whether or not you want the ability to enable disable mirroring of values and if so specifies the initial state no a
209. WARE This software application may include crypto third party software 1999 The OpenSSL Project All rights reserved 1999 Bodo Moeller All rights reserved 1995 1998 Eric Young All rights reserved 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this software must display the following acknowledgment This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit http www OpenSSL org 4 The names OpenSSL Toolkit and OpenSSL Project must not be used to endorse or promote products derived from this software without prior written permission For written permission please contact licensing 9 OpenSSL org 5 Products derived from this software may not be called OpenSSL nor may OpenSSL appear in their names without prior written permission of the OpenSSL Project 6 Redistributions of any form whatsoever must retain the following acknowledgment This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit http www OpenSSL org THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT AS IS AND ANY EXPRESSED O
210. WIDTH 4 parameter DEBUG 0 reg 3 0 d reg clk dff4 d4 q clk ad assign err 0 initial begin Sdump_all_vpi Sdump_tree_vpi test_dff4 Sdump_tree_vpi test_dff4 d4 Sdump_tree_vpi test_dff4 Sdump_tree_vpi test_dff4 d Sdump_tree_vpi test_dff4 d4 d0 Sdump_tree_vpi test_dff4 d4 Sdump_tree_vpi test_dff4 d4 q end endmodule module dff4 output 3 0 q input clk test_dff4 clk test dff4 q test dff4 d4 833 test dff4 d4 clk input 3 0 d pragma protect data method aes128 cbc pragma protect author IP Provider pragma protect author info Widget 5 version 3 2 pragma protect key keyowner MTI key method rsa pragma protect key keyname MGC DVT MTI pragma protect begin dff gate dO q 0 clk d 0 dff gate dl q 1 clk d 1 ModelSim User s Manual v6 3g May 2008 105 Protecting Your Source Code Creating an Encryption Envelope dff_gate d2 q 2 clk dff gate d3 q 3 clk endmodule dff4 module dff_gate output q wire preset 1 wire clear 1 nand 5 gl ll preset 14 12 g2 12 11 clear clk g3 1 g4 Bd Ay CLK LAY 4 13 clear d g5 q preset l12 qbar g6 qbar q clear 13 endmodule pragma protect end input clk input d Example 3 2 Encryption Envelope Contains include Compiler Directives timescale ins 1ps
211. WT BLK 3 11 5b00010000000 WT BLK 4 11 5b00100000000 WT BLK 5 11 5b01000000000 RD WD 1 11 b10000000000 RD WD 2 default hex Figure 2 2 shows an FSM signal called test sm sm_seqO sm_O state in the Wave window with a binary radix and with the user defined States radix as defined in Example 2 1 Figure 2 2 User Defined Radix States in the Wave Window E jtest_smjsm_seqO sm_Ojstate 00000001000 E jtest_sm sm_seqO sm_Ojstate WT_WD_2 Now 1000000 ps ra ve Figure 2 3 shows an FSM signal called test sm sm_seqO sm_O state in the List window with a binary radix and with the user defined States radix as defined in Example 2 1 Figure 2 3 User Defined Radix States in the List Window psy ftest_sm sm_seq0 sm_0 state delta ftest_sm sm_seq0 sm_0 statey 291000 0 00001000000 WT_BLK_3 311000 0 00010000000 WT_BLK_4 331000 0 00100000000 WT BLK 5 351000 0 oooo00000001 IDLE 44 lines x ModelSim User s Manual v6 3g 39 May 2008 Graphical User Interface Main Window Main Window The primary access point in the ModelSim GUI is called the Main window It provides convenient access to design libraries and objects source files debugging commands simulation status messages etc When you load a design or bring up debugging tools ModelSim adds panes or opens windows appropriate for your debugging environment Figure 2 4 File Edit View Format Compile
212. Y KIND CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE Copyright c 2001 Christopher G Demetriou All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY
213. a delay solution is found If a timing check in the design was zeroed because a delay solution was not found a summary message like the following will be issued Warning vsim 3316 No solution possible for some delayed timing check nets 1 negative limits were zeroed Use ntc warn for more info Invoking vsim with the ntc_warn option identifies the timing check that is being zeroed Finally consider the case where the RST and D timing check is specified on the posedge RST setuphold posedge CLK D 10 20 notifier dCLK dD setuphold posedge CLK negedge RST 40 50 notifier dCLK dRST setuphold posedge RST D 1 1 notifier dRST dD 0 10 20 30 45 RST violation VVVVVVVAVVVAVVAA D violation XXXXXXXXXX CLK 4 D violation XX RST In this case the delay solution converges when an rising delay on dRST is used Rising Falling dCLK 31 31 ModelSim User s Manual v6 3g 199 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Rising Falling dD 20 20 dRST 20 10 0 10 21 23 30 40 45 RST violation VAVVVVAVAAVVAVAN D violation XXXXXXXXXX CLK D violation XX RST Using Delayed Inputs for Timing Checks By default ModelSim performs timing checks on inputs specified in the timing check If you want timing checks performed on the delayed inputs use the delayed_timing_checks argument to vsim Consider an example This timing check set
214. a wait statement warnings e Value Range 0 1 e Default on 1 Show Warning3 This variable enables null range warnings e Value Range 0 1 e Default on 1 Show Warning4 This variable enables no space in time literal warnings e Value Range 0 1 e Default on 1 Show Warning5 This variable enables multiple drivers on unresolved signal warnings e Value Range 0 1 e Default on 1 Show Warning9 This variable enables warnings about signal value dependency at elaboration e Value Range 0 1 e Default on 1 Show_Warning10 This variable enables warnings about VHDL 1993 constructs in VHDL 1987 code e Value Range 0 1 e Default on 1 ModelSim User s Manual v6 3g 379 May 2008 Simulator Variables Simulator Control Variables Show_WarnLocallyStaticError This variable enables warnings about locally static errors deferred until run time e Value Range 0 1 e Default on 1 VHDL93 This variable enables support for VHDL 1987 where 1 enables support for VHDL 1993 and 2 enables support for VHDL 2002 e Value Range 0 1 2 e Default 2 DpiOutOfTheBlue This variable enables DPI out of the blue calls from C functions must not be declared as import tasks or functions For more information see Making Verilog Function Calls from non DPI C Models e Value Range 0 1 e Default 0 Support for out of the blue DPI calls is disabled Simulation Control Variables You can find these variables
215. able 377 Now simulator state variable 404 now simulator state variable 404 null value debugging 190 numeric bit package 136 numeric std package 136 disabling warning messages 401 NumericStdNoWarnings ini file variable 388 0 object defined 30 Object handle initialize with new function 190 objects virtual 229 Objects window 62 see also windows Objects window OnFinish ini file variable 388 operating systems supported See Installation Guide optimizations VHDL subprogram inlining 140 Optimize_1164 ini file variable 377 ordering files for compile 116 organizing projects with folders 123 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I organizing windows MDI pane 42 others ini file variable 371 overview simulation tasks 24 p packages standard 135 textio 135 util 155 VITAL 1995 153 VITAL 2000 153 page setup Dataflow window 289 Wave window 262 pan Dataflow window 290 panes docking and undocking 459 Memory panes 58 parameters making optional 359 using with macros 358 path delay mode 204 path delays matching to DEVICE statements 321 path delays matching to GLOBALPATHPULSE statements 321 path delays matching to IOPATH statements 320 path delays matching to PATHPULSE statements 321 pathnames hiding in Wave window 251 PATHPULSE matching to specify path delays 321 PathSeparator ini file variable 389 PedanticErrors ini file variable 377 perf
216. able 8 2 Structure Tab Columns Column name Description Instance the name of the instance Design unit the name of the design unit Design unit type the type e g Module Entity etc of the design unit You can hide or show columns by right clicking a column name and selecting the name on the list Managing Multiple Datasets GUI When you have one or more datasets open you can manage them using the Dataset Browser To open the browser select File gt Datasets Figure 8 4 The Dataset Browser LT x r Dataset_ Context Mode_ _ Pathname compare gold test sm View gold wif J sim test_sm Simulation vsim wlf J ee pl Open SaveAs Close Make Active Rename Done Command Line You can open multiple datasets when the simulator is invoked by specifying more than one vsim view filename option By default the dataset prefix will be the filename of the WLF ModelSim User s Manual v6 3g 225 May 2008 Recording Simulation Results With Datasets Managing Multiple Datasets file You can specify a different dataset name as an optional qualifier to the vsim view switch on the command line using the following syntax view lt dataset gt lt filename gt For example vsim view foo vsim wlf ModelSim designates one of the datasets to be the active dataset and refers all names without dataset prefixes to that dataset The active dataset is displayed in the context path at the
217. ach this count for the limit to take effect For example if you are collecting toggle data on Q gt 1 and 1 gt 0 transitions both transition counts must reach the limit If you are collecting full data on 6 edge transitions all 6 must reach the limit If the limit is set to zero then it is treated as unlimited e Value Range 0 or positive integer up to max positive value of 32 bit signed integer e Default 1 ToggleMaxintValues This variable sets the maximum number of VHDL integer values to record with toggle coverage e Value Range positive integer Default 100 ModelSim User s Manual v6 3g 391 May 2008 Simulator Variables Simulator Control Variables ToggleVlogintegers This variable controls toggle coverage for Verilog integer types except for enumeration types e Value Range 0 1 e Default off 0 ToggleWidthLimit This variable limits the width of signals that are automatically added to toggle coverage with the cover t argument for vcom or vlog The limit applies to Verilog registers and VHDL arrays A value of 0 is taken as unlimited e Value Range 0 or positive integer up to max positive value of 32 bit signed integer Default 128 TranscriptFile This variable specifies a file for saving command transcript You can specify environment variables in the pathname e Value Range any valid filename e Default transcript UnbufferedOutput This variable controls VHDL and Verilog files o
218. ad of time with vsim dpiexportobj export object file In this case you must manually integrate the resulting object code into the simulation by non standard means described as follows Link the exportwrapper object file export object file directly into a shared object containing the DPI import code and then load the shared object with sv lib This process can only work in simple scenarios specifically when there is only one sv_lib library that calls exported SystemVerilog tasks or functions Use the vsim gblso switch to load the export object file before any import shared objects are loaded This is the more general approach When you manually integrate the DPI export object file into the simulation database the normal automatic integration flow must be disabled by using the vsim nodpiexports option Another reason you may want to use this process is to simplify the set of shared objects that the OS is required to keep track of ModelSim User s Manual v6 3g 425 May 2008 Verilog PLI VPI DPI DPI Use Flow When Your DPI Export Function is Not Getting Called This issue can arise in your C code due to the way the C linker resolves symbols It happens if a name you choose for a SystemVerilog export function happens to match a function name in a custom or even standard C library In this case your C compiler will bind calls to the function in that C library rather than to the export function in the SystemVerilog simula
219. add mem lt instance gt at the vsim command prompt Viewing Multiple Memory Instances You can view multiple memory instances simultaneously A memory tab appears in the MDI frame for each instance you double click in the Memory list When you open more than one tab for the same memory the name of the tab receives an numerical identifier after the name such as 2 Figure 2 15 Viewing Multiple Memories z memory ram_tb spram mem 00000000 00101000 00101001 00101010 00101011 00101100 00101101 00101110 Bo000007 00101111 00110000 00110001 00110010 00110011 00110100 00110101 OO00000e 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00000015 00111101 00111110 00111111 01000000 01000001 01000010 01000011 OO00001e 1000100 01000101 01000110 01000111 01001000 01001001 01001010 00000023 01001011 01001100 01001101 01001110 01001111 01010000 01010001 00000028 01010010 01010011 01010100 01010101 01010110 01010111 01011000 00000031 701011001 01011010 01011011 01011100 01011101 01011110 01011111 00000038 01100000 01100001 01100010 01100011 01100100 01100101 01100110 nnnnnn r COi100814 01308 nn 0143608 1 D1308 08 0 0308083 083043 00 0433 083 013 Ast LE ren Ern Ea See Organizing Windows with Tab Groups for more information on tabs 60 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Memory Panes Saving Memory Formats in a DO File You can save all open memory instances and their forma
220. aded but before any simulation events take place The sdf_annotate task annotates the design at the time it is called in the Verilog source code This provides more flexibility than the command line options 318 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation sdf_annotate sdf_annotate Syntax sdf_annotate lt sdffile gt lt instance gt lt config_file gt lt log_file gt lt mtm_spec gt lt scale_factor gt lt scale_type gt Arguments lt sdffile gt String that specifies the SDF file Required lt instance gt Hierarchical name of the instance to be annotated Optional Defaults to the instance where the sdf_annotate call is made lt config_file gt String that specifies the configuration file Optional Currently not supported this argument is ignored log file gt String that specifies the logfile Optional Currently not supported this argument is ignored mtm spec String that specifies the delay selection Optional The allowed strings are minimum typical maximum and tool control Case is ignored and the default is tool control The tool control argument means to use the delay specified on the command line by mindelays typdelays or maxdelays defaults to typdelays lt scale_factor gt String that specifies delay scaling factors Optional The format is lt min_mult gt lt typ_mult gt lt
221. al envelopes The protected envelopes usage model as presented in Annex H section H 3 is the recommended methodology for users of Verilog s pragma protect compiler directives We recommend that you obtain these specifications for reference ModelSim also supports encryption of VHDL files using the vcom nodebug command Usage Models for Protecting Source Code ModelSim s encryption capabilities support the following usage models for IP vendors and their customers e P vendors may use the vencrypt utility to deliver Verilog and SystemVerilog code containing undefined macros and directives The IP user can then define the macros and directives and use the code in a wide range of EDA tools and design flows e IP vendors may use protect pragmas to protect Verilog and SystemVerilog code containing vendor defined macros and directives The IP code can be delivered to IP customers for use in a wide range of EDA tools and design flows e JP vendors and IP users may use the ModelSim specific protect endprotect compiler directives to define regions of Verilog and SystemVerilog code to be protected The code is then compiled with the vlog protect command and simulated with ModelSim The vencrypt utility may be used if the code contains undefined macros or directives but the code must then be compiled and simulated with ModelSim ModelSim User s Manual v6 3g 97 May 2008 Protecting Your Source Code Usage Models for Protecting
222. ally works fine if the libraries are created and used on a single system However when multiple systems access a library across a network the physical pathnames are not always the same and the source file reference rules do not always work Using Location Mapping Location maps are used to replace prefixes of physical pathnames in the library with environment variables The location map defines a mapping between physical pathname prefixes and environment variables ModelSim tools open the location map file on invocation if the MGC_LOCATION_MAP environment variable is set If MGC LOCATION MAP is not set ModelSim will look for a file named mgc_location_map in the following locations in order e the current directory e your home directory e the directory containing the ModelSim binaries e the ModelSim installation directory Use these two steps to map your files ModelSim User s Manual v6 3g 405 May 2008 Location Mapping Referencing Source Files with Location Maps 1 Set the environment variable MGC LOCATION MAP to the path of your location map file 2 Specify the mappings from physical pathnames to logical pathnames SSRC home vhdl src usr vhdl src SIEEE usr modeltech ieee Pathname Syntax The logical pathnames must begin with and the physical pathnames must begin with The logical pathname is followed by one or more equivalent physical pathnames Physical pathnames are equivalent if they refer to the same p
223. ame to the library Library Mapping from the Command Line You can set the mapping between a logical library name and a directory with the vmap command using the following syntax vmap lt logical_name gt lt directory_pathname gt You may invoke this command from either a UNIX DOS prompt or from the command line within ModelSim The vmap command adds the mapping to the library section of the modelsim ini file You can also modify modelsim ini manually by adding a mapping line To do this use a text editor and add a line under the Library section heading using the syntax lt logical_name gt lt directory_pathname gt More than one logical name can be mapped to a single directory For example suppose the modelsim ini file in the current working directory contains following lines Library work usr rick design my_asic usr rick design ModelSim User s Manual v6 3g 133 May 2008 Design Libraries Working with Design Libraries This would allow you to use either the logical name work or my_asic in a library or use clause to refer to the same design library Unix Symbolic Links You can also create a UNIX symbolic link to the library using the host platform command In s lt directory_pathname gt logical name The vmap command can also be used to display the mapping of a logical library name to a directory To do this enter the shortened form of the command vmap logical name Library Search Rules
224. ample below VHDL Syntax init signal driver src object dest object delay delay type lt verbose gt Verilog Syntax init signal driver src object dest object delay delay type lt verbose gt ModelSim User s Manual v6 3g 299 May 2008 Signal Spy init_signal_driver SystemC Syntax init_signal_driver lt src_object gt lt dest_object gt lt delay gt lt delay_type gt lt verbose gt Returns Nothing Arguments 300 src_object Required string A full hierarchical path or relative downward path with reference to the calling block toa VHDL signal Verilog net or SystemC signal Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal or Verilog net Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes ow delay Optional time value Specifies a delay relative to the time at which the src object changes The delay can be an inertial or transport delay If no delay is specified then a delay of zero is assumed delay type Optional del mode or integer Specifies the type of delay
225. an exception is thrown and thus the return code may be wrong The workaround is to avoid building the application using cygwin or to use the switch mno cygwin in cygwin the gcc command line systemf list_of_args This system function can take any number of arguments The list_of_args is treated exactly the same as with the display function The OS command that runs is the final output from display given the same list_of_args Return value of the systemf function is a 32 bit integer that is set to the exit status code of the underlying OS process ModelSim User s Manual v6 3g 213 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Note __ 4 There is a known issue in the return value of this system function on the win32 platform If the OS command is built with a cygwin compiler the exit status code may not be reported correctly when an exception is thrown and thus the return code may be wrong The workaround is to avoid building the application using cygwin or to use the switch mno cygwin in cygwin the gcc command line Supported Tasks that Have Been Extended The setuphold and recrem system tasks have been extended to provide additional functionality for negative timing constraints and an alternate method of conditioning as in Verilog XL See Negative Timing Check Limits Unsupported Verilog XL System Tasks The following system tasks are Verilog XL system tasks that are not implemented
226. an immediately solve problems caused by an improperly defined interface An example command for creating the header file would be vlog dpiheader lt dpiheaders gt h files v Required for Windows only Run a preliminary invocation of vsim with the dpiexportobj switch ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI DPI Use Flow Because of limitations with the linker loader provided on Windows this additional step is required You must create the exported task function compiled object file exportobj by running a preliminary vsim command such as vsim dpiexportobj exportobj top Include the dpiheader h file in your C code ModelSim recommends that any user DPI C code that accesses exported tasks functions or defines imported tasks functions should include the dpiheader h file This allows the C compiler to verify the interface between C and ModelSim Compile the C code into a shared object Compile your code providing any a or other o files required For Windows users In this step the object file needs to be bound together with the obj that you created using the dpiexportobj switch into a single dll file Simulate the design When simulating specify the name of the imported DPI C shared object according to the SystemVerilog LRM For example vsim sv_lib lt test gt top Integrating Export Wrappers into an Import Shared Object Some workflows require you to generate export tf wrappers ahe
227. and its contributors 4 Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 1999 America Online Inc 1998 Paul Duffin 2005 Tcl Core Team 1996 Lucent Technologies and Jim Ingham 1995 Dave Nebinger 1993 1994 Lockheed Missle amp Space Company AI Center 1995 Apple Computer Inc 2005 Daniel A Steffen lt das users sourceforge net gt 2001 Donal K Fellows 2003 2006 Patrick Thoyts 1998 Mark Harrison 2001 2002 David Gravereaux 1995 by General Electric Company All rights reserved 2000 Andreas Kupries 1993 1997 Bell Labs Innovat
228. and not have it be overwritten select the dataset tab in the Workspace and then select File Save Or you can use the wIf filename argument to the vsim command or the dataset save command 220 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Saving a Simulation to a WLF File Note If you do not use dataset save or dataset snapshot you must end a simulation session with a quit or quit sim command in order to produce a valid WLF file If you don t end the simulation in this manner the WLF file will not close properly and ModelSim may issue the error message bad magic number when you try to open an incomplete dataset in subsequent sessions If you end up with a damaged WLF file you can try to repair it using the wlfrecover command WLF File Parameter Overview There are a number of WLF file parameters that you can control via the modelsim ini file or a simulator argument This section summarizes the various parameters Table 8 1 WLF File Parameters Feature vsim argument Default WLF Filename wlf filename WLFFilename lt filename gt vsim wlf WLE Size Limit wlfslim lt n gt WLESizeLimit n no limit WLE Time Limit wlftlim lt t gt WLFTimeLimit lt t gt no limit WLE Compression wlfcompress WLFCompress OI1 1 wlfcompress wlfnocompress WLE Optimization wlfopt WLFOptmize 0l1 1 wlfopt wlfnoopt WLF Delete on
229. and vlog with the refresh argument to update Verilog design units By default the work library is updated Use either vcom or vlog with the work library argument to update a different library For example if you have a library named mylib that contains both VHDL and Verilog design units vcom work mylib refresh vlog work mylib refresh 136 ModelSim User s Manual v6 3g May 2008 Design Libraries Importing FPGA Libraries Note L L You may specify a specific design unit name with the refresh argument to vcom and vlog in order to regenerate a library image for only that design but you may not specify a file name An important feature of refresh is that it rebuilds the library image without using source code This means that models delivered as compiled libraries without source code can be rebuilt for a specific release of ModelSim In general this works for moving forwards or backwards on a release Moving backwards on a release may not work if the models used compiler switches directives language constructs or features that do not exist in the older release Note You don t need to regenerate the std ieee vital22b and verilog libraries Also you cannot use the refresh option to update libraries that were built before the 4 6 release Maintaining 32 and 64 bit Versions in the Same Library ModelSim allows you to maintain 32 bit and 64 bit versions of a design in
230. andard Delay Format SDF Timing Annotation sdf_annotate In this case the cell accommodates more accurate data than can be supplied by the tool that created the SDF file and both timing checks correctly receive the same value Likewise the SDF file may contain more accurate data than the model can accommodate Table 12 17 SDF Data May Be More Accurate Than Model SETUP posedge data posedge clock 4 setup data posedge clk 0 SETUP negedge data posedge clock 6 setup data posedge clk 0 In this case both SDF constructs are matched and the timing check receives the value from the last one encountered Timing check edge specifiers can also use explicit edge transitions instead of posedge and negedge However the SDF file is limited to posedge and negedge For example Table 12 18 Matching Explicit Verilog Edge Transitions to Verilog SETUP data posedge clock 5 setup data edge 01 Ox clk 0 The explicit edge specifiers are 01 Ox 10 1x x0 and x1 The set of 01 Ox x1 is equivalent to posedge while the set of 10 1x x0 is equivalent to negedge A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port Optional Conditions Timing check ports and path delays can have optional conditions The annotator uses the following rules to match conditions e A match occurs if the SDF does not have a condition e A match
231. angling pointers are easily created when using the TextIO package because WRITELINE de allocates the access type pointer that is passed to it Following are examples of good and bad VHDL coding styles Bad VHDL because L1 and L2 both point to the same buffer READLINE infile L1 Read and allocate buffer L2 L1 Copy pointers WRITELINE outfile L1 Deallocate buffer Good VHDL because L1 and L2 point to different buffers ModelSim User s Manual v6 3g 151 May 2008 VHDL Simulation TextlO Implementation Issues READLINE infile L1 Read and allocate buffer L2 new string Ll all Copy contents WRITELINE outfile L1 Deallocate buffer The ENDLINE Function The ENDLINE function described in the JEEE Standard VHDL Language Reference Manual IEEE Std 1076 1987 contains invalid VHDL syntax and cannot be implemented in VHDL This is because access values must be passed as variables but functions do not allow variable parameters Based on an ISAC VASG recommendation the ENDLINE function has been removed from the TextIO package The following test may be substituted for this function L NULL OR L LENGTH 0 The ENDFILE Function In the VHDL Language Reference Manuals the ENDFILE function is listed as function ENDFILE L in TEXT return BOOLEAN As you can see this function is commented out of the standard TextIO package This is because the ENDFILE functi
232. ap command to add library mappings to the current modelsim ini file Table A 1 Add Library Mappings to modelsim ini File Prompt Type Command Result added to modelsim ini DOS prompt vmap MY_VITAL MY_PATH MY VITAL c temp work ModelSim or vmap MY VITAL MY_PATH MY VITAL MY_PATH vsim prompt 1 The dollar sign character is Tcl syntax that indicates a variable The backslash character is an escape character that prevents the variable from being evaluated during the execution of vmap You can easily add additional hierarchy to the path For example vmap MORE_VITAL MY_PATH more_path and_more_path vmap MORE_VITAL MY_PATH more_path and_more_path Referencing Environment Variables There are two ways to reference environment variables within ModelSim Environment variables are allowed in a FILE variable being opened in VHDL For example 368 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables use std textio all entity test is end architecture only of test is begin process FILE in_file text is in SENV_VAR_NAME begin wait end process end Environment variables may also be referenced from the ModelSim command line or in macros using the Tcl env array mechanism echo env ENV VAR NAME Note Environment variable expansion does not occur in files that are referenced via the f argument to vcom vlog or vsim Removing Temp Files VSOUT The VSOUT temp fi
233. ard The attribute is also defined in package standard Using the definition from package standard Size of CHARACTER type In VHDL 87 type CHARACTER has 128 values in VHDL 93 it has 256 values Code which depends on this size will behave incorrectly This situation occurs most commonly in test suites that check VHDL functionality It s unlikely to occur in practical designs A typical instance is the replacement of warning message range nul downto del is null by range nul downto y is null range is nul downto y umlaut bit string literals In VHDL 87 bit string literals are of type bit vector In VHDL 93 they can also be of type STRING or STD LOGIC VECTOR This implies that some expressions that are unambiguous in VHDL 87 now become ambiguous is VHDL 93 A typical error message is Error bit string literal vhd 5 Subprogram is ambiguous Suitable definitions exist in packages std logic 1164 and standard Sub element association In VHDL 87 when using individual sub element association in an association list associating individual sub elements with NULL is discouraged In VHDL 93 such association is forbidden A typical message is Formal name must not be associated with OPEN when subelements are associated individually ModelSim User s Manual v6 3g 143 May 2008 VHDL Simulation Simulating VHDL Designs Simulating VHDL Designs A VHDL design is ready for simulation afte
234. are dif specifies the default file name for saving compare di defaultDiffsReportF compare txt the default file name for a compare differences repol defaultFast n defaultGoldDataset gold default name for the reference dataset in a waveforrr defaultHidelfMoDiffs 0 defaultlgnoreVerilo 1 setting to 1 specifies that Verilog net strengths shou defaultLeadTolera 0 specifies a time value to use for asynchronous comp defaultLeadUnits ns specifies the default units for lead tolerances range aj 2l DK Apply Cancel Clicking OK or Apply at the bottom of the Preferences dialog changes the variable and the change is saved when you exit ModelSim Saving GUI Preferences GUI preferences are saved automatically when you exit the tool If you prefer to store GUI preferences elsewhere set the MODELSIM PREFERENCES environment variable to designate where these preferences are stored Setting this variable causes ModelSim to use a specified path and file instead of the default location Here are some additional points to keep in mind about this variable setting e The file does not need to exist before setting the variable as ModelSim will initialize it e If the file is read only ModelSim will not update or otherwise modify the file e This variable may contain a relative pathname in which case the file is relative to the working directory at the time the tool is started 464 Mo
235. are written in compressed format e Value Range 0 1 e Default on 1 CommandHistory This variable specifies the name of a file in which to store the Main window command history e Value Range any valid filename e Default commented out ConcurrentFileLimit This variable controls the number of VHDL files open concurrently This number should be less than the current limit setting for max file descriptors e Value Range any positive integer or 0 unlimited Default 40 CoverCountaAll This variable applies to condition and expression coverage UDP tables If this variable is turned off 0 and a match occurs in more than one row none of the counts for all matching rows is incremented By default counts are incremented for all matching rows ModelSim User s Manual v6 3g 381 May 2008 Simulator Variables Simulator Control Variables e Value Range 0 1 e Default on 1 CoverOpt This variable controls the default level of optimizations for simulations running with code coverage e Value Range e Turns off all optimizations that affect coverage reports e 2 Allows optimizations that provide large performance improvements by invoking sequential processes only when the data changes Allows VHDL flip flop recognition This setting may result in major reductions in coverage counts e 3 Allows all optimizations in 2 and allows optimizations that may change expressions or remove some statements
236. argument or the PLIOBJS environment variable see Registering PLI Applications Support for VHDL Objects The PLI ACC routines also provide limited support for VHDL objects in either an all VHDL design or a mixed VHDL Verilog design The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants Table C 3 Supported VHDL Objects accArchitecture accArchitecture instantiation of an architecture ModelSim User s Manual v6 3g 439 May 2008 Verilog PLI VPI DPI Support for VHDL Objects accArchitecture Table C 3 Supported VHDL Objects accEntity VitalLevelO Description instantiation of an architecture whose entity is marked with the attribute VITAL LevelO accArchitecture accArchVitalLevelO instantiation of an architecture which is marked with the attribute VITAL LevelO accArchitecture accArchVitalLevell instantiation of an architecture which is marked with the attribute VITAL Levell accArchitecture accForeignArch instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics accArchitecture accForeignArchMixed instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics accBlock accBlock block statement accForLoop a
237. argument to vlog It reports the warning for any NULL module ports Suggested action If you wish to ignore this warning do not use the lint argument Lock message waiting for lock by user user Lockfile is lt library_path gt _lock Description The _lock file is created in a library when you begin a compilation into that library and it is removed when the compilation completes This prevents simultaneous updates to the library If a previous compile did not terminate properly ModelSim may fail to remove the _lock file Suggested action Manually remove the _lock file after making sure that no one else is actually using that library Metavalue detected warning Warning NUMERIC_STD gt metavalue detected returning FALSE Description This warning is an assertion being issued by the IEEE numeric_std package It indicates that there is an X in the comparison Suggested action The message does not indicate which comparison is reporting the problem since the assertion is coming from a standard package To track the problem note the time the warning occurs restart the simulation and run to one time unit before the noted time At this point start stepping the simulator until the warning appears The location of the blue arrow in a Source window will be pointing at the line following the line with the comparison These messages can be turned off by setting the NumericStdNoWarnings variable to 1 from the co
238. ase 314 ModelSim User s Manual v6 3g May 2008 Chapter 12 Standard Delay Format SDF Timing Annotation This chapter covers the ModelSim implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulator s built in SDF annotator Note SDF timing annotations can be applied only to your FPGA vendor s libraries all other libraries will simulate without annotation Specifying SDF Files for Simulation ModelSim supports SDF versions 1 0 through 4 0 except the NETDELAY statement The simulator s built in SDF annotator automatically adjusts to the version of the file Use the following vsim command line options to specify the SDF files the desired timing values and their associated design instances sdfmin lt instance gt lt filename gt sdftyp lt instance gt lt filename gt sdfmax lt instance gt lt filename gt Any number of SDF files can be applied to any instance in the design by specifying one of the above options for each file Use sdfmin to select minimum sdftyp to select typical and sdfmax to select maximum timing values from the SDF file Instance Specification The instance paths in the SDF file are relative to the instance to which the SDF is applied Usually this instance is an ASIC or FPGA model instantiated under a testbench
239. ase 3 If the design consists of modules with no timescale directives then the time units default to the value specified by the Resolution variable in the modelsim ini file The variable is set to 1 ps by default timescale Option The timescale option can be used with the vlog and vopt commands to specify the default timescale in effect during compilation for modules that do not have an explicit timescale directive The format of the timescale argument is the same as that of the timescale directive timescale lt time_units gt lt time_units gt where time units is n units The value of n must be 1 10 or 100 The value of units must be fs ps ns us ms or s In addition the time units must be greater than or equal to the time precision For example timescale Ins 1ps The argument above needs quotes because it contains white space Multiple Timescale Directives As alluded to above your design can have multiple timescale directives The timescale directive takes effect where it appears in a source file and applies to all source files which follow in the same vlog command Separately compiled modules can also have different timescales The simulator determines the smallest timescale of all the modules in a design and uses that as the simulator resolution timescale t and Rounding The optional vsim argument t sets the simulator resolution limit for the overall simulatio
240. atching specify statement is updated with the SDF timing value SDF constructs are matched to Verilog constructs as follows e IOPATH is matched to specify path delays or primitives Table 12 2 Matching SDF IOPATH to Verilog IOPATH posedge clk q 3 4 posedge clk gt q 0 IOPATH a y 3 4 buf ul y a The IOPATH construct usually annotates path delays If ModelSim can t locate a corresponding specify path delay it returns an error unless you use the sdf iopath to prim ok argument to vsim If you specify that argument and the module contains no path delays then all primitives that drive the specified output port are annotated e INTERCONNECT and PORT are matched to input ports Table 12 3 Matching SDF INTERCONNECT and PORT to Verilog INTERCONNECT Ur 2a 5 PORT Wa Both of these constructs identify a module input or inout port and create an internal net that is a delayed version of the port This is called a Module Input Port Delay MIPD All primitives specify path delays and specify timing checks connected to the original port are reconnected to the new MIPD net 320 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation sdf_annotate e PATHPULSE and GLOBALPATHPULSE are matched to specify path delays Table 12 4 Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog PATHPULSE a y 5 10 a 2 y 20 GLOBALPATHPULSE a y 30 60 a gt y 0
241. ates an error WRITE L 010101 This call is even more ambiguous because the compiler could not determine even if allowed to whether the argument 010101 should be interpreted as a string or a bit vector There are two possible solutions to this problem e Use a qualified expression to specify the type as in WRITE L string hello e Call a procedure that is not overloaded as in WRITE_STRING L hello The WRITE_STRING procedure simply defines the value to be a STRING and calls the WRITE procedure but it serves as a shell around the WRITE procedure that solves the overloading problem For further details refer to the WRITE_STRING procedure in the io_utils package which is located in the file lt install_dir gt modeltech examples misc io_utils vhd Reading and Writing Hexadecimal Numbers The reading and writing of hexadecimal numbers is not specified in standard VHDL The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group ISAC VASG has specified that the TextIO package reads and writes only decimal numbers To expand this functionality ModelSim supplies hexadecimal routines in the package io utils which is located in the file install dir modeltech examples misc io utils vhd To use these routines compile the io utils package and then include the following use clauses in your VHDL source code use std textio all use work io utils all Dangling Pointers D
242. ation task overview 24 simulations event order in 185 saving results 219 saving results at intervals 227 Simulator 363 simulator control with ini variables 395 simulator resolution returning as a real 155 Verilog 182 VHDL 144 simulator state variables 403 sizetf callback function 438 SKEW matching to Verilog 322 so shared object file loading PLI VPI DPI C applications 429 loading PLI VPI DPI C applications 431 source code security 101 104 source files referencing with location maps 405 source files specifying with location maps 405 source highlighting customizing 72 source libraries arguments supporting 177 Source window 63 colorization 72 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I tab stops in 72 see also windows Source window specify path delays matching to DEVICE construct 321 matching to GLOBALPATHPULSE construct 321 matching to IOPATH statements 320 matching to PATHPULSE construct 321 standards supported 31 startup environment variables access during 468 files accessed during 467 macro in the modelsim ini file 391 macros 401 startup macro in command line mode 29 using a startup file 401 Startup ini file variable 391 state variables 403 status bar Main window 44 Status field Project tab 120 std ini file variable 370 std arith package disabling warning messages 401 std developerskit ini file variable 370 std logic arith package 136 std logic si
243. ators such as ModelSim may process multiple events at a given simulation time The Verilog language is defined such that you cannot explicitly control the order in which simultaneous events are processed Unfortunately some designs rely on a particular event order and these designs may behave differently than you expect Event Queues Section 11 of the IEEE Std 1364 2005 LRM defines several event queues that determine the order in which events are evaluated At the current simulation time the simulator has the following pending events active events e inactive events e non blocking assignment update events ModelSim User s Manual v6 3g 185 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs monitor events e future events o inactive events o non blocking assignment update events The LRM dictates that events are processed as follows 1 all active events are processed 2 the inactive events are moved to the active event queue and then processed 3 the non blocking events are moved to the active event queue and then processed 4 the monitor events are moved to the active queue and then processed 5 simulation advances to the next time where there is an inactive event or a non blocking assignment update event Within the active event queue the events can be processed in any order and new active events can be added to the queue in any order In other words you cannot control event order within the activ
244. ault 200 Hazard This variable turns on Verilog hazard checking order dependent accessing of global variables e Value Range 0 e Default off 0 Incremental This variable activates the incremental compilation of modules e Value Range 0 1 e Default off 0 LibrarySearchPath This variable defines a space separated list of path entries which describe where to find a resource library containing a precompiled package The behavior of this variable is identical to using the L argument with the vlog command e Value Range any library path 372 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables e Default MODEL TECH avm MultiFileCompilationUnit Controls how Verilog files are compiled into compilation units Valid arguments e 1 On Compiles all files on command line into a single compilation unit This behavior is called Multi File Compilation Unit MFCU mode same as mfcu argument to e 0 Off Default value Compiles each file in the compilation command line into separate compilation units This behavior is called Single File Compilation Unit SFCU mode Refer to SystemVerilog Multi File Compilation Issues for details on the implications of these settings Note i The default behavior in versions prior to 6 1 was opposite of the current default behavior NoDebug This variable when on disables the inclusion of debugging info within design units
245. author IP Provider pragma protect author info Widget 5 version 3 2 pragma protect key keyowner MTI key method rsa pragma protect key keyname MGC DVT MTI pragma protect begin protected 108 ModelSim User s Manual v6 3g May 2008 Protecting Your Source Code Compiling a Design with vlog protect pragma protect encrypt agent Model Technology pragma protect encrypt_agent_info DEV pragma protect data method aes128 cbc pragma protect key keyowner MTI pragma protect key keyname MGC DVT MTI key method rsa pragma protect key block encoding enctype base64 RKFpQLpt 2PEyyIkeR8c5fhZi QTachzLFh2iCMuWJtVVd1l7ggjjfiCanXaBtpT3 xzgIx4frhkcZD2L6DphLZ0s6m9f1fi1808Ccs2V5u025U7Q2hpfCbLVsD80X1j0 g yxRAi2FdMyfJE31BcojE RGY2yv9kJePt6w7Qjdxm30o pragma protect data block encoding enctype base64 bytes 389 xHOWl19CUbo98hGy 6TWfMFwXc7T9T82m07WNv CqsJtjM6Pil41if6N70DBLJdqP 3QuIlZhwbrlM8kZFAyDHSS66qKJe5yLjGvezfrj GJp57vIKkAhaVAFI6LwPJJNu Ogr0Ohhj2WrfDwx4yCezZ4cOO0MUj2knUvs60ymXeAEzpNWGhpOMf2Bhc jUC55 M C nspNi0t2xSYtSM1IPpnOe8hIxT EYBIG6ENvr33A3kfOQEf4 0 B4kSRRKGVF 1MDN s9CQIpcezvQo0369q7at 6nKhgAt LuHhdCGsxGrinsXOhMQ2Rg9LR1 HISP5q 13g7 JEn103Bk8C9FAWO0SjK573t rT MSwOZkx SCSIqgl80kYaWg TDVPC7KLMkrRnaLx C5RIKwTkkZbeqGW3l1FDyWbluK9MiAxl3fOtWgGpOMbNpaJM33URFMk6dDKWSePTn ZvEARbYJhdA7arTOl6XCFpOgUABiaD3ihg78uysv3 FBOsN81MugtMVY AYAmdZQ E9xjlwhTpHEMMycw6T
246. ave window Show Drivers display driver s of the selected signal net or register in the Dataflow window Dataflow window Navigate Expand net to drivers Dataflow window Expand net to all drivers right mouse in wave pane Show Drivers 94 Restart reloads the design elements and resets the simulation time to zero with the option of keeping the current formatting breakpoints and WLF file Main menu Simulate Run Restart restart lt arguments gt ModelSim User s Manual v6 3g May 2008 Graphical User Interface Wave Window Table 2 11 Wave Window Toolbar Buttons and Menu Selections Menu equivalent Other options Run Main menu use the run command at the run the current simulation for Simulate gt Run gt Run VSIM prompt the default time length lt default_length gt Continue Run Main menu use the run continue continue the current Simulate gt Run gt command at the VSIM prompt simulation run Continue Run All Main menu use the run all command at run the current simulation Simulate gt Run gt Run the VSIM prompt forever or until it hits a All breakpoint or specified break event Break stop the current simulation run Find First Difference 3 find the first difference in a rm waveform comparison Find Previous Annotated Difference find the previous annotated difference in a waveform comparison Find Previous Difference find th
247. aving a time precision of 10ps from the timescale directive then the path delay receives a value of 20ps The SDF value of 16ps is rounded to 20ps Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD SDF for Mixed VHDL and Verilog Designs Annotation of a mixed VHDL and Verilog design is very flexible VHDL VITAL cells and Verilog cells can be annotated from the same SDF file This flexibility is available only by using the simulator s SDF command line options The Verilog sdf annotate system task can annotate Verilog cells only See the vsim command for more information on SDF command line options Interconnect Delays An interconnect delay represents the delay from the output of one device to the input of another ModelSim can model single interconnect delays or multisource interconnect delays for Verilog VHDL VITAL or mixed designs See the vsim command for more information on the relevant command line arguments Timing checks are performed on the interconnect delayed versions of input ports This may result in misleading timing constraint violations because the ports may satisfy the constraint while the delayed versions may not If the simulator seems to report incorrect violations be sure to account for the effect of interconnect delays ModelSim User s Manual v6 3g 325 May 2008 Standard Delay Format SDF Timing Annotation Disabling Timing Checks Disabling Timing Checks
248. ay 2008 Graphical User Interface Organizing Windows with Tab Groups Multiple Document Interface MDI Frame The MDI frame is an area in the Main window where the Source Memory Wave and List windows display The frame allows multiple windows to be displayed simultaneously as shown below A tab appears for each window Figure 2 5 Tabs in the MDI Frame Object name Copyright amp Mentor Graphics Corporation 2004 ll Rights Reserved 1 Zz 3 4 5 THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPE 6 MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS 3 8 define clk pd 100 10 timescale lns lns 11 fpodule ram tb 0 12 reg we 13 reg clk 14 reg 19 0 addr 15 reg 3 0 inaddr 16 reg 3 0 outaddr 1 reg 31 0 data_in 18 19 wire 7 0 data spl z EE ESSEEN Na NES NNN 2l ajeno rcm ene m sb Window tabs The object name is displayed in the title bar at the top of the window You can switch between the windows by clicking on a tab Organizing Windows with Tab Groups The MDI can quickly become unwieldy if many windows are open You can create tab groups to help organize the windows A tab group is a collection of tabs that are separated from other groups of tabs Figure 2 6 shows how the collection of files in Figure 2 5 could be organized into two tab groups 42 ModelSim User s Manual v6 3g May 2008
249. bility to enable disable and mirroring is enabled default 0 turns on the ability to enable disable and initially disables mirroring turns on the ability to enable disable and initially enables mirroring Related procedures init signal driver signal force signal release enable signal spy disable signal spy Limitations e When mirroring the value of a Verilog register net onto a VHDL signal the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Verilog memories arrays of registers are not supported init_signal_spy Example In this example the value of top uut inst1 sig1 is mirrored onto top top_sig A message is issued to the transcript The ability to control the mirroring of values is turned on and the init signal spy is initially enabled 304 ModelSim User s Manual v6 3g May 2008 Signal Spy init_signal_spy The mirroring of values will be disabled when enable sig transitions to a 0 and enable when enable sig transitions to a 1 library ieee library modelsim lib use ieee std logic 1164 a11 use modelsim lib util all entity top is end architecture only of top is signal top sigl std logic begin Spy process process begin init signal spy top uut insti sigl top top sig1 1 1 wait end process spy process Spy enable disable process enable sig begin if enable sig 1 then enable signal spy top uut insti sig1
250. bl amp amp i lt 7 za begin 29 increment i val i carry 30 carry val i amp carry 31 end 32 end 23 endfunction 34 35 gt always B posedge clk or posedge reset 36 if reset 37 count tpd_reset to count 8 h00 38 else 39 count lt ftpd clk to count increment count an a h counter v ModelSim User s Manual v6 3g 69 May 2008 Graphical User Interface Source Window The breakpoint markers are toggles Click once to create the breakpoint click again to disable or enable the breakpoint To delete the breakpoint completely right click the red breakpoint marker and select Remove Breakpoint Other options on the context menu include e Disable Enable Breakpoint Deactivate or activate the selected breakpoint e Edit Breakpoint Open the File Breakpoint dialog to change breakpoint arguments e Edit All Breakpoints Open the Modify Breakpoints dialog Adding File Line Breakpoints with the bb Command Use the bp command to add a file line breakpoint from the VSIM gt prompt For example bp top vhd 147 sets a breakpoint in the source file top vhd at line 147 Modifying File Line Breakpoints To modify or add a breakpoint according to the line number in a source file choose Tools Breakpoints from the Main menu which displays the Modify Breakpoints dialog box shown in Figure 2 28 70 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Source Win
251. ble names To access environment variables use the construct env var name echo My user name is env USER Environment variables can also be set using the env array set env SHELL bin csh See Simulator State Variables for more information about ModelSim defined variables System Commands To pass commands to the UNIX shell or DOS window use the Tcl exec command echo The date is exec date ModelSim User s Manual v6 3g 351 May 2008 Tcl and Macros DO Files List Processing List Processing In Tcl a list is a set of strings in curly braces separated by spaces Several Tcl commands are available for creating lists indexing into lists appending to lists getting the length of lists and shifting lists as shown in Table 14 3 Table 14 3 Tcl List Commands Command syntax Description lappend var name vall val2 appends vall val2 etc to list var name lindex list name index returns the index th element of list name the first element is 0 linsert list name index vall val2 inserts vall val2 etc just before the index th element of list name list vall val2 returns a Tcl list consisting of vall val2 etc llength list name returns the number of elements in list name Irange list name first last returns a sublist of list name from index first to index last first or last may be end which refers to the last element in the list Ireplace list name first last vall r
252. by John K Ousterhout published by Addison Wesley Publishing Company Inc and Practical Programming in Tcl and Tk by Brent Welch published by Prentice Hall You can also consult the following online references e Select Help gt Tcl Man Pages Tcl Commands For complete information on Tcl commands select Help Tcl Man Pages Also see Simulator GUI Preferences for information on Tcl preference variables ModelSim User s Manual v6 3g 345 May 2008 Tcl and Macros DO Files Tcl Command Syntax ModelSim command names that conflict with Tcl commands have been renamed or have been replaced by Tcl commands as shown in Table 14 1 Table 14 1 Changes to ModelSim Commands Previous ModelSim Command changed to or replaced by command continue run with the continue option format list wave write format with either list or wave specified if replaced by the Tcl if command see If Command Syntax for more information list add list nolist nowave delete with either list or wave specified set replaced by the Tcl set command source vsource wave add wave Tcl Command Syntax The following eleven rules define the syntax and semantics of the Tcl language Additional details on If Command Syntax 346 1 A Tcl script is a string containing one or more commands Semi colons and newlines are command separators unless quoted as described below Close brackets are command terminators during co
253. cally to the ModelSim force deposit command disable_warnings lt keyword gt lt module_instance gt This system task instructs ModelSim to disable warnings about timing check violations or triregs that acquire a value of X due to charge decay keyword may be decay or timing You can specify one or more module instance names If you do not specify a module instance ModelSim disables warnings for the entire simulation enable warnings keyword module instance This system task enables warnings about timing check violations or triregs that acquire a value of X due to charge decay keyword may be decay or timing You can specify one or more module instance names If you do not specify a module instance ModelSim enables warnings for the entire simulation system command This system function takes a literal string argument executes the specified operating system command and displays the status of the underlying OS process Double quotes are required for the OS command For example to list the contents of the working directory on Unix system ls 1 Return value of the system function is a 32 bit integer that is set to the exit status code of the underlying OS process Note LL There is a known issue in the return value of this system function on the win32 platform If the OS command is built with a cygwin compiler the exit status code may not be reported correctly when
254. can also use the transcript file command to perform a deletion transcript file transcript file my file log The first line will close the current log file The second will open a new log file If it has the same name as an existing file it will replace the previous one 358 ModelSim User s Manual v6 3g May 2008 Tcl and Macros DO Files Macros DO Files Making Macro Parameters Optional If you want to make macro parameters optional i e be able to specify fewer parameter values with the do command than the number of parameters referenced in the macro you must use the argc simulator state variable The arge simulator state variable returns the number of parameters passed The examples below show several ways of using argc Example 14 9 Specifying Files to Compile With argc Macro This macro specifies the files to compile and handles 0 2 compiler arguments as parameters If you supply more arguments ModelSim generates a message switch Sarge 0 vcom filel vhd file2 vhd file3 vhd 1 vcom 1 filel vhd file2 vhd file3 vhd 2 vcom 1 2 filel vhd file2 vhd file3 vhd default echo Too many arguments The macro accepts 0 2 args Example 14 10 Specifying Compiler Arguments With Macro This macro specifies the compiler arguments and lets you compile any number of files variable Files set nbrArgs Sarge for set x 1 x lt SnbrArgs incr x set Files concat Files 1 shift eval vcom 93 expl
255. ccForLoop for loop statement accForeign accShadow foreign scope created by mti CreateRegion accGenerate accGenerate generate statement accPackage accPackage package declaration accSignal accSignal signal declaration The type and fulltype constants for VHDL objects are defined in the acc_vhdl h include file All of these objects except signals are scope objects that define levels of hierarchy in the structure window Currently the PLI ACC interface has no provision for obtaining handles to generics types constants variables attributes subprograms and processes 440 ModelSim User s Manual v6 3g May 2008 IEEE Std 1364 ACC Routines ModelSim Verilog supports the following ACC routines Routines acc_append_delays acc_append_pulsere acc_close acc_collect acc_compare_handles acc_configure acc_count acc fetch argc acc fetch argv acc fetch attribute acc fetch attribute int acc fetch attribute str acc fetch defname acc fetch delay mode acc fetch delays acc fetch direction acc fetch edge acc fetch fullname acc fetch fulltype acc fetch index acc fetch location acc fetch name acc fetch paramtype acc fetch paramval acc fetch polarity acc fetch precision acc fetch pulsere acc fetch range acc fetch size acc fetch tfarg acc fetch itfarg acc fetch tfarg int acc fetch itfarg int acc fetch tfarg str acc fetch itfarg str acc fetch timescale info acc
256. ce Source Window Figure 2 22 Setting Context from Source Files d mponent vlogchk lt 4 port id is end ano nant 4 Open Instance Ascend Env td n 28 bogin Back 29 a Cut ns OO aftet Zopy Paste 1 i Find Examine Describe Drivers DELAY Headers jenerate Breakpoints 4 i GoTo 41 end Show Language Templates 4 Show Source Annotation v Read Only a This functionality allows you to easily navigate your design for debugging purposes by remembering where you have been similar to the functionality in most web browsers The navigation options in the pop up menu function as follows e Open Instance changes your context to the instance you have selected within the source file This is not available if you have not placed your cursor in or highlighted the name of an instance within your source file If any ambiguities exists most likely due to generate statements this option opens a dialog box allowing you to choose from all available instances e Ascend Env changes your context to the next level up within the design This is not available if you are at the top level of your design e Forward Back allows you to change to previously selected contexts This is not available if you have not changed your context The Open Instance option is essentially executing an environment command to change your context therefore any time you use this command
257. ce information in the Locals window it is updated as you go through your simulation However there are several ways you can trigger the Locals window to be updated e Run your simulation while debugging 56 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Locals Window Select a Process from the Process Window Select a Verilog function or task or VHDL function or procedure from the Done Indicates that the process has executed a VHDL wait statement without a time out or a sensitivity list The process will not restart during the current simulation run Call Stack Pane GUI Elements of the Locals Window This section describes the GUI elements specific to the Locals Window Column Descriptions Name lists the names of the immediately visible data objects This column also includes design object icons for the objects refer to the section Design Object Icons and Their Meaning for more information Value lists the current value s associated with each name State Count Not shown by default This column State Hits and State are all specific to coverage analysis State Hits Not shown by default State Not shown by default Menu Items View Declaration Displays in the Source window the declaration of the object You can access this feature from the Locals menu of the Main window or the right click menu in the Locals window Add Adds the selected object s to the
258. ces Dialog Wave Window Preferences x Display Grid amp Timeline Grid Configuration Grid Offset M Minimum Grid Spacing o ns 40 Grid Period 34 20 ht Reset to Default r Timeline Configuration Display simulation time in timeline area Display grid period count cycle count DK Cancel Enter the period of your clock in the Grid Period field and select Display grid period count cycle count The timeline will now show the number of clock cycles as shown in Figure 9 22 Figure 9 22 Clock Cycles in Timeline of Wave Window test_counter clk test_counter reset Formatting Objects in the Wave Window You can adjust various object properties to create the view you find most useful Select one or more objects and then select View gt Properties or use the selections in the Format menu 252 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Formatting the Wave Window Changing Radix base for the Wave Window One common adjustment is changing the radix base of an object When you select View gt Properties the Wave Signal Properties dialog appears Figure 9 23 Changing Signal Radix Wave Properties Signal sim test counter count View Format Compare Display Name Wave Color Radix Colors default a Name Color Colors The default radix is symbolic which means that for an
259. ch applications may include complex 3rd party integrations or multi threaded C testbenches Normally calls to export functions from PLI or FLI code are illegal These calls are referred to as out of the blue calls since they do not originate in the controlled environment of a DPI import tf You can set the ModelSim tool to allow out of the blue Verilog function calls either for all simulations DpiOutOfTheBlue z 1 in modelsim ini file or for a specific simulation vsim dpioutoftheblue 1 One restriction applies only Verilog functions may be called out of the blue It is illegal to call Verilog tasks in this way The simulator issues an error if it detects such a call Calling C C Functions Defined in PLI Shared Objects from DPI Code In some instances you may need to share C C code across different shared objects that contain PLI and or DPI code There are two ways you can achieve this goal e The easiest is to include the shared code in an object containing PLI code and then make use of the vsim gblso option e Another way is to define a standalone shared object that only contains shared function definitions and load that using vsim gblso In this case the process does not require PLI or DPI loading mechanisms such as pli or sv lib You should also take into consideration what happens when code in one global shared object needs to call code in another global shared object In this case place the gblso argument for
260. compiled libraries without providing source code and without revealing internal model variables and structure Note _ LLLLLLL hn nodebug encrypts entire files The Verilog protect compiler directive allows you to encrypt regions within a file Refer to Compiler Directives for details When you compile with nodebug all source text identifiers and line number information are stripped from the resulting compiled object so ModelSim cannot locate or display any information of the model except for the external pins Specifically this means that e aSource window will not display the design units source code e a structure pane will not display the internal structure e the Objects pane will not display internal signals the Active Processes pane will not display internal processes e the Locals pane will not display internal variables e none of the hidden objects may be accessed through the Dataflow window or with ModelSim commands You can access the design units comprising your model via the library and you may invoke vsim directly on any of these design units and see the ports To restrict even this access in the lower levels of your design you can use the following nodebug options when you compile Table 3 1 Compile Options for the nodebug Compiling vcom nodebug ports makes the ports of a VHDL design unit invisible vlog nodebug ports makes the ports of a Verilog design unit invisible
261. ction with wlftlim the more restrictive of the limits takes precedence The WLF file can be limited by time with the WLFTimeLimit simulation control variable in the modelsim ini file or with the wlftlim switch for the vsim command Either method specifies the duration of simulation time for WLF file recording The duration specified should be an integer of simulation time at the current resolution however you can specify a different resolution if you place curly braces around the specification For example vsim wlftlim 5000 ns sets the duration at 5000 nanoseconds regardless of the current simulator resolution 222 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Opening Datasets The time range begins at the current simulation time and moves back in simulation time for the specified duration In the example above the last 5000ns of the current simulation is written to the WLF file If used in conjunction with wlfslim the more restrictive of the limits will take effect The wlfslim and wlftlim switches were designed to help users limit WLF file sizes for long or heavily logged simulations When small values are used for these switches the values may be overridden by the internal granularity limits of the WLF file format The WLF file saves data in arecord like format The start of the record checkpoint contains the values and is followed by transition data This continues until the next chec
262. cts Figure 4 4 Create Project File Dialog Create Project File E x File Name foo Browse r Add file as type Folder Verilog Top Level vij DK Cancel Specify a name file type and folder location for the new file When you select OK the file is listed in the Project tab Double click the name of the new file and a Source editor window will open allowing you to create source code Add Existing File You can add an existing file to the project by selecting Project gt Add to Project gt Existing File or by right clicking in the Project tab and selecting Add to Project gt Existing File Figure 4 5 Add file to Project Dialog Add file to Project x File Name counter v tcounter Browse Add file as type Folder ni E Top Level M Reference from current location Copy to project directory OK Cancel When you select OK the file s is added to the Project tab Step 3 Compiling the Files The question marks in the Status column in the Project tab denote either the files haven t been compiled into the project or the source has changed since the last compile To compile the files select Compile gt Compile All or right click in the Project tab and select Compile gt Compile All Figure 4 6 ModelSim User s Manual v6 3g 115 May 2008 Projects Getting Started with Projects Figure 4 6 Right click Compile M
263. d during the elaboration phase of simulation Configurations actually consist of two pieces the library mapping and the configuration itself The library mapping is used at compile time to determine into which libraries the source files are to be compiled Here is an example of a simple library map file library work i top Y library rtlLib lrm ex top v library gateLib lrm ex adder vg library aLib lrm ex adder v Here is an example of a library map file that uses incdir library libl src dir v incdir include dir2 my incdir The name of the library map file is arbitrary You specify the library map file using the libmap argument to the vlog command Alternatively you can specify the file name as the first item on the vlog command line and the compiler reads it as a library map file The library map file must be compiled along with the Verilog source files Multiple map files are allowed but each must be preceded by the libmap argument The library map file and the configuration can exist in the same or different files If they are separate only the map file needs the libmap argument The configuration is treated as any other Verilog source file Configurations and the Library Named work The library named work is treated specially by ModelSim see The Library Named work for details for Verilog configurations Consider the following code example 180 ModelSim User s Manual v6 3g May 2008 Veri
264. d signal Find Next Transition locate the next signal value change for the selected signal ModelSim User s Manual v6 3g May 2008 Edit gt Search Search Reverse Edit gt Search Search Forward keyboard Shift Tab keyboard Tab 93 Graphical User Interface Wave Window Table 2 11 Wave Window Toolbar Buttons and Menu Selections Select Mode set mouse to Select Mode click left mouse button to select drag middle mouse button to zoom Menu equivalent View gt Zoom gt Mouse Mode gt Select Mode Other options al Zoom Mode set mouse to Zoom Mode drag left mouse button to zoom click middle mouse button to select View gt Zoom gt Mouse Mode gt Zoom Mode E Zoom In 2x zoom in by a factor of two from the current view Zoom Out 2x zoom out by a factor of two from current view View Zoom Zoom In View Zoom Zoom Out keyboard 1 I or right mouse in wave pane gt Zoom In keyboard o O or right mouse in wave pane gt Zoom Out Zoom in on Active Cursor center active cursor in the display and zoom in View gt Zoom gt Zoom Cursor keyboard c or C Zoom Full zoom out to view the full range of the simulation from time 0 to the current time View gt Zoom gt Zoom Full keyboard f or F right mouse in wave pane gt Zoom Full E Stop Wave Drawing halts any waves currently being drawn in the W
265. d its attached signals or one signal and its attached processes as displayed in Figure 2 10 Figure 2 10 Dataflow Window ModelSim lt gt dataflow File Edit View Navigate Trace Tools Window amp X m 4 sBBQ2M be oheRHK ADGA amp amp i m INITIAL 58 addr_r data_r wee 4 LI The Dataflow window displays processes e signals nets and registers The window has built in mappings for all Verilog primitive gates 1 e AND OR PMOS NMOS etc For components other than Verilog primitives you can define a mapping between processes and built in symbols See Symbol Mapping for details 50 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Dataflow Window Dataflow Window Toolbar The buttons on the Dataflow window toolbar are described below Table 2 7 Dataflow Window Toolbar Button Menu equivalent Print print the current view of the Dataflow File gt Print Windows window File gt Print Postscript UNIX Select mode set left mouse button to select View gt Select mode and middle mouse button to zoom mode Zoom mode set left mouse button to zoom View Zoom Oy mode and middle mouse button to pan mode Pan mode set left mouse button to pan mode View Pan and middle mouse button to zoom mode Cut cut the selected object s Edit Cut d Copy copy the selected object s Edit Copy Paste paste the previ
266. d that the above copyright notice appears in all copies and that both the copyright notice and this permission notice appear in supporting documentation In addition Intel grants this permission provided that you prominently mark as not part of the original any modifications made to this software or documentation and that the name of Intel Corporation not be used in advertising or publicity pertaining to distribution of the software or the documentation without specific written prior permission Intel Corporation provides this AS IS WITHOUT ANY WARRANTY EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE Intel makes no guarantee or representations regarding the use of or the results of the use of the software and documentation in terms of correctness accuracy reliability currentness or otherwise and you rely on the software documentation and results solely at your own risk IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE LOSS OF BUSINESS LOSS OF PROFITS INDIRECT INCIDENTAL SPECIAL OR CONSEQUENTIAL DAMAGES OF ANY KIND IN NO EVENT SHALL INTEL S TOTAL LIABILITY EXCEED THE SUM PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER Copyright 1992 1993 1994 Henry Spencer All rights reserved This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the University of California Permission is granted to anyone
267. delSim User s Manual v6 3g May 2008 Setting GUI Preferences Simulator GUI Preferences The modelsim tcl File Previous versions saved user GUI preferences into a modelsim tcl file Current versions will still read in a modelsim tcl file if 1t exists ModelSim searches for the file as follows e use MODELSIM TCL environment variable if it exists f MODELSIM_TCL is a list of files each file is loaded in the order that it appears in the list else e use nodelsim tcl else e use HOME modelsim tcl if it exists Note that in versions 6 1 and later ModelSim will save to the modelsim file any variables it reads in from a modelsim tcl file The values from the modelsim tcl file will override like variables in the modelsim file ModelSim User s Manual v6 3g 465 May 2008 Setting GUI Preferences Simulator GUI Preferences 466 ModelSim User s Manual v6 3g May 2008 Appendix F System Initialization ModelSim goes through numerous steps as it initializes the system during startup It accesses various files and environment variables to determine library mappings configure the GUI check licensing and so forth Files Accessed During Startup The table below describes the files that are read during startup They are listed in the order in which they are accessed Table F 1 Files Accessed During Startup modelsim ini contains initial tool settings see Simulator Control Variables for specific details on the modelsim ini file
268. designers using VHDL AMS to test digital parts of their model e Value Range 0 1 374 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables e Default off 0 BindAtCompile This variable instructs the tool to perform VHDL default binding at compile time rather than load time Refer to Default Binding for more information e Value Range 0 1 e Default off 0 CheckSynthesis This variable turns on limited synthesis rule compliance checking which includes checking only signals used read by a process and understanding only combinational logic not clocked logic e Value Range 0 1 e Default off 0 CoverRespectHandL This variable specifies whether you want the VHDL H and L input values on conditions and expressions to be automatically converted to 1 and 0 respectively The default is 1 whereby the H and L values are NOT automatically converted e Value Range 0 1 e Default off 1 As an alternative to setting this variable to 0 if you are not using H and L values and don t want the additional UDP rows that are difficult to cover you can either e change your VHDL expressions of the form a 1 to to x01 a 1 or to std_match a 1 These functions are recognized and used to simplify the UDP tables e use the nocoverrespecthandl argument to vcom DisableOpt This variable disables all optimizations enacted by the compiler similar to
269. directory in which the binary executable resides DO NOT SET THIS VARIABLE MODEL TECH TCL The toolset uses the MODEL TECH TCL environment variable to find Tcl libraries for Tcl Tk 8 3 and vsim and may also be used to specify a startup DO file This variable defaults to modeltech tcl however you may set it to an alternate path MGC LOCATION MAP The toolset uses the MGC LOCATION MAP environment variable to find source files based on easily reallocated soft paths ModelSim User s Manual v6 3g 365 May 2008 Simulator Variables Environment Variables MODELSIM The toolset uses the MODELSIM environment variable to find the modelsim ini file The argument consists of a path including the file name An alternative use of this variable is to set it to the path of a project file lt Project_Root_Dir gt lt Project_Name gt mpf This allows you to use project settings with command line tools However if you do this the mpf file will replace modelsim ini as the initialization file for all tools MODELSIM_PREFERENCES The MODELSIM_PREFERENCES environment variable specifies the location to store user interface preferences Setting this variable with the path of a file instructs the toolset to use this file instead of the default location your HOME directory in UNIX or in the registry in Windows The file does not need to exist beforehand the toolset will initialize it Also if this file is read only the toolset will not update
270. do with the saved variable e Read the value of foo with the set command set foo e Put foo in the Expression entry box for the Search for Expression selection e Issue a searchlog command using foo searchlog expr foo 0 Searching for when a Signal Reaches a Particular Value Select the signal in the Wave window and click Insert Selected Signal and Then click the value buttons or type a value Evaluating Only on Clock Edges Click the amp amp button to AND this condition with the rest of the expression Then select the clock in the Wave window and click Insert Selected Signal and rising You can also select the falling edge or both edges Operators Other buttons will add operators of various kinds see Expression Syntax or you can type them in Formatting the Wave Window Setting Wave Window Display Preferences You can set Wave window display preferences by selecting Tools gt Options gt Wave Preferences when the window is docked in the MDI frame or Tools gt Window Preferences when the window is undocked These commands open the Wave Window Preferences dialog Figure 9 20 250 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Formatting the Wave Window Figure 9 20 Display Tab of the Wave Window Preferences Dialog Wave Window Preferences x Display Grid amp Timeline Display Signal Path Snap Distance D elements 10 ipte Use 0 for full pat
271. dow Figure 2 28 Modifying Existing Breakpoints xi Breakpoints fly asicSimulation counter v Line 36 diy sim Jtest counter reset Add Modify Enable Delete Label File Breakpoint x File C Tutorialfexamples tutorials verilog Browse sim test_counterjreset Line Instance Name Condition 36 sim test_counter reset Breakpoint Condition Command echo Break on sim test_counter reset stop eRe command OK Cancel OK Cancel The Modify Breakpoints dialog box provides a list of all breakpoints in the design To modify a breakpoint do the following 1 Select a file line breakpoint from the list 2 Click Modify which opens the File Breakpoint dialog box shown in Figure 2 28 3 Fill out any of the following fields to modify the selected breakpoint e Instance Name The full pathname to an instance that sets a SystemC breakpoint so it applies only to that specified instance e Breakpoint Condition One or more conditions that determine whether the breakpoint is observed You must enclose the condition expression within quotation marks If the condition is true the simulation stops at the breakpoint If false the simulation bypasses the breakpoint A condition cannot refer to a VHDL variable only a signal ModelSim User s Manual v6 3g 71 May 2008 Graphical User Interface Sourc
272. drestart arguments to vsim for related information reason endofreset For the completion of the restart command after the simulation state has been reset but before the design has been reloaded reason interactive For the execution of the stop system task or any other time the simulation is interrupted and waiting for user input reason scope ModelSim User s Manual v6 3g 437 May 2008 Verilog PLI VPI DPI The sizetf Callback Function For the execution of the environment command or selecting a scope in the structure window Also for the call to acc_set_interactive_scope if the callback_flag argument is non zero reason paramvc For the change of value on the system task or function argument reason synch For the end of time step event scheduled by tf synchronize reason rosynch For the end of time step event scheduled by tf rosynchronize reason reactivate For the simulation event scheduled by tf setdelay reason paramdrc Not supported in ModelSim Verilog reason force Not supported in ModelSim Verilog reason release Not supported in ModelSim Verilog reason disable Not supported in ModelSim Verilog The sizetf Callback Function A user defined system function specifies the width of its return value with the sizetf callback function and the simulator calls this function while loading the design The following details on the sizetf callback function are not found in the IEEE Std 1364
273. ducts into your products or applications without first signing or otherwise agreeing to a separate agreement with Mentor Graphics for such purpose BETA CODE Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on your feedbac
274. dule hello top int ret export DPI C task verilog task task verilog task input int i 10 required by tasks output int 0 Sdisplay Hello from verilog task endtask import DPI C context task c task input int i output int o initial begin c task 1 ret Call the c task named c_task end endmodule Compile the Verilog code vlib work oe oe Com O vlog sv dpiheader dpiheader h hello v ile the DPI code for the Solaris operating system gcc c I install dir include hello c c gcc shared Bsymbolic o hello c so hello c o Simulate the design o F Loading work hello c Loading hello c so VSIM 1 run all Hello from c task Hello from verilog task VSIM 2 quit 436 vsim c sv lib hello c hello top do run all quit f ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI The PLI Callback reason Argument The PLI Callback reason Argument The second argument to a PLI callback function is the reason argument The values of the various reason constants are defined in the veriuser h include file See IEEE Std 1364 for a description of the reason constants The following details relate to ModelSim Verilog and may not be obvious in the IEEE Std 1364 Specifically the simulator passes the reason values to the misctf callback functions under the following circumstances rea
275. e else elsif endcelldefine endif ifdef ifndef include line nounconnected drive resetall timescale unconnected drive undef Verilog XL Compatible Compiler Directives The following compiler directives are provided for compatibility with Verilog XL default_decay_time lt time gt This directive specifies the default decay time to be used in trireg net declarations that do not explicitly declare a decay time The decay time can be expressed as a real or integer number or as infinite to specify that the charge never decays delay mode distributed This directive disables path delays in favor of distributed delays See Delay Modes for details delay mode path This directive sets distributed delays to zero in favor of path delays See Delay Modes for details delay mode unit This directive sets path delays to zero and non zero distributed delays to one time unit See Delay Modes for details delay mode zero This directive sets path delays and distributed delays to zero See Delay Modes for details uselib This directive is an alternative to the v y and libext source library compiler arguments See Verilog XL uselib Compiler Directive for details The following Verilog XL compiler directives are silently ignored by ModelSim Verilog Many of these directives are irrelevant to ModelSim Verilog but may appear in code being ported from Verilog XL 216 ModelSim User s Manual
276. e For example vsim nowarnTFMPC suppresses warning messages about too few port connections ModelSim User s Manual v6 3g 409 May 2008 Error and Warning Messages Exit Codes Exit Codes The table below describes exit codes used by ModelSim tools 410 Exit code Table B 2 Exit Codes Description Normal non error return Incorrect invocation of tool Previous errors prevent continuing Cannot create a system process execv fork spawn etc Licensing problem Cannot create open find read write a design library Cannot create open find read write a design unit Ho tn Ut Nj Cannot open read write dup a file open lseek write mmap munmap fopen fdopen fread dup2 etc File is corrupted or incorrect type version or format of file Memory allocation error General language semantics error General language syntax error Problem during load or elaboration Problem during restore Problem during refresh Communication problem Cannot create read write close pipe socket Version incompatibility License manager not found unreadable unexecutable vlm mgvlm Lost license License read write failure Modeltech daemon license checkout failure 44 Modeltech daemon license checkout failure 45 Assertion failure SEVERITY_QUIT Unexpected error in tool GUI Tcl initialization failure ModelSim User s Manual v6 3g
277. e compatible with NCSim s argument list The file format argument accepts the following values or an ORed combination thereof see examples below Table 13 8 Values for file format Argument File format value Meaning Ignore strength range Use strength ranges produces IEEE 1364 compliant behavior Compress the EVCD output Include port direction information in the EVCD file header same as using direction argument to vcd dumpports Here are some examples ignore strength range S dumpports top filename 0 0 342 ModelSim User s Manual v6 3g May 2008 Value Change Dump VCD Files Capturing Port Driver Data compress and ignore strength range Sdumpports top filename 0 4 print direction and ignore strength range Sdumpports top filename 0 8 compress print direction and ignore strength range Sdumpports top filename 0 12 Example 13 5 VCD Output from vcd dumpports This example demonstrates how ved dumpports resolves values based on certain combinations of driver values and strengths and whether or not you use strength ranges Table 13 9 is sample driver data Table 13 9 Sample Driver Data time in value out value in strength value range out strength value range 0 0 7 strong 7 strong 100 0 6 strong 7 strong 5 strong 7 strong 4 weak 7 strong 6 strong 7 strong 5 strong 4 weak 4 weak 4
278. e GUI e Refresh Rebuilds the library image of the selected library without using source code Related command line command is vcom or vlog with the refresh argument e Recompile Recompiles the selected design unit Related command line command is vcom or vlog e Update Updates the display of available libraries and design units Assigning a Logical Name to a Design Library VHDL uses logical library names that can be mapped to ModelSim library directories By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI a command or a project to assign a logical name to a design library 132 ModelSim User s Manual v6 3g May 2008 Design Libraries Working with Design Libraries Library Mappings with the GUI To associate a logical name with a library select the library in the workspace right click you mouse and select Edit from the context menu that appears This brings up a dialog box that allows you to edit the mapping Figure 5 3 Edit Library Mapping Dialog ES Library Mapping Name simprim m Library Pathname CM odeltech 5 7b simprim Browse OK Cancel The dialog box includes these options e Library Mapping Name The logical name of the library e Library Pathname The pathn
279. e Main window workspace The tab is labeled with the name of the dataset and displays a hierarchy of the design units in that dataset The graphic below shows three structure tabs one for the active simulation sim and one each for two datasets test and gold Figure 8 3 Structure Tabs in Workspace Pane Workspace w nsance Design unit_ Design unit type Visbilty test ringbuf test_ringbuf ScModule acc lt full gt JM clock sc clock ScModule ace lt full gt B nna INST ringbuf ScModule acc lt full gt block control rtl Architecture acc inone A block2 store Module acc lt full gt A block3 retrieve Module acc lt full gt lf standard standard Package acc v Wi std logic 1154 std logic 1 Package acc v Bf std logic arith std logic arith Package acczv lf std logic unsigned std logic un Package acczv reset generator test_ringbuf ScMethod generate data test_ringbuf ScMethod compare data test ringbuf ScMethod print error test_tingbuf ScMethod print restore test_tingbuf ScMethod Aoo R EET um Tum als If you have too many tabs to display in the available space you can scroll the tabs left or right by clicking the arrow icons at the bottom right hand corner of the window 224 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Managing Multiple Datasets Structure Tab Columns Each structure tab displays three columns by default T
280. e Window e Breakpoint Command A string enclosed in braces that specifies one or more commands to be executed at the breakpoint Use a semicolon to separate multiple commands ay These fields in the File Breakpoint dialog box use the same syntax and format as the inst switch the condition switch and the command string of the bp command For more information on these command options refer to the bp command in the Reference Manual 4 Click OK to close the File Breakpoints dialog box 5 Click OK to close the Modify Breakpoints dialog box Checking Object Values and Descriptions There are two quick methods to determine the value and description of an object displayed in the Source window e select an object then right click and select Examine or Describe from the context menu e pause over an object with your mouse pointer to see an examine pop up Select Tools gt Options gt Examine Now or Tools gt Options gt Examine Current Cursor to choose at what simulation time the object is examined or described You can also invoke the examine and or describe commands on the command line or in a macro Marking Lines with Bookmarks Source window bookmarks are blue circles that mark lines in a source file These graphical icons may ease navigation through a large source file by highlighting certain lines As noted above in the discussion about finding text in the Source window you can insert bookmarks on any line con
281. e a VCD file for a single design unit using the vcd dumpports command 2 Resimulate the single design unit using the vcdstim argument to vsim Note that vcdstim works only with VCD files that were created by a ModelSim simulation Example 13 1 Verilog Counter First create the VCD file for the single instance using ved dumpports cd modeltech examples misc 96 vlib work 96 vlog counter v tcounter v 96 vsim test counter VSIM 1 gt vcd dumpports file counter vcd test counter dut VSIM 2 run VSIM 3 gt quit f Next rerun the counter without the testbench using the vcdstim argument 96 vsim vcdstim counter vcd counter VSIM 1 gt add wave VSIM 2 run 200 Example 13 2 VHDL Adder First create the VCD file using ved dumpports 96 cd modeltech examples misc 96 vlib work 96 vcom gates vhd adder vhd stimulus vhd 96 vsim testbench2 VSIM 1 ved dumpports file addern vcd testbench2 uut VSIM 2 gt run 1000 VSIM 3 gt quit f Next rerun the adder without the testbench using the vcdstim argument vsim vcdstim addern vcd addern gnz8 do add wave run 1000 Example 13 3 Mixed HDL Design First create three VCD files one for each module ModelSim User s Manual v6 3g 331 May 2008 Value Change Dump VCD Files Using Extended VCD as Stimulus 96 cd modeltech examples tutorials mixed projects 96 vlib work 96 vlog cache v memory v proc v 96 vcom util vhd set vhd top vhd 96 vsim to
282. e click the Simulation Configuration verilog_sim to load the design Organizing Projects with Folders The more files you add to a project the harder it can be to locate the item you need You can add folders to the project to organize your files These folders are akin to directories in that you can have multiple levels of folders and sub folders However no actual directories are created via the file system the folders are present only within the project file Adding a Folder To add a folder to your project select Project Add to Project Folder or right click in the Project tab and select Add to Project Folder Figure 4 15 Figure 4 15 Add Folder Dialog xi Folder Name Design Files Folder Location Top Level vi OK Cancel Specify the Folder Name the location for the folder and click OK The folder will be displayed in the Project tab ModelSim User s Manual v6 3g 123 May 2008 Projects Organizing Projects with Folders You use the folders when you add new objects to the project For example when you add a file you can select which folder to place it in Figure 4 16 Specifying a Project Folder Add file to Project ES File Name counter v tcounter vv Browse Add file as type Folder defaut vj veniog files vi Reference from current location C Copy to project directory OK Cancel If you want to move a file into a folder later on you can do so using the P
283. e invoked in the project s root directory If you want to invoke outside the project directory set the MODELSIM environment variable with the path to the project file lt Project_Root_Dir gt lt Project_Name gt mpf You can also use the project command from the command line to perform common operations on projects 128 ModelSim User s Manual v6 3g May 2008 Chapter 5 Design Libraries VHDL designs are associated with libraries which are objects that contain compiled design units Verilog and SystemVerilog designs simulated within ModelSim are compiled into libraries as well Design Library Overview A design library is a directory or archive that serves as a repository for compiled design units The design units contained in a design library consist of VHDL entities packages architectures and configurations Verilog modules and UDPs user defined primitives The design units are classified as follows e Primary design units Consist of entities package declarations configuration declarations modulesUDPs Primary design units within a given library must have unique names e Secondary design units Consist of architecture bodiespackage bodies Secondary design units are associated with a primary design unit Architectures by the same name can exist if they are associated with different entities or modules Design Unit Information The information stored for each design unit in a design library is e retargetable exec
284. e previous difference in a waveform comparison Find Next Difference EJ find the next difference in a waveform comparison Find Next Annotated Difference find the next annotated difference in a waveform comparison Find Last Difference find the last difference in a waveform comparison ModelSim User s Manual v6 3g 95 May 2008 Graphical User Interface Wave Window 96 ModelSim User s Manual v6 3g May 2008 Chapter 3 Protecting Your Source Code As today s IC designs increase in complexity silicon manufacturers are leveraging third party intellectual property IP to maintain or shorten design cycle times This third party IP is often sourced from several IP vendors each of whom may require different levels of protection in EDA tool flows The number of protection encryption schemes developed by IP vendors has complicated the use of protected IP in design flows made up of tools from several EDA providers ModelSim s encryption solution allows IP vendors to deliver encrypted IP code that can be used in a wide range of EDA tools and design flows This enables usage scenarios such as making module ports parameters and specify blocks publicly visible while keeping the implementation private ModelSim supports encryption of Verilog and SystemVerilog IP code in protected envelopes as defined by the IEEE Standard 1364 2005 section 28 titled Protected envelopes and Annex H section H 3 titled Digit
285. e queue The example below illustrates potential ramifications of this situation Say you have these four statements 1 always q p q 2 always q p2 not q 3 always p or p2 clk p and p2 4 always posedge clk and current values as follows q 0 p 0 p2 1 The tables below show two of the many valid evaluations of these statements Evaluation events are denoted by a number where the number is the statement to be evaluated Update events are denoted lt name gt old gt new where lt name gt indicates the reg being updated and new is the updated value Table 7 2 Evaluation 1 of always Statements q 0 gt 1 1 2 p 0 1 2 p 0 gt 1 3 2 3 clk 0 gt 1 2 clk 0 gt 1 4 2 2 p2 1 gt 0 186 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Table 7 2 Evaluation 1 of always Statements cont Event being processed Active event queue p2 1 gt 0 3 3 clk 1 gt 0 clk 1 gt 0 lt empty gt Table 7 3 Evaluation 2 of always Statement q 0 gt 1 1 2 p 0 gt 1 2 p2 1 gt 0 p 0 gt 1 p 0 gt 1 3 p2 1 gt 0 p2 1 0 3 3 empty clk doesn t change Again both evaluations are valid However in Evaluation 1 clk has a glitch on it in Evaluation 2 clk doesn t This indicates that the design has a zero delay race condition on clk Controlling
286. e queued and executed as well The steps taken to evaluate the design without advancing simulation time are referred to as delta times or just deltas The diagram below represents the process for VHDL designs This process continues until the end of simulation time 146 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Simulating VHDL Designs Figure 6 1 VHDL Delta Delay Process Execute concurrent _ Statements at wdvance delta time lt current time Advance simulation No Any transactions to time T process Any events to No process p Execute concurrent statements that are sensitive to events This mechanism in event based simulators may cause unexpected results Consider the following code snippet clk2 lt clk process rst clk begin if rst 0 then s0 lt 0 elsif clk event and clk 1 then s0 lt inp end if end process process rst clk2 begin if rst 0 then Sl lt 107 elsif clk2 event and clk2 2 1 then sl lt s0 end if end process In this example you have two synchronous processes one triggered with clk and the other with clk2 To your surprise the signals change in the c k2 process on the same edge as they are set in the clk process As a result the value of inp appears at s rather than 50 During simulation an event on clk occurs from the testbench From this eve
287. e that is a Verilog module You would want to compile these two files together To group files follow these steps 1 Select the files you want to group ModelSim User s Manual v6 3g 117 May 2008 Projects Getting Started with Projects Figure 4 9 Grouping Files x Current Order B memory v Cs rn util yhd set vhd top vhd rj Auto Generate DK E 2 Click the Group button ER To ungroup files select the group and click the Ungroup button Es Step 4 Simulating a Design To simulate a design do one of the following e double click the Name of an appropriate design object such as a testbench module or entity in the Library tab of the Workspace right click the Name of an appropriate design object and select Simulate from the popup menu e select Simulate gt Start Simulation from the menus to open the Start Simulation dialog Figure 4 10 Select a design unit in the Design tab Set other options in the VHDL Verilog Libraries SDF and Others tabs Then click OK to start the simulation 118 ModelSim User s Manual v6 3g May 2008 Projects Getting Started with Projects Figure 4 10 Start Simulation Dialog xi Design VHDL Verilog Libraries SDF Others b work Library C Tutorial examples tutorials verilog pr counter Module C Tutorial examples tutorials verilog pr test_counter Module C Tutorial examples tutorials verilog pr i sv_std Library MODEL_TECH
288. e the actual delay observed Most Verilog cells use path delays exclusively with the distributed delays set to zero For example module and2 y a b input a b output y and y a b specify a gt y b gt y endspecify endmodule In the above two input and gate cell the distributed delay for the and primitive is zero and the actual delays observed on the module ports are taken from the path delays This is typical for most cells but a complex cell may require non zero distributed delays to work properly Even so these delays are usually small enough that the path delays take priority over the distributed delays The rule is that if a module contains both path delays and distributed delays then the larger of the two delays for each path shall be used as defined by the IEEE Std 1364 This is the default behavior but you can specify alternate delay modes with compiler directives and arguments These arguments and directives are compatible with Verilog XL Compiler delay mode arguments take precedence over delay mode directives in the source code Distributed Delay Mode In distributed delay mode the specify path delays are ignored in favor of the distributed delays Select this delay mode with the delay_mode_distributed compiler argument or the delay mode distributed compiler directive ModelSim User s Manual v6 3g 203 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Path Delay Mode I
289. e the default name used when saving the transcript file The saved transcript file will contain all the text in the current transcript file e Command History Allows you to change the default name used when saving command history information This file is saved at the same time as the transcript file e Save File Allows you to change the default name used when selecting File gt Save As e Saved Lines Allows you to change how many lines of text are saved in the transcript window Setting this value to zero 0 saves all lines e Line Prefix Allows you to change the character s that precedes the lines in the transcript e Update Rate Allows you to change the length of time in ms between transcript refreshes the transcript refreshes ModelSim User s Manual v6 3g 75 May 2008 Graphical User Interface Transcript Window e ModelSim Prompt Allows you to change the string used for the command line prompt e VSIM Prompt Allows you to change the string used for the simulation prompt e Paused Prompt Allows you to change the string used for when the simulation is paused Message Viewer Tab The Message Viewer tab found in the Transcript window allows you to easily access organize and analyze any Note Warning Error or other elaboration and runtime messages written to the transcript during the simulation run Displaying the Message Viewer Tab e Select View gt Message Viewer e Use the command
290. e to the Verilog scope for the R specifier and does not log any attributes for F filename or L line number The following messagelog task messagelog V S C 1 L Unexpected AHB interrupt received in transactor R 1 Error AHB UNEXPINTRPT LINE ahbtop c190 transcripts the message Error AHB UNEXPINTRPT 238 Unexpected AHB interrupt received in transactor ahbtop c190 where the verbosity level 90 V is 1 severity level S is Error the category C is AHB and the message identifier I is UNEXPINTRPT There is a direct reference for the region R and the macro __LINE__ is used for line number L resulting in no attribute logged for F filename ModelSim User s Manual v6 3g 211 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions psprintf Syntax psprintf Description The psprintf system function behaves like the sformat file I O task except that the string result is passed back to the user as the function return value for psprintf not placed in the first argument as for sformat Thus psprintf can be used where a string is valid Note that at this time unlike other system tasks and functions psprintf cannot be overridden by a user defined system function in the PLI sdf_done Syntax sdf_done Description This task is a cleanup function that removes internal buffers called MIPDs
291. e used in ModelSim Layouts and Modes of Operation ModelSim ships with three default layouts that correspond to three modes of operation Table E 1 Predefined GUI Layouts NoDesign a design is not yet loaded Simulate a design is loaded a design is loaded with code coverage enabled As you load and unload designs ModelSim switches between the layouts Custom Layouts You can create custom layouts or modify the three default layouts Creating Custom Layouts To create a custom layout or modify one of the default layouts follow these steps 1 Rearrange the GUI as you see fit see Navigating the Graphic User Interface for details ModelSim User s Manual v6 3g 457 May 2008 Setting GUI Preferences Customizing the Simulator GUI Layout 2 Select Layout gt Save Figure E 1 Save Current Window Layout Dialog Box lolx Save Layout As NoD esign wi v Use this layout when no design is loaded Also save main window geometry OK Cancel 3 Specify a new name or use an existing name to overwrite that layout 4 Click OK The layout is saved to the modelsim file or Registry on Windows Assigning Layouts to Modes You can assign which layout appears in each mode no design loaded design loaded design loaded with coverage Follow these steps 1 Create your custom layouts as described above 2 Select Layout gt Configure Example E 1 Configure Window Layouts Dialog Box Configure Window
292. e window 261 FPGA libraries importing 137 Function call debugging 49 functions virtual 231 G generate statements Veilog 181 GenerateFormat ini file variable 383 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I GenerateLooplterationMax ini file variable 372 GenerateRecursionDepthMax ini variable 372 GenerouslIdentifierParsing ini file variable 384 get_resolution VHDL function 155 global visibility PLI FLI shared objects 434 GLOBALPATHPULSE matching to specify path delays 321 GlobalSharedObjectsList ini file variable 384 graphic interface 233 275 grouping files for compile 117 grouping objects Monitor window 83 groups in wave window 256 GUI_expression_format GUI expression builder 248 H Hazard ini file variable 372 hazards limitations on detection 189 hierarchy driving signals in 299 forcing signals in 156 307 referencing signals in 156 303 releasing signals in 156 311 highlighting in Source window 72 history of commands shortcuts for reuse 449 HOLD matching to Verilog 321 HOME environment variable 364 HOME OIN environment variable 364 zb T O TextIO package 149 icons shapes and meanings 37 identifiers escaped 201 ieee ini file variable 370 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWX YZ IEEE libraries 136 IEEE Std 1076 31 differences between versions 141 IEEE Std 1364 31 169 IEEE Std 1364 2005 97 323 Ignore
293. ecifies the default simulation length in units specified by the UserTimeUnit variable e Value Range positive integer e Default 100 ShowFunctions This variable sets the format for Breakpoint and Fatal error messages When set to 1 the default value messages will display the name of the function task subprogram module or architecture where the condition occurred in addition to the file and line number Set to 0 to revert messages to previous format e Value Range 0 1 e Default 1 390 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables SignalSpyPathSeparator This variable specifies a unique path separator for the Signal Spy functions The argument to SignalSpyPathSeparator must not be the same character as DatasetSeparator e Value Range any character except those with special meaning such as etc e Default Startup This variable specifies a simulation startup macro Refer to the do command e Value Range do lt DO filename gt any valid macro do file e Default commented out StdArithNoWarnings This variable suppresses warnings generated within the accelerated Synopsys std_arith packages e Value Range 0 1 e Default off 0 ToggleCountLimit This variable limits the toggle coverage count for a toggle node After the limit is reached further activity on the node will be ignored for toggle coverage All possible transition edges must re
294. ecify the dataset that will contain the database with wlf lt db_pathname gt If a dataset name is not specified the default name will be vsim wlf The debug database and the dataset that contains it should have the same base name db pathname The add log r command instructs ModelSim to save all signal values generated when the simulation is run Run the simulation Quit the simulation Use the Post Simulation Debug Database l Start ModelSim by typing vsim at a UNIX shell prompt or double click a ModelSim icon in Windows Select File gt Change Directory and change to the directory where the post simulation debug database resides Recall the post simulation debug database with the following dataset open db pathname wlf ModelSim opens the w f dataset and its associated debug database dbg file with the same basename if it can be found If ModelSim cannot find db pathname dbg it will attempt to open vsim dbg Common Tasks for Dataflow Debugging Common tasks for current and post simulation Dataflow debugging include Adding Objects to the Dataflow Window Exploring the Connectivity of the Design Exploring Designs with the Embedded Wave Viewer Tracing Events Causality Tracing the Source of an Unknown State StX Finding Objects by Name in the Dataflow Window ModelSim User s Manual v6 3g 277 May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Adding Objects to
295. ecifying File Properties 0 0 0 0 cece eee Ie 126 Figure 4 19 Project Settings Dialoes o 0442004d254 RR R4 EE ERRARE EE PEEL E ERES 127 Figure 5 1 Creating a New Library 0 0 cee eect eh 131 Figure 5 2 Design Unit Information in the Workspace seleleeeeeeeee 132 Figure 5 3 Edit Library Mapping Dialog sese 133 Figure 5 4 Import Library Wizard 259 c9 REESE RICE RE edee e eepern Seen s 138 Figure 6 1 VHDL Delta Delay Process osse cer hh Re ph RR mh rhe 147 Figure 7 1 Fatal Signal Segmentation Violation SIGSEGV 000 191 Figure 7 2 Current Process Where Error Occurred lllleeeeeeeleeeeeeee 191 Figure 7 3 Blue Arrow Indicates Where Code Stopped Executing 191 Figure 7 4 null Values in the Locals Window eleseeeeeeeeeeeeA 192 Figure 8 1 Displaying Two Datasets in the Wave Window 2 ee ee eee 220 Figure 8 2 Open Dataset Dialog Box 1 0 2 cece eee eee nee 223 Figure 8 3 Structure Tabs in Workspace Pane 0 0 eee eee eee eee 224 Figure 8 4 The Dataset Browser 1 0 0 0 eee eee eee e ees 225 Figure 8 5 Dataset Snapshot Dialog 2 2ec eben ee eee ee ee rh 228 Figure 8 6 Virtual Objects Indicated by Orange Diamond 04 230 Figure 9 1 Undocking the Wave Window 0 0 0 cece ee eect eens 234 Figure 9 2 Docking the Wave Window 0 0c eee e eee e 235 Mode
296. ed e Suggested action Reinstall ModelSim with all three files Too few port connections Warning vsim 3017 foo v 1422 TFMPC Too few port connections Expected 2 found 1 Region foo tb e Description This warning occurs when an instantiation has fewer port connections than the corresponding module definition The warning doesn t necessarily mean anything is wrong it is legal in Verilog to have an instantiation that doesn t connect all of the pins However someone that expects all pins to be connected would like to see such a warning Here are some examples of legal instantiations that will and will not cause the warning message Module definition module foo a b c qd Instantiation that does not connect all pins but will not produce the warning foo instl e f g positional association foo instl a e b f c g d named association Instantiation that does not connect all pins but will produce the warning foo instl e f g positional association foo instl a e b f c g named association ModelSim User s Manual v6 3g 413 May 2008 Error and Warning Messages Enforcing Strict 1076 Compliance Any instantiation above will leave pin d unconnected but the first example has a placeholder for the connection Here s another example foo instl e g h foo instl a e b c g d h e Suggested actions o Check that there is not an
297. ed for resolved signals But if you prefer freeze as the default for both resolved and unresolved signals you can change the defaults in the modelsim ini file vsim Default Force Kind The choices are freeze drive or deposit DefaultForceKind freeze ModelSim User s Manual v6 3g 401 May 2008 Simulator Variables Variable Precedence Restart Command Defaults The restart command has force nobreakpoint nofcovers nolist nolog and nowave options You can set any of these as defaults by entering the following line in the modelsim ini file DefaultRestartOptions lt options gt where lt options gt can be one or more of force nobreakpoint nofcovers nolist nolog and nowave Example DefaultRestartOptions nolog force VHDL Standard You can specify which version of the 1076 Std ModelSim follows by default using the VHDL93 variable VHDL93 variable selects language version as the default Default is VHDL 2002 Value of 0 or 1987 for VHDL 1987 Value of 1 or 1993 for VHDL 1993 Default or value of 2 or 2002 for VHDL 2002 VHDL93 2002 Opening VHDL Files You can delay the opening of VHDL files with an entry in the ZMI file if you wish Normally VHDL files are opened when the file declaration is elaborated If the DelayFileOpen option is enabled then the file is not opened until the first read or write to that file vsim DelayFileOpen 1 Variable
298. ed in any order as they are not order dependent See Compiling Verilog Files for details Compiling VHDL vcom ModelSim s compiler for VHDL design units is vcom VHDL files must be compiled according to the design requirements of the design Projects may assist you in determining the compile order for more information see Auto Generating Compile Order See Compiling VHDL Files for details on VHDL compilation ModelSim User s Manual v6 3g 27 May 2008 Introduction Basic Steps for Simulation Step 3 Loading the Design for Simulation vsim topLevelModule Your design is ready for simulation after it has been compiled You may then invoke vsim with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking the design together by connecting the ports and resolving hierarchical references Using SDF You can incorporate actual delay values to the simulation by applying SDF back annotation files to the design For more information on how SDF is used in the design see Specifying SDF Files for Simulation Step 4 Simulating the Design Once the design has been successfully loaded the simulation time is set to zero and you must enter a r
299. ed with a particular third party A current list of Mentor Graphics trademarks may be viewed at www mentor com terms_conditions trademarks cfm Table of Contents Chapter 1 Introduction PPP Pr m 23 Tool Structure and Plow se chssq beochPercbetensesabeeRRerzmOtAnrqeki ee adara 23 Simulation Task Overview as eese x3 24644465608 444 RO eg eR e ICH ER ES ME REN 24 Basic Steps for Simulation sa core pa cede RE RENE RE CEFQGG PENA TEARS RES 25 Step 1 Collecting Files and Mapping Libraries eese 26 Step 2 Compiling the Design vlog vcom sccOM 0 ec eee eee eee eee 27 Step 3 Loading the Design for Simulation 28 Step 4 Simulating the Design 28 Step 5 Debugging the Design 4 452 vow qo eek Iu Ke xS RES i 28 Modes of Operatolr a 2s sexa d kA PRYGGORSGeRA X REG UPAGORG RR RN Ga ha X ER RA RR eas 20 Command Lime Mod s iu od deu rici dt 1r USE EV Red do ad 20 Batch Mode issus dk RA RG sa e EG ER DR QN RH or Rn Y RUP OE RA RUP ROUES RO UR E 30 Whalis al ODEO P Pr eee Saw eee ee os eae aes aes 30 Standards Supported iiis aae RE ERE RAEERTEASaR NERTRSRRSENT S newb kee d 31 AASSHTHDDIGHS ea be errr E C e E Roe a ae r DN Eare 31 Sections In This DOPUDSUE v Log VERO P DWRPRRA NEU PERTH WPTPRR UEKPERE EY QS 32 Text Conventions a dee RE Ex Rd exRERREQIRERCL RI M ERN QE ES eePECE Eder S EE E 33 Installation Directory Pathnames 2 4243 Ses 4E RE XA nde sada ae oon ed eke ea es 33 De
300. ed with Projects ModelSim automatically creates a working design library If you don t create a project you need to create a working design library before you run the compiler This can be done from either the command line or from the ModelSim graphic interface From the ModelSim prompt or a UNIX DOS prompt use this vlib command vlib lt directory_pathname gt To create a new library with the graphic interface select File gt New gt Library Figure 5 1 Creating a New Library Create C amap to an existing library Library Name work Library Physical Name work When you click OK ModelSim creates the specified library directory and writes a specially formatted file named info into that directory The _info file must remain in the directory to distinguish it as a ModelSim library The new map entry is written to the modelsim ini file in the Library section Refer to Library Path Variables for more information Note Remember that a design library is a special kind of directory The only way to create a library is to use the ModelSim GUI or the vlib command Do not try to create libraries using UNIX DOS or Windows commands Managing Library Contents Library contents can be viewed deleted recompiled edited and so on using either the graphic interface or command line ModelSim User s Manual v6 3g 131 May 2008 Design Libraries Working with Design Libraries The Library
301. eform viewing 394 saving 220 saving at intervals 227 WLFCacheSize ini file variable 393 WLFCollapseMode ini file variable 393 WLFCompress ini variable 393 WLFDeleteOnQuit ini variable 394 491 ABCDEFGHIJKLMNOPQRSTUVWXYZ WLFFilename ini file variable 394 WLFSaveAllRegions ini variable 394 WLFSimCacheSize ini variable 394 WLFsSizeLimit ini variable 395 WLFTimeLimit ini variable 395 work library 130 creating 131 workspace 41 WRITE procedure problems with 150 nns X tracing unknowns 281 zero delay elements 146 zero delay mode 204 zero delay loop infinite 148 zero delay oscillation 148 zero delay race condition 185 zoom Dataflow window 290 saving range with bookmarks 245 zooming window panes 460 492 ModelSim User s Manual v6 3g May 2008 Third Party Information This section provides information on third party software that may be included in the ModelSim product including any additional license terms e This product may include Valgrind third party software Julian Seward All rights reserved THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF
302. elSim User s Manual v6 3g 261 May 2008 Waveform Analysis Printing and Saving Waveforms in the Wave window e Select File gt Load Note Window format files are design specific Use them only with the design you were simulating when they were created Printing and Saving Waveforms in the Wave window You can print the waveform display or save it as an encapsulated postscript EPS file Saving a eps Waveform File and Printing in UNIX Select File gt Print Postscript Wave window to print all or part of the waveform in the current Wave window in UNIX or save the waveform as a eps file on any platform see also the write wave command Printing from the Wave Window on Windows Platforms Select File gt Print Wave window to print all or part of the waveform in the current Wave window or save the waveform as a printer file a Postscript file for Postscript printers Printer Page Setup Select File gt Page setup or click the Setup button in the Write Postscript or Print dialog box to define how the printed page will appear Saving List Window Data to a File Select File gt Write List in the List window to save the data in one of these formats e Tabular writes a text file that looks like the window listing ns delta a b cin sum cout 0 0 X X U X U 0 1 0 1 0 X U 2 0 0 1 0 X U e Events writes a text file containing transitions during simulation 262 ModelSim User s Manual v6 3g May 2008
303. emplates Language Templates PN New Design Wizard z Create Testbench s 27 for i 4 bO carry 4 Module 28 begin Primitive 29 increment i val i D Declarations 30 carry val i amp carry S Statements 31 end Til Instantiations 32 end Compiler Directives 33 et uneton 34 35 always posedge clk or posedge 36 mp if reset 37 count tpd reset to count 38 else S System Tasks and Functions Stimulus Generators ga wave Ih counter h tcounter v Opening Source Files You can open source files using the File Open command or by clicking the Open icon Alternatively you can open source files by double clicking objects in other windows For example if you double click an item in the Objects window or in the structure tab sim tab of the Workspace the underlying source file for the object will open in the Source window and scroll to the line where the object is defined By default files you open from within the design e g by double clicking an object in the Objects pane open in Read Only mode To make the file editable right click in the Source window and select uncheck Read Only To change this default behavior set the PrefSource ReadOnly variable to 0 See Simulator GUI Preferences for details on setting preference variables 64 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Source Window Displaying Multiple Source Files By default each file you open or c
304. enes 326 Table 13 1 VCD Commands and SystemTasks llleleeeleeeeeeee 333 Table 13 2 VCD Dumpport Commands and System Tasks 00 334 Table 13 3 VCD Commands and System Tasks for Multiple VCD Files 334 Table 13 4 SystemC TYpeS 22ic2ieeavaubrebasehaseewgavsetdaxcdarebarauateds 335 Table 13 5 Driver States asesan daa esee hb RED pes ers ele deed NO d ARAS 340 Table 13 6 State When Direction is Unknown 0 0 cee eee eee 340 Table 13 7 Driver Strength 2212s pera e h tkeea ber nw 9 hierani irie raea Ehi 341 Table 13 8 Values for file format Argument 0 0 ee eee eee eee 342 Table 13 9 Sample Driver Dalila ice Re deenseen Secs Seer SE enee ee Sern d 343 Table 14 1 Changes to ModelSim Commands 0 0 0 e ee eee eee 346 Table 14 2 Tcl Backslash Sequences 0 0 cece eee ete 348 Table 14 5 Tel List Commands o 22d 2r udu nee S ERE aE eased eae beds ERES 352 Table 14 4 Simulator Specific Tcl Commands 0 0 0 cece eee eee 352 Table 14 5 Tcl Time Conversion Commands 0 0 0 cece eee ee eee 354 Table 14 6 Tcl Time Relation Commands 0 0 0 0 354 Table 14 7 Tcl Time Arithmetic Commands slleleeeeeeeeeeeee 355 Table 14 8 Commands for Handling Breakpoints and Errors in Macros 360 Table A 1 Add Library Mappings to modelsim ini File 00000 5 368 Table A 2 License Variable License Opti
305. ently but they have different implementations The signal based architecture rtl is not a recommended style spraml entity work sp_syn_ram_protected GENERIC MAP data width gt 8 addr width gt 12 PORT MAP inclk gt clk outclk gt clk we gt we addr gt addr 11 downto 0 data in gt data inl data out data spl clock generator clock driver PROCESS BEGIN clk lt 0 WAIT FOR clk_pd 2 LOOP clk lt 1 0 AFTER clk pd 2 WAIT FOR clk pg END LOOP END PROCESS data in process datain drivers PROCESS data in BEGIN data inl std logic vector data in 7 downto 0 END PROCESS simulation control process ctrl sim PROCESS ModelSim User s Manual v6 3g May 2008 VHDL Simulation Modeling Memory 165 VHDL Simulation Modeling Memory SEVERITY failure END PROCESS END testbench 166 BEGIN FOR i IN 0 TO 1023 LOOP we lt 11 data in lt to unsigned 9000 i data in lengtnh addr lt to unsigned i addr lengtnh inaddr lt to unsigned i inaddr length outaddr lt to unsigned i outaddr length WAIT UNTIL clk EVENT AND clk 0 WAIT UNTIL clk EVENT AND clk
306. enu in Project Tab of Workspace Workspace Name jsteus Type Order Modified C Design Files Folder H HDL Folder counter 07 12 07 Edit 07 12 07 08 52 18 PM Execute Compile Compile Selected Add to Project LEN Remove from Project Compile ut of Date Close Project Compile Order Update Compile Report N Compile Summary Properties Project Settings Compile Properties n Library Once compilation is finished click the Library tab expand library work by clicking the and you will see the compiled design units Figure 4 7 Click Plus Sign to Show Design Hierarchy Workspace mam Type work Library work T test_counter Module C Tutorial examples tutorials n counter Module C Tutorial examples tutorials Hl mtem Library MODEL TECH Javm i sv std Library MODEL TECH sv std i vital2000 Library MODEL TECH vital2000 i Library MODEL_TECH fieee Changing Compile Order The Compile Order dialog box is functional for HDL only designs When you compile all files in a project ModelSim by default compiles the files in the order in which they were added to the project You have two alternatives for changing the default compile order 1 select and compile each file individually 2 specify a custom compile order To specify a custom compile order follow these steps 116 ModelSim User s Manual v6 3g May 2008 Projects Getting Star
307. eplaces elements first through last with vall val2 etc vaL Two other commands Isearch and Isort are also available for list manipulation See the Tcl man pages Help Tcl Man Pages for more information on these commands Simulator Tcl Commands These additional commands enhance the interface between Tcl and ModelSim Only brief descriptions are provided in Table 14 4 For more information and command syntax see Commands Table 14 4 Simulator Specific Tcl Commands alias creates a new Tcl procedure that evaluates the specified commands used to create a user defined alias find locates incrTcl classes and objects Ishift takes a Tcl list as argument and shifts it in place one place to the left eliminating the Oth element Isublist returns a sublist of the specified Tcl list that matches the specified Tcl glob pattern 352 ModelSim User s Manual v6 3g May 2008 Tcl and Macros DO Files Simulator Tcl Time Commands Table 14 4 Simulator Specific Tcl Commands printenv echoes to the Transcript pane the current names and values of all environment variables Simulator Tcl Time Commands ModelSim Tcl time commands make simulator time based values available for use within other Tcl procedures Time values may optionally contain a units specifier where the intervening space is also optional If the space is present the value must be quoted e g 10ns 10 ns Time values without units are taken to be
308. er or process Depending on the specific object you click the view will expand to show the driving process and interconnect the reading process and interconnect or both Alternatively you can select a signal register or net and use one of the toolbar buttons or menu commands described in Table 10 1 Table 10 1 Icon and Menu Selections for Exploring Design Connectivity Expand net to all drivers Navigate Expand net to drivers 2e display driver s of the selected signal net or register 278 ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Table 10 1 Icon and Menu Selections for Exploring Design Connectivity Expand net to all drivers and readers Navigate gt Expand net display driver s and reader s of the selected signal net or register Expand net to all readers Navigate gt Expand net to readers display reader s of the selected signal net or register As you expand the view the layout of the design may adjust to show the connectivity more clearly For example the location of an input signal may shift from the bottom to the top of a process Tracking Your Path Through the Design You can quickly traverse through many components in your design To help mark your path the objects that you have expanded are highlighted in green Figure 10 3 Green Highlighting Shows Your Path Through the Design RASSIGN 7 1 strb Ae nu AND 22 m
309. er Software this Agreement or the rights under it whether by operation of law or otherwise attempted transfer without Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may at Mentor Graphics option result in the immediate termination of the Agreement and licenses granted under this Agreement The terms of this Agreement including without limitation the licensing and assignment provisions shall be binding upon your successors in interest and assigns The provisions of this section 4 shall survive the termination or expiration of this Agreement LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or improper installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EX
310. er System Information 0000005 356 Example 14 7 Tcl Used to Specify Compiler Arguments 0000 5 357 Example 14 8 Tcl Used to Specify Compiler Arguments Enhanced 357 Example 14 9 Specifying Files to Compile With argc Macro 0000 5 359 Example 14 10 Specifying Compiler Arguments With Macro 04 359 Example 14 11 Specifying Compiler Arguments With Macro Enhanced 359 Example C 1 VPI Application Registration 0 0 cece eee eee 421 Example E 1 Configure Window Layouts Dialog Box 0 0 0 0 ee eee 458 15 ModelSim User s Manual v6 3g May 2008 List of Figures Figure 1 1 Tool Structure and Flow ModelSim 0 0 0 0 eee eee eee 24 Figure 2 1 Graphical User Interface 22 22 ees ec ees ERR RR ERROR ES 33 Figure 2 2 User Defined Radix States in the Wave Window 00 5 39 Figure 2 3 User Defined Radix States in the List Window 0 0 5 39 Figure 2 4 Main Window sub 5945000 I RE R P F ER Coo eerie eden d See Soon E NER 40 Figure 2 5 Tabs in the MDI Frame 2uasdue RA cue ERR dare Y LX REFERT E ysees 42 Figure 2 6 Organizing Files in Tab Groups 0 0 cece eee eee eee 43 Figure 2 7 Main Window Status Bar llle 44 Figure 2 8 Process Window cs se kp Ep bocce RESO Ran RE ade Xr oe eae ed 48 Figure 2 0 Call Stack Pafe Lesen iurEe ARE TRI E R TR
311. erface VPI or the SystemVerilog DPI Direct Programming Interface If the simulator issues warnings regarding undefined system tasks or functions then it is likely that these tasks or functions are defined by a PLI VPI application that must be loaded by the simulator IEEE Std 1364 System Tasks and Functions The following supported system tasks and functions are described in detail in the IEEE Std 1364 204 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Note 3 The change command can be used to modify local variables in Verilog and SystemVerilog tasks and functions Table 7 4 IEEE Std 1364 System Tasks and Functions 1 Timescale tasks Simulator control Simulation time Command line input tasks functions printtimescale finish realtime test plusargs timeformat stop stime value plusargs time Table 7 5 IEEE Std 1364 System Tasks and Functions 2 Probabilistic Conversion Stochastic analysis Timing check tasks distribution functions tasks functions dist_chi_square bitstoreal q_add hold dist_erlang itor q_exam nochange dist_exponential realtobits q_full period dist_normal rtoi q_initialize recovery dist_poisson signed q_remove setup dist_t Sunsigned setuphold dist_uniform skew random width removal recrem 1 Verilog XL ignores the threshold argument even though it is part of the Verilog spec ModelSim does not ig
312. eric Matching An SDF file contains delay and timing constraint data for cell instances in the design The annotator must locate the cell instances and the placeholders VHDL generics for the timing data Each type of SDF timing construct is mapped to the name of a generic as specified by the VITAL modeling specification The annotator locates the generic and updates it with the timing value from the SDF file It is an error if the annotator fails to find the cell instance or the named generic The following are examples of SDF constructs and their associated generic names Table 12 1 Matching SDF to VHDL Generics IOPATH a y 3 tpd_a_y IOPATH posedge clk q 1 2 tpd_clk_q_posedge INTERCONNECT ul y u2 a 5 tipd_a SETUP d posedge clk 5 tsetup_d_clk_noedge_posedge HOLD negedge d posedge clk 5 thold_d_clk_negedge_posedge SETUPHOLD d clk 5 5 tsetup_d_clk amp thold_d_clk WIDTH COND reset 1 b0 clk 5 tpw_clk_reset_eq_0 The SDF statement CONDELSE when targeted for Vital cells is annotated to a tpd generic of the form tpd_ lt inputPort gt _ lt outputPort gt ModelSim User s Manual v6 3g 317 May 2008 Standard Delay Format SDF Timing Annotation Verilog SDF Resolving Errors If the simulator finds the cell instance but not the generic then an error message is issued For example Error vsim SDF 3240 myasic sdf 18 Instance testbench dut ul does not have a ge
313. ering up the Objects pane If the virtual signal has elements from more than one WLF file it will be automatically installed in the virtual region virtuals Signals 230 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Virtual Objects Virtual signals are not hierarchical if two virtual signals are concatenated to become a third virtual signal the resulting virtual signal will be a concatenation of all the scalar elements of the first two virtual signals The definitions of virtuals can be saved to a macro file using the virtual save command By default when quitting ModelSim will append any newly created virtuals that have not been saved to the virtuals do file in the local directory If you have virtual signals displayed in the Wave or List window when you save the Wave or List format you will need to execute the virtuals do file or some other equivalent to restore the virtual signal definitions before you re load the Wave or List format during a later run There is one exception implicit virtuals are automatically saved with the Wave or List format Implicit and Explicit Virtuals An implicit virtual is a virtual signal that was automatically created by ModelSim without your knowledge and without you providing a name for it An example would be if you expand a bus in the Wave window then drag one bit out of the bus to display it separately That action creates a one bit virtual signal who
314. ero with the option of maintaining various settings and objects Simulate gt Run gt Restart E Run Length specify the run length for the current simulation Simulate gt Runtime Options Run run the current simulation for the specified run length Simulate gt Run gt Run default_run_length eh EJ Continue Run continue the current simulation run until the end of the specified run length or until it hits a breakpoint or specified break event Simulate Run Continue run continue ModelSim User s Manual v6 3g May 2008 Graphical User Interface Process Window Table 2 6 Main Window Toolbar Buttons Menu equivalent Command equivalents Run All Simulate gt Run gt Run All run all run the current simulation forever or until it hits a breakpoint or specified break event Step Simulate gt Run gt Step step the current simulation to the next statement Step Over Simulate gt Run gt step over HDL statements are executed but Step Over treated as simple statements instead of entered and traced line by line Contains filter items in Objects and Workspace panes CO Contains e Show Language Templates Source Show Language display language templates Templates Process Window The Process window displays a list of HDL processes These processes are also displayed in the Structure tabs of the Workspace window By default the Process wi
315. err Writing the logo causes Tcl to think an error occurred If you have Cygwin installed make sure that the Cygwin ink exe executable is not in your search path ahead of the Microsoft Visual C link executable If you mistakenly bind your dll s with the Cygwin ink exe executable the d will not function properly It may be best to rename or remove the Cygwin ink exe file to permanently avoid this scenario e MinGW C Version 3 2 3 g c l lt install_dir gt modeltech include app cpp g shared Bsymbolic o app dll app o L lt install_dir gt modeltech win32 Imtipli ModelSim requires the use of the MinGW gcc compiler rather than the Cygwin gcc compiler DPI Imports on Windows Platforms C When linking the shared objects be sure to specify one export option for each DPI imported task or function in your linking command line You can use Verilog s isymfile option to obtain a complete list of all imported tasks and functions expected by ModelSim DPI Special Flow for Exported Tasks and Functions Since the Windows platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to compile the HDL source files into the shared object file You need to invoke a special run of vsim The command is as follows vsim lt top du list gt dpiexportobj lt objname gt lt other args gt 432 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Specifying Application Fil
316. es are ignored by default unless the protect argument is used with vlog Once compiled the original source file is copied to a new file in the current work directory The vlog protect command produces a vp or a svp extension to distinguish it from other non encrypted Verilog and SystemVerilog files respectively For example ModelSim User s Manual v6 3g 101 May 2008 Protecting Your Source Code Usage Models for Protecting Source Code top v becomes top vp and cache sv becomes cache svp This new file can be delivered and used as a replacement for the original source file Note The vencrypt utility may be used if the code also contains undefined macros or directives but the code must then be compiled and simulated with ModelSim You can use vlog protect lt filename gt to create an encrypted output file with the designated filename in the current directory not in the work directory as in the default case where lt filename gt is not specified For example vlog test v protect test vp If the filename is specified in this manner all source files on the command line will be concatenated together into a single output file Any include files will also be inserted into the output file protect and endprotect directives cannot be nested If errors are detected in a protected region the error message always reports the first line of the protected block Using the include Compiler Directi
317. es much more memory This style should be avoided Architectures style 57 and style_93 work with equal efficiently However VHDL 1993 offers additional flexibility because the ram storage can be shared between multiple processes For example a second process is shown that initializes the memory you could add other processes to create a multi ported memory To implement this model you will need functions that convert vectors to integers To use it you will probably need to convert integers to vectors Example functions are provided below in package conversions For completeness sake we also show an example using VHDL 2002 protected types though in this example protected types offer no advantage over shared variables ModelSim User s Manual v6 3g 159 May 2008 VHDL Simulation Modeling Memory VHDL87 and VHDL93 Example library ieee use ieee std logic 1164 all use work conversions all entity memory is generic add bits integer 12 data bits integer 32 port add in in std ulogic vector add bits 1 downto 0 data in in std ulogic vector data bits 1 downto 0 data out out std ulogic vector data bits 1 downto 0 cs mwrite in std ulogic do init in std ulogio subtype word is std ulogic vector data bits 1 downto 0 constant nwords integer 2 add bits type ram type is array 0 to nwords 1 of word end architecture style 93 of memory is shared variable ram ram type begin
318. es specified with Lf arguments in the order they appear on the command line Search the library specified in the Verilog XL uselib Compiler Directive section Search libraries specified with L arguments in the order they appear on the command line Search the work library Search the library explicitly named in the special escaped identifier instance name Handling Sub Modules with Common Names Sometimes in one design you need to reference two different modules that have the same name This situation can occur if you have hierarchical modules organized into separate libraries and you have commonly named sub modules in the libraries that have different definitions This may happen if you are using vendor supplied libraries For example say you have the following design configuration 174 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files Example 7 3 Sub Modules with Common Names top modA modB gt ba libl lib2 modA modB cellX cellX The normal library search rules fail in this situation For example if you load the design as follows vsim L lib1 L lib2 top both instantiations of cellX resolve to the lib version of cellX On the other hand if you specify L lib2 L lib1 both instantiations of cellX resolve to the lib2 version of cellX To handle this situation ModelSim implements a s
319. es to Load The dpiexportobj generates the object file lt objname gt obj that contains glue code for exported tasks and functions You must add that object file to the link line listed after the other object files For example if the object name was dpi the link line for MinGW would be g shared Bsymbolic o app dll app obj lt objname gt obj L lt install_dir gt modeltech win32 Imtipli Specifying Application Files to Load PLI and VPI file loading is identical DPI file loading uses switches to the vsim command PLI VPI file loading The PLI VPI applications are specified as follows e As alist in the Veriuser entry in the modelsim ini file Veriuser pliapp1 so pliapp2 so pliappn so e Asa list in the PLIOBJS environment variable setenv PLIOBJS pliapp1 so pliapp2 so pliappn so e As a pli argument to the simulator multiple arguments are allowed pli pliapp1 so pli pliapp2 so pli pliappn so Note LL On Windows platforms the file names shown above should end with d rather than so The various methods of specifying PLI VPI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases See also Simulator Variables for more information on the modelsim ini file DPI File Loading DPI applications are specified to vsim using the following SystemVerilog arguments Table C 2 vsim Ar
320. es you quick access to cursor and timeline features and configurations Figure 9 6 Wave Window Cursor Pane Now Cursor 1 200 ns Cursor 2 All of these panes can be resized by clicking and dragging the bar between any two panes In addition to these panes the Wave window also contains a Messages bar at the top of the window The Messages bar contains indicators pointing to the times at which a message was output from the simulator 236 ModelSim User s Manual v6 3g May 2008 Waveform Analysis List Window Overview Figure 9 7 Wave Window Messages Bar PR wave default List Window Overview The List window displays simulation results in tabular format Common tasks that people use the window for include e Using gating expressions and trigger settings to focus in on particular signals or events See Configuring New Line Triggering in the List Window e Debugging delta delay issues See Delta Delays for more information The window is divided into two adjustable panes which allows you to scroll horizontally through the listing on the right while keeping time and delta visible on the left Figure 9 8 Tabular Format of the List Window ee adsl File Edit View Add Tools Window 5 Uh psy ftest sm into test sm out wire deltay ftest sm outof ftest sm rst ftest sm clk 490000 0 00000030 171 O 1 juegue uda duda uu o ER Ru Ru 491000 1 00000030 T bE a 495000 0 oooo0000
321. ess during startup 467 msgmode ini file variable 399 msgmode variable 76 mti cosim trace environment variable 366 mti inhibit inline attribute 141 MTI TF LIMIT environment variable 366 MTI VOPT FLOW 367 multi file compilation issues SystemVerilog 175 MultiFileCompilationUnit ini file variable 3123 multiple document interface 42 Multiple simulations 219 N n simulator state variable 403 Name field Project tab 120 name visibility in Verilog generates 181 names modules with the same 174 Negative timing algorithm for calculating delays 192 check limits 192 constraint algorithm 195 constraints 193 delay solution convergence 195 syntax for recrem 194 syntax for setuphold 192 using delayed inputs for checks 200 nets Dataflow window displaying in 50 275 values of 482 JKLMNOPQRSTUVWXYZ displaying in Objects window 62 saving as binary log file 219 waveforms viewing 84 new function initialize SV object handle 190 Nlview widget Symlib format 284 NoCaseStaticError ini file variable 376 NOCHANGE matching to Verilog 323 NoDebug ini file variable 373 376 NoIndexCheck ini file variable 376 NOMMATP environment variable 367 non blocking assignments 187 NoOthersStaticError ini file variable 376 NoRangeCheck ini file variable 377 Note ini file variable 398 Notepad windows text editing 450 notrigger argument 268 NoVital ini file variable 377 NoVitalCheck ini file vari
322. essages generated from your design and subsequently written to the transcript file will cause the simulator to pause A transcript file that contains only valid simulator commands will work fine comment out anything else with a Stand alone tools pick up project settings in command line mode if they are invoked in the project s root directory If invoked outside the project directory stand alone tools pick up project settings only if you set the MODELSIM environment variable to the path to the project file Project Root Dir Project Name mpf Batch Mode Batch mode is an operational mode that provides neither an interactive command line nor interactive windows In a Windows environment vsim is run from a Windows command prompt and standard input and output are redirected from and to files Here is an example of a batch mode simulation using redirection of std input and output vsim counter yourfile outfile where yourfile is a script containing various ModelSim commands You can use the CTRL C keyboard interrupt to break batch simulation in UNIX and Windows environments What is an Object Because ModelSim works with so many languages Verilog VHDL SystemVerilog an object refers to any valid design element in those languages The word object is used 30 ModelSim User s Manual v6 3g May 2008 Introduction Standards Supported whenever a specific language reference is not needed Depending on the con
323. est the edge should be on a signal that is an output of the process Select Trace Trace input net to event A second cursor is added at the most recent input event Keep selecting Trace gt Trace next event until you ve reached an input event of interest Note that the signals with the events are selected in the wave viewer pane Now select Trace Trace Set The Dataflow display jumps to the source of the selected input event s The operation follows all signals selected in the wave viewer pane You can change which signals are followed by changing the selection To continue tracing go back to step 5 and repeat If you want to start over at the originally selected output select Trace Trace event reset Tracing the Source of an Unknown State StX Another useful Dataflow window debugging tool is the ability to trace an unknown state StX back to its source Unknown values are indicated by red lines in the Wave window Figure 10 5 and in the wave viewer pane of the Dataflow window ModelSim User s Manual v6 3g 281 May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Figure 10 5 Unknown States Shown as Red Lines in Wave Window m wave default Atop p data r Atop p rw r top p strb_r top p verbose top p t_out top p t_set top p rw_out top p test top p test2 top p _tw The procedure for tracing to the source of an unknown state in the Dataflo
324. esults With Datasets To split the window select Add gt Window Pane In the illustration below the top split shows the current active simulation with the prefix sim and the bottom split shows a second dataset with the prefix gold ModelSim User s Manual v6 3g 255 May 2008 Waveform Analysis Wave Groups Figure 9 25 Splitting Wave Window Panes m wave default File Edit View Add Format Tools Window B SHS XB gt me n sim test_sm dat 2222222222222222222 sim test_sm addr 0000110011 000000 000 000 Yo 3 sim test_sm loop WXKXXKMKXNNNKKNKKKNN sim test_sm i sim test_sm td_ gold test_sm clk gold test_sm out_ Previous simulation gold test_sm dat 22zz2zz2222222222222 d D gold gold test sm addr 0000110011 000000 000 5000 mag gold test sm loop XXKXXXXNXXKNXXXNXM gold test sm i gold test sm rd Current simulation sim 50400 ps to 565800 ps Now 750 ns Delta The Active Split The active split is denoted with a solid white bar to the left of the signal names The active split becomes the target for objects added to the Wave window Wave Groups You can create a wave group to collect arbitrary groups of items in the Wave window Wave groups have the following characteristics e A wave group may contain 0 1 or many items e You can add or remove items from groups either by using a command or by dragging and dropping e You can drag a
325. et I bz ftd set I bl ftd set 1 b0 end ftd set I bl end endmodule endmodule Case 1 Run the vsim command in the following order vsim mod2 mod1 Module 1 sets the simulator resolution to 10 ps Module 2 has no timescale directive so the time units default to the simulator resolution in this case 10 ps If you looked at mod1 set and mod2 set in the Wave window you would see that Module 1 transitions every 1 55 ns as expected because of the 1 ns time unit in the timescale directive However in Module 2 set transitions every 20 ps That is because the delay of 1 55 in Module 2 is read as 15 5 ps which is rounded up to 20 ps ModelSim issues the following warning message during elaboration Warning vsim 3010 TSCALE Module modl1 has a timescale directive in effect but previous modules do not Case 2 Run the vsim command in the following order vsim mod1 mod2 ModelSim User s Manual v6 3g 183 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Module 2 sets the simulator resolution to its default 10 ps so the simulation results would be the same However ModelSim issues a different warning message Warning vsim 3009 TSCALE Module mod2 does not have a timescale directive in effect but previous modules do Note You should always investigate these warning messages to make sure that the timing of your design operates as intended C
326. et with the TMPDIR variable which allows you to find and delete the file in the event of a crash because an unnamed VSOUT file is not deleted after a crash TMP Windows environments The TMP environment variable specifies the path to a tempnam generated file VSOUT containing all stdout from the simulation kernel TMPDIR UNIX environments The TMPDIR environment variable specifies the path to a tempnam generated file VSOUT containing all stdout from the simulation kernel ModelSim User s Manual v6 3g 367 May 2008 Simulator Variables Environment Variables Creating Environment Variables in Windows In addition to the predefined variables shown above you can define your own environment variables This example shows a user defined library path variable that can be referenced by the vmap command to add library mapping to the modelsim ini file 1 From your desktop right click your My Computer icon and select Properties 2 Inthe System Properties dialog box select the Advanced tab 3 Click Environment Variables 4 In the Environment Variables dialog box and User variables for user pane select New 5 In the New User Variable dialog box add the new variable with this data Variable ame MY PATH Variable value temp work 6 OK New User Variable Environment Variable and System Properties dialog boxes Library Mapping with Environment Variables Once the MY PATH variable is set you can use it with the vm
327. eubwie 407 Message System oosexp o Ie pae oeira DF EATER ERAEN EA P I ualeri gx e E 407 Message Fommat V2 o Sae eeoRn Reste sei edP Red e ARE epe dee sd 407 Getting More Information sscdsd es p ERE E RE Er RA REA RS 407 Changing Message Severity Level 2cds252 0ssceseceteeeide pU ERE 408 Suppressing Warning Messages itesxessytesrewRa tesa cea exe qu eos wees oes 408 Suppressing VCOM Warning Messages 0 00 cece eee e 408 Suppressing VLOG Warning Messages lisse 409 Suppressing VSIM Warning Messages 0 0 ce eee eee eee tenes 409 Exit CCS MERETRICEM MICUPTD PI Ee aA E E E Ear 410 Miscellaneous Messages 4 ode EE ROV S40 ERR PERSO eS Eee OE eee ee Lu hee ees 411 Enforcing Strict 1076 Compliance 2 22 due x Oe Reed eb RR ae ep sow Ra 414 Appendix C Verilog PLUVPUDPI ii4ssssat amp kerb etesPRRATYAAUREFRA EAT ERAR C ERRENAS ADR 417 Implementation Information 1 54 redes i PeterecsRbeeRPRer3 RO t amp mr4 p RR AIRE 417 g Compiler Support for use with PLUVPUDPI sese BIB 419 Registering PLI Applications 29 See RR RE C REA RREQEEPAREER Te RS ER Eque 419 Registering VPI Applications 22x uk esx RR RR AR ERER E Rae A REPE Ire ERE REA 421 Registering DPI Applications 2222934426 Ret EUER RPER ERRARE RC CRI PER RS 422 B aS Sd 423 Integrating Export Wrappers into an Import Shared Object 00 425 When Your DPI Export Function is Not Getting Called
328. ew name or by clicking the Edit this cursor icon The Edit this cursor icon will open the Cursor Properties dialog Figure 9 12 where you assign a cursor name and time You can also lock the cursor to the specified time Figure 9 12 Cursor Properties Dialog Box Cursor Properties 2 xl Cursor Mame Cursor 1 r Cursor Time Ons Lock cursor to specified time OK Cancel Working with Cursors The table below summarizes common cursor actions Table 9 2 Actions for Cursors Action Menu command Menu command Icon Wave window docked Wave window undocked Add gt Wave gt Cursor Add gt Cursor ModelSim User s Manual v6 3g 241 May 2008 Waveform Analysis Measuring Time with Cursors in the Wave Window Edit cursor Table 9 2 Actions for Cursors cont Menu command Wave window docked Wave gt Edit Cursor Menu command Wave window undocked Edit gt Edit Cursor Delete cursor Wave gt Delete Cursor Edit gt Delete Cursor Zoom In on Active Cursor Wave gt Zoom gt Zoom Cursor View gt Zoom gt Zoom Cursor Lock cursor Select a cursor Wave gt Edit Cursor Wave gt Cursors Edit gt Edit Cursor View gt Cursors Shortcuts for Working with Cursors There are a number of useful keyboard and mouse shortcuts related to the actions listed above Select a cursor by clicking the cursor name Jump to a hidden curs
329. extra comma at the end of the port list e g model a b The extra comma is legal Verilog and implies that there is a third port connection that is unnamed o If you are purposefully leaving pins unconnected you can disable these messages using the nowarnTFMPC argument to vsim VSIM license lost Console output Signal 0 caught Closing vsim vlm child vsim is exiting with code 4 FATAL ERROR in license manager transcript vsim output Error VSIM license lost attempting to re establish Time 5027 ns Iteration 2 Fatal Unable to kill and restart license process Time 5027 ns Iteration 2 e Description ModelSim queries the license server for a license at regular intervals Usually these License Lost error messages indicate that network traffic is high and communication with the license server times out e Suggested action Anything you can do to improve network communication with the license server will probably solve or decrease the frequency of this problem Enforcing Strict 1076 Compliance The optional pedanticerrors argument to vcom enforces strict compliance to the IEEE 1076 LRM in the cases listed below The default behavior for these cases is to issue an insuppressible warning message If you compile with pedanticerrors the warnings change to an error unless otherwise noted Descriptions in quotes are actual warning error messages emitted by vcom
330. fault S R n Time T Iteration WD K i File F n MessageFormatFatal This variable defines the format of messages for VHDL Fatal assertions ModelSim User s Manual v6 3g 387 May 2008 Simulator Variables Simulator Control Variables If undefined MessageFormat is used unless assertion causes a breakpoint in which case MessageFormatBreak is used e Value Range Refer to Table A 3 Default S R n Time T Iteration WD K i File F n MessageFormatNote This variable defines the format of messages for VHDL Note assertions If undefined MessageFormat is used unless assertion causes a breakpoint in which case MessageFormatBreak is used e Value Range Refer to Table A 3 Default S R n Time T Iteration D I n MessageFormatWarning This variable defines the format of messages for VHDL Warning assertions If undefined MessageFormat is used unless assertion causes a breakpoint in which case MessageFormatBreak is used e Value Range Refer to Table A 3 e Default S R n Time T Iteration D I n NumericStdNoWarnings This variable disables warnings generated within the accelerated numeric_std and numeric_bit packages e Value Range 0 1 e Default off 0 OnFinish This variable controls the behavior of the tool when it encounters either an assertion failure a finish in the design code e Value Range e ask o In batch mode the simulation exits 388 ModelSim User
331. ferences Allows you to specify the preferences of the List window e File gt Export gt Tabular List Exports the information in the List window to a file in tabular format Equivalent to the command write list lt filename gt e File gt Export gt Event List Exports the information in the List window to a file in print on change format Equivalent to the command write list event lt filename gt ModelSim User s Manual v6 3g 55 May 2008 Graphical User Interface Locals Window e File gt Export gt TSSI List Exports the information in the List window to a file in TSSI Equivalent to the command write tssi event filename e Edit Signal Search Allows you to search the List window for activity on the selected signal Locals Window The Locals window displays data objects declared in the current or local scope of the active process These data objects are immediately visible from the statement that will be executed next which is denoted by a blue arrow in the Source editor window The contents of the window change from one statement to the next Figure 2 12 Locals Window addr_size set_size word_size size dly line__43 e data_mem QUUUUUUUUUUUL fs atag_mem UUU UUU UU fs valid_mem False False false False Displaying the Locals Window e Select View gt Locals e Use the command view locals Viewing Data in the Locals Window You cannot actively pla
332. file memory vcd top m run 1000 Next simulate your design and map the instances to the VCD files you created vsim top vcdstim top p proc vcd vcdstim top c cache vcd vcdstim top mzmemory vcd 332 ModelSim User s Manual v6 3g May 2008 Value Change Dump VCD Files VCD Commands and VCD Tasks Port Order Issues The vcdstim argument to the vcd dumpports command ensures the order that port names appear in the VCD file matches the order that they are declared in the instance s module or entity declaration Consider the following module declaration module proc clk addr data rw strb rdy input clk rdy output addr rw strb inout data The order of the ports in the module line clk addr data does not match the order of those ports in the input output and inout lines clk rdy addr In this case the vcdstim argument to the vcd dumpports command needs to be used In cases where the order is the same you do not need to use the vcdstim argument to vcd dumpports Also module declarations of the form module proc input clk output addr inout data do not require use of the argument VCD Commands and VCD Tasks ModelSim VCD commands map to IEEE Std 1364 VCD system tasks and appear in the VCD file along with the results of those commands The table below maps the VCD commands to their associated tasks Table 13 1 VCD Commands and SystemTasks VCD commands VCD system tasks ved add dump
333. files Apple hereby grants permission to use copy modify distribute and license this software and its documentation for any purpose provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions No written agreement license or royalty fee is required for any of the authorized uses Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here provided that the new terms are clearly indicated on the first page of each file where they apply IN NO EVENT SHALL APPLE THE AUTHORS OR DISTRIBUTORS OF THE SOFTWARE BE LIABLE TO ANY PARTY FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE ITS DOCUMENTATION OR ANY DERIVATIVES THEREOF EVEN IF APPLE OR THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE APPLE THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT THIS SOFTWARE IS PROVIDED ON AN AS IS BASIS AND APPLE THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE SUPPORT UPDATES ENHANCEMENTS OR MODIFICATIONS GOVERNMENT USE If you are acquiring this software on behalf of the U S government the Government shall have only Restricted Rights in the software and related documentation as de
334. fined in the Federal Acquisition Regulations FARs in Clause 52 227 19 c 2 If you are acquiring the software on behalf of the Department of Defense the software shall be classified as Commercial Computer Software and the Government shall have only Restricted Rights as defined in Clause 252 227 7013 c 1 of DFARs Notwithstanding the foregoing the authors grant the U S Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license The following terms apply to all files originating from Apple Computer Inc Apple and associated with the software unless explicitly disclaimed in individual files This software application may include Advanced Verification Methodology third party software Refer to the license file in your install directory lt install_directory gt verilog_src avm LICENSE txt This software application may include libtecla 1 6 1 third party software that may be subject to the following terms of use and copyright s Copyright c 2000 2001 2002 2003 2004 by Martin C Shepherd All rights reserved Permission is hereby granted free of charge to any person obtaining a copy of this software and associated documentation files the Software to deal in the Software without restriction including without limitation the rights to use copy modify merge publish distribute and or sell copies of the Software and to permit persons
335. for any of the authorized uses Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here provided that the new terms are clearly indicated on the first page of each file where they apply IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE ITS DOCUMENTATION OR ANY DERIVATIVES THEREOF EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT THIS SOFTWARE IS PROVIDED ON AN AS IS BASIS AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE SUPPORT UPDATES ENHANCEMENTS OR MODIFICATIONS This software application may include Tk third party software 1994 Software Research Associates Inc 2002 by Ludwig Callewaert 1998 Paul Duffin 1999 Jan Nijtmans 2005 Tcl Core Team 2005 Daniel A Steffen lt das users sourceforge net gt 1993 1994 Lockheed Missle amp Space Company AI Center Reed Wade wade cs utk edu University of Tennessee 2000 Jeffrey Hobbs 2003 2006 Patrick Thoyts 2001 2002 David Gravereaux 1987 1993 Adobe Systems Incorporated All Rights Reserved 1994 The
336. g 175 compilation unit scope 175 compile order auto generate 117 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ changing 116 SystemVerilog packages 171 Compiler Control Variable SystemC CppOptions 380 Compiler Control Variables Verilog CoverCells 371 382 DisableOpt 372 GenerateLooplterationMax 372 GenerateRecursionDepthMax 372 Hazard 372 Incremental 372 LibrarySearchPath 372 MultiFileCompilationUnit 373 NoDebug 373 Quiet 373 Show_ WarnMatchCadence 374 Show_BadOptionWarning 373 Show_Lint 373 Show_source 374 Show_WarnCantDoCoverage 374 vlog95compat 374 VHDL AmsStandard 374 BindAtCompile 375 CheckSynthesis 375 DisableOpt 375 Explicit 376 Ignore VitalErrors 376 NoCaseStaticError 376 NoDebug 376 NolIndexCheck 376 NoOthersStaticError 376 NoRangeCheck 377 NoVital 377 NoVitalCheck 377 Optimize_1164 377 PedanticErrors 377 Quiet 377 RequireConfigForAllDefaultBinding 377 Show_Lint 378 Show_source 378 Show VitalChecksOpt 378 475 ABCDEFGHIJKLMNOPQRSTUVWXYZ Show VitalChecksWarning 378 Show WarnCantDoCoverage 378 Show Warningl 378 Show Warning10 379 Show Warning2 379 Show Warning3 379 Show Warning4 379 Show Warning5 379 Show Warning9 379 Show WarnLocallyStaticError 380 VHDL93 380 compiler directives 215 IEEE Std 1364 2000 215 XL compatible compiler directives 216 compiling overview 27 changing order in the GUI 116 grouping files
337. g May 2008 DO files macros error handling 361 executing at startup 365 391 parameters passing to 358 Tcl source command 361 docking window panes 459 DOPATH environment variable 364 DPI export TFs 411 missing DPI import function 426 registering applications 422 use flow 423 DPI access routines 443 DPI export TFs 411 DPI VPI PLI 417 drivers Dataflow Window 278 show in Dataflow window 269 Wave window 269 dumpports tasks VCD files 334 DumpportsCollapse ini file variable 383 E edit breakpoints 70 270 273 Editing in notepad windows 450 in the Main window 450 in the Source window 450 EDITOR environment variable 364 editor default changing 364 embedded wave viewer 279 empty port name warning 412 enable_signal_spy 297 encrypt IP code pulblic keys 99 undefined macros 98 vendor defined macros 100 IP source code 97 usage models 97 protect pragmas 97 vencrypt utility 97 vencrypt command header file 99 477 ABCDEFGH I vlog protect 100 101 encrypting IP code vencrypt utility 97 encryption protect compiler directive 101 securing pre compiled libraries 104 ENDFILE function 152 ENDLINE function 152 endprotect compiler directive 101 entities default binding rules 145 entity simulator state variable 403 environment variables 363 accessed during startup 468 expansion 363 referencing from command line 369 referencing with VHDL FILE variable 368 setti
338. g 181 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs In addition note that the keyword pair generate endgenerate is optional under the 2005 rules and are excluded in the second example Simulating Verilog Designs A Verilog design is ready for simulation after it has been compiled with vlog The simulator may then be invoked with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking the design together by connecting the ports and resolving hierarchical references By default all modules and UDPs are loaded from the library named work Modules and UDPs from other libraries can be specified using the L or Lf arguments to vsim see Library Usage for details On successful loading of the design the simulation time is set to zero and you must enter a run command to begin simulation Commonly you enter run all to run until there are no more simulation events or until finish is executed in the Verilog code You can also run for specific time periods e g run 100 ns Enter the quit command to exit the simulator Simulator Resolution Limit Verilog The simulator internally represents time as a 64 bit integer i
339. g design regions e Value Range 0 1 e Default 1 on GlobalSharedObjectsList This variable instruct the tool to load the specified PLI FLI shared objects with global symbol visibility e Value Range comma separated list of filenames e Default commented out IgnoreError This variable instructs the tool to disable runtime error messages e Value Range 0 1 e Default off 0 IgnoreFailure This variable instructs the tool to disable runtime failure messages e Value Range 0 1 e Default off 0 IgnoreNote This variable instructs the tool to disable runtime note messages e Value Range 0 1 e Default off 0 384 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables IgnoreWarning This variable instructs the tool to disable runtime warning messages e Value Range 0 1 e Default off 0 IterationLimit This variable specifies a limit on simulation kernel iterations allowed without advancing time e Value Range positive integer Default 5000 License This variable controls the license file search e Value Range one ore more of the following license option separated by spaces if using multiple entries Refer also to the vsim license option Table A 2 License Variable License Options license option Description Inlonly only use msimhdlsim and hdlsim mixedonly exclude single language licenses nomgc exclude MGC licenses exclude language neutral
340. g information using the g option and without optimizations for example don t use the O option 2 Load vsim into a debugger Even though vsim is stripped most debuggers will still execute it You can invoke the debugger directly on vsimk the simulation kernel where your application code is loaded for example ddd which vsimk or you can attach the debugger to an already running vsim process In the second case you must attach to the PID for vsimk and you must specify the full path to the vsimk executable for example gdb MTI HOME sunos5 vsimk 1234 On Solaris and Linux systems you can use either gdb or ddd 446 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Debugging PLI VPI DPI Application Code 3 Set an entry point using breakpoint Since initially the debugger recognizes only vsim s PLI VPI DPI function symbols when invoking the debugger directly on vsim you need to place a breakpoint in the first PLI VPI DPI function that is called by your application code An easy way to set an entry point is to put a call to acc_product_version as the first executable statement in your application code Then after vsim has been loaded into the debugger set a breakpoint in this function Once you have set the breakpoint run vsim with the usual arguments When the breakpoint is reached the shared library containing your application code has been loaded 4 In some debuggers you must use the share command
341. g strength and the output is driving a weak strength the resolved value is D d U or u and the strength is the strength of the input ModelSim User s Manual v6 3g 341 May 2008 Value Change Dump VCD Files Capturing Port Driver Data e If the input is driving a weak strength and the output is driving a strong strength the resolved value is L 1 H or h and the strength is the strength of the output Ignoring Strength Ranges You may wish to ignore strength ranges and have ModelSim handle each strength separately Any of the following options will produce this behavior e Use the no_strength_range argument to the vcd dumpports command e Use an optional argument to dumpports see Extended dumpports Syntax below e Use the dumpports no_strength_range argument to vsim command In this situation ModelSim reports strengths for both the zero and one components of the value if the strengths are the same If the strengths are different ModelSim reports only the winning strength In other words the two strength values either match e g pA 5 5 or the winning strength is shown and the other is zero e g pH 0 5 Extended dumpports Syntax ModelSim extends the dumpports system task in order to support exclusion of strength ranges The extended syntax is as follows Sdumpports scope list file pathname ncsim file index file format The nc sim index argument is required yet ignored by ModelSim It is required only to b
342. ge is part of the modelsim_lib library which is located in the modeltech tree and is mapped in the default modelsim ini file To include the utilities in this package add the following lines similar to your VHDL code library modelsim lib use modelsim lib util all get resolution The get resolution utility returns the current simulator resolution as a real number For example a resolution of 1 femtosecond 1 fs corresponds to 1e 15 Syntax resval z get resolution Returns Name Type Description resval real The simulator resolution represented as a real Arguments None Related functions to real e to time Example If the simulator resolution is set to 10ps and you invoke the command resval z get resolution the value returned to resval would be 1e 11 init signal driver The init signal driver utility drives the value of a VHDL signal or Verilog net onto an existing VHDL signal or Verilog net This allows you to drive signals or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench ModelSim User s Manual v6 3g 155 May 2008 VHDL Simulation Util Package See init_signal_driver for complete details init signal spy The init signal spy utility mirrors the value of a VHDL signal or Verilog register net onto an existing VHDL signal or Verilog register This allows you to reference signals registers or nets at any level of hierarchy from within a VHDL a
343. ging in the cursor pane below the waveforms Jumping to a Signal Transition You can move the active selected cursor to the next or previous transition on the selected signal using these two toolbar icons shown in Figure 9 13 Figure 9 13 Find Previous and Next Transition Icons Find Previous Find Next Transition Je Transition l locate the next signal locate the previous value change for the signal value change selected signal for the selected signal These actions will not work on locked cursors Setting Time Markers in the List Window Time markers in the List window are similar to cursors in the Wave window Time markers tag lines in the data table so you can quickly jump back to that time Markers are indicated by a thin box surrounding the marked line ModelSim User s Manual v6 3g 243 May 2008 Waveform Analysis Zooming the Wave Window Display Figure 9 14 Time Markers in the List Window a nm File Edit view Add Tools Window Signal Properties Goto sim test sm out El 510000 0 eiufufululalutatatelelatatateteletatatateleleiep RR Ru 511000 1 uu Te e d d d o n aaan D 511000 10010101011 515000 10010111011 520000 0 uus edd dude ed eue o o o o n o n 529000 1 uuu RD e d d o T o n n n o E 530000 0 531000 oooooo0o00000000000000001 oooooooo00000000000000001 oooooooo00000000000000001 EO O oJjoJjo 0 0000000000000000000000001 0 ooooo0O0000000000000000001 1
344. gn load time immediately after elaboration and used later Figure 10 2 illustrates the current and post sim usage flows for Dataflow debugging Figure 10 2 Dataflow Debugging Usage Flow compile design create database for post sim debug load design load design with vsim aie with vsim debugDB command run simulation CREATE post sim debug database recall post sim debug database with dataset open command Post Simulation Debug Flow Details The post sim debug flow for Dataflow analysis is most commonly used when performing simulations of large designs in simulation farms where simulation results are gathered over extended periods and saved for analysis at a later date In general the process consists of two steps creating the database and then using it The details of each step are as follows Create the Post Sim Debug Database 1 Compile the design using the vlog and or vcom commands 2 Load the design with the following commands 276 ModelSim User s Manual v6 3g May 2008 SF 4 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging vsim debugDB lt db_pathname dbg gt wlf db pathname wlf design name add log r Specify the post simulation database file name with the debugDB lt db_pathname gt argument to the vsim command If a database pathname is not specified ModelSim creates a database with the file name vsim dbg in the current working directory Sp
345. gned package 136 std logic textio 136 std logic unsigned package 136 StdArithNoWarnings ini file variable 391 STDOUT environment variable 367 steps for simulation overview 25 subprogram inlining 140 subprogram write is ambiguous error fixing 150 Suppress ini file variable 399 sv std ini file variable 371 symbol mapping Dataflow window 284 symbolic link to design libraries UNIX 134 synopsys ini file variable 370 Synopsys libraries 136 syntax highlighting 72 synthesis ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ rule compliance checking 375 system calls VCD 334 Verilog 204 system commands 351 system tasks proprietary 208 VCD 334 Verilog 204 Verilog XL compatible 212 SystemVerilog keyword considerations 170 multi file compilation 175 object handle initialize with new function 190 suppported implementation details 31 SystemVerilog DPI specifying the DPI file to load 433 SystemVerilog types radix 87 253 T tab groups 42 tab stops Source window 72 Tcl to 355 command separator 350 command substitution 349 command syntax 346 evaluation order 350 history shortcuts 449 preference variables 461 relational expression evaluation 350 time commands 353 variable substitution 351 VSIM Tcl commands 352 with escaped identifiers 202 Tcl_init error message 413 temp files VSOUT 369 testbench accessing internal objectsfrom 293 text and command sy
346. group around the Wave window or to another Wave window e You can nest multiple wave groups either from the command line or by dragging and dropping Nested groups are saved or restored from a wave do format file restart and checkpoint restore 256 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Wave Groups Creating a Wave Group There are two ways to create a wave group 1 Use the Tools gt Group menu selection a Select a set of signals in the Wave window b Select the Tools Group menu item The Wave Group Create dialog will appear Figure 9 26 Fill in the name of the group in the Group Name field E Wave Group Create x Group Name om Group Height OK Cancel c Click Ok The new wave group will be denoted by a red diamond in the Wave window pathnames Figure 9 27 Wave groups denoted by red diamond EX sim test sm addr 0000110011 0000770071 E sim test_sm loop HERRKRRKERRRKRERKRED mygroup sim test_sm i sim test_sm rd_ sim test_sm wr_ Now 746 ns to 750200 ps Now 750 ns Delta 2 2 Use the group argument to the add wave command Example 1 The following command will create a group named mygroup containing three items add wave group mygroup sigl sig2 sig3 Example 2 The following command will create an empty group named mygroup add wave group mygroup ModelSim User s Manual v6 3g 257 May 2008 Waveform Analysis Wave Groups
347. guments for DPI Application Argument Description sv lib lt name gt specifies a library name to be searched and used No filename extensions must be specified The extensions ModelSim expects are dll for Win32 so for all other platforms SV root lt name gt specifies a new prefix for shared objects as specified by sv lib ModelSim User s Manual v6 3g 433 May 2008 Verilog PLI VPI DPI PLI Example Table C 2 vsim Arguments for DPI Application sv_liblist specifies a bootstrap file to use When the simulator finds an imported task or function it searches for the symbol in the collection of shared objects specified using these arguments For example you can specify the DPI application as follows vsim sv_lib dpiapp1 sv_lib dpiapp2 sv_lib dpiappn top It is a mistake to specify DPI import tasks and functions tf inside PLI VPI shared objects However a DPI import tf can make calls to PLI VPI C code providing that vsim gblso was used to mark the PLI VPI shared object with global symbol visibility See Loading Shared Objects with Global Symbol Visibility Loading Shared Objects with Global Symbol Visibility On Unix platforms you can load shared objects such that all symbols in the object have global visibility To do this use the gblso argument to vsim when you load your PLI VPI application For example vsim pli obj1 so pli obj2 so gblso obj1 so top The gblso argument works in conjunction wi
348. gure 10 11 Configuring Dataflow Options Dataflow Options General options Warning options IV Hide cells V Keep Dataflow Keep previous contents i when adding new nets or Show Hierarchy instances to the DA o a v Bottom inout pins Disable Sprout Select equivalent nets Log nets v Select Environment v Automatic Add to Wave OK Cancel How Do Zoom and Pan the Display The Dataflow window offers tools for zooming and panning the display These zoom buttons are available on the toolbar Zoom In Zoom Out Zoom Full zoom in by a factor zoom out by a zoom out to view of two from the i factor of two from E the entire schematic current view current view To zoom with the mouse you can either use the middle mouse button or enter Zoom Mode by selecting View gt Zoom and then use the left mouse button Four zoom options are possible by clicking and dragging in different directions e Down Right Zoom Area In e Up Right Zoom Out zoom amount is displayed at the mouse cursor e Down Left Zoom Selected e Up Left Zoom Full The zoom amount is displayed at the mouse cursor A zoom operation must be more than 10 pixels to activate 290 ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference Panning with the Mouse You can pan with the mouse in two ways 1 enter Pan Mode by selecting View gt Pan and then drag with the left m
349. h Row Margin 4 pixels Justify Value Child Row Margin 7 Left C Right 2 pixels Enable Disable JV Waveform Popup Enabled Waveform Selection Highlighting Enabled v Double Click to Show Drivers Dataflow Window On Close Warn for Save Format Always undock wave window v On Close Warn for saving editable wave Commands Dataset Prefix Display C Always Show Dataset Prefixes Show Dataset Prefixes if 2 or more C Never Show Dataset Prefixes OK Cancel Hiding Showing Path Hierarchy You can set how many elements of the object path display by changing the Display Signal Path value in the Wave Window Preferences dialog Figure 9 20 Zero indicates the full path while a non zero number indicates the number of path elements to be displayed Setting the Timeline to Count Clock Cycles You can set the timeline of the Wave window to count clock cycles rather than elapsed time If the Wave window is docked in the MDI frame open the Wave Window Preferences dialog by selecting Tools Options Wave Preferences from the Main window menus If the Wave window is undocked select Tools Window Preferences from the Wave window menus This opens the Wave Window Preferences dialog In the dialog select the Grid amp Timeline tab Figure 9 21 ModelSim User s Manual v6 3g 251 May 2008 Waveform Analysis Formatting the Wave Window Figure 9 21 Grid amp Timeline Tab of Wave Window Preferen
350. hat appears as user input to the simulator e g on the vsim command line in a do file etc should be composed of components with escaped identifier syntax appropriate to its language kind A modelsim ini variable called GenerouslIdentifierParsing can control parsing of identifiers input to the tool If this variable is on the variable is on by default value 1 either VHDL extended identifiers or Verilog escaped identifier syntax may be used for objects of either language kind This provides backward compatibility with older do files which often contain pure VHDL extended identifier syntax even for escaped identifiers in Verilog design regions Note that SDF files are always parsed in generous mode SignalSpy function arguments are also parsed in generous mode Tcl and Escaped Identifiers In Tcl the backslash is one of a number of characters that have a special meaning For example n creates a new line When a Tcl command is used in the command line interface the TCL backslash should be escaped by adding another backslash For example force freeze top ix iy yw 1 10 0 01 50 ns r 100 The Verilog identifier in this example is yw 1 Here backslashes are used to escape the square brackets which have a special meaning in Tcl For a more detailed description of special characters in Tcl and how backslashes should be used with those characters click Help gt Tcl Syntax in the menu bar or simply open
351. he Clear command is disabled However if you click in the Transcript pane and choose Edit the Clear command is enabled The active pane is denoted by a blue title bar For more information see Navigating the Graphic User Interface Main Window Status Bar Figure 2 7 Main Window Status Bar Project rtl Now Ons Delta 0 sim top p Z Fields at the bottom of the Main window provide the following information about the current simulation Table 2 5 Information Displayed in Status Bar Field Description Project name of the current project Now the current simulation time Delta the current simulation iteration number Profile Samples the number of profile samples collected during the current simulation Memory the total memory used during the current simulation environment name of the current context object selected in the active Structure tab of the Workspace line column line and column numbers of the cursor in the active Source window 44 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Navigating in the Main Window Main Window Toolbar Buttons on the Main window toolbar give you quick access to various ModelSim commands and functions Table 2 6 Main Window Toolbar Buttons Button Menu equivalent Command equivalents New File File gt New gt Source create a new source file Open File gt Open open the Open File dialog Save File gt Save save the contents
352. he Memories tab of the Main window Workspace and displays the contents of a selected memory in the Main window MDI frame Figure 2 14 Memory Panes tam tb spram2 mem 0001 0001100101100 00010001100101101 0001 0001100101110 00010001100101111 00010001 100110000 00010001100110001 00010001 100110010 00010001100110011 00010001 100110100 00010001 100110101 00010001 100110110 00010001100110111 00010001 100111000 00010001100111001 0001 0001100111010 00010001100111011 0001 0001109111100 00010001100111101 AAA ec 30 444409 Cii Cort 4 0099434314434 Ei ven tm The memory list is from the top level of the design In other words it is not sensitive to the context selected in the Structure tab gt ram tb spram3 mem 0 65535 65536 x49 ram tb spram4 mem 0 3 4 16 gt Iram tb dprami mem 0 15 16 8 58 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Memory Panes ModelSim identifies certain kinds of arrays in various scopes as memories Memory identification depends on the array element kind as well as the overall array kind i e associative array unpacked array etc Table 2 8 Memories Verilog SystemVerilog SystemC Element Kind enum any integral type i e unsigned char std_logic_vector integer_type unsigned short std_bit_vector or shortint int longint unsigned int integer byte bit 2 state unsigned long logic reg integer unsigned long long ti
353. he WLF reader cache WLF reader caching caches blocks of the WLF file to reduce redundant file I O e Value Range positive integer e Default 0 WLFCollapseMode This variable controls when the WLF file records values e Value Range 0 every change of logged object 1 end of each delta step 2 end of simulator time step e Default 1 WLFCompress This variable enables WLF file compression e Value Range 0 1 ModelSim User s Manual v6 3g 393 May 2008 Simulator Variables Simulator Control Variables e Default 1 on WLFDeleteOnQuit This variable specifies whether a WLF file should be deleted when the simulation ends e Value Range 0 1 e Default 0 do not delete WLFFilename This variable specifies the default WLF file name e Value Range filename e Default vsim wlf WLFOptimize This variable specifies whether the viewing of waveforms is optimized e Value Range 0 1 e Default 1 on WLFSaveAllRegions This variable specifies the regions to save in the WLF file e Value Range 0 only regions containing logged signals 1 all design hierarchy Default 0 WLFSimCacheSize This variable sets the number of megabytes for the WLF reader cache for the current simulation dataset only The default value is zero WLF reader caching caches blocks of the WLF file to reduce redundant file I O This makes it easier to set different sizes for the WLF reader cache used during simulation and those used duri
354. he type of file you create For example Module and Primitive templates are available for Verilog files and Entity and Architecture templates are available for VHDL files Double click an object in the list to open a wizard or to begin creating code Some of the objects bring up wizards while others insert code into your source file The dialog below is part of the wizard for creating a new design Simply follow the directions in the wizards ModelSim User s Manual v6 3g 67 May 2008 Graphical User Interface Source Window Figure 2 24 Create New Design Wizard Create New Design Wizard E loj x The New Design Wizard will step you through the tasks necessary to add a VHDL Design Unit or Verilog Module or SystemC SC M DULE to your code Design Unit First you need to enter the name you want for the design unit and Please enter the name you then the wizard will allow you to enter each of the pins on the want to use for this design block you want to create S S Design Unit Name Next gt Cancel Code inserted into your source contains a variety of highlighted fields The example below shows a module statement inserted from the Verilog template Figure 2 25 Inserting Module Statement from Verilog Language Template Language Templates PN New Design Wizard Create Testbench module module nane ESENGENSHESEPSENNS SESE Module IU Primitive module item Declarations Statements endmodule Instantia
355. hm that will be used to encrypt the key Note The combination of key_keyowner key_keyname and key_method expressions uniquely identify a key e begin designates the beginning of the source code to be encrypted e end designates the end of the source code to be encrypted Note___ Encryption envelopes cannot be nested A pragma protect begin end pair cannot bracket another pragma protect begin end pair Optional pragma protect expressions that may be included are as follows e author designates the IP provider e author_info designates optional author information e encoding specifies an encoding method The default encoding method if none is specified is base 64 If a number of pragma expressions occur in a single protection pragma the expressions are evaluated in sequence from left to right In addition the interpretation of protected envelopes is not dependent on this sequence occurring in a single protection pragma or a sequence of protection pragmas However the most recently value assigned to a protection pragma keyword will be the one used Unsupported Protection Pragma Expressions Optional pragma protect expressions that are not currently supported include e any digest_ expression e decrypt_license ModelSim User s Manual v6 3g 107 May 2008 Protecting Your Source Code Compiling a Design with vlog protect e runtime license e viewpoint Comp
356. ht notice and this permission notice appear in supporting documentation and that the names of Digital or MIT not be used in advertising or publicity pertaining to distribution of the software without specific written prior permission DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS IN NO EVENT SHALL DIGITAL BE LIABLE FOR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE DATA OR PROFITS WHETHER IN AN ACTION OF CONTRACT NEGLIGENCE OR OTHER TORTIOUS ACTION ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 1987 by Digital Equipment Corporation Maynard Massachusetts and the Massachusetts Institute of Technology Cambridge Massachusetts All Rights Reserved Permission to use copy modify and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation and that the names of Digital or MIT not be used in advertising or publicity pertaining to distribution of the software without specific written prior permission DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS IN NO EVENT SHALL DIGITAL BE LIABLE FOR ANY SPECIAL IND
357. hysical directory they just have different pathnames on different systems How Location Mapping Works When a pathname is stored an attempt is made to map the physical pathname to a path relative to a logical pathname This is done by searching the location map file for the first physical pathname that is a prefix to the pathname in question The logical pathname is then substituted for the prefix For example usr vhdl src test vhd is mapped to SRC test vhd If a mapping can be made to a logical pathname then this is the pathname that is saved The path to a source file entry for a design unit in a library is a good example of a typical mapping For mapping from a logical pathname back to the physical pathname ModelSim expects an environment variable to be set for each logical pathname with the same name ModelSim reads the location map file when a tool is invoked If the environment variables corresponding to logical pathnames have not been set in your shell ModelSim sets the variables to the first physical pathname following the logical pathname in the location map For example if you don t set the SRC environment variable ModelSim will automatically set it to home vhdl src Mapping with TCL Variables Two Tcl variables may also be used to specify alternative source file paths SourceDir and SourceMap You would define these variables in a modelsim tcl file See the The modelsim tcl File for details 406 ModelSim User s Manua
358. iable is DefaultRadix e Suppress Warnings o Selecting From Synopsys Packages suppresses warnings generated within the accelerated Synopsys std_arith packages The corresponding modelsim ini variable is StdArithNoWarnings o Selecting From IEEE Numeric Std Packages suppresses warnings generated within the accelerated numeric_std and numeric_bit packages The corresponding modelsim ini variable is NumericStdNoWarnings e Default Run Sets the default run length for the current simulation The corresponding modelsim ini variable is RunLength e Iteration Limit Sets a limit on the number of deltas within the same simulation time unit to prevent infinite looping The corresponding modelsim ini variable is IterationLimit e Default Force Type Selects the default force type for the current simulation The corresponding modelsim ini variable is DefaultForceKind The Assertions tab includes these options 396 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables Figure A 2 Runtime Options Dialog Box Assertions Tab Runtime Options lx Defaults Assertions WLF Files gt Immediate Assertion Break Severity No Message Display For C Fata VHDL Verilog G Faxo Failure Fatal C Enor Ero Eno C Wari Warming v Waring Note Info Note Iv Info OK Cancel Apply No Message Display For VHDL Selects the VHDL assertion severity for which me
359. icit noaccel SFiles Example 14 11 Specifying Compiler Arguments With Macro Enhanced This macro is an enhanced version of the one shown in example 2 The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type Note that the macro assumes your VHDL files have a vhd file extension ModelSim User s Manual v6 3g 359 May 2008 Tcl and Macros DO Files Macros DO Files variable vhdFiles variable vFiles set nbrArgs Sarge set vhdFilesExist O0 set vFilesExist 0 for set x 1 x lt SnbrArgs incr x if string match vhd 11 set vhdFiles concat SvhdFiles 1 set vhdFilesExist 1 else set vFiles concat SvFiles 1 set vFilesExist 1 shift if vhdFilesExist 1 eval vcom 93 explicit noaccel vhdFiles if SvFilesExist 1 eval vlog vFiles Useful Commands for Handling Breakpoints and Errors If you are executing a macro when your simulation hits a breakpoint or causes a run time error ModelSim interrupts the macro and returns control to the command line The commands in Table 14 8may be useful for handling such events Any other legal command may be executed as well Table 14 8 Commands for Handling Breakpoints and Errors in Macros command run continue continue as if the breakpoint had not been executed completes the run that was interrupted onbreak specify a co
360. ign hierarchy from within a VHDL architecture or Verilog or SystemC module e g a testbench A signal_force works the same as the force command with the exception that you cannot issue a repeating force The force will remain on the signal until a signal_release a force or release command or a subsequent signal_force is issued Signal_force can be called concurrently or sequentially in a process This command displays any signals using your radix setting either the default or as you specify unless you specify the radix in the value you set By default this command uses a backslash as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file VHDL Syntax signal_force lt dest_object gt lt value gt lt rel_time gt lt force_type gt lt cancel_period gt lt verbose gt Verilog Syntax signal_force lt dest_object gt lt value gt lt rel_time gt lt force_type gt lt cancel_period gt lt verbose gt SystemC Syntax signal_force lt dest_object gt lt value gt lt rel_time gt lt force_type gt lt cancel_period gt lt verbose gt Returns Nothing Arguments e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal Verilog register net or SystemC signal Use the path separator to which your simulation is set i e or A full hierarchical pa
361. ign to actually execute a replay but many problems can be resolved with the trace only Invoking a Trace To invoke the trace call vsim with the trace foreign argument Syntax vsim trace foreign action tag lt name gt Arguments action ModelSim User s Manual v6 3g 445 May 2008 Verilog PLI VPI DPI Debugging PLI VPI DPI Application Code Can be either the value 1 2 or 3 Specifies one of the following actions Table C 6 Values for lt action gt Argument Operation create log only writes a local file called mti_trace_ lt tag gt create replay only writes local files called mti data tag c mti init tag c mti replay tag c and mti top tag c create both log and writes all above files replay tag lt name gt Used to give distinct file names for multiple traces Optional Examples vsim trace foreign 1 mydesign Creates a logfile vsim trace foreign 3 mydesign Creates both a logfile and a set of replay files vsim trace foreign 1 tag 2 mydesign Creates a logfile with a tag of 2 The tracing operations will provide tracing during all user foreign code calls including PLI V PI user tasks and functions calltf checktf sizetf and misctf routines and Verilog VCL callbacks Debugging PLI VPI DPI Application Code In order to debug your PLI VPI DPI application code in a debugger you must first 1 Compile the application code with debuggin
362. igure 4 3 113 ModelSim User s Manual v6 3g May 2008 Projects Getting Started with Projects Figure 4 3 Add items to the Project Dialog X m Click on the icon to add items of that type _ Create New File Add Existing File Create Simulation Create New Folder Close The name of the current project is shown at the bottom left corner of the Main window Step 2 Adding Items to the Project The Add Items to the Project dialog includes these options e Create New File Create a new VHDL Verilog Tcl or text file using the Source editor See below for details e Add Existing File Add an existing file See below for details e Create Simulation Create a Simulation Configuration that specifies source files and simulator options See Creating a Simulation Configuration for details e Create New Folder Create an organization folder See Organizing Projects with Folders for details Create New File The File gt New gt Source menu selections allow you to create a new VHDL Verilog Tcl or text file using the Source editor You can also create a new project file by selecting Project Add to Project New File the Project tab in the Workspace must be active or right clicking in the Project tab and selecting Add to Project New File This will open the Create Project File dialog Figure 4 4 114 ModelSim User s Manual v6 3g May 2008 Projects Getting Started with Proje
363. iling a Design with vlog protect To encrypt IP code with ModelSim the protect argument must be used with the vlog command For example if the source code file containing encryption envelopes is named encrypt v it would be compiled as follows vlog protect encrypt v When vlog protect is used encryption envelope pragma expressions are transformed into decryption envelope pragma expressions and decryption content pragma expressions Source text within encryption envelopes is encrypted using the specified key and is recorded in the decryption envelope within a data block And the file is renamed with a vp extension it becomes encrypt vp Example 3 3shows the resulting source code when the IP code used in Example 3 1 is compiled with vlog protect Example 3 3 Results After Compiling with vlog protect module test_dff4 output 3 0 q output err parameter WIDTH 4 parameter DEBUG 0 reg 3 0 d reg clk dff4 d4 q clk d assign err 0 initial begin Sdump_all_vpi Sdump_tree_vpi test_dff4 Sdump_tree_vpi test_dff4 d4 Sdump_tree_vpi test_dff4 Sdump_tree_vpi test_dff4 d4 Sdump_tree_vpi test_dff4 d test_dff4 clk test dff4 q Sdump_tree_vpi test_dff4 d4 d0 test_dff4 d4 d3 Sdump_tree_vpi test_dff4 d4 q test dff4 d4 clk end endmodule module dff4 output 3 0 q input clk input 3 0 d pragma protect data method aes128 cbc pragma protect
364. im prefix A dataset from a previous simulation is shown in the bottom pane and is indicated by the gold prefix Figure 8 1 Displaying Two Datasets in the Wave Window F wave default File Edit View Add Format Tools Window e H g Sy S22 AE Curent simulation sim test_sm dat 2222222222222222222 n sim sim test sm addr 0000110011 000000 X000 O00 JO L sim test sm loop WKXKXMKKKXNKKKKKXKNN sim test_sm i x sim test_sm rd_ SH gold test_sm clk gold test_sm out_ Previous simulation gold test_sm dat 2222222222222222222 gold gold test_sm addr 0000110011 po00000 gold test_sm loop KXKXKXXXNXXNXKKXNXX gold test_sm i x gold test_sm rd_ St Cursor 1 50400 ps to 565800 ps Now 750 ns Delta The simulator resolution see Simulator Resolution Limit Verilog or Simulator Resolution Limit VHDL must be the same for all datasets you are comparing including the current simulation If you have a WLF file that is in a different resolution you can use the wlfman command to change it Saving a Simulation to a WLF File If you add objects to the Dataflow List or Wave windows or log objects with the log command the results of each simulation run are automatically saved to a WLF file called vsim wlf in the current directory If you then run a new simulation in the same directory the vsim wlf file is overwritten with the new results If you want to save the WLF file
365. im User s Manual v6 3g May 2008 Simulator Variables Environment Variables argument of 0 zero the tool will not release the licenses after being suspended You can change the default length of time number of seconds by setting this environment variable to an integer greater than O zero MTI USELIB DIR The MTI USELIB DIR environment variable specifies the directory into which object libraries are compiled when using the compile uselibs argument to the vlog command MTI VOPT FLOW The environment variable MTI VOPT FLOW determines whether vopt is used as part of the vsim command This variable is overriden by vsim switches vopt and novopt but it overrides the VoptFlow setting in modelsim ini Setting MTI VOPT FLOW to 0 means do not use vopt novopt Setting it to any other value means use vopt vopt NOMMAP When set to 1 the NOMMAP environment variable disables memory mapping in the toolset You should only use this variable when running on Linux 7 1 because it will decrease the speed with which the tool reads files PLIOBJS The toolset uses the PLIOBJS environment variable to search for PLI object files for loading The argument consists of a space separated list of file or path names STDOUT The argument to the STDOUT environment variable specifies a filename to which the simulator saves the VSOUT temp file information Typically this information is deleted when the simulator exits The location for this file is s
366. ime values Show frequency in cursor delta OK Cancel The Grid Configuration selections allow you to set grid offset minimum grid spacing and grid period or you can reset the grid configuration to default values The Timeline Configuration selections give you a user definable time scale You can display simulation time on the timeline or a clock cycle count The time value is scaled appropriately for the selected unit By default the timeline will display time delta between any two adjacent cursors By clicking the Show frequency in cursor delta box you can display the cursor delta as a frequency instead Cursors may be added when the Wave window is active by clicking the Insert Cursor icon or by selecting Add gt Wave gt Cursor from the menu bar Each added cursor is given a default cursor name Cursor 2 Cursor 3 etc which can be changed by simply right clicking the cursor name then typing in a new name or by clicking the Edit this cursor icon The Edit this cursor icon will open the Cursor Properties dialog Figure 2 44 where you assign a cursor name and time You can also lock the cursor to the specified time 90 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Wave Window Figure 2 44 Cursor Properties Dialog Cursor Properties loj xl Cursor Name Cursor 1 Cursor Time lo ns Lock cursor to specified time OK Cancel Messages Bar The
367. imulation Converting an Integer Into a bit_vector 168 library ieee use ieee numeric_bit ALL entity test is end test architecture only of test is signal sl bit_vector 7 downto 0 Signal int integer 45 begin p process begin wait for 10 ns sl lt bit_vector to_signed int 8 end process p end only ModelSim User s Manual v6 3g May 2008 Chapter 7 Verilog and SystemVerilog Simulation This chapter describes how to compile and simulate Verilog and SystemVerilog designs with ModelSim ModelSim implements the Verilog language as defined by the IEEE Standards 1364 1995 and 1364 2005 We recommend that you obtain these specifications for reference The following functionality is partially implemented in ModelSim e Verilog Procedural Interface VPI see install dir modeltech docs technotes Verilog VPI note for details e JEEE Std P1800 2005 SystemVerilog see install dir modeltech docs technotes sysvlog note for implementation details Terminology This chapter uses the term Verilog to represent both Verilog and SystemVerilog unless otherwise noted Basic Verilog Flow Simulating Verilog designs with ModelSim includes four general steps 1 Compile your Verilog code into one or more libraries using the vlog command See Compiling Verilog Files for details 2 Load your design with the vsim command See Simulating Verilog Designs for details 3 Run and debug your design
368. in the Memory List pane is equal to the integer size and the depth is the size of the array itself ModelSim User s Manual v6 3g 59 May 2008 Graphical User Interface Memory Panes Memories with three or more dimensions display with a plus sign next to their names in the Memory List Click the to show the array indices under that level When you finally expand down to the 2D level you can double click on the index and the data for the selected 2D slice of the memory will appear in a memory contents pane in the MDI frame Viewing Packed Arrays By default packed dimensions are treated as single vectors in the memory contents pane To expand packed dimensions of packed arrays select View gt Memory Contents gt Expand Packed Memories To change the permanent default edit the PrefMemory ExpandPackedMem variable This variable affects only packed arrays If the variable is set to 1 the packed arrays are treated as unpacked arrays and are expanded along the packed dimensions such that they appear as a linearized bit vector See Simulator GUI Preferences for details on setting preference variables Viewing Memory Contents When you double click an instance on the Memory tab ModelSim automatically displays a memory contents pane in the MDI frame see Multiple Document Interface MDI Frame where the name used on the tab is taken from the name of the instance as seen in the Memory list You can also enter the command
369. in the UserTimeScale Return values are always in the current Time Scale Units All time values are converted to a 64 bit integer value in the current Time Scale This means that values smaller than the current Time Scale will be truncated to 0 ModelSim User s Manual v6 3g 353 May 2008 Tcl and Macros DO Files Simulator Tcl Time Commands Conversions Table 14 5 Tcl Time Conversion Commands Command Description intl oTime intHi32 lt intLo32 gt converts two 32 bit pieces high and low order into a 64 bit quantity Time in ModelSim is a 64 bit integer RealToTime real converts a real number to a 64 bit integer in the current Time Scale scaleTime time lt scaleFactor gt returns the value of time multiplied by the scaleFactor integer Relations Table 14 6 Tcl Time Relation Commands Command Description eqTime time time evaluates for equal neqTime time time evaluates for not equal gtTime time time evaluates for greater than gteTime time time evaluates for greater than or equal ItTime time time evaluates for less than IteTime time time evaluates for less than or equal All relation operations return 1 or 0 for true or false respectively and are suitable return values for TCL conditional expressions For example if eqTime Now 1750ns 354 ModelSim User s Manual v6 3g May 2008 Tcl and Macros D
370. inal objects do not call acc_close while these callbacks are in effect Third Party PLI Applications Many third party PLI applications come with instructions on using them with ModelSim Verilog Even without the instructions it is still likely that you can get it to work with ModelSim Verilog as long as the application uses standard PLI routines The following guidelines are for preparing a Verilog XL PLI application to work with ModelSim Verilog Generally a Verilog XL PLI application comes with a collection of object files and a veriuser c file The veriuser c file contains the registration information as described above in Registering PLI Applications To prepare the application for ModelSim Verilog you must compile the veriuser c file and link it to the object files to create a dynamically loadable object see Compiling and Linking C Applications for PLI VPI DPI For example if you have a veriuser c file and a library archive libapp a file that contains the application s object files then the following commands should be used to create a dynamically loadable object for the Solaris operating system cc c l lt install_dir gt modeltech include veriuser c usr ccs bin Id G Bsymbolic o app sl veriuser o libapp a The PLI application is now ready to be run with ModelSim Verilog All that s left is to specify the resulting object file to the simulator for loading using the Veriuser entry in the modesim ini file the pli simulator
371. including the Transcript tab is always open in the Main window and cannot be closed Viewing Data in the Transcript Tab The Transcript tab contains the command line interface identified by the ModelSim prompt and the simulation interface identified by the VSIM prompt Transcript Tab Tasks This section introduces you to several tasks you can perform related to the Transcript tab Saving the Transcript File Variable settings determine the filename used for saving the transcript If either PrefMain file in the modelsim file or TranscriptFile in the modelsim ini file is set then the transcript output is logged to the specified file By default the TranscriptFile variable in modelsim ini is set to transcript If either variable is set the transcript contents are always saved and no explicit saving 1s necessary If you would like to save an additional copy of the transcript with a different filename click in the Transcript pane and then select File gt Save As or File gt Save The initial save must be made with the Save As selection which stores the filename in the Tcl variable PrefMain saveFile Subsequent saves can be made with the Save selection Since no automatic saves are performed for this file itis written only when you invoke a Save command The file is written to the specified directory and records the contents of the transcript at the time of the save Using the Saved Transcript as a Macro DO file Saved transcript
372. indow ModelSim User s Manual v6 3g 227 May 2008 Recording Simulation Results With Datasets Collapsing Time and Delta Steps Figure 8 5 Dataset Snapshot Dialog Dataset Snapshot x Dataset Snapshot State Enabled C Disabled Snapshot Type Simulation Time 1000000 ns vw C WLF File Size 100 Megabytes Snapshot Contents C Snapshot contains only data since previous snapshot Snapshot contains all previous data Snapshot Directory and File Directory File Prefix c dataflow Browse vsim snapshot verwrite Increment Always replace snapshot file C Use incrementing suffix on snapshot files Selected Snapshot Filename C dataflow vsim snapshot wlf Collapsing Time and Delta Steps By default ModelSim collapses delta steps This means each logged signal that has events during a simulation delta has its final value recorded to the WLF file when the delta has expired The event order in the WLF file matches the order of the first events of each signal 228 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Virtual Objects You can configure how ModelSim collapses time and delta steps using arguments to the vsim command or by setting the WLFCollapseMode variable in the modelsim ini file The table below summarizes the arguments and how they affect event recording Table 8 3 vsim Arguments for Collapsing Time and Delta
373. ine This backslash sequence is unique in that it is replaced in a separate pre pass before the command is actually parsed This means that it will be replaced even when it occurs between braces and the resulting space will be treated as a word separator if it isn t in braces or quotes Backslash The digits ooo one two or three of them give the octal value of the character 10 348 The hexadecimal digits hh give the hexadecimal value of the character Any number of digits may be present Backslash substitution is not performed on words enclosed in braces except for backslash newline as described above If a pound sign appears at a point where Tcl is expecting the first character of the first word of a command then the pound sign and the characters that follow it up through the next newline are treated as a comment and ignored The character denotes a comment only when it appears at the beginning of a command Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command For example if variable substitution occurs then no further substitutions are performed on the value of the variable the value is inserted into the word verbatim If command substitution occurs then the nested command is processed entirely by the recursive call to the Tcl interpreter no substitutions are performed before making the recursive call and no additional substitutions are
374. ing SDF INTERCONNECT and PORT to Verilog 320 Table 12 4 Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog 321 Table 12 5 Matching SDF DEVICE to Verilog eeeeee ee 321 Table 12 6 Matching SDF SETUP to Verilog 0 0 0 cee eee ee eee 32 Table 12 7 Matching SDF HOLD to Verilog elles 321 Table 12 8 Matching SDF SETUPHOLD to Verilog 0 0 00 0000005 322 Table 12 9 Matching SDF RECOVERY to Verilog sseeeeeeeeeee 322 Table 12 10 Matching SDF REMOVAL to Verilog 0 0 0 0 0c ee eee eee 322 Table 12 11 Matching SDF RECREM to Verilog 0 0 00 cece eee eee 322 Table 12 12 Matching SDF SKEW to Verilog 0 0 eee eee ee eee 322 Table 12 13 Matching SDF WIDTH to Verilog 0 0 0 eee eee eee 323 Table 12 14 Matching SDF PERIOD to Verilog 0 0 eee e 323 Table 12 15 Matching SDF NOCHANGE to Verilog 0 0 0 0 e eee eee ee 323 Table 12 16 Matching Verilog Timing Checks to SDF SETUP 323 Table 12 17 SDF Data May Be More Accurate Than Model 04 324 Table 12 18 Matching Explicit Verilog Edge Transitions to Verilog 324 Table 12 19 SDF Timing Check Conditions 904242925044 EE RRRDe PERRA dade 324 Table 12 20 SDF Path Delay Conditions 0 0 eee eee ee eee 325 Table 12 21 Disabling Timing Checks 2342454 i0360004284e4o4ee8eeeoueque
375. ing the List You can sort the list by any of the five columns Click on a column heading to sort by that column click the heading again to invert the sort order An arrow in the column heading indicates which field the list is sorted by and whether the sort order is descending down arrow or ascending up arrow Creating a Simulation Configuration A Simulation Configuration associates a design unit s and its simulation options For example assume you routinely load a particular design and you also have to specify the simulator resolution limit generics and SDF timing files Ordinarily you would have to specify those options each time you load the design With a Simulation Configuration you would specify the design and those options and then save the configuration with a name e g top_config The name is then listed in the Project tab and you can double click it to load the design along with its options To create a Simulation Configuration follow these steps 1 Select Project gt Add to Project gt Simulation Configuration from the main menu or right click the Project tab and select Add to Project gt Simulation Configuration from the popup context menu in the Project tab ModelSim User s Manual v6 3g 121 May 2008 Projects Creating a Simulation Configuration Figure 4 13 Add Simulation Configuration Dialog Add Simulation Configuration E x Simulation Configuration Name Place in Folder Ex 1 Top Level w Add Folder
376. ing unnecessary reads and writes but there are also optimizations that can produce additional false hazards Limitations of Hazard Detection e Reads and writes involving bit and part selects of vectors are not considered for hazard detection The overhead of tracking the overlap between the bit and part selects is too high e A WRITE WRITE hazard is flagged even if the same value is written by both processes e A WRITE READ or READ WRITE hazard is flagged even if the write does not modify the variable s value ModelSim User s Manual v6 3g 189 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs e Glitches on nets caused by non guaranteed event ordering are not detected e A non blocking assignment is not treated as a WRITE for hazard detection purposes This is because non blocking assignments are not normally involved in hazards In fact they should be used to avoid hazards e Hazards caused by simultaneous forces are not detected Debugging Signal Segmentation Violations Attempting to access a System Verilog object that has not been constructed with the new operator will result in a fatal error called a signal segmentation violation SIGSEGV For example the following code will produce a SIGSEGV fatal error class C int x endclass C obj initial obj x 5 The code attempts to initialize a property of obj but obj has not been constructed The code is missing the following C obj new
377. ion of compiled design units 1 e it does not need to be mapped In other words the work library is the default working library Archives By default design libraries are stored in a directory structure with a sub directory for each design unit in the library Alternatively you can configure a design library to use archives In this case each design unit is stored in its own archive file To create an archive use the archive argument to the vlib command Generally you would do this only in the rare case that you hit the reference count limit on I nodes due to the entries in the lower level directories the maximum number of sub directories on UNIX and Linux is 65533 An example of an error message that is produced when this limit is hit is mkdir cannot create directory 65534 Too many links Archives may also have limited value to customers seeking disk space savings Note d GMAKE won t work with these archives on the IBM platform Working with Design Libraries The implementation of a design library is not defined within standard VHDL or Verilog Within ModelSim design libraries are implemented as directories and can have any legal name allowed by the operating system with one exception extended identifiers are not supported for library names 130 ModelSim User s Manual v6 3g May 2008 Design Libraries Working with Design Libraries Creating a Library When you create a project refer to Getting Start
378. ion of data before it is needed for use in simulation It also serves as a way to streamline simulation invocation Instead of compiling all design data each and every time you simulate ModelSim uses binary pre compiled data from these libraries So if you make a changes to a single Verilog module only that module is recompiled rather than all modules in the design Working and Resource Libraries Design libraries can be used in two ways 1 as a local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you update your design and recompile A resource library is typically unchanging and serves as a parts source for your design Examples of resource libraries might be shared information within your group vendor libraries packages or previously compiled elements of your own working design You can create your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor For more information on resource libraries and working libraries see Working Library Versus Resource Libraries Managing Library Contents Working with Design Libraries and Specifying Resource Libraries 26 ModelSim User s Manual v6 3g May 2008 Introduction Basic Steps for Simulation Creating the Logical Library vlib Before you can compile your source files you must create a library in which to store the compilation re
379. ions for Lucent Technologies 2001 Vincent Darley 2002 by Kevin B Kenny All rights reserved 1992 1995 Karl Lehenbauer and Mark Diekhans 1998 Lucent Technologies Inc 2000 by Ajuba Solutions 1989 1993 The Regents of the University of California 1994 1997 Sun Microsystems Inc 1998 1999 Scriptics Corporation This software is copyrighted by the Regents of the University of California Sun Microsystems Inc Scriptics Corporation ActiveState Corporation and other parties The following terms apply to all files associated with the software unless explicitly disclaimed in individual files The authors hereby grant permission to use copy modify distribute and license this software and its documentation for any purpose provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions No written agreement license or royalty fee is required for any of the authorized uses Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here provided that the new terms are clearly indicated on the first page of each file where they apply IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE ITS DOCUMENTATION OR ANY DERIVATIVES THEREOF EVEN IF THE AUTHORS HAVE BEEN ADVISED OF
380. is a group of icons called the Cursor and Timeline Toolbox Toolbox for Cursors and Timeline The Cursor and Timeline Toolbox on the left side of the cursor pane gives you quick access to cursor and timeline features 88 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Wave Window Figure 2 42 Toolbox for Cursors and Timeline The action for each toolbox icon is shown in Table 2 10 Table 2 10 Icons and Actions Toggle short names lt gt full names Edit grid and timeline properties Insert cursor Toggle lock on cursor to prevent it from moving Edit this cursor Remove this cursor The Toggle short names lt gt full names icon allows you to switch from displaying full pathnames the default in the Pathnames Pane to displaying short pathnames The Edit grid and timeline properties icon opens the Wave Window Properties dialog to the Grid amp Timeline tab Figure 2 43 ModelSim User s Manual v6 3g 89 May 2008 Graphical User Interface Wave Window Figure 2 43 Editing Grid and Timeline Properties Wave Window Preferences x Display Grid amp Timeline Grid Configuration Grid Offset Minimum Grid Spacing 0 ns 40 pixels Grid Period 20 ns Reset to Default M Timeline Configuration Display simulation time in timeline area Display grid period count cycle count Time units ns v Use commas in t
381. is an example of how to properly use non blocking assignments w genl always master clkl master gen2 always clk1 Clk2 clk1 fl always posedge clk1 begin ql lt dl end 23 always posedge clk2 begin q2 lt ql end If written this way a value on d always takes two clock cycles to get from d to q2 If you change c k master and clk2 clk1 to non blocking assignments or q2 lt q1 and q1 lt dl to blocking assignments then d7 may get to q2 is less than two clock cycles Debugging Event Order Issues Since many models have been developed on Verilog XL ModelSim tries to duplicate Verilog XL event ordering to ease the porting of those models to ModelSim However ModelSim does not match Verilog XL event ordering in all cases and if a model ported to ModelSim does not behave as expected then you should suspect that there are event order dependencies ModelSim helps you track down event order dependencies with the following compiler arguments compat hazards and keep_delta See the vlog command for descriptions of compat and hazards 188 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Hazard Detection The hazards argument to vsim detects event order hazards involving simultaneous reading and writing of the same register in concurrently executing processes vsim detects the following kinds of hazards e WRITE WRITE
382. is list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this softwaremust display the following acknowledgement This product includes software developed by the University of California Berkeley and its contributors 4 Neither the name of the University nor the names of its contributorsmay be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1987 Regents of the University of California Copyright c 1987 1993 The Regents of the University of California All rights reserved Redistribution and use in source and binary forms are
383. is that the HDL design is not using the full subset of objects that both the simulator and VPI ought to be able to handle 418 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI g Compiler Support for use with PLI VPI DPI g Compiler Support for use with PLI VPI DPI You must acquire the g compiler for your given platform as defined in the sections Compiling and Linking C Applications for PLI VPI DPI and Compiling and Linking C Applications for PLI VPI DPI Registering PLI Applications Each PLI application must register its system tasks and functions with the simulator providing the name of each system task and function and the associated callback routines Since many PLI applications already interface to Verilog XL ModelSim Verilog PLI applications make use of the same mechanism to register information about each system task and function in an array of S tfcell structures This structure is declared in the veriuser h include file as follows typedef int p tffn typedef struct t tfcell short type USERTASK USERFUNCTION or USERREALFUNCTION short data passed as data argument of callback function p tffn checktf argument checking callback function p tffn sizetf function return size callback function p tffn calltf task or function call callback function p tffn misctf miscellaneous reason callback function char tfname name of system
384. it libraries 137 64 bit time now variable 404 Tcl time commands 353 64 bit vsim using with 32 bit FLI apps 445 A ACC routines 441 accelerated packages 136 access hierarchical objects 293 Active Processes pane 47 see also windows Active Processes pane Algorithm negative timing constraint 195 AmsStandard ini file variable 374 architecture simulator state variable 403 archives described 130 argc simulator state variable 403 arguments passing to a DO file 358 arithmetic package warnings disabling 401 AssertFile ini file variable 380 AssertionDebug ini variable 380 AssertionFormat deprecated see MessageFormat 34 AssertionFormatBreak deprecated see MessageFormatBreak 34 AssertionFormatFail deprecated 474 JKLMNOPQRSTUVWXYZ see MessageFormatFail 34 AssertionFormatFatal deprecated see MessageFormatFatal 34 AssertionFormatNote deprecated see MessageFormatNote 34 AssertionFormatWarning deprecated see MessageFormatWarning 34 assertions file and line number 386 message display 397 messages turning off 401 setting format of messages 386 warnings locating 386 B bad magic number error message 221 base radix List window 259 Wave window 253 batch mode simulations 30 BindAtCompile ini file variable 375 binding VHDL default 145 blocking assignments 187 bookmarks Source window 72 Wave window 245 break stop simulation run 46 BreakOnAs
385. ix describes ModelSim error and warning messages Appendix C Verilog PLI VPI DPI This appendix describes the ModelSim implementation of the Verilog PLI and VPI Appendix D Command and Keyboard Shortcuts This appendix describes ModelSim keyboard and mouse shortcuts Appendix F System Initialization This appendix describes what happens during ModelSim startup Text Conventions Text conventions used in this manual include Table 1 4 Text Conventions italic text provides emphasis and sets off filenames pathnames and design unit names bold text indicates commands command options menu choices package and library logical names as well as variables dialog box selections and language keywords monospace type monospace type is used for program and command examples The right angle 2 is used to connect menu choices when traversing menus as in File Quit UPPER CASE denotes file types used by ModelSim e g DO WLF INI MPF PDF etc Installation Directory Pathnames When referring to installation paths this manual uses modeltech as a generic representation of the installation directory for all versions of ModelSim The actual installation directory on your system may contain version information Deprecated Features Commands and Variables This section provides tables of features commands command arguments and modelsim ini variables that have been superseded by new version
386. ize_1164 This variable disables optimization for the IEEE std_logic_1164 package e Value Range 0 1 e Default on 1 PedanticErrors This variable overrides NoCaseStaticError and NoOthersStaticError e Value Range 0 1 e Default off 0 Quiet This variable disables the loading messages e Value Range 0 1 e Default off 0 RequireConfigForAllDefaultBinding This variable instructs the compiler not to generate a default binding during compilation ModelSim User s Manual v6 3g 377 May 2008 Simulator Variables Simulator Control Variables e Value Range 0 1 e Default off 0 Show_Lint This variable enables lint style checking e Value Range 0 1 e Default off 0 Show_source This variable shows source line containing error e Value Range 0 1 e Default off 0 Show_VitalChecksOpt This variable enables VITAL optimization warnings e Value Range 0 1 e Default on 1 Show_VitalChecksWarnings This variable enables VITAL compliance check warnings e Value Range 0 1 e Default on 1 Show_WarnCantDoCoverage This variable enables warnings when the simulator encounters constructs which code coverage cannot handle e Value Range 0 1 e Default on 1 Show_Warning1 This variable enables unbound component warnings e Value Range 0 1 378 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables e Default on 1 Show_Warning2 This variable enables process without
387. jb djc dja_reg Dataflow Window Graphic Interface Reference This section answers the following common questions about using the Dataflow window s graphic user interface 286 What Can I View in the Dataflow Window How is the Dataflow Window Linked to Other Windows How Can I Print and Save the Display How Do I Configure Window Options How Do I Zoom and Pan the Display ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference What Can I View in the Dataflow Window The Dataflow window displays processes e signals nets and registers The window has built in mappings for all Verilog primitive gates 1 e AND OR etc For components other than Verilog primitives you can define a mapping between processes and built in symbols See Symbol Mapping for details How is the Dataflow Window Linked to Other Windows The Dataflow window is dynamically linked to other debugging windows and panes as described in Table 10 2 Table 10 2 Dataflow Window Links to Other Windows and Panes Window Main Window select a signal or process in the Dataflow window and the structure tab updates if that object is in a different design unit Process Window select a process in either window and that process is highlighted in the other Objects Pane select a design object in either window and that object is highlighted in the other Wave Window trace through
388. jects with a Command Use the add list or add wave commands to add objects from the command line For example VSIM gt add wave proc a Adds signal proc a to the Wave window VSIM gt add list Adds all the objects in the current region to the List window VSIM gt add wave r Adds all objects in the design to the Wave window Adding Objects with a Window Format File Select File gt Open gt Format and specify a previously saved format file See Saving the Window Format for details on how to create a format file 238 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Measuring Time with Cursors in the Wave Window Measuring Time with Cursors in the Wave Window ModelSim uses cursors to measure time in the Wave window Cursors extend a vertical line over the waveform display and identify a specific simulation time Multiple cursors can be used to measure time intervals as shown in the graphic below When the Wave window is first drawn it contains two cursors the Now cursor and Cursor 1 Figure 9 9 Figure 9 9 Original Names of Wave Window Cursors Now 390335000 ps The Now cursor is always locked to the current simulation time and it is not manifested as a graphical object vertical cursor bar in the Wave window Cursor 1 is located at time zero Clicking anywhere in the waveform display moves the Cursor 1 vertical cursor bar to the mouse location and makes this cursor the se
389. k will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this section 3 shall survive the termination or expiration of this Agreement RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and on site contractors excluding Mentor Graphics competitors whose job performance requires access and who are under obligations of confidentiality You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transf
390. k Brown Fox Jumped Over The Lazy Doq Select an item from the Category list and then edit the available properties on the right Click OK or Apply to accept the changes The changes will be active for the next Source window you open The changes are saved automatically when you quit ModelSim Transcript Window The Transcript window contains the following tabs e Transcript Tab maintains a running history of commands that are invoked and messages that occur as you use the tool e Message Viewer Tab allows you to easily access organize and analyze any messages written to the transcript during the simulation run The Transcript window is always open and part of the Main window ModelSim User s Manual v6 3g 73 May 2008 Graphical User Interface Transcript Window Transcript Tab The Transcript portion of the Main window maintains a running history of commands that are invoked and messages that occur as you work with ModelSim When a simulation is running the Transcript displays a VSIM prompt allowing you to enter command line commands from within the graphic interface You can scroll backward and forward through the current work history by using the vertical scrollbar You can also use arrow keys to recall previous commands or copy and paste using the mouse within the window see Main and Source Window Mouse and Keyboard Shortcuts for details Displaying the Transcript Tab The Transcript window
391. keywords to the Verilog language see Table B 1 in Appendix B of the P1800 SystemVerilog standard If your design uses one of these keywords as a regular identifier for a variable module task function etc your design will not compile in ModelSim Incremental Compilation ModelSim Verilog supports incremental compilation of designs Unlike other Verilog simulators there is no requirement that you compile the entire design in one invocation of the compiler You are not required to compile your design in any particular order unless you are using SystemVerilog packages see note below because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator Note __ Compilation order may matter when using SystemVerilog packages As stated in the IEEE std p1800 2005 LRM section entitled Referencing data in packages which states Packages must exist in order for the items they define to be recognized by the scopes in which they are imported Incremental compilation is made possible by deferring these bindings and as a result some errors cannot be detected during compilation Commonly these errors include modules that were referenced but not compiled incorrect port connections and incorrect hierarchical references Example 7 2 Incremental Compilation Example Contents of testbench sv ModelSim User s Manual v6 3g 171 May 2008 Verilog and SystemVerilog Sim
392. kpoint is written When the WLF file is limited with the wlfslim and wlftlim switches only whole records are truncated So if for example you are were logging only a couple of signals and the amount of data is so small there is only one record in the WLF file the record cannot be truncated and the data for the entire run is saved in the WLF file Opening Datasets To open a dataset do one of the following e Select File gt Open to open the Open File dialog and set the Files of type field to Log Files wif Then select the w f file you want and click the Open button e Select File gt Datasets to open the Dataset Browser then click the Open button to open the Open Dataset dialog Figure 8 2 Figure 8 2 Open Dataset Dialog Box Dataset Browser I x Dataset Context Mode Pathname x Dataset Pathname r wi Em m Name for Dataset OK Cancel Make Active Rename e Use the dataset open command ModelSim User s Manual v6 3g 223 May 2008 Recording Simulation Results With Datasets Viewing Dataset Structure The Open Dataset dialog includes the following options Dataset Pathname Identifies the path and filename of the WLF file you want to Logical Name for Dataset This is the name by which the dataset will be referred By default this is the name of the WLF file Viewing Dataset Structure Each dataset you open creates a structure tab in th
393. kpoints 0 0 0 0 ce eect 71 Figure 2 29 Preferences Dialog for Customizing Source Window 5 73 Figure 2 30 Message Viewer Tabo2 istas rr a RRERERRR I LR RATS RR ARE T11 Figure 2 31 Message Viewer Filter Dialog Box lees 80 Figure 2 32 Watch Pane 2 susce rb E RR X RES x Rack a Ra sane RE PETER e 8l Figure 2 33 Scrollable Hierarchical Display 0 cece eee eee 82 Figure 2 34 Expanded Array 144 uence koh 26 oe REAG uad Hak Pad ERA Rue oe aieee 83 Figure 2 35 Grouping Objects in the Watch Pane 0 0 0 0 eee eee eee 84 Figure 2 36 Wave Window Undock Button 0 0 eee eee eee 85 Figure 2 37 Wave Window Dock Button 86 Figure 2 35 Patbnames Pale o scsz s saw eas PEE RpIEES RE e aed Goes cu Exe vt 87 Figure 2 39 Values Pale ers seduce e Eb gun scl E E E ee REX sed aaa RI ab RE 87 16 ModelSim User s Manual v6 3g May 2008 List of Figures Figure 2 40 Waveforms Pane 42 2exeRbee re RI RESP RR RE REPRE E 88 Fig re 2 41 Cursor Palen PME 88 Figure 2 42 Toolbox for Cursors and Timeline 0 0 0 0 cece eee eee 89 Figure 2 43 Editing Grid and Timeline Properties 0 0 0 0 cece eee eee 90 Figure 2 44 Cursor Properties Dialog 91 Figure 2 45 Wave Window Message Bar 91 Figure 3 1 venctypt Usage PlOW ee ono 42 cease E REREGO ux eX RR RARE oon ney 98 Figure 3 2 Delivering IP Code with Vendor Defined Macros 04 5 100 Figure 3
394. l v6 3g May 2008 Appendix B Error and Warning Messages Message System The ModelSim message system helps you identify and troubleshoot problems while using the application The messages display in a standard format in the Transcript pane Accordingly you can also access them from a saved transcript file see Saving the Transcript File for more details Message Format The format for the messages is SEVERITY LEVEL Tool Group MsgNum Message e SEVERITY LEVEL may be one of the following Table B 1 Severity Level Types severity level meaning This is an informational message There may be a problem that will affect the accuracy of your results The tool cannot complete the operation The tool cannot complete execution e Tool indicates which ModelSim tool was being executed when the message was generated For example tool could be vcom vdel vsim etc e Group indicates the topic to which the problem is related For example group could be FLI PLL VCD etc Example Error vsim PLI 3071 src 19 testfile 77 Sfdumplimit Too few arguments Getting More Information Each message is identified by a unique MsgNum id You can access additional information about a message using the unique id and the verror command For example ModelSim User s Manual v6 3g 407 May 2008 Error and Warning Messages Suppressing Warning Messages verror 30
395. l do else echo Signal value fails do macro 2 do Evaluation Order An important thing to remember when using Tcl is that anything put in braces is not evaluated immediately This is important for if then else statements procedures loops and so forth Tcl Relational Expression Evaluation When you are comparing values the following hints may be useful e Tcl stores all values as strings and will convert certain strings to numeric values when appropriate If you want a literal to be treated as a numeric value don t quote it if exa var 1 345 The following will also work if exa var 1 345 e However if a literal cannot be represented as a number you must quote it or Tcl will give you an error For instance if exa var 2 0012 will give an error if exa var 2 001Z2 J 350 ModelSim User s Manual v6 3g May 2008 Tcl and Macros DO Files Tcl Command Syntax will work okay e Don t quote single characters in single quotes if exa var_3 X will give an error if ema var 3 X will work okay e For the equal operator you must use the C operator For not equal you must use the C operator Variable Substitution When a lt var_name gt is encountered the Tcl parser will look for variables that have been defined either by ModelSim or by you and substitute the value of the variable Note Tcl is case sensitive for varia
396. lSim User s Manual v6 3g 17 May 2008 List of Figures Figure 9 3 Wave Window Object Pathnames Pane 0 0 c eee eee 235 Figure 9 4 Wave Window Object Values Pane 0 0 0 eee eee eee 236 Figure 9 5 Wave Window Waveforms Pane 0 0 0 e cece eee eee 236 Figure 9 6 Wave Window Cursor Pane 22 22 5464 485 Rp ERE RYRE RA e ERES 236 Figure 9 7 Wave Window Messages Bar 0 0 e eee eee eee nee 237 Figure 9 8 Tabular Format of the List Window 0 0 c eee eee eee nee 237 Figure 9 9 Original Names of Wave Window Cursors 00000 e ee eee ee eee 239 Figure 9 10 Cursor and Timeline Toolbox 2 0 0 0 0 cee cece ee eee 239 Figure 9 11 Grid and Timeline Properties 2 2 2 422522 4000 05 4s4eeseeeene abacus 240 Figure 9 12 Cursor Properties Dialog Box 1 2 0 0 0 cece ee eee 241 Figure 9 13 Find Previous and Next Transition Icons 0 0 0 eee ee ee eee 243 Figure 9 14 Time Markers in the List Window else eee ee 244 Figure 9 15 Bookmark Properties Dialog 2 0 0 0 0 cece eee eee eee 246 Figure 9 16 Find Signals by Name or Value 0 0 eee ee eee 247 Figure 9 17 Wave Signal Search Dialog 0 0 cece eee eee 248 Figure 9 18 Expression Builder Dialog Box 0 0 cece eee eee 249 Figure 9 19 Selecting Signals for Expression Builder 0 0 0 0 000000 249 Figure 9 20 Display Tab of the Wave Windo
397. lay on the specified signals For example add list clk notrigger a b c When you run the simulation List window entries for clk a b and c appear only when clk changes If you want to display on rising edges only you have two options 1 Turn off the List window triggering on the clock signal and then define a repeating strobe for the List window 2 Define a gating expression for the List window that requires the clock to be in a specified state See above 268 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Miscellaneous Tasks Miscellaneous Tasks Examining Waveform Values You can use your mouse to display a dialog that shows the value of a waveform at a particular time You can do this two ways e Rest your mouse pointer on a waveform After a short delay a dialog will pop up that displays the value for the time at which your mouse pointer is positioned If you d prefer that this popup not display it can be toggled off in the display properties See Setting Wave Window Display Preferences e Right click a waveform and select Examine A dialog displays the value for the time at which you clicked your mouse This method works in the List window as well Displaying Drivers of the Selected Waveform You can automatically display in the Dataflow window the drivers of a signal selected in the Wave window You can do this three ways e Select a waveform and click the Show Drivers button on the toolbar
398. le is the communication mechanism between the simulator kernel and the Graphical User Interface In normal circumstances the file is deleted when the simulator exits If the tool crashes however the temp file must be deleted manually Specifying the location of the temp file with TMPDIR above will help you locate and remove the file Simulator Control Variables Initialization INI files contain control variables that specify reference library paths and compiler and simulator settings The default initialization file is modelsim ini and is located in your install directory Tip When a design is loaded you can use the where command to display which modelsim ini or ModelSim Project File mpf file is in use To set these variables edit the initialization file directly with any text editor The syntax for variables in the file is lt variable gt lt value gt Comments within the file are preceded with a semicolon The following sections contain information about the variables e Library Path Variables ModelSim User s Manual v6 3g 369 May 2008 Simulator Variables Simulator Control Variables e Verilog Compiler Control Variables e VHDL Compiler Control Variables e Simulation Control Variables Library Path Variables You can find these variables under the heading Library in the modelsim ini file ieee This variable sets the path to the library containing IEEE and Synopsys arithmetic packages e Value Range an
399. le2 vhd Compile gt Compile All icons VHDL Step 3 vsim lt top gt or a Simulate gt Start Simulate icon Load the vsim lt opt_name gt Simulation design into the b Click on top design E simulator module or optimized design unit name c Click OK This action loads the design for simulation Step 4 Simulate gt Run Run or Run the Run continue or simulation Run all icons Common debugging commands bp describe drivers examine force log show Basic Steps for Simulation This section provides further detail related to each step in the process of simulating your design using ModelSim ModelSim User s Manual v6 3g 25 May 2008 Introduction Basic Steps for Simulation Step 1 Collecting Files and Mapping Libraries Files needed to run ModelSim on your design e design files VHDL and or Verilog including stimulus for the design e libraries both working and resource e modelsim ini automatically created by the library mapping command Providing Stimulus to the Design You can provide stimulus to your design in several ways e Language based testbench e Tcl based ModelSim interactive command force e VCD files commands See Creating a VCD File and Using Extended VCD as Stimulus e 3rd party testbench generation tools What is a Library A library is a location where data to be used for simulation is stored Libraries are ModelSim s way of managing the creat
400. lected cursor The selected cursor is drawn as a bold solid line all other cursors are drawn with thin lines Cursor and Timeline Toolbox The Cursor and Timeline Toolbox on the left side of the cursor pane gives you quick access to cursor and timeline features Figure 9 10 Cursor and Timeline Toolbox The action for each toolbox icon is shown in Table 9 1 Table 9 1 Cursor and Timeline Toolbox Icons and Actions Toggle short names lt gt full names Edit grid and timeline properties Insert cursor ModelSim User s Manual v6 3g 239 May 2008 Waveform Analysis Measuring Time with Cursors in the Wave Window Table 9 1 Cursor and Timeline Toolbox Icons and Actions Toggle lock on cursor to prevent it from moving Edit this cursor n Remove this cursor The Toggle short names full names icon allows you to switch from displaying full pathnames the default in the Pathnames Pane to displaying short pathnames The Edit grid and timeline properties icon opens the Wave Window Properties dialog to the Grid amp Timeline tab Figure 9 11 Figure 9 11 Grid and Timeline Properties Wave Window Preferences x Display Grid amp Timeline l l Grid Configuration Grid Offset Minimum Grid Spacing 0 ns 40 pixels Grid Period 20 ns Reset to Default M Timeline Configuration Display simulation time in timeline area Display g
401. limit notifier tstamp cond tcheck cond delayed ctrl delayed data Arguments 194 The control event argument is required It is an asynchronous control signal with an edge identifier to indicate the release from an active state The data event argument is required It is clock or gate signal with an edge identifier to indicate the active edge of the clock or the closing edge of the gate The recovery limit argument is required It is the minimum interval between the release of the asynchronous control signal and the active edge of the clock event Any change to a signal within this interval results in a timing violation The removal limit argument is required It is the minimum interval between the active edge of the clock event and the release of the asynchronous control signal Any change to a signal within this interval results in a timing violation The notifier argument is optional It is a register whose value is updated whenever a timing violation occurs The notifier can be used to define responses to timing violations The tstamp_cond argument is optional It conditions the data event for the removal check and the control event for the recovery check This alternate method of conditioning precludes specifying conditions in the control event and data event arguments The tcheck cond argument is optional It conditions the data event for the recovery check and the c k event for the removal check This alternate
402. lk 0 e NOCHANGE is matched to nochange Table 12 15 Matching SDF NOCHANGE to Verilog SDF Verilog NOCHANGE negedge write addr 5 5 nochange negedge write addr 0 0 To see complete mappings of SDF and Verilog constructs please consult IEEE Standard 1364 2005 Chapter 16 Back Annotation Using the Standard Delay Format SDF Optional Edge Specifications Timing check ports and path delay input ports can have optional edge specifications The annotator uses the following rules to match edges e A match occurs if the SDF port does not have an edge e A match occurs if the specify port does not have an edge e A match occurs if the SDF port edge is identical to the specify port edge e A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge These rules allow SDF annotation to take place even if there is a difference between the number of edge specific constructs in the SDF file and the Verilog specify block For example the Verilog specify block may contain separate setup timing checks for a falling and rising edge on data with respect to clock while the SDF file may contain only a single setup check for both edges Table 12 16 Matching Verilog Timing Checks to SDF SETUP SETUP data posedge clock 5 setup posedge data posedge clk 0 SETUP data posedge clock 5 setup negedge data posedge clk 0 ModelSim User s Manual v6 3g 323 May 2008 St
403. llows the message viewer to link to the specified file If you do not include F the tool automatically logs the value of the filename in which the messagelog is called If you do include R F or L or a combination of any two of these the tool does not automatically log values for the undefined specifier s e 1 Message ID A string argument The Message Viewer displays this value in the ID column This attribute is not used internally therefore you do not need to be concerned about uniqueness or conflict with other message IDs e L Line number An integer argument If you do not include L the tool automatically logs the value of the line number on which the messagelog is called If you do include R F or L or a combination of any two of these the tool does not automatically log values for the undefined specifier s e 25 0 Object Signal Name A hierarchical reference to a variable or net such as sig or top sigx 0 You can specify multiple O for each messagelog which effectively forms a list of attributes of that kind for example messagelog The signals are 0 0 and 0 Sigl top sigx 0 ar 3 sig e 95 R Instance Region name A hierarchical reference to a scope such as top sub1 or subl You can also specify a string argument such as top mychild where the identifier inside the quotes does not need to correlate with an actual scope it can be an artificial sco
404. loading libraries see DPI File Loading For PLI VPI only If app so is not in your current directory you must tell Solaris where to search for the shared object You can do this one of two ways e Add a path before app so in the foreign attribute specification The path may include environment variables e Put the path in a UNIX shell environment variable LD_LIBRARY_PATH_32 lt library path without filename gt 32 bit ModelSim User s Manual v6 3g 431 May 2008 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI or LD_LIBRARY_PATH_64 library path without filename 64 bit Windows Platforms C e Microsoft Visual C 4 1 or Later cl c GX l lt install_dir gt modeltech include app cxx link dll export lt init_function gt app obj lt install_dir gt modeltech win32 mtipli lib out app dll The GX argument enables exception handling For the Verilog PLI the lt init_function gt should be init_usertfs Alternatively if there is no init_usertfs function the lt init_function gt specified on the command line should be veriusertfs For the Verilog VPI the init function should be vlog startup routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL When executing cl commands in a DO file use the NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to std
405. log and SystemVerilog Simulation Compiling Verilog Files config cfg design top instance top u1 use work u1 endconfig In this case work ul indicates to load u from the current library Verilog Generate Statements ModelSim implements the rules adopted for Verilog 2005 because the Verilog 2001 rules for generate statements had numerous inconsistencies and ambiguities Most of the 2005 rules are backwards compatible but there is one key difference related to name visibility Name Visibility in Generate Statements Consider the following code example module m parameter p 1 generate if p integer x 1 else real x 2 0 endgenerate initial display x endmodule This example is legal under 2001 rules However it is illegal under the 2005 rules and causes an error in ModelSim Under the new rules you cannot hierarchically reference a name in an anonymous scope from outside that scope In the example above x does not propagate its visibility upwards and each condition alternative is considered to be an anonymous scope For this example to simulate properly in ModelSim change it to the following module m parameter p 1 if p begin s integer x 1 end else begin s real x 2 0 end initial Sdisplay s x endmodule Because the scope is named in this example begin s normal hierarchical resolution rules apply and the code runs without error ModelSim User s Manual v6 3
406. log constructs 322 SDF WIDTH matching to Verilog constructs 323 sdf_done 212 searching Expression Builder 248 Verilog libraries 174 sensitivity list warning 412 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWX YZ set simulator control with GUI 395 SETUP matching to Verilog 321 SETUPHOLD matching to Verilog 322 severity changing level for errors 408 shared objects loading FLI applications see FLI Reference manual loading PLI VPI DPI C applications 429 loading PLI VPI DPI C applications 431 loading with global symbol visibility 434 Shortcuts text editing 450 shortcuts command history 449 command line caveat 449 List window 453 Main window 450 Source window 450 Wave window 454 show drivers Dataflow window 278 Wave window 269 Show_ WarnMatchCadence ini file variable 374 Show_BadOptionWarning ini file variable 373 Show Lint ini file variable 373 378 Show source ini file variable 374 378 Show VitalChecksOpt ini file variable 378 Show VitalChecksWarning ini file variable 378 Show WarnCantDoCoverage ini file variable 374 Show_WarnCantDoCoverage variable 378 Show_Warning1 ini file variable 378 Show WarninglO ini file variable 379 Show Warning2 ini file variable 379 Show Warning3 ini file variable 379 Show Warning4 ini file variable 379 Show Warning5 ini file variable 379 Show Warning ini file variable 379 Show WarnLocallyStaticError variable 380 485
407. lude GNU gcc third party software GNU gcc is licensed under the GNU GPL v 2 To obtain original source code of GNU gcc or modifications made if any send a request to request sourcecode mentor com Software distributed under the GPL is distributed on an AS IS basis WITHOUT WARRANTY OF ANY KIND either express or implied See the License for the specific language governing rights and limitations under the License See the Legal Directory for the text of the GNU GPL v 2 install directory2 docs legal gnu gpl 2 0 pdf This product may include freeWrap open source software Dennis R LaBelle All Rights Reserved Disclaimer of warranty Licensor provides the software on an as is basis Licensor does not warrant guarantee or make any representations regarding the use or results of the software with respect to it correctness accuracy reliability or performance The entire risk of the use and performance of the software is assumed by licensee ALL WARANTIES INCLUDING WITHOUT LIMITATION ANY WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY ARE HEREBY EXCLUDED This software application may include MinGW GNU diffutils third party software MinGW GNU diffutils is licensed under the GNU GPL v 2 To obtain original source code of MinGW GNU diffutils or modifications made if any send a request to request sourcecode mentor com Software distributed under the GPL is distributed on an AS IS basis WITHOUT WARRANTY OF
408. lues at the end of a compilation unit If a compiler directive is specified as an option to the compiler this setting is used for all compilation units present in the current compilation Verilog XL Compatible Compiler Arguments The compiler arguments listed below are equivalent to Verilog XL arguments and may ease the porting of a design to ModelSim See the vlog command for a description of each argument 176 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files define lt macro_name gt lt macro_text gt delay_mode_distributed delay_mode_path delay_mode_unit delay_mode_zero f filename tincdirt lt directory gt mindelays maxdelays nowarn lt mnemonic gt ttypdelays Arguments Supporting Source Libraries The compiler arguments listed below support source libraries in the same manner as Verilog XL See the vlog command for a description of each argument Note that these source libraries are very different from the libraries that the ModelSim compiler uses to store compilation results You may find it convenient to use these arguments if you are porting a design to ModelSim or if you are familiar with these arguments and prefer to use them Source libraries are searched after the source files on the command line are compiled If there are any unresolved references to modules or UDPs then the compiler searches the source libraries to satisfy the
409. lush fstrobeh sscanf fgetc fstrobeo swrite fgets ftell swriteb fmonitor fwrite swriteh fmonitorb fwriteb swriteo fmonitorh ungetc SystemVerilog System Tasks and Functions The following ModelSim supported system tasks and functions are described in detail in the SystemVerilog IEEE Std p1800 2005 LRM Table 7 8 SystemVerilog System Tasks and Functions 1 Expression size function Range function bits isunbounded Table 7 9 SystemVerilog System Tasks and Functions 2 Shortreal Array querying conversions functions shortrealbits dimensions bitstoshortreal left right low high increment size ModelSim User s Manual 6 390222 907 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Table 7 10 SystemVerilog System Tasks and Functions 4 Reading packed data Writing packed data Other functions functions functions readmemb writememb root readmemh writememh unit System Tasks and Functions Specific to the Tool The following system tasks and functions are specific to ModelSim They are not included in the IEEE Std 1364 nor are they likely supported in other simulators Their use may limit the portability of your code Table 7 11 Tool Specific Verilog System Tasks and Functions disable_signal_spy messagelog enable_signal_spy psprintf init_signal_driver sdf_done init_signal_spy signal_force signal_release messagelog Sy
410. m The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched again This process is repeated until all references are resolved or until no new unresolved references are found Source libraries are searched in the order they appear on the command line v lt filename gt y lt directory gt libext lt suffix gt librescan nolibcell R lt simargs gt Verilog XL uselib Compiler Directive The uselib compiler directive is an alternative source library management scheme to the v y and libext compiler arguments It has the advantage that a design may reference different modules having the same name You compile designs that contain uselib directive statements using the compile_uselibs argument described below to vlog The syntax for the uselib directive is uselib lt library_reference gt where lt library_reference gt can be one or more of the following ModelSim User s Manual v6 3g 177 May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files e dir lt library_directory gt which is equivalent to the command line argument y library directory e file library file which is equivalent to the command line argument v library file e libext file extension which is equivalent to the command line argument Flibext 4 file extension lib library name which references a library fo
411. m User s Manual v6 3g 311 May 2008 Signal Spy signal_release Related procedures init_signal_driver init_signal_spy signal_force Limitations e You cannot release a bit or slice of a register you can release only the entire register signal_release Example This example releases any forces on the signals data and c k when the signal release flag is a 1 Both calls will send a message to the transcript stating which signal was released and when library IEEE modelsim_lib use IEEE std logic 1164 a11 use modelsim lib util all entity testbench is end architecture only of testbench is signal release flag std logic begin stim design process begin wait until release_flag 1 signal release testbench dut blkl data 1 signal release testbench dut blkl clk 1 end process stim design end signal release Example This example releases any forces on the signals data and clk when the register release flag transitions to a 1 Both calls will send a message to the transcript stating which signal was released and when 312 ModelSim User s Manual v6 3g May 2008 Signal Spy signal_release module testbench reg release_flag always posedge release_flag begin Ssignal_r ase testbench dut blkl data 1 signal release testbench dut blk1 clk 1 end endmodule ModelSim User s Manual v6 3g 313 May 2008 Signal Spy signal_rele
412. mands 15 24 ERR eane 352 Simulator Tcl Time Commands Lie sa sched S nauenean 353 ODVEESIODS epeei a equ ra ras kx E Ka E E qe DER RA aee dab Rees 354 DT Lao MR ETT 354 FSK CUIUS SCORE ERE ERES TTE EL E TO OTT OI TE ID 355 TOUR AINE PTC 355 Macros DO Files 0 0 eenen e rr ras 357 Creams DO Piles Sou orco ER e RESEESRUERRUA TUA EN cote PX Edd dep e Eos 357 Using Parameters with DO Files 5 RR RR RE RERASTASSERESAG RR AREERSAS 358 Deleting a File from a do Script odceecaretesucs9kkec D eT RR E E Rb EP ERES 358 Making Macro Parameters Optional 0 0 c eee eee 359 Useful Commands for Handling Breakpoints and Errors 0000000 360 Error Action im DO Paes oan os ears eos Sah en Sp Rc A o bao Spec aa RN 361 Appendix A Simulator Variables 45455929 tides sed bPeRRRORAdURPERAESEACIEROP ERqPREWR TEPORE 363 Variable Settings REGO asd c4 qt REOR CEREREA NER PESRONERERISA CERRO MM ES 363 Environment Variables 42x22 vex ES ieena aiaee RET ARER RR PER E E AR 363 Environment Variable Expansion 0 0 00 cece eee e 363 Setting Environment Variables o5 0i 05 seeders gate eae een eee RIA sete RAW 364 Creating Environment Variables in Windows 0 0 0 cece eee ee eens 368 Referencing Environment Variables 0 0 0 c cece eee teens 368 Removing Temp Files VSOUT 0 0 0 0 eect tenes 369 Simulator Control Variables ausa suo Er Fees Sie dees n
413. manually at the command prompt that information is also saved for use with the Forward Back options 66 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Source Window Using Language Templates ModelSim language templates help you write code They are a collection of wizards menus and dialogs that produce code for new designs testbenches language constructs logic blocks etc Note The language templates are not intended to replace thorough knowledge of coding They are intended as an interactive reference for creating small sections of code If you are unfamiliar with a particular language you should attend a training class or consult one of the many available books To use the templates either open an existing file or select File New Source to create a new file Once the file is open select Source Show Language Templates if the Source window is docked in the Main window select View Show Language Templates of the Source window is undocked This displays a pane that shows the available templates Figure 2 23 Language Templates Ihi C modeltech examples systeme sc_vhdl_vlog Untitled 1 Language Templates aN New Design Wizard Create Testbench Language Constructs Stimulus Generators uni C ringbuf h H control vhd h Untitled 1 KE The templates that appear depend on t
414. mation End User License Agreement 14 ModelSim User s Manual v6 3g May 2008 List of Examples Example 2 1 Using the radix define Command 0 0 0 0 eee eee eee 38 Example 3 1 Encryption Envelope Contains IP Code to be Protected 105 Example 3 2 Encryption Envelope Contains include Compiler Directives 106 Example 3 3 Results After Compiling with vlog protect 0 e eee 108 Example 7 1 Invocation of the Verilog Compiler 0 0 170 Example 7 2 Incremental Compilation Example 0 0 0 0 c eee eee eee 171 Example 7 3 Sub Modules with Common Names 0 000 e eee eee eee 175 Example 13 1 Verilog Counter 24254 axo SEX xe EE Rp SEEN RM esque se RSS NEA RE 331 Example 13 2 VHDL Adder scuba ELDER I eet eens eG eed wees RERO 331 Example 15 3 Mixed HDL Design 15 2 n lt eenecidecshd cand IA Per RR ex3 rhe RARE Rd 331 Example 13 4 Replacing Instances 1 2 0 2 0 cece eee eh 332 Example 13 5 VCD Output from vcd dumpports 0 00 0 343 Example 14 1 Tel while Loop 2 224 444 4464 nh RERO RESO REERR RRI EROR abe goed 355 Example 14 2 Tcl for Command 0 eee eee eee 355 Example 14 3 Tcl foreach Command oy 50 sea bass cee ede RR EP EIN RDPE RE 355 Example 14 4 Tcl break Command 214 eo ere e ed ree Y ear v A x RR as 356 Example 14 5 Tcl continue Command 0 cece eee eere 356 Example 14 6 Access and Transf
415. max_mult gt Each multiplier is a real number that is used to scale the corresponding delay in the SDF file lt scale_type gt String that overrides the lt mtm_spec gt delay selection Optional The lt mtm_spec gt delay selection is always used to select the delay scaling factor but if a scale type is specified then it will determine the min typ max selection from the SDF file The allowed strings are from min from minimum from typ from typical from max from maximum and from mtm Case is ignored and the default is from mtm which means to use the mtm spec value Examples Optional arguments can be omitted by using commas or by leaving them out if they are at the end of the argument list For example to specify only the SDF file and the instance to which it applies ModelSim User s Manual v6 3g 319 May 2008 Standard Delay Format SDF Timing Annotation sdf_annotate Ssdf_annotate myasic sdf testbench ul To also specify maximum delay values Ssdf_annotate myasic sdf testbench ul maximum SDF to Verilog Construct Matching The annotator matches SDF constructs to corresponding Verilog constructs in the cells Usually the cells contain path delays and timing checks within specify blocks For each SDF construct the annotator locates the cell instance and updates each specify path delay or timing check that matches An SDF construct can have multiple matches in which case each m
416. me 4 state char short int float packed_struct packed_union double enum 2 state packed_struct sc_bigint packed_union 4 state sc_biguint packed_array single Dim sc_int multi D 2 state and 4 state sc_uint enum or string sc_signed sc_unsigned Scope architecture module interface package sc_module Recognizable process or record compilation unit struct or in static variables within a task function named block class Array Kind single dimensional any combination of single dimensional or or multi unpacked dynamic and multi dimensional dimensional associative arrays real shortreal and float 1 These enumerated type value sets must have values that are longer than one character The listed width is the number of entries in the enumerated type definition and the depth is the size of the array itself 2 Any combination of unpacked dynamic and associative arrays is considered a memory provided the leaf level of the data structure is a string or an integral type Associative Arrays in Verilog SystemVerilog For an associative array to be recognized as a memory the index must be of an integral type see above or wildcard type For associative arrays the element kind can be any type allowed for fixed size arrays Viewing Single and Multidimensional Memories Single dimensional arrays of integers are interpreted as 2D memory arrays In these cases the word width listed
417. ment 437 PLI support for VHDL objects 439 registering PLI applications 419 489 ABCDEFGHIJKLMNOPQRSTUVWXYZ specifying the PLI VPI file to load 433 Verilog XL compatibility with 169 417 Veriuser ini file variable 393 420 Veriuser specifying PLI applications 420 veriuser c file 439 VHDL compiling design units 139 conditions and expressions automatic conversion of H and L 375 creating a design library 139 delay file opening 402 dependency checking 140 file opening delay 402 language templates 67 language versions 141 library clause 135 object support in PLI 439 optimizations inlining 140 resource libraries 135 simulating 144 source code viewing 63 standards 31 timing check disabling 144 VITAL package 136 VHDL utilities 155 156 303 get resolution 155 to real 156 to time 157 VHDL 1987 compilation problems 141 VHDL 1993 enabling support for 380 VHDL 2002 enabling support for 380 VHDLO3 ini file variable 380 viewing 76 library contents 131 waveforms 219 virtual compare signal restrictions 263 virtual hide command 230 virtual objects 229 virtual functions 231 virtual regions 232 virtual signals 230 490 virtual types 232 virtual region command 232 virtual regions reconstruct RTL hierarchy 232 virtual save command 231 virtual signal command 230 virtual signals reconstruct RTL level design busses 230 reconstruct the origi
418. ming VITAL_Primitives and VITAL_memory packages The optimized procedures are functionally equivalent to the IEEE 1076 4 VITAL ASIC Modeling Specification VITAL 1995 and 2000 VITAL Compliance Checking If you are using VITAL 2 2b you must turn off the compliance checking either by not setting the attributes or by invoking vcom with the option novitalcheck Compiling and Simulating with Accelerated VITAL Packages vcom automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built in routines Invoke with the novital option if you do not want to use the built in VITAL routines when debugging for instance To exclude all VITAL functions use novital all vcom novital all design vhd To exclude selected VITAL functions use one or more novital lt fname gt options vcom novital VitalTimingCheck novital VitalAND design vhd The novital switch only affects calls to VITAL functions from the design units currently being compiled Pre compiled design units referenced from the current design units will still call the built in functions unless they too are compiled with the novital option ModelSim VITAL built ins will be updated in step with new releases of the VITAL packages 154 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Util Package Util Package The util package contains various VHDL utilities that you can run as commands The packa
419. mmand line or in the modelsim ini file Sensitivity list warning 412 signal is read by the process but is not in the sensitivity list Description ModelSim outputs this message when you use the check synthesis argument to vcom It reports the warning for any signal that is read by the process but is not in the sensitivity list Suggested action There are cases where you may purposely omit signals from the sensitivity list even though they are read by the process For example in a strictly sequential process you may prefer to include only the clock and reset in the sensitivity ModelSim User s Manual v6 3g May 2008 Error and Warning Messages Miscellaneous Messages list because it would be a design error if any other signal triggered the process In such cases your only option is to not use the check_synthesis argument Tcl Initialization error 2 Tcl Init Error 2 Can t find a usable Init tcl in the following directories vf wa fECL ECIE 3 e Description This message typically occurs when the base file was not included in a Unix installation When you install ModelSim you need to download and install 3 files from the ftp site These files are modeltech base tar gz modeltech docs tar gz modeltech platform exe gz If you install only the platform file you will not get the Tcl files that are located in the base file This message could also occur if the file or directory was deleted or corrupt
420. mmand substitution see below unless quoted A command is evaluated in two steps First the Tcl interpreter breaks the command into words and performs substitutions as described below These substitutions are performed in the same way for all commands The first word is used to locate a command procedure to carry out the command then all of the words of the command are passed to the command procedure The command procedure is free to interpret each of its words in any way it likes such as an integer variable name list or Tcl script Different commands interpret their words differently Words of a command are separated by white space except for newlines which are command separators If the first character of a word is a double quote then the word is terminated by the next double quote character If semi colons close brackets or white space characters including newlines appear between the quotes then they are treated as ordinary characters and included in the word Command substitution variable substitution and backslash substitution are performed on the characters between the quotes as described below The double quotes are not retained as part of the word ModelSim User s Manual v6 3g May 2008 5 Tcl and Macros DO Files Tcl Command Syntax If the first character of a word is an open brace then the word is terminated by the matching close brace Braces nest within the word for each additional open brace there
421. mmand to run when you hit a breakpoint within a macro onElabError specify a command to run when an error is encountered during elaboration onerror specify a command to run when an error is encountered within a macro status get a traceback of nested macro calls when a macro is interrupted abort terminate a macro once the macro has been interrupted or paused pause cause the macro to be interrupted the macro can be resumed by entering a resume command via the command line 360 ModelSim User s Manual v6 3g May 2008 Tcl and Macros DO Files Macros DO Files You can also set the OnErrorDefaultAction Tcl variable to determine what action ModelSim takes when an error occurs To set the variable on a permanent basis you must define the variable in a modelsim tcl file see The modelsim tcl File for details Error Action in DO Files If a command in a macro returns an error ModelSim does the following 1 If an onerror command has been set in the macro script ModelSim executes that command The onerror command must be placed prior to the run command in the DO file to take effect 2 If no onerror command has been specified in the script ModelSim checks the OnErrorDefaultAction variable If the variable is defined its action will be invoked 3 If neither 1 or 2 is true the macro aborts Using the Tcl Source Command with DO Files Either the do command or Tcl source command can execute a DO file but the
422. mpf file every time the project is opened Project Conversion Between Versions Projects are generally not backwards compatible for either number or letter releases When you open a project created in an earlier version you will see a message warning that the project will be converted to the newer version You have the option of continuing with the conversion or cancelling the operation As stated in the warning message a backup of the original project is created before the conversion occurs The backup file is named project name gt mpf bak and is created in the same directory in which the original project is located Language templates have been added for SystemVerilog support and the SystemVerilog syntax radio button was removed from the Verilog tab in the project compiler settings dialog box Old projects with Verilog files that had the SystemVerilog syntax selected will automatically convert to SystemVerilog type Customers may need to remove the hte directory from their home directory in order for the new templates to load properly Getting Started with Projects This section describes the four basic steps to working with a project 112 Step 1 Creating a New Project This creates a mpf file and a working library Step 2 Adding Items to the Project Projects can reference or include source files folders for organization simulations and any other files you want to associate with the project You can copy files into the pr
423. mple If the simulator resolution is set to 1 ps and you enter the following function timeval to time 72 49 then the value returned to timeval would be 72 ps Modeling Memory As a VHDL user you might be tempted to model a memory using signals Two common simulator problems are the likely result e You may get a memory allocation error message which typically means the simulator ran out of memory and failed to allocate enough storage e Or you may get very long load elaboration or run times These problems are usually explained by the fact that signals consume a substantial amount of memory many dozens of bytes per bit all of which needs to be loaded or initialized before your simulation starts Modeling memory with variables or protected types instead provides some excellent performance benefits e storage required to model the memory can be reduced by 1 2 orders of magnitude e startup and run times are reduced e associated memory allocation errors are eliminated In the VHDL example below we illustrate three alternative architectures for entity memory 158 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Modeling Memory e Architecture bad_style_87 uses a vhdl signal to store the ram data e Architecture style_87 uses variables in the memory process e Architecture style_93 uses variables in the architecture For large memories architecture bad_style_S7 runs many times longer than the other two and us
424. must be an additional close brace however if an open brace or close brace within the word is quoted with a backslash then it is not counted in locating the matching close brace No substitutions are performed on the characters between the braces except for backslash newline substitutions described below nor do semi colons newlines close brackets or white space receive any special interpretation The word will consist of exactly the characters between the outer braces not including the braces themselves If a word contains an open bracket then Tcl performs command substitution To do this it invokes the Tcl interpreter recursively to process the characters following the open bracket as a Tcl script The script may contain any number of commands and must be terminated by a close bracket The result of the script i e the result of its last command is substituted into the word in place of the brackets and all of the characters between them There may be any number of command substitutions in a single word Command substitution is not performed on words enclosed in braces If a word contains a dollar sign then Tcl performs variable substitution the dollar sign and the following characters are replaced in the word by the value of a variable Variable substitution may take any of the following forms o S name Name is the name of a scalar variable the name is terminated by any character that isn t a letter digit or underscore
425. n Ctrl a Windows Only Ctrl select the entire contents of the widget clear any selection in the widget Ctrl UNIX Ctrl UNIX Ctrl z Windows Meta lt UNIX only undoes previous edits in the Source window move cursor to the beginning of the file Meta gt UNIX only move cursor to the end of the file Page Up Meta v UNIX only move cursor up one screen Meta w UNIX Ctrl c Windows copy selection F3 F4 Shift F4 Peforms a Find Next action in the Source Window Change focus to next pane in main window Change focus to previous pane in main window F5 Shift F5 Toggle between expanding and restoring size of pane to fit the entire main window Toggle on off the pane headers F8 search for the most recent command that matches the characters typed Main window only F9 F10 run simulation continue simulation F11 Windows only 452 single step ModelSim User s Manual v6 3g May 2008 Command and Keyboard Shortcuts List Window Keyboard Shortcuts Table D 3 Keyboard Shortcuts cont FI Windows on The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line List Window Keyboard Shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Table D 4
426. n If the resolution set by t is larger than the precision set in a module the time values in that module are rounded up If the resolution set by t is smaller than the precision of the module the precision of that module remains whatever is specified by the timescale directive Consider the following code 184 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs timescale 1 ns 100 ps module foo initial 12 536 Sdisplay The list below shows three possibilities for t and how the delays in the module are handled in each case e t not set The delay is rounded to 12 5 as directed by the module s timescale directive e tis set to 1 fs The delay is rounded to 12 5 Again the module s precision is determined by the timescale directive ModelSim does not override the module s precision e tis set to 1 ns The delay will be rounded to 13 The module s precision is determined by the t setting ModelSim can only round the module s time values because the entire simulation is operating at 1 ns Choosing the Resolution for Verilog You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays The time precision should not be unnecessarily small because it limits the maximum simulation time limit and it degrades performance in some cases Event Ordering in Verilog Designs Event based simul
427. n The correct syntax for setuphold and recrem is as follows setuphold Syntax setuphold clk_event data_event setup_limit hold_limit notifier tstamp_cond tcheck_cond delayed_clk delayed_data Arguments 192 The clk_event argument is required It is a transition in a clock signal that establishes the reference time for tracking timing violations on the data_event Since setuphold combines the functionality of the setup and hold system tasks the clk_event sets the lower bound event for hold and the upper bound event for setup The data_event argument is required It is a transition of a data signal that initiates the timing check The data_event sets the upper bound event for hold and the lower bound limit for setup The setup_limit argument is required It is a constant expression or specparam that specifies the minimum interval between the data_event and the clk_event Any change to the data signal within this interval results in a timing violation The hold_limit argument is required It is a constant expression or specparam that specifies the interval between the c k event and the data_event Any change to the data signal within this interval results in a timing violation ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs e The notifier argument is optional It is a register whose value is updated whenever a timing violation occurs The notifier
428. n H 15 C QuestaTestcases callstackView callstack sv 7e83Sefd 4 Module top 35 C QuestaTestcases calistackView callstack sv 7e83a9b5 Using the Call Stack Pane The Call Stack pane contains five columns of information to assist you in debugging your design indicates the depth of the function call with the most recent at the top In indicates the function Line indicates the line number containing the function call File indicates the location of the file containing the function call Address indicates the address of the execution in a foreign subprogram such as C The Call Stack pane allows you to perform the following actions within the pane Double click on the line of any function call o Displays the local variables at that level in the Locals Window o Displays the corresponding source code in the Source Window Right click in the column headings o Displays a pop up window that allows you to show or hide columns ModelSim User s Manual v6 3g 49 May 2008 Graphical User Interface Dataflow Window Dataflow Window The Dataflow window allows you to explore the physical connectivity of your design Note 3 OEM versions of ModelSim have limited Dataflow functionality Many of the features described below will operate differently The window will show only one process an
429. n Results With Datasets This chapter describes datasets and virtuals both methods for viewing and organizing simulation data in ModelSim Chapter 9 Waveform Analysis This chapter describes how to perform waveform analysis with the ModelSim Wave and List windows Chapter 10 Debugging with the Dataflow Window This chapter describes how to trace signals and assess causality using the ModelSim Dataflow window Chapter 11 Signal Spy This chapter describes Signal Spy a set of VHDL procedures and Verilog system tasks that let you monitor drive force or release a design object from anywhere in the hierarchy of a VHDL or mixed design Chapter 12 Standard Delay Format SDF Timing Annotation This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Chapter 13 Value Change Dump VCD Files This chapter explains Model Technology s Verilog VCD implementation for ModelSim The VCD usage is extended to include VHDL designs Chapter 14 Tcl and Macros DO Files This chapter provides an overview of Tcl tool command language as used with ModelSim Appendix A Simulator Variables This appendix describes environment system and preference variables used in ModelSim ModelSim User s Manual v6 3g May 2008 Introduction Text Conventions Appendix B Error and Warning Messages This append
430. n error message such as Error mixed package b vhd 4 Parameter kinds do not conform between declarations in package header and body out file Direction of concatenation To solve some technical problems the rules for direction and bounds of concatenation were changed from VHDL 87 to VHDL 93 You won t see any difference in simple variable signal assignments such as ModelSim User s Manual v6 3g May 2008 VHDL Simulation Compiling VHDL Files But if you 1 have a function that takes an unconstrained array as a parameter 2 pass a concatenation expression as a formal argument to this parameter and 3 the body of the function makes assumptions about the direction or bounds of the parameter then you will get unexpected results This may be a problem in environments that assume all arrays have downto direction xnor xnor is a reserved word in VHDL 93 If you declare an xnor function in VHDL 87 without quotes and compile it under VHDL 2002 you will get an error message like the following Error xnor vhd 3 near xnor expecting STRING IDENTIFIER FOREIGN attribute In VHDL 93 package STANDARD declares an attribute FOREIGN If you declare your own attribute with that name in another package then ModelSim issues a warning such as the following Compiling package foopack Warning foreign vhd 9 vcom 1140 VHDL 1993 added a definition of the attribute foreign to package std stand
431. n path delay mode the distributed delays are set to zero in any module that contains a path delay Select this delay mode with the delay_mode_path compiler argument or the delay mode path compiler directive Unit Delay Mode In unit delay mode the non zero distributed delays are set to one unit of simulation resolution determined by the minimum time precision argument in all timescale directives in your design or the value specified with the t argument to vsim and the specify path delays and timing constraints are ignored Select this delay mode with the delay mode unit compiler argument or the delay mode unit compiler directive Zero Delay Mode In zero delay mode the distributed delays are set to zero and the specify path delays and timing constraints are ignored Select this delay mode with the delay mode zero compiler argument or the delay mode zero compiler directive System Tasks and Functions ModelSim supports system tasks and functions as follows e All system tasks and functions defined in IEEE Std 1364 e Some system tasks and functions defined in SystemVerilog IEEE std p1800 2005 LRM e Several system tasks and functions that are specific to ModelSim e Several non standard Verilog XL system tasks The system tasks and functions listed in this section are built into the simulator although some designs depend on user defined system tasks implemented with the Programming Language Interface PLI Verilog Procedural Int
432. n referencing bit selects or part selects of Verilog registers in the GUI or when expanding Verilog registers in the Objects Wave or List window This is necessary because referencing Verilog register elements requires an intermediate step of shifting and masking of the Verilog vreg data structure Virtual Regions User defined design hierarchy regions can be defined and attached to any existing design region or to the virtuals context tree They can be used to reconstruct the RTL hierarchy in a gate level design and to locate virtual signals Thus virtual signals and virtual regions can be used in a gate level design to allow you to use the RTL test bench Virtual regions are created and attached using the virtual region command Virtual Types User defined enumerated types can be defined in order to display signal bit sequences as meaningful alphanumeric names The virtual type is then used in a type conversion expression to convert a signal to values of the new type When the converted signal is displayed in any of the windows the value will be displayed as the enumeration string corresponding to the value of the original signal Virtual types are created using the virtual type command 232 ModelSim User s Manual v6 3g May 2008 Chapter 9 Waveform Analysis When your simulation finishes you will often want to analyze waveforms to assess and debug your design Designers typically use the Wave window for waveform analysis Howeve
433. n time is not considered an attribute of the message system This time is available in the Message Viewer Minimum field width specifiers are accepted before each specifier character for example oo 0I i TOT oo Left right justification specifier is accepted as it is for display Macros You can use the macros LINE returns line number information and __FILE__ returns filename information when creating your messagelog tasks For example module top function void wrapper string file int line Smessagelog Hello The caller was at F 0L file line endfunction ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions initial begin wrapper __FILE__ LINE wrapper __ FILE LINE end endmodule which would produce the following output Hello The caller was at test sv 7 Hello The caller was at test sv 8 Examples The following messagelog task messagelog hello world transcripts the message hello world while logging all default attributes but does not log a category The following messagelog task Smessagelog S 0t PCI X burst read started in transactor R Note Stime 50 top sysfixture pcix transcripts the message 150 PCI X burst read started in transactor top sysfixture pcix while silently logging the severity level of Note and uses a direct referenc
434. n units equivalent to the smallest unit of simulation time also known as the simulator resolution limit The resolution limit defaults to the smallest time units that you specify among all of the timescale compiler directives in the design Here is an example of a timescale directive timescale 1 ns 100 ps The first number 1 ns is the time units the second number 100 ps is the time precision which is the rounding factor for the specified time units The directive above causes time values to be read as nanoseconds and rounded to the nearest 100 picoseconds Time units and precision can also be specified with SystemVerilog keywords as follows timeunit 1 ns timeprecision 100 ps 182 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Modules Without Timescale Directives Unexpected behavior may occur if your design contains some modules with timescale directives and others without The time units for modules without a timescale directive default to the simulator resolution Example Assume you have the two modules shown in Table 7 1 Table 7 1 Example Modules With and Without Timescale Directive Module 1 with directive Module 2 without directive timescale 1 ns 10 ps module mod2 set module mod 1 set output set reg set output set parameter d 1 55 reg set parameter d 1 55 initial begin initial set I bz begin ftd set 1 b0 s
435. nal RTL hierarchy 230 virtual hide command 230 visibility of declarations in unit 175 VITAL compiling and simulating with accelerated VITAL packages 154 disabling optimizations for debugging 154 specification and source code 153 VITAL packages 154 vital95 ini file variable 371 vlog command protect argument 100 101 vlog95compat ini file variable 374 VPI registering applications 421 VPI PLI 217 VPI PLI DPI 417 compiling and linking C applications 429 compiling and linking C applications 43 VSIM license lost 414 VSOUT temp file 369 W WarnConstantChange ini file variable 393 Warning ini file variable 399 warnings empty port name 412 exit codes 410 getting more information 407 messages long description 407 metavalue detected 412 severity level changing 408 suppressing VCOM warning messages 408 suppressing VLOG warning messages 409 suppressing VSIM warning messages 409 Tcl initialization error 2 413 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I too few port connections 413 turning off warnings from arithmetic packages 401 waiting for lock 412 watching a signal value 80 wave groups 256 add items to existing 258 creating 257 deleting 258 drag from Wave to List 258 drag from Wave to Transcript 258 removing items from existing 258 ungrouping 258 Wave Log Format WLF file 219 wave log format WLF file see also WLF files wave viewer Dataflow
436. nary forms with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1997 2002 FreeBSD Project All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the f
437. native Input Output Files 25 2222 educado RE Re ARRA ERES 152 Flushing the TEXTIO Buffet is iicaco kae ERE ERRAT ERE REGRRX XR sana eee 152 Providing SOUS a acra a achete bte perd m Pad ac Ed dE e Died dra i 153 VITAL Specification and Source Code 0 2 cece eens 153 VITAL PACKABES lt 2 hao and Soe RIXTSEQEREIQd PODER IEN EOD Seedy Pie dees Bees 153 VITAL Compliance 2 2cseasiiereidbacesskesedeeeeddavgeedesetbeceddicaeaes 154 VITAL Compliance Checking 2 c02 lt elosstbsivectdedstetesedsbesewnaseegees 154 Compiling and Simulating with Accelerated VITAL Packages 4 154 Util Packets uude Gun Gee EXER EOME ea E onere doe Keira bir Sede etn 155 BEL TESOLDIUCU cg esas dac eias Padus sd uad esa ed ak ees dua sRu eee 155 imi signal Ot Vet 5 oen e Reg UE CERERI IQ I HM mete d Re oA ei 155 iit Serial Spy euge instr px eR Ser s md gx sx wee eee xa sita ies 2h 156 Sigrial Torce ases t RR REPERI OERPMC RERO ERI P rERE SE I RRIE EE MD EE 156 signal Tele 3880 sos aye So dep R I ed eet Oe ERE M Ea FREE qs BEE aa ee 156 io Xxeadl i tatecieibadadetac ase ene acatadnsecataensadalacad scasecandebasee 156 to NE sree eos OG hob eed TOT TT TTE TRITT 157 Modeling Memory scsezia i ERRARE RE DER EARS RR SR RR Ru E ELE RR RES 158 VHDLSrand VHDLOS Examples sod oys dades co REPRE OUS NE eV RFIPeS OPEN 160 VHDLO2 example cns cebasi ess arine p RR UR EEEP Rx Rame es ndo Rd 163 Affecting Performance by Cancelling Scheduled Events
438. nce dir library directory or the directory containing the file in the library reference file library file The simulator will ignore a library reference libext file extension For example the following uselib directives infer the same object library 178 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files uselib dir h vendorA uselib file h vendorA libcells v In both cases the simulator assumes that the library source is compiled into the object library h vendorA work The simulator also extends the uselib directive to explicitly specify the object library with the library reference lib library name For example uselib lib h vendorA work The library name can be a complete path to a library or it can be a logical library name defined with the vmap command compile_uselibs Argument Use the compile uselibs argument to vlog to reference uselib directives The argument finds the source files referenced in the directive compiles them into automatically created object libraries and updates the modelsim ini file with the logical mappings to the libraries When using compile uselibs ModelSim determines into which directory to compile the object libraries by choosing in order from the following three values e The directory name specified by the compile uselibs argument For example compile uselibs mydir e The directory specified by the
439. nce x h 4 d hop leryAs essert__0 kopimydutlsssert 1 kopimydutlasseit 2 kopimydutlaeset 3 kopimydutisssert 4 kopierydutlaeseit dt pta kopimydutlassert dut ptas kopinydutlazoeit t pib hkopierydutlaesert de ptc Roplmydutiassert__dut_pid kopjmvdutlassert aut pte Now eo T L B HA Misc 54 s JA Error 53 FR Asserbon faded A Assertion faked A Assertion faled FR Assertion faled FR Assertion faded FR Assertion faded ipm Fa Tacit A message ve Now 1 us Deka 1 simcjtop a35 ns to 601 ns Here is an example of a Wave window that is undocked from the MDI frame All menus and icons associated with Wave window functions now appear in the menu and toolbar areas of the Wave window ModelSim User s Manual v6 3g 85 May 2008 Graphical User Interface Wave Window Figure 2 37 Wave Window Dock Button ipi xi File Edit View Add Format Tools Window Dock button Messages top mydut assert__0 top mydut assert__1 top mydut assert__2 top mydut assert__3 ftop mydutfassert__4 top mydut assert__dut_pla top mydut assert_ dut_plaa top mydut assert__dut_pib top mydut assert__dut_pic top mydut assert__dut_pid fhantrwdikisccark dik mica Cursor 1 E 446 ns to 786 ns Now 1us Delta 1 If the Wave window is docked into the Main window MDI frame all menus and icons that were in the standalone version of the Wave window move i
440. ncel_period Optional time or integer Cancels the signal_force command after the specified period of time units Cancellation occurs at the last simulation delta cycle of a time unit ModelSim User s Manual v6 3g May 2008 Signal Spy signal_force For the VHDL procedure a value of zero cancels the force at the end of the current time period Default is 1 ms A negative value means that the force will not be cancelled For the Verilog task A value of zero cancels the force at the end of the current time period Default is 1 A negative value means that the force will not be cancelled For the SystemC function A value of zero cancels the force at the end of the current time period Default is 1 A negative value means that the force will not be cancelled e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the value is being forced on the dest_object at the specified time 0 Does not report a message Default Reports a message Related procedures init signal driver init signal spy signal release Limitations e You cannot force bits or slices of a register you can force only the entire register e Verilog memories arrays of registers are not supported signal force Example This example forces reset to a 1 from time 0 ns to 40 ns At 40 ns reset is forced to a 0 200000 ns after the second signal_force call was executed
441. ncelling Scheduled Events Affecting Performance by Cancelling Scheduled Events Performance will suffer if events are scheduled far into the future but then cancelled before they take effect This situation will act like a memory leak and slow down simulation In VHDL this situation can occur several ways The most common are waits with time out clauses and projected waveforms in signal assignments The following code shows a wait with a time out Signals synch bit 0 p process begin wait for 10 ms until synch 1 end process synch lt not synch after 10 ns At time 0 process p makes an event for time 10ms When synch goes to 1 at 10 ns the event at 10 ms is marked as cancelled but not deleted and a new event is scheduled at 10ms 10ns The cancelled events are not reclaimed until time 10ms is reached and the cancelled event is processed As a result there will be 500000 10ms 20ns cancelled but un deleted events Once 10ms is reached memory will no longer increase because the simulator will be reclaiming events as fast as they are added For projected waveforms the following would behave the same way Signals synch bit 0 p process synch begin output lt 0 1 after 10ms end process synch lt not synch after 10 ns Converting an Integer Into a bit_vector The following code demonstrates how to convert an integer into a bit_vector ModelSim User s Manual v6 3g 167 May 2008 VHDL S
442. nd All button allows you to find and highlight all occurrences of the item in the Find field If Zoom to is checked the view will change such that all selected items are viewable If Zoom to is not selected then no change is made to zoom or scroll state ModelSim User s Manual v6 3g 283 May 2008 Debugging with the Dataflow Window Dataflow Concepts Dataflow Concepts This section provides an introduction to the following important Dataflow concepts e Symbol Mapping e Current vs Post Simulation Command Output e Window vs Pane Symbol Mapping The Dataflow window has built in mappings for all Verilog primitive gates i e AND OR etc For components other than Verilog primitives you can define a mapping between processes and built in symbols This is done through a file containing name pairs one per line where the first name is the concatenation of the design unit and process names DUname Processname and the second name is the name of a built in symbol For example xorg only pl XOR org only pl OR andg only pl AND Entities and modules are mapped the same way AND1 AND AND2 AND A 2 input and gate AND3 AND AND4 AND AND5 AND AND6 AND xnor test XNOR Note that for primitive gate symbols pin mapping is automatic The Dataflow window looks in the current working directory and inside each library referenced by the design for the file dataflow bsm bsm stands for Built in Symbol Map It
443. nd to specify a signal to be removed from the group Note The delete wave command removes all occurrences of a specified name from the Wave window not just an occurrence within a group Miscellaneous Wave Group Features Dragging a wave group from the Wave window to the List window will result in all of the items within the group being added to the List window 258 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Formatting the List Window Dragging a group from the Wave window to the Transcript window will result in a list of all of the items within the group being added to the existing command line if any Formatting the List Window Setting List Window Display Properties Before you add objects to the List window you can set the window s display properties To change when and how a signal is displayed in the List window select Tools gt List Preferences from the List window menu bar when the window is undocked Figure 9 28 Modifying List Window Display Properties Modify Display Properties list 7 x Window Properties Triggers BE Signal Names fo Path Elements 0 for Full Path Max Title Rows 5 Dataset Prefix C Always Show Dataset Prefixes Show Dataset Prefixes if 2 or more C Never Show Dataset Prefixes Always undock list windows OK Cancel Apply Formatting Objects in the List Window You can adjust various properties of objects to create the view you find m
444. ndow displays the active processes in your simulation where the title bar of the window shows Active Processes You can change the window to show all the processes in a selected region by selecting the Process In Region menu item where the title bar of the window changes to Processes in Region ModelSim User s Manual v6 3g 47 May 2008 Graphical User Interface Process Window Figure 2 8 Process Window Active Processes Processes In Region lt Ready gt INITIAL 25 top lt Ready gt BUF 43 lt Ready gt ALWAYS 29 top lt Ready gt BUF 44 lt Ready gt NOT 29 top p lt Ready gt OR 45 lt Ready gt BUF 21 top p i lt Ready gt BUF 46 lt Ready gt BUF 22 top p i0 lt Ready gt 4ND 23 top p i0 lt Ready gt BUF 24 top p i0 Ready NOR 49 Jtop p Ready NAND 50 top p lt Ready gt INITIAL 69 top p lt Ready gt BUF 43 top p it lt Ready gt BUF 44 jtop p it Ready OR 45 Jtop p il Process Active default Process In Region Displaying the Process Window e Select View gt Process e Use the command view process Viewing Data in the Process Window You cannot actively place information in the Process window It is populated as you select regions of your design via the Structure tab also known as the Sim tab of the Workspace window The data in this window will change as you run your simulation and processes become inactive Each process in the window has a given stat
445. neric named tpd a y In this case make sure that the design is using the appropriate VITAL library cells If it is then there is probably a mismatch between the SDF and the VITAL cells You need to find the cell instance and compare its generic names to those expected by the annotator Look in the VHDL source files provided by the cell library vendor If none of the generic names look like VITAL timing generic names then perhaps the VITAL library cells are not being used If the generic names do look like VITAL timing generic names but don t match the names expected by the annotator then there are several possibilities e The vendor s tools are not conforming to the VITAL specification e The SDF file was accidentally applied to the wrong instance In this case the simulator also issues other error messages indicating that cell instances in the SDF could not be located in the design e The vendor s library and SDF were developed for the older VITAL 2 2b specification This version uses different name mapping rules In this case invoke vsim with the vital2 2b option vsim vital2 2b sdfmax testbench u1 myasic sdf testbench For more information on resolving errors see Troubleshooting Verilog SDF Verilog designs can be annotated using either the simulator command line options or the sdf_annotate system task also commonly used in other Verilog simulators The command line options annotate the design immediately after it is lo
446. nfiguring New Line Triggering in the List Window Figure 9 31 Signals Combined to Create Virtual Bus Mwave aeta MNT File Edit View Add Format Tools Window pard CIEI EE E test sm into E test sm outof oooo0000000000001 4 test_sm rst D 1 9 0994990949 9 994 34 test sm clk 1 33 downto 2 test sm i x 1J test_sm td_ O test_sm wr_ test_sm clk 750000 ps Cursor 1 Ops iA p a 18800 ps to 23200 ps Now 750 ns Delta 2 Configuring New Line Triggering in the List Window New line triggering refers to what events cause a new line of data to be added to the List window By default ModelSim adds a new line for any signal change including deltas within a single unit of time resolution You can set new line triggering on a signal by signal basis or for the whole simulation To set for a single signal select View gt Signal Properties from the List window menu bar when the window is undocked and select the Triggers line setting Individual signal settings override global settings 264 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Configuring New Line Triggering in the List Window Figure 9 32 Line Triggering in the List Window List Signal Properties 2 2 s e e y D To modify new line triggering for the whole simulation select Tools gt List Preferences from the List window menu bar when the window is undocked or use the configure command When yo
447. nformation gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights under this Agreement or addendum to this Agreement The provisions of this section 14 shall survive the expiration or termination of this Agreement 15 16 17 CONTROLLING LAW JURISDICTION AND DISPUTE RESOLUTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF THE STATE OF OREGON USA IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH OR SOUTH AMERICA All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Portland Oregon when the laws of Oregon apply or Dublin Ireland when the laws of Ireland apply Notwithstanding the foregoing all disputes in Asia except for Japan arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the Chairman of the Singapore International Arbitration Centre SIAC to be conducted in the English language in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute which rules are deemed to be incorporated by reference in this section 15 This section shall not restrict Mentor Graphics right to bring an action against you in the jurisdiction where your place of business is located The United Nations Convention on Contract
448. ng 364 setting in Windows 368 TranscriptFile specifying location of 392 used in Solaris linking for FLI 431 used in Solaris linking for PLI VPI DPI FLI 365 using with location mapping 405 variable substitution using Tcl 351 error can t locate C compiler 411 Error ini file variable 398 ErrorFile ini file variable 383 errors bad magic number 221 DPI missing import function 426 getting more information 407 severity level changing 408 SystemVerilog missing declaration 373 Tcl init error 413 VSIM license lost 414 escaped identifiers 201 Tcl considerations 202 event order in Verilog simulation 185 event queues 185 event watching commands placement of 357 events tracing 281 exit codes 410 478 JKLMNOPQRSTUVWXYZ exiting tool on sc stop or finish 388 expand environment variables 363 expand net 278 Explicit ini file variable 376 export TFs in DPI 411 Expression Builder 248 configuring a List trigger with 267 saving expressions to Tcl variable 250 Extended system tasks Verilog 214 F F8 function key 452 Fatal ini file variable 398 Fatal error SIGSEGV 191 File compression VCD tasks 335 file I O TextIO package 149 file line breakpoints 69 edit 70 273 files modelsim 467 files grouping for compile 117 filter processes 47 filtering signals in Objects window 62 folders in projects 123 fonts scaling 37 force command defaults 401 format file 261 Wav
449. ng post simulation debug If neither the wlfsimcachesize option for vsim nor the WLFSimCacheSize is specified the WLFCacheSize setting will be used e Value Range positive integer e Default 0 394 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables WLFSizeLimit This variable limits the WLF file by size as closely as possible to the specified number of megabytes if both size and time limits are specified the most restrictive is used See Limiting the WLF File Size e Value Range any positive integer in units of MB or 0 unlimited e Default O unlimited WLFTimeLimit This variable limits the WLF file by time as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used See Limiting the WLF File Size e Value Range any positive integer or 0 unlimited e Default O unlimited WLFUseThreads This variable specifies whether the logging of information to the WLF file is performed using multithreading This behavior is on by default on Solaris and Linux platforms where there are more than one processor on the system If there is only one processor available or you are running on a Windows system this behavior is off by default When this behavior is enabled the logging of information is performed on the secondary processor while the simulation and other tasks are performed on the primary processor e
450. nline of foo procedure is true To inhibit inlining for a particular package e g pack add the following attribute assignment attribute mti_inhibit_inline of pack package is true Do similarly for entities and architectures Differences Between Language Versions There are three versions of the IEEE VHDL 1076 standard VHDL 1987 VHDL 1993 and VHDL 2002 The default language version for ModelSim is VHDL 2002 If your code was written according to the 87 or 93 version you may need to update your code or instruct ModelSim to use the earlier versions rules To select a specific language version do one of the following Select the appropriate version from the compiler options menu in the GUI Invoke vcom using the argument 87 93 or 2002 Set the VHDL93 variable in the vcom section of the modelsim ini file Appropriate values for VHDL93 are 0 87 or 1987 for VHDL 1987 1 93 0r 1993 for VHDL 1993 ModelSim User s Manual v6 3g 141 May 2008 VHDL Simulation Compiling VHDL Files 2 02 or 2002 for VHDL 2002 The following is a list of language incompatibilities that may cause problems when compiling a design 142 VHDL 93 and VHDL 2002 The only major problem between VHDL 93 and VHDL 2002 is the addition of the keyword PROTECTED VHDL 93 programs which use this as an identifier should choose a different name All other incompatibilities are between VHDL 87 and VHDL 93 VITAL and SD
451. nore this argument Be careful that you do not set the threshold argument greater than or equal to the limit argument as that essentially disables the width check Also note that you cannot override the threshold argument by using SDF annotation ModelSim User s Manual v6 3g 205 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Table 7 6 IEEE Std 1364 System Tasks Display tasks PLA modeling tasks Value change dump VCD file tasks display Sasync and array dumpall displayb async nand array dumpfile displayh async or array dumpflush displayo async nor array dumplimit monitor async and plane dumpoff monitorb async nand plane dumpon monitorh async or plane dumpvars monitoro async nor plane monitoroff sync and array monitoron sync nand array strobe sync or array strobeb sync nor array strobeh sync and plane strobeo sync nand plane write sync or plane writeb sync nor plane writeh writeo Table 7 7 IEEE Std 1364 File I O Tasks File I O tasks fclose fmonitoro fwriteh fdisplay fopen fwriteo fdisplayb fread readmemb fdisplayh fscanf readmemh fdisplayo fseek rewind feof fstrobe sdf_annotate 206 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Table 7 7 IEEE Std 1364 File I O Tasks cont File I O tasks ferror fstrobeb sformat ff
452. nscript file by using the following ModelSim command immediately after ModelSim starts transcript file 400 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables Using a Startup File The system initialization file allows you to specify a command or a do file that is to be executed after the design is loaded For example VSIM Startup command Startup do mystartup do The line shown above instructs ModelSim to execute the commands in the macro file named mystartup do VSIM Startup command Startup run all The line shown above instructs VSIM to run until there are no events scheduled See the do command for additional information on creating do files Turning Off Assertion Messages You can turn off assertion messages from your VHDL code by setting a switch in the modelsim ini file This option was added because some utility packages print a huge number of warnings vsim IgnoreNote 1 IgnoreWarning IgnoreError IgnoreFailure I e l Turning off Warnings from Arithmetic Packages You can disable warnings from the Synopsys and numeric standard packages by adding the following lines to the vsim section of the modelsim ini file vsim NumericStdNoWarnings 1 StdArithNoWarnings 1 Force Command Defaults The force command has freeze drive and deposit options When none of these is specified then freeze is assumed for unresolved signals and drive is assum
453. nt Example 7 1 Invocation of the Verilog Compiler Here is a sample invocation of vlog vlog top v libext v u y vlog lib After compiling top v vlog scans the v og lib library for files with modules with the same name as primitives referenced but undefined in top v The use of libext v u implies filenames with a v or u suffix any combination of suffixes may be used Only referenced definitions are compiled Parsing SystemVerilog Keywords With standard Verilog files lt filename gt v vlog will not automatically parse SystemVerilog keywords SystemVerilog keywords are parsed when any of the following situations exists e any file within the design contains the sv file extension e or the sy argument is used with the vlog command 170 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files Here are two examples of the vlog command that enable SystemVerilog features and keywords in ModelSim vlog testbench sv top v memory v cache v vlog sv testbench v proc v In the first example the sv extension for testbench automatically instructs ModelSim to parse SystemVerilog keywords The sv option used in the second example enables SystemVerilog features and keywords Though a primary goal of the SystemVerilog standardization efforts has been to ensure full backward compatibility with the Verilog standard there is an issue with keywords SystemVerilog adds several new
454. nt ModelSim performs the clk2 lt clk assignment and the process which is sensitive to clk Before advancing the simulation time ModelSim finds that the process sensitive to clk2 can also be ModelSim User s Manual v6 3g 147 May 2008 VHDL Simulation Simulating VHDL Designs run Since there are no delays present the effect is that the value of inp appears at s in the same simulation cycle In order to get the expected results you must do one of the following e Insert a delay at every output e Make certain to use the same clock e Insert a delta delay To insert a delta delay you would modify the code like this process rst clk begin if rst 0 then s0 lt 0 elsif clk event and clk 1 then s0 lt inp s0 delayed lt s0 end if end process process rst clk2 begin if rst 0 then Sl lt tts elsif clk2 event and clk2 2 1 then sl lt s0 delayeg end if end process The best way to debug delta delay problems is observe your signals in the List window There you can see how values change at each delta time Detecting Infinite Zero Delay Loops If a large number of deltas occur without advancing time it is usually a symptom of an infinite zero delay loop in the design In order to detect the presence of these loops ModelSim defines a limit the iteration limit on the number of successive deltas that can occur When ModelSim reaches the iteration limit it issues a warning me
455. nt agencies RESTRICTED RIGHTS NOTICE Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227 7202 3 a or as set forth in subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville Oregon 97070 7777 USA THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth herein AUDIT RIGHTS You will monitor access to location and use of Software With reasonable prior notice and during your normal business hours Mentor Graphics shall have the right to review your software monitoring system and reasonably relevant records to confirm your compliance with the terms of this Agreement an addendum to this Agreement or U S or other local export laws Such review may include FLEXIm or FLEXnet report log files that you shall capture and provide at Mentor Graphics request Mentor Graphics shall treat as confidential information all of your i
456. ntax messagelog lt message gt lt value gt Arguments e lt message gt Your message enclosed in quotes using text and specifiers to define the output e lt value gt A scope object or literal value that corresponds to the specifiers in the message You must specify one value for each specifier in the message Specifiers The messagelog task supports all specifiers available with the display system task For more information about display refer to section 17 1 of the IEEE std 1364 2005 The following specifiers are specific to messagelog 208 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions Note The format of these custom specifiers differ from the display specifiers Specifically denotes a messagelog specifier and the letter denotes the type of specifier e C Group Category A string argument enclosed in quotes This attribute defines a group or category used by the message system If you do not specify C the message system logs User as the default e F Filename A string argument specifying a simple filename relative path to a filename or a full path to a filename In the case of a simple filename or relative path to a filename the tool uses what you specify in the message output but internally uses the current directory to complete these paths to form a full path this a
457. ntax 33 Text editing 450 TEXTIO buffer flushing 152 TextIO package 487 ABCDEFGHIJKLMNOPQRSTUVWXYZ alternative I O files 152 containing hexadecimal numbers 151 dangling pointers 151 ENDFILE function 152 ENDLINE function 152 file declaration 149 implementation issues 150 providing stimulus 153 standard input 150 standard output 150 WRITE procedure 150 WRITE STRING procedure 151 TF routines 443 TFMPC explanation 413 time measuring in Wave window 239 time resolution as a simulator state variable 404 time collapsing 228 time resolution in Verilog 182 in VHDL 144 time type converting to real 156 timeline display clock cycles 251 timescale directive warning investigating 183 timing disabling checks 326 Timing checks delay solution convergence 195 negative constraint algorithm 195 constraints 193 syntax for recrem 194 syntax for setuphold 192 using delayed inputs for checks 200 negative check limits described 192 TMPDIR environment variable 367 to real VHDL function 156 to time VHDL function 157 toggle coverage 488 count limit 391 max VHDL integer values 391 ToggleCountLimit ini file variable 391 ToggleVlogIntegers ini file variable 392 ToggleWidthLimit ini file variable 392 too few port connections explanation 413 tool structure 23 toolbar Dataflow window 51 Main window 45 tracing events 281 source of unknown 281 transcript disable file creation
458. nto the Main window menu bar and toolbar Wave Window Panes The Wave window is divided into a number of window panes All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes Pathname Pane The pathname pane displays signal pathnames Signals can be displayed with full pathnames as shown here or with only the leaf element displayed You can increase the size of the pane by clicking and dragging on the right border The selected signal is highlighted The white bar along the left margin indicates the selected dataset see Splitting Wave Window Panes 86 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Wave Window Figure 2 38 Pathnames Pane jtop mydut assert 0 jtop mydut assert 1 jtop mydut assert 2 jtop mydut assert 3 jtop mydut assert 4 jtop mydut assert dut pia jtop mydut assert dut piaa jtop mydut assert dut pib jtop mydut assert dut pic jtop mydut assert dut pid jtop mydut assert dut pie jtop mydut assert dut pif jtop mydut assert dut pig JtopJmvdut assert dut oih e e e 5 m e e m e Values Pane The values pane displays the values of the displayed signals The radix for each signal can be symbolic binary octal decimal unsigned hexadecimal ASCII or default The default radix can be set by selecting Simulate gt Runtime Options Note 22222222 LLL When the symbolic radix is chosen for SystemVerilog reg and
459. o S name index Name gives the name of an array variable and index gives the name of an element within that array Name must contain only letters digits and underscores Command substitutions variable substitutions and backslash substitutions are performed on the characters of index o name Name is the name of a scalar variable It may contain any characters whatsoever except for close braces There may be any number of variable substitutions in a single word Variable substitution is not performed on words enclosed in braces If a backslash V appears within a word then backslash substitution occurs In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word This allows characters such as double quotes close brackets and dollar signs to be included in words without ModelSim User s Manual v6 3g 347 May 2008 Tcl and Macros DO Files Tcl Command Syntax triggering special processing Table 14 2 lists the backslash sequences that are handled specially along with the value that replaces each sequence Table 14 2 Tcl Backslash Sequences Sequence Value Audible alert bell 0x7 Backspace 0x8 Form feed Oxc Newline Oxa Carriage return Oxd Tab 0x9 Vertical tab Oxb lt newline gt whiteSpace A single space character replaces the backslash newline and all spaces and tabs after the newl
460. o specify SDF files by using the sdf_annotate system task See sdf_annotate for more details Errors and Warnings Errors issued by the SDF annotator while loading the design prevent the simulation from continuing whereas warnings do not e Use either the sdfnoerror or the nosdferror option with vsim to change SDF errors to warnings so that the simulation can continue 316 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation VHDL VITAL SDF e Use either the sdfnowarn or the nosdfwarn option with vsim to suppress warning messages Another option is to use the SDF tab from the Start Simulation dialog box Figure 12 1 Select Disable SDF warnings sdfnowarn nosdfwarn to disable warnings or select Reduce SDF errors to warnings sdfnoerror to change errors to warnings See Troubleshooting for more information on errors and warnings and how to avoid them VHDL VITAL SDF VHDL SDF annotation works on VITAL cells only The IEEE 1076 4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation Once again the designer does not need to know the details of this specification because the library provider has already written the VITAL cells and tools that create compatible SDF files However the following summary may help you understand simulator error messages For additional VITAL specification information see VITAL Specification and Source Code SDF to VHDL Gen
461. o very top or scroll bar arrow bottom vertical scroll or far left or right horizontal scroll Click middle mouse button in scroll bar scrolls window to position of UNIX only click 1 If you choose Wave Mouse Mode Zoom Mode you do not need to press the Ctrl key Table D 6 Wave Window Keyboard Shortcuts Keystroke Action bring into view and center the currently active cursor i zoom in Shift i mouse pointer must be over the cursor or waveform panes o zoom out Shift o mouse pointer must be over the cursor or waveform panes f zoom full Shift f mouse pointer must be over the cursor or waveform panes l zoom last Shift 1 mouse pointer must be over the cursor or waveform panes r zoom range Shift r mouse pointer must be over the cursor or waveform panes 454 ModelSim User s Manual v6 3g May 2008 Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts Table D 6 Wave Window Keyboard Shortcuts Keystroke Up Arrow Down Arrow scrolls entire window up or down one line when mouse pointer is over waveform pane scrolls highlight up or down one line when mouse pointer is over pathname or values pane Left Arrow scroll pathname values or waveform pane left Right Arrow scroll pathname values or waveform pane right Page Up scroll waveform pane up by a page Page Down scroll waveform pane down by a page Tab Shif
462. occurs for a timing check if the SDF port condition is semantically equivalent to the specify port condition e A match occurs for a path delay if the SDF condition is lexically identical to the specify condition Timing check conditions are limited to very simple conditions therefore the annotator can match the expressions based on semantics For example Table 12 19 SDF Timing Check Conditions SETUP data COND reset 1 setup data posedge clk amp amp amp posedge clock 5 reset 0 0 324 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation SDF for Mixed VHDL and Verilog Designs The conditions are semantically equivalent and a match occurs In contrast path delay conditions may be complicated and semantically equivalent conditions may not match For example Table 12 20 SDF Path Delay Conditions COND r1 Il r2 IOPATH clk q 5 if r1 Il r2 clk gt q 5 matches COND r1 Il 12 IOPATH clk q 5 if r2 I r1 clk gt q 5 does not match The annotator does not match the second condition above because the order of rl and r2 are reversed Rounded Timing Values The SDF TIMESCALE construct specifies time units of values in the SDF file The annotator rounds timing values from the SDF file to the time precision of the module that is annotated For example if the SDF TIMESCALE is Ins and a value of 016 is annotated to a path delay in a module h
463. odelSim User s Manual v6 3g May 2008 Simulator Variables Environment Variables LD_LIBRARY_PATH A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used for both 32 bit and 64 bit shared libraries on Solaris Linux systems LD LIBRARY PATH 32 A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used only for 32 bit shared libraries on Solaris Linux systems LD LIBRARY PATH 64 A UNIX shell environment variable setting the search directories for shared libraries It instructs the OS where to search for the shared libraries for FLI PLI VPI DPI This variable is used only for 64 bit shared libraries on Solaris Linux systems LM LICENSE FILE The toolset s file manager uses the LM LICENSE FILE environment variable to find the location of the license file The argument may be a colon separated semi colon for Windows set of paths including paths to other vendor license files The environment variable is required MGC AMS HOME Specifies whether vcom adds the declaration of REAL VECTOR to the STANDARD package This is useful for designers using VHDL AMS to test digital parts of their model MODEL TECH The toolset automatically sets the MODEL TECH environment variable to the
464. oes Gees sass rs 369 Library Path Variables 52d Ra RERE EG KR ee RP RA RMASGd E x rd addo 370 Verilog Compiler Control Variables llleeeeeeeeeeee 371 VHDL Compiler Control Variables llle 374 Simulation Control Variables 54 632 e ERE ERE dber see eeeee he ee IARE ARE ERR 380 Setting Simulator Control Variables With The GUI 0 0 0 0 00 0000005 395 Message System Variables does ber RA DU PERERS RE RECRXQ CE REC RPeCR ECC ERES 398 Commonly Used INI Variables 4s ceres ERG RERZrORWIECRERT SERE CAR WE SR 399 Variable Precedente c duexea ep badd ceca x x uu deed RO A Race REA EROR DRN 402 smpuldtor SINS Variables sesca se Paw Sea SS pee Ge be ERI ese ew S E ESENS 403 ModelSim User s Manual v6 3g 11 May 2008 Table of Contents Referencing Simulator State Variables 2 0 cece eee eee eee eee 404 Special Considerations for the now Variable 1 0 0 0 0 eee eee eee ees 404 Appendix A Location Map pines iu 2a epo RE CER RE ne o 5095049540 0500S44054409 405 Referencing Source Files with Location Maps 0 0 cee e eee eee eee ee 405 Using Location Mapping 0 eee eect ete e t 405 PatBndme Synbax unus od un di a adeo EET Age SU P eee dae edi ue Seeker a s 406 How Location Mapping Works sseeeeeeeeeeeee hh 406 Mapping with TCL Vatiableg cuect3eske ke RERO RD e RO Ad E EESTI qd 406 Appendix B Err r and Warming Messages usas waa auwaawEeadrert ex eias a aeu Re vq
465. of the active pane E 5 Print File Print open the Print dialog Cut Edit Cut 4 cut the selected text to the clipboard Copy Edit gt Copy copy the selected text to the clipboard Paste Edit gt Paste HA paste the clipboard text Undo Edit Undo undo the last edit Redo Edit Redo redo the last undone edit Fi Edit Find find text in the active window Collapse All Edit gt Expand gt Collapse All collapse all instances in the active window Expand All Edit gt Expand gt Expand All expand all instance in the active window aoe ModelSim User s Manual v6 3g 45 May 2008 Graphical User Interface Navigating in the Main Window 46 Table 2 6 Main Window Toolbar Buttons Compile open the Compile Source Files dialog to select files for compilation Menu equivalent Compile gt Compile Command equivalents Compile All compile all files in the open project Simulate load the selected design unit or simulation configuration object Compile gt Compile All Simulate gt Start Simulation Break stop the current simulation run Simulate gt Break Environment up move up one level in the design hierarchy Environment back navigate backward to a previously selected context Environment forward navigate forward to a previously selected context r r Restart reload the design elements and reset the simulation time to z
466. ogether with the specified link instructions Although compilation and simulation switches are platform specific loading shared libraries is the same for all platforms For information on loading libraries for PLI VPI see PLI VPI file loading For DPI loading instructions see DPI File Loading Correct Linking of Shared Libraries with Bsymbolic In the examples shown throughout this appendix the Bsymbolic linker option is used with the compilation gcc or g or link Id commands to correctly resolve symbols This option instructs the linker to search for the symbol within the local shared library and bind to that symbol if it exists If the symbol is not found within the library the linker searches for the symbol within the vsimk executable and binds to that symbol if it exists When using the Bsymbolic option the linker may warn about symbol references that are not resolved within the local shared library It is safe to ignore these warnings provided the symbols are present in other shared libraries or the vsimk executable An example of such a warning would be a reference to a common API call such as vpi_printf Windows Platforms C e Microsoft Visual C 4 1 or Later cl c l lt install_dir gt modeltech include app c link dll export lt init_function gt app obj lt install_dir gt win32 mtipli lib out app dll For the Verilog PLI the lt init_function gt should be init_usertfs Alternatively if there is no init_user
467. oject directory or simply create mappings to files in other locations Step 3 Compiling the Files This checks syntax and semantics and creates the pseudo machine code ModelSim uses for simulation Step 4 Simulating a Design ModelSim User s Manual v6 3g May 2008 Projects Getting Started with Projects This specifies the design unit you want to simulate and opens a structure tab in the Workspace pane Step 1 Creating a New Project Select File gt New gt Project to create a new project This opens the Create Project dialog where you can specify a project name location and default library name You can generally leave the Default Library Name set to work The name you specify will be used to create a working library subdirectory within the Project Location This dialog also allows you to reference library settings from a selected ini file or copy them directly into the project Figure 4 1 Create Project Dialog TT x Project Name proi Project Location Ic Tutorial examples Browse Default Library Name work Copy Settings From modelsim ini Browse Copy Library Mappings Reference Library Mappings DK Cancel After selecting OK you will see a blank Project tab in the Workspace pane of the Main window Figure 4 2 Figure 4 2 Project Tab in Workspace Pane Workspace and the Add Items to the Project dialog F
468. ollowing disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Copyright c 1984 2000 S L Moshier Permission to use copy modify and distribute this software for any purpose without fee is hereby granted provided that this entire notice is included in all copies of any software which is or includes a copy or modification of this software and in all copies of the supporting documentation for such software THIS SOFTWARE IS BEING PROVIDED AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY IN PARTICULAR THE AUTHOR MAKES NO REPRESENTATION OR WARRANTY OF ANY KIND
469. ols rule groupings by specifying if necessary any closed parentheses The up and down arrows increase or decrease the number of parentheses in the field Figure 2 31 shows an example where you want to show all messages either errors or warnings that reference the 15th line of the file cells v Figure 2 31 Message Viewer Filter Dialog Box Message Viewer Filter E xj Setup Fiter Of wilt airaa iaa xf Insensitive chen 2 O Gm severity w Contains w Case Insensitive w fvarniny p 2 Hoe eae e vhs 4 O fio v irieme w eoncains wiese Sensitive vifensy fp ii ok cancel Apply When you select OK or Apply the Message Viewer is updated to contain only those messages that meet the criteria defined in the Message Viewer Filter dialog box Also when selecting OK or Apply the transcript pane will contain an echo of the messages setfilter command where the argument is a Tcl definition of the filter You can then cut paste this command for reuse at another time Watch Pane The Watch pane shows values for signals and variables at the current simulation time allows you to explore the hierarchy of object oriented designs Unlike the Objects or Locals pane the 80 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Watch Pane Watch pane allows you to view any signal or variable in the design regardless of the current context You can view the following objects in the Watch pane
470. on configurations 121 folders in 123 grouping files in 117 loading a design 118 MODELSIM environment variable 366 open and existing 120 overview 111 protect source code 97 protect compiler directive 101 protect pragmas encrypting IP code 97 protected types 159 Public encryption keys 99 Q quick reference table of simulation tasks 24 Quiet ini file variable 373 377 R race condition problems with event order 185 Radix change in Watch pane 81 radix List window 259 SystemVerilog types 87 253 user defined 38 definition body 38 Wave window 253 range checking 140 readers and drivers 278 real type converting to time 157 reconstruct RTL level design busses 230 RECOVERY matching to Verilog 322 RECREM matching to Verilog 322 redirecting messages TranscriptFile 392 refreshing library images 136 regions virtual 232 484 JKLMNOPQRSTUVWXYZ registers values of displaying in Objects window 62 saving as binary log file 219 waveforms viewing 84 REMOVAL matching to Verilog 322 report simulator control 363 simulator state 363 RequireConfigForAllDefaultBinding variable 3T resolution returning as a real 155 verilog simulation 182 VHDL simulation 144 Resolution ini file variable 390 resolution simulator state variable 404 resource libraries specifying 135 restart command defaults 402 toolbar button 46 94 results saving simulations 219 return to
471. on is implicitly declared so it can be used with files of any type not just files of type TEXT Using Alternative Input Output Files You can use the TextIO package to read and write to your own files To do this just declare an input or output file of type TEXT For example for an input file The VHDL 87 declaration is file myinput TEXT is in pathname dat The VHDL 93 declaration is file myinput TEXT open read mode is pathname dat Then include the identifier for this file myinput in this example in the READLINE or WRITELINE procedure call Flushing the TEXTIO Buffer Flushing of the TEXTIO buffer is controlled by the UnbufferedOutput variable in the modelsim ini file 152 ModelSim User s Manual v6 3g May 2008 VHDL Simulation VITAL Specification and Source Code Providing Stimulus You can stimulate and test a design by reading vectors from a file using them to drive values onto signals and testing the results A VHDL test bench has been included with the ModelSim install files as an example Check for this file lt install_dir gt modeltech examples misc stimulus vhd VITAL Specification and Source Code VITAL ASIC Modeling Specification The IEEE 1076 4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers Inc IEEE Customer Service 445 Hoes Lane Piscataway NJ 08854 1331 Tel 732 981 0060 Fax 732 981 1721 home page
472. ons 0 0 e ee eee eee eee ee 385 Table A 3 MessageFormat Variable Accepted Values 0 0 0 0 00 ee ee eee 386 Table B 1 Severity Level Types 664v het PER RPerE RO rea d er RI WE AG 407 Table B3 EXC Dd6S sos panes eit euia PRESE REEENEEL EE REESE ELE EE EE RE 410 ModelSim User s Manual v6 3g 21 May 2008 List of Tables Table C 1 VPI Compatibility Considerations 0 0 0 cece eee eee ee 418 Table C 2 vsim Arguments for DPI Application 0 0 00 c eee eee eee 433 Table C 3 Supported VHDL Objects 0 0 0 0 eee eect teens 439 Table C4 Supported ACC Routines 36405 sce cuss eer Sato eee sexo ese EE ES 441 Table C 5 Supported TF Routines 225 oisue a RR Rh RR RE RR 443 Table C 6 Values Tor action Argument 3d rex sek T PER RET UAR DES RR Y ERES 446 Table D 1 Command History Shortcuts 0 0 0 ccc eee ee 449 Table D 2 Mouse Shortcuts rac ER E REReR RA R RF WeEDOIE ER e ERI KA RUE 450 Table D 3 Keyboard Shortcuts 2222 sssre ike ERGO A ERLERU aa RE RORIS dp qo d d 450 Table D 4 List Window Keyboard Shortcuts lllleeeeeeeeee 453 Table D 5 Wave Window Mouse Shortcuts 0 eee eee ee eee 454 Table D 6 Wave Window Keyboard Shortcuts llllllllleleleeesn 454 Table E 1 Predefined GUI Layouts 54243 4 3 RR CRPETUH RERO ERR Rd tX ANLASS 457 Table F 1 Files Accessed During Startup 0 0 c eee eee nee 467 Table F 2 Environment Variables Acces
473. ons which are brought into the simulator using the sv_lib argument Use Model for Locked Work Libraries You may want to create the work library as a locked entity which enables multiple users to simultaneously share the design library at runtime The vsim switch locklib allows you to create a library that prevents compilers from recompiling or refreshing a target library To prevent vsim from creating objects in the library at runtime the vsim dpiexportobj flow is available on all platforms Use this flow after compilation but before you start simulation using the design library An example command sequence would be vlib locklib work vlog dpiheader dpiheader h test sv gcc shared Bsymbolic o test so test c vsim c dpiexportobj work dpi exportwrapper top The work dpi exportwrapper argument provides a basename for the shared object ModelSim User s Manual v6 3g 427 May 2008 Verilog PLI VPI DPI DPI Use Flow The library is now ready for simulation by multiple simultaneous users as follows vsim top sv_lib test At runtime vsim automatically checks to see if the file work _dpi exportwrapper so is up to date with respect to its C source code If it is out of date an error message is issued and elaboration stops Making Verilog Function Calls from non DPI C Models Working in certain FLI or PLI C applications you might want to interact with the simulator by directly calling Verilog DPI export functions Su
474. ontal Note that you can also move the tabs within a tab group by dragging them with the middle mouse button Navigating in the Main Window The Main window can contain of a number of panes and sub windows that display various types of information about your design simulation or debugging session Here are a few important points to keep in mind about the Main window interface e Windows panes can be resized moved zoomed undocked etc and the changes are persistent ModelSim User s Manual v6 3g 43 May 2008 Graphical User Interface Navigating in the Main Window You have a number of options for re sizing re positioning undocking redocking and generally modifying the physical characteristics of windows and panes Windows and panes can be undocked from the main window by pressing the Undock button in the header or by using the view undock lt window_name gt command For example view undock objects will undock the Objects window The default docked or undocked status of each window or pane can be set with the PrefMain ViewUnDocked window name preference variable When you exit ModelSim the current layout is saved so that it appears the same the next time you invoke the tool e Menus are context sensitive The menu items that are available and how certain menu items behave depend on which pane or window is active For example if the sim tab in the Workspace is active and you choose Edit from the menu bar t
475. or one that is out of view by double clicking the cursor name Name a cursor by right clicking the cursor name and entering a new value Press lt Enter gt on your keyboard after you have typed the new name Move a locked cursor by holding down the lt shift gt key and then clicking and dragging the cursor Move a cursor to a particular time by right clicking the cursor value and typing the value to which you want to scroll Press Enter on your keyboard after you have typed the new value Understanding Cursor Behavior The following list describes how cursors behave when you click in various panes of the Wave window 242 If you click in the waveform pane the closest unlocked cursor to the mouse position is selected and then moved to the mouse position Clicking in a horizontal track in the cursor pane selects that cursor and moves it to the mouse position Cursors snap to a waveform edge if you click or drag a cursor along the selected waveform to within ten pixels of a waveform edge You can set the snap distance in the Display tab of the Window Preferences dialog Select Tools gt Options gt Wave Preferences when the Wave window is docked in the Main window MDI frame Select ModelSim User s Manual v6 3g May 2008 Waveform Analysis Setting Time Markers in the List Window Tools gt Window Preferences when the Wave window is a stand alone undocked window e You can position a cursor without snapping by drag
476. or PLI VPI DPI and a link line for Visual C would be link dll export lt init_function gt app obj lt objname gt obj lt install_dir gt modeltech win32 mtipli lib out app dll Compiling and Linking C Applications for PLI VPI DPI ModelSim does not have direct support for any language other than standard C however C code can be loaded and executed under certain conditions Since ModelSim s PLI VPI DPI functions have a standard C prototype you must prevent the C compiler from mangling the PLI VPI DPI function names This can be accomplished by using the following type of extern extern C lt PLI VPI DPI application function prototypes gt The header files veriuser h acc_user h and vpi_user h svdpi h and dpiheader h already include this type of extern You must also put the PLI VPI DPI shared library entry point veriusertfs init usertfs or vlog startup routines inside of this type of extern You must also place an extern C declaration immediately before the body of every import function in your C source code for example extern C int myimport int i vpi_printf The value of i is d n i The following platform specific instructions show you how to compile and link your PLI VPI DPI C applications so that they can be loaded by ModelSim Although compilation and simulation switches are platform specific loading shared libraries is the same for all platforms For information on
477. or otherwise modify the file This variable may contain a relative pathname in which case the file will be relative to the working directory at the time the tool is started MODELSIM_TCL The toolset uses the MODELSIM_TCL environment variable to look for an optional graphical preference file The argument can be a colon separated UNIX or semi colon separated Windows list of file paths MTI COSIM TRACE The MTI COSIM TRACE environment variable creates an mti trace cosim file containing debugging information about FLI PLI VPI function calls You should set this variable to any value before invoking the simulator MTI TF LIMIT The MTI TF LIMIT environment variable limits the size of the VSOUT temp file generated by the toolset s kernel Set the argument of this variable to the size of k bytes The environment variable TMPDIR controls the location of this file while STDOUT controls the name The default setting is 10 and a value of 0 specifies that there is no limit This variable does not control the size of the transcript file MTI RELEASE ON SUSPEND The MTI RELEASE ON SUSPEND environment variable allows you to turn off or modify the delay for the functionality of releasing all licenses when the tool is suspended The default setting is 10 in seconds which means that if you do not set this variable your licenses will be released 10 seconds after your run is suspended If you set this environment variable with an 366 ModelS
478. ormance cancelling scheduled events 167 PERIOD matching to Verilog 323 platforms supported See Installation Guide PLI loading shared objects with global symbol visibility 434 specifying which apps to load 420 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ Veriuser entry 420 PLI VPI 217 tracing 445 PLI VPI DPI 417 registering DPlapplications 422 specifying the DPI file to load 433 PLIOBJS environment variable 367 420 PORT matching to input ports 320 Port driver data capturing 339 Postscript saving a waveform in 262 saving the Dataflow display in 287 post sim debug flow 276 pragmas protecting IP code 97 precedence of variables 402 precision in timescale directive 182 simulator resolution 182 preference variables ini files located in 369 editing 461 saving 461 preferences saving 461 Wave window display 250 PrefMain ShowFilePane preference variable 41 PrefMemory ExpandPackedMem variable 60 primitives symbols in Dataflow window 284 printing Dataflow window display 287 waveforms in the Wave window 262 printing simulation stats 390 Programming Language Interface 217 417 project tab information in 120 sorting 121 projects 111 accessing from the command line 128 adding files to 114 benefits 111 close 120 compile order 116 483 ABCDEFGH I changing 116 compiler properties in 125 compiling files 115 creating 113 creating simulati
479. ort option for each DPI imported task or function in your linking command line You can use the isymfile argument from the vlog command to obtain a complete list of all imported tasks functions expected by ModelSim As an alternative to specifying one export option for each imported task or function you can make use of the __declspec dllexport macro supported by Visual C You can place this macro before every DPI import task or function declaration in your C source All the marked functions will be available for use by vsim as DPI import tasks and functions DPI Flow for Exported Tasks and Functions on Windows Platforms Since the Windows platform lacks the necessary runtime linking capabilities you must perform an additional manual step in order to prepare shared objects containing calls to exported System Verilog tasks or functions You need to invoke a special run of vsim The command is as follows vsim top du list dpiexportobj objname other args The dpiexportobj generates an object file lt objname gt obj that contains glue code for exported tasks and functions You must add that object file to the link line for your dll listed after the other object files For example a link line for MinGW would be gcc shared Bsymbolic o app dll app obj lt objname gt obj L lt install_dir gt modeltech win32 Imtipli 430 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI Compiling and Linking C Applications f
480. ost useful Select one or more objects and then select View gt Signal Properties from the List window menu bar when the window is undocked Changing Radix base for the List Window One common adjustment you can make to the List window display is to change the radix base of an object To do this choose View gt Signal Properties from the main menu which displays the List Signal Properties dialog box Figure 9 29 shows the list of radix types you can select in this dialog box ModelSim User s Manual v6 3g 259 May 2008 Waveform Analysis Formatting the List Window Figure 9 29 List Signal Properties Dialog List Signal Properties Signal test_counter count Display Name Radix C Symbolic The default radix type is symbolic which means that for an enumerated type the window lists the actual values of the enumerated type of that object For the other radix types binary octal decimal unsigned hexadecimal ASCII time the object value is converted to an appropriate representation in that radix Changing the radix can make it easier to view information in the List window Compare the image below with decimal values with the image in the section List Window Overview with symbolic values 260 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Saving the Window Format Figure 9 30 Changing the Radix in the List Window IDi x File Edit View Add Tools Window MERETET psc test sm rst
481. ouble dollar sign Setting Environment Variables Before compiling or simulating several environment variables may be set to provide the functions described below The variables are set through the System control panel on Windows 2000 and XP machines For UNIX the variables are typically found in the ogin script The LM_LICENSE_FILE variable is required all others are optional DOPATH The toolset uses the DOPATH environment variable to search for DO files macros DOPATH consists of a colon separated semi colon for Windows list of paths to directories You can override this environment variable with the DOPATH Tcl preference variable The DOPATH environment variable isn t accessible when you invoke vsim from a UNIX shell or from a Windows command prompt It is accessible once ModelSim or vsim is invoked If you need to invoke from a shell or command line and use the DOPATH environment variable use the following syntax vsim do do lt dofile_name gt design unit EDITOR The EDITOR environment variable specifies the editor to invoke with the edit command HOME The toolset uses the HOME environment variable to look for an optional graphical preference file and optional location map file Refer to Simulator Control Variables for additional information HOME OIN The HOME OIN environment variable identifies the location of the 0 In executables directory Refer to the 0 In documentation for more information 364 M
482. ouse button to move the design 2 hold down the lt Ctrl gt key and drag with the middle mouse button to move the design ModelSim User s Manual v6 3g 291 May 2008 Debugging with the Dataflow Window Dataflow Window Graphic Interface Reference 292 ModelSim User s Manual v6 3g May 2008 Chapter 11 Signal Spy The Verilog language allows access to any signal from any other hierarchical block without having to route it via the interface This means you can use hierarchical notation to either assign or determine the value of a signal in the design hierarchy from a testbench This capability fails when a Verilog testbench attempts to reference a signal in a VHDL block or reference a signal in a Verilog block through a VHDL level of hierarchy This limitation exists because VHDL does not allow hierarchical notation In order to reference internal hierarchical signals you have to resort to defining signals in a global package and then utilize those signals in the hierarchical blocks in question But this requires that you keep making changes depending on the signals that you want to reference The Signal Spy procedures and system tasks overcome the aforementioned limitations They allow you to monitor spy drive force or release hierarchical objects in a VHDL or mixed design The VHDL procedures are provided via the Util Package within the modelsim lib library To access the procedures you would add lines like the following to your V
483. ously cut or copied Edit Paste object s E Undo undo the last action Edit Undo Y e Redo redo the last undone action Edit Redo Find search for an instance or signal Edit Find Trace input net to event move the next event Trace Trace next event cursor to the next input event driving the selected output Trace Set jump to the source of the selected Trace Trace event set input event ModelSim User s Manual v6 3g 51 May 2008 Graphical User Interface Dataflow Window Table 2 7 Dataflow Window Toolbar Button Menu equivalent Trace Reset return the next event cursor to the Trace gt Trace event reset selected output Trace net to driver of X step back to the last Trace gt TraceX driver of an unknown value Expand net to all drivers display driver s of Navigate gt Expand net to drivers the selected signal net or register x 8 e Expand net to all drivers and readers display Navigate Expand net driver s and reader s of the selected signal net or register Expand net to all readers display reader s of Navigate gt Expand net to readers the selected signal net or register Erase highlight clear the green highlighting Edit Erase highlight which identifies the path you ve traversed through the design Erase all clear the window Edit Erase all Regenerate clear and redraw the
484. override the value that was set by init signal spy By default this command uses a backslash V as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file Call only once The init signal spy call creates a persistent relationship between the source and destination signals Hence you need to call init signal spy once for a particular pair of signals Once init signal spy is called any change on the source signal will mirror on the destination signal until the end of the simulation unless the control state is set The control state determines whether the mirroring of values can be enabled disabled and what the initial state is Subsequent control of whether the mirroring of values is enabled disabled is handled by the enable signal spy and disable signal spy calls For VHDL procedures we recommend that you place all init signal spy calls in a VHDL process You need to code the VHDL process correctly so that it is executed only once The VHDL process should not be sensitive to any signals and should contain only init signal spy calls and a simple wait statement The process will execute once and then wait forever which is the desired behavior See the example below For Verilog tasks we recommend that you place all Sinit signal spy tasks in a Verilog initial block See the example below VHDL Syntax init signal spy src object dest object lt verbose gt control state
485. p VSIM 1 vcd dumpports file proc vcd top p VSIM 2 gt ved dumpports file cache vcd top c VSIM 3 vcd dumpports file memory vcd top m VSIM 4 run 1000 VSIM 5 gt quit f Next rerun each module separately using the captured VCD stimulus 96 vsim vcdstim proc vcd proc do add wave run 1000 VSIM 1 gt quit f 96 vsim vcdstim cache vcd cache do add wave run 1000 VSIM 1 gt quit f 96 vsim vcdstim memory vcd memory do add wave run 1000 VSIM 1 gt quit f Replacing Instances with Output Values from a VCD File Replacing instances with output values from a VCD file lets you simulate without the instance s source or even the compiled object The general procedure includes two steps 1 Create VCD files for one or more instances in your design using the vcd dumpports command If necessary use the vcdstim switch to handle port order problems see below 2 Re simulate your design using the vcdstim instance filename argument to vsim Note that this works only with VCD files that were created by a ModelSim simulation Example 13 4 Replacing Instances In the following example the three instances top p top c and top m are replaced in simulation by the output values found in the corresponding VCD files First create VCD files for all instances you want to replace vcd dumpports vcdstim file proc vcd top p vcd dumpports vcdstim file cache vcd top c vcd dumpports vcdstim
486. pe If you do not include R the tool automatically logs the instance or region in which the messagelog is called ModelSim User s Manual v6 3g 209 May 2008 Verilog and SystemVerilog Simulation System Tasks and Functions If you do include R F or L or a combination of any two of these the tool does not automatically log values for the undefined specifier s e S Severity Level A case insensitive string argument enclosed in quotes that is one of the following Note This is the default if you do not specify S Warning Error Fatal Info The error message system recognizes this as a Note Message The error message system recognizes this as a Note e 95 V Verbosity Rating An integer argument where the default is zero 0 The verbosity rating allows you to specify a field you can use to sort or filter messages in the Message Viewer In most cases you specify that this attribute is not printed using the tilde character Description 210 Non printing attributes You can specify that an attribute value is not to be printed in the transcripted message by placing the tilde character after the percent character for example Smessagelog S Do not print the Severity Level Warning However the value of S is logged for use in the Message Viewer Logging of simulation time For each call to messagelog the simulation time is logged however the simulatio
487. pecial interpretation of the expression L work When you specify L work first in the search library arguments you are directing vsim to search for the instantiated module or UDP in the library that contains the module that does the instantiation In the example above you would invoke vsim as follows vsim L work L lib1 L lib2 top SystemVerilog Multi File Compilation Issues Declarations in Compilation Unit Scope System Verilog allows the declaration of types variables functions tasks and other constructs in compilation unit scope unit The visibility of declarations in unit scope does not extend outside the current compilation unit Thus it is important to understand how compilation units are defined by the tool during compilation By default vlog operates in Single File Compilation Unit mode SFCU This means the visibility of declarations in unit scope terminates at the end of each source file Visibility does not carry forward from one file to another except when a module interface or package declaration begins in one file and ends in another file In that case the compilation unit spans from the file containing the beginning of the declaration to the file containing the end of the declaration ModelSim User s Manual v6 3g 175 May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files vlog also supports a non default behavior called Multi File Compilation Unit mode MFCU In MFCU mode vlogcompiles all
488. pen for write e Value Range 0 buffered 1 unbuffered e Default 0 UserTimeUnit This variable specifies the multiplier for simulation time units and the default time units for commands such as force and run Generally you should set this variable to default in which case it takes the value of the Resolution variable Note LL The value you specify for UserTimeUnit does not affect the display in the Wave window To change the time units for the X axis in the Wave window choose Wave Wave Preferences Grid amp Timeline from the main menu and specify a value for Grid Period e Value Range fs ps ns us ms sec or default Default default 392 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables Veriuser This variable specifies a list of dynamically loadable objects for Verilog PLI VPI applications e Value Range one or more valid shared object names e Default commented out WarnConstantChange This variable controls whether a warning is issued when the change command changes the value of a VHDL constant or generic e Value Range 0 1 e Default on 1 WaveSignalNameWidth This variable controls the number of visible hierarchical regions of a signal name shown in the Wave Window e Value Range 0 display full name positive integer display corresponding level of hierarchy e Default 0 WLFCacheSize This variable sets the number of megabytes for t
489. performed on the result of the nested script ModelSim User s Manual v6 3g May 2008 Tcl and Macros DO Files Tcl Command Syntax 11 Substitutions do not affect the word boundaries of a command For example during variable substitution the entire value of the variable becomes part of a single word even if the variable s value contains spaces If Command Syntax The Tcl if command executes scripts conditionally Note that in the syntax below the question mark indicates an optional argument Syntax if expr1 then body elseif expr2 then body2 elseif else bodyN Description The if command evaluates expr as an expression The value of the expression must be a boolean a numeric value where 0 is false and anything else is true or a string value such as true or yes for true and false or no for false if it is true then body is executed by passing it to the Tcl interpreter Otherwise expr2 is evaluated as an expression and if it is true then body2 is executed and so on If none of the expressions evaluates to true then bodyN is executed The then and else arguments are optional noise words to make the command easier to read There may be any number of elseif clauses including zero BodyN may also be omitted as long as else is omitted too The return value from the command is the result of the body script that was executed or an empty string if none of the expressions was non zero and there was no bodyN Command Subs
490. pib jtop mydut assert dut pic jtop mydut assert dut pid thanirweiikisccark dik nia 999799999 gt Cursor 1 M gt El o When the Wave window is docked in the Main window all menus and icons that were in the undocked Wave window move into the Main window menu bar and toolbar The Wave window is divided into a number of window panes The Object Pathnames Pane displays object paths Figure 9 3 Wave Window Object Pathnames Pane jtop mydut assert jtop mydut assert 1 Itop mydut assert 2 jtop mydut assert 3 jtop mydut assert 4 jtop mydut assert dut pia jtop mydut assert dut piaa jtop mydut assert dut pib jtop mydut assert dut pic jtop mydut assert dut pid jtop mydut assert dut pie jtop mydut assert dut pif jtop mydut assert dut pig Jton mvdut assert dut oth X 5 5 5 5 5 LI ModelSim User s Manual v6 3g 235 May 2008 Waveform Analysis Wave Window Overview The Object Values Pane displays the value of each object in the pathnames pane at the time of the selected cursor Figure 9 4 Wave Window Object Values Pane 0000100000 XXXXXXXXXXX The Waveforms Pane displays the object waveforms over the time of the simulation Figure 9 5 Wave Window Waveforms Pane 0000100000 0000110000 aaa ANL a a A The Cursor Pane displays cursor names cursor values and the cursor locations on the timeline This pane also includes a toolbox that giv
491. pkg avm named comp m name scb af fifo m name request _fifo m parent null m parent null m children m children mrmzi m m1 L s named object repository 1 s named object repository 1 s orphans 1 L s orphans 1 super Javm pkg tlm FiFo tlm FiFo 2 mir analysis export 1 m size 1 put export 1 blocking put export 1 nonblocking put export 1 Two Ref handles that refer to the same object will point to the same Watch pane box even if the name used to reach the object is different This means circular references will be draw as circular in the Watch pane Selecting a line item in the Watch pane adds the item s full name to the global selection This allows you to past the full name in the Transcript by simply clicking the middle mouse button or other external application that accepts text from the global selection Adding Objects to the Watch Pane To add objects to the Watch pane drag and drop objects from the Structure tab in the Workspace or from any of the following panes List Locals Objects Source and Wave Alternatively you can use the add watch command to add objects to the Watch pane Expanding Objects to Show Individual Bits If you add an array or record to the Watch pane you can view individual bit values by double clicking the array or record As shown in Figure 2 3
492. point dialog Figure 9 36 opens allowing you to modify the breakpoint Figure 9 36 Signal Breakpoint Dialog Signal Breakpoint x Breakpoint Label sim test_counter reset Breakpoint Condition sim test_counter reset Breakpoint Commands echo Break on sim test_counter reset stop ModelSim User s Manual v6 3g 271 May 2008 Waveform Analysis Creating and Managing Breakpoints File Line Breakpoints File line breakpoints are set on executable lines in your source files When the line is hit the simulator stops and the Source window opens to show the line with the breakpoint You can change this behavior by editing the PrefSource OpenOnBreak variable See Simulator GUI Preferences for details on setting preference variables Setting File Line Breakpoints Using the bb Command Use the bp command to set a file line breakpoint from the VSIM gt prompt For example bp top vhd 147 sets a breakpoint in the source file top vhd at line 147 Setting File Line Breakpoints Using the GUI File line breakpoints are most easily set using your mouse in the Source Window Position your mouse cursor in the BP column next to a red line number which indicates an executable line and click the left mouse button A red ball denoting a breakpoint will appear Figure 9 37 Figure 9 37 Breakpoints in the Source Window hi C Tutorialfexamples tutorials verilog basicSimulation counter v 27 for i 4 bO carry
493. pplied to the wrong instance Warning vsim SDF 3432 myasic sdf Ignoring subsequent missing instances from this file After annotation is done the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance Warning vsim SDF 3440 myasic sdf Failed to find any of the 358 instances from this file Warning vsim SDF 3442 myasic sdf Try instance testbench dut It contains all instance paths from this file The simulator recommends an instance only if the file was applied to the top level and a qualifying instance is found one level down Also see Resolving Errors for specific VHDL VITAL SDF troubleshooting 328 ModelSim User s Manual v6 3g May 2008 Chapter 13 Value Change Dump VCD Files This chapter describes how to use VCD files in ModelSim The VCD file format is specified in the IEEE 1364 standard It is an ASCII file containing header information variable definitions and variable value changes VCD is in common use for Verilog designs and is controlled by VCD system task calls in the Verilog source code ModelSim provides command equivalents for these system tasks and extends VCD support to SystemC and VHDL designs The ModelSim commands can be used on VHDL Verilog SystemC or mixed designs If you need vendor specific ASIC design flow documentation that incorporates VCD please contact your ASIC vendor Crea
494. ppressing Warning Messages 1 unbound component 2 process without a wait statement 3 null range 4 no space in time literal 5 multiple drivers on unresolved signal 6 VITAL compliance checks VitalChecks also works 7 VITAL optimization messages 8 lint checks 9 signal value dependency at elaboration 10 VHDL 1993 constructs in VHDL 1987 code 13 constructs that coverage can t handle 14 locally static error deferred until simulation run These numbers are unrelated to vcom arguments that are specified by numbers such as vcom 87 which disables support for VHDL 1993 and 2002 Suppressing VLOG Warning Messages As with the vcom command you can use the nowarn category number argument with the vlog command to suppress a specific warning message The warning message category numbers for vlog are 12 non LRM compliance in order to match Cadence behavior 13 constructs that coverage can t handle Or you can use the nowarn lt CODE gt argument with the vlog command to suppress a specific warning message Warnings that can be disabled include the lt CODE gt name in square brackets in the warning message For example vlog nowarnDECAY suppresses decay warning messages Suppressing VSIM Warning Messages Use the nowarn lt CODE gt argument to vsim to suppress a specific warning message Warnings that can be disabled include the CODE name in square brackets in the warning messag
495. precated Features Commands and Variables 0 0 0 33 Chapter 2 Graphical User Interface sic i6 isi050 564060008 62040966 040600045 004060 EUR ERA TE 35 Design Object Icons and Their Meaning 0 cece eee eens 37 Deus MOMS nut ber eon eee eo poate POE ESee ee See oe Pee eee ee SER ES 37 User Defined Radibes v2 lt e us dunce ese ee kiea keun Ti Tean EARE Ed ERG dus 38 Main WIDUOW 242 c2 per ete P qua heo rata nn ene REC A Aere D ua a Ra qaad 40 WOKS pace oet onse ep ee oxmu ie SR edu t nad Fg Gees dd oed pedit d eei a di gehts 41 Multiple Document Interface MDI Frame eseeeeeeee ee 42 Organizing Windows with Tab Groups 20 00 cee eee n 42 Navigating in the Main Window 0 cee eee eee eens 43 Main Window Status Dat soa 44464 y CERA REA eneu dete eeodeee ean o erra D 44 Main Window Toolbar 0 0 0 cece eee m 45 PROCESS WANK ug oucacy 3369 hh eS ho cab COR Ka aper Nos AO Soa ae Ra 47 Displaying the Process Window 00 cece cette eee eens 48 Viewing Data in the Process Window 0 0 cece eee eee 48 Done Indicates that the process has executed a VHDL wait statement without a time out or a sensitivity list The process will not restart during the current simulation run Call Stack Pale o1 sre oleae eir ex bie ob et de an EE aee ode ea bande oe dee Mme 49 Dataflow Window 0 0 ccc eee eee ee eee re 50 Dataflow Window Toolbar 0 0 0 0
496. pression evaluates to true This setup behaves much like a hardware signal analyzer that starts recording data on a specified setup of address bits and clock edges Here are some points about gating expressions e Gating expressions affect the display of data but not acquisition of the data e The expression is evaluated when the List window would normally have displayed a row of data given the other trigger settings e The duration determines for how long triggering stays enabled after the gating expression returns to false 0 The default of O duration will enable triggering only while the expression is true 1 The duration is expressed in x number of default timescale units e Gating is level sensitive rather than edge triggered Trigger Gating Example Using the Expression Builder This example shows how to create a gating expression with the ModelSim Expression Builder Here is the procedure 1 Select Tools gt Window Preferences from the List window menu bar when the window is undocked and select the Triggers tab 2 Click the Use Expression Builder button Figure 9 34 Trigger Gating Using Expression Builder Expression Builder Expression Builder Insert Signal I 31 event Tising faling 8 amp I ano orn o 1 gt gt _ lt xoR SLL xd x ep rep pes sei spa oH ch Clear Save Test OK Cancel ModelSim User s Manual v6 3g 267 May 20
497. r you can also look at waveform data in a textual format in the List window To analyze waveforms in ModelSim follow these steps 1 PA 3 Compile your files Load your design Add objects to the Wave or List window add wave object name add list object name Run the design Objects You Can View The list below identifies the types of objects can be viewed in the Wave or List window VHDL objects indicated by dark blue diamond in the Wave window signals aliases process variables and shared variables Verilog objects indicated by light blue diamond in the Wave window nets registers variables and named events Virtual objects indicated by an orange diamond in the Wave window virtual signals buses and functions see Virtual Objects for more information Wave Window Overview The Wave window opens by default in the Main window as shown Figure 9 1 The window can be undocked from the main window by clicking the Undock button in the window header or by using the view undock wave command Setting the PrefMain ViewUnDocked wave preference variable will change the default behavior so that the Wave window will open undocked each time you start ModelSim ModelSim User s Manual v6 3g 233 May 2008 Waveform Analysis Wave Window Overview Figure 9 1 Undocking the Wave Window Undock button dl Fie Edt Wew Compie Simulate Add Wave Tools Layout Window Heb OSDA RAAE nf OAL LE
498. r a group of files Note Any changes you make to the compile properties outside of the project whether from the command line the GUI or the modelsim ini file will not affect the properties of files already in the project ModelSim User s Manual v6 3g 125 May 2008 Projects Specifying File Properties and Project Settings To customize specific files select the file s in the Project tab right click on the file names and select Properties The resulting Project Compiler Settings dialog Figure 4 18 varies depending on the number and type of files you have selected If you select a single VHDL or Verilog file you will see the General tab Coverage tab and the VHDL or Verilog tab respectively On the General tab you will see file properties such as Type Location and Size If you select multiple files the file properties on the General tab are not listed Finally if you select both a VHDL file and a Verilog file you will see all tabs but no file information on the General tab Figure 4 18 Specifying File Properties xi General Verilog Coverage BE General Settings DoNot Compile Compile to library work vi Place in Folder Top Level vi File Properties File sm v Location C examples coverage verilog sm v MS DOS name C examples coverage verilog sm Type Verilog Change T ype Size 2459 2KB Modification Time Thu Nov 04 7 35 06 PM Pacific Standard Time Last Compile Source has not
499. r instantiated objects This behaves similarly to a LIBRARY USE clause in VHDL You must ensure the correct mappings are set up if the library does not exist in the current working directory The compile uselibs argument does not affect this usage of uselib For example the following directive uselib dir h vendorA libext v is equivalent to the following command line arguments y h vendorA libextt v Since the uselib directives are embedded in the Verilog source code there is more flexibility in defining the source libraries for the instantiations in the design The appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved completely overriding any previous uselib directives An important feature of uselib is to allow a design to reference multiple modules having the same name therefore independent compilation of the source libraries referenced by the uselib directives is required Each source library should be compiled into its own object library The compilation of the code containing the uselib directives only records which object libraries to search for each module instantiation when the design is loaded by the simulator Because the uselib directive is intended to reference source libraries the simulator must infer the object libraries from the library references The rule is to assume an object library named work in the directory defined in the library refere
500. r it has been compiled with vcom The simulator may then be invoked with the name of the configuration or entity architecture pair Note This section discusses simulation from the UNIX or Windows DOS command line You can also use a project to simulate see Getting Started with Projects or the Start Simulation dialog box open with Simulate gt Start Simulation menu selection This example invokes vsim on the entity my_asic and the architecture structure vsim my_asic structure vsim is capable of annotating a design using VITAL compliant models with timing data from an SDF file You can specify the min typ max delay by invoking vsim with the sdfmin sdftyp or sdfmax options Using the SDF file f7 sdf in the current work directory the following invocation of vsim annotates maximum timing values for the design unit my_asic vsim sdfmax my_asic f1 sdf my_asic By default the timing checks within VITAL models are enabled They can be disabled with the notimingchecks option For example vsim notimingchecks topmod If notimingchecks is set on the vsim command line the generic TimingChecksOn is set to FALSE for all VHDL Vital models with the Vital levelO or Vital_levell attribute Setting this generic to FALSE disables the actual calls to the timing checks along with anything else that is present in the model s timing check block In addition if these models use the generic TimingChecksOn to control behavior beyond timing checks
501. r iteration entity This variable returns the name of the top level VHDL entity or Verilog module currently being simulated library This variable returns the library name for the current region MacroNestingLevel This variable returns the current depth of macro call nesting n This variable represents a macro parameter where n can be an integer in the range 1 9 ModelSim User s Manual v6 3g 403 May 2008 Simulator Variables Simulator State Variables Now This variable always returns the current simulation time with time units e g 110 000 ns Note will return a comma between thousands now This variable when time resolution is a unary unit i e Ins Ips 1fs returns the current simulation time without time units e g 100000 when time resolution is a multiple of the unary unit i e 1Ons 100ps 10fs returns the current simulation time with time units e g 110000 ns Note will not return comma between thousands resolution This variable returns the current simulation time resolution Referencing Simulator State Variables Variable values may be referenced in simulator commands by preceding the variable name with a dollar sign For example to use the now and resolution variables in an echo command type echo The time is now resolution Depending on the current simulator state this command could result in The time is 12390 ps 10ps If you do not want the dollar sign to denote a sim
502. r object green vertical highlight e Moving the active marker List window markers behave the same as Wave window cursors There is one active marker which is where you click along with inactive markers generated by the Add Marker command Markers move based on where you click The closest marker either active or inactive will become the active marker and the others remain inactive e Adding a marker You can add an additional marker to the List window by right clicking at a location in the right hand side and selecting Add Marker e Deleting a marker You can delete a marker by right clicking in the List window and selecting Delete Marker The marker closest to where you clicked is the marker that will be deleted Menu Items The following menu items are available from the right click menu within the List window e Examine Displays the value of the signal over which you used the right mouse button at the time selected with the Active Marker e Add Marker Adds a marker at the location of the Active Marker e Delete Marker Deletes the closest marker to your mouse location The following menu items are available when the List window is active e List gt Add Marker Adds a marker at the location of the Active Marker e List gt Delete Marker Deletes the closest marker to your mouse location e List gt Combine Signals Combines the signals you ve selected in the List window e List gt List Pre
503. r the location of the library to be imported below Import Library Pathname aooo lt Previous Next gt Cancel Follow the instructions in the wizard to complete the import Protecting Source Code The Protecting Your Source Code chapter provides details about protecting your internal model data This allows a model supplier to provide pre compiled libraries without providing source code and without revealing internal model variables and structure 138 ModelSim User s Manual v6 3g May 2008 Chapter 6 VHDL Simulation This chapter describes how to compile optimize and simulate VHDL designs in ModelSim It also discusses using the TextIO package with ModelSim ModelSim s implementation of the VITAL VHDL Initiative Towards ASIC Libraries specification for ASIC modeling and ModelSim s special built in utilities package The TextIO package is defined within the VHDL Language Reference Manual IEEE Std 1076 it allows human readable text input from a declared source within a VHDL file during simulation Basic VHDL Flow Simulating VHDL designs with ModelSim includes four general steps 1 Compile your VHDL code into one or more libraries using the vcom command See Compiling VHDL Files for details 2 Load your design with the vsim command See Simulating VHDL Designs for details 3 Run and debug your design Compiling VHDL Files Creating a Design Library for VHDL Before you can compile
504. rMyTfs void S vpi systf data systf data vpiHandle systf handle systf_data type vpiSysTask systf_data sysfunctype vpiSysTask systf_data tfname Shello systf_data calltf hello systf_data compiletf 0 systf_data sizetf 0 systf_data user_data 0 systf_handle vpi register systf amp systf data vpi free object systf handle void vlog startup routines O RegisterMyTfs 0 hello v module hello initial Shello endmodule Compile the VPI code for the Solaris operating system oe gcc c I install dir include hello c gcc shared Bsymbolic o hello sl hello o ile the Verilog code vlib work vlog hello v Simulate the design oe Com oe oe TO ModelSim User s Manual v6 3g May 2008 435 Verilog PLI VPI DPI DPI Example vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 run all Hello world VSIM 2 quit DPI Example The following example is a trivial but complete DPI application For win32 platforms an additional step is required For additional examples see the install dir modeltech examples systemverilog dpi directory hello c c include svdpi h include dpiheader h int c task int i int o printf Hello from c_task n verilog task i o Call back into Verilog to i return 0 Return success hello v mo
505. rce that was applied to an existing VHDL signal Verilog register net or SystemC signal called the dest object This allows you to release signals registers or nets at any level of the design hierarchy from within a VHDL architecture or Verilog or SystemC module e g a testbench A signal_release works the same as the noforce command Signal_release can be called concurrently or sequentially in a process By default this command uses a backslash as a path separator You can change this behavior with the SignalSpyPathSeparator variablie in the modelsim ini file VHDL Syntax signal_release lt dest_object gt lt verbose gt Verilog Syntax signal_release lt dest_object gt lt verbose gt SystemC Syntax signal_release lt dest_object gt lt verbose gt Returns Nothing Arguments e dest object Required string A full hierarchical path or relative downward path with reference to the calling block to an existing VHDL signal Verilog register net or SystemC signal Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes e verbose Optional integer Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the signal is being released and the time of the release 0 Does not report a message Default Reports a message ModelSi
506. rchitecture such as a testbench See init signal spy for complete details signal force The signal force utility forces the value specified onto an existing VHDL signal or Verilog register or net This allows you to force signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal force works the same as the force command with the exception that you cannot issue a repeating force See signal force for complete details signal release The signal release utility releases any force that was applied to an existing VHDL signal or Verilog register or net This allows you to release signals registers or nets at any level of the design hierarchy from within a VHDL architecture e g a testbench A signal release works the same as the noforce command See signal release for complete details to real The to real utility converts the physical type time value into a real value with respect to the current value of simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 1900 fs to a real and the simulator resolution was ps then the real value would be rounded to 2 0 i e 2 ps Syntax realval to real timeval 156 ModelSim User s Manual v6 3g May 2008 Returns Name Type realval real Arguments Name Type timeval time Related functions e get resolution e to time
507. reach i Sa if i ZZZ break set b linsert b 0 i Example 14 5 is a list reversal that skips a particular element by using the Tcl continue command Example 14 5 Tcl continue Command set b list foreach i a if i ZZZ continue set b linsert b 0 i Example 14 6 works in UNIX only In a Windows environment the Tcl exec command will execute compiled files only not system commands The example shows how you can access system information and transfer it into VHDL variables or signals and Verilog nets or registers When a particular HDL source breakpoint occurs a Tcl function is called that gets the date and time and deposits it into a VHDL signal of type STRING If a particular environment variable DO_ECHO is set the function also echoes the new date and time to the transcript file by examining the VHDL variable Example 14 6 Access and Transfer System Information in VHDL source signal datime string 1 to 28 28 spaces on VSIM command line or in macro proc set date global env set do the echo set env DO ECHO set s clock format clock seconds force deposit datime s if do the echo echo New time is examin value datime bp src waveadd vhd 133 set_date continue sets the breakpoint to call set_date Example 14 7 specifies the compiler arguments and lets you compile any number of files 356 ModelSim User s Manual v6 3g May 2008
508. reate is marked by a window tab as shown in the graphic below Figure 2 21 Displaying Multiple Source Files C modeltech examp emc sc_vhdl_vlog store v 14 module store clock reset oeenable ramadrs txda buffer 15 16 parameter counter size 4 17 parameter buffer size 16 18 19 Define blocks I O s 20 input clock reset oeenable txda 21 input counter size 2 0 ramadrs 22 output buffer size 1 0 buffer 23 24 Define wires for connecting wires 2 wire clock reset oeenable txda outstrobe rxda 26 wire counter size 2 0 ramadrs Ss Lam wave C ringbuth H contolvhd i stores h Unite tabs al See Organizing Windows with Tab Groups for more information on these tabs Dragging and Dropping Objects into the Wave and List Windows ModelSim allows you to drag and drop objects from the Source window to the Wave and List windows Double click an object to highlight it then drag the object to the Wave or List window To place a group of objects into the Wave and List windows drag and drop any section of highlighted code Setting your Context by Navigating Source Files When debugging your design from within the GUI you can change your context while analyzing your source files Figure 2 22 shows the pop up menu the tool displays after you select then right click an instance name in a source file ModelSim User s Manual v6 3g 65 May 2008 Graphical User Interfa
509. rid period count cycle count Time units ns v Use commas in time values Show frequency in cursor delta OK Cancel e The Grid Configuration selections allow you to set grid offset minimum grid spacing and grid period You can also reset these grid configuration settings to their default values 240 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Measuring Time with Cursors in the Wave Window e The Timeline Configuration selections give you a user definable time scale You can display simulation time on a timeline or a clock cycle count If you select Display simulation time in timeline area use the Time Units dropdown list to select one of the following as the timeline unit fs ps ns us ms sec min hr Note The time unit displayed in the Wave window does not affect the simulation time that is currently defined The current configuration is saved with the wave format file so you can restore it later The Show frequency in cursor delta box causes the timeline to display the difference delta between adjacent cursors as frequency By default the timeline displays the delta between adjacent cursors as time To add cursors when the Wave window is active click the Insert Cursor icon or choose Add gt Wave gt Cursor from the menu bar Each added cursor is given a default cursor name Cursor 2 Cursor 3 etc which can be changed by simply right clicking the cursor name then typing in a n
510. riginal state right click on a blank spot of the main toolbar area and select Reset Simulator GUI Preferences Simulator GUI preferences are stored by default either in the modelsim file in your HOME directory on UNIX Linux platforms or the Registry on Windows platforms ModelSim User s Manual v6 3g 461 May 2008 Setting GUI Preferences Simulator GUI Preferences Setting Preference Variables from the GUI To edit a variable value from the GUI select Tools gt Edit Preferences This opens the Preferences dialog The dialog organizes preferences by window and by name The By Window tab primarily allows you to change colors and fonts for various GUI objects For example if you want to change the color of the text in the Source window do the following 1 Select Source window from the Window List column Window List Dataflow Windows emory Windows Active Process Window Objects Window Source Windows Structure Windows ocals Window ave Windows 2 Select Text from the Source Color Scheme column r Source Color Scheme Category Editor Files Code Browser Annotation Window Document Types 3 Click the type of text you want to change Regular Text Selected Text Found Text etc from the Colors area Colors selected Text 462 ModelSim User s Manual v6 3g May 2008 Setting GUI Preferences Simulator GUI Preferences 4 Click the Foreg
511. ring value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use acc_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms 442 ModelSim User s Manual v6 3g May 2008 IEEE Std 1364 TF Routines ModelSim Verilog supports the following TF task and function routines Routines io mcdprintf 1o printf mc scan plusargs tf add long tf asynchoff tf iasynchoff tf asynchon tf iasynchon tf clearalldelays tf iclearalldelays tf compare long tf copypvc flag tf icopypvc flag tf divide long tf dofinish tf dostop tf error tf evaluatep tf ievaluatep tf exprinfo tf iexprinfo tf getcstringp tf igetcstringp tf getinstance tf getlongp tf igetlongp tf getlongtime tf igetlongtime tf getnextlongtime tf getp tf igetp tf getpchange tf igetpchange tf getrealp tf igetrealp Verilog PLI VPI DPI IEEE Std 1364 TF Routines Table C 5 Supported TF Routines tf getrealtime tf igetrealtime tf gettime tf igettime tf gettimeprecision tf igettimeprecision tf gettimeunit tf igettimeunit tf getworkarea tf igetworkarea tf long to real tf longtime tostr tf message tf mipname tf imipname tf movepvc flag tf imovepvc flag tf multiply long tf nodeinfo tf inodeinfo tf nump tf inump tf propagatep tf ipropaga
512. rmation Dependency Checking Dependent design units must be reanalyzed when the design units they depend on are changed in the library vcom determines whether or not the compilation results have changed For example if you keep an entity and its architectures in the same source file and you modify only an architecture and recompile the source file the entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity Range and Index Checking A range check verifies that a scalar value defined with a range subtype is always assigned a value within its range An index check verifies that whenever an array subscript expression is evaluated the subscript will be within the array s range Range and index checks are performed by default when you compile your design You can disable range checks potentially offering a performance advantage and index checks using arguments to the vcom command Or you can use the NoRangeCheck and NoIndexCheck variables in the modelsim ini file to specify whether or not they are performed See Simulator Control Variables Range checks in ModelSim are slightly more restrictive than those specified by the VHDL LRM ModelSim requires any assignment to a signal to also be in range whereas the LRM requires only that range checks be done whenever a signal is updated Most assignments to signals update the signal anyway and the more restrictive requirement allows
513. roperties dialog for the file Simply right click on the filename in the Project tab and select Properties from the context menu that appears This will open the Project Compiler Settings Dialog Figure 4 17 Use the Place in Folder field to specify a folder Specify a folder here 124 ModelSim User s Manual v6 3g May 2008 Projects Specifying File Properties and Project Settings Figure 4 17 Project Compiler Settings Dialog Project Compiler Settings o 24 General VHDL Coverage General Settings Do Not Compile Compile to library work yi Place in Folder VHDL v m File Properties File stimulus vhd Location C examples stimulus vhd MS DOS name C examples stimulus vhd Type VHDL Change Type Size 3145 3KB Modification Time 13 47 28 Pacific Standard Time Last Compile Source has not been compiled File Attributes Archive On Windows platforms you can also just drag and drop a file into a folder Specifying File Properties and Project Settings You can set two types of properties in a project file properties and project settings File properties affect individual files project settings affect the entire project File Compilation Properties The VHDL and Verilog compilers vcom and vlog respectively have numerous options that affect how a design is compiled and subsequently simulated You can customize the settings on individual files o
514. round or Background color block Sample Selected Text Foreground Background p O 5 Select a color from the palette To change the font type and or size of the window selected in the Windows List column use the Fonts section of the By Window tab that appears under General Text Settings Figure E 9 Figure E 9 Change Text Fonts for Selected Window General Text Settings r Fonts Document text courier New 1o B 7 You can also make global font changes to all GUI windows with the Fonts section of the By Window tab Figure E 10 Making Global Font Changes Tahoma 8 Choose Restore default Fonts Preview Sample Text 01234567894BCDEFUWXxzZz The Quick Brown Fox Jumped Over The Lazy Dog The By Name tab Figure E 11 lists every Tcl variable in a tree structure The procedure for changing a Tcl variable is 1 Expand the tree 2 Highlight a variable 3 Click Change Value to edit the current value ModelSim User s Manual v6 3g 463 May 2008 Setting GUI Preferences Simulator GUI Preferences Figure E 11 Preferences Dialog Box By Name Tab TTT x By Window By Name l l Preferences Assertions Compare default amp ddTowave 1 if setto 1 comparison items are automatically adde defaultClockName default clock the default clock name used in the add signal regior defaultDiffsFile comp
515. rray aggregate of an array type whose element subtype is itself an array all expressions in the array aggregate must have the same index constraint which is the ModelSim User s Manual v6 3g 415 May 2008 Error and Warning Messages Enforcing Strict 1076 Compliance element s index constraint No warning is issued the presence of pedanticerrors will produce an error e Non static choice in an array aggregate must be the only choice in the only element association of the aggregate e The range constraint of a scalar subtype indication must have bounds both of the same type as the type mark of the subtype indication e The index constraint of an array subtype indication must have index ranges each of whose both bounds must be of the same type as the corresponding index subtype e When compiling VHDL 1987 various VHDL 1993 and 2002 syntax is allowed Use pedanticerrors to force strict compliance Warnings are all level 10 416 ModelSim User s Manual v6 3g May 2008 Appendix C Verilog PLI VPI DPI This appendix describes the ModelSim implementation of the e Verilog PLI Programming Language Interface e VPI Verilog Procedural Interface e SystemVerilog DPI Direct Programming Interface These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface There are many third party applications available that interface to Verilog simulators through
516. rrorFlag 1 OR now 2 ms stop adds 2 ms to the simulation time at which the when statement is first evaluated then stops The white space between the value and time unit is required for the time unit to be understood by the simulator See the when command in the Command Reference for more examples Setting Signal Breakpoints with the GUI Signal breakpoints are most easily set in the Objects Pane and the Wave window Right click a signal and select Insert Breakpoint from the context menu A breakpoint is set on that signal and will be listed in the Modify Breakpoints dialog accessible by selecting Tools gt Breakpoints from the Main menu bar Modifying Signal Breakpoints You can modify signal breakpoints by selecting Tools gt Breakpoints from the Main menus This will open the Modify Breakpoints dialog Figure 9 35 which displays a list of all breakpoints in the design 270 ModelSim User s Manual v6 3g May 2008 Waveform Analysis Creating and Managing Breakpoints Figure 9 35 Modifying the Breakpoints Dialog Modify Breakpoints x Breakpoints fll asicSimulation counter Line 36 diy sim test_counter reset Add Modify Modify Enable Delete Label sim test_counter reset Condition sim test_counter reset Command echo Break on sim test_counter reset stop OK Cancel When you select a signal breakpoint from the list and click the Modify button the Signal Break
517. rs see Organizing Projects with Folders IEEE 5 5 eure o o Project metadata are updated and stored only for actions taken within the project itself For example if you have a file in a project and you compile that file from the command line rather than using the project menu commands the project will not update to reflect any new compile settings What are the Benefits of Projects Projects offer benefits to both new and advanced users Projects e simplify interaction with ModelSim you don t need to understand the intricacies of compiler switches and library mappings eliminate the need to remember a conceptual model of the design the compile order is maintained for you in the project Compile order is maintained for HDL only designs e remove the necessity to re establish compiler switches and settings at each session these are stored in the project metadata as are mappings to source files ModelSim User s Manual v6 3g 111 May 2008 Projects Getting Started with Projects allow users to share libraries without copying files to a local directory you can establish references to source files that are stored remotely or locally allow you to change individual parameters across multiple files in previous versions you could only set parameters one file at a time enable what if analysis you can copy a project manipulate the settings and rerun it to observe the new results reload the initial settings from the project
518. rved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this software must display the following acknowledgement This product includes software developed by Winning Strategies Inc 4 The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE AUTHOR AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF
519. s process name kind of object path points to returns Instance Signal Process or Unknown instance or region path without leaf process file line number of assertion or if from subprogram line from which call is made 386 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables Table A 3 MessageFormat Variable Accepted Values print 26 character e Default S R n Time T Iteration D I n MessageFormatBreak This variable defines the format of messages for VHDL assertions that trigger a breakpoint e Value Range Refer to Table A 3 e Default S R n Time T Iteration WD 96K i File F n MessageFormatBreakLine This variable defines the format of messages for VHDL assertions that trigger a breakpoint e Value Range Refer to Table A 3 e Default S R n Time T Iteration WD K i File WF Line L n MessageFormatError This variable defines the format of all error messages If undefined MessageFormat is used unless the error causes a breakpoint in which case MessageFormatBreak is used e Value Range Refer to Table A 3 Default S R n Time T Iteration WD K i File F n MessageFormatFail This variable defines the format of messages for VHDL Fail assertions If undefined MessageFormat is used unless assertion causes a breakpoint in which case MessageFormatBreak is used e Value Range Refer to Table A 3 e De
520. s Figure E 6 GUI Zoom Button To restore the pane to its original size and position click the unzoom button in the heading of the pane 460 ModelSim User s Manual v6 3g May 2008 Setting GUI Preferences Simulator GUI Preferences Figure E 7 GUI Unzoom Button Columnar Information Display Many panes e g Objects Workspace etc display information in a columnar format You can perform a number of operations on columnar formats e Click and drag on a column heading to rearrange columns e Click and drag on a border between column names to increase decrease column size e Sort columns by clicking once on the column heading to sort in ascending order clicking twice to sort in descending order and clicking three times to sort in default order e Hide or show columns by either right clicking a column heading and selecting an object from the context menu or by clicking the column list drop down arrow and selecting an object Quick Access Toolbars Toolbar buttons provide access to commonly used commands and functions Toolbars can be docked and undocked moved to or from the main toolbar area by clicking and dragging on the toolbar handle at the left edge of a toolbar Figure E 8 Toolbar Manipulation Toolbar Handle You can also hide show the various toolbars To hide or show a toolbar right click on a blank spot of the main toolbar area and select a toolbar from the list To reset toolbars to their o
521. s 383 DelayFileOpen 383 DumpportsCollapse 383 ErrorFile 383 GenerateFormat 383 GenerousldentifierParsing 384 GlobalSharedObjectList 384 IgnoreError 384 IgnoreFailure 384 ModelSim User s Manual v6 3g May 2008 Index IgnoreNote 384 Ignore Warning 385 IterationLimit 385 License 385 MessageFormat 386 MessageFormatBreak 387 MessageFormatBreakLine 387 MessageFormatError 387 MessageFormatFail 387 MessageFormatFatal 387 MessageFormatNote 388 MessageFormatWarning 388 NumericStdNoWarnings 388 PathSeparator 389 Resolution 390 RunLength 390 Startup 391 StdArithNoWarnings 391 ToggleCountLimit 391 ToggleMaxIntValues 391 Toggle VlogIntegers 392 ToggleWidthLimit 392 TranscriptFile 392 UnbufferedOutput 392 UserTimeUnit 392 Veriuser 393 WarnConstantChange 393 WaveSignalName Width 393 WLFCacheSize 393 WLFCollapseMode 393 WLFCompress 393 WLFDeleteOnQuit 394 WLFFilename 394 WLFOptmize 394 WLFSaveAllRegions 394 WLFSimCacheSize 394 WLESizeLimit 395 WLFTimeLimit 395 ini variables set simulator control with GUI 395 473 ABCDEFGH I modelsim file in initialization sequence 470 purpose 467 So shared object file loading PLI VPI DPI C applications 429 loading PLI VPI DPI C applications 431 Numerics O In tools setting environment variable 364 1076 IEEE Std 31 differences between versions 141 1364 IEEE Std 31 169 1364 2005 IEEE std 97 323 64 b
522. s Although you can still use superseded features commands arguments or variables Mentor Graphics deprecates their usage you should use the corresponding new version whenever possible or convenient ModelSim User s Manual v6 3g 33 May 2008 Introduction Deprecated Features Commands and Variables The following tables indicate the version in which the item was superseded and a link to the new item that replaces it where applicable Table 1 5 Deprecated Commands vencrypt auto 6 3 vencrypt lt filename gt By default the vencrypt command now automatically encrypts Table 1 6 Deprecated Command Arguments Table 1 7 Deprecated modelsim ini Variables Variable Version New Variable Information Assertion Format MessageFormat AssertionFormatBreak MessageFormatBreak AssertionFormatError MessageFormatError AssertionFormatFail MessageFormatFail AssertionFormatFatal MessageFormatFatal AssertionFormatNote MessageFormatNote AssertionFormatWarning MessageFormatWarning 34 ModelSim User s Manual v6 3g May 2008 Chapter 2 Graphical User Interface ModelSim s graphical user interface GUI consists of various windows that give access to parts of your design and numerous debugging tools Some of the windows display as panes within the ModelSim Main window and some display as windows in the Multiple Document Interface MDI frame Figure 2 1 Graphical User Interface SARAJA es I s
523. s DPI C imports the DPI shared object is loaded at runtime automatically Neither the C implementation of the import tf nor the sv lib argument is required Also on most platforms see Platform Specific Information you can declare most standard C library functions as DPI C imports The following example is processed directly without DPI C code package cmath import DPI C function real sin input real x import DPI C function real sqrt input real x endpackage package fli import DPI C function mti Cmd input string cmd 426 ModelSim User s Manual v6 3g May 2008 Verilog PLI VPI DPI DPI Use Flow endpackage module top import cmath import flis int status A initial begin Sdisplay sin 0 98 Sf sin 0 98 Sdisplay sqrt 0 98 Sf sqrt 0 98 status mti_Cmd change A 123 Sdisplay A 1d status 1d A status end endmodule To simulate you would simply enter a command such as vsim top Precompiled packages are available with that contain import declarations for certain commonly used C calls lt installDir gt verilog_src dpi_cpack dpi_cpackages sv You do not need to compile this file it is automatically available as a built in part of the SystemVerilog simulator Platform Specific Information On Windows only FLI and PLI commands may be imported in this fashion C library functions are not automatically importable They must be wrapped in user DPI C functi
524. s an alias o 2001 Instructs vsim to use the object models as defined in IEEE Std 1364 2001 When you specify this argument SystemVerilog objects will not be accessible You can also use 01 as an alias e Default latest You can also control this behavior with the plicompatdefault switch to the vsim command where the plicompatdefault argument will override the PliCompatDefault variable You should note that there are a few cases where the 2005 VPI object model is incompatible with the 2001 model which is inherent in the specifications ModelSim User s Manual v6 3g 389 May 2008 Simulator Variables Simulator Control Variables Refer to the appendix Verilog PLI VPI DPI in the User s Manual for more information PrintSimStats This variable instructs the simulator to print out simulation statistics at the end of the simulation before it exits You can set this variable interactively with the printsimstats argument to the vsim command e Value Range 0 1 e Default 0 Resolution This variable specifies the simulator resolution The argument must be less than or equal to the UserTimeUnit and must not contain a space between value and units for example Resolution 10fs You can override this value with the t argument to vsim You should set a smaller resolution if your delays get truncated e Value Range fs ps ns us ms or sec with optional prefix of 1 10 or 100 e Default ps RunLength This variable sp
525. s for the International Sale of Goods does not apply to this Agreement SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect PAYMENT TERMS AND MISCELLANEOUS You will pay amounts invoiced in the currency specified on the applicable invoice within 30 days from the date of such invoice Any past due invoices will be subject to the imposition of interest charges in the amount of one and one half percent per month or the applicable legal rate currently in effect whichever is lower Some Software may contain code distributed under a third party license agreement that may provide additional rights to you Please see the applicable Software documentation for details This Agreement may only be modified in writing by authorized representatives of the parties Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse Rev 060210 Part No 227900
526. s ia cusa eR ERA ks oy ade be EERERSARAEEAGIE GARE REESE 112 Step 1 Creating a New Project S oe se dra eta ox bb UR ORES ARIA RET AS aM 113 Step 2 Adding Items to the Project iiid ue od deed PR R9 eh does e RR Re 114 Step 3 Compiling the Files vicki 5 re e ERROR ERROR RR ACD Race RP Rs 115 Step 4 Simulating a Design v uose dp eee cedro x RS EXER ee RRS SEE RENS 118 Other Basic Project Operations idee ele y E RE RH Ro x REA RR eas 120 Th Proj t TaD PT aaa tees bb Oe eee ae ees eee eee ene eee eae te 120 Sorting the Listo cca hace esa RO RH REG Gade EEG CR RO PRU RR Y eg ARCU RR ER eg 121 Creating a Simulation Configuration 0 cece eee eee teenie nee 121 Organizing Projects with POlders soos ooh ade ded uisevine RRRAGMRREXE S Re xReES 123 Adding a F ld r losecane eir ER odds RE ROLES E RQURE cabs eter d IE LAM qe qp ES 123 Specifying File Properties and Project Settings llle 125 File Compilation Properties 123424 exe bep ROS RRRURATPORRRC RED DREE RI M RP EE XS 125 lude m ienten ri aN hr pO Eea EEEO AER 127 Accessing Projects from the Command Line 128 Chapter 5 Design LIBDEIAPIeS 66 56 60 2a es ee Rex ER ete eee i Nese oe0R ones chines eee ewes 129 Design Library Overview os ecques eux eser ura q eR REXTESE TERN eS RE RENE EE 129 Design Unit Information 24a desde Rd IRR ERR REG I QUPREE E TUS diee 129 Working Library Versus Resource Libraries 0 0 0 00 cee eee eee ee 129 P wn 2
527. s in the specified design Specifying the Wrong Instance By far the most common mistake in SDF annotation is to specify the wrong instance to the simulator s SDF options The most common case is to leave off the instance altogether which is the same as selecting the top level design unit This is generally wrong because the instance paths in the SDF are relative to the ASIC or FPGA model which is usually instantiated under a top level testbench See Instance Specification for an example A common example for both VHDL and Verilog testbenches is provided below For simplicity the test benches do nothing more than instantiate a model that has no ports 326 ModelSim User s Manual v6 3g May 2008 Standard Delay Format SDF Timing Annotation Troubleshooting VHDL Testbench entity testbench is end architecture only of testbench is component myasic end component begin dut myasic end Verilog Testbench module testbench myasic dut endmodule The name of the model is myasic and the instance label is dut For either testbench an appropriate simulator invocation might be vsim sdfmax testbench dut myasic sdf testbench Optionally you can leave off the name of the top level vsim sdfmax dut myasic sdf testbench The important thing is to select the instance for which the SDF is intended If the model is deep within the design hierarchy an easy way to find the instance name is to first invoke the simulator witho
528. s of a list of number pattern label pairs numeric value lt enum label gt numeric value enum label default radix A lt numeric value gt is any legitimate HDL integer numeric literal To be more specific lt base gt lt base integer gt lt base gt is 2 8 10 or 16 base bit value base is B O or X integer lt size gt lt base gt lt number gt size is an integer base is b d o or h Check the Verilog and VHDL LRMs for exact definitions of these numeric literals The comma in the definition body is optional The lt enum label gt is any arbitrary string It should be quoted especially if it contains spaces The default entry is optional If present it defines the radix to use if a match is not found for a given value The default entry can appear anywhere in the list it does not have to be at the end Example 2 1 shows the radix define command used to create a radix called States which will display state values in the List Watch and Wave windows instead of numeric values Example 2 1 Using the radix define Command radix define States 38 ModelSim User s Manual v6 3g May 2008 Graphical User Interface User Defined Radices 11 5b00000000001 IDLE 11 5b00000000010 CTRL 11 5b00000000100 WT WD 1 11 5b00000001000 WT WD 2 11 5b00000010000 WT BLK 1 11 5b00000100000 WT BLK 2 11 5b00001000000
529. s of the source code Library Usage All modules and UDPs in a Verilog design must be compiled into one or more libraries One library is usually sufficient for a simple design but you may want to organize your modules into various libraries for a complex design If your design uses different modules having the same name then you are required to put those modules in different libraries because design unit names must be unique within a library The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another ModelSim User s Manual v6 3g 173 May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files 96 vlib work 96 vlib asiclib 96 vlog work asiclib and2 v or2 v Compiling module and2 Compiling module or2 Top level modules and2 or2 96 vlog top v Compiling module top Top level modules top Note that the first compilation uses the work asiclib argument to instruct the compiler to place the results in the asiclib library rather than the default work library Library Search Rules for vlog Since instantiation bindings are not determined at compile time you must instruct the simulator to search your libraries when loading the design The top level modules are loaded from the library named work unless you prefix the modules with the library option All other Verilog instantiations are resolved in the following order Search librari
530. s tasks 334 from VHDL source to VCD output 335 stimulus using as 330 supported TSSI states 340 translate into WLF 339 VCD system tasks 334 vcd2wlf command 339 vencrypt command header file 99 Verilog ACC routines 441 capturing port driver data with dumpports 339 cell libraries 202 compiler directives 215 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ compiling and linking PLI C applications 429 compiling and linking PLI C applications 431 compiling design units 170 compiling with XL uselib compiler directive 177 configurations 180 DPI access routines 443 event order in simulation 185 extended system tasks 214 generate statements 181 language templates 67 library usage 173 resource libraries 135 SDF annotation 318 sdf annotate system task 318 simulating 182 delay modes 203 XL compatible options 201 simulation hazard detection 189 simulation resolution limit 182 source code viewing 63 standards 31 system tasks 204 TF routines 443 XL compatible compiler options 176 XL compatible routines 444 XL compatible system tasks 212 verilog ini file variable 371 Verilog 2001 disabling support 374 Verilog PLI VP DPII registering VPI applications 421 Verilog PLI VPI 64 bit support in the PLI 445 debugging PLI VPI code 445 Verilog PLI VPI DPI compiling and linking PLI VPI C applications 431 compiling and linking PLI VPI CPI C applications 429 PLI callback reason argu
531. s until convergence is found For example in this timing check setuphold posedge CLK D 10 20 notifier dCLK dD dCLK is the delayed version of the input CLK and dD is the delayed version of D By default the timing checks are performed on the inputs while the model s functional evaluation uses the delayed versions of the inputs This posedge D Flipflop module has a negative setup limit of 10 ModelSim User s Manual v6 3g 195 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs time units which allows posedge CLK to occur up to 10 time units before the stable value of D is latched D violation 10 20 region XXXXXXXXXX CLK Without delaying CLK by 11 an old value for D could be latched Note that an additional time unit of delay is added to prevent race conditions The inputs look like this CLK resulting in delayed inputs of dD dCLK Because the posedge CLK transition is delayed by the amount of the negative setup limit plus one time unit to prevent race conditions no timing violation is reported and the new value of D is latched However the effect of this delay could also affect other inputs with a specified timing relationship to CLK The simulator is reponsible for calculating the delay between all inputs and their delayed versions The complete set of delays delay solution convergence must consider all timing check limits together so that
532. saving a Wave window format file see Saving the Window Format 92 ModelSim User s Manual v6 3g May 2008 Wave Window Toolbar Graphical User Interface Wave Window The Wave window toolbar in the undocked Wave window gives you quick access to these ModelSim commands and functions Button Table 2 11 Wave Window Toolbar Buttons and Menu Selections Open Dataset open a previously saved dataset Menu equivalent File gt Open Other options File gt Open from Main window when Transcript window sim tab is active Save Format save the current Wave window display and signal preferences to a DO macro file File gt Save none te e v Print print a user selected range of the current Wave window display to a printer or a file File Print File Print Postscript Export Waveform export a created waveform File gt Export gt Waveform Cut cut the selected signal from the Wave window Edit Cut right mouse in pathname pane Cut Copy copy the signal selected in the pathname pane Edit Copy right mouse in pathname pane Copy Paste paste the copied signal above another selected signal Edit Paste right mouse in pathname pane Paste Find find a name or value in the Wave window Edit Find lt control f gt Windows control s UNIX GE Find Previous Transition locate the previous signal value change for the selecte
533. se definition is stored in a special location and is not visible in the Objects pane or to the normal virtual commands All other virtual signals are considered explicit virtuals Virtual Functions Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel They consist of logical operations on logged signals and can be dependent on simulation time They can be displayed in the Objects Wave and List windows and accessed by the examine command but cannot be set by the force command Examples of virtual functions include the following e a function defined as the inverse of a given signal e a function defined as the exclusive OR of two signals e a function defined as a repetitive clock e a function defined as the rising edge of CLK delayed by 1 34 ns Virtual functions can also be used to convert signal types and map signal values The result type of a virtual function can be any of the types supported in the GUI expression syntax integer real boolean std_logic std_logic_vector and arrays and records of these types Verilog types are converted to VHDL 9 state std_logic equivalents and Verilog net strengths are ignored ModelSim User s Manual v6 3g 231 May 2008 Recording Simulation Results With Datasets Virtual Objects Virtual functions can be created using the virtual function command Virtual functions are also implicitly created by ModelSim whe
534. sed During Startup 000 468 22 ModelSim User s Manual v6 3g May 2008 Chapter 1 Introduction This documentation was written for UNIX Linux and Microsoft Windows users Not all versions of ModelSim are supported on all platforms Contact your Mentor Graphics sales representative for details Tool Structure and Flow The diagram below illustrates the structure of the ModelSim tool and the flow of that tool as it is used to verify a design ModelSim User s Manual v6 3g 23 May 2008 Introduction Simulation Task Overview Figure 1 1 Tool Structure and Flow ModelSim Map libraries local work Libraries library Verilog VHDL Analyze Compile compiled database vsim Simulate Debug Simulation Output e g vcd Post processing Debug Simulation Task Overview The following table provides a reference for the tasks required for compiling loading and simulating a design in ModelSim 24 ModelSim User s Manual v6 3g May 2008 Introduction Basic Steps for Simulation Table 1 1 Simulation Tasks ModelSim Example Command Line GUI Menu Pull down GUI Icons Entry Step 1 vlib lt library_name gt a File gt New gt Project Map libraries vmap work library name b Enter library name c Add design files to project Step 2 vlog filel v file2 v a Compile Compile Compile or Compile the Verilog or Compile All design vcom filel vhd fi
535. sertion ini file variable 381 breakpoints command execution 72 conditional 71 deleting 70 272 edit 70 270 273 set with GUI 69 Source window viewing in 64 bsm file 284 buffered unbuffered output 392 busses RTL level reconstructing 230 user defined 263 C C applications compiling and linking 429 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I C applications compiling and linking 431 Call Stack pane 49 cancelling scheduled events performance 167 causality tracing in Dataflow window 281 cell libraries 202 change command modifying local variables 205 chasing X 281 check_synthesis argument warning message 412 CheckPlusargs ini file variable VLOG 381 CheckpointCompressMode ini file variable 381 CheckSynthesis ini file variable 375 clock change sampling signals at 268 clock cycles display in timeline 251 Clocking block inout display 92 collapsing time and delta steps 228 colorization in Source window 72 columns hide showing in GUI 461 moving 461 sorting by 461 Combine Selected Signals dialog box 54 combining signals busses 263 CommandHistory ini file variable 381 command line mode 29 commands event watching in DO file 357 system 351 ved2wlf 339 VSIM Tcl commands 352 where 369 comment character Tcl and DO files 348 compare signal virtual restrictions 263 compare simulations 219 compilation multi file issues SystemVerilo
536. simulator state or simulator control variables Use the following commands at either the ModelSim or VSIM prompt report simulator state report simulator control Environment Variables Environment Variable Expansion The shell commands vcom vlog vsim and vmap no longer expand environment variables in filename arguments and options Instead variables should be expanded by the shell beforehand in the usual manner The f switch that most of these commands support now performs environment variable expansion throughout the file Environment variable expansion is still performed in the following places ModelSim May 2008 Pathname and other values in the modelsim ini file Strings used as file pathnames in VHDL and Verilog VHDL Foreign attributes The PLIOBJS environment variable may contain a path that has an environment variable Verilog uselib file and dir directives User s Manual v6 3g 363 Simulator Variables Environment Variables e Anywhere in the contents of a f file The recommended method for using flexible pathnames is to make use of the MGC Location Map system see Using Location Mapping When this is used then pathnames stored in libraries and project files mpf will be converted to logical pathnames If a file or path name contains the dollar sign character and must be used in one of the places listed above that accepts environment variables then the explicit dollar sign must be escaped by using a d
537. sion is preserved if a directive is used in the file to be encrypted For more information see Compiling a Design with vlog protect The IP vendor delivers the encrypted IP The IP user simulates the code like any other Verilog file Delivering Protected IP with protect Compiler Directives The protect and endprotect compiler directives are specific to ModelSim and are not compatible with other simulators Though other simulators have a protect directive the algorithm ModelSim uses to encrypt source files is different Hence even though an uncompiled source file with protect is compatible with another simulator once the source is compiled in ModelSim the resulting vp or svp source file is not compatible Figure 3 3 Delivering IP with protect Compiler Directives protect selected regions of Verilog or SystemVerilog code with protect compiler directives vlog protect IP vendor creates vp or svp file or user simulate The IP vendor protects selected regions of Verilog or SystemVerilog IP with the protect endprotect directive pair The code in protect endprotect encryption envelopes has all debug information stripped out This behaves exactly as if using vlog nodebug ports tpli except that it applies to selected regions of code rather than the whole file The IP vendor uses the vlog protect command to encrypt IP code contained within encryption envelopes The protect endprotect directiv
538. son_endofcompile For the completion of loading the design reason_finish For the execution of the finish system task or the quit command reason_startofsave For the start of execution of the checkpoint command but before any of the simulation state has been saved This allows the PLI application to prepare for the save but it shouldn t save its data with calls to tf_write_save until it is called with reason_save reason save For the execution of the checkpoint command This is when the PLI application must save its state with calls to tf write save reason startofrestart For the start of execution of the restore command but before any of the simulation state has been restored This allows the PLI application to prepare for the restore but it shouldn t restore its state with calls to tf read restart until it is called with reason restart The reason startofrestart value is passed only for a restore command and not in the case that the simulator is invoked with restore reason restart For the execution of the restore command This is when the PLI application must restore its state with calls to tf read restart reason reset For the execution of the restart command This is when the PLI application should free its memory and reset its state We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be reloaded See the keeploaded and keeploade
539. ss The Project Tab The Project tab contains information about the objects in your project By default the tab is divided into five columns Figure 4 12 Project Displayed in Workspace Workspace Bp nel F5 Folder adder vhd VHDL 3 06 07 06 07 35 46 PM testadder vhd VHDL 2 06 07 06 07 36 26 PM Verilog files Folder uL tcounter v y Verilog 0 06 07 06 07 36 21 PM NE counter v Verilog 1 06 07 06 07 35 56 PM verllog sim Simulation Project Library e Name The name of a file or object e Status Identifies whether a source file has been successfully compiled Applies only to VHDL or Verilog files A question mark means the file hasn t been compiled or the source file has changed since the last successful compile an X means the compile failed a check mark means the compile succeeded a checkmark with a yellow triangle behind it means the file compiled but there were warnings generated e Type The file type as determined by registered file types on Windows or the type you specify when you add the file to the project e Order The order in which the file will be compiled when you execute a Compile All command 120 ModelSim User s Manual v6 3g May 2008 Projects Creating a Simulation Configuration e Modified The date and time of the last modification to the file You can hide or show columns by right clicking on a column title and selecting or deselecting entries Sort
540. ssage The iteration limit default value is 1000 If you receive an iteration limit warning first increase the iteration limit and try to continue simulation You can set the iteration limit from the Simulate gt Runtime Options menu or by modifying the IterationLimit variable in the modelsim ini See Simulator Control Variables for more information on modifying the modelsim ini file If the problem persists look for zero delay loops Run the simulation and look at the source code when the error occurs Use the step button to step through the code and see which signals 148 ModelSim User s Manual v6 3g May 2008 VHDL Simulation Using the TextlO Package or variables are continuously oscillating Two common causes are a loop that has no exit or a series of gates with zero delay where the outputs are connected back to the inputs Using the TextlO Package To access the routines in TextIO include the following statement in your VHDL source code USE std textio all A simple example using the package TextIO is USE std textio all ENTITY simple_textio IS END ARCHITECTURE simple_behavior OF simple_textio IS BEGIN PROCESS VARIABLE i INTEGER 42 VARIABLE LLL LINE BEGIN WRITE LLL i WRITELINE OUTPUT LLL WAIT END PROCESS END simple_behavior Syntax for File Declaration The VHDL 87 syntax for a file declaration is file identifier subtype indication is mode file logical name where
541. ssages will not be displayed even if break on assertion is set for that severity Multiple selections are possible The corresponding modelsim ini variables are IgnoreFailure IgnoreError IgnoreWarning and IgnoreNote The WLF Files tab includes these options Figure A 3 Runtime Options Dialog Box WLF Files Tab Defaults Assertions WLF Files WLF File Size Limit 3 WLF File Time Limit No Size Limit No Time Limit C Size Limit O Meg C Time Lina s w WLF Attributes Design Hierarchy v Compress WLF data Save regions containing logged signals Delete WLF file on exit C Save all regions in design OK Cancel Apply ModelSim User s Manual v6 3g 397 May 2008 Simulator Variables Simulator Control Variables e WLF File Size Limit Limits the WLF file by size as closely as possible to the specified number of megabytes If both size and time limits are specified the most restrictive is used Setting it to 0 results in no limit The corresponding modelsim ini variable is WLFSizeLimit e WLF File Time Limit Limits the WLF file by size as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used Setting it to O results in no limit The corresponding modelsim ini variable is WLFTimeLimit e WLF Attributes Specifies whether to compress WLF files and whether to delete the WLF file when the simulation ends You would
542. ssed 403 startup macros 401 Main window 40 see also windows Main window mapping libraries from the command line 133 hierarchically 400 ModelSim User s Manual v6 3g May 2008 ABCDEFGH I symbols Dataflow window 284 mapping libraries library mapping 133 math_complex package 136 math_real package 136 MDI frame 42 MDI pane tab groups 42 memories displaying the contents of 58 navigation 61 saving formats 61 selecting memory instances 60 viewing contents 60 viewing multiple instances 60 memory modeling in VHDL 158 memory leak cancelling scheduled events 167 Memory pane 58 pane Memory pane see also Memory pane memory tab memories you can view 59 Memory window 58 see also windows Memory window message system 407 Message Viewer Display Options dialog box 79 Message Viewer tab 76 MessageFormat ini file variable 386 MessageFormatBreak ini file variable 387 MessageFormatBreakLine ini file variable 387 MessageFormatError ini file variable 387 MessageFormatFail ini file variable 387 MessageFormatFatal ini file variable 387 MessageFormatNote ini file variable 388 MessageFormatWarning ini file variable 388 Messages 76 messages 407 bad magic number 221 empty port name warning 412 exit codes 410 getting more information 407 ModelSim User s Manual v6 3g May 2008 JKLMNOPQRSTUVWXYZ lock message 412 long description 407 message system variables 398 metavalue detected 4
543. ssion Searches 0 0000 e eee eee 248 Formatting the Wave Window o4 xs ced x haer eee EORR RR He PORRO 250 Setting Wave Window Display Preferences 0 eee 250 Formatting Objects in the Wave Window 0 0 eee eee eee eee 252 Dividing the Wave WIIdOW cues akt rib C EX RS a See ddp RH 254 Splitting Wave Window Panes scc5s eh Pech hetec en Ee E PR Pete ER PENAT 255 bro ite AMT 256 Creating a Wave OIDUD eco Svo SERRE ERA RERRR oder hee eee See OSEE SEDE 251 Deleting or Ungrouping a Wave Group 0 0 eee eee teenies 258 Adding Items to an Existing Wave Group 0 0 cece ee ee eens 258 Removing Items from an Existing Wave Group 0 e ce eee eee eee ee 258 Miscellaneous Wave Group Features 258 Formatting the List Window 3 S9 oppeto pXaes E RITIENE ae de dee aie de abeeees 259 Setting List Window Display Properties 0 0 cece eee eee eens 259 Formatting Objects in the List Window 0 0 eee eee eee 259 saving the Window PODBaE duas eir ERAS die ek LEX x e Rat ERES EE E 261 Printing and Saving Waveforms in the Wave window 0c eee eee eee 262 Saving a eps Waveform File and Printing in UNIX 0 0 00 eee eee eee 262 ModelSim User s Manual v6 3g May 2008 Table of Contents Printing from the Wave Window on Windows Platforms lees esses 262 Printer Page Se esas cu treonin ie oriana NAE S EA REM RELIER EnEP ER ERA
544. ssion must be a named type or subtype it can t have a constraint on it When the actual in a PORT MAP association is an expression it must be a globally static expression The port must also be of mode IN The expression in the CASE and selected signal assignment statements must follow the rules given in 8 8 of the LRM In certain cases we can relax these rules but pedanticerrors forces strict compliance A CASE choice expression must be a locally static expression We allow it to be only globally static but pedanticerrors will check that it is locally static Same rule for selected signal assignment statement choices Warning level is 8 When making a default binding for a component instantiation ModelSim s non standard search rules found a matching entity VHDL 2002 LRM Section 5 2 2 spells out the standard search rules Warning level is 1 Both FOR GENERATE and IF GENERATE expressions must be globally static We allow non static expressions unless pedanticerrors is present When the actual part of an association element is in the form of a conversion function call or a type conversion and the formal is of an unconstrained array type the return type of the conversion function type mark of the type conversion must be of a constrained array subtype We relax this with a warning unless pedanticerrors is present when it becomes an error OTHERS choice in a record aggregate must refer to at least one record element In an a
545. st be placed before run commands within the macros in order to take effect ModelSim User s Manual v6 3g 357 May 2008 Tcl and Macros DO Files Macros DO Files The following is a simple DO file that was saved from the transcript It is used in the dataset exercise in the ModelSim Tutorial This DO file adds several signals to the Wave window provides stimulus to those signals and then advances the simulation add wave ld add wave rst add wave clk add wave d add wave q force freeze clk 00 1 50 ns r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 onerror cont run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1 run 200 force rst 0 10 run 1500 Using Parameters with DO Files You can increase the flexibility of DO files by using parameters Parameters specify values that are passed to the corresponding parameters 1 through 9 in the macro file For example say the macro festfile contains the line bp 1 2 The command below would place a breakpoint in the source file named design vhd at line 127 do testfile design vhd 127 There is no limit on the number of parameters that can be passed to macros but only nine values are visible at one time You can use the shift command to see the other parameters Deleting a File from a do Script To delete a file from a do script use the Tcl file command as follows file delete myfile log This will delete the file myfile log You
546. stantial portions of the Software THE SOFTWARE IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM DAMAGES OR OTHER LIABILITY WHETHER IN AN ACTION OF CONTRACT TORT OR OTHERWISE ARISING FROM OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE Copyright 2003 2005 Amiga Inc Copyright 2002 Daryle Walker Copyright 2002 Thomas Wegner This software application may include Tcl third party software 1996 Sun Microsystems Inc 2002 ActiveState Corporation 1982 1986 1989 Regents of the University of California Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 All advertising materials mentioning features or use of this software must display the following acknowledgement This product includes software developed by the University of California Berkeley
547. sults You can create the logical library using the GUI using File gt New gt Library see Creating a Library or you can use the vlib command For example the command vlib work creates a library named work By default compilation results are stored in the work library Mapping the Logical Work to the Physical Work Directory vmap VHDL uses logical library names that can be mapped to ModelSim library directories If libraries are not mapped properly and you invoke your simulation necessary components will not be loaded and simulation will fail Similarly compilation can also depend on proper library mapping By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI Library Mappings with the GUI a command Library Mapping from the Command Line or a project Getting Started with Projects to assign a logical name to a design library The format for command line entry is vmap lt logical_name gt lt directory_pathname gt This command sets the mapping between a logical library name and a directory Step 2 Compiling the Design vlog vcom sccom Designs are compiled with one of the three language compilers Compiling Verilog vlog ModelSim s compiler for the Verilog modules in your design is vlog Verilog files may be compil
548. sunuimPx gall oT 7 ROC ANRIA i RE JT Bai lee gt e Rx ELS S2 ESSA LB d RM 2x wave defauk e te te std_logic_1164 standard M Time 2820 ne Iteration Instance top p VSIM 7 fA Transcript E Now 2840 ns Delta 1 sim top Limited Visibility Region rego ns to 2040 ns A ModelSim User s Manual v6 3g 35 May 2008 Graphical User Interface The following table summarizes all of the available windows and panes Table 2 1 GUI Windows and Panes Window pane name Main Description central GUI access point More details Main Window Process displays all processes that are scheduled to run during the current simulation cycle Process Window Dataflow displays physical connectivity and lets you trace events causality Dataflow Window List shows waveform data in a tabular format List Window Locals displays data objects that are immediately visible at the current execution point of the selected process a Workspace tab and MDI windows that show memories and their contents Locals Window Memory Panes Objects displays signal or variable values at the current simulation time displays all declared data objects in the current scope Watch Pane Objects Pane Source Transcript a text editor for viewing and editing HDL DO etc files keeps a running history of commands and messages and provides a command line interface So
549. t 64 bit Support for PLI The PLI function acc fetch paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc fetch paramval str has been added to the PLI for this use acc fetch paramval str is declared in acc user h It functions in a manner similar to acc fetch paramval except that it returns a char acc fetch paramval str can be used on all platforms Using 64 bit ModelSim with 32 bit Applications If you have 32 bit PLI VPI DPI applications and wish to use 64 bit ModelSim you will need to port your code to 64 bits by moving from the ILP32 data model to the LP64 data model We strongly recommend that you consult the 64 bit porting guides for Sun PLI VPI Tracing The foreign interface tracing feature is available for tracing PLI and VPI function calls Foreign interface tracing creates two kinds of traces a human readable log of what functions were called the value of the arguments and the results returned and a set of C language files that can be used to replay what the foreign interface code did The Purpose of Tracing Files The purpose of the logfile is to aid you in debugging PLI or VPI code The primary purpose of the replay facility is to send the replay files to support for debugging co simulation problems or debugging PLI VPI problems for which it is impractical to send the PLI VPI code We still need you to send the VHDL Verilog part of the des
550. t Tab search forward right to the next transition on the selected signal finds the next edge search backward left to the previous transition on the selected signal finds the previous edge Ctrl f Windows Ctrl s UNIX Ctrl Left Arrow Ctrl Right Arrow ModelSim User s Manual v6 3g May 2008 open the find dialog box searches within the specified field in the pathname pane for text strings scroll pathname values or waveform pane left or right by a page 455 Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts 456 ModelSim User s Manual v6 3g May 2008 Appendix E Setting GUI Preferences The ModelSim GUI is programmed using Tcl Tk It is highly customizable You can control everything from window size position and color to the text of window prompts default output filenames and so forth Most user GUI preferences are stored as Tcl variables in the modelsim file on Unix Linux platforms or the Registry on Windows platforms The variable values save automatically when you exit ModelSim Some of the variables are modified by actions you take with menus or windows e g resizing a window changes its geometry variable Or you can edit the variables directly either from the ModelSim gt prompt or the Edit Preferences dialog Customizing the Simulator GUI Layout You can customize the layout of panes windows toolbars etc This section discusses layouts and how they ar
551. t sta 0000 00000011 1000 1111 0111 1 2820 ns a000 m o Oon Oon Oo Ny au T D CC TITT ETEN ENE ATE EREE ITE TE ETEF ET ea ONE 10 20 30 40 50 ns 1s Keep T GEOR 55 Another scenario is to select a process in the Dataflow pane which automatically adds to the wave viewer pane all signals attached to the process See Tracing Events Causality for another example of using the embedded wave viewer 280 ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Tracing Events Causality You can use the Dataflow window to trace an event to the cause of an unexpected output This feature uses the Dataflow window s embedded wave viewer see Exploring Designs with the Embedded Wave Viewer for more details First you identify an output of interest in the dataflow pane then use time cursors in the wave viewer pane to identify events that contribute to the output The process for tracing events is as follows 1 d 8 Log all signals before starting the simulation add log r After running a simulation for some period of time open the Dataflow window and the wave viewer pane Add a process or signal of interest into the dataflow pane if adding a signal find its driving process Select the process and all signals attached to the selected process will appear in the wave viewer pane Place a time cursor on an edge of inter
552. t working library By default this is the library named work To change the current working library you can use vcom work and specify the name of the desired target library Predefined Libraries Certain resource libraries are predefined in standard VHDL The library named std contains the packages standard env and textio which should not be modified The contents of these packages and other aspects of the predefined language environment are documented in the JEEE Standard VHDL Language Reference Manual Std 1076 Refer also to Using the TextIO Package A VHDL use clause can be specified to select particular declarations in a library or package that are to be visible within a design unit during compilation A use clause references the compiled version of the package not the source ModelSim User s Manual v6 3g 135 May 2008 Design Libraries Specifying Resource Libraries By default every VHDL design unit is assumed to contain the following declarations LIBRARY std work USE std standard all To specify that all declarations in a library or package can be referenced add the suffix all to the library package name For example the use clause above specifies that all declarations in the package standard in the design library named std are to be visible to the VHDL design unit immediately following the use clause Other libraries or packages are not visible unless they are explicitly specified using a library or use clause
553. t Process Where Error Occurred Active Processes Ee ree BS lt Ready gt INITIAL 19 top Double click the highlighted process to open a Source editor window A blue arrow will point to the statement where the simulation stopped executing Figure 7 3 Figure 7 3 Blue Arrow Indicates Where Code Stopped Executing E C Tutorial SIGSEGY example top syv 12 module top 13 14 class C 15 int x 16 endclass 17 16 C obj 19 mp initial obj x 5 20 21 endmodule x g g top sv al gt You may then look for null values in the ModelSim Locals window Figure 7 4 which displays data objects declared in the current or local scope of the active process ModelSim User s Manual v6 3g 191 May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs Figure 7 4 null Values in the Locals Window The null value in Figure 7 4 indicates that the object handle for obj was not properly constructed with the new operator Negative Timing Check Limits By default ModelSim supports negative timing check limits in Verilog setuphold and recrem system tasks Using the no_neg_tcheck argument with the vsim command causes all negative timing check limits to be set to zero Models that support negative timing check limits must be written properly if they are to be evaluated correctly These timing checks specify delayed versions of the input ports which are used for functional evaluatio
554. t a veriusertfs table does exist then only those system tasks and functions listed in the veriusertfs table will be defined e If an init_usertfs function does not exist and a veriusertfs table does not exist but a vlog startup routines table does exist then only those system tasks and functions and callbacks registered by functions in the vlog startup routines table will be defined As a result when PLI and VPI applications exist in the same application object file they must be registered in the same manner VPI registration functions that would normally be listed in a vlog startup routines table can be called from an init usertfs function instead Registering DPI Applications DPI applications do not need to be registered However each DPI imported or exported task or function must be identified using SystemVerilog import DPI C or export DPI C syntax Examples of the syntax follow export DPI C task tl task tl input int i output int o end task import DPI C function void fl input int i output int o Your code must provide imported functions or tasks compiled with an external compiler An imported task must return an int value 1 indicating that it is returning due to a disable or 0 indicating otherwise These imported functions or objects may then be loaded as a shared library into the simulator with either the command line option sv_lib lib or sv liblist bootstrap file For example
555. t dataset changes If locked to both a dataset and a context e g test top foo the pane will update only when that specific context changes You specify the dataset to which the pane is locked by selecting File gt Environment Restricting the Dataset Prefix Display The default for dataset prefix viewing is set with a variable in pref tcl PrefMain DisplayDatasetPrefix Setting the variable to 1 will display the prefix setting it to 226 ModelSim User s Manual v6 3g May 2008 Recording Simulation Results With Datasets Saving at Intervals with Dataset Snapshot 0 will not It is set to 1 by default Either edit the pref tcl file directly or use the Tools gt Edit Preferences command to change the variable value Additionally you can restrict display of the dataset prefix if you use the environment nodataset command to view a dataset To display the prefix use the environment command with the dataset option you won t need to specify this option if the variable noted above is set to 1 The environment command line switches override the pref tcl variable Saving at Intervals with Dataset Snapshot Dataset Snapshot lets you periodically copy data from the current simulation WLF file to another file This is useful for taking periodic snapshots of your simulation or for clearing the current simulation WLF file based on size or elapsed time Once you have logged the appropriate objects select Tools Dataset Snapshot Wave w
556. t notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation Christian Michelsen Research AS makes no representations about the suitability of this software for any purpose It is provided as is without express or implied warranty This software application may include third party content icons from www famfamfam com which is distributed under the Creative Commons Attribution License 2 5 Attribution 2 5 CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE LEGAL SERVICES DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN ATTORNEY CLIENT RELATIONSHIP CREATIVE COMMONS PROVIDES THIS INFORMATION ON AN AS IS BASIS CREATIVE COMMONS MAKES NO WARRANTIES REGARDING THE INFORMATION PROVIDED AND DISCLAIMS LIABILITY FOR DAMAGES RESULTING FROM ITS USE Refer to the license file in your install directory install directory docs legal cc2 5 license pdf End User License Agreement The latest version of the End User License Agreement is available on line at www mentor com terms_conditions enduser cfm IMPORTANT INFORMATION USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY END USER
557. t open already You can also right click an object name and add it to the List or Wave window or the current log file Figure 2 17 Objects Pane data_in oooo0000000000 data spl 01111010 data sp2 00111011001111 data_sp3 oooooo00000000 data_sp4 01110110011110 data dpl 01111010 4 7 sto gt 6 St 4 5 St gt 4 St 4 3 St 4 2 cm A A EEEEE Filtering the Objects List You can filter the objects list by name or by object type Filtering by Name To filter by name undock the Objects pane from the Main window and start typing letters in the Contains field in the toolbar Figure 2 18 Objects Filter Ti 0s Contains e As you type the objects list filters to show only those signals that contain those letters 62 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Source Window Figure 2 19 Filtering the Objects List by Name File Edit View Add Tools Window data_in Packed Array Intemal data sp 01111010 Net Intemal the objects list filters dynamically data sp2 00111011001111 Net Internal to show only objects that match your data_sp3 Net Internal entry data sp4 0111011001111010 Net Internal data dp 01111010 Net Internal 7 St Net Internal 5 St Net Internal 5 sti Net Internal 4 Stl Net Internal 3 Sti Net Internal 2 Sto Net Internal 1 ot Net Internal 0 St Net Intemal To display all objects again click the Eraser icon to clear
558. taining the text for which you are searching The other method for inserting bookmarks is to right click a line number and select Add Remove Bookmark To remove a bookmark right click the line number and select Add Remove Bookmark again Customizing the Source Window You can customize a variety of settings for Source windows For example you can change fonts spacing colors syntax highlighting and so forth To customize Source window settings select Tools gt Edit Preferences This opens the Preferences dialog Select Source Windows from the Window List 72 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Transcript Window Figure 2 29 Preferences Dialog for Customizing Source Window Preferences EN X By Window By Name a gt r Window List rSource Color Scheme Dataflow Windows Category General Text Settings Editor Fonts Active Process Window Files courier New m foz Objects Window Code Browser Document text Courier New B B 7 bird ih Window Document Types Regular Text B Sample Default Selected Text Regular Text Printing Foreground a Fonts Background Spacing Cxx Macro PSL Tcl x gt VHDL 93 i verilog 95 VHDL Templates Verilog2005 use upper case key words XML use lower case key words Tahoma 8 Choose Restore default fonts tt Sample Text 0123456789ABCDEFUWXxZz The Quic
559. task or function The following fields are ignored by ModelSim Verilog int forwref char tfveritool char tferrmessage int hash struct t tfcell left p struct t tfcell right p char namecell p int warning printed s tfcell p tfcell The various callback functions checktf sizetf calltf and misctf are described in detail in the IEEE Std 1364 The simulator calls these functions for various reasons All callback functions are optional but most applications contain at least the calltf function which is called when the system task or function is executed in the Verilog code The first argument to the callback functions is the value supplied in the data field many PLI applications don t use this field The type field defines the entry as either a system task USERTASK or a system function that returns either a register USERFUNCTION or a real USERREALFUNCTION The tfname field is the system task or function name it must begin with The remaining fields are not used by ModelSim Verilog On loading of a PLI application the simulator first looks for an init usertfs function and then a veriusertfs array If init usertfs is found the simulator calls that function so that it can call mti RegisterUserTF for each system task or function defined The mti RegisterUserTF function is declared in veriuser h as follows ModelSim User s Manual v6 3g 419 May 2008 Verilog PLI VPI DPI Registering PLI Applica
560. tch the local clk0O but be delayed by 100 ps library IEEE modelsim lib use IEEE std logic 1164 a11 use modelsim lib util all entity testbench is end architecture only of testbench is signal clkO std logic begin gen clkO0 process begin clkO lt 1 after 0 ps O after 20 ps wait for 40 ps end process gen clk0 drive sig process process begin init signal driver clk0 testbench uut blkl clk init signal driver clk0 testbench uut blk2 clk mti transport wait end process drive sig process end open open 1 100 ps 302 ModelSim User s Manual v6 3g May 2008 Signal Spy init_signal_spy init signal spy This reference section describes the following e VHDL Procedure init signal spy e Verilog Task S init signal spy e SystemC Function init signal spy The init signal spy call mirrors the value of a VHDL signal Verilog register net or SystemC signal called the src object onto an existing VHDL signal Verilog register or SystemC signal called the dest object This allows you to reference signals registers or nets at any level of hierarchy from within a VHDL architecture or Verilog or SystemC module e g a testbench The init signal spy call only sets the value onto the destination signal and does not drive or force the value Any existing or subsequent drive or force of the destination signal by some other means will
561. tched as long as a timing constraint has not been violated Optional arguments not included in the task must be indicated as null arguments by using commas For example recrem posedge CLK D 2 4 tcheck_cond The recrem task does not specify notifier or tstamp_cond but does include a tcheck_cond argument Notice that there are no commas after the tcheck_cond argument Using one or more commas after the last argument results in an error Negative Timing Constraint Algorithm The ModelSim negative timing constraint algorithm attempts to find a set of delays such that the data net is valid when the clock or control nets transition and the timing checks are satisfied The algorithm is iterative because a set of delays that satisfies all timing checks for a pair of inputs can cause misordering of another pair where both pairs of inputs share a common input When a set of delays that satisfies all timing checks is found the delays are said to converge When none of the delay sets cause convergence the algorithm pessimistically changes the timing check limits to force convergence Basically the algorithm zeroes the smallest negative setup recovery limit If a negative setup recovery doesn t exist then the algorithm zeros the smallest negative hold removal limit After zeroing a negative limit the delay calculation procedure is repeated If the delays do not converge the algorithm zeros another negative limit repeating the proces
562. te 276 debug flow post simulation 276 debugging null value 190 SIGSEGV 190 debugging the design overview 28 default binding BindAtCompile ini file variable 375 disabling 146 ModelSim User s Manual v6 3g May 2008 ABCDEFGHIJKLMNOPQRSTUVWXYZ default binding rules 145 Default editor changing 364 DefaultForceKind ini file variable 382 DefaultRadix ini file variable 383 DefaultRestartOptions ini variable 383 DefaultRestartOptions variable 402 delay delta delays 146 modes for Verilog models 203 Delay solution convergence 195 DelayFileOpen ini file variable 383 deleting library contents 131 delta collapsing 228 delta simulator state variable 403 deltas in List window 266 referencing simulator iteration as a simulator state variable 403 dependent design units 140 descriptions of HDL items 72 design library creating 131 logical name assigning 132 mapping search rules 134 resource type 129 VHDL design units 139 working type 129 design object icons described 37 design units 129 DEVICE matching to specify path delays 321 dialogs Runtime Options 395 Direct Programming Interface 417 directories moving libraries 134 disable signal spy 295 DisableOpt ini file variable 372 375 display preferences Wave window 250 displaymsgmode ini file variable 399 distributed delay mode 203 dividers Wave window 254 DLL files loading 429 431 ModelSim User s Manual v6 3
563. ted with Projects 1 Select Compile gt Compile Order or select it from the context menu in the Project tab Figure 4 8 Setting Compile Order Compile Order x M Current Order util vhd cache v E JEU rp p m m a E JE JE memory v proc v set vhd top vhd 2 Drag the files into the correct order or use the up and down arrow buttons Note that you can select multiple files and drag them simultaneously Auto Generating Compile Order Auto Generate is supported for HDL only designs The Auto Generate button in the Compile Order dialog see above determines the correct compile order by making multiple passes over the files It starts compiling from the top if a file fails to compile due to dependencies it moves that file to the bottom and then recompiles it after compiling the rest of the files It continues in this manner until all files compile successfully or until a file s can t be compiled for reasons other than dependency Files can be displayed in the Project tab in alphabetical or compile order by clicking the column headings Keep in mind that the order you see in the Project tab is not necessarily the order in which the files will be compiled Grouping Files You can group two or more files in the Compile Order dialog so they are sent to the compiler at the same time For example you might have one file with a bunch of Verilog define statements and a second fil
564. tep tf putlongp tf iputlongp tf putp tf iputp tf putrealp tf iputrealp tf read restart tf real to long tf rosynchronize tf irosynchronize tf scale longdelay tf scale realdelay tf setdelay tf isetdelay tf setlongdelay tf isetlongdelay tf setrealdelay tf isetrealdelay tf setworkarea tf isetworkarea tf sizep tf isizep tf spname tf ispname tf strdelputp tf istrdelputp tf strgetp tf istrgetp tf strgettime tf strlongdelputp tf istrlongdelputp tf strrealdelputp tf istrrealdelputp tf subtract long tf synchronize tf isynchronize tf testpvc flag tf itestpvc flag tf text tf typep tf itypep tf unscale longdelay tf unscale realdelay tf warning tf write save SystemVerilog DPI Access Routines ModelSim SystemVerilog supports nearly all routines defined in the svdpi h file defined in the IEEE Std 1800 2005 ModelSim User s Manual v6 3g May 2008 443 Verilog PLI VPI DPI Verilog XL Compatible Routines The exception relates to open arrays as described in section F 11 Open Arrays specifically e F 11 2 Array Querying Functions The tool supports the following functions o SvLeft svRight svLow svHigh svIncrement svSize and svDimensions e F 11 4 Access to actual functions The tool supports the following functions o svGetArrayPtr and svSizeOfArray The tool does not support the following functions and will produce a message stating that it is Not implemented
565. test sdi 18 Waming vsim SDF 3240 test sdi 18p Entity vhdichk does 3040 not have a genetic named setup d ck noedge negedge Timnglhecks b i PM Enor 3 test sdi 18 CER celis v 15 setup d 20 ns posedge ck 25 ns 8 ns EX celis v 15 setup d 40 ns posedge clk 45 ns 8 ns Fa cells 16 fhold posedge clk 25 ns dns 9 ns tf Warring 3 Table 2 9 Message Viewer Tasks Task Action Display a detailed description of the right click the message text then message select View Verbose Message Open the source file and add a bookmark to double click the object name s the location of the object s Change the focus of the Workspace and double click the hierarchical Objects panes reference Open the source file and set a marker at the double click the file name line number GUI Elements of the Message Viewer Tab This section describes the GUI elements specific to the Message Viewer tab ModelSim User s Manual v6 3g 7T May 2008 Graphical User Interface Transcript Window Column Descriptions Messages contains the organized tree structure of the sorted messages as well as when expanded the text of the messages Time displays the time of simulation when the message was issued Objects displays the object s related to the message if any Region displays the hierarchical region related to the message if any File Info displays the filename related
566. text object can refer to any of the following Table 1 3 Definition of Object by Language Language An object can be block statement component instantiation constant generate statement generic package signal alias or variable Verilog function module instantiation named fork named begin net task register or variable SystemVerilog In addition to those listed above for Verilog class package program interface array directive property or sequence property sequence directive or endpoint Standards Supported ModelSim VHDL implements the VHDL language as defined by IEEE Standards 1076 1987 1076 1993 and 1076 2002 ModelSim also supports the 1164 1993 Standard Multivalue Logic System for VHDL Interoperability and the 1076 2 1996 Standard VHDL Mathematical Packages standards Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with the 1076 specs ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364 1995 and 1364 2005 ModelSim Verilog also supports a partial implementation of System Verilog P1800 2005 see lt install_dir gt modeltech docs technotes sysvlog note for implementation details Both PLI Programming Language Interface and VCD Value Change Dump are supported for ModelSim users In addition all products support SDF 1 0 through 4 0 except the NETDELAY statement VITAL 2 2b VITAL 95 IEEE 1076 4
567. tfs function the lt init_function gt specified on the command line should be ModelSim User s Manual v6 3g 429 May 2008 Verilog PLI VPI DPI Compiling and Linking C Applications for PLI VPI DPI veriusertfs For the Verilog VPI the init function should be vlog_startup_routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL When executing cl commands in a DO file use the NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to stderr Writing the logo causes Tcl to think an error occurred If you have Cygwin installed make sure that the Cygwin link exe executable is not in your search path ahead of the Microsoft Visual C link executable If you mistakenly bind your dll s with the Cygwin link exe executable the d will not function properly It may be best to rename or remove the Cygwin link exe file to permanently avoid this scenario e MinGW gcc 3 2 3 gcc c l lt install_dir gt include app c gcc shared Bsymbolic o app dll app o L lt install_dir gt win32 Imtipli The ModelSim tool requires the use of the MinGW gcc compiler rather than the Cygwin gcc compiler MinGW gcc is available on the ModelSim FTP site Remember to add the path to your gcc executable in the Windows environment variables DPI Imports on Windows Platforms C When linking the shared objects be sure to specify one link exp
568. th must begin with a or The path must be contained within double quotes ModelSim User s Manual v6 3g 307 May 2008 Signal Spy signal_force 308 value Required string Specifies the value to which the dest_object is to be forced The specified value must be appropriate for the type The value can be a sequence of character literals or as a based number with a radix of 2 8 10 or 16 For example the following values are equivalent for a signal of type bit_vector 0 to 3 e 1111 character literal sequence e 281111 binary radix e 10 15 decimal radix e 16 F hexadecimal radix rel_time Optional time Specifies a time relative to the current simulation time for the force to occur The default is 0 force_type Optional forcetype or integer Specifies the type of force that will be applied For the VHDL procedure the value must be one of the following default which is freeze for unresolved objects or drive for resolved objects deposit drive freeze For the Verilog task the value must be one of the following 0 default which is freeze for unresolved objects or drive for resolved objects 1 deposit 2 drive 3 freeze For the SystemC function the value must be one of the following 0 default which is freeze for unresolved objects or drive for resolved objects 1 deposit 2 drive 3 freeze See the force command for further details on force type ca
569. th the GlobalSharedObjectList variable in the modelsim ini file This variable allows user C code in other shared objects to refer to symbols in a shared object that has been marked as global All shared objects marked as global are loaded by the simulator earlier than any non global shared objects PLI Example The following example is a trivial but complete PLI application hello c include veriuser h static PLI INT32 hello io printf Hi there n return 0 S tfcell veriusertfs usertask 0 0 0 hello 0 Shello 0 last entry must be 0 hello v module hello initial Shello endmodule Compile the PLI code for the Solaris operating system 434 ModelSim User s Manual v6 3g May 2008 oe oe ld G Bsymbolic o hello sl hello o ile the Verilog code vlib work vlog hello v Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 run all Hi there VSIM 2 quit Com oe O oe VPI Example cc c I install dir modeltech include hello c Verilog PLIAVPI DP VPI Example The following example is a trivial but complete VPI application A general VPI example can be found in install dir modeltech examples verilog vpi hello c include vpi user h static PLI INT32 hello PLI BYTE8 param vpi printf Hello world n return 0 void Registe
570. that has been loaded into ModelSim is called a dataset One common example of a dataset is a wave log format WLF file hat has been reopened for viewing In particular you can save any ModelSim simulation to a wave log format WLF file for future viewing or comparison to a current simulation A WLF file is a recording of a simulation run that is written as an archive file in binary format and used to drive the debug windows at a later time The files contain data from logged objects such as signals and variables and the design hierarchy in which the logged objects are found You can record the entire design or choose specific objects A WLF file provides you with precise in simulation and post simulation debugging capability You can reload any number of WLF files for viewing or comparing to the active simulation You can also create virtual signals that are simple logical combinations or functions of signals from different datasets Each dataset has a logical name to indicate the dataset to which a command applies This logical name is displayed as a prefix The current active simulation is prefixed by sim WLF datasets are prefixed by the name of the WLF file by default ModelSim User s Manual v6 3g 219 May 2008 Recording Simulation Results With Datasets Saving a Simulation to a WLF File Figure 8 1 shows two datasets in the Wave window The current simulation is shown in the top pane along the left side and is indicated by the s
571. the Dataflow Window You can use any of the following methods to add objects to the Dataflow window e drag and drop objects from other windows e use the Navigate menu options in the Dataflow window e use the add dataflow command e double click any waveform in the Wave window display The Navigate menu offers four commands that will add objects to the window e View region clear the window and display all signals from the current region e Add region display all signals from the current region without first clearing the window e View all nets clear the window and display all signals from the entire design e Add ports add port symbols to the port signals in the current region When you view regions or entire nets the window initially displays only the drivers of the added objects You can easily view readers as well by selecting an object and invoking Navigate Expand net to readers A small circle above an input signal on a block denotes a trigger signal that is on the process sensitivity list Exploring the Connectivity of the Design A primary use of the Dataflow window is exploring the physical connectivity of your design One way of doing this is by expanding the view from process to process This allows you to see the drivers readers of a particular signal net or register You can expand the view of your design using menu commands or your mouse To expand with the mouse simply double click a signal regist
572. the PLI see Third Party PLI Applications In addition you may write your own PLI VPI DPI applications Implementation Information This chapter describes only the details of using the PLI VPI DPI with ModelSim Verilog and SystemVerilog e ModelSim SystemVerilog implements DPI as defined in IEEE Std P1800 2005 e PLI Implementation Verilog implements the PLI as defined in the IEEE Std 1364 2001 with the exception of the acc handle datapath routine The acc handle datapath routine is not implemented because the information it returns is more appropriate for a static timing analysis tool e VPI Implementation The VPI is partially implemented as defined in the IEEE Std 1364 2005 and IEEE Std 1800 2005 The list of currently supported functionality can be found in the following file install dir docs technotes Verilog VPI note The simulator allows you to specify whether it runs in a way compatible with the IEEE Std 1364 2001 object model or the combined IEEE Std 1364 2005 IEEE Std 1800 2005 object models By default the simulator uses the combined 2005 object models This control is accessed through the vsim plicompatdefault switch or the PliCompatDefault variable in the modelsim ini file ModelSim User s Manual v6 3g 417 May 2008 Verilog PLI VPI DPI Implementation Information The following table outlines information you should know about when performing a simulation with VPI and HDL files using the two different
573. ting a VCD File There are two flows in ModelSim for creating a VCD file e One flow produces a four state VCD file with variable changes in 0 1 x and z with no strength information e The other flow produces an extended VCD file with variable changes in all states and strength information and port driver data Both flows will also capture port driver changes unless filtered out with optional command line arguments Flow for Four State VCD File First compile and load the design cd modeltech examples misc 96 vlib work vlog counter v tcounter v 96 vsim test counter Next with the design loaded specify the VCD file name with the vcd file command and add objects to the file with the vcd add command VSIM 1 gt ved file myvcdfile vcd VSIM 2 vcd add test counter dut VSIM 3 run VSIM 4 gt quit f ModelSim User s Manual v6 3g 329 May 2008 Value Change Dump VCD Files Using Extended VCD as Stimulus There will now be a VCD file in the working directory Flow for Extended VCD File First compile and load the design cd modeltech examples misc 96 vlib work 96 vlog counter v tcounter v 96 vsim test counter Next with the design loaded specify the VCD file name and objects to add with the vcd dumpports command VSIM 1 gt ved dumpports file myvcdfile vcd test counter dut VSIM 3 run VSIM 4 gt quit f There will now be an extended VCD file called myvcdfile vcd in the working directory
574. tion of the modelsim ini file See Simulation Control Variables for more details Parses any command line arguments that were included when you started ModelSim and reports any problems Defines the following environment variables e use MODEL TECH TCL if it exists else e set MODEL TECH TCL MODEL TECH y tcl e set TCL_LIBRARY MODEL_TECH_TCL tcl8 3 e set TK_LIBRARY MODEL_TECH_TCL Ak8 3 e setITCL LIBRARY MODEL TECH TCLJitcl3 0 e setITK LIBRARY MODEL TECH TCLJitk3 0 e set VSIM LIBRARY MODEL TECH TCLyvsim Initializes the simulator s Tcl interpreter Checks for a valid license a license is not checked out unless specified by a modelsim ini setting or command line option The next four steps relate to initializing the graphical user interface Sets Tcl variable MTI LIB DIR MODEL TECH TCL Loads MTI LIB DIR vsim pref tcl Loads GUI preferences project file etc from the registry Windows or HOME modelsim UNIX Searches for the modelsim tcl file by evaluating the following conditions e use MODELSIM TCL environment variable if it exists Gf MODELSIM TCL is a list of files each file is loaded in the order that it appears in the list else ModelSim User s Manual v6 3g May 2008 System Initialization Initialization Sequence e use modelsim tcl else e use HOME modelsim tcl if it exists That completes the initialization sequence Also note the following about the modelsim ini file When
575. tions void mti RegisterUserTF p tfcell usertf The storage for each usertf entry passed to the simulator must persist throughout the simulation because the simulator de references the usertf pointer to call the callback functions We recommend that you define your entries in an array with the last entry set to O If the array is named veriusertfs as is the case for linking to Verilog XL then you don t have to provide an init usertfs function and the simulator will automatically register the entries directly from the array the last entry must be 0 For example S tfcell veriusertfs usertask 0 0 0 abc calltf 0 Sabc usertask 0 0 0 xyz calltf 0 Sxyz 0 last entry must be 0 l Alternatively you can add an init_usertfs function to explicitly register each entry from the array void init_usertfs p_tfcell usertf veriusertfs whil usertf gt type mti_RegisterUserTF usertf It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs function Since PLI applications are dynamically loaded by the simulator you must specify which applications to load each application must be a dynamically loadable library see Compiling and Linking C Applications for PLI VPI DPI The PLI applications are specified as follows note that on a Windows platform the file extension would be dll e Asa list in the Veriuser entry in the modelsim ini file
576. tions Compiler Directives Blocks System T asks and Fur Stimulus Generators NM C ringbuf h H control vhd hy Untitled 1 Some of the fields such as module name in the example above are to be replaced with names you type Other fields can be expanded by double clicking and still others offer a context menu of options when double clicked The example below shows the menu that appears when you double click module item then select gate instantiation 68 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Source Window Figure 2 26 Language Template Context Menus Language Templates X New Design Wizard Create Testbench 1 ERE Primitive module item declaration gt Declarations module instantiation Statements m ation n input gate Instantiations generated instantialit n output gate aba Directives Bike enable gate System Tasks and Fur pullup Stimulus Generators pulldown mos switch cmos switch pass switch pass enable switch Setting File Line Breakpoints with the GUI You can easily set file line breakpoints in your source code by clicking your mouse cursor in the BP breakpoint column of a Source window Click the left mouse button in the BP column next to a red line number and a red ball denoting a breakpoint will appear Figure 2 27 Figure 2 27 Breakpoint in the Source Window Ih C Tutorialfexamples tutorials verilog basicSimulation counter v 27 for i 4 b0 carry 4
577. titution Placing a command in square brackets will cause that command to be evaluated first and its results returned in place of the command An example is set a 25 set b 11 setc 3 echo the result is expr a b c will output the result is 12 This feature allows VHDL variables and signals and Verilog nets and registers to be accessed using examine lt radix gt name The name substitution is no longer supported Everywhere name could be used you now can use examine value radix name which allows the flexibility of specifying command options The radix specification is optional ModelSim User s Manual v6 3g 349 May 2008 Tcl and Macros DO Files Tcl Command Syntax Command Separator A semicolon character works as a separator for multiple commands on the same line It is not required at the end of a line in a command sequence Multiple Line Commands With Tcl multiple line commands can be used within macros and on the command line The command line prompt will change as in a C shell until the multiple line command is complete In the example below note the way the opening brace is at the end of the if and else lines This is important because otherwise the Tcl scanner won t know that there is more coming in the command and will try to execute what it has up to that point which won t be what you intend if exa sig a 001122 echo Signal value matches do macro 1
578. to load the application s symbols At this point all of the application s symbols should be visible You can now set breakpoints in and single step through your application code ModelSim User s Manual v6 3g 447 May 2008 Verilog PLI VPI DPI Debugging PLI VPI DPI Application Code 448 ModelSim User s Manual v6 3g May 2008 Appendix D Command and Keyboard Shortcuts This appendix is a collection of the keyboard and command shortcuts available in the ModelSim GUI Command Shortcuts e You may abbreviate command syntax but there s a catch the minimum number of characters required to execute a command are those that make it unique Remember as we add new commands some of the old shortcuts may not work For this reason ModelSim does not allow command name abbreviations in macro files This minimizes your need to update macro files as new commands are added e Multiple commands may be entered on one line if they are separated by semi colons For example vlog nodebug ports level3 v level2 v vlog nodebug top v The return value of the last function executed is the only one printed to the transcript This may cause some unexpected behavior in certain circumstances Consider this example vsim c do run 20 simstats quit f top You probably expect the simstats results to display in the Transcript window but they will not because the last command is quit f To see the return values of intermediate commands
579. to the cause of the message and in some cases the line number in parentheses Category displays a keyword for the various categories of messages which are as follows Display SDF VITAL FLI Timing Check TCHK WLF PA User Misc MISC PLI VCD 1 Related to Verilog display system tasks 2 Related to messagelog system tasks Severity displays the message severity such as Warning Note or Error Timing Check Kind displays additional information about timing checks Assertion Start Time Assertion Name Verbosity displays verbosity information from messagelog system tasks Id displays the message number Message Viewer Menu Items 78 Source opens the source file in the MDI window and in some cases takes you to the associated line number Verbose Message displays the Verbose Message dialog box containing further details about the selected message Object Declaration opens and highlights the object declaration related to the selected message Filter displays the Message Viewer Filter Dialog Box which allows you to create specialized rules for filtering the Message Viewer ModelSim User s Manual v6 3g May 2008 Graphical User Interface Transcript Window e Clear Filter restores the Message Viewer to an unfiltered view by issuing the messages clearfilter command e Display Reset resets the display of the Message Viewer tab e Display Options displays the Message Viewer
580. to use this software for any purpose on any computer system and to alter it and redistribute it subject to the following restrictions 1 The author is not responsible for the consequences of use of this software no matter how awful even if they arise from flaws in it 2 The origin of this software must not be misrepresented either by explicit claim or by omission Since few users ever read sources credits must appear in the documentation 3 Altered versions must be plainly marked as such and must not be misrepresented as being the original software Since few users ever read sources credits must appear in the documentation 4 This notice may not be removed or altered Copyright c 2001 Mike Barcroft mike FreeBSD org gt All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DI
581. tor The symptoms of such a misbinding can be difficult to detect Generally the misbound function silently returns an unexpected or incorrect value To determine if you have this type of name aliasing problem consult the C library documentation either the online help or man pages and look for function names that match any of your export function names You should also review any other shared objects linked into your simulation and look for name aliases there To get a comprehensive list of your export functions you can use vsim dpiheader option and review the generated header file Troubleshooting a Missing DPI Import Function DPI uses C function linkage If your DPI application is written in C it is important to remember to use extern C declaration syntax appropriately Otherwise the C compiler will produce a mangled C name for the function and the simulator is not able to locate and bind the DPI call to that function Also if you do not use the Bsymbolic argument on the command line for specifying a link the system may bind to an incorrect function resulting in unexpected behavior For more information see Correct Linking of Shared Libraries with Bsymbolic Simplified Import of FLI PLI C Library Functions In addition to the traditional method of importing FLI PLI C library functions a simplified method can be used you can declare VPI and FLI functions as DPI C imports When you declare VPI and FLI functions a
582. ts e g address radix data radix etc by creating a DO file With the memory tab active select File gt Save As The Save memory format dialog box opens where you can specify the name for the saved file By default it is named mem do The file will contain all open memory instances and their formats To load it at a later time select File gt Load Direct Address Navigation You can navigate to any address location directly by editing the address in the address column Double click on any address type in the desired address and hit Enter The address display scrolls to the specified location Splitting the Memory Contents Pane To split a memory contents window into two screens displaying the contents of a single memory instance so any one of the following e select Memories gt Split Screen if the Memory Contents Pane is docked in the Main window e select View gt Split Screen if the Memory Contents Pane is undocked e right click in the pane and select Split Screen from the pop up menu This allows you to view different address locations within the same memory instance simultaneously Figure 2 16 Split Screen View of Memory Contents mem 00000000 00000006 0000000c 00000012 00000018 0000001e 00000024 0000002a 00000000 00000006 o000000c 00000012 00000018 000000le 00000024 D0000002a 00101000 00101110 00110100 00111010 01000000 01000110 01001100 01010010 00101000 00101110
583. ts in a hierarchical tree format The Transcript pane tracks command history and messages and provides a command line interface where you can enter ModelSim commands The Objects pane displays design objects such as signals nets generics etc in the current design scope ModelSim User s Manual v6 3g May 2008 Graphical User Interface Main Window Workspace The Workspace provides convenient access to projects libraries design files compiled design units simulation dataset structures and Waveform Comparison objects It can be hidden or displayed by selecting View gt Workspace menu item The Workspace can display the types of tabs listed below Project tab Shows all files that are included in the open project Refer to Projects for details Library tab Shows design libraries and compiled design units To update the current view of the library select a library and then Right click gt Update See Managing Library Contents for details on library management Structure tabs Shows a hierarchical view of the active simulation and any open datasets There is one tab for the current simulation named sim and one tab for each open dataset See Viewing Dataset Structure for details An entry is created by each object within the design When you select a region in a structure tab it becomes the current region and is highlighted The Source Window and Objects Pane change dynamically to reflect the information for the c
584. ty above that declaration would be hidden because component entity names cannot be overloaded As a result we implemented the following rules for determining default binding e If performing default binding at load time search the libraries specified with the Lf argument to vsim e Ifadirectly visible entity has the same name as the component use it e If an entity would be directly visible in the absence of the component declaration use it e If the component is declared in a package search the library that contained the package for an entity with the same name If none of these methods is successful ModelSim will also do the following e Search the work library e Search all other libraries that are currently visible by means of the library clause e If performing default binding at load time search the libraries specified with the L argument to vsim Note that these last three searches are an extension to the 1076 standard Disabling Default Binding If you want default binding to occur only via configurations you can disable ModelSim s normal default binding methods by setting the RequireConfigForAllDefaultBinding variable in the modelsim ini to 1 true Delta Delays Event based simulators such as ModelSim may process many events at a given simulation time Multiple signals may need updating statements that are sensitive to these signals must be executed and any new events that result from these statements must then b
585. u Can View in the Wave Window The following types of objects can be viewed in the Wave window VHDL objects indicated by a dark blue diamond signals aliases process variables and shared variables Verilog objects indicated by a light blue diamond nets registers variables and named events The GUI displays inout variables of a clocking block separately where the output of the inout variable is appended with o for example you would see following two objects clockl cl input portion of the inout cl clockl cl__o output portion of the inout cl This display technique also applies to the Objects window Verilog transactions indicated by a blue four point star Virtual objects indicated by an orange diamond virtual signals buses and functions see Virtual Objects for more information The data in the object values pane is very similar to the Objects window except that the values change dynamically whenever a cursor in the waveform pane is moved At the bottom of the waveform pane you can see a time line tick marks and the time value of each cursor s position As you click and drag to move a cursor the time value at the cursor location is updated at the bottom of the cursor You can resize the window panes by clicking on the bar between them and dragging the bar to a new location Waveform and signal name formatting are easily changed via the Format menu You can reuse any formatting changes you make by
586. u select Tools gt List Preferences the Modify Display Properties dialog appears ModelSim User s Manual v6 3g 265 May 2008 Waveform Analysis Configuring New Line Triggering in the List Window Figure 9 33 Setting Trigger Properties Modify Display Properties list E lol x Deltas ExpandDeltas Colapse Delas No Deltas Trigger On Iv Signal Change Strobe First Strobe at o ns Strobe Period 0 ns m Trigger Gating Use Gating Expression Use Expression Builder Expression On Duration o ns DK Cancel Apply The following table summaries the triggering options Table 9 6 Triggering Options Description Deltas Choose between displaying all deltas Expand Deltas displaying the value at the final delta Collapse Delta You can also hide the delta column all together No Delta however this will display the value at the final delta Strobe trigger Specify an interval at which you want to trigger data display Trigger gating 266 Use a gating expression to control triggering see Using Gating Expressions to Control Triggering for more details ModelSim User s Manual v6 3g May 2008 Waveform Analysis Configuring New Line Triggering in the List Window Using Gating Expressions to Control Triggering Trigger gating controls the display of data based on an expression Triggering is enabled once the gating ex
587. ugging information about FLI PLI VPI function calls set to any value before invoking the simulator MTI LIB DIR 468 identifies the path to all Tcl libraries installed with ModelSim ModelSim User s Manual v6 3g May 2008 System Initialization Initialization Sequence Table F 2 Environment Variables Accessed During Startup Environment variable Purpose MTI_VCO_MODE determines which version of ModelSim to use on platforms that support both 32 and 64 bit versions when ModelSim executables are invoked from the modeltech bin directory by a Unix shell command using full path specification or PATH search MODELSIM_TCL identifies the pathname to a user preference file e g C nodeltech nodelsim tcl can be a list of file pathnames separated by semicolons Windows or colons UNIX note that user preferences are now stored in the modelsim file Unix or registry Windows ModelSim will still read this environment variable but it will then save all the settings to the modelsim file when you exit the tool Initialization Sequence The following list describes in detail ModelSim s initialization sequence The sequence includes a number of conditional structures the results of which are determined by the existence of certain files and the current settings of environment variables In the steps below names in uppercase denote environment variables except MTI LIB DIR which is a Tcl variable Instances of NAME
588. ulation Compiling Verilog Files module testbench timeunit ins timeprecision 10ps bit d 1 clk 0 wire q initial for int cycles 0 cycles lt 100 cycles t 100 clk clk design dut q d clk endmodule Contents of design v module design output bit q input bit d clk timeunit ins timeprecision 10ps always posedge clk q d endmodule Compile the design incrementally as follows ModelSim gt vlog testbench sv Top level modules testbench ModelSim gt vlog sv test1 v Top level modules dut Note that the compiler lists each module as a top level module although ultimately only testbench is a top level module If a module is not referenced by another module compiled in the same invocation of the compiler then it is listed as a top level module This is just an informative message and can be ignored during incremental compilation The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator For example vlog top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Automatic Incremental Compilation with incr The most efficient method of incremental compilation is to manually compile only the modules that have changed However this is not always convenient especially if your source files have compiler directi
589. ulator variable precede it with a V For example now will not be interpreted as the current simulator time Special Considerations for the now Variable For the when command special processing is performed on comparisons involving the now variable If you specify when now 100 the simulator will stop at time 100 regardless of the multiplier applied to the time resolution You must use 64 bit time operators if the time value of now will exceed 2147483647 the limit of 32 bit numbers For example if gt Time now 2us See Simulator Tcl Time Commands for details on 64 bit time operators 404 ModelSim User s Manual v6 3g May 2008 Appendix A Location Mapping Pathnames to source files are recorded in libraries by storing the working directory from which the compile is invoked and the pathname to the file as specified in the invocation of the compiler The pathname may be either a complete pathname or a relative pathname Referencing Source Files with Location Maps ModelSim tools that reference source files from the library locate a source file as follows e Ifthe pathname stored in the library is complete then this is the path used to reference the file e Ifthe pathname is relative then the tool looks for the file relative to the current working directory If this file does not exist then the path relative to the working directory stored in the library is used This method of referencing source files gener
590. un command to begin simulation For more information see Verilog and System Verilog Simulation and VHDL Simulation The basic simulator commands are e add wave e force e bp e run e step Step 5 Debugging the Design Numerous tools and windows useful in debugging your design are available from the ModelSim GUI In addition several basic simulation commands are available from the command line to assist you in debugging your design describe drivers 28 ModelSim User s Manual v6 3g May 2008 Introduction Modes of Operation examine e force e log e show Modes of Operation Many users run ModelSim interactively pushing buttons and or pulling down menus in a series of windows in the GUI graphical user interface But there are really three modes of ModelSim operation the characteristics of which are outlined in the following table Table 1 2 Use Modes ModelSim use Characteristics How ModelSim is invoked mode interactive has graphical via a desktop icon or from the OS command windows push buttons shell prompt Example menus and a command OS vsim line in the transcript Default mode Command line interactive command with c argument at the OS command prompt line no GUI Example OS vsim c non interactive batch at OS command shell prompt using redirection script no windows or of standard input Example interactive command line C vsim vfiles v infile gt outfile
591. uphold posedge clk posedge t 20 12 NOTIFIER clk_dly t_dly reports a timing violation when posedge f occurs in the violation region 20 12 With the delayed timing checks argument the violation region between the delayed inputs is t_dly clk_dly Although the check is performed on the delayed inputs the timing check violation message is adjusted to reference the undelayed inputs Only the report time of the violation message is noticeably different between the delayed and undelayed timing checks By far the greatest difference between these modes is evident when there are conditions on a delayed check event because the condition is not implicitly delayed Also timing checks 200 ModelSim User s Manual v6 3g May 2008 specified without explicit delayed signals are delayed if necessary when they reference an input that is delayed for a negative timing check limit Verilog and SystemVerilog Simulation Simulating Verilog Designs Other simulators perform timing checks on the delayed inputs To be compatible ModelSim supports both methods Verilog XL Compatible Simulator Arguments The simulator arguments listed below are equivalent to Verilog XL arguments and may ease the porting of a design to ModelSim See the vsim command for a description of each argument talt path delays filename maxdelays mindelays multisource int delays tno cancelled e msg tno neg tchk tno notifier tno path edge tno
592. urce Window Transcript Window Workspace displays waveforms provides easy access to projects libraries compiled design units memories etc Wave Window Workspace The windows and panes are customizable in that you can position and size them as you see fit and ModelSim will remember your settings upon subsequent invocations See Navigating the Graphic User Interface for more details 36 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Design Object Icons and Their Meaning Design Object Icons and Their Meaning The color and shape of icons convey information about the language and type of a design object Table 2 2 shows the icon colors and the languages they indicate Table 2 2 Design Object Icons Icon color Design Language light blue Verilog or SystemVerilog dark blue VHDL orange virtual object Here is a list of icon shapes and the design object types they indicate Table 2 3 Icon Shapes and Design Object Types icon shape example design object type square any scope VHDL block Verilog named block SC module class interface task function etc circle 2 process valued object signals nets registers etc diamond an editable waveform created with the waveform editor with red dot star transaction The color of the star for each transaction depends on the language of the region in which the transaction stream occurs dark blue for VHDL
593. urrent region This feature provides a useful method for finding the source code for a selected region because the system keeps track of the pathname where the source is located and displays it automatically without the need for you to provide the pathname Also when you select a region in the structure pane the Process Window is updated The Active Processes window will in turn update the Locals Window Objects can be dragged from the structure tabs to the Dataflow List and Wave windows You can toggle the display of processes by clicking in a Structure tab and selecting View gt Filter gt Processes You can also control implicit wire processes using a preference variable By default Structure tabs suppress the display of implicit wire processes To enable the display of implicit wire processes set PrefMain HideImplicitWires to 0 select Tools gt Edit Preferences By Name tab and expand the Main object Files tab Shows the source files for the loaded design You can disable the display of this tab by setting the PrefMain ShowFilePane preference variable to 0 See Simulator GUI Preferences for information on setting preference variables Memories tab Shows a hierarchical list of all memories in the design This tab is displayed whenever you load a design containing memories When you double click a memory on the tab a memory contents page opens in the MDI frame See Memory Panes ModelSim User s Manual v6 3g 41 M
594. us defined as follows e Ready Indicates that the process is scheduled to be executed within the current delta time If you select a Ready process it will be executed next by the simulator e Wait Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time out period 48 ModelSim User s Manual v6 3g May 2008 Graphical User Interface lt Done gt Indicates that the process has executed a VHDL wait statement without a time out or a lt Done gt Indicates that the process has executed a VHDL wait statement without a time out or a sensitivity list The process will not restart during the current simulation run Call Stack Pane The Call Stack pane displays the current call stack when you single step your simulation or when the simulation has encountered a breakpoint When debugging your design you can use the call stack data to analyze the depth of function calls which include Verilog functions and tasks and VHDL functions and procedures that led up to the current point of the simulation Accessing the Call Stack Pane View gt Call Stack Figure 2 9 Call Stack Pane Call stack EE Fa C 0 Module bot 30 C Questal estcase stackView callstack sv 7e83a722 1 Function f3 rae P ileal rere vu em rr semp er sv 7e83a41f 2 Function f2 20 C QuestaT estcases calistackView callstack sv 7e83a18f 3 Functio
595. using the O0 argument to vcom e Value Range 0 e Default off 0 ModelSim User s Manual v6 3g 375 May 2008 Simulator Variables Simulator Control Variables Explicit This variable enables the resolving of ambiguous function overloading in favor of the explicit function declaration not the one automatically created by the compiler for each type declaration e Value Range 0 1 e Default on 1 IgnoreVitalErrors This variable instructs the tool to ignore VITAL compliance checking errors e Value Range 0 1 e Default off 0 NoCaseStaticError This variable changes case statement static errors to warnings e Value Range 0 1 e Default off 0 NoDebug This variable disables turns off inclusion of debugging info within design units e Value Range 0 1 e Default off 0 NolndexCheck This variable disables run time index checks e Value Range 0 1 e Default off 0 NoOthersStaticError This variable disables errors caused by aggregates that are not locally static e Value Range 0 1 e Default off 0 376 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables NoRangeCheck This variable disables run time range checking e Value Range 0 1 e Default off 0 NoVital This variable disables acceleration of the VITAL packages e Value Range 0 1 e Default off 0 NoVitalCheck This variable disables VITAL compliance checking e Value Range 0 1 e Default off 0 Optim
596. ut SDF options view the structure pane navigate to the model instance select it and enter the environment command This command displays the instance name that should be used in the SDF command line option Mistaking a Component or Module Name for an Instance Label Another common error is to specify the component or module name rather than the instance label For example the following invocation is wrong for the above testbenches vsim sdfmax testbench myasic myasic sdf testbench This results in the following error message Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench myasic Forgetting to Specify the Instance If you leave off the instance altogether then the simulator issues a message for each instance path in the SDF that is not found in the design For example vsim sdfmax myasic sdf testbench ModelSim User s Manual v6 3g 327 May 2008 Standard Delay Format SDF Timing Annotation Troubleshooting Results in Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testbench ul Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE i Jtestbencii ng Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE Jtestbench u3 Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE Jtestbench u4 Error vsim SDF 3250 myasic sdf 0 Failed to find INSTANCE testhendh u5 Warning vsim SDF 3432 myasic sdf This file is probably a
597. utable code e debugging information e dependency information Working Library Versus Resource Libraries Design libraries can be used in two ways 1 asa local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you update your design and recompile A resource library is typically static and serves as a parts source for your design You can create ModelSim User s Manual v6 3g 129 May 2008 Design Libraries Working with Design Libraries your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor Only one library can be the working library Any number of libraries can be resource libraries during a compilation You specify which resource libraries will be used when the design is compiled and there are rules to specify in which order they are searched refer to Specifying Resource Libraries A common example of using both a working library and a resource library is one in which your gate level design and testbench are compiled into the working library and the design references gate level models in a separate resource library The Library Named work The library named work has special attributes within ModelSim it is predefined in the compiler and need not be declared explicitly i e library work It is also the library name used by the compiler as the default destinat
598. utclk BEGIN IF inclk event AND inclk 1 THEN IF we 1 THEN memory write data_in addr END IF END IF IF outclk event AND outclk 1 THEN data out lt memory read addr END IF END PROCESS END intarch Source ram_tb vhd Component VHDL testbench for RAM memory exampl Remarks Simple VHDL example random access memory RAM LIBRARY ieee USE ieee std_logic_1164 ALL USE ieee numeric_std ALL ENTITY ram_tb IS END ram tb ARCHITECTURE testbench OF ram tb IS Component declaration single port RAM COMPONENT sp syn ram protected GENERIC data width positive 8 addr width positive 3 PORT inclk IN std logic outclk IN std logic we IN std logic addr IN unsigned addr width 1 DOWNTO 0 data in IN std logic vector data width 1 DOWNTO 0 data out OUT std logic vector data width 1 DOWNTO 0 END COMPONENT ModelSim User s Manual v6 3g May 2008 Intermediate signals and constants SIGNAL addr unsigned 19 DOWNTO 0 SIGNAL inaddr unsigned 3 DOWNTO 0 SIGNAL outaddr unsigned 3 DOWNTO 0 SIGNAL data_in unsigned 31 DOWNTO 0 SIGNAL data_inl std_logic_vector 7 DOWNTO 0 SIGNAL data_spl std_logic_vector 7 DOWNTO 0 SIGNAL we std_logic SIGNAL clk std_logic CONSTANT clk_pd time 100 ns BEGIN instantiations of single port RAM architectures All architectures behav quival
599. vars vcd checkpoint dumpall vcd file dumpfile ved flush dumpflush vcd limit dumplimit vcd off dumpoff ved on dumpon ModelSim User s Manual v6 3g 333 May 2008 Value Change Dump VCD Files VCD Commands and VCD Tasks ModelSim also supports extended VCD dumpports system tasks The table below maps the VCD dumpports commands to their associated tasks Table 13 2 VCD Dumpport Commands and System Tasks VCD dumpports commands vcd dumpports vcd dumpportsall VCD system tasks dumpports dumpportsall ved dumpportsflush dumpportsflush vcd dumpportslimit vcd dumpportsoff dumpportslimit dumpportsoff vcd dumpportson dumpportson ModelSim supports multiple VCD files This functionality is an extension of the IEEE Std 1364 specification The tasks behave the same as the IEEE equivalent tasks such as dumpfile dumpvar etc The difference is that fdumpfile can be called multiple times to create more than one VCD file and the remaining tasks require a filename argument to associate their actions with a specific file Table 13 3 VCD Commands and System Tasks for Multiple VCD Files VCD commands VCD system tasks vcd add file lt filename gt fdumpvars vcd checkpoint filename fdumpall vcd files lt filename gt fdumpfile vcd flush lt filename gt fdumpflush vcd limit lt filename gt fdumplimit
600. ve If any include directives occur within a protected region and you use vlog protect to compile the compiler generates a copy of the include file with a vp or a svp extension and encrypts the entire contents of the include file For example if we have a header file header v with the following source code initial begin a lt b b lt C end and the file we want to encrypt top v contains the following source code module top protect include header v endprotect endmodule then when we use the vlog protect command to compile the source code of the header file will be encrypted If we could decrypt the resulting work top vp file it would look like module top protect initial begin a lt D lt c end 102 ModelSim User s Manual v6 3g May 2008 Protecting Your Source Code Usage Models for Protecting Source Code endprotect endmodule In addition vlog protect creates an encrypted version of header v in work header vp In the vencrypt flow see Delivering IP Code with Undefined Macros any include statements will be treated as text just like any other source code and will be encrypted with the other source code So if we used the vencrypt utility on the top v file above the resulting work top vp file would look like the following if we could decrypt it module top protect include header v endprotect endmodule The vencrypt utility will not create an encr
601. ve interdependencies such as macros In this case you may prefer to compile 172 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Compiling Verilog Files your entire design along with the incr argument This causes the compiler to automatically determine which modules have changed and generate code only for those modules The following is an example of how to compile a design with automatic incremental compilation 96 vlog incr top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Now suppose that you modify the functionality of the or2 module 96 vlog incr top v and2 v or2 v Skipping module top Skipping module and2 Compiling module or2 Top level modules top The compiler informs you that it skipped the modules top and and2 and compiled or2 Automatic incremental compilation is intelligent about when to compile a module For example changing a comment in your source code does not result in a recompile however changing the compiler command line arguments results in a recompile of all modules Note o e o o ee s Changes to your source code that do not change functionality but that do affect source code line numbers such as adding a comment line will cause all affected modules to be recompiled This happens because debug information must be kept current so that ModelSim can trace back to the correct area
602. view msgviewer e Open a dataset dataset open WLF file Viewing Data in the Message Viewer Tab By default the tool writes transcripted messages during elaboration and runtime to both the transcript and the WLF file By writing to the WLF file the Message Viewer tab is able to organize the messages for your analysis You can control what messages are available in the Message Viewer tab in the following ways e Elaboration and runtime messages Use the msgmode argument to vsim The syntax is vsim msgmode both tran wlf where the default setting is both You can also use the msgmode variable in the modelsim ini file e Display system task messages Use the displaymsgmode argument to vsim The syntax is vsim displaymsgmode both tran wlfj where the default setting is tran You can also use the displaymsgmode variable in the modelsim ini file 76 ModelSim User s Manual v6 3g May 2008 Graphical User Interface Transcript Window Message Viewer Tab Tasks Figure 2 30 and Table 2 9 provide an overview of the Message Viewer and several tasks you can perform Figure 2 30 Message Viewer Tab Column Headings Right click to view heading options Left click to toggle sort order Misc 2 4 Note 1 wamng 1 A vsm 3473 Component instance u7 vlogbuf2 is not bound 3473 Ons 0 hl SDF 2 FA _ Warming 2 A Waning vsim SDF 3240 test sdi 18 Entity vhdichk does 3549
603. w Preferences Dialog 251 Figure 9 21 Grid amp Timeline Tab of Wave Window Preferences Dialog 252 Figure 9 22 Clock Cycles in Timeline of Wave Window 000 02 ee aee 252 Figure 9 25 Changing Signal Radix iiis uie due eR yess padee sere deals Sade 253 Figure 9 24 Separate Signals with Wave Window Dividers 0 000 5 254 Figure 9 25 Splitting Wave Window Panes 02 ee eee eee eee 256 Figure 9 26 Fill in the name of the group in the Group Name field 257 Figure 9 27 Wave groups denoted by red diamond 0 0 00 e eee eee 257 Figure 9 28 Modifying List Window Display Properties 259 Figure 9 29 List Signal Properties Dialog 0 0 0 eee cece eee eee 260 Figure 9 30 Changing the Radix in the List Window 0 0 0 0 0c eee ee eee 261 Figure 9 31 Signals Combined to Create Virtual Bus 0 0 00 00 eee eee 264 Figure 9 32 Line Triggering in the List Window 265 Figure 9 33 Setting Trigger Properties 2 esecs when eda de ERE RSR A ENT REESE ERERSA 266 Figure 9 34 Trigger Gating Using Expression Builder 0 0000 00005 267 Figure 9 35 Modifying the Breakpoints Dialog llle 271 Figure 9 36 Signal Breakpoint Dialog 0 0 eee eee ee 271 Figure 9 37 Breakpoints in the Source Window else 272 Figure 9 38 File Breakpoint Dialog Box 0 cece eee eee eee nee
604. w window is as follows 1 Load your design 2 Log all signals in the design or any signals that may possibly contribute to the unknown value log r will log all signals in the design 3 Add signals to the Wave window or wave viewer pane and run your design the desired length of time 4 Puta Wave window cursor on the time at which the signal value is unknown StX In Figure 10 5 Cursor 1 at time 2305 shows an unknown state on signal f out 5 Add the signal of interest to the Dataflow window by doing one of the following o double click on the signal s waveform in the Wave window o right click the signal in the Objects window and select Add to Dataflow Selected Signals from the popup menu o select the signal in the Objects window and select Add Dataflow Selected Signals from the menu bar 6 In the Dataflow window make sure the signal of interest is selected 7 Trace to the source of the unknown by doing one of the following 282 o If the Dataflow window is docked make one of the following menu selections Tools Trace TraceX Tools Trace TraceX Delay ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Common Tasks for Dataflow Debugging Tools gt Trace gt ChaseX or Tools gt Trace gt ChaseX Delay o If the Dataflow window is undocked make one of the following menu selections Trace gt TraceX Trace gt TraceX Delay Trace gt ChaseX or Trace gt ChaseX Delay
605. weak 0 0 0 0 0 1 1 1 3 weak 4 weak Given the driver data above and use of 1364 strength ranges here is what the VCD file output would look like pO 7 0 0 pO 7 0 0 pO 7 0 0 pL 7 0 0 pB 7 6 0 pu 0 5 lt 0 pl 0 4 0 ModelSim User s Manual v6 3g May 2008 343 Value Change Dump VCD Files Capturing Port Driver Data 344 ModelSim User s Manual v6 3g May 2008 Chapter 14 Tcl and Macros DO Files Tcl is a scripting language for controlling and extending ModelSim Within ModelSim you can develop implementations from Tcl scripts without the use of C code Because Tcl is interpreted development is rapid you can generate and execute Tcl scripts on the fly without stopping to recompile or restart ModelSim In addition if ModelSim does not provide the command you need you can use Tcl to create your own commands Tcl Features Using Tcl with ModelSim gives you these features e command history like that in C shells e full expression evaluation and support for all C language operators e a full range of math and trig functions e support of lists and arrays e regular expression pattern matching procedures e the ability to define your own commands e command substitution that is commands may be nested robust scripting language for macros Tcl References Two books about Tcl are Tcl and the Tk Toolkit
606. whenever timing is met the correct data value is latched Consider the following timing checks specified relative to CLK setuphold posedge CLK D 10 20 notifier dCLK dD setuphold posedge CLK negedge RST 40 50 notifier dCLK dRST 196 ModelSim User s Manual v6 3g May 2008 Verilog and SystemVerilog Simulation Simulating Verilog Designs 0 10 20 30 40 RST violation VVVVVAAVANA D violation XXXXXXXXXX CLK To solve the timing checks specified relative to CLK the following delay values are necessary Rising Falling dCLK 3l 31 dD 20 20 dRST 0 0 The simulator s intermediate delay solution shifts the violation regions to overlap the reference events 0 10 20 30 40 45 dRST violation VVVVVVVAVVVAVVAN dD violation XXXXXXXXXX dCLK Notice that no timing is specified relative to negedge CLK but the dCLK falling delay is set to the dCLK rising delay to minimumize pulse rejection on dCLK Pulse rejection that occurs due to delayed input delays is reported by WARNING 3819 Scheduled event on delay net dCLK was cancelled Now consider the following case where a new timing check is added between D and RST and the simulator cannot find a delay solution Some timing checks are set to zero In this case the new timing check is not annotated from an SDF file and a default setuphold limit of 1 1 is used setuphold posedge CLK D 10 20 notifier dCLK dD setuphold posedge CLK negedge
607. will read all files found User Defined Symbols You can also define your own symbols using an ASCII symbol library file format for defining symbol shapes This capability is delivered via Concept Engineering s Nlview M widget Symlib format The Dataflow window will search the current working directory and inside each library referenced by the design for the file dataflow sym Any and all files found will be given to the Nlview widget to use for symbol lookups Again as with the built in symbols the DU name and optional process name is used for the symbol lookup Here s an example of a symbol for a full adder 284 ModelSim User s Manual v6 3g May 2008 Debugging with the Dataflow Window Dataflow Concepts symbol adder structural DEF port a in loc 12 15 0 15 pinattrdsp name cl 2 15 8 port b in loc 12 15 0 15 X pinattrdsp name cl 2 15 8 port cin in loc 20 40 20 28 pinattrdsp name uc 19 26 8 port cout out loc 20 40 20 28 pinattrdsp name lc 19 26 8 port sum out loc 63 0 510 pinattrdsp name cr 49 0 8 path 10 007 path 0 7 0 35 path 0 35 51 17 path 51 17 51 17 path 51 17 0 35 path 0 35 0 7 N path 0 7 10 0 Port mapping is done by name for these symbols so the port names in the symbol definition must match the port names of the Entity ModulelProcess in the case of the process it s the signal names that the process reads writes Note 2222 LLLLLL
608. y behave differently With the Tcl source command the DO file is executed exactly as if the commands in it were typed in by hand at the prompt Each time a breakpoint is hit the Source window is updated to show the breakpoint This behavior could be inconvenient with a large DO file containing many breakpoints When a do command is interrupted by an error or breakpoint it does not update any windows and keeps the DO file locked This keeps the Source window from flashing scrolling and moving the arrow when a complex DO file is executed Typically an onbreak resume command is used to keep the macro running as it hits breakpoints Add an onbreak abort command to the DO file if you want to exit the macro and update the Source window ModelSim User s Manual v6 3g 361 May 2008 Tcl and Macros DO Files Macros DO Files 362 ModelSim User s Manual v6 3g May 2008 Appendix A Simulator Variables This appendix documents the following types of variables Environment Variables Variables referenced and set according to operating system conventions Environment variables prepare the ModelSim environment prior to simulation Simulator Control Variables Variables used to control compiler simulator and various other functions Simulator State Variables Variables that provide feedback on the state of the current simulation Variable Settings Report The report command returns a list of current settings for either the
609. y default This feature caches blocks of the WLF file to reduce redundant file I O If the cache is made smaller or disabled least recently used data will be freed to reduce the cache to the specified size e WLFSimCacheSize Specify the size in megabytes of the WLF reader cache for the current simulation dataset only This makes it easier to set different sizes for the WLF reader cache used during simulation and those used during post simulation debug If neither wlfsimcachesize nor WLFSimCacheSize are specified the wlfcachesize or WLFCacheSize settings will be used e WLF Collapse Mode WLF event collapsing has three settings disabled delta time o When disabled all events and event order are preserved o Delta mode records an object s value at the end of a simulation delta iteration only Default o Time mode records an object s value at the end of a simulation time step only Limiting the WLF File Size The WLF file size can be limited with the WLFSizeLimit simulation control variable in the modelsim ini file or with the wlfslim switch for the vsim command Either method specifies the number of megabytes for WLF file recording A WLF file contains event header and symbol portions The size restriction is placed on the event portion only When ModelSim exits the entire header and symbol portion of the WLF file is written Consequently the resulting file will be larger than the size specified with wlfslim If used in conjun
610. y for the binary executables MODEL_TECH is set to this path MODELSIM identifies the pathname of the modelsim ini file MGC WD identifies the Mentor Graphics working directory MGC LOCATION MAP MODEL TECH TCL identifies the pathname of the location map file set by ModelSim if not defined identifies the pathname of all Tcl libraries installed with ModelSim HOME identifies your login directory UNIX only MGC HOME identifies the pathname of the MGC tool suite TCL LIBRARY identifies the pathname of the Tcl library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology TK LIBRARY identifies the pathname of the Tk library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology ITCL LIBRARY identifies the pathname of the incr Tcl library set by ModelSim to the same path as MODEL TECH TCL must point to libraries supplied by Model Technology ITK LIBRARY identifies the pathname of the incr Tk library set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology VSIM LIBRARY identifies the pathname of the Tcl files that are used by ModelSim set by ModelSim to the same pathname as MODEL TECH TCL must point to libraries supplied by Model Technology MTI COSIM TRACE creates an mti trace cosim file containing deb
611. y produces a file with a vp or a svp extension to distinguish it from other non encrypted Verilog and SystemVerilog files respectively The file extension may be changed for use with simulators other than ModelSim The original file extension is preserved if the directive lt path gt argument is used with vencrypt or if a directive is used in the file to be encrypted With the h filename argument for vencrypt the IP vendor may specify a header file that can be used to encrypt a large number of files that do not contain the pragma protect or protect information about how to encrypt the file Instead encryption information is provided in the filename specified by h filename This argument essentially concatenates the header file onto the beginning of each file and saves the user from having to edit hundreds of files in order to add in the same pragma protect to every file For example vencrypt h encrypt head top v cache v gates v memory v concatenates the information in the encrypt_head file into each verilog file listed The encrypt head file may look like the following pragma protect data method aes128 cbc pragma protect author IP Provider pragma protect key keyowner MTI key method rsa pragma protect key keyname MGC DVT MTI pragma protect key block encoding enctype base64 pragma protect begin Notice there is no pragma protect end expression in the
612. y valid path may include environment variables e Default MODEL TECH ieee modelsim lib This variable sets the path to the library containing Model Technology VHDL utilities such as Signal Spy e Value Range any valid path may include environment variables e Default SMODEL TECH modelsim lib std This variable sets the path to the VHDL STD library e Value Range any valid path may include environment variables Default MODEL_TECH std std_developerskit This variable sets the path to the libraries for MGC standard developer s kit e Value Range any valid path may include environment variables e Default MODEL_TECH std_developerskit synopsys This variable sets the path to the accelerated arithmetic packages e Value Range any valid path may include environment variables e Default MODEL_TECH synopsys 370 ModelSim User s Manual v6 3g May 2008 Simulator Variables Simulator Control Variables sv_std This variable sets the path to the SystemVerilog STD library e Value Range any valid path may include environment variables e Default MODEL_TECH sv_std verilog This variable sets the path to the library containing VHDL Verilog type mappings e Value Range any valid path may include environment variables e Default MODEL_TECH verilog vital2000 This variable sets the path to the VITAL 2000 library e Value Range any valid path may include environment variables e Default SMODE
613. ypted version of header h When you use vlog protect to generate encrypted files the original source files must all be complete Verilog or SystemVerilog modules or packages Compiler errors will result if you attempt to perform compilation of a set of parameter declarations within a module You can avoid such errors by creating a dummy module that includes the parameter declarations For example if you have a file that contains your parameter declarations and a file that uses those parameters you can do the following module dummy protect include params v contains various parameters include tasks v uses parameters defined in params v endprotect endmodule Then compile the dummy module with the protect switch to generate an encrypted output file with no compile errors vlog protect dummy v After compilation the work library will contain encrypted versions of params v and tasks v called params vp and tasks vp You may then copy these encrypted files out of the work directory to more convenient locations These encrypted files can be included within your design files for example module main include params vp include tasks vp Y ModelSim User s Manual v6 3g 103 May 2008 Protecting Your Source Code Protecting Source Code Using nodebug Protecting Source Code Using nodebug The nodebug argument for both vcom and vlog hides internal model data This allows a model supplier to provide pre

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