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DSP56311 User's Manual

1. Reserved bit Read as zero Write with zero for future compatibility Values after reset 0 0 00 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 CP1 CPO RM SM CE SA FV Core Priority Bit 1 Core Priority Bit 0 Rounding Mode Arithmetic Saturation Mode Instruction Cache Enable Sixteen Bit Arithmetic DO Forever Flag LF DO Loop Flag S Scaling Flag DM Double Precision Multiply L Limit Flag SC Sixteen bit Compatibility E Extension Flag S1 Scaling Mode Bit 1 U Unnormalized Flag SO Scaling Mode Bit O N Negative Flag I Interrupt Mask Bit 1 Z Zero Flag l0 Interrupt Mask Bit 0 V Overflow Flag C Carry Flag Figure 4 4 Status Register Table 4 7 Status Register Bit Definitions Bit Number Bit Name Reset Value Description 23 22 CP 1 0 11 Core Priority Under control of the CDP 1 0 bits in the OMR the CP bits specify the priority of core accesses to external memory These bits are compared against the priority bits of the active DMA channel If the core priority is greater than the DMA priority the DMA waits for a free time slot on the external bus If the core priority is less than the DMA priority the core waits for a free time slot on the external bus If the core priority equals the DMA priority the core and DMA access the external b
2. Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 00 1 0 95K 16K 16K Enabled 16M 0400 BFFF 0000 3FFF 0000 3FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 4 Memory Switch On MSW 00 Cache On 24 Bit Mode 3 12 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Program X Data Y Data FFFFFF FFFFFF FFFFFF External l O Internal I O FFFFCO FFFF80 FFFFgo Internal I O FFF000 FFFooo External Internal Reserved Internal Internal Reserved Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 External 018000 014000 Reserved 00C000 Internal Program RAM 80K 006000 000000 000000 External Internal Reserved Internal X data RAM 24K 006000 000000 Freescale Semiconductor Inc External 00C000 Internal Reserved Internal Y data RAM 24K Memory Maps Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 01 0 0 80K 24K 24K None 16 M 0000 0000 5FFF 0000 5FFF 13FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can
3. 18 ALC 0 Alignment Control The ESSI handles 24 bit fractional data Shorter data words are left aligned to the MSB bit 23 For applications that use 16 bit fractional data shorter data words are left aligned to bit 15 The ALC bit supports shorter data words If ALC is set received words are left aligned to bit 15 in the receive shift register Transmitted words must be left aligned to bit 15 in the transmit shift register If the ALC bit is cleared received words are left aligned to bit 23 in the receive shift register Transmitted words must be left aligned to bit 23 in the transmit shift register NOTE If the ALC bit is set only 8 12 or 16 bit words are used The use of 24 or 32 bit words leads to unpredictable results 17 Reserved Set to 0 for future compatibility 16 12 DC 4 0 Frame Rate Divider Control Control the divide ratio for the programmable frame rate dividers that generate the frame clocks In Network mode this ratio is the number of words per frame minus one In Normal mode this ratio determines the word transfer rate The divide ratio ranges from 1 to 32 DC 00000 to 11111 for Normal mode and 2 to 32 DC 00001 to 11111 for Network mode A divide ratio of one DC 00000 in Network mode is a special case known as On Demand mode In Normal mode a divide ratio of one DC 00000 provides continuous periodic data word transfers A bit length frame sync must be used in this c
4. BG Input Ignored Input Bus Grant An active low input BG must be asserted deasserted synchronous to the internal clock for proper operation BG is asserted by an external bus arbitration circuit when the DSP56311 becomes the next bus master When BG is asserted the DSP56311 must wait until BB is deasserted before taking bus mastership When BG is deasserted bus mastership is typically given up at the end of the current bus cycle This may occur in the middle of an instruction that requires more than one external bus cycle for execution The default operation of this bit requires a setup and hold time as specified in DSP56311 Technical Data the data sheet An alternate mode can be invoked set the asynchronous bus arbitration enable ABE bit Bit 13 in the OMR When this bit is set BG and BB are synchronized internally This eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input BB Input Input Bus Busy A bidirectional active low input output Must be asserted Output and deasserted synchronous to the internal clock BB indicates that the bus is active Only after BB is deasserted can the pending bus master become the bus master and then assert the signal again The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted Called bus parking this allows
5. EFCOP initialisation DMA channel 0 initialisation input request ORG move move move move move rep move move movep movep movep movep movep movep movep movep movep nop nop p Start 0 b 0 a 0 x0 DST COUN x0O x r0 DST ADDRS r FIR LEN 1 y DST_COUNT bO FDBA ADDRS r0 0 i M FCNT FDBA ADDRS y M FDBA FCBA ADDRS y M FCBA FCON y M FCSR SRC_ADDRS x M_DSRO M_FDIR x M_DDRO SRC_COUNT x M_DCOO 51 x M_DORO 5940004 x M DCRO counter for output interrupt FDM memory area clear FDM memory area Destination address FIR length FIR input samples Start Address FIR Coeff Start Address Enable EFCOP to EFCOP DMA source address points to the DATA bank Init DMA destination address Init DMA count to line mode DMA offset reg is l Init DMA control reg to line mode FDIBE fp TS ORRARELEARAERREREREER DRA BRERA R LESS RN GKONOKOR ARRAS AENEAN INANE BAD DST_COUNT endd endd stop_label Motorola do nop jclr 15 y M_FCSR movep y M FDOR x r0 nop nop Enhanced Filter Coprocessor EFCOP 10 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes nop jmp stop label org x SRC ADDRS INCLUDE input asm org y FCBA ADDRS INCLUDE coefs asm 10 7 1 3 DMA Input Interrupt Output
6. 6 18 DSP Side Registers After Reset 20 e eee eee eee neces 6 22 Host Side Register Map o dene m ERE REPRE dae estes E PERPE 6 24 Interface Control Register ICR Bit Definitions 6 25 Command Vector Register CVR Bit Definitions 6 27 Interface Status Register ISR Bit Definitions lesse 6 28 Host Side Registers After Reset 2 eece scene e oh xr RR eee 6 31 HI08 Programming Model DSP Side 0 0 0 eee eee eee 6 32 HI08 Programming Model Host Side 0 0 0 eee eee eee 6 35 ESSI Clock SDUICBS 224 ru ex agua ro une na opt XR RP er p cag 7 4 Mode and Signal Definitions llle 7 5 ESSI Control Register A CRA Bit Definitions 7 14 ESSI Control Register B CRB Bit Definitions 7 19 DSP56311 User s Manual xvii For More Information On This Product Go to www freescale com Tables Table 7 5 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Table 10 7 Table 10 8 Table 10 9 Table 10 10 Table 10 11 Table B 1 Table B 2 Table B 3 Table B 4 Table B 5 Motorola Freescale Semiconductor Inc ESSI Status Register SSISR Bit Definitions 04 7 29 SCI Registers Alter Reset 22 iccesvcseded nde eiderenes Ee e RA D
7. Receive Sync TX 2 Flag1 or drive enb Async RX F S Frame Sync o SYN These signals are identical in sync mode avian X2 Flagi Out or drive enb Sync Mode CRB TE2 CRB OF1 CRA SSC1 Sync Mode CRB SCD2 CRB FSI 1 0 CRB FSR Y TX Word Clock CRA DC4 0 EJ Internal TX Frame Sync 1 to 32 Sync TX RX F S Async TX ES Transmit Control Logic Frame Sync Figure 7 4 ESSI Frame Sync Generator Functional Block Diagram 7 5 2 ESSI Control Register B CRB Control Register B CRB is one of two read write control registers that direct the operation of the ESSI see Figure 7 5 The CRB bit definitions are presented in Table 7 4 CRB controls the ESSI multifunction signals SC 2 0 which can be used as clock inputs or outputs frame synchronization signals transmit data signals or serial I O flag signals 23 22 21 20 19 18 17 16 15 14 13 12 REIE TEIE RLIE TLIE RIE TIE RE TEO TE1 TE2 MOD SYN 11 10 9 8 7 6 5 4 3 2 1 0 CKP FSP FSR FSL1 FSLO SHFD SCKD SCD2 SCD1 SCDO OF1 OFO ESSIO X FFFFB6 ESSI1 X FFFFA6 Figure 7 5 ESSI Control Register B CRB The CRB contains the serial output flag control bits and the direction control bits for the serial control signals Also in the CRB are interrupt enable bits for the receiver and the transmitter Bit settings of the CRB determines
8. Bus Address Attribute Polarity A read write Bus Address Attribute Polarity BAAP control bit that defines whether the AA RAS signal is active low or active high When BAAP is cleared the AA RAS signal is active low useful for enabling memory modules or for DRAM Row Address Strobe If BAAP is set the appropriate AA RAS signal is active high useful as an additional address bit 4 24 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG Boundary Scan Register BSR Table 4 9 Address Attribute Registers AARO AAR3 Bit Definitions Bit Number Bit Name Reset Value Description 1 0 BAT 0 Bus Access Type Read write bits that define the type of external memory DRAM or SRAM to access for the area defined by the BAC 11 0 BYEN BXEN and BPEN bits The encoding of BAT 1 0 is 00 Reserved 01 SRAM access 10 DRAM access 11 Reserved When the external access type is defined as a DRAM access BAT 1 0 10 AA RAS acts as a Row Address Strobe RAS signal Otherwise it acts as an Address Attribute signal External accesses to the default area always execute as if BAT 1 0 01 i e SRAM access 4 9 JTAG Identification ID Register The JTAG ID register is a 32 bit read only factory programmed register that distinguishes the component on a board according to the IEEE 1149 1 standard Figure
9. M STXH EQU FFFF97 M SRXL EQU FFFF98 M STXA EQU FFFF94 M SCR EQU FFFF9C M SSR EQU FFFF93 M SCCR EQU FFFF9B Freescale Semiconductor Inc Host Receive interrupts Enable Host Transmit Interrupt Enable Host Command Interrupt Enable Host Flag 2 Host Flag 3 Host Receive Data Full Host Receive Data Empty Host Command Pending Host Flag 0 Host Flag 1 Host Port GPIO Enable Host Address 8 Enable Host Address 9 Enable Host Chip Select Enable Host Request Enable Host Acknowledge Enable Host Enable Host Request Open Drain mode Host Data Strobe Polarity Host Address Strobe Polarity Host Multiplexed bus select Host Double Single Strobe select Host Chip Select Polarity Host Request Polarity Host Acknowledge Polarity SCI Transmit Data Register high M STXM EQU FFFF96 SCI Transmit Data Register middle M STXL EQU FFFF95 SCI Transmit Data Register low M SRXH EQU S FFFF9A SCI Receive Data Register high M SRXM EQU S FFFF99 SCI Receive Data Register middle SCI Receive Data Register low SCI Transmit Address Register SCI Control Register SCI Status Register SCI Clock Control Register SCI Control Register Bit Flags M WDS EQU 3 7 M WDSO EQU 0 A 10 Word Select Mask WDSO WDS3 Word Select 0 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola M WDS EQU 1 M W
10. 0 0 2 eee eee 10 8 5 Output Sequence for Example D 4 20 0 0 eee eee Appendix A Bootstrap Program A l BOUistap 006 Pr A 2 Internal UO Equates ike se 94 o ERE dasees Seis e EO RS ERE ER EE EE A 3 lnrvsdwedsonr PC Appendix B Programming Reference B 1 B 2 B 3 INDEX Motorola Internal VO Memory M3p vaa seco heed sh ERE RARI ERERERE XE EE ER AREE Interrupt Sources and Priorities Programming SDSBlS uoa dash Sr ed cepP khe ib Pres d ES REPRE Contents For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Motorola DSP56311 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figures Figurel 1 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 5 1 Figure 5 2 Figure 5 3 Motorola DSP56311 Block Diagram 0 0 cece eee ee eee 1 11 Signals Identified by Functional Group eese 2 3 Memory Switch Off Cache Off 24 Bit Mode Default 3 9 Memory Switch Off Cache On 24 Bit Mode 055 3 10 Memory Switch On
11. 19497 bu L ZIVI poN voul SOA SOA SOA ON 0 peiqeu3 LIXX di VNA JOSseoo0Jg eJiue Interrupt Priority Register Core IPR C Figure B 6 Programming Reference B 17 For More Information On This Product Motorola Go to www freescale com 0 se weibolg paniasay ae Jd44 X d Hadl 4e1si68u INARA Gt 9L ZI 8L 6L Oc le ce ez SOA SOA SOA ON 0 peiqeu3 010S SOA SO SOA ON pajqeuy ddl 0ISS3 Freescale Semiconductor Inc SOA SOA ON 0 dl IOS peiqeu3 O1dH SOA SOA ON Programming Sheets qdl 1S0H peiqeua 0711S Idi HSS3 JOSsoooJg eJlue Interrupt Priority Register Peripherals IPR P Figure B 7 DSP56311 User s Manual Motorola For More Information On This Product B 18 Go to www freescale com Freescale Semiconductor Inc Programming Sheets ei WPeeu dddddd X 1194 49181694 OAN LAW ZAN EAW PAW SAW 93IN Z4 83IN 63IN OLAN EE3IN 04A tA 240 HILX GILX dLSd Nad 009 ead eaa 104409 Tid cL EL VE SI 9l gu 8L 6L Oc Le cc z Se e L o o z dd soyeyuoisinig 040 240 I Z4A 04A sug 101263 UOISIAIG o 4dd 101284 UOISIAIP91g 0Ad dd dd Odd siia 101284 UOISIAIPA
12. External I O Internal I O Internal Reserved External 00C000 Reserved Internal Y data RAM 32K Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 10 1 0 63K 32K 32K Enabled 16M 0400 FFFF 0000 7FFF 0000 7FFF the EFCOP but not by the DMA controller Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and Figure 3 8 Memory Switch On MSW 10 Cache On 24 Bit Mode 3 16 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Memory Maps Program X Data Y Data FFFFFF SFFFFFF External 1 0 Internal I O FFFFCO FFFFFF FFFF80 FFFFgo Internal I O sena SFFFOOO FFF000 Reserved Internal Internal FFOOCO Reserved Reserved FF0000 Bootstrap ROM FF0000 FF0000 External External External 018000 Reserved 00C000 00C000 00C000 00A000 00A000 Internal Program RAM 48K Internal Y data RAM 40K Internal X data RAM 40K 000000 000000 000000 Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 11 0 0 48K 40K 40K None 16M 0000 BFFF 0000 9FFF 0000 9FFF Lowest 10K of
13. Multidrop is a special case of asynchronous data transfer The key difference is that a protocol allows networking transmitters and receivers on a single data transmission line Inter processor messages in a multidrop network typically begin with a destination address All receivers check for an address match at the start of each message Receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message Receivers with an address match can 8 2 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Signals receive the message and optionally transmit an acknowledgment to the sender The particular message format and protocol used are determined by the user s software 8 1 3 1 Transmitting Data and Address Characters To send data the 8 bit data character must be written to the STX register Writing the data character to the STX register sets the ninth bit in the frame to zero which indicates that this frame contains data To send an 8 bit address the address data is written to the STXA register and the ninth bit in the frame is set to one indicating that this frame contains an address 8 1 3 2 Wired OR Mode Building a multidrop bus network requires connecting multiple transmitters to a common wire The Wired OR mode allows this to be done without damaging the transmitters when
14. contiguous PRAM memory locations starting at the specified starting address Motorola Bootstrap Program A 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Code After the program words are read program execution starts from the same address where loading started 32522523225232222222222222222222222522252222222222222222222222252222522522522222225 If MD MC MB MA 1010 then the program RAM is loaded from the SCI interface The number of program words to be loaded and the starting address must be specified The SCI bootstrap code expects to receive 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are received least significant byte first followed by the mid and then by the most significant byte After the program words are received program execution starts in the same address where leading started The SCI 1s programmed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source 1s external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter 3252252322523222222222222222222222522252522222522222222222222252222522522522222225 Operation mode MD MC MB MA 1
15. spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 1 Enable address 9 input HA8EN 1 Enable address 8 input HGEN 0 Host GPIO pins are disabled HIO8CONT bset HEN x M_HPCR Enable the HIO8 to operate as host interface set HEN 1 A 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Code jelr HRDF x M_HSR wait for the program length to be written movep x M_HRX a0 jelr HRDF x M_HSR wait for the program starting address to be written movep x M_HRX r0 move 10 rl do a0 HIOSLOOP set a loop with the downloaded length HIOSLL jset ZHRDEx M HSR HIOSNW Ifnew word was loaded then jump to read that word jelr HFO x M_HSR HIO8LL If HFO 0 then continue with the downloading enddo Must terminate the do loop bra HIOSLOOP HIO8NW movep x M_HRX p r0 Move the new word into its destination location in the program RAM nop pipeline delay HIOSLOOP bra FINISH EPRSCILD jelr 1 omr EPROMLD If MD MC MB MA 1001 go load from EPROM If MD MC MB MA 1011 reserved default to SCI This is the routine that loads from the SCI MD MC MB MA 1010 external SCI clock SCILD
16. FCBA 10 13 FCM 10 4 FCNT 10 7 FCSR 10 8 FDBA 10 12 FDCH 10 13 10 14 FDIR 10 7 FDM 10 4 FDOR 10 7 Filter Coefficient Memory bank 10 2 Filter Data Memory 10 2 FKIR 10 7 FMAC 10 6 initialization 10 2 input data buffer 10 2 interrupt vector table 10 6 memory bank base address pointers 10 2 memory banks 10 4 memory organization 10 4 PMB 10 4 programming model 10 6 Saturation mode 10 6 Sixteen bit Arithmetic mode 10 6 enable disable receive portion of ESSI 7 21 enable disablesan interrupt at beginning of last slot of a frame when ESSI is in Network mode 7 20 Enhanced Filter Coprocessor EFCOP 1 4 1 14 Enhanced Synchronous Serial Interface ESSI 2 15 2 17 7 1 see also ESSI ensure proper operation of the ESSI 7 7 equalization 10 1 ESSI 1 13 2 3 2 15 2 17 5 2 7 1 after reset 7 6 Asynchronous mode 7 21 Asynchronous modes 7 11 asynchronous operating mode 7 11 audio enhancements 7 3 byte format 7 13 Clock Generator 7 17 clock generator 7 11 Clock Sources 7 4 codecs 7 13 configure an ESSI exception 7 9 control and time slot registers 7 6 control direction of SC2 I O signal 7 23 control divide ratio for programmable frame rate dividers 7 16 control fixed divide by eight prescaler in series with variable prescaler 7 16 Control functionality of SC1 signal 7 15 Control Register A 7 14 Control Register A CRA Alignment Control 7 16 Index 2 DSP56311 User s Manual Motorola For More Information On This Product Go to
17. Freescale Semiconductor Inc Host Programmer s Model 6 7 4 Interrupt Vector Register IVR The IVR is an 8 bit read write register that typically contains the interrupt vector number used with MC68000 family processor vectored interrupts Only the host processor can read and write this register The contents of the IVR are placed on the host data bus H 7 0 when both the HREQ and HACK signals are asserted The contents of this register are initialized to 0F by a hardware or software reset This value corresponds to the uninitialized interrupt vector in the MC68000 family The hardware and software reset value of the IVR is 0F 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IV4 IV3 IV2 IV1 IVO Figure 6 17 Interrupt Vector Register IVR 6 7 5 Receive Byte Registers RXH RXM RXL The host processor views the receive byte registers as three 8 bit read only registers the receive high register RXH the receive middle register RXM and the receive low register RXL They receive data from the high middle and low bytes respectively of the HTX register and are selected by the external host address inputs HA 2 0 during a host processor read operation The memory address of the receive byte registers are set by ICR HLEND If ICR HLEND is set the RXH is located at address 7 RXM at 6 and RXL at 5 If ICR HLEND is cleared the RXH is located at address 5 RXM at 6 and RXL at 7 When data is tran
18. Go to www freescale com Freescale Semiconductor Inc Peripherals mapping allows you to program DSP core communication with the HI08 registers using standard instructions and addressing modes 1 9 3 ESSI The DSP56311 provides two independent and identical ESSIs Each ESSI has a full duplex serial port for communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola SPI The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator ESSI capabilities include the following m Independent asynchronous or shared synchronous transmit and receive sections with separate or shared internal external clocks and frame syncs Normal mode operation using frame sync Network mode operation with as many as 32 time slots Programmable word length 8 12 or 16 bits Program options for frame synchronization and clock generation One receiver and three transmitters per ESSI 1 9 4 SCI The SCI provides a full duplex port for serial communication with other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as the RS 232C RS 422 etc This interface uses three dedicated signals transmit da
19. Host Receive Interrupt Enable 0 Disable 1 Enable if HRDF 1 Host Transmit Interrupt Enable 0 Disable 1 Enable if HTDE 1 Host Command Interrupt Enable 0 Disable 1 Enable if HCP 1 Host Flag 2 Host Control Register HCR X FFFFC2 Read Write Reset 0 DSP Side Host Receive Data Full 0 3Wait 1 23 Read Host Transmit Data Empty 0 3Wait 1 3 Write bi Command Pending 3Wait 1 3 Ready Host Flags Read Only Host Staus Register HSR X FFFFC3 Read Only Reset 2 Programming Sheets Host Flag 3 HF1 HFO HCP HTDE HRDF x Reserved Program as 0 Programming Reference For More Information On This Product Go to www freescale com Figure B 10 Host Control and Host Status Registers B 21 Freescale Semiconductor Inc Programming Sheets Host Base Address Register HBAR X FFFFC5 Reset 80 Host Request Open Drain Host GPIO Port Enable HDRQ HROD HREN HEW 0 GPIO Pins Disable 1 GPIO Pin Enable 0 0 1 0 1 1 Host Address Line 8 Enable 1 0 1 0 gt HA8 GPIO 1 HA8 HA8 1 1 1 Host Address Line 9 Enable 0 Strobe Active Low 1 Strobe Active High O HAI GRIO eee ee Host Address Strobe Polarity Host Chip Select Enable 0 Strobe Active Low 1 Strobe Active High 0 gt HCS HAIO GPIO 1 gt HCS HA10 HC8 if HMUX 0 Host Multiplexed Bus 1 HCS HA10 HC10 if HMUX 1 0 Nonmultiplexed 1 Multiplexed Host Dual Data Strobe Host Request Enable 0
20. N write preload first event M write compare TE Clock CLK 2 or prescale CLK TLR N Counter TCR x lt o0 N N 1 M lt M 1 0 EN 1 TCPR DX M TCF Compare Interrupt if TCIE 1 4 TIO pin INV 0 First toggle M M clock periods Second and later toggles 2 clock periods TIO pin INV 1 TOF Overflow Interrupt if TCIE 1 po Figure 9 8 Toggle Mode TRM 0 Motorola Triple Timer Module 9 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 1 4 Timer Event Counter Mode 3 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 1 1 3 Event Counter Timer Input External In Mode 3 the timer counts external events and issues an interrupt if interrupt enable bits are set when the timer counts a preset number of events The timer clock signal can be taken from either the TIO input signal or the prescalar clock output If an external clock is used it must be internally synchronized to the internal clock and its frequency must be less than the DSP56311 internal operating frequency divided by 4 The value of the TCSR INV bit determines whether low to high 0 to 1 transitions or high to low 1 to 0 transitions increment the counter If the INV bit is se
21. Priority H 10 Permitted Exceptions Masked Lowest 0 0 IPL 0 1 2 8 None IPL 1 2 3 IPL O IPL 2 3 IPL 0 1 Highest 1 1 IPL 3 IPL 0 1 2 Scaling Set when a result moves from accumulator A or B to the XDB or YDB buses during an accumulator to memory or accumulator to register move and remains set until explicitly cleared that is the S bit is a sticky bit The logical equations of this bit are dependent on the Scaling mode The scaling bit is set if the absolute value in the accumulator before scaling is gt 0 25 or 0 75 Limit Set if the overflow bit is set or if the data shifter limiter circuits perform a limiting operation In Arithmetic Saturation mode the L bit is also set when an arithmetic saturation occurs in the Data ALU result otherwise it is not affected The L bit is cleared only by a processor reset or by an instruction that specifically clears it i e a sticky bit this allows the L bit to be used as a latching overflow bit The L bit is affected by data movement operations that read the A or B accumulator registers Motorola Core Configuration 4 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Status Register SR Table 4 7 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 5 E 1 Extension Cleared if all the bits of the integer portion of the
22. Single Strobe 1 Dual Strobe 0 HREQ HACK GPIO 1 HREQ HREQ if HDRQ 0 Host Chip Select Polarity 0 HCS Active Low Host Acknowledge Enable HTRQ amp HRRQ Enable 0 HACK GPIO 1 HCS Active High If HDRQ amp HREN 1 HACK HACK Host Request Polarity HRP Host Enable HREQ Active Low 0 gt HIO08 Disable HREQ Active High Pins GPIO HTRQ HRRQ Active Low 1 HI08 Enable HTRQ HRRQ Active High Host Acknowledge Polarity 0 HACK Active Low 1 HACK Active High 0 4 0 1 14 1 1 15 3 12 0 9 8 7 6 5 4 3 2 1 0 Host Port Control HAP HRP HCSP HDDS HMUX HASP HDSP HROD Ye HEN HAEN HREN HCSEN HA9EN HABEN HGEN Register HPCR 0 X FFFFC4 Reset 0 Reserved Program as 0 Figure B 11 Host Base Address and Host Port Control Registers B 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Processor Side Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP Host Transmit Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 DSP Host 1 Host gt DSP HREQ HTRQ HACK HRRQ HREQ HACK HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize Write Only 0 NoAction 1 Initialize DMA mA 6 4 3 2 1 0 INIT
23. Y Data Memory Memory switch mode reallocates of portions of X and Y data RAM as program RAM Bit 7 in the OMR is the MS bit that controls this function as follows Note 3 6 When the MS bit is cleared the Y data memory consists of the default 48K x 24 bit memory space described in the previous section In this default mode the lowest external Y data memory location is 6000 When MS mode bit in the OMR is set a portion of the higher locations of the internal Y memory are switched to internal program memory The memory switch configuration MSW 1 0 bits in the OMR select one of the following options MSWT 1 0 00 The 32K higher locations 4000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 3FFF The Y memory space at the switched locations 4000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 MSWTL 1 0 01 The 24K higher locations 6000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 5FFF The Y memory space at the switched locations 6000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 MSWTL 1 0 10 The 8K higher locations 8000 BFFF of the internal Y memory are switched to internal program memory and therefore the highe
24. 0000 0000 Bit Settings Memory Configuration MSW x Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 11 0 1 48K 40K 40K None 64K 0000 BFFF 0000 9FFF 0000 9FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 19 Memory Switch On MSW 11 Cache Off 16 Bit Mode Motorola Memory Configuration 3 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data 2i dia External I O Internal I O FFCO Reserved FF80 FF80 Internal I O FFFF External External C000 C000 C000 Reserved Reserved A000 A000 Internal Program RAM Internal X data Internal Y data 47K RAM 40K RAM 40K 0400 0000 0000 0000 Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 11 1 1 47K 40K 40K Enabled 64K 0400 BFFF 0000 9FFF 0000 9FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 20 Memory Switch On MSW 11 Cache On 16 Bit Mode 3 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www f
25. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FCNT11 FCNT10 FONT9 FCNT8 FCNT7 FCNT6 FCNT5 FONTA FCNT3 FONT2 FCNT1 FCNTO Reserved bit read as 0 should be written with 0 for future compatibility Figure 10 4 Filter Count FCNT Register Table 10 3 Filter Count FCNT Register Bits Bit Abbr Description 23 12 These bits are reserved and unused They are read as 0 and should be written with O for future compatibility 11 0 FONT _ Filter Count The actual value written to the FONT register must be the number of coefficient values minus one The number of coefficient values is the number of locations used in the FCM For a real FIR filter the number of coefficient values is identical to the number of filter taps For a complex FIR filter the number of coefficient values is twice the number of filter taps 10 3 5 EFCOP Control Status Register FCSR The FCSR is a 24 bit read write register by which the DSP56300 core controls the main operation modes of the EFCOP and monitors the EFCOP status 23 22 21 20 19 18 17 16 15 14 13 12 FDOBF FDIBE FCONT FSAT 11 10 9 8 7 6 5 4 3 2 1 0 FDOIE FDIIE FSCO FPRC FMLC FOM1 FOMO FUPD FADP FLT FEN Reserved bit read as 0 should be written with 0 for future compatibility Motorola DSP56311 User s Manual 10 8 For More Information On This Product Go to www freescale com Freescale Semicond
26. 6 7 1 Interface Control Register IB ciues atre su ES X NO Race iy se ADR 6 24 6 7 2 Command Vector Register CVR lt 20snees sees nse cue hh a nas 6 27 Motorola Contents V For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 7 3 Interface Status Register ISR llleleseeeeeeee A 6 28 6 7 4 Interrupt Vector Register IVR socosezake tbee a berteesrsbetese rxdeedqea 6 30 6 7 5 Receive Byte Registers RXH RXM RXL 0 0 0 0 eee eee 6 30 6 7 6 Transmit Byte Registers TXH TXM TXL 0 0 eee eee eee 6 30 6 7 7 Host Side Registers After Reset 4 402 204des0s40eaeeeeeredabeeees ge Rn 6 31 6 8 Programming Model Quick Reference 0 0 cece eee ee eee 6 32 Chapter Enhanced Synchronous Serial Interface ESSI 7 1 ESSI Enhancements srscoseXoc eR RREER ERR G9 w DepP P be ERR ES Red 7 2 7 2 ESSI Data and Control Signals ou cese etupeRisa naana 7 3 7 2 1 Serial Transmit Data Signal STD 0 0 00 0 eee eee 7 3 7 2 2 Serial Receive Data Signal SRD 20 2 0 cece eee eee ene eee 7 3 7 3 3 Seral Clock SCR enews rerxesdackeR nE i p hEE aod eG a ed Esdras 7 3 7 2 4 serial Control Signal SCO 22 522 indes berbecruh rhce Eher P exa herd adu Ri 7 4 7 2 5 Serial Control Signal SCI censes x eo cere raes ar eu Say e aa 7 5 7 2 6 Serial Control Signal 8C2 suse beads aoe eG ages beads GU EY Ra rg 7 6 7 3 Oper t N ses ed at ragi aea aiaa
27. 8 5 b9998c Sbad8cb be8b2d c7b90 6 Freescale Semiconductor Inc Verification For All Exercises Output Sequence for Examples D 1 D 2 and D 3 10 8 4 Desired Signal for Example D 4 000000 0D310F dc dc Motorola 191 EA7C 25B8E2 30312E 38F46D 3FB327 443031 4642D6 45D849 42F452 3DB126 363E7F 2C 211 DFE8 EA5B 15C13A 08 SFB945D D2CE SEE7E02 SE2066F D69EB2 SCCAE3C SC48F2F SBE8B32 SBAD8D3 B99999 Enhanced Filter Coprocessor EFCOP 10 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Verification For All Exercises dc SBAD8D3 dc SBE8B32 10 8 5 Output Sequence for Example D 4 000000 Sf44c4c See54b3 Se7cd b daed26 cc1071 c7dblc Scdfe45 Motorola DSP56311 User s Manual 10 40 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A Bootstrap Program This appendix lists the bootstrap program for the DSP56311 Motorola posts updates to the bootstrap program on the Worldwide Web at the following URL http www mot com SPS DSP software other html 56301 A 1 Bootstrap Code BOOTSTRAP CODE FOR DSP56311 C Copyright 1999 Motorola Inc Revised March 18 1999 Bootstrap through the Host Interface External EPROM or SCI This is the Bootstrap program contained in the
28. External Access Type AA pin polarity Program space Enable X data space Enable Y data space Enable Reserved Packing Enable Ty Reserved Bit Write to zero for future compatibility Number of Address bit to compare Figure 4 7 Address Attribute Registers AARO AAR3 X F FFFF9 FFFFF6 Table 4 9 Address Attribute Registers AARO AAR3 Bit Definitions Bit Number Bit Name Reset Value Description 23 12 BAC 11 0 0 Bus Address to Compare Read write control bits that define the upper 12 bits of the 24 bit address with which to compare the external address to determine whether to assert the corresponding AA RAS signal This is also true of 16 bit compatibility mode The BNC 3 0 bits define the number of address bits to compare 11 8 BNC 3 0 Bus Number of Address Bits to Compare Specify the number of bits from the BAC bits that are compared to the external address The BAC bits are always compared with the Most Significant Portion of the external address e g if BNC 3 0 0011 then the BAC 11 9 bits are compared to the 3 MSBs of the external address If no bits are specified i e BNC 3 0 0000 the AA signal is activated for the entire 16 M word space identified by the space enable bits BPEN BXEN BYEN but only when the address is external to the internal memory map The combinations BNC 3 0 1111 1110 1101 are reserved Mo
29. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation by jumping to the appropriate interrupt service routine The following DSP core interrupts are possible from the HI08 peripheral m Hostcommand m Transmit data register empty W Receive data register full These interrupts are maskable via the Host Receive Interrupt Enable bit HCR 0 HRIE the Host Transmit Interrupt Enable bit HCR 1 HTIE and the Host Command Interrupt Enable bit HCR 2 2HCIBE respectively Receive Data Full and Transmit Data Empty interrupts move data to from the HTX and HRX data registers The DSP interrupt service routine must read or write the appropriate HIOS8 data register HRX or HTX to clear the interrupt condition Enable DSP Core Interrupts Receive Data Full Transmit Data Empty Host Command Status Figure 6 2 H108 Core Interrupt Operation Host commands allow the host to issue command requests to the DSP by selecting any of 128 DSP interrupt routines for execution For example the host may issue a command via the HI08 that sets up and enables a DMA transfer The DSP56311 processor has reserved interrupt vector addresses for application specific service routines However this flexibility is independent of the data transfer mechanisms in the HIOS and allows the host to force execution of any interrupt handler for example SSI SCI IRQx and so on To enable Host Command interrupts
30. Function 1 1or0 SCI 0 0 GPIO input 0 1 GPIO output 8 7 3 Port E Data Register PDRE The read write PDRE reads or writes data to or from SCI GPIO signals Bits PD 2 0 read or write data to or from the corresponding port signals if they are configured as GPIO If a port signal i is configured as a GPIO input then the corresponding PD i bit reflects the value of this signal If a port signal 1 is configured as a GPIO output then the value of the corresponding PD i bit is reflected on this signal A hardware RESET signal or a software RESET instruction clears all PDRE bits 8 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 7 6 5 4 3 2 1 0 L 5 LL P02 PD PDO Reserved Read as 0 Write with 0 for future compatibility Figure 8 11 Port E Data Register PDRE Motorola Serial Communication Interface SCI 8 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 8 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 9 Triple Timer Module The timers in the DSP56311 internal triple timer module act as timed pulse generators or as pulse width modulators Each timer has a single signal that can function as a GPIO signal or as a ti
31. Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt B 10 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Table B 5 Freescale Semiconductor Inc Interrupt Sources and Priorities Interrupt Source Priorities Within an IPL Continued Priority Interrupt Source DMA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSIO RX Data with Exception Interrupt ESSIO RX Data Interrupt ESSIO Receive Last Slot Interrupt ESSIO TX Data With Exception Interrupt ESSIO Transmit Last Slot Interrupt ESSIO TX Data Interrupt ESSH RX Data With Exception Interrupt ESSI1 RX Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt Lowest SCI Receive Data Highest SCI Transmit Data SCI Idle Line SCI Timer TimerO Overflow Interrupt TimerO Compare Interrupt
32. Inc SCI Programming Model Fcore Divide Prescaler Divide 12 bit Counter By 2 Divide by By2 10r8 CD 11 0 SCP Internal Clock Divide SCI Core Logic by 16 Uses Divide by 16 for Asynchronous Uses Divide by 2 for STIR I Synchronous O If Asynchronous ad Divide by 1 or 16 EUIS COD If Synchronous Divide By 2 Ecore BPS 64 x 7 SCP 1 x CD 1 where SCP Oor1 SCKP SCKP Op CD 000 to FFF SCKP 1p TO SCLK Figure 8 7 SCI Baud Rate Generator 8 6 4 SCI Data Registers The SCI data registers are divided into two groups receive and transmit as shown in Figure 8 8 There are two receive registers a receive data register SRX and a serial to parallel receive shift register There are also two transmit registers a transmit data register called either STX or STXA and a parallel to serial transmit shift register 8 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model SCI Receive Data Register High Read Only SCI Receive Data Register Middle Read Only SCI Receive Data Register Low Read Only SCI Receive Data Shift Register Note SRX is the same register decoded at three different addresses a Receive Data Register SCI Transmit Data Register High Write Only SCI Transmit Data Register Middle Write Only SCI Transmit Data Register Low Write Only SCI
33. Internal I O Equates Register Addresses Of DMA M DSTR EQU FFFFF4 DMA Status Register M DORO EQU FFFFF3 DMA Offset Register 0 M DORI EQU FFFFF2 DMA Offset Register 1 M DOR2 EQU FFFFFI DMA Offset Register 2 M DOR3 EQU FFFFFO DMA Offset Register 3 Register Addresses Of DMAO M DSRO EQU FFFFEF DMAO Source Address Register M DDRO EQU FFFFEE DMAO Destination Address Register M DCO0 EQU FFFFED DMAO Counter M DCRO EQU FFFFEC DMAO Control Register Register Addresses Of DMA1 M DSRI EQU FFFFEB DMA Source Address Register M DDRI EQU FFFFEA DMAI Destination Address Register M DCO EQU FFFFE9 DMAI Counter M DCRI EQU FFFFES DMA Control Register Register Addresses Of DMA2 M DSR2 EQU S FFFFE7 DMA2 Source Address Register M DDR2 EQU FFFFE6 DMA2 Destination Address Register M DCO2 EQU FFFFES DMA2 Counter M DCR2 EQU FFFFE4 DMA2 Control Register Register Addresses Of DMA4 M DSR3 EQU S FFFFE3 DMA3 Source Address Register M DDR3 EQU FFFFE2 DMA3 Destination Address Register M DCO3 EQU FFFFEI DMA3 Counter M DCR3 EQU FFFFEO DMA3 Control Register Register Addresses Of DMA4 M_DSR4 EQU FFFFDF DMA4 Source Address Register M DDR4 EQU FFFFDE DMA4 Destination Address Register M DCO4 EQU FFFFDD DMA4 Counter M DCR4 EQU S FFFFDC DMA4 Control Register Register Addresses Of DMA5 M DSR5 EQU FFFFDB DMAS Source Address Register M D
34. MD The mode input signals MODA MODD and the resulting MA MB MC and MD bits determine which bootstrap mode the DSP56311 enters see Table 4 1 Note To stop the bootstrap in any HI08 bootstrap mode set the Host Flag 0 HFO The loaded user program begins executing from the specified starting address You can invoke the bootstrap program options except modes 0 and 8 at any time by setting the MA MB MC and MD bits in the OMR and jumping to the bootstrap program entry point FF0000 Software can directly set the mode selection bits in the OMR Bootstrap modes 0 and 8 are the normal DSP56311 functioning modes Bootstrap modes 9 A and C F select different specific bootstrap loading source devices In these modes the bootstrap program expects the following data sequence when downloading the user program through an external port 1 Three bytes that specify the number of 24 bit program words to be loaded 2 Three bytes that specify the 24 bit start address where the user program loads in the DSP56311 program memory 3 The user program three bytes for each 24 bit program word Note The three bytes for each data sequence are loaded least significant byte first When the bootstrap program finishes loading the specified number of words it jumps to the specified starting address and executes the loaded program 4 3 Interrupt Sources and Priorities DSP56311 interrupt handling like that for all DSP56300 family members is opt
35. MSB LSB Least Significant 12 bit Data Zero Fill LSB 16 bit Data LSB 24 bit Data NOTES b Transmit Registers Data is received MSB first if SHFD 0 4 bit fractional format ALC 0 32 bit mode is not shown Figure 7 13 ESSI Data Path Programming Model SHFD 1 Motorola Enhanced Synchronous Serial Interface ESSI 7 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 7 5 7 ESSI Transmit Data Registers TX 2 0 ESSIO TX20 TX10 TX00 ESSI1 TX21 TX11 TX01 TX2 TX1 and TXO are 24 bit write only registers Data written into these registers automatically transfers to the transmit shift registers See Figure 7 12 and Figure 7 13 The data transmitted 8 12 16 or 24 bits is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is Bit 23 When ALC is set the MSB is Bit 15 If the transmit data register empty interrupt has been enabled the DSP is interrupted whenever a transmit data register becomes empty Note When data is written to a peripheral device there is a two cycle pipeline delay while any status bits affected by this operation are updated If any of those status bits are read during the two cycle delay the status bit may not reflect the current status For details see the DSP56300 Family Manual Appendix B Polling a Peripheral Device for Write 7 5 8 ESSI Time Slot Register TSR TSR is effective
36. MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 00 1 1 63K 16K 16K Enabled 64K 0400 FFFF 0000 3FFF 0000 3FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 14 Memory Switch On MSW 00 Cache On 16 Bit Mode 3 22 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Memory Maps Program X Data Y Data ail IPEFF External I O Internal I O FFCO FF80 FF80 Internal I O FFFF External External Internal Program RAM oak C000 C000 6000 6000 Internal X data Internal Y data RAM 24K RAM 24K 0000 0000 0000 Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 01 0 1 64K 24K 24K None 64K 0000 FFFF 0000 5FFF 0000 5FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 15 Memory Switch On MSW 01 Cache Off 16 Bit Mode Motorola Memory Configuration 3 23 For More Information On This Product Go to www freescale com Memory Maps FFFF Internal External Program RAM 63K CO000 Reserved 6000 Internal X da
37. MSW 00 Cache Off 24 Bit Mode 3 11 Memory Switch On MSW 00 Cache On 24 Bit Mode 3 12 Memory Switch On MSW 01 Cache Off 24 Bit Mode 3 13 Memory Switch On MSW 01 Cache On 24 Bit Mode 3 14 Memory Switch On MSW 10 Cache Off 24 Bit Mode 3 15 Memory Switch On MSW 10 Cache On 24 Bit Mode 3 16 Memory Switch On MSW 11 Cache Off 24 Bit Mode 3 17 Memory Switch On MSW 11 Cache On 24 Bit Mode 3 18 Memory Switch Off Cache Off 16 Bit Mode 04 3 19 Memory Switch Off Cache On 16 Bit Mode 3 20 Memory Switch On MSW 00 Cache Off 16 Bit Mode 3 21 Memory Switch On MSW 00 Cache On 16 Bit Mode 3 22 Memory Switch On MSW 01 Cache Off 16 Bit Mode 3 23 Memory Switch On MSW 01 Cache On 16 Bit Mode 3 24 Memory Switch On MSW 10 Cache Off 16 Bit Mode 3 25 Memory Switch On MSW 10 Cache On 16 Bit Mode 3 26 Memory Switch On MSW 11 Cache Off 16 Bit Mode 3 27 Memory Switch On MSW 11 Cache On 16 Bit Mode 3 28 Interrupt Priority Register C IPR C X FFFFFF 4 4 7 Interrupt Priority Register P IPR P X SFFFFFE 4 7 DSP56311 Operating Mode Register OMR Format 4 11 Stat s urs erne
38. Operating Modes Freescale Semiconductor Inc Table 4 1 DSP56311 Operating Modes Mode MODD MODC Reset MODB MODA Vector Description 0 0 C00000 Expanded mode Bypasses the bootstrap ROM and the DSP56311 starts fetching instructions beginning at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected default Address C00000 is reflected as address 00000 on Port A signals A0 A17 0 1 FF0000 Reserved 1 0 FF0000 Reserved 1 1 FF0000 Reserved 0 0 FF0000 Reserved 0 1 FF0000 Reserved 1 0 FF0000 Reserved 1 1 FF0000 Reserved 0 0 008000 Expanded mode Bypasses the bootstrap ROM and the DSP56311 starts fetching instructions beginning at address 008000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected 0 1 FF0000 Bootstrap from byte wide memory The bootstrap program loads instructions through Port A from external byte wide memory starting at P D00000 The SRAM memory access type is selected by the values in address attribute register 1 AAR1 Thirty one wait states are inserted between each memory access Address D00000 is reflected as address 00000 on Port A signals A0 A17 The boot program concatenates every 3 bytes read from the external memory into a 24 bit
39. SCI pins RXD TXD SCLK 8 3 SCI Programming Model Data Registers 8 23 SCI Receive Data Registers SRX 8 9 SCI Receive Register SRX 8 23 SCI Serial Clock signal SCLK 8 4 SCI Status Register SSR 8 9 8 17 Idle Line Flag 8 18 Overrun Error Flag 8 18 Parity Error 8 17 Receive Data Register Full 8 18 Received Bit 8 8 17 Transmit Data Register Empty 8 18 Transmitter Empty 8 19 SCI Status Register SSR Bit Definitions 8 17 SCI Transmit Data Address Register STX A 8 9 SCI Transmit Data Registers STX 8 9 SCI Transmit Register STX STX register 8 24 SCK 7 3 SCK signal 7 3 SCLK 8 4 SCLK pin 8 2 8 6 SCLK signal 8 4 SCR 8 12 SCR Control Register SCR Receiver Enable 8 14 SCR register 8 12 select operational mode of the ESSI 7 22 Send Break bit SBK 8 16 Serial Clock 7 3 Serial Clock signal SCK 7 3 Serial Communicaiton Interface SCI indicate whether received byte is an address or data 8 17 Serial Communication Interface 2 19 Asynchronous mode 8 2 enable disable SCI timer interrupt 8 13 Serial Communication Interface SCI Address Mode Wakeup 8 3 bootstrap loading 8 7 byte is ready to transfer from receive shift register to receive data register 8 18 clock generator features 8 19 control clock polarity sourced or received on the clock signal SCLK 8 12 control divide by 32 in the SCI Timer interrupt generator 8 12 crystal frequency 8 6 determine order in which SCI data shift registers shift data in or out 8 16 emp
40. The EFCOP processes the data Then one sample the real magnitude of the input signal is read from the FDOR Magnitude mode is selected by setting both the FCSR FOM bits 10 5 1 1 6 Initialization Before the first sample is processed the EFCOP filter must be initialized that is the input samples for times before n 0 assuming that time starts at 0 must be loaded into the FDM The number of samples needed to initialize the filter is the number of filter coefficients minus one To select Initialization mode clear the FCSR FPRC bit If FCSR FPRC is set initialization is disabled and the EFCOP assumes that the core wrote the initial input values to the FDM before the EFCOP was enabled Thus the first value written to FDIR is the first sample to be filtered If FCSR FPRC is clear initialization mode is enabled and the EFCOP initializes the FDM by receiving the number of coefficients minus one samples through the FDIR After samples are loaded the next value written to the FDIR is the first sample to be filtered 10 5 1 1 7 Decimation Decimation is another option that can be used with any four of the modes available with the FIR filter type Decimation cannot be used in conjunction with Adaptive and Multichannel modes Decimation decreases downsamples the sampling rate The decimation ratio defines the number of input samples per output sample The decimation ratio is one plus the number in the FDCH FDCM bits The decimation rati
41. The different stages of DMA input and interrupt output are as follows l Setup Set the filter count register FCNT to the length of the filter coefficients 1 i e N 1 Set the Data and Coefficient Base Address pointers FDBA FCBA Set the operation mode FCSR 5 4 FOM 00 Set Initialization mode FCSR 7 FPRC 0 Set Filter Data Output Interrupt Enable FSCR 11 FDOIE 1 Set DMA register with DMA input as per channel 0 in Section 10 7 1 1 2 Initialization Enable interrupts in the Interrupt Priority Register IPRP 10 11 EOL 11 Enable interrupts in the Status Register SR 8 9 00 Enable EFCOP FCSR 0 FEN 1 Enable the DMA input channel DCRO 23 DE 1 3 Processing Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA which loads the next input into the FDIR Compute F n the result is stored in FDOR The core is interrupted when FDOBF is set and stores the data in memory Example 10 3 Real FIR Filter DMA Input Interrupt Output INCLUDE ioequ asm pq OCIO Ck Kk hehe kk ko koe e ERK KE Ke Ree Ke OK KK Ke E EEK KK KK KC KC KRKAKEK ERK ERKK ek lee ede equates pp Ck kokcke hehe hok ko koe e EER kk Ke Ree e EK KERR EER eK e CR KK KEK ERK CK KK eek eee Ke dee Start equ 00100 main program starting address FCON equ 801 EFCOP FSCR register contents enable output interrupt enable the EFCOP FIR LEN equ 20 EFCO
42. can be selected The bit clock output is available at the transmit clock signal SCK and or the receive clock SCO signal of the DSP The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers Figure 7 3 shows the ESSI clock generator functional block diagram Feore is the DSP56311 core clock frequency the same frequency as the enabled CLKOUT signal Careful choice of the crystal oscillator frequency and the prescaler modulus can generate the industry standard CODEC master clock frequencies of 2 048 MHz 1 544 MHz and 1 536 MHz TX 1 or FlagO Out Flago In CRB TE1 CRB OFO SSISR IFO Sync Mode Sync Mode CRA WL2 0 Sync TX 1 or FlagO Async CRB SCDO RX clk TX Word Clock Sync TX RX clk TX Shift Register Ee CRB SCKD TACK Note 1 Foore is the DSP56300 core CRA PSR CRA PM7 0 internal clock frequency 2 ESSI internal clock range ie min Fogc 4096 1 0 max Fosc 4 FCORE Opposite 3 n in signal name is ESSI 0 or 1 from SSI Figure 7 3 ESSI Clock Generator Functional Block Diagram Motorola Enhanced Synchronous Serial Interface ESSI 7 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model CRB FSL1 CRB FSR RX Word CRA DC4 0 Internal Rx Frame Sync CRB SCD1 Receive Control Logic
43. m Chapter 3 Memory Configuration DSP56311 memory spaces RAM configuration memory configuration bit settings memory configurations and memory maps m Chapter 4 Core Configuration Registers for configuring the DSP56300 core when programming the DSP56311 in particular the interrupt vector locations and the operation of the interrupt priority registers operating modes and how they affect the processor s program and data memories m Chapter 5 Programming the Peripherals Guidelines on initializing the DSP56311 peripherals including mapping control registers specifying a method of transferring data and configuring for general purpose input output GPIO Motorola Overview 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Manual Conventions Chapter 6 Host Interface HIO8 Features signals architecture programming model reset interrupts external host programming model initialization and a quick reference to the HIO8 programming model Chapter 7 Enhanced Synchronous Serial Interface ESSI Enhancements data and control signals programming model operating modes initialization exceptions and GPIO Chapter 8 Serial Communication Interface SCI Signals programming model operating modes reset initialization and GPIO Chapter 9 Triple Timer Module Architecture programming model and operating modes of three identical timer devices avail
44. that is FEN 0 10 3 7 EFCOP Data Base Address FDBA The FDBA is a 16 bit read write counter register used as an address pointer to the EFCOP FDM bank FDBA points to the location to write the next data sample The FDBA points to a modulo delay buffer of size M defined by the filter length M FCNT 11 0 1 The address range of this modulo delay buffer is defined by lower and upper address boundaries The lower address boundary is the FDBA value with 0 in the k LSBs where 25 M 2 2 Fit therefore must be a multiple of 2 The upper boundary is equal to the lower boundary plus M 1 Since M x 2 once M has been chosen that is FCNT has been assigned a sequential series of data memory blocks each of length 2 will be created where multiple circular buffers for multichannel filtering can be located If M lt 24 Motorola DSP56311 User s Manual 10 12 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model there will be a space between sequential circular buffers of 2 M The address pointer is not required to start at the lower address boundary or to end on the upper address boundary It can point anywhere within the defined modulo address range If the data address pointer FDB A increments and reaches the upper boundary of the modulo buffer it will wrap around to the lower boundary 10 3 8 EFCOP Coefficient Base Address FCBA The FCBA
45. transmits Software can directly set the OF 1 0 values allowing the DSP56311 to control data transmission by indirectly controlling the value of the SC 1 0 flags Motorola Enhanced Synchronous Serial Interface ESSI 7 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 7 5 ESSI Programming Model The ESSI is composed of the following registers Two control registers CRA CRB page 7 14 and page 7 18 One status register SSISR page 7 29 One Receive Shift Register page 7 31 One Receive Data Register RX page 7 31 Three Transmit Shift Registers page 7 31 Three Transmit Data Registers TX0 TX1 TX2 page 7 31 One special purpose Time Slot Register TSR page 7 34 Two Transmit Slot Mask Registers TSMA TSMB page 7 34 B Two Receive Slot Mask Registers RSMA RSMB page 7 35 This section discusses the ESSI registers and describes their bits Section 7 6 GPIO Signals and Registers on page 7 36 covers ESSI GPIO 7 5 1 ESSI Control Register A CRA The ESSI Control Register A CRA is one of two 24 bit read write control registers that direct the operation of the ESSI CRA controls the ESSI clock generator bit and frame sync rates word length and number of words per frame for serial data 23 22 21 20 19 18 17 16 15 14 13 12 SSC1 WL2 WL1 WLO ALC DC4 DC3 DC2 DC1 DCO 11 10 9 8 7 6 5 4 3 2 1 0 PSR PM7 PM6 PM5 PM4 PM3 PM2 PM1 P
46. www freescale com Freescale Semiconductor Inc Data Transfer Methods 5 4 3 DMA The Direct Memory Access DMA controller permits data transfers between internal external memory and or internal external I O in any combination without the intervention of the DSP56311 core Dedicated DMA address and data buses and internal memory partitioning ensure that a high level of isolation is achieved so the DMA operation does not interfere with the core operation or slow it down The DMA moves data to from the peripheral transmit receive registers The programmer may use the DMA control registers to configure sources and destinations of data transfers Depending on the peripheral you will find one to four peripheral request sources available This is the most efficient method of data transfer available Core intervention is not required after the DMA channel is initialized Table 5 1 DMA Accessible Registers DMA Block Register Read Write ESSI TXO No Yes TX1 No Yes TX2 No Yes RX Yes No SCI SRX Yes No STX No Yes EFCOP FDIR No Yes FDOR Yes No HIO8 HTX No Yes HRX Yes No Timer Example 5 3 shows a DMA configuration for transferring data to the Host Transmit register of the HIOS Example 5 3 DMA Transfers bclr SM D1LO0O x M IPRC disable DMA1 interrupts belie M_D1L1 x M_IPRC movep TBUFF_START x M_DSR1 movep 4M HTX x M DDR1 movep TBUFF_SIZE 1 x M_DCO1 movep 4 INIT DCR1
47. www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes 10 7 3 1 Implementation Using Polling Figure 10 12 shows a flowchart for an adaptive FIR filter that uses polling to transfer data Set FCNT N 1 Calculate Ke Set FDBA FCBA Enable EFCOP ADP Real FIR Mode Write Ke to FKIR Write next x n Set FUPD 1 opt Automatically Done in ADP Mode Ae Output Buffer Full Read y n Block No Done Yes End Figure 10 12 Adaptive FIR Filter Using Polling Motorola Enhanced Filter Coprocessor EFCOP 10 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes 10 7 3 2 Implementation Using DMA Input and Interrupt Output Figure 10 13 shows a flowchart for an adaptive FIR filter that uses DMA and an interrupt to transfer data t Buffer ull Interrupt Outpu F Set DMA Int for input on FDIBE Set FCONT L 1 Set FDBA FCBA Enable EFCOP ADP Real FIR Mode Calculate Ke Write Ke to FKIR Set FUPD 1 opt Automatically Done in ADP Mode Figure 10 13 Adaptive FIR Filter Using DMA Input and Interrupt Output 10 7 3 3 Updating an FIR Filter The following example shows an FIR adaptive filter that is updated using the LMS algorithm Example 10 4 FIR Adaptive Filter Update Using the LMS Algorithm TITLE ADAPTIVE INCLUDE ioequ asm
48. 1 stop Reserved 8 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model 8 6 2 SCI Status Register SSR The SSR is a 24 bit read only register that indicates the status of the SCI 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 R8 FE PE OR IDLE RDRF TDRE TRNE Figure 8 4 SCI Status Register Table 8 3 SCI Status Register SSR Bit Definitions Bit Number Bit Name Reset Value Description 23 8 Reserved Set to 0 for future compatibility R8 Received Bit 8 In 11 bit Asynchronous Multidrop mode the R8 bit indicates whether the received byte is an address or data R8 is set for addresses and is cleared for data R8 is not affected by reads of the SRX or SCI status register A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears R8 FE Framing Error Flag In Asynchronous mode FE is set when no stop bit is detected in the data string received FE and RDRE are set simultaneously when the received word is transferred to the SRX However the FE flag inhibits further transfer of data into the SRX until it is cleared FE is cleared when the SCI status register is read followed by a read of the SRX A
49. 10 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model 10 2 3 Filter Multiplier and Accumulator FMAC The FMAC machine can perform a 24 bit x 24 bit multiplication with accumulation in a 56 bit accumulator The FMAC operates a pipeline the multiplication is performed in one clock cycle and the accumulation occurs in the following clock cycle Throughput is one MAC result per clock cycle The two MAC operands are read from the FDM and from the FCM The full 56 bit width of the accumulator is used for intermediate results during the filter calculations For operations in which saturation mode is disabled the final result is rounded according to the selected rounding mode and limited to the most positive number 7FFFFF if overflow occurred or most negative number 800000 if underflow occurred after processing of all filter taps is completed In saturation mode the result is limited to the most positive number 7FFFFF if overflow occurred or the most negative number 800000 if underflow occurred after each MAC operation The 24 bit result from the FMAC is stored in the EFCOP output buffer FDOR Operating in sixteen bit arithmetic mode the FMAC performs a 16 bit x 16 bit multiplication with accumulation into a 40 bit accumulator As with 24 bit operations if saturation mode is disabled the result is rounded according to the selected rounding mode and limited
50. 20 16 0 31 BA3W 15 13 0 7 Bus Lock Hold Bit 22 0 BL pin is asserted only for attempted read write modify external access BATW 9 5 0 31 1 BL pin is always asserted BA2W 12 10 0 7 BAOW 4 0 0 31 Bus Request Hold Bit 23 0 BR pin is asserted only for attempted or pending access 1 BR pin is always asserted as i Bus Control Register BCR Reset 1FFFFF Figure B 4 Bus Control Register BCR Motorola Programming Reference B 15 For More Information On This Product Go to www freescale com Programming Sh Central Processor DMA Request Freescale Semiconductor Inc eets Source Bits 15 11 Three Dimensional Mode Bit 10 0 Three Dimensional mode disabled 1 Three Dimensional mode enabled DRS 4 0 Requesting Device 00000 External IRQA Pin 00001 External IRQB pin 00010 00011 External IRQC pin External IRQD pin 00100 Transfer done from channel 0 DMA Address Mode Bits 9 4 Non Three Dimensional Addressing Modes D3D 0 DAM 2 0 source DAM 5 3 Destination 00101 Transfer done from channel 1 00110 Transfer done from channel 2 DAMI5 3 DAM 2 0 Addressing Mode Mode Counter Offset Register Selection 00111 Transfer done from channel 3 000 2D B DORO 01000 Transfer done from channel 4 001 2D
51. 24 bit operand The LSP is either truncated or rounded into the MSP Rounding is performed if specified 1 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56300 Core Functional Blocks 1 5 2 Address Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into halves each with its own identical address ALU Each address ALU has four sets of register triplets and each register triplet includes an address register offset register and modifier register Each contains a 24 bit full adder called an offset adder A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder work in parallel and share common inputs The only difference between them is that the carry propagates in opposite directions Test logic determines which of the three summed results of the full adders is output Each addres
52. 4 0 in the DMA control status registers encode the source of DMA requests that trigger DMA transfers The DMA request sources may be internal peripherals or external devices requesting service through the IRQA IRQB IRQC or IRQD signals Table 4 5 shows the values of the DRS bits Table 4 5 DMA Request Sources DMA Request Source Bits Requesting Device DRS4 DRSO 00000 External IRQA signal 00001 External IRQB signal 00010 External IRQC signal 00011 External IRQD signal 00100 Transfer done from DMA channel 0 00101 Transfer done from DMA channel 1 00110 Transfer done from DMA channel 2 00111 Transfer done from DMA channel 3 01000 Transfer done from DMA channel 4 01001 Transfer done from DMA channel 5 01010 ESSIO receive data RDFO 1 01011 ESSIO transmit data TDEO 1 01100 ESSI receive data RDF1 1 01101 ESSI1 transmit data TDE1 1 01110 SCI receive data RDRF 1 01111 SCI transmit data TDRE 1 10000 TimerO TCFO 1 10001 Timer1 TCF1 1 10010 Timer2 TCF2 1 10011 Host receive data full HRDF 1 10100 Host transmit data empty HTDE 1 10101 EFCOP input buffer empty FDIBE 1 10110 EFCOP output buffer full FDOBF 1 10111 11111 Reserved Note The lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller 4 10 DSP56311 User
53. 4 8 shows the JTAG ID register configuration Version information corresponds to the revision number 0 for revision 0 1 for revision A etc 31 28 27 22 21 12 11 1 0 Version Information Design Center Sequence Manufacturer 1 Number Number Identity 0000 000110 0000001011 00000001110 1 Figure 4 8 JTAG Identification Register Configuration Revision 0 4 10 JTAG Boundary Scan Register BSR The BSR in the DSP56311 JTAG implementation contains bits for all device signals clock pins and their associated control signals All DSP56311 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR For details on the BSR consult the DSP56300 Family Manual Motorola Core Configuration 4 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG Boundary Scan Register BSR 4 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 5 Programming the Peripherals When peripherals are programmed in a given application a number of possible modes and options are available for use Chapters 6 through 10 describe in detail the possible modes and configurations for peripheral registers and ports This chapter presents general guidelines for initializing the peripherals These guidelines include a descrip
54. 48 bit accumulator or the 32 bit accumulator in Arithmetic Sixteen bit mode 0 C 0 Carry Set if a carry is generated by the MSB resulting from an addition operation This bit is also set if a borrow is generated in a subtraction operation otherwise this bit is cleared The carry or borrow is generated from Bit 55 of the result The C bit is also affected by bit manipulation rotate and shift instructions 4 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PLL Control Register PCTL 4 6 PLL Control Register PCTL The PCTL is an X I O mapped read write register that directs the operation of the on chip PLL See Figure 4 5 23 22 21 20 19 18 17 16 15 14 13 12 PD3 PD2 PD1 PDO COD PEN PSTP XTLD XTLR DF2 DF1 DFO 11 10 9 8 7 6 5 4 3 2 1 0 MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MFO Figure 4 5 PLL Control Register PCTL Table 4 8 defines the DSP56311 PCTL bits Table 4 8 PLL Control Register PCTL Bit Definitions Bit Number Bit Name Reset Value Description 23 20 PD 3 0 0 Predivider Factor Bits hardware reset which corresponds to a PDF of one Define the predivision factor PDF to be applied to the PLL input frequency The PD 3 0 bits are cleared during DSP5631 1 19 COD Clock Output Disable Controls the output buffer of th
55. 6 19 Host Request Enable 6 20 Host Request Open Drain 6 19 Host Request Polarity 6 18 HREQ pin when a single request line is used 6 10 HREQ HTRQ handshake flags 6 23 HSR General purpose flags for host to DSP communication 6 15 Host Command Pending 6 15 Host Flags 0 1 6 15 Host Receive Data Full 6 16 Host Transmit Data Empty 6 15 indicate that host transmit data register HTX is empty and can be written by DSP core 6 15 indicates that host receive data register HR X contains data from host processor 6 16 HTX register 6 30 ICR Double Host Request 6 25 Host Flag 0 6 25 Host Flag 1 6 25 Host Little Endian 6 25 Initialize 6 25 Receive Request Enable 6 26 Transmit Request Enable 6 26 ICR Double Host Request bit 6 9 indicate state of HF2 in the HCR on DSP side 6 28 indicate that TXH TXM TXL and HRX registers are empty 6 29 instructions and addressing modes 6 4 Interface Control Register ICR 6 24 Interface Status Registe ISR 6 28 interrupt routines 6 8 interrupt vector number used with MC68000 family processor vectored interrupts 6 30 Interrupt Vector Register IVR 6 30 interrupt based techniques 6 23 ISR Host Flag 2 6 28 Host Flag 3 6 28 Host Request 6 28 Receive Data Register Full 6 29 Transmit Data Register Empty 6 29 Transmitter Ready 6 29 masking interrupts 6 8 MOVEP instruction 6 13 multiplexed bus mode 6 20 multiplexed bus modes 6 17 multiplexed mode 6 4 non multiplexed bus mode 6 20 non multiplexed mode 6 4 p
56. DO loops m Fastauto return interrupts m Hardware system stack The PCU uses the following registers Program counter register Status register Loop address register Loop counter register Vector base address register Size register Stack pointer Operating mode register Stack counter register 1 5 4 PLL and Clock Oscillator The clock generator in the DSP56300 core comprises two main blocks the PLL which performs clock input division frequency multiplication and skew elimination and the clock generator which performs low power division and clock pulse generation These features allow you to m Change the low power divide factor without losing the lock Output a clock with skew elimination The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input a feature that offers two immediate benefits m A lower frequency clock input reduces the overall electromagnetic interference generated by a system m The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system 1 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56300 Core Functional Blocks 1 5 5 JTAG TAP and OnCE Module In the DSP56300 core is a dedicated user accessible TAP that is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan A
57. DOR1 01001 Transfer done from channel 5 010 2D DOR2 01010 ESSI 0 Receive Data 011 2D DORS 100 No update None TOTT 11111 Reserved 101 Postincrement by 1 None DMA Continuous Mode Enable Bit 16 0 Disables continuous mode 110 reserved 111 reserved 1 Enables continuous mode DMA Channel Priority Bits 18 17 DPR 1 0 Channel Priority 00 Priority level O lowest 01 Priority level 1 10 Priority level 2 11 Priority level 3 highest DMA Transfer Mode Bits 21 19 Three Dimensional Addressing Modes D3D 1 DAM 5 3 Addressing Mode Offset Selection 000 2D DORO 001 2D DOR1 010 2D DOR2 011 2D DORS 100 No update None 101 Postincrement by 1 None 110 3D DORO DOR1 DTM 2 0 Triggered By DE Cleared Transfer Mode 000 request yes block transfer 111 3D DOR2 DOR3 001 request yes word transfer 010 request yes line transfer 011 DE yes block transfer 100 request no block transfer 101 request no word transfer 110 reserved 111 reserved DMA Interrupt E 0 Disables DMA Interrupt 1 Enables DM nable Bit 22 A i
58. DSP56311 192 word Boot ROM This program can load any program RAM segment from an external EPROM from the Host Interface or from the SCI serial interface 225252322523222222222222222222222522222522225222222222222222252522522522522222255 If MD MC MB MA x000 then the Boot ROM is bypassed and the DSP56311 starts fetching instructions beginning with address C00000 MD 0 or 008000 MD 1 assuming that an external memory of SRAM type is used The accesses are performed using 31 wait states with no address attributes selected default area 2252523222322222222222222222222252222252222222222222222222232522522522522222255 Operation modes MD MC MB MA 0001 0111 are reserved 225252322522222222222222222222225222225222252222222222222222522522522522222255 If MD MC MB MA 1001 then it loads a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0 The memory is selected by the Address Attribute AAT and is accessed with 31 wait states The EPROM bootstrap code expects to read 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words are condensed into 24 bit words and stored in
59. Data Bus Bus Control HIO8 ESSI SCI Timer Grounds PLL PLL Internal Logic Address Bus Data Bus Bus Control HIO8 ESSI SCI Timer Port A External Address Bus External Data Bus External Bus Control Interrupt Mode Control Host Interface HIO8 Porti Enhanced Synchronous Serial Interface Port 0 ESSI0 Enhanced Synchronous Serial Interface Port 1 ESSI1 Serial Communications Interface SCI Port Timers OnCE JTAG Port 8 During Reset MODA MODB MODC MODD RESET Non Multiplexed Bus Ho H7 HAO HA1 HA2 HCS HCS Single DS HRW HDS HDS Single HR HREQ HREQ HACK HACK SC00 SC02 SCKO SRDO STDO SC10 SC12 SCK1 SRD1 STD1 Multiplexed Port B Bus GPIO HAD0O HAD7 PERI PB8 HAS HAS PB9 PB10 PB13 Double DS HRD HRD HWR HWR zDouble HR HTRQ HTRQ HRRQ HRRQ PBT PB12 PB14 PB15 Port C GPIO PCO PC2 PCS PC4 PC5 Port D GPIO PDO PD2 PD3 PD4 PD5 Port E GPIO PEO PE1 PE2 Timer GPIO TIOO TIO1 TIO2 The HI08 port supports a non multiplexed or a multiplexed bus single or double Data Strobe DS and single or double Host Request HR configurations Since each of these modes is configured independently any combination of these modes is possible These HI08 signals can also be configured alternately as GPIO signals PBO PB15 Signals with dual designations e g HAS HAS have configurable polarity 2 The ESSIO ESSI1 and S
60. During Signal Name Type Reset Signal Description HREQ HREQ Output Input Host Request When HI08 is programmed to interface a single host request host bus and the HI function is selected this signal is the host request HREQ output The polarity of the host request is programmable but is configured as active low HREQ following reset The host request may be programmed as a driven or open drain output Transmit Host Request When HIO8 is programmed to HTRQ HTRQ Output interface a double host request host bus and the HI function is selected this signal is the transmit host request HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request may be programmed as a driven or open drain output Port B 14 When the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR this signal is individually programmed as an PB14 Input or input or output through the HDDR Output NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated HACK Input Input Host Acknowledge When HIO8 is programmed to interface a HACK single host request host bus and the HI function is selected this signal is the host acknowledge HACK Schmitt trigger input The polarity of the host acknowledge is programmable but is configured as active low HACK after reset Receive Hos
61. FFB9 FFFFB9 ESSI 0 Time Slot Register TSRO FFB8 FFFFB8 ESSI 0 Receive Data Register RXO FFB7 FFFFB7 ESSI 0 Status Register SSISRO FFB6 FFFFB6 ESSI 0 Control Register B CRBO FFB5 FFFFB5 ESSI 0 Control Register A CRAO FFB4 FFFFB4 ESSI 0 Transmit Slot Mask Register A TSMAO FFB3 FFFFB3 ESSI 0 Transmit Slot Mask Register B TSMBO FFB2 FFFFB2 ESSI 0 Receive Slot Mask Register A RSMAO FFB1 FFFFB1 ESSI 0 Receive Slot Mask Register B RSMBO FFBO FFFFBO Reserved Port D FFAF FFFFAF Port D Control Register PCRD FFAE FFFFAE Port D Direction Register PRRD FFAD FFFFAD Port D GPIO Data Register PDRD Motorola Programming Reference B 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Memory Map Table B 2 Internal X I O Memory Map Continued Peripheral 16 Bit Address 24 Bit Address Register Name ESSI 1 FFAC FFFFAC ESSI 1 Transmit Data Register 0 TX10 FFAB FFFFAB ESSI 1 Transmit Data Register 1 TX11 FFAA FFFFAA ESSI 1 Transmit Data Register 2 TX12 FFA9 FFFFA9 ESSI 1 Time Slot Register TSR1 FFA8 FFFFA8 ESSI 1 Receive Data Register RX1 FFA7 FFFFA7 ESSI 1 Status Register SSISR1 FFA6 FFFFA6 ESSI 1 Control Register B CRB1 FFA5 FFFFA5 ESSI 1 Control Register A CRA1 FFA4 FFFFA4 ESSI 1 Transmit Slot Mask Regi
62. Figure 7 17 ESSI Receive Slot Mask Register B RSMB RSMA and RSMB as in Figure 7 12 and Figure 7 13 can be seen as one 32 bit register RSM Bit nin RSM RSn is an enable disable control bit for time slot number N When RSn is cleared all the data signals of the enabled receivers are tri stated during time slot number N Data transfers from the receive data register s to the receive shift register s but the RDF and ROE flags are not set Consequently during a disabled slot no receiver full interrupt is generated The DSP is interrupted only for enabled slots When RSn is set the receive sequence proceeds normally Data is received during slot number N and the RDF flag is set When the bits in the RSM are set their setting affects the next frame transmission The frame being transmitted is not affected by the new RSM setting If the RSM is read it shows the current setting When RSMA or RSMB is read by the internal data bus the register contents occupy the two low order bytes of the data bus and the high order byte is filled by 0 After a hardware RESET signal or a software RESET instruction the RSM register is reset to FFFFFFFF enabling all 32 time slots for data transmission 7 6 GPIO Signals and Registers The GPIO functionality of an ESSI port whether C or D is controlled by three registers port control register PCRC PCRD port direction register PRRC PRRD and port data register PDRC PDRD 7 6 1 Port Contro
63. Freescale Semiconductor Inc Interrupt Sources and Priorities Table 4 3 Interrupt Priority Level Bits IPL bits Interrupts Enabled Interrupts Masked Interrupt Priority Level xxL1 xxLO 0 0 No 0 0 1 Yes 0 1 1 0 Yes 0 1 2 1 1 Yes 0 1 2 3 4 3 3 Interrupt Source Priorities Within an IPL If more than one interrupt request is pending when an instruction executes the interrupt source with the highest IPL is serviced first When several interrupt requests with the same IPL are pending another fixed priority structure within that IPL determines which interrupt source is serviced first Table 4 4 shows this fixed priority list of interrupt sources within an IPL from highest to lowest at each level The interrupt mask bits in the Status Register I 1 0 can be programmed to ignore low priority level interrupt requests Table 4 4 Interrupt Source Priorities Within an IPL Priority Interrupt Source Level 3 nonmaskable Highest Hardware RESET Stack error Illegal instruction Debug request interrupt Trap Lowest Nonmaskable interrupt Levels 0 1 2 maskable Highest IRQA external interrupt IRQB external interrupt external interrupt IRQC IRQD external interrupt DMA channel 0 interrupt DMA channel 1 interrupt DMA channel 2 interrupt DMA channel 3 interrupt DMA channel 4 interrupt DSP563
64. HI08 is a byte wide full duplex double buffered parallel port that can connect directly to the data bus of a host processor The HIO8 supports a variety of buses and provides glueless connection with a number of industry standard microcomputers microprocessors and DSPs The HI08 signals not used to interface to the host can be configured as GPIO signals up to a total of 16 6 1 Features The HI08 host is a slave device that operates asynchronously to the DSP core and host clocks Thus the HI08 peripheral has a host processor interface and a DSP core interface This section lists the features of the host processor and DSP core interfaces 6 1 1 DSP Core Interface m Mapping Registers are directly mapped into eight internal X data memory locations m Data word DSP56311 24 bit native data words are supported as are 8 bit and 16 bit words m Handshaking protocols Software polled Interrupt driven Core DMA accesses m Instructions Memory mapped registers allow the standard MOVE instruction to transfer data between the DSP56311 and external hosts A special MOVEP instruction for I O service capability using fast interrupts Bit addressing instructions for example BCHG BCLR BSET BTST JCLR JSCLR JSET JSSET simplify I O service routines Motorola Host Interface H108 6 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Features 6 1
65. Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Synchronous Serial Interface 1 2 9 Enhanced Synchronous Serial Interface 1 Table 2 12 Enhanced Serial Synchronous Interface 1 Signal Name Type State During Reset Signal Description SC10 PDO Input or Output Input or Output Input Serial Control 0 The function of SC10 is determined by the selection of either synchronous or asynchronous mode For asynchronous mode this signal will be used for the receive clock I O Schmitt trigger input For synchronous mode this signal is used either for transmitter 1 output or for serial I O flag 0 Port D 0 The default configuration following reset is GPIO input PDO When configured as PDO signal direction is controlled through the port directions register PRR1 The signal can be configured as an ESSI signal SC10 through the port control register PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SC11 PD1 Input Output Input or Output Input Serial Control 1 The function of this signal is determined by the selection of either synchronous or asynchronous mode For asynchronous mode this signal is the receiver frame sync I O For synchronous mode this signal is used either for Transmitter 2 output or for Serial I O Flag 1 Port D 1 The default configuration following reset is GPIO inpu
66. Interface H108 6 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Model Quick Reference Table 6 18 HI08 Programming Model DSP Side Continued Bit Reset Type Reg Name Value Function HW IR ST SW HSR 0 HRDF Host Receive 0 no receive data to be read 0 0 0 Data Full 1 Receive Data Register is full 1 HTDE Host Transmit 1 The Transmit Data Register is 1 1 1 Data Empty 0 empty The Transmit Data Register is not empty 2 HCP Host Command 0 no host command pending 0 0 0 Pending 1 host command pending 3 HFO Host Flag 0 0 4 HF1 Host Flag 1 0 i HBAR 7 0 BA10 B Host Base 80 A3 Address Register HRX 23 0 DSP Receive empty Data Register HTX 23 0 DSP Transmit empty Data Register HDR 16 0 D16 GPIO signal 0000 DO Data HDRR 16 0 DR16 D GPIO signal 0 Input 0000 RO Direction 1 Output 6 34 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Model Quick Reference Table 6 19 HI08 Programming Model Host Side Bit Reset Type Reg HW Name Value Function sw IR ICR 0 RREQ Receive Request Enable 0 HRRQ interrupt disabled 0 1 HRRQ interrupt enabled 1 TREQ Transmit Request Enable 0 HTRQ interrupt disa
67. Interface HI08 6 32 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Model Quick Reference Table 6 18 HI08 Programming Model DSP Side Continued Bit Reset Type Reg Name Value Function HW IR ST SW HPCR 4 HREN Host Request HDRQ 0 0 i Enable HDRQ 1 0 HREQ HTRQ GPIO HREQ HTRQ 1 HACK HRRQ GPIO HREQ HTRQ HREQ HREQ HTRQ HACK HRRQ HTRQ HRRQ 5 HAEN Host HDRQ 0 0 Acknowledge HDRQ 1 Enable 0 HACK HRRQ GPIO HREQ HTRQ 1 HACK HRRQ GPIO HACK HRRQ HACK HREQ HTRQ HACK HRRQ HTRQ HRRQ 6 HEN Host Enable 0 Host Port GPIO 0 1 Host Port Active 8 HROD Host Request 0 HREQ HTRQ HRRQ driven 0 Open Drain 1 HREQ HTRQ HRRQ open drain 9 HDSP Host Data 0 HDS HRD HWR active low 0 Strobe Polarity 1 HDS HRD HWR active high 10 HASP Host Address 0 HAS active low 0 Strobe Polarity 1 HAS active high 11 HMUX Host 0 Separate address and data 0 Ea Multiplexed Bus 1 lines Multiplexed address data 12 HDDS Host Dual Data 0 Single Data Strobe HDS 0 Strobe 1 Double Data Strobe HWR HRD HPCR 13 HCSP Host Chip 0 HCS active low 0 Select Polarity 1 HCS active high 14 HRP Host Request 0 HREQ HTRQ HRRQ active low 0 Polarity 1 HREQ HTRQ HRRQ active high 15 HAP Host 0 HACK active low 0 Acknowledge 1 HACK active high Polarity Motorola Host
68. Level low DMAS Interrupt Priority Level high Interrupt Priority Register Peripheral IPRP M HPL EQU M HPLO EQU M HPLI EQU M SOL EQU M SOLO EQU M SOL EQU M SIL EQU M SILO EQU M SIL1 EQU M SCL EQU M SCLO EQU M_SCL1 EQU M TOL EQU M TOLO EQU M TOLI EQU M EPL EQU M EPLO EQU M EPLI EQU 3 0 1 C 2 3 30 4 5 CO 6 7 300 8 9 COO 10 1l Host Interrupt Priority Level Mask Host Interrupt Priority Level low Host Interrupt Priority Level high SSIO Interrupt Priority Level Mask SSIO Interrupt Priority Level low SSIO Interrupt Priority Level high SSI1 Interrupt Priority Level Mask SSI1 Interrupt Priority Level low SSI1 Interrupt Priority Level high SCI Interrupt Priority Level Mask SCI Interrupt Priority Level low SCI Interrupt Priority Level high TIMER Interrupt Priority Level Mask TIMER Interrupt Priority Level low TIMER Interrupt Priority Level high EFCOP Interrupt Priority Level Mask EFCOP Interrupt Priority Level low EFCOP Interrupt Priority Level high Register Addresses Of TIMERO A 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com M TCSRO EQU SFFFF8F M TLRO EQU FFFFSE M TCPRO EQU S SFFFF8D M TCRO EQU S FFFF8C Freescale Semiconductor Inc TIMERO Control Status Register TIMERO Load Reg TIMERO Compare Register IIMERO Count Register Register A
69. MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request B After reset this input becomes a IROB Input level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If IRQB is asserted synchronous to the internal clock multiple processors can be resynchronized using the WAIT instruction and asserting IRQB to exit the wait state If the processor is in the stop standby state and IRQB is asserted the processor will exit the stop state MODC Input Input Mode Select C An active low Schmitt trigger input internally synchronized to the internal clock MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request C After reset this input becomes a IROG Input level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If IRQC is asserted synchronous to the internal clock multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state If the processor is in the stop standby state and IRQC is asserted the processor will exit the stop state 2 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Table 2 9 Fre
70. Operating Modes Normal Network and On Demand 7 4 2 Synchronous Asynchronous Operating Modes The transmit and receive sections of the ESSI interface are synchronous or asynchronous The transmitter and receiver use common clock and synchronization signals in Synchronous mode they use separate clock and sync signals in Asynchronous mode The SYN bit in CRB selects synchronous or asynchronous operation When the SYN bit is cleared the ESSI TX and RX clocks and frame sync sources are independent If the SYN bit is set the ESSI TX and RX clocks and frame sync are driven by the same source either external or internal Since the ESSI operates either synchronously or asynchronously separate receive and transmit interrupts are provided Transmitter 1 and transmitter 2 operate only in Synchronous mode Data clock and frame sync signals are generated internally by the DSP or obtained from external sources If clocks are internally generated the ESSI clock generator derives bit clock and frame sync signals from the DSP internal system clock The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame rate divider with a word length divider for frame rate sync signal generation 7 4 3 Frame Sync Selection The transmitter and receiver can operate independently The transmitter can have either a bit long or word long frame sync signal format and the receiver ca
71. PC 2 0 bits controls the functionality of the corresponding port signal When a PC i bit is set the corresponding port signal is configured as an SCI signal When a PC i bit is cleared the corresponding port signal is configured as a GPIO signal A hardware RESET signal or a software RESET instruction clears all PCR bits P Pct Po LJ 4 3 Port Control Bits 1 SCI 0 GPIO Reserved Read as 0 Write with 0 for future compatibility Figure 8 9 Port E Control Register PCRE Motorola Serial Communication Interface SCI 8 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 8 7 2 Port E Direction Register PRRE The read write PRRE controls the direction of SCI GPIO signals When port signal i is configured as GPIO PDC i controls the port signal direction When PDCTi is set the GPIO port signal i is configured as output When PDC i is cleared the GPIO port signal 1 is configured as input A hardware RESET signal or a software RESET instruction clears all PRR bits 7 6 5 4 3 2 1 0 L Lp epce pc Ppco Direction Control Bits 1 Output 0 Input C Reserved Read as 0 Write with O for future compatibility Figure 8 10 Port E Direction Register PRRE Table 8 5 shows the port signal configurations Table 8 5 Port Control Register and Port Direction Register Bits PC i PDC i Port Signal i
72. Port E Direction Register PRRE i2ecekereceu eer RPIe er ck3u a Reed er 8 26 8 7 3 Port E Data Register PDRE sudes xar eR ERE EE X ERES Rb E xe 8 26 Chapter 9 Triple Timer Module 9 1 OVErVIEW MMC 9 1 9 2 Operan MM PF ak a a AE a EE E EERE E E R 9 2 9 2 1 Timer After i MP pers aay Eea R Sake aE GS e 9 2 9 2 2 Timer Initialization kee a ba eae ee hee RE RE eGo aad alee 9 3 9 2 3 Timer BXGeptHOllSe 296r nO EP AR EETORPRCSEEQRAD GA ACRRPquR ES I E dU AS 9 3 93 Operating Modes csset oy ek en REX RR eR EN EIN EE RES ce alek pad oe eee 2 9 4 9 3 1 Triple Timer Mode eed x I ERR sree gate ease enSee whee stees Verse 9 5 9 3 1 1 Timer GPICEOMOOS D Lau iode mr RACER HERR RECTO a desea DE RR D 9 5 9 3 1 2 Timer Pulse Mode 1 3 03 6 0 dob eh cache at dates RUPEE RE UE a RR 9 7 9 3 1 3 Timet Toggle Mod 2 Los a scd eee RE ab ALES RS a TR a qud aede eee 9 8 9 3 1 4 Timer Event Counter Mode 3 00 cece cece een eee e eee nnenas 9 10 Motorola Contents vii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 9 3 2 Signal Measurement Modes llle 9 11 9 3 2 1 Measurement Input Width Mode 4 0 cece eee eee 9 12 9 3 2 2 Measurement Input Period Mode 5 0 2 20 eee ee eee 9 13 9 3 2 3 Measurement Capture Mode 0 aru EEREPAG PIX RETE eS See aee xS 9 15 9 3 3 Pulse Width Modulation PWM Mode 7 0 0 0 cee eee eens 9 16 9 34 Watchdog Mo
73. Port E Direction Register H X X xX x Pb c2 Ppct Ppco HHHH iiia X FFFF9E PDCn 1 gt Port Pin is Output PDCn 0 5 Port Pin is Input HeadWre Reset 5 5 o4 5 2 i 0 emen STIS ST T T PDRE X FFFF9D 01010 If port pin n is GPIO input then PDn reflects the value on port pin n If port pin n is GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure B 28 Port E Registers PCRE PRRE PDRE Motorola Programming Reference B 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets B 40 EFCOP 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 2 7 o B 0 0 0 0 0 0 0 Filter Count Value Filter Count Register FCNT x Reserved Program as 0 Y FFFFB3 Read Write Reset 000000 Filter Enable Bit 0 0 EFCOP Disabled FilterData Input Interrupt Enable Bit 10 1 EFCOP Enabled Read write control bit 0 Interrupt disabled Filter Type Bit 1 1 Interrupt enabled 0 FIR 1 IIR FilterData Output Interrupt Enable Bit 11 Read write control bit n Adaptive Mode Enable Bit 2 0 Adaptive Mode Disabled 0 Interrupt disabled 1 Adaptive Mode Enabled 1 Interrupt enabled Update Mode Enable Bit 3 Read only status bit 0 Update Mode Disabled 0 No FMAC underflow overflow 1 Upeate Mode Enabled 1 FMAC underflow overflow occurred Filter Operating ModeBits 5 4 00
74. Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes 10 7 1 1 DMA Input DMA Output A 20 tap FIR filter using a 28 input sample signal is implemented in the following stages 1 Set the filter count register FCNT to the length of the filter coefficients 1 i e Set the Data and Coefficient Base Address pointers FDBA FCBA Setup N 1 2 3 Set the operation mode FCSR 5 4 FOM 00 4 Set Initialization mode FCSR 7 FPRC 0 5 Set DMA registers DMA input A two dimensional 2D DMA transfer fills up the FDM bank via channel 0 The DMA input control registers are initialized as shown in Table 10 10 Table 10 10 DMA Channel 0 Regisister Initialization Register Setting Description DCRO bit values are as follows DMA Control Register 0 DIE 0 Disables end of transfer interrupt DTM 2 Chooses line transfer triggered by request DE auto clear on end of transfer DPR 2 Priority 2 DCON 0 Disables continuous mode DRS 15 Chooses DMA to trigger on EFCOP input buffer empty D3D 0 Chooses non 3D mode DAM 20 Sets the following DMA Address Mode E source address 2D E counter mode B E offset DORO E destination address no update no offset DDS 1 Destination in Y memory space because the EFCOP is in Y memory DSS 0 Source in X memory space DORO 1 DMA Offset Register 0 DCOO 006003 DMA Counter Register 0 Gives
75. Program data placed in the Program RAM Instruction Cache area changes its placement after the MS bit is set i e the Instruction Cache always uses the lowest internal Program RAM addresses 2 To ensure proper operation place six NOP instructions after the instruction that changes the MS bit 3 To ensure proper operation do not set the MS bit while the Instruction Cache is enabled CE bit is set in SR SD Stop Delay Mode Determines the length of the delay invoked when the core exits the Stop state The STOP instruction suspends core processing indefinitely until a defined event occurs to restart it If SD is cleared a 128K clock cycle delay is invoked before a STOP instruction cycle continues However if SD is set the delay before the instruction cycle continues is 16 clock cycles The long delay allows a clock stabilization period for the internal clock to begin oscillating and to stabilize When a stable external clock is used the shorter delay allows faster start up of the DSP56300 core Reserved Write to zero for future compatibility EBD External Bus Disable Disables the external bus controller to reduce power consumption when external memories are not used When EBD is set the external bus controller is disabled and external memory cannot be accessed When EBD is cleared the external bus controller is enabled and external access can be performed Hardware reset clears the EBD bit MD MA C
76. Programming Model The SCR WDSO WDS1 and WDS2 control bits define the length and format of the serial word The SCR receive clock mode RCM defines the clock source In Synchronous mode the start bit the eight data bits the address data indicator bit or the parity bit and the stop bit are received respectively Data bits are sent LSB first if SSFTD is cleared and MSB first if SSFTD is set In Synchronous mode a gated clock provides synchronization In either synchronous or Asynchronous mode when a complete word is clocked in the contents of the shift register can be transferred to the SRX and the flags RDRF FE PE and OR are changed appropriately Because the operation of the receive shift register is transparent to the DSP the contents of this register are not directly accessible to the programmer 8 6 4 2 SCI Transmit Register STX The transmit data register is a one byte wide register mapped into four addresses as STXL STXM STXH and STXA In Asynchronous mode when data is to be transmitted STXL STXM and STXH are used When STXL is written the low byte on the data bus is transferred to the STX When STXM is written the middle byte is transferred to the STX When STXH is written the high byte is transferred to the STX This structure makes it easy for the programmer to unpack the bytes in a 24 bit word for transmission TDXA should be written in 11 bit asynchronous multidrop mode when the data is an address and the progra
77. RX and TX have different frame sync lengths CRB FSLO is ignored when CRB SYN is set 7 4 6 Word Length Frame Sync and Data Word Timing The CRB FSR bit controls the relative timing of the word length frame sync relative to the data word timing m When CRB FSR is cleared the word length frame sync is generated or expected with the first bit of the data word m When CRB FSR is set the word length frame sync is generated or expected with the last bit of the previous word CRB FSR is ignored when a bit length frame sync is selected 7 4 7 Frame Sync Polarity The CRB FSP bit controls the polarity of the frame sync m When CRB FSP is cleared the polarity of the frame sync is positive that is the frame sync signal is asserted high The ESSI synchronizes on the leading edge of the frame sync signal m When CRB FSP is set the polarity of the frame sync is negative that is the frame sync is asserted low The ESSI synchronizes on the trailing edge of the frame sync signal The ESSI receiver looks for a receive frame sync edge leading edge if CRB FSP is cleared trailing edge if FSP is set only when the previous frame is completed If the frame sync is asserted before the frame is completed or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with CRB FSR set the current frame sync is not recognized and the receiver is internally disabled until the next frame sy
78. Real 10 Alt Complex FilterContention Bit 13 01 Complex 11 Magnitude Read only status bit 0 No dual access occurred 1 Core and EFCOP tried to access the same bank in FDM or FCM FilterSaturation Bit 12 Channels Bit 6 0 Single channel 1 Multichannel Initialization Bit 7 0 Preprocess initialization 1 No initialization Filter Data Input Buffer Empty Bit 14 Read only status bit 0 FDIR is not empty 1 FDIR is empty Coefficients Bit 8 0 Not shared Filter Data Output Buffer Full Bit 15 1 Shared Read only status bit 0 FDOR is not full 1 FDOR is full 23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 k KKK KL KLE rae ae mu FSAT FDOE FDIE Xe FSCOJFPCR FMLC FOM1 FOMO FUPD FADP FLT FEN 0 10 0 0 0 0 0 0 0 EFCOP Control Status Register FCSR Reserved Program as 0 Y FFFFB4 Read Write Reset 000000 Figure B 29 EFCOP Counter and Control Status Registers FCNT and FCSR DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Filter Rounding Mode Bits 3 2 Saturation Moge pirs 01 ae Filter Scaling Bits 1 0 0 Disabled _1 Enabled 10 Truncation 00 x1 10 x 16 11 Reserved 01 x 8 11 Reserved Sixteen bit Arithmetic Mode Bit 5 0 Disabled 1 Enabled Filter Input Scaling Bit 6 0 Not used 1 Used Filter Scaling EFCOP ALU Control Register FACR x
79. Receive Last Slot VBA 36 0 2 ESSIO Transmit Data VBA 38 0 2 ESSIO Transmit Data With Exception Status VBA 3A 0 2 ESSIO Transmit Last Slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 ESSI1 Receive Data VBA 42 0 2 ESSI1 Receive Data With Exception Status VBA 44 0 2 ESSI1 Receive Last Slot VBA 46 0 2 ESSI1 Transmit Data VBA 48 0 2 ESSI1 Transmit Data With Exception Status VBA 4A 0 2 ESSI1 Transmit Last Slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI Receive Data VBA 52 0 2 SCI Receive Data With Exception Status VBA 54 0 2 SCI Transmit Data VBA 56 0 2 SCI Idle Line VBA 58 0 2 SCI Timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved Motorola Programming Reference B 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Sources and Priorities Table B 4 Interrupt Sources Continued Interrupt pipi Interrupt Source Starting Address Level Range VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA 68 0 2 EFCOP Data Input Buffer Empty VBA 6A 0 2 EFCOP Data Output Buffer Full VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA FE 0 2 Reserved Table B 5 Interrupt Source Priorities Within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error
80. Register TPCR Table 9 2 Timer Prescalar Count Register TPCR Bit Definitions Bit Number Bit Name Reset Value Description 23 21 0 Reserved Write to zero for future compatibility 20 0 PC 20 0 0 Prescalar Counter Value Contain the current value of the prescalar counter 9 4 4 Timer Control Status Register TCSR The TCSR is a read write register controlling the timer and reflecting its status 23 22 21 20 19 18 17 16 15 14 13 12 TCF TOF PCE DO DI 11 10 9 8 7 6 5 4 3 2 1 0 DIR TRM INV TC3 TC2 TC1 TCO TCIE TOIE TE Reserved Read as 0 Write with O for future compatibility Figure 9 23 Timer Control Status Register TCSR Table 9 3 Timer Control Status Register TCSR Bit Definitions Bit Number Bit Name Reset Value Description 23 22 0 Reserved Write to zero for future compatibility 9 24 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 21 TCF 0 Timer Compare Flag Indicate that the event count is complete In timer PWM and watchdog modes the TCF bit is set after M N 1 events are counted M is the value in the compare register and N is the TLR value In measurement modes the TCF bit is set when the measurement completes Writing a one to the TCF bit clears it A zer
81. SIIQ JO JoquinN 01M FIM J0 3u02 u1Bue p10A ISSA CRA ESSI Control Register A 15 igure F DSP56311 User s Manual Motorola For More Information On This Product B 26 Go to www freescale com Freescale Semiconductor Inc Programming Sheets 000000 1eseu eiiWpeeu 984444 0ISS3 XguH2 g 1eisiDeu jonuo2 W 40 oaosjtaos zaosjayosja4HS 0S4 HS4 usd PEREEEMERMEENEEEN ISS4 8 6 OL LL ZL EF vL SE 9L ZLE SL 6L 0c Ic ce Ee eiqeu3 eigqesiq 0 e qeu3 1dnue1u uondeox3 eAle280H eiqeu3 eigqesiq 0 9 qeu3 1dnujeju uondaeox3 usuel e9jqeu3 ejgesid 0 eiqeu3 1dnuelu 10IS ISV eAie2eH eiqeu3 ejgesid 0 e qeu3 1dnueiu 10JS 1s 1 uisuejJ L eigeu3 aiqesiq 0 eiqeu3 1dnueju eaisoey jqeuJ aigesiq 0 giqeuz 1dnueju jusueJ Yyoo D Jeusaju 90J9 jeuselxy 0 eiqeu3 e qesiq 0 uonoeiJig eounos Y42019 e qgeu3 1eAle2eH eigeu37 aiqesiq 0 SJl4 dS17 S4 GSW 0 uonoaiig uus e qeu3 0 pusug eigeu3 eigesiq 0 indino yndu 0 Ajuo L NAS ejqeu3 WWwSued Sq uoroeur O4JUOD eas aiqeuz aiqesiq 0 fuo L NAS eigeua z Wwsued YIOMION L euuoN 0 uld XOS XJO 99 8S PON L LAOS PU NAS IH snouoiyouAS SnouoJugou sy 0 x Bej4 1ndino 10u 10 1941960 JaJSUeI XH 9 XL OUD ou Asy ou S ug pJoM Buie uo 1no Gussu uo u Burger uo ul Bursu uo 1n0 2 Q 1g ug UIANO pexoojo ou S
82. SYNC N FSLO 0 FSL1 0 Frame SYNC N N FSLO 0 FSL1 1 Slot 0 Wait Slot 0 Figure 7 9 Normal Mode External Frame Sync 8 Bit 1 Word in Frame Frame SYNC X4 fF ND FSLO 0 FSL1 0 Frame SYNC EM MN 0 FSLO 0 FSL1 1 Dat OXI KKK KKK SLOT 0 SLOT 1 v SLOT 0 c SLOT i Figure 7 10 Network Mode External Frame Sync 8 Bit 2 Words in Frame 7 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 7 5 3 ESSI Status Register SSISR The SSISR is a 24 bit read only status register by which the DSP reads the ESSI status and serial input flags 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF1 IFO ESSIO X FFFFB7 ESSI1 X FFFFA7 Figure 7 11 ESSI Status Register SSISR Table 7 5 ESSI Status Register SSISR Bit Definitions Bit Number Bit Name Reset Value Description 23 8 0 Reserved Set to 0 for future compatibility 7 RDF 0 Receive Data Register Full Set when the contents of the receive shift register transfer to the receive data register RDF is cleared when the DSP reads the receive data register If RIE is set a DSP receive data interrupt request is issued when RDF is set 6 TDE 0 Transmit Data Register Empty Set when the contents of the transmit dat
83. Status Register HSR The HSR is a 16 bit read only status register by which the reads the HIO8 status and flags The host processor cannot access it directly The initialization values for the HSR bits are discussed in Section 6 6 9 DSP Side Registers After Reset on page 6 22 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 HF1 HFO HCP HTDE HRDF Reserved bit read as 0 should be written with 0 for future compatibility Figure 6 7 Host Status Register HSR X FFFFC3 Table 6 8 Host Status Register HSR Bit Definitions Bit Number Bit Name Reset Value Description 15 5 0 Reserved Set to 0 for future compatibility 4 3 HF 1 0 0 Host Flags 0 1 General purpose flags for host to DSP communication These bits reflect the status of host flags HF 1 0 in the ICR on the host side These two general purpose flags can be used individually or as encoded pairs in a simple host to DSP communication protocol implemented in both the DSP and the host processor software 2 0 Host Command Pending Reflects the status of the CVR HC bit When set it indicates that a host command interrupt is pending HI08 hardware clears HC and HCP when the DSP core services the interrupt request If the host clears HC HCP is also cleared 1 HTDE 0 Host Transmit Data Empty Indicates that the host transmit data register HTX is empty and can be
84. Synchronize Select Bit 11 00 X Memory 4000 BFFF im See Y Memory 4000 BFFF o MO S08 i id Bus Release Timing Bit 12 0 Fast Bus Release mode 10 X Memory 8000 BFFF 1 Slow Bus Release mode Y Memory 8000 BFFF 11 X Memory A000 BFFF Y Memory A000 BFFF 23 C22 20 21 2019 18 17 16 15 14 a 12 11 10 9 Ei sabitini dni pd e E e e e Operating Mode Register Reserved Program as 0 Reset 000300 Figure B 2 Operating Mode Register Motorola Programming Reference B 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Central Processor Bus Number of Address Bits to Compare Bits 11 8 BNC 3 0 number of bits from BAC bits that are compared to the external address Combinations BNC 3 0 1111 1110 1101 are reserved Bus Address to Compare Bits 23 12 BAC 11 0 address to compare to the Bus Packing Enable Bit 7 0 Disable internal packing unpacking logic 1 Enable internal packing unpacking logic Bus Y Data Memory Enable Bit 5 0 Disable AA pin and logic during external Y data space accesses 1 Enable AA pin and logic during external Y data space accesses Bus X Data Memory Enable Bit 4 0 Disable AA pin and logic during external X data space accesses 1 Enable AA pin and logic during ext
85. Timer 0 Compare Register TCPRO FF8C FFFF8C Timer 0 Count Register TCRO FF8B FFFF8B Timer 1 Control Status Register TCSR1 FF8A FFFF8A Timer 1 Load Register TLR1 FF89 FFFF89 Timer 1 Compare Register TCPR1 FF88 FFFF88 Timer 1 Count Register TCR1 FF87 FFFF87 Timer 2 Control Status Register TCSR2 FF86 FFFF86 Timer 2 Load Register TLR2 FF85 FFFF85 Timer 2 Compare Register TCPR2 FF84 FFFF84 Timer 2 Count Register TCR2 FF83 FFFF83 Timer Prescaler Load Register TPLR FF82 FFFF82 Timer Prescaler Count Register TPCR FF81 FFFF81 Reserved FF80 FFFF80 Reserved Table B 3 Internal Y I O Memory Map Peripheral Paus Found Register Name FFBF FFFFBF Reserved FFBE FFFFBE Reserved FFBD FFFFBD Reserved FFBC FFFFBC Reserved FFBB FFFFBB Reserved FFBA FFFFBA Reserved FFB9 FFFFB9 Reserved Motorola Programming Reference B 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Sources and Priorities Table B 3 Internal Y I O Memory Map Peripheral i Pee Register Name Enhanced Filter FFB8 FFFFB8 EFCOP Decimation Channel FDCH Register Coprocessor EFCOP FFB7 FFFFB7 EFCOP Coefficient Base Address FCBA FFB6 FFFFB6 EFCOP Data Base Address FDBA FFB5 FFFFB5 EFCOP ALU Control Register FACR FFB4 FFFFB4 EFCOP Control Status Register FCSR FFB3 FFFFB3 EFCOP Filter Count FCNT Register FFB2 FFFFB2 E
86. Timer1 Overflow Interrupt Timer1 Compare Interrupt Timer2 Overflow Interrupt Timer2 Compare Interrupt EFCOP Data Input Buffer Empty Lowest EFCOP Data Output Buffer Full Motorola Programming Reference B 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets B 3 Programming Sheets Central Processor Ove Negative Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Interrupt Mask Scaling Mode Exceptions Masked Scaling Mode None No scaling IPL O Scale down IPL 0 1 Scale up IPL 0 1 2 Reserved Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteenth Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority Core Priority 0 lowest 1 2 3 highest f C LX fT 23 22 21 20419 18 17 16 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 CELLS aE ETE EC EEE TETE c c JJ Extended Mode Register MR Mode Register MR Condition Code Register CCR Status Register SR Read Write Reset C00300 se Reserved Program as 0 Figure B 1 Status Register SR B 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Fre
87. Transmit Data Shift Register 23 16 15 8 7 T 0 Sn Saas STXA SCI Transmit Data Address Register Write Only Note Bytes are masked on the fly 1 STX is the same register decoded at four different addresses b Transmit Data Register Figure 8 8 SCI Programming Model Data Registers 8 6 4 1 SCI Receive Register SRX Data bits received on the RXD signal are shifted into the SCI receive shift register When a complete word is received the data portion of the word is transferred to the byte wide SRX This process converts serial data to parallel data and provides double buffering Double buffering promotes flexibility and increased throughput since the programmer can save and process the previous word while the current word is being received The SRX can be read at three locations as SRXL SRXM and SRXH When SRXL is read the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are read as zeros Similarly when SRXM is read the contents of SRX are placed into the middle byte of the bus and when SRXH is read the contents of SRX are placed into the high byte with the remaining bits are read as Os This way of mapping SRX efficiently packs three bytes into one 24 bit word by ORing three data bytes read from the three addresses Motorola Serial Communication Interface SCI 8 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI
88. VEC 4A ESSII Transmit last slot I SCIRD EQU I VEC 50 SCI Receive Data I SCIRDE EQU I VEC 52 SCI Receive Data With Exception Status I SCITD EQU I VEC 54 SCI Transmit Data I SCHL EQU I VEC 56_ SCIIdle Line I SCITM EQU I VEC 58 SCI Timer I HRDF EQU I _VEC 60_ Host Receive Data Full I HTDE EQU I VEC 62_ Host Transmit Data Empty I HC EQU I VEC 64 Default Host Command Motorola Bootstrap Program For More Information On This Product Go to www freescale com Interrupt Equates A 21 Freescale Semiconductor Inc Interrupt Equates I FDIBE EQU I VEC 68 EFCOP Input Buffer Empty I FDOBF EQU I VEC4 6A EFCOP Output Buffer Full I INTEND EQU I VEC FF last address of interrupt vector space A 22 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Appendix B Programming Reference This reference for programmers includes a table showing the addresses of all DSP memory mapped peripherals an exception priority table and programming sheets for the major programmable DSP registers The programming sheets are grouped in the following order central processor Phase Lock Loop PLL Host Interface HIO8 Enhanced Synchronous Serial Interface ESSI Serial Communication Interface SCI Timer GPIO and EFCOP Each sheet provides room to write in the value of each bit and the hexadecimal value for each register Yo
89. Vcc GND or left floating PINIT Input Input PLL Initial During assertion of RESET the value of PINIT is written into the PLL enable PEN bit of the PLL control PCTL register determining whether the PLL is enabled or disabled Nonmaskable Interrupt After RESET deassertion and during NMI Input normal instruction processing this Schmitt trigger input is the negative edge triggered NMI request internally synchronized to the internal clock 2 5 External Memory Expansion Port Port A When the DSP56311 enters a low power standby mode stop or wait it releases bus mastership and tri states the relevant Port A signals A0 A17 D0 D23 AAO RASO AA3 RAS3 RD WR BB CAS 2 5 1 External Address Bus Table 2 6 External Address Bus Signals State During zd Signal Name Type Reset Signal Description A0 A17 Output Tri stated Address Bus When the DSP is the bus master A0 A17 are active high outputs that specify the address for external program and data memory accesses Otherwise the signals are tri stated To minimize power dissipation A0 A17 do not change state when external memory spaces are not being accessed 2 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Memory Expansion Port Port A 2 5 2 External Data Bus Table 2 7 External Data Bus Signals State During Signal
90. a dD ari aa E ara aa a aaa aaa anes 7 6 7 3 1 ESS Aller Reset ciu sou oeeees aden sey eke ee eee ca AE EENE ATARE 7 6 Gio Aiilalizaoie 4422 secon Sdevsee eG Gc sehr R RES E heb G RE E a 7 6 Teneo SEXCSD UOHS s 2 Jou done iea eaa coe soa ey dedit dco eae dee DA EEEa 7 8 7 4 Operating Modes Normal Network and On Demand 7 10 7 4 1 Normal Network On Demand Mode Selection lslslleleleeeeee 7 10 1 4 2 Synchronous Asynchronous Operating Modes 0 000 lessen 7 11 TS Brame Syne Selecto 2 a c45 cduer anes radenn EAEE EEE EEEE eases 7 11 7 44 4 Frame Sync Signal Format oi ecu ceduca tes donee du he re ya coals SU e Gee GS 7 11 7 4 5 Frame Sync Length for Multiple Devices eee 7 12 7 4 6 Word Length Frame Sync and Data Word Timing 0000 7 12 7 4 7 Frame Sync Polarity 2s ca sek a RU REX RR Ra dh ea aha bad xs 7 12 7 4 8 Byte Format LSB MSB for the Transmitter 0 0 00 0 e eee 7 13 pECIEME UO Pr 7 13 7 5 ESSI Programming MouUel z 424ecrberakr teeeckherePesxemQreces dd et qua 7 14 7 5 1 ESSI Control Register A CRA ioorhosou ens Rak ERERDRR ERE Rd Adr ERR 7 14 7 5 2 ESSI Control Register B CRB 0 c eee eee eee teens 7 18 7 5 3 ESSI Status Register SSISR 5 2522 opecesnsbod aUmpmpPDE STO Rd HERO HAS ages 7 29 7 5 4 ESS Receive Shift Register 2 25 di224 d d b RR dd bia ERR URE RR ado ee 7 31 7 5 5 ESSI Receive Data Register RX 14 4
91. a normal counter bit 16 XYS 0 Stack Extension XY Select Determines whether the stack extension is mapped onto X or Y memory space If the bit is clear then the stack extension is mapped onto the X memory space If the XYS bit is set the stack extension is mapped to the Y memory space 15 0 Reserved Set to 0 for future compatibility 14 APD 0 Address Attribute Priority Disable Disables the priority assigned to the Address Attribute signals AA0 AA3 When APD 0 default setting the four Address Attribute signals each have a certain priority AA3 has the highest priority AAO has the lowest priority Therefore only one AA signal can be active at one time This allows continuous partitioning of external memory however certain functions such as using the AA signals as additional address lines require the use of additional interface hardware When APD is set the priority mechanism is disabled allowing more than one AA signal to be active simultaneously Therefore the AA signals can be used as additional address lines without the need for additional interface hardware For details on the Address Attribute Registers see Section 4 8 Address Attribute Registers AARO AAR3 on page 4 22 4 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Mode Register OMR Table 4 6 Operating Mode Register OMR Bit
92. a receiver error parity framing or overrun error To clear the pending interrupt read the SCI status register then read SRX Use a long interrupt service routine to handle the error condition This interrupt is enabled by SCR 16 REIE 2 SCI receive data occurs when the receive data register is full Read SRX to clear the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR 11 RIE 3 SCItransmit data occurs when the transmit data register is empty Write STX to clear the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR 12 TIE 4 SCI idle line occurs when the receive line enters the idle state 10 or 11 bits of ones This interrupt is latched and then automatically reset when the interrupt is accepted This interrupt is enabled by SCR 10 ILIE 5 SCItimer occurs when the baud rate counter reaches zero This interrupt is automatically reset when the interrupt is accepted This interrupt is enabled by SCR 13 TMIE 8 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model 8 6 SCI Programming Model The SCI programming model can be viewed as three types of registers m Control SCI Control Register SCR in Figure 8 3 SCI Clock Control Regis
93. and FDOBE are cleared while the EFCOP is in the Individual Reset state The most straightforward EFCOP data transfer method uses the core processor to poll the status flags monitoring for input output service requests The disadvantage of this approach is that it demands large amounts of if not all of the core s processing time The interrupt and DMA methods are more efficient in their use of the core processor Interrupts intervene on the core processor infrequently to service input output data DMA can operate concurrently with the processor core and demands only minimal core resource for setup DMA transfers are recommended when the EFCOP is in FIR IIR filtering mode since the core can operate independently of the EFCOP while DMA transfers data to the FDIR and from the FDOR Since the EFCOP input buffer FDIR is four words deep the DMA can input in blocks of up to four words A combination of Motorola Enhanced Filter Coprocessor EFCOP 10 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes DMA transfer for input and an interrupt request for processing the output is recommended for adaptive FIR mode This combination gives the following benefits m Input data transfers to the FDIR can occur independently of the core B There is minimal intervention of the core while the weight update multiplier is updated If the initialization mode is enabled that i
94. and SCLK signals can be programmed for GPIO However at least one of the three signals must be selected as an SCI signal to release the SCI from reset Motorola Serial Communication Interface SCI 8 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI After Reset To enable SCI interrupts program the SCI control registers before any of the SCI signals are programmed as SCI functions In this case only one transmit interrupt can be generated because the Transmit Data Register is empty The timer and timer interrupt operate regardless of how the SCI pins are configured either as SCI or GPIO 8 2 1 Receive Data RXD This input signal receives byte oriented serial data and transfers the data to the SCI receive shift register Asynchronous input data is sampled on the positive edge of the receive clock 1 x SCLK if the SCI Clock Polarity SCKP bit is cleared RXD can be configured as a GPIO signal PEO when the SCI RXD function is not in use 8 2 2 Transmit Data TXD This output signal transmits serial data from the SCI transmit shift register Data changes on the negative edge of the asynchronous transmit clock SCLK if SCKP is cleared This output is stable on the positive edge of the transmit clock TXD can be programmed as a GPIO signal PE1 when the SCI TXD function is not in use 8 2 3 SCI Serial Clock SCLK This bidirectional signal provides an input or output clock from w
95. as follows 8 bit synchronous shift register mode 10 bit asynchronous 1 start 8 data 1 stop 11 bit asynchronous 1 start 8 data 1 even parity 1 stop 11 bit asynchronous 1 start 8 data 1 odd parity 1 stop 11 bit multidrop asynchronous 1 start 8 data 1 data type 1 stop This mode is used for master slave operation with wake up on idle line and wakeup on address bit capability It allows the DSP56311 to share a single serial line efficiently with other peripherals These modes are selected by the SCR WD 0 2 bits Synchronous data mode is essentially a high speed shift register for I O expansion and stream mode channel Motorola Serial Communication Interface SCI 8 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes interfaces A gated transmit and receive clock compatible with the Intel 8051 serial interface mode 0 synchronizes data Asynchronous modes are compatible with most UART type serial devices Standard RS232C communication links are supported by these modes Multidrop Asynchronous mode is compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface 8 1 1 Synchronous Mode Synchronous mode WDS 0 Shift Register mode handles serial to parallel and parallel to serial conversions In Synchronous mode the clock is always common to the transmit and receive shift registers As a controller synchronous master
96. at high speed The host can access the HIO8 asynchronously using polling techniques or interrupt based techniques The HIO8 appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space See Table 6 13 The eight HIOS registers include the following Acontrol register ICR on page 6 24 m A status register ISR on page 6 28 m Three data registers RXH TXH RXM TXM and RXL TXL on page 6 30 B Two vector registers CVR and IVR on page 6 27 and page 6 30 To transfer data between itself and the HI08 the host processor bus performs the following steps 1 Asserts the HIOS8 address and strobes to select the register to be read or written Chip select in non multiplexed mode the address strobe in multiplexed mode 2 Selects the direction of the data transfer If it is writing the host processor sources the data on the bus Otherwise the HIOS places the data on the bus 3 Strobes the data transfer Host processors can use standard host processor instructions for example byte move and addressing modes to communicate with the HIOS registers The HIOS registers are aligned so that 8 bit host processors can use 8 16 or 24 bit load and store instructions for data transfers The HREQ HTRQ and HACK HRRQ handshake flags are provided for polled or interrupt driven data transfers with the host processor Because of the speed of the DSP56311 interrupt response most host micro
97. be chosen carefully An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI When the SCI is configured in Synchronous mode internal clock and all the SCI pins are simultaneously enabled an extra pulse of one DSP clock length is provided on the SCLK pin There are two workarounds for this issue m Enable an SCI pin other than SCLK m In the next instruction enable the remaining SCI pins including the SCLK pin Following is an example of one way to initialize the SCI 1 Ensure that the SCI is in its individual reset state PCRE 0 2 Configure the control registers SCR SCCR according to the operating mode but do not enable transmitter TE 0 or receiver RE 0 It is now possible to set the interrupts enable bits that are used during the operation No interrupt occurs yet 8 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Initialization 3 Enable the SCI by setting the PCRE bits according to which signals are used during operation 4 If transmit interrupt is not used write data to the transmitter If transmitter interrupt enable is set an interrupt is issued and the interrupt handler should write data into the transmitter The DMA channel services the SCI transmit request if it is programmed to service the SCI transmitter 5 Enable transmitters TE 1 and
98. bit mode is not shown 2 16 15 3 87 0 Transmit High Byte Transmit Middle Byte Transmit Low Byte 0 dm m ESSI Transmit Transmit High Byte Transmit Middle Byte Transmit Low Byte Shift Register 7 0 7 07 0 n 8 bit Data 0 0 0 Least Significant Zero Fill LSB MSB 12 bit Data LSB 16 bit Data ESSI Transmit Data Register LSB 24 bit Data b Transmit Registers NOTES Data is transmitted MSB first if SHFD 0 4 bit fractional format ALC 0 32 bit mode is not shown Figure 7 12 ESSI Data Path Programming Model SHFD 0 7 32 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 23 16 15 87 0 Receive High Byte Receive Middle Byte Receive Low Byte E 23 16 15 07 0 Receive High Byte Receive Middle Byte Receive Low Byte ESSI Receive r Shift Register 7 0 7 07 eo MSB LSB 8 bit Data Ls 0 0 0 Least Significant Zero Fill LSB 12 bit Data LSB 16 bit Data LSB 24 bit Data NOTES a Receive Registers Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 2 bi i h 2 16 15 87 32 bit mode js not shown 3 ESSI Transmit Data Transmit High Byte Transmit Middle Byte Transmit Low Byte Register Write Only ESSI Transmit Shift Register MSB 7 24 Bit 8 Bit MSB LSB 8 bit Data TONS 0 0 0 WL1 WLO
99. can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 17 Memory Switch On MSW 10 Cache Off 16 Bit Mode Motorola Memory Configuration 3 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data 2i dia External I O Internal I O FFCO FF80 FF80 Internal I O FFFF External External Internal Program RAM 63K C000 C000 A000 A000 Internal X data Internal Y data 0000 Reserved 0000 PRAM 24K 0000 PAM 24K Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 10 1 1 63K 24K 24K Enabled 64K 0400 FFFF 0000 9FFF 0000 9FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 18 Memory Switch On MSW 10 Cache On 16 Bit Mode 3 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data VERRE IPEFF External I O Internal I O FFCO Reserved FF80 FF80 Internal I O FFFF External External C000 C000 C000 Reserved Reserved A000 A000 Internal Internal X data Internal Y data i RAM RAM 40K RAM 40K 0000
100. capacitors GNDA Address Bus Ground An isolated ground for sections of the address bus I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are four GND 4 connections 2 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Table 2 3 Ground Continued Signals Ground Description Name R GNDp Data Bus Ground An isolated ground for sections of the data bus I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors GNDc Bus Control Ground An isolated ground for the bus control I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors GNDy Host Ground An isolated ground for the HI08 I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors GNDg ESSI SCI and Timer Ground An isolated ground for the ESSI SCI and timer I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors 2 3 Clock Table 2 4 Clock Signals Signal S
101. chip power inputs except Voca The user must provide adequate external decoupling capacitors Vccc Bus Control Power An isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs except Vcco The user must provide adequate external decoupling capacitors VccH Host Power An isolated power for the HIO8 I O drivers This input must be tied externally to all other chip power inputs except Vcco The user must provide adequate external decoupling capacitors Vccs ESSI SCI and Timer Power An isolated power for the ESSI SCI and timer I O drivers This input must be tied externally to all other chip power inputs except Voca The user must provide adequate external decoupling capacitors 2 2 Ground Table 2 3 Ground Signals Ground Name Description GNDp PLL Ground A ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground Vccp should be bypassed to GNDp by a 0 47 uF capacitor located as close as possible to the chip package GNDp PLL Ground 1 A ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground GNDo Quiet Ground An isolated ground for the internal processing logic This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling
102. clock cycles between signals set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled Mode 1 internal clock TRM 1 N write preload first event M write compare Y TE Clock NL IL l CLK 2 or prescale CLK TLR bw N 7 Counter TCR 0 N N 1 M N TCPR lt M TCF Compare Interrupt if TCIE 1 C TIO pin INV 0 pulse width timer clock TIO pin INV 1 period Figure 9 5 Pulse Mode TRM 1 Motorola Triple Timer Module 9 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Mode 1 internal clock TRM 0 N write preload first event M write compare TE Clock _ CLK 2 or prescale CLK TLR N Counter TCR E X N ve M XM 1 0 X4 TCPR XM TCF Compare Interrupt if TCIE 1 TIO pin INV 0 pulse width timer clock iod TIO pin INV 1 ai TOF Overflow Interrupt if TCIE 1 Figure 9 6 Pulse Mode TRM 0 9 3 1 3 Timer Toggle Mode 2 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 1 0 2 Toggle Timer Output Internal In Mode 2 the timer periodically toggles the polarity of the TIO signal When
103. configuration such as a master slave multidrop configuration An external pullup resistor is required on the bus When WOMS is cleared the TXD signal uses an active internal pullup Either a hardware RESET signal or a software RESET instruction clears WOMS 8 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 6 RWU 0 Receiver Wakeup Enable When RWU is set and the SCI is in Asynchronous mode the wakeup function is enabled i e the SCI is asleep and can be awakened by the event defined by the WAKE bit In Sleep state all interrupts and all receive flags except IDLE are disabled When the receiver wakes up RWU is cleared by the wakeup hardware You can also clear the RWU bit to wake up the receiver You can use RWU to ignore messages that are for other devices on a multidrop serial network Wakeup on idle line i e WAKE is cleared or wakeup on address bit i e WAKE is set must be chosen When WAKE is cleared and RWU is set the receiver does not respond to data on the data line until an idle line is detected When WAKE is set and RWU is set the receiver does not respond to data on the data line until a data frame with Bit 9 set is detected When the receiver wakes up the R
104. controller SRIINT is not directly accessible to the user When a valid start bit is received an idle interrupt is generated if both IDLE and ILIE are set The idle interrupt acknowledge from the interrupt controller clears this interrupt request The idle interrupt is not asserted again until at least one character has been received The results are as follows E The IDLE bit shows the real status of the receive line at all times W An idle interrupt is generated once for each idle state no matter how long the idle state lasts Motorola Serial Communication Interface SCI 8 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 9 TE 0 Transmitter Enable When TE is set the transmitter is enabled When TE is cleared the transmitter completes transmission of data in the SCI transmit data shift register and then the serial output is forced high that is idle Data present in the SCI transmit data register STX is not transmitted STX can be written and TDRE cleared but the data is not transferred into the shift register TE does not inhibit TDRE or transmit interrupts Either a hardware RESET signal or a software RESET instruction clears TE Setting TE causes the transmitter to send a preamble of 10 or 11 cons
105. count is complete 9 25 operating modes 9 4 polarity definition of the incoming signal on the TIO signal 9 26 reflect value of TIO signal 9 25 select prescalar clock as the timer source clock 9 25 source of TIO value when it is a data output signal 9 25 special cases 9 21 timer compare interrupts enable 9 28 Timer GPIO 5 9 timer after Reset 9 2 Timer Compare exception 9 3 Timer Compare Register TCPR 9 3 9 30 Timer Control Register 9 2 Timer Control Status Register TCSR 9 24 Data Input 9 25 Data Output 9 25 Direction 9 26 Inverter 9 26 Prescalar Clock Enable 9 25 Timer Compare Flag 9 25 Timer Compare Interrupt Enable 9 28 Timer Control 9 27 Timer Enable 9 28 Timer Overflow Flag 9 25 Timer Overflow Interrupt Enable 9 28 Timer Reload Mode 9 26 Timer Control Status Register TCSR bit definitions 9 24 Timer Count Register TCR 9 30 Timer Enable bit TE 9 24 timer exception configuring 9 4 timer exceptions 9 3 Timer GPIO Mode 0 9 5 timer initialization 9 2 9 3 Timer Load Register TLR 9 29 timer mode Index 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc mode 5 measurement input period 9 13 mode 6 measurement capture 9 15 mode 7 pulse width modulation 9 16 mode 8 reserved 9 19 mode 9 watchdog pulse 9 19 mode 10 measurement toggle 9 20 modes 11 15 reserved 9 21 Timer module 1 14 architecture 9 1 timer block diagram 9 1 timer opeating modes PWM
106. e pde RR pude e da d aped 3 7 35334 External Y I O Spaces i262 ERE ERR RE REA HE RERPR ARR E RR dor 3 7 3 4 Dynamic Memory Configuration Switching 0 0 0 0 cece eee eee 3 7 3 5 Sixteen Bit Compatibility Mode Configuration 0 0 00 0002 ee aes 3 8 3 6 Memory Maps iieencetide nube TI Ie ROC ARENE PETER TER ARP QUARO TAM EMT 3 8 Chapter 4 Core Configuration 4 1 Operating Modes vos e aps Oe ane obese ba RO S ard ee bees BEE eee ake 4 1 4 2 Bootstrap Prostam iso d E radar a E aaie steht ee ada acce Rara iei 4 4 4 3 Interrupt Sources and Priorities ise ERR YU REA RET ARPqERRerA AXXd ad 4 4 4 3 1 TUS PE SOM CES on nessa oe eee hocks epee own ees ke RE one Gewese dew eee 4 5 4 3 2 Interrupt Priority Levels 2 22422 0cs cece eee eR e re m 9n 4 7 4 3 3 Interrupt Source Priorities Within an IPL 1 4 8 434 DMA Request Sources cuoc RR ER ERRARE REX betes bev ERU EK ERE dox 4 10 4 4 Operating Mode Register OMR ssseeeeeee e 4 1 4 5 Status Register SR eus ees eky esu ub Ree Pix OPE RAP RE Rex T i ed 4 15 4 6 PEL Control Register PUT case os pezenret haee E TERPCERET REDUX ACE quA 4 21 4 7 Device Identification Register IDR 2 4 eacevasedea e XE p REPE SES 4 22 4 8 Address Attribute Registers AARO AAR3 1 0 0 0 0 eee ee eee 4 22 4 9 JTAG Identification ID Register duce cua s oa ER WERE RACE oh 04 4 25 4 10 JTAG Boundary Scan Register BSR 0 eee eee eee eee ees 4 25 Motorola DSP56311 User
107. eceern sere RO RPEREPARE D ERR rar 7 31 7 5 6 ESSI Transmit Shift Registers assez scere r RP Ier EXE Tr ES 7 31 7 5 7 ESSI Transmit Data Registers TX 2 O lecce III 7 34 7 5 8 ESSI Time Slot Register TSR 042 40420dedwev eased o ie face E R a ES 24 7 34 7 5 9 Transmit Slot Mask Registers TSMA TSMB 0 20 e eee ee eee 7 34 7 5 10 Receive Slot Mask Registers RSMA RSMB 0 0 02 c eee eee eee 7 35 7 6 GPIO Signals and Revisters 2 2 oudodcveavad os seexdedweees toes xe ERR 7 36 7 6 1 Port Control Register PCR uuu saeya xd EXC ERECE QR hee eeaeeee EE 7 36 7 6 2 Port Direction Register PRR iue duh Re 9E eens Rx E ERE EA E ERLNA EAS 7 37 7 6 3 Port Data Register PDR iiis RR be a ERE IRR UHR E ERA ERES 7 38 Motorola DSP56311 User s Manual vi For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 8 Serial Communication Interface SCI 8 1 Operins Modes cc ioe eee ee RA RR RAWRRREREQSCRPS SX REX E MORES T 8 1 8 1 1 Synchronous Mode os eee cree ehh ET eda SEAT E ERES dE E Ig IRR 8 2 8 1 2 Asynchronous Mod6 5 2 cecasecasess sds acetage est s rre reder ieradas 8 2 8 1 3 Mu ltidrop Mod s srecen rT epr undasa ea a a O ed pe S Rd E RUE 8 2 8 1 3 1 Transmitting Data and Address Characters 0 0 0 cece eee eee 8 3 BI32 Wir ed OR Mode s s54 0404 ur doa ERR RUE RR S ge PT op CR RR 8 3 BIOS Ale line Wakeup c dense ek ia ERE RE tesieni
108. eureJJ 3 eyep eDpe xi Auejogd 42019 pJoM ug eAneDeu e e Mo e nisod jane uBiu 0 pJoM PJONA Ayuejod ou S owes Xu XL 4q ejepis ueurjJejiee BOAO yOO O L Iq BYP ISL uM 0 uiuo ou S aure14 Auo ou s eure14 IM Buru L eAgejeg OUAS ewes CRB ESSI Control Register B 16 igure F Programming Reference B 27 For More Information On This Product Motorola Go to www freescale com Freescale Semiconductor Inc Programming Sheets Serial Input Flag 0 If SCDO 0 SYN 1 amp TE1 0 latch SCO on FS Serial Input Flag 1 If SCD1 0 SYN 1 amp TE2 0 latch SCO on FS Transmit Frame Sync 0 Sync Inactive 1 Sync Active Receive Frame Sync 0 Wait 1 Frame Sync Occurred Transmitter Underrun Error Flag 0 OK 1 Error Receiver Overrun Error Flag 0 OK 1 Error Transmit Data Register Empty 0 Wait 1 Write Receive Data Register Full 0 Wait 1 Read ESSI Status Register SSISRx ESSIO FFFFB7 Read ESSI1 FFFFA7 Read SSI Status Bits Reserved program as 0 Figure B 17 ESSI Status Register SSISR B 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com ESSI ESSI Transmit Slot Mask A TSMAx ESSIO FFFFB4 Read Write ESSI1 FFFFA4 Read Write Reset FFFF ESSI Transmit Slot Mask B TSMBx ESSIO FFFFB3 Read Write ESSI1 FFFFA3 Read Write Reset FFFF ESSI R
109. fp KOKORUWORORE ROKOKUOK KORG KON UK EAL AEE ES E YCNCNOK OKCKORCRONCKORCKOKORCRCNCKOKCAOKORCROR KORCKORORCKCROORCKUKORKCACKOROR RUN E ORCROROKCRCR UE ROW OROR EK EEE equates pOONKORURORRROKOKUK KC EERE ORE OEICNONKUR AK CREEK RUN KORGKKOR RN ROR CKOKCIEROR ERA RARE EA EAEER EKRER ERA ER ROWOROR EK EK Start equ 00100 main program starting address FCON equ 805 EFCOP FSCR register contents enable output interrupt Choose adaptive real FIR mode enable the EFCOP FIR LEN equ 20 EFCOP FIR length Motorola DSP56311 User s Manual 10 34 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DES ADDRS equ 3200 SRC ADDRS equ 3100 DST_ADDRS equ 3000 SRC_COUNT equ 06003 DST_COUN equ 8 MU2 equ 100000 FDBA ADDRS equ 0 FCBA ADDRS equ 0 Examples of Use in Different Modes Desired signal R n Reference signal D n address at which to begin output signal F n DMAO count 7 4 word transfers number of outputs generated stepsize mu 0 0625 that is 2mu 0 125 Input samples Start Address x 0 Coeff Start Address y 0 pK CK kk hehe CK KO CK KK koe ke e kk kk eee ek ok KKK KREK ERK KR REK EKER EKER KER EK EKER ER EKERE EKER ERERKE ER org p 0 jmp Start ORG p 6a jsr gt kdo nop nop pp RRRRRRRRRER ERR R KER ER EKER EE KERR EK ERR EER EERE EER ER KERR KER REE RR EE REE KER KK ERK ERE EKER KEKE KEK KK Main program pp ECCE kdek k
110. hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears FE In 8 bit Synchronous mode FE is always cleared If the byte received causes both framing and overrun errors the SCI receiver recognizes only the overrun error PE Parity Error In 11 bit Asynchronous modes PE is set when an incorrect parity bit is detected in the received character PE and RDRF are set simultaneously when the received word is transferred to the SRX If PE is set further data transfer into the SRX is not inhibited PE is cleared when the SCI status register is read followed by a read of SRX A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction also clears PE In 10 bit Asynchronous mode 11 bit multidrop mode and 8 bit Synchronous mode the PE bit is always cleared since there is no parity bit in these modes If the byte received causes both parity and overrun errors the SCI receiver recognizes only the overrun error Motorola Serial Communication Interface SCI 8 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 3 SCI Status Register SSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 4 OR 0 Overrun Error Flag Set when a byte is ready to be transferred from the receive shift reg
111. how many transmitters are enabled 0 1 2 7 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model or 3 The CRB settings also determine the ESSI operating mode Either a hardware RESET signal or a software RESET instruction clears all the bits in the CRB Table 7 2 Mode and Signal Definitions on page 7 5 summarizes the relationship between the ESSI signals SC 2 0 SCK and the CRB bits The ESSI has two serial output flag bits OF1 and OFO The normal sequence follows for setting output flags when transmitting data by transmitter 0 through the STD signal only 1 Wait for TDE TXO empty to be set 2 Write the flags 3 Write the transmit data to the TX register Bits OFO and OF1 are double buffered so that the flag states appear on the signals when the TX data is transferred to the transmit shift register The flag bit values are synchronized with the data transfer Note The timing of the optional serial output signals SC 2 0 is controlled by the frame timing and is not affected by the settings of TE2 TE1 TEO or the receive enable RE bit of the CRB The ESSI has three transmit enable bits TE 2 0 one for each data transmitter The process of transmitting data from TX1 and TX2 is the same TXO differs from these two bits in that it can also operate in Asynchronous mode The normal transmit enable seque
112. ieia Aa ES ER IRE ERE RS 8 3 8 1 3 4 Address Mode Wakeup sso e Era ECRRE RREEEEM REEF RIA RE SEXE 8 3 8 2 VO Signals o5oeirbd eeec tees eet age E a aE a Tia E EE AE ye ET ses 8 3 8 2 1 Receive Data E XD 4 Lua kaaucpewadc hzc a E ora bre dora ed ce ad esca 8 4 8 2 2 Transit Data DXDIE 25 up due Ree seed PA Sob aan Y Xo dada 8 4 8 2 3 SCI Serial Clock SCLK s 40 hahaa ek X49 RV XR REA KDE GC ese dC 8 4 8 3 SCI After ROS sesssetaeseskah ehiesrsh rerduaberd3eA a her cerad rdPe42 8 4 8 4 SC Bintirdivs i Tcr 8 6 8 4 1 Preamble Break and Data Transmission Priority 0 000 e eee ee eee 8 7 8 4 2 Bootstrap Loading Through the SCI Operating Mode 6 4 8 7 8 5 Excepting PPP beaches iaecck dedas dese A E 8 8 8 6 SCL Programming Model sso v Sdoeyy isisa ope tea es EX YES eee Sandee RE 8 9 8 6 1 SCI Control Register SCR ol ede sacr Pu ware pd e ac qoare voa ae Rae C 8 12 8 6 2 SCI Status Resister 3S Ra oves per Ser RRERRASRIUPEOCCHPMERES EETU ENTERRER 8 17 8 6 3 SCI Clock Control Register SCCR 20 0 0 ee eee 8 19 8 6 4 SCI Data Registers 24224 kee pp e be exe RE eh be b x ves eek en bea ad 8 22 8 6 4 1 SCI Receive Register iS X odiosa eras eee eeseeeede evant P to 8 23 8 6 4 2 SCI Transmit Register STX 222244 lt ccc0eieeedvekaviseeahariedeanaes 8 24 8 7 GPIO Signals and Registers iade ex pen RE REA REC E eee ee eeensees 8 25 8 7 1 Port E Control Register PCRE i esee E rer ee dee yeas RRENG PE 8 25 8 7 2
113. individually programmed as an input or output through the HDDR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated HA1 HA8 PB9 Input Input Input or Output Input Host Address Input 1 When the HIO8 is programmed to interface a nonmultiplexed host bus and the HI function is selected this signal is line 1 of the host address HA1 input bus Host Address 8 When HIO8 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 8 of the host address HA8 input bus Port B 9 When the HIO8 is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated HA2 HA9 PB10 Input Input Input or Output Input Host Address Input 2 When the HIO8 is programmed to interface a nonmultiplexed host bus and the HI function is selected this signal is line 2 of the host address HA2 input bus Host Address 9 When HIO8 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 9 of the host address HAQ input bus Port B 10 When the HIO08 is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR NOTE This signal has a weak keeper to maintain
114. input increment the counter or high pulse width measured or high pulse output on TIO 1 1 to 0 transitions on TIO input increment the counter or low pulse width measured or low pulse output on TIO Timer Reload Mode Bit 9 Timer Control Bits 4 7 TCO TC3 0 Timer operates as a free TC 3 0 TIO Clock Mode running counter 0000 GPIO Internal Timer 1 Timer is reloaded when 0001 Output Internal Timer Pulse selected condition occurs 0010 Output Internal Timer Toggle 0011 Input External Event Counter 0100 Input Internal Input Width 0101 Input Internal Input Period 0110 Input Internal Capture 0111 Output Internal Pulse Width Modulation 1000 Reserved Data Input Bit 12 1001 Output Internal Watchdog Pulse 0 Zero read on TIO pin 1010 Output Internal Watchdog Toggle 1 One read on TIO pin 1011 Resev d 1100 Reserved Data Output Bit 13 1101 Reserved 0 Zero written to TIO pin 1110 Reserved 1 One written to TIO pin 1111 Reserved Timer Enable Bit 0 Prescaled Clock Enable Bit 15 0 Timer Disabled 0 Clock source is CLK 2 or TIO 1 Timer Enabled 1 Clock source is prescaler output Direction Bit 11 0 TIO pin is input 1 TIO pin is output Timer Overflow Interrupt Enable Bit 1 0 Overflow Interrupts Disabled Timer Compare Flag Bit 21 1 Overflow inerapte Enabled 0 1 has been written to TCSR TCF or timer compare interrupt servi
115. input signal providing the serial bit rate clock for the ESSI The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes Although an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6T i e the system clock frequency must be at least three times the external ESSI clock frequency The ESSI needs at least three DSP phases inside each half of the serial clock Port D 3 The default configuration following reset is GPIO input PD3 When configured as PD3 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal SCK1 through PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SRD1 PD4 Input Output Input or Output Input Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SRD1 is an input when data is being received Port D 4 The default configuration following reset is GPIO input PD4 When configured as PD4 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal SRD1 through PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated STD1 PD5 Input Output Input or Output Input Serial Transmit Data Tr
116. it can be accessed by MOVE MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The contents of the internal X I O memory space are listed in Appendix A 3 3 Y Data Memory Space The Y data memory space consists of the following Internal Y data memory 48K by default down to 16K Internal Y I O space 16 locations FFFF80 FFFF8F External Y I O space upper 112 locations Optional off chip memory expansion as much as 128K in 16 bit mode or 256K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to the DSP56300 Family Manual for details on using the external memory interface to access external Y data memory Note The Y memory space at locations SFF0000 SFFEFFF is reserved and should not be accessed 3 3 1 Internal Y Data Memory The default on chip Y data RAM is a 24 bit wide internal static memory occupying the lowest 48K locations 0 SBFFF in Y memory space The on chip Y data RAM is organized in 48 banks 1024 locations each Available Y data memory space is reduced and reallocated to program memory by using the memory switch mode described in the following paragraphs Motorola Memory Configuration 3 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Y Data Memory Space 3 3 2 Memory Switch Modes
117. mode 7 9 5 timer operating mode setting 9 3 timer operating modes Event Counter Mode 3 9 10 Event counter mode 3 9 4 GPIO Mode 0 9 5 GPIO mode 0 9 4 Input pulse mode 5 9 5 Input width mode 4 9 5 Measurement Capture Mode 6 9 15 Measurement Input Width Mode 4 9 12 overview 9 5 Pulse Mode 1 9 7 Pulse Width Modulation PWM Mode 7 9 16 Pulse mode 1 9 4 Pulse mode 9 9 5 reserved modes 9 20 9 21 signal measurement modes 9 11 Toggle Mode 2 9 8 Toggle mode 10 9 5 Toggle mode 2 9 4 Watchdog 9 5 Watchdog modes 9 18 Watchdog Pulse 9 18 Watchdog Pulse Mode 9 9 19 Watchdog Pulse mode 9 19 Watchdog Toggle 9 18 Watchdog Toggle Mode 10 9 20 Timer Overflow exception 9 3 Timer Prescalar Count Register TPCR Prescalar Counter Value 9 24 Timer Prescaler Count Register TPCR 9 24 Timer Prescaler Count Register TPCR bit definitions 9 24 Timer Prescaler Load Register TPLR 9 23 Prescaler Preload Value 9 23 Timer Prescaler Load Register TPLR bit definitions 9 23 timer enabling 9 3 Timers 2 3 2 19 TLR register 9 29 TPCR register 9 24 TPLR register 9 23 transcoder basestation 10 1 Transmit Byte Registers 6 6 Transmit Byte Registers TXH TXM TXL 6 30 Transmit Data signal TXD 8 4 transmit data signal ESSI 7 4 Transmit Exception Interrupt Enable bit TEIE 7 20 Transmit Frame Sync Flag bit TFS 7 30 transmit interrupt enable ESSI 7 20 Transmit Shift Registers 7 31 Transmit Slot Mask Registers TSMA TSMB
118. movep 0302 X M_ SCR Configure SCI Control Reg movep C000 X M_ SCCR Configure SCI Clock Control Reg movep 7 X M_PCRE Configure SCLK TXD and RXD do 6 LOOP6 get 3 bytes for number of program words and 3 bytes for the starting address jelr 2 X M_SSR Wait for RDRF to go high movep X M SRXL A2 Put 8 bits in A2 jelr 1 X M_SSR Wait for TDRE to go high movep A2 X M STXL echo the received byte asr 8 a a _LOOP6 move al rO starting address for load move al rl save starting address do a0 LOOP7 Receive program words do 3 LOOPS jelr 2 X M_SSR Wait for RDRF to go high movep X M_SRXL A2 Put 8 bits in A2 jelr 1 X M_SSR Wait for TDRE to go high movep a2 X M STXL echo the received byte asr 8 a a Motorola Bootstrap Program A 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Code LOOPS movem al p r0 Store 24 bit result in P mem nop pipeline delay _LOOP7 bra lt FINISH Boot from SCI done This is the routine that loads from external EPROM MD MC MB MA 1001 EPROMLD move BOOT r2 12 address of external EPROM movep AARV X M_AARI aarl configured for SRAM types of access do 6 LOOP9 read number of words and starting address movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into Al _LOOP9 i move al rO starting address for load move al rl saveitinrl a0 holds the n
119. offset size of three For details refer to Motorola application note APR23 D Using the DSP56300 Direct Memory Access Controller 3 To prevent improper operation DMA address 1 and DMA address 2 should not cross the AAR bank borders 4 Arbitration is not allowed during the packing access i e the three accesses are treated as one access with respect to arbitration and the bus mastership is not released during these accesses Reserved Set to 0 for future compatibility BYEN Bus Y Data Memory Enable A read write control bit that enables disables the AA pin and logic during external Y data space accesses When set BYEN enables the comparison of the external address to the BAC bits during external Y data space accesses If BYEN is cleared no address comparison is performed BXEN Bus X Data Memory Enable A read write control bit that enables disables the AA pin and logic during external X data space accesses When set BXEN enables the comparison of the external address to the BAC bits during external X data space accesses If BXEN is cleared no address comparison is performed BPEN Bus Program Memory Enable A read write control bit that enables disables the AA RAS pin and logic during external program space accesses When set BPEN enables the comparison of the external address to the BAC bits during external program space accesses If BPEN is cleared no address comparison is performed BAAP
120. register 6 22 HSR register 6 15 HTX register 6 21 I O space external Y data Memory 3 7 X data Memory 3 5 Y data Memory 3 7 ICR Double Host Request bit 6 9 ICR register 6 24 Idle Line Interrupt Enable bit ILIE 8 13 Idle Line Wakeup mode 8 3 IFO bit 7 31 IIR filter 10 1 10 2 scaling 10 2 ILIE bit 8 13 Indicate state of HF3 in HCR on DSP side 6 28 Infinite Impulse Response filter 10 1 INIT bit 6 25 initialization EFCOP 10 2 Initialize bit INIT 6 25 initializing the timer 9 2 9 3 Instruction Cache 3 3 instruction cache 3 1 instruction set 1 5 Interface Control Register ICR 6 24 Interface Status Register ISR 6 28 Index 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interface Vector Register IVR 6 30 internal buses 1 10 internal program memory 3 1 internal Y data Memory 3 5 Internal Y I O space 3 7 interrupt 1 8 ESSI 7 8 HIOS8 6 7 priority levels 4 7 sources 4 4 4 5 interrupt and mode control 2 9 interrupt conditions 5 2 interrupt control 2 9 interrupt DSP after last slot in frame ends regardless of receive mask register setting 7 20 interrupt handler forcing execution 6 8 Interrupt Priority Levels 4 7 Interrupt Priority Register P IPR P 4 7 interrupt routines HIO8 6 8 interrupt service routine 7 9 interrupt service routine ISR 9 4 Interrupt Source Priorities 4 8 Interrupt Sources 4 5 interrupt t
121. s Manual iv For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 5 Programming the Peripherals 5 1 Peripheral Initialization Steps 2 lt 0s 2cseeeSee RR REI REEF REPARARE RR 5 1 5 2 Mapping the Control Registers susuusuuan rh RR eg 5 2 5 3 Reading Status RESIS iex ere PERIERE RO S cer eti PEE NERINE ELE EER ERE 5 2 5 4 Data Transfer Methods scscsrerosare istened Xue x E ae eee E A aoe 5 3 5 4 1 PONE 4 aquas nea aa hae AO EE A EH CER GEH OUO GOR OG Sk ee 5 3 5 4 2 inre 26 64424 cneeint a tesa deeb een eae ds Awe eae eae 5 3 5 4 3 DMA cee eee ee ee ee ee ee ee ee ee ee eee ee eee ee ee ee 5 5 5 4 4 Advantages and Disadvantages 2 2 4222222 b e Re E RE EROR saees vee xs 5 6 2i General Purpose Input Output GPIO 0 0 cee eee eA 5 6 5 5 1 Port B Signals and Registers 2 2 2 ccs cceeeee eee ee ar ah Rx ean 5 6 5 5 2 Port C Signals and Registers 225 alsocEs ha ERR aeaea 5 7 5 5 3 Port D Signals and Registers i 24c4 px S EP ER REIX VE ux PR Rx RE 5 8 5 5 4 Port E Signals and Registers 2er Des berbee a her REexwkh r ecura der ead 5 8 5 5 5 Triple Timer Signals and Register 2 22 22 exa Re ews sa oheeeneeeddew bes 5 9 Chapter 6 Host Interface H108 6 1 p uu MP 6 1 6 1 1 DSP Core IMerfdee i4 soe racar Deu RPRAdeUxEESPRP SERES AP E D qa 6 1 6 1 2 Host Processor IMerI 368 5 ooa x ox pr a unc du Re VAR genase weeg uate 6 2 6 2 Host Port Signals 5 koe be
122. select one of the following options MSW 1 0 00 The 32K higher locations 4000 BFFF of the internal X data memory and the 32K higher locations 6000 BFFF of the internal Y data memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 96K locations 0 17FFF in the program memory space The instruction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 MSWTL I1 0 01 The 24K higher locations 6000 BFFF of the internal X data memory and the 24K higher locations 6000 BFFF of the internal Y data memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 80K locations 0 13FFF in the program memory space The instruction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations 14000 17FFF are considered reserved and should not be accessed MSWTL I1 0 10 The 16K higher locations 8000 BFFF of the internal X data memory and the 16K higher locations 8000 BFFF of the internal Y data memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 64K locations 0 FFFF in the program memory space The in
123. specify SR as a destination e g MOVEC During hardware reset all EMR bits are cleared The MR register bits are affected by DO instructions and instructions that directly reference the MR e g ANDI ORI or instructions such as MOVEC that specify SR as the destination During processor reset the interrupt mask bits are set and all other bits are cleared m Condition Code Register CCR SR 7 0 Defines the results of previous arithmetic computations The CCR bits are affected by Data Arithmetic Logic Unit Data ALU operations parallel move operations instructions that directly reference the CCR ORI and ANDI and instructions that specify SR as a destination e g MOVEC Parallel move operations affect only the S and L bits of the CCR During processor reset all CCR bits are cleared The definition of the three 8 bit registers within the SR is primarily for the purpose of compatibility with other Motorola DSPs Bit definitions in the following paragraphs identify the bits within the SR and not within the subregister Motorola Core Configuration 4 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Status Register SR Extended Mode Register EMR Mode Register MR Condition Code Register CCR 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 CP1 0 RM SM CE SA FV LF DM SC S1 0 11 0 S L EJU N Z V C
124. sync selection ESSI 7 11 frame sync signal 7 7 7 10 frame sync signal format ESSI 7 11 frame synchronization signals ESSI 7 18 frequency operation 1 5 functional groups 2 3 G Global Data Bus 1 10 GPIO 1 12 2 3 Timers 2 3 GPIO ESSIO Port C 5 7 GPIO ESSII Port D 5 8 GPIO HI08 Port B 5 6 GPIO SCI Port E 5 8 GPIO Timer 5 9 GPIO functionality on ESSI 7 36 GPIO functions 6 4 Motorola DSP56311 User s Manual GPIO Port Direction Register PRR 7 23 Ground 2 4 PLL 2 4 H HASEN bit 6 20 HAQEN bit 6 20 handshaking mechanisms HI08 6 6 hardware stack 1 8 HASP bit 6 19 CVR 6 15 HI08 HSR Reflect status of the CVR 6 15 HCSEN bit 6 20 HCSP bit 6 18 HDDR 6 4 HDDS bit 6 18 HDR and HDDR Functionality 6 16 HDR register 6 16 HDRQ bit 6 25 HDSP bit 6 19 HEN bit 6 19 HI08 1 12 2 3 2 11 2 12 2 13 2 14 5 2 6 1 GPIO 5 6 cause the chip to execute an interrupt 6 27 CAUTION 6 29 Chip Select logic 6 17 Command Vector Register CVR 6 8 configuring for host requests 6 9 control HI08 operating mode 6 17 control host request signals 6 20 control HREQ signal for host receive data transfers 6 26 control output drive of host request signals 6 19 control polarity of host request signals 6 18 control register ICR 6 23 controls direction of data flow for each HIO8 signal configured as GPIO 6 16 core communication with HIOS registers 6 13 core interrupts host command 6 8 receive data register full 6 8 transmi
125. that TCPR gt TLR for correct functionality TCPR DXM if TCIE 1 TCF Compare Interrupt TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width S ndi Period NOTE On overflow TCR is loaded with the value of TLR Figure 9 17 Pulse Width Modulation Toggle Mode TRM 0 9 3 4 Watchdog Modes The following watchdog timer modes are provided m Watchdog Pulse m Watchdog Toggle 9 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 4 1 Watchdog Pulse Mode 9 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 1 0 0 1 9 Pulse Watchdog Output Internal In Mode 9 the timer generates an external signal at a preset rate The signal period is equal to the period of one timer clock After the counter reaches the value in the TCPR if the TCSR TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count resumes Therefore TRM 1 is not useful for watchdog functions If the TCSR TRM bit is cleared the counter continues to increment on each subsequent timer clock This process repeats until the timer is disabled that is TCSR TE is cleared If the counter overflows a pulse is output on the TIO signal with a pulse width equal to the timer clock period I
126. that the transmit byte registers TXH TXM TXL are empty and can be written by the host processor TXDE is set when the contents of the transmit byte registers are transferred to the HRX register TXDE is cleared when the transmit register TXL or TXH according to HLEND bit is written by the host processor The host processor can set TXDE using the initialize function TXDE can assert the external HTRQ signal if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE indicates whether the TX registers are full and data can be latched in so that polling techniques may be used by the host processor Hardware software individual and stop resets all set TXDE RXDF Receive Data Register Full Indicates that the receive byte registers RXH RXM RXL contain data from the DSP56311 to be read by the host processor RXDF is set when the HTX is transferred to the receive byte registers RXDF is cleared when the host processor reads the receive data register RXL or RXH according to HLEND bit The host processor can clear RXDF using the initialize function RXDF can assert the external HREQ signal if the RREQ bit is set Regardless of whether the RXDF interrupt is enabled RXDF indicates whether the RX registers are full and data can be latched out so that the host processor can use polling techniques Motorola Host Interface H108 6 29 For More Information On This Product Go to www freescale com
127. the HCR 2 HCIE bit is set on the DSP side The host then uses the Command Vector Register CVR to start an interrupt routine The host sets the Host Command bit CVR 7 HC to request the command interrupt and the seven Host Vector bits CVR 6 0 JZHV6 HVO to select the interrupt address to be used When 6 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation the DSP core recognizes the host command interrupt the address of the interrupt taken is 2xHV For host command interrupts the interrupt acknowledge from the DSP56311 program controller clears the pending interrupt condition Note When the DSP enters Stop mode the HIOS8 pins are electrically disconnected internally thus disabling the HIOS until the core leaves Stop mode Do not issue a STOP command via the HIOS8 unless some other mechanism for exiting this mode is provided 6 4 3 Core DMA Access The DSP56300 family Direct Memory Access DMA controller permits transfers between internal or external memory and I O without any core intervention A DMA channel can be set up to transfer data to from the HTX and HRX data registers freeing the core to use its processing power on functions other than polling or interrupt routines for the HI08 DMA may well be the best method to use for data transfers but it requires that one of the six DMA channels be available for use Two HIO8 DMA sources are poss
128. the current bus master to reuse the bus without rearbitration until another device requires the bus The deassertion of BB is done by an active pull up method i e BB is driven high and then released and held high by an external pull up resistor The default operation of this bit requires a setup and hold time as specified in the DSP56311 Technical Data sheet An alternate mode can be invoked set the ABE bit Bit 13 in the OMR When this bit is set BG and BB are synchronized internally See BG for additional information NOTE BB requires an external pull up resistor CAS Output Tri stated Column Address Strobe When the DSP is the bus master CAS is an active low output used by DRAM to strobe the column address Otherwise if the bus mastership enable BME bit in the DRAM control register is cleared the signal is tri stated 2 6 Interrupt and Mode Control The interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is deasserted these inputs are hardware interrupt request lines Motorola Signals Connections 2 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt and Mode Control Table 2 9 Interrupt and Mode Control State During Reset Signal Description Signal Name Type RESET Input Input Reset An active low Schmitt trigger input Deassertion of RESET is internally syn
129. the timer is enabled the TIO signal is loaded with the value of the TCSR INV bit When the counter value matches the value in the TCPR the polarity of the TIO output signal is inverted TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count resumes If the TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is cleared disabling the timer The TCPR TLR value sets the delay between starting the timer and toggling the TIO signal To generate output signals with a delay of X clock cycles between toggles set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled that is TCSR TE is cleared 9 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Mode 2 internal clock TRM 1 N write preload first event M write compare TE Clock M M CLK 2 or prescale CLK TLR XK N Counter TCR 0 N N 1 M N TCPR lt M TCF Compare Interrupt if TCIE 1 q TIO pin INV 0 pulse width M N clock TIO pin INV 1 perioas Figure 9 7 Toggle Mode TRM 1 Mode 2 internal clock TRM 0
130. to allow the DSP and host processor to transfer data efficiently at high speed Direct memory mapping allows the DSP56311 core to communicate with the HIOS registers using standard instructions and addressing modes In addition the MOVEP instruction allows direct data transfers between DSP56311 internal memory and the HIOS registers or vice versa There are two types of host processor registers data and control with eight registers in all The DSP core can access all eight registers but the external host cannot The following data registers are 24 bit registers used for high speed data transfer to and from the DSP m Host data receive register HRX on page 6 22 m Host data transmit register HTX on page 6 21 The DSP side control registers are 16 bit registers that control HI08 functionality Host control register HCR on page 6 14 Host status register HSR on page 6 15 Host GPIO data direction register HDDR on page 6 16 Host GPIO data register HDR on page 6 16 Host base address register HBAR on page 6 17 m Host port control register HPCR on page 6 17 Both hardware and software resets disable the HIOS8 After a reset the HIOS signals are configured as GPIO and disconnected from the DSP56300 core that is the signals are left floating Motorola Host Interface H108 6 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model 6 6 1 Host Con
131. to the most positive number 7FFF if overflow occurred or the most negative number 8000 if underflow occurred after processing of all filter taps is completed In saturation mode the result is limited to the most positive number 7FFF if overflow occurred or the most negative number 8000 if underflow occurred after every MAC operation The 16 bit result from the FMAC is stored in the EFCOP output buffer FDOR 10 3 EFCOP Programming Model This section documents the registers for configuring and operating the EFCOP The EFCOP registers available to the DSP programmer are listed in Table 10 2 The following paragraphs describe these registers in detail Table 10 2 EFCOP Registers and Base Addresses Address EFCOP Register Name Y FFFFBO Filter data input register FDIR Y FFFFB1 Filter data output register FDOR Y FFFFB2 Filter K constant register FKIR Y FFFFB3 Filter count register FCNT Y FFFFB4 Filter control status register FCSR Y FFFFB5 Filter ALU control register FACR Y FFFFB6 Filter data buffer base address FDBA Motorola DSP56311 User s Manual 10 6 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model Table 10 2 EFCOP Registers and Base Addresses Continued Address EFCOP Register Name Y FFFFB7 Filter coefficient base address FCBA Y FFFFB8 Filter decimation channel re
132. transfer of 7 4 28 items input sequence length DSRO Address of source data DMA Source Address Register 0 DDRO FFFFBO DMA Destination Address Register for Channel 0 Motorola Enhanced Filter Coprocessor EFCOP For More Information On This Product Go to www freescale com 10 23 Freescale Semiconductor Inc Examples of Use in Different Modes m DMA output Channel 1 is used with a configuration similar to that of the DMA input channel except for a 1D transfer The DMA output control registers are initialized as shown in Table 10 11 Table 10 11 DMA Channel 1 Register Initialization Register Setting Description DCR1 bit values are as follows DMA Control Register 1 DIE 0 Disables end of transfer interrupt DTM 1 Chooses word transfer triggered by request DE auto clear on end of transfer DPR 3 Priority 3 DCON 0 Disables continuous mode DRS 16 Chooses DMA to trigger on EFCOP output buffer full D3D 0 Chooses non 3D mode DAM 2C Sets the following DMA address mode B6 source address no update no offset E destination address 1D post increment by 1 no offset DDS 0 Destination in X memory space DSS 1 Source in Y memory space because EFCOP is in Y memory DCO1 12 DMA Counter Register 1 Gives transfer of 9 items DSR1 address of FDOR DMA Source Address Register 1 FFFFFB1 DDR1 address of destination DMA Destination Address Re
133. transmit data register during the time slot when TFS is set is transmitted in Network mode during the second time slot in the frame TFS is useful in Network mode to identify the start of a frame TFS is valid only if at least one transmitter is enabled that is when TEO TE1 or TE2 is set NOTE In Normal mode TFS is always read as 1 when data is being transmitted because there is only one time slot per frame the frame sync time slot 1 IF1 0 Serial Input Flag 1 The ESSI latches any data on the SC1 signal during reception of the first received bit after the frame sync is detected IF1 is updated with this data when the data in the receive shift register transfers into the receive data register IF1 is enabled only when SC1 is an input flag and Synchronous mode is selected that is when SC1 is programmed as ESSI in the port control register PCR the SYN bit is set and the TE2 and SCD1 bits are cleared If it is not enabled IF1 is cleared 0 IFO 0 Serial Input Flag 0 The ESSI latches any data on the SCO signal during reception of the first received bit after the frame sync is detected The IFO bit is updated with this data when the data in the receive shift register transfers into the receive data register IFO is enabled only when SCO is an input flag and the Synchronous mode is selected that is when SCO is programmed as ESSI in the port control register PCR the SYN bit is set and the TE1 and SCDO bits are cleared If
134. update multiplier FKIR is accessible only to the DSP core for reads or writes When adaptive mode is enabled the EFCOP immediately starts the coefficient update if a K Constant value is written to FKIR If no value is written to FKIR for the current data sample the EFCOP halts processing until the K Constant is written to FKIR After the weight update multiplier is written to FKIR the EFCOP transfers it to the FMAC unit and starts updating the filter coefficients according to the following equation New coefficients Old coefficients FKIR Input buffer 10 3 4 Filter Count FCNT Register The FCNT register is a read write register that selects the filter length number of filter taps Always write the initial count into the FCNT register before you enable the EFCOP Motorola Enhanced Filter Coprocessor EFCOP 10 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model that is before you set FEN The number stored in FCNT is used to generate the correct addressing for the FDM and for the FCM Note To ensure correct operation never change the contents of the FCNT register unless the EFCOP is in the individual reset state that is FEN 0 In the individual reset state that is FEN 0 the EFCOP module is inactive but the contents of the FCNT register are preserved
135. wide DSP56311 word 4 2 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Table 4 1 Freescale Semiconductor Inc Operating Modes DSP56311 Operating Modes Continued Mode MODD MODC MODB MODA Reset Vector Description FF0000 Bootstrap through SCI Instructions are loaded through the SCI The bootstrap program sets the SCI to operate in 10 bit asynchronous mode with 1 start bit 8 data bits 1 stop bit and no parity Data is received in this order start bit 8 data bits LSB first and one stop bit Data is aligned in the SCI receive data register with the LSB of the least significant byte of the received data appearing at Bit 0 The user must provide an external clock source with a frequency at least 16 times the transmission data rate Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter The boot program concatenates every 3 bytes read from the SCI into a 24 bit wide DSP56311 word FF0000 Reserved FF0000 HI08 bootstrap in ISA DSP563xx mode The HIO8 is configured to interface with an ISA bus or with the memory expansion port of a master DSP563xx processor through the HI08 The HI08 pin configuration is optimized for connection to the ISA bus or memory expansion port of a master DSP based on the DSP56300 core FF0000 HIO8 bootstrap in HC11 nonmultiplexed mode The b
136. written by the DSP core HTDE is set when the HTX register is transferred to the RXH RXM RXL registers The host processor can also set HTDE using the initialize function HTDE is cleared when the DSP core writes to HTX Motorola Host Interface H108 6 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model Table 6 8 Host Status Register HSR Bit Definitions Bit Number Bit Name Reset Value Description 0 HRDF 0 Host Receive Data Full Indicates that the host receive data register HRX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the HRX register The host processor can also clear HRDF using the initialize function 6 6 3 Host Data Direction Register HDDR The HDDR controls the direction of the data flow for each of the HI08 signals configured as GPIO Even when the HI08 functions as the host interface its unused signals can be configured as GPIO signals For information on the HI08 GPIO configuration options see Section 6 2 Host Port Signals on page 6 3 If Bit DRxx is set the corresponding HI08 signal is configured as an output signal If Bit DRxx is cleared the corresponding HIOS signal is configured as an input signal Hardware and software reset clear the HDDR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR15 DR14 DR13 DR12 DR11 DR10 DR
137. www freescale com Freescale Semiconductor Inc Frame Rate Divider Control 7 16 Prescale Modulus Select 7 17 Prescaler Range 7 16 Select SC1 7 15 Word Length Control 7 15 Control Register A CRA bit definitions 7 14 Control Register B 7 18 Control Register B CRB Clock Polarity 7 22 Clock Source Direction 7 23 Frame Sync Length 7 23 Frame Sync Polarity 7 22 Frame Sync Relative Timing 7 23 Mode Select 7 22 Receive Enable 7 21 Receive Exception Interrupt Enable 7 19 Receive Interrupt Enable 7 20 Receive Last Slot Interrupt Enable 7 20 Serial Control Direction 0 7 24 Serial Control Direction 1 7 24 Serial Control Direction 2 7 23 Serial Output Flag 0 7 24 Serial Output Flag 1 7 24 Shift Direction 7 23 Synchronous Asynchronous 7 22 Transmit 0 Enable 7 21 Transmit 1 Enable 7 21 Transmit 2 Enable 7 22 Transmit Exception Interrupt Enable 7 20 Transmit Interrupt Enable 7 20 Transmit Last Slot Interrupt Enable 7 20 Control Register B bit definitions 7 19 control whether the receive and transmit functions occur synchronously or asynchronously with respect to each other 7 22 control which bit clock edge data and frame sync are clocked out and latched i 7 22 CRA and CRB 7 10 data and control signals 7 3 determine polarity of the receive and transmit frame sync signals 7 22 determine relative timing of the receive and transmit frame sync signal 7 23 determine shift direction of the transmit or receive shift register 7 23 DMA services t
138. www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model 9 4 2 Timer Prescalar Load Register TPLR The TPLR is a read write register that controls the prescalar divide factor 1 e the number that the prescalar counter loads and begins counting from and the source for the prescalar input clock 23 22 21 20 19 18 17 16 15 14 13 12 PS1 PSO PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 11 10 9 8 7 6 5 4 3 2 1 0 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO I Reserved bit Read as 0 Write with O for future compatibility Figure 9 21 Timer Prescalar Load Register TPLR Table 9 1 Timer Prescalar Load Register TPLR Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to zero for future compatibility 22 21 PS 1 0 0 Prescalar Source Control the source of the prescalar clock The prescalar s use of a TIO signal is not affected by the TCSR settings of the timer of the corresponding TIO signal If the prescalar source clock is external the prescalar counter is incremented by signal transitions on the TIO signal The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56311 internal operating frequency divided by 4 that is CLK 4 NOTE To ensure proper operation c
139. x M DCR1 DMA1 source is transmit buffer DMA1 destination is HTX DMA1 count is the full buffer init DMA1 control register Ne Ne Ne Ne Motorola Programming the Peripherals 5 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Purpose Input Output GPIO DMA requires more initialization code and consideration of DMA modes However it is the most efficient use of core resources Once these registers are programmed the user must enable the DMA by triggering a DMA request off one of the peripheral control flags or enabling it in normal program flow or an interrupt service routine 5 4 4 Advantages and Disadvantages Polling is the easiest method to implement but it requires a large amount of DSP56311 core processing power The core cannot be involved in other processing activities while it is polling receive and transmit ready bits Interrupts require more code but the core can process other routines while waiting for data I O An interrupt is generated when data is ready to be transferred to or from the peripheral device DMA requires even less core intervention and the setup code is minimal but the DMA channels must be available Note Do not interrupt requests and DMA requests simultaneously 5 5 General Purpose Input Output GPIO The DSP56311 provides 34 bidirectional signals that can be configured as GPIO signals or as perip
140. 011 is reserved 22522523252322222222222222222222225222522222225222222222222222522252522522522222225 If MD MC MB MA 1100 then the program RAM 1s loaded from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words are stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address 3252252322523222222222222222223222225222522222225222222222222222522252522522522222225 If MD MC MB MA 1101 then the program RAM is loaded from the Host Interface programmed to operate in the HC11 non multiplexed mode The HOST HC11 bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words 1s stored in contiguous PRAM memory locations starting at the specified starting address After the program words are
141. 1 Sample Code Listing BFSET S0007 X PCC Configure line 1 MISOO MOSIO SCKO for SPI master line 2 SSO as PC3 for GPIO line 3 Hex values are indicated with a dollar sign preceding the hex value as follows FFFFFF is the X memory address for the core interrupt priority register Motorola Overview 1 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Features m The word reset is used in four different contexts in this manual the reset signal written as RESET the reset instruction written as RESET the reset operating state written as Reset the reset function written as reset 1 3 Features The Motorola DSP56311 a member of the DSP56300 core family of programmable DSPs supports wireless infrastructure applications with general filtering operations The on chip EFCOP processes filter algorithms in parallel with core operation thus increasing overall DSP performance and efficiency Like the other family members the DSP56311 uses a high performance single clock cycle per instruction engine code compatible with Motorola s popular DSP56000 core family a barrel shifter 24 bit addressing instruction cache and DMA controller The DSP56311 offers 150 million instructions per second MIPS performance 255 MIPS using the EFCOP in filtering applications using an internal 150 MHz clock with 1 8 V core and independent 3 3 V input output I O po
142. 1 TCO Mode Name Function TIO Clock 1 0 1 0 10 Toggle Watchdog Output Internal In Mode 10 the timer toggles an external signal after a preset period The TIO signal is set to the value of the INV bit When the counter equals the value in the TCPR TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is also set If the TCSR TRM bit is set the counter loads with the TLR value on the next timer clock and the count resumes Therefore TRM 1 is not useful for watchdog functions If the TCSR TRM bit is cleared the counter continues to increment on each subsequent timer clock When a counter overflow occurs the polarity of the TIO output signal is inverted The counter is reloaded whenever the TLR is written with a new value while the TCSR TE bit is set This process repeats until the timer is disabled In Mode 10 internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the hardware RESET signal is asserted This convention ensures that a valid reset signal is generated when the TIO signal resets the DSP56311 Mode 10 internal clock TRM 0 N write preload M write compare f TRM 1 is not useful for watchdog function first event TE crock _ LL FL I LA CLK 2 or prescale CLK TLR N Counter 0 N 10x M 1 9 N 1 TCPR M TCF Compare Interrupt if TCIE 1 T
143. 11 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Interrupt Sources and Priorities Table 4 4 Interrupt Source Priorities Within an IPL Continued Priority Interrupt Source DMA channel 5 interrupt Highest Host command interrupt Host transmit data empty Host receive data full ESSIO RX data with exception interrupt ESSIO RX data interrupt ESSIO receive last slot interrupt ESSIO TX data with exception interrupt ESSIO transmit last slot interrupt ESSIO TX data interrupt ESSH RX data with exception interrupt ESSH RX data interrupt ESSI receive last slot interrupt ESSH TX data with exception interrupt ESSI1 transmit last slot interrupt ESSH TX data interrupt SCI receive data with exception interrupt SCI receive data SCI transmit data SCI idle line SCI timer TIMERO overflow interrupt TIMERO compare interrupt TIMER 1 overflow interrupt TIMER1 compare interrupt TIMER overflow interrupt TIMER2 compare interrupt EFCOP data input buffer empty Lowest EFCOP data output buffer full Motorola Core Configuration 4 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Sources and Priorities 4 3 4 DMA Request Sources The DMA request source bits DRS
144. 18 CRB FSLO and FSL1 Bit Operation FSR 0 0000 5 7 25 CRB SYN Bit Operation 2s sd edo ur a Rr REESE ESSERE RP ER PES a4 7 26 CRB MOD Bit Operation 5 uxeeice ace ende ac er e pur exa e Rx 7 27 Normal Mode External Frame Sync 8 Bit 1 Word in Frame 7 28 Network Mode External Frame Sync 8 Bit 2 Words in Frame 7 28 ESSI Status Register SSISR sueee eee Res 7 29 ESSI Data Path Programming Model SHFD 20 lusus 7 32 ESSI Data Path Programming Model SHFD 1 Lesser 7 33 ESSI Transmit Slot Mask Register A TSMA 00000 7 34 ESSI Transmit Slot Mask Register B TSMB 00 7 35 ESSI Receive Slot Mask Register A RSMA 0 000 000 000 7 35 ESSI Receive Slot Mask Register B RSMB 00 000 7 36 DSP56311 User s Manual xii For More Information On This Product Go to www freescale com Figure 7 18 Figure 7 19 Figure 7 20 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 9 11 Figure 9 12 Figure 9 13 Figure 9 14 Figure 9 15 Figure 9 16 Figure 9 17 Figure 9 18 Figure 9 19 Figure 9 20 Figure 9 21 Motorola Freescale Semiconductor Inc Figures Port Contr
145. 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Equates M MA EQUO Operating Mode A M MB EQUI Operating Mode B M MC EQU2 Operating Mode C M MD EQU3 Operating Mode D M EBD EQU 4 External Bus Disable bit in OMR MSD EQU 6 Stop Delay MMS EQU 7 Memory Switch bit in OMR M CDPO EQU 8 bit O of priority bits in OMR M CDP EQU 9 bit 1 of priority bits in OMR M BEN EQU 10 Burst Enable M TAS EQU ll TA Synchronize Select M_BRT EQU 12 Bus Release Timing M ATE EQU 15 Address Tracing Enable bit in OMR M XYS EQU 16 Stack Extension space select bit in OMR M EUN EQU 17 Extended stack UNderflow flag in OMR M EOV EQU 18 Extended stack O Verflow flag in OMR M WRP EQU 19 Extended WRaP flag in OMR M SEN EQU 20 Stack Extension Enable bit in OMR A 3 Interrupt Equates ELLLLLLLLLLLLLLLLLELLLLLLLLLLLLLELLLLLLLLLLLILLLLLLLLLLLLLLILLLLILLLLLLLLLILLLLLI 2 EQUATES for 56311 interrupts gt Last update February 20 1999 2 BIG SI GIO ICIOI ICI SI I IOI ICI OI ICI II I 1 3 3 E 21 3 3 21 21 321 3 3 E 2128 21 1 5 28 21 E E 1 29 E 2 25 2 EE EE E 2 EE E E a ICO OF oR a oR a a aa gt page 132 55 0 0 0 opt mex intequ ident 1 0 if DEF L_VEC leave user definition as is else I VEC EQU 0 endif I RESET EQU I VEC 00 Hardware RESET I STACK EQU I VEC 02 Stack Error I ILL EQU I VEC 04 Illegal Instruction I DBG EQU I V
146. 1d 44 4434 n ejeis YBIH UI PIPH Uld L00 Y29019 91949 inq 0S 0 L 000 a09 eigesiq 1ndino 49019 JIN 1019843 uoneordnin 0AN LLAN LLAN OJIN Sig 101284 uoneordninig pe geuj peiqeu4 e qeu OIqesi ZHMO0O0Z gt bei e1x jeueix3 ET Mise ZHM002 lt b 14 e1x jeujeix3 0 Jojejioso Tid 471X Hg eBuey esM dois Suung uonejedo 3d lsd diysuonejay N3d pue dLSd eoJnog euJe x3 uy ui044 ueAuq IVIX37 L JoiejIoSO 1v LX eiqeua 0 GLX 18 ejgesiq 1v Lx 7 7 d Phase Lock Loop Control Register PCTL Figure B 8 Programming Reference B 19 For More Information On This Product Motorola Go to www freescale com Freescale Semiconductor Inc Programming Sheets Host Receive Data usually Read by program _ _ _ _ e xnX S Oss 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 44 3 2 1 0 Er pes TIE IE eiu LEE Host Receive Data Register HRX X FFEC6 Read Only Reset empty Host Transmit Data usually Loaded by program a a ee ee A EE Ce 23 22 21 20419 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ESI GET EEITSETTETTg TI Host Transmit Data Register HTX X FFEC7 Write Only Reset empty Figure B 9 Host Receive and Host Transmit Data Registers B 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc
147. 2 Host Processor Interface 6 2 Sixteen signals support nonmultiplexed or multiplexed buses H0 H7 HADO HAD host data bus H0 H7 or host multiplexed address data bus HADO HAD7 HAS HAO address strobe HAS or host address line HAO HAS HAI host address line HAS or host address line HA1 HA9 HA2 host address line HA9 or host address line HA2 HRW HRD read write select HRW or read strobe HRD HDS HWR data strobe HDS or write strobe HWR HCS HA10 host chip select HCS or host address line HA10 HREQ HTRQ host request HREQ or host transmit request HTRQ HACK HRRQ host acknowledge HACK or host receive request HRRQ Mapping HIOS8 registers are mapped into eight consecutive locations in the host s external bus address space The HIOS8 acts as a memory or I O mapped peripheral for microprocessors microcontrollers etc Transfer modes Mixed 8 bit 16 bit and 24 bit data transfers DSP to host Host to DSP Host command Handshaking protocols Software polled Interrupt driven Interrupts are compatible with most processors including the MC68000 8051 HC11 and Hitachi H8 m Data word 8 bits m Dedicated interrupts Separate request lines for each interrupt source Special host commands force DSP core interrupts under host processor control These commands are useful for Real time production diagnostics DSP5
148. 29 TS28 11 10 9 8 7 6 5 4 3 2 1 0 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 ESSIO X FFFFB3 ESSI1 X FFFFA3 Figure 7 15 ESSI Transmit Slot Mask Register B TSMB TSMA and TSMB as in Figure 7 12 and Figure 7 13 can be seen as a single 32 bit register TSM Bit n in TSM TSn is an enable disable control bit for transmission in slot number N When TSn is cleared all the data signals of the enabled transmitters are tri stated during transmit time slot number N The data still transfers from the enabled transmit data register s to the transmit shift register However the TDE and the TUE flags are not set Consequently during a disabled slot no transmitter empty interrupt is generated The DSP is interrupted only for enabled slots Data written to the transmit data register when the transmitter empty interrupt request is serviced transmits in the next enabled transmit time slot When TSn is set the transmit sequence proceeds normally Data transfers from the TX register to the shift register during slot number N and the TDE flag is set The TSM slot mask does not conflict with the TSR Even if a slot is enabled in the TSM you can chose to write to the TSR to tri state the signals of the enabled transmitters during the next transmission slot Setting the bits in the TSM affects the next frame transmission The frame being transmitted is not
149. 3 6 EFCOP ALU Control Register FACR The FACR is a read write register by which the DSP56300 core controls the main operation modes of the EFCOP ALU 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FISL FSA FSM FRM1 FRMO FSCL1 FSCLO Reserved bit read as 0 should be written with 0 for future compatibility Reserved for internal use read as 0 should be written with O for proper use Figure 10 5 EFCOP ALU Control Register FACR Motorola Enhanced Filter Coprocessor EFCOP 10 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model Table 10 5 EFCOP ALU Control Register FACR Bits Bit Bit Reset Description Number Name Value P 23 16 0 Reserved They are read as 0 and should be written with 0 for future compatibility 15 12 0 Reserved for internal use Written as 0 for proper operation 11 7 0 Reserved and unused They are read as 0 and should be written with O for future compatibility 6 FISL 0 Filter Input Scale When set this read write control bit directs the EFCOP ALU to scale the IIR feedback terms but not the IIR input When cleared the EFCOP ALU scales both the IIR feedback terms and the IIR input The scaling value in both cases is determined by the FSCL 1 0 bits 5 FSA 0 Filter Sixteen bit A
150. 4 Port D Signals 5 5 4 Port E Signals and Registers Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port E Port E control register PCRE Port E direction register PRRE and Port E data register PDRE Chapter 8 Serial Communication Interface SCI discusses these registers DSP56311 Port E GPIO RXD PEO Serial TXD PE1 Communications A Interface SCI Port SCLK PE2 Figure 5 5 Port E Signals Motorola DSP56311 User s Manual 5 8 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Purpose Input Output GPIO 5 5 5 Triple Timer Signals and Registers Each of the three triple timer interface signals TIOO TIO2 not used as a timer signal can be configured as a GPIO signal Each signal is controlled by the appropriate timer control status register TCSRO TCSR2 Chapter 9 Triple Timer Module discusses these registers DSP56311 TIOO TIMERS TIO1 TIO2 Figure 5 6 Triple Timer Signals Motorola Programming the Peripherals Timer GPIO TIOO TIO1 TIO2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Purpose Input Output GPIO Motorola DSP56311 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 6 Host Interface HI08 The host interface
151. 4 HLEND HF1 HFO HDRQ TREQ RREQ Interrupt Control Register ICR 0 X Reset 0 Receive Data Register Full 0 Wait 1 Read Transmit Data Register Empty 0 Wait 1 Write Transmitter Ready 0 Datain HI 1 Data Not in HI Host Flags Read Only DMA Status 0 3 DMA Disabled 1 DMA Enabled Host Request 0 3 HREQ Deasserted 1 HREQ Asserted A 5 4 3 2 1 0 HREQ DMA HF3 HF2 TRDY TXDE RXDF Interrupt Status Register ISR Per a re 2 Read Write x Reserved Program as 0 Figure B 12 Interrupt Control and Interrupt Status Registers Motorola Programming Reference B 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Reset 0F 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IVA IV3 IV2 IV1 IVO Interrupt Vector Register IVR Contains the interruptvectoror number Host Vector Contains Host Command Interrupt Address 2 Host Command Handshakes Executing Host Command Interrupts Reset 2A qe 7 6 5 4 3 2 1 0 HC7 HC6 HC5 HC4 HC3 HC2 HC1 HCO Command Vector Register CVR Contains the host command interrupt addressr Figure B 13 Interrupt Vector and Command Vector Registers B 24 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Processor Side Host Receive Data usually Read by progra
152. 4004044440644034 404459004 10 6 10 3 1 Filter Data Input Register FDIR 0 0 00 eee eee 10 7 10 3 2 Filter Data Output Register FDOR 0 0 eee eee ees 10 7 10 3 3 Filter K Constant Input Register FKIR 0 00 0 eee eee 10 7 10 3 4 Filter Count FCNT Register epoca he nRS RO PETRA EPGCCREN E R Ee RE 10 7 10 3 5 EFCOP Control Status Register FCSR 0 0 0 0 eee 10 8 10 3 6 EFCOP ALU Control Register FACR 0 0 eee ees 10 11 10 3 7 EFCOP Data Base Address FDBA llle 10 12 10 3 8 EFCOP Coefficient Base Address FCBA 0 000 cee eee 10 13 10 3 9 Decimation Channel Count Register FDCH 0 00 e eee eee 10 13 10 3 10 EFCOP Interrupt Vectors issues exeenebextesraerw te ai dene x eae 10 14 10 4 EDCOP PFOSFAIBBIE nes iodex ke te RO RE E rE EEEE EHI RR PORC ER 10 14 10 5 Operation S mMmMma y srece eb PP E SPE SERESXPS PS Puede yee seahes 10 16 10 5 1 FIR Filter Type use eek RE ROSA EE benda aonne aa E e dons 10 16 IUSJLI R l Mode casos sare er maed dieto rn ndi sepe pito a Rs LR Sep RR ie y A 10 17 10 5 1 1 1 Adaptive NOU scs oy nak S REX RR ERA EN SEA RR SHAH SONG US 10 17 10 5 1 1 2 Multichannel Modes sx y aacri Xe RIaOEREA X aa Ree RE HORE EO X ER 10 17 10 5 1 1 3 Complex MOUB s ouui ose siete uy cutesy a E dyed ES PR ic Regu irs 10 18 Motorola DSP56311 User s Manual viii For More Information On This Product Go to www freescale com Freescale Semiconduct
153. 56 bit result are all ones or all zeros otherwise this bit is set The Scaling mode defines the integer portion If the E bit is cleared then the low order fraction portion contains all the significant bits the high order integer portion is sign extension In this case the accumulator extension register can be ignored If the E bit is set it indicates that the accumulator extension register is in use S1 SO Scaling Mode Integer Portion 0 0 No Scaling Ra eu 0 1 Scale Down En as 1 0 Scale Up PON PTT U 0 Unnormalized Set if the two MSBs of the Most Significant Portion MSP of the result are identical otherwise this bit is cleared The MSP portion of the A or B accumulators is defined by the Scaling mode S1 S0 Scaling Mode Integer Portion 0 0 No Scaling U Bit 47 xor Bit 46 0 1 Scale Down U Bit 48 xor Bit 47 1 0 Scale Up U Bit 46 xor Bit 45 3 N 0 Negative Set if the MSB of the result is set otherwise this bit is cleared 2 Z 0 Zero Set if the result equals zero otherwise this bit is cleared 1 V 0 Overflow Set if an arithmetic overflow occurs in the 56 bit result otherwise this bit is cleared V indicates that the result cannot be represented in the accumulator register i e the register overflowed In Arithmetic Saturation mode an arithmetic overflow occurs if the Data ALU result is not representable in the accumulator without the extension part i e
154. 6 Figure B 17 Figure B 18 Figure B 19 Figure B 20 Figure B 21 Figure B 22 Figure B 23 Motorola Freescale Semiconductor Inc Timer Prescalar Count Register TPCR llle sess 9 24 Timer Control Status Register TCSR 0 00 ee eee eee ee 9 24 EFCOP Block Eu3Bralliz o5 przy ode EV ois dee eddie EE EXE DE ERE 10 3 Storage of Filter Coefficients ia sss sux dnt eeeseekdoeweaduaeeh sc 10 5 EFCOP Memory Organization 0 cece eee es 10 5 Filter Count PONT Register 22e 0 4 seereed ERE ERAI E ERES E 10 8 EFCOP ALU Control Register FACR 0 0 2 10 11 Decimation Channel Count Register FDCH 05 10 13 FIR Filter Type Processing Loses de ebex pur RENOHPRdURREC RA YO RE RE 10 16 IIR Filler Type Process 24s ex VR nisd tana ae edP RS 10 20 Real FIR Filter Data stream oon esse suerk C REREREDKESE EA REPRE RENS 10 25 Adaptive FIR PIIet uei REED ROT edi RORESPC AP ETRAS 10 31 Real FIR Filter Data Stream With Decimation by M 10 31 Adaptive FIR Filter Using Polling lees 10 33 Adaptive FIR Filter Using DMA Input and Interrupt Output 10 34 Status Register SR uuo dus re Ede RR RPeCRES REDE PI GR x EP RES B 13 Operating Mode Register sura zs ad pxper Rep y RE Sd pe eee dede ees B 14 Address Attribute Registers AAR3 AARO 0 000000 B 15 Bus Control Register BCR sera keticctoRRORBO 4ERLCREAGXG RER RAN S B 16 DMA Control
155. 602 244 6609 1 800 774 1848 RMFAX0 email sps mot com Asia Pacific Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 Technical Resource Center 1 800 521 6274 DSP Helpline dsphelp dsp sps mot com Japan Nippon Motorola Ltd SPD Strategic Planning Office141 4 32 1 Nishi Gotanda Shinagawa ku Japan 81 3 5487 8488 Internet http www motorola dsp com MOTOROLA INC 1999 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Contents Chapter 1 Overview 1 1 Manual OrgantzatiOll x i eesabbrPec9ket4 se 3 me RPeren tioecad ba de uia 1 1 1 2 Manual COnVellolls 2 esses oa CS Eh RE EESTI dele REPRE NA Rd e Er TREES 1 2 1 3 Peatutes ex escebcic odes SRR Pee eS Ed t Een E RAE EE DAE ES 1 4 1 4 DS PSO 206 0 m 1 5 1 5 DSP56300 Core Functional Blocks 1 5 1 5 1 Data ADU ete temai ara eeu aE ew Geese tse eet US NP eS PERS 1 6 1 5 1 1 Data ALU Registers once rex e odie desde rece e E T RES ewe RE 1 6 1 5 1 2 Mult pher Accumulator MAC uielleeeleeeleeee ee lees 1 6 1 5 2 Address Generation Unit AGU i siecss esee RR Seba REESE RR a 1 7 1 5 3 Program Control Unit PCU sssseeeseeeeeee I I 1 7 1 5 4 PLL and Clock Oscillator js air aeter o aede ERR qo S ded SCRUCR INR dee cn 1 8 1 5 5 JTAG TAP and OnCE Module 1 sat ae RR AG R KER GG CR acre 1 9 1 5 6 Orn clip Memo
156. 6311 When the DSP56311 acknowledges the host command interrupt HIO8 hardware clears the HC bit The host processor can read the state of HC to determine when the host command has been accepted After setting HC the host must not write to the CVR again until the HIO8 hardware clears the HC Setting the HC bit causes host command pending HCP to be set in the HSR The host can write to the HC and HV bits in the same write cycle 6 0 HV 6 0 0 Host Vector Select the host command interrupt address for use by the host command interrupt logic When the DSP interrupt control logic recognizes the host command interrupt the address of the interrupt routine taken is 2 x HV The host can write HC and HV in the same write cycle The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine address divided by 2 into the HV bits This means that the host processor can force any interrupt handler SSI SCI IRQA IRQB etc and can use any reserved or otherwise unused addresses if have been pre programmed in the DSP HV is set to 32 vector location 0064 by hardware software individual and stop resets Motorola Host Interface H108 6 27 For More Information On This Product Go to www freescale com Host Programmer s Model Freescale Semiconductor Inc 6 7 3 Interface Status Register ISR The host processor uses the ISR an 8 bit read only
157. 6311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Creation of a debugging window for program development Host control protocols m Interface capabilities Glueless interface no external logic required to Motorola HC11 Hitachi H8 8051 family Thomson P6 family Host Port Signals Minimal glue logic pull ups pull downs required to interface to ISA bus Motorola 68K family Intel X86 family 6 2 Host Port Signals The host port signals are discussed in Chapter 2 Signals Connections Each host port signal can be programmed as a host port signal or as a GPIO signal PBO PB15 See Table 6 1 through Table 6 3 Table 6 1 HI08 Signal Definitions for Operational Modes HIO8 Port Signal Multiplexed Address Data Bus Nonmultiplexed Bus Mode GPIO Mode Mode HADO HAD7 HADO HAD7 H0 H7 PBO PB7 HAS HAO HAS HAS HAO PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 Table 6 2 HI08 Data Strobe Signals FICE Pent Single Strobe Bus Dual Strobe Bus GPIO Mode Signal HRW HRD HRW HRD HRD PB11 HDS HWR HDS HDS HWR HWR PB12 Motorola Host Interface H108 6 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview Table 6 3 HI08 Host Request Signals j
158. 7 34 Transmitter Enable bit TE 8 14 HI08 ICR 6 31 triple timer 5 2 triple timer module 1 14 TSMA and TSMB 7 14 7 34 TSMA TSMB registers 7 34 TSR 7 34 TSR register 7 34 TXO TX2 7 14 7 34 TX2 TX1 TXO registers 7 34 TXD 8 4 TXD signal 8 4 HI08 HSR 6 31 TXH TXM TXL registers 6 30 V VBA register 1 8 Vector Base Address register VBA 1 8 vocoder 10 1 W wait standby mode 1 5 see also reset WAKE bit 8 15 Wakeup Mode Select bit WAKE 8 15 Watchdog pulse 9 18 Watchdog Pulse mode 9 19 Watchdog Toggle 9 18 Wired OR Select bit WOMS 8 14 WOMS bit 8 14 word length frame sync 7 12 X X data memory 3 3 X I O space 3 5 X Memory Address Bus XAB 1 10 X Memory Data Bus XDB 1 10 X Memory Expansion Bus 1 10 Index 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc XAB 1 10 XDB 1 10 Y Y data Memory 3 5 internal 3 5 Y I O space 3 7 Y Memory Address Bus YAB 1 10 Y Memory Data Bus YDB 1 10 Y Memory Expansion Bus 1 10 YAB 1 10 YDB 1 10 Motorola For More Information On This Product DSP56311 User s Manual Go to www freescale com Index 15 Freescale Semiconductor Inc For More Information On This Product Go to www freescale com
159. 9 DR8 DR7 DR6 DRS DR4 DR3 DR2 DR1 DRO Figure 6 8 Host Data Direction Register HDDR X FFFFC8 6 6 4 Host Data Register HDR The HDR register holds the data value of the corresponding bits of the HIOS signals configured as GPIO signals The functionality of Dxx depends on the corresponding HDDR bit that is DRxx Table 6 9 HDR and HDDR Functionality HDDR HDR Dxx DRxx GPIO Signal Non GPIO Signal 0 Read only bit The value read is the binary value Read only bit Does not contain significant data of the signal The corresponding signal is configured as an input 1 Read write bit The value written is the value Read write bit The value written is the value read The corresponding signal is configured as an read output and is driven with the data written to Dxx 1 Defined by the selected configuration 6 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model 6 6 5 Host Base Address Register HBAR In multiplexed bus modes HBAR selects the base address where the host side registers are mapped into the host bus address space The address from the host bus is compared with the base address as programmed in the Base Address Register An internal chip select is generated if a match is found Figure 6 10 s
160. 9 general purpose flag for host to DSP communication 6 25 general purpose flags for communication between the host and the DSP 6 7 GPIO configuration options 6 16 HACK signal 6 19 HACK HRRQ handshake flags 6 23 handshake the execution of host command interrupts 6 27 handshaking mechanisms 6 6 handshaking protocol 6 6 handshaking protocols 6 6 Core DMA access 6 6 host requests 6 6 software polling 6 6 handshaking protocols choosing 6 6 handshaking protocols pros and cons of polling 6 7 hardware reset 6 22 6 31 HBAR Base Address 6 17 HCR General purpose flags for DSP to host communication 6 14 Generate a host command interrupt request 6 14 Generate a host receive data interrupt request 6 15 Generate a host transmit data interrupt request 6 14 Host Receive Interrupt Enable 6 15 HDDR 6 4 HDDR and HDR GPIO mode 6 4 HDR and HDDR functionality 6 16 HIOS8 to DSP core interface 6 1 HIOS to host processor interface 6 2 hold data value of corresponding bits of HIO8 signals configured as GPIO signals 6 16 Host Base Address Register HBAR 6 17 host can access the HIO8 in Big Endian byte order 6 25 host can access the HIO8 in Little Endian byte order 6 25 host command 6 23 host commands 6 8 Host Control Register Host Command Interrupt Enable 6 14 Host control Register Host Transmit Interrupt Enable 6 14 Host Control Register HCR Host Flags 2 3 6 14 Host Data Direction Register HDDR 6 16 Host Data Register HDR 6 16 host inte
161. AP VERRE 4 2 Intetr pt SOURCES i itkx 9 baute Abe P E Y RE REA AIRE RE SERRE dd d 4 5 Interrupt Priority Level Bits 2123424 cu RR RRREEG REESE T DRE RES 4 8 Interrupt Source Priorities Within an IPL 0 0 0 0 eee eee 4 8 DMA Request Sources lila RR ER RARE RR RR GS ERA ERG ARES 4 10 Operating Mode Register OMR Bit Definitions 4 1 Status Register Bit Definitions 0 0 0 0 eee eee eee 4 16 PLL Control Register PCTL Bit Definitions 4 21 Address Attribute Registers AARO AAR3 Bit Definitions 4 23 DMA Accessible Registers 2 cee seed een be cease RR heed abe awe 5 5 HI08 Signal Definitions for Operational Modes 0000 5 6 3 HIOS Data Strobe Signals 22s secure 9d seer ese Seer ER ERPREE RES 6 3 HIO8 Host Request Signals idisse beam mere E EE RR RE PE Res 6 4 DMA Request Sources i czzi Re be E Y bet debe EPIG RA ERXGRRNG d REA 6 9 HREQ Pin Operation In Single Request Mode ICR 2 HDRQ 0 6 10 HTRQ and HRRQ Pin Operation In Double Request Mode ICRI2ISHDROST iis ca ced Rees see m Rx E RH ER REM RE Ad 6 10 Host Control Register HCR Bit Definitions llle eese 6 14 Host Status Register HSR Bit Definitions 004 6 15 HDR and HDDR Functionality 20 0 ee eee 6 16 Host Base Address Register HBAR Bit Definitions 6 17 Host Port Control Register HPCR Bit Definitions
162. CI signals are multiplexed ESSIO with the Port C GPIO signals PCO PC5 ESSI with Port D GPIO signals PDO PD5 and SCI with Port E GPIO signals PEO PE2 3 TIOO TIO2 can be configured as GPIO signals Motorola Figure 2 1 Signals Connections For More Information On This Product Go to www freescale com Signals Identified by Functional Group 2 3 Power Freescale Semiconductor Inc 2 1 Power Table 2 2 Power Inputs Power Name Description VccP PLL Power VCC dedicated for PLL use The voltage should be well regulated and the input should be provided with an extremely low impedance path to the Vcc power rail Vocat Quiet Core Low Power An isolated power for the core processing logic This input must be isolated externally from all other chip power inputs The user must provide adequate external decoupling capacitors VccaH Quiet External High Power A quiet power source for I O lines This input must be tied externally to all other chip power inputs except Vcco The user must provide adequate decoupling capacitors VCCA Address Bus Power An isolated power for sections of the address bus I O drivers This input must be tied externally to all other chip power inputs except Voca The user must provide adequate external decoupling capacitors Vccp Data Bus Power An isolated power for sections of the data bus I O drivers This input must be tied externally to all other
163. CO5 FFD8 FFFFD8 DMA Control Register DCR5 FFD7 FFFFD7 Reserved FFD6 FFFFD6 Reserved FFD5 FFFFD5 Reserved FFD4 FFFFD4 Reserved FFD3 FFFFD3 Reserved FFD2 FFFFD2 Reserved FFD1 FFFFD1 Reserved FFDO FFFFDO Reserved FFCF FFFFCF Reserved FFCE FFFFCE Reserved FFCD FFFFCD Reserved FFCC FFFFCC Reserved FFCB FFFFCB Reserved FFCA FFFFCA Reserved Port B FFC9 FFFFC9 Host Port GPIO Data Register HDR FFC8 FFFFC8 Host Port GPIO Direction Register HDDR HI08 FFC7 FFFFC7 Host Transmit Register HTX FFC6 FFFFC6 Host Receive Register HRX FFC5 FFFFC5 Host Base Address Register HBAR FFC4 FFFFC4 Host Port Control Register HPCR FFC3 FFFFC3 Host Status Register HSR FFC2 FFFFC2 Host Control Register HCR B 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Memory Map Table B 2 Internal X I O Memory Map Continued Peripheral 16 Bit Address 24 Bit Address Register Name FFC1 FFFFC1 Reserved FFCO FFFFCO Reserved Port C FFBF FFFFBF Port C Control Register PCRC FFBE FFFFBE Port C Direction Register PRRC FFBD FFFFBD Port C GPIO Data Register PDRC ESSI 0 FFBC FFFFBC ESSI 0 Transmit Data Register 0 TX00 FFBB FFFFBB ESSI 0 Transmit Data Register 1 TX01 FFBA FFFFBA ESSI 0 Transmit Data Register 2 TX02
164. D TXC Transmitter clock RXC Receiver clock XC Transmitter receiver clock synchronous operation FST Transmitter frame sync FSR Receiver frame sync FS Transmitter receiver frame sync synchronous operation TDO Transmit data signal 0 TD1 Transmit data signal 1 TD2 Transmit data signal 2 TOD Transmitter 0 drive enable if SSC1 1 amp SCD1 1 RD Receive data FO Flag 0 F1 Flag if SSC1 0 U Unused can be used as GPIO signal X Indeterminate Motorola Enhanced Synchronous Serial Interface ESSI 7 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation When configured as an output the SC1 signal functions as a serial output flag as the transmitter 0 drive enabled signal or as the receive frame sync signal output If SC1 is used as serial output flag 1 its value is determined by the value of the serial output flag 1 OF1 bit in the CRB When configured as an input this signal can receive frame sync signals from an external source or it acts as a serial input flag As a serial input flag SClcontrols status bit IF1 in the SSISR When SC1 is configured as a transmit data signal it is always an output signal regardless of the SCDI bit value As an output it is fully synchronized with the other ESSI transmit data signals STD and SCO SC1 can be programmed as a GPIO signal P1 when the ESSI SC1 function is not in use 7 2 6 Serial Con
165. DR5 EQU FFFFDA DMAS Destination Address Register M DCO5 EQU FFFFD9 DMAS Counter A 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Equates M DCR5 EQU FFFFD8 DMAS Control Register DMA Control Register M_DSS EQU 3 DMA Source Space Mask DSSO Dss1 M_DSSO EQU 0 DMA Source Memory space 0 M_DSS1 EQU 1 DMA Source Memory space 1 M_DDS EQU C DMA Destination Space Mask DDS DDS1 M_DDSO EQU 2 DMA Destination Memory Space 0 M_DDS1 EQU 3 DMA Destination Memory Space 1 M DAM EQU 3f0 DMA Address Mode Mask DAM5 DAMO M DAMO EQU 4 DMA Address Mode 0 M DAMI EQU 5 DMA Address Mode 1 M DAM2 EQU 6 DMA Address Mode 2 M DAMS3 EQU 7 DMA Address Mode 3 M DAMA EQU 8 DMA Address Mode 4 M DAMS EQU 9 DMA Address Mode 5 M D3D EQU 10 DMA Three Dimensional Mode M DRS EQU F800 DMA Request Source Mask DRSO DRS4 M DCON EQU 16 DMA Continuous Mode M DPR EQU 60000 DMA Channel Priority M DPRO EQU 17 DMA Channel Priority Level low M DPR1 EQU 18 DMA Channel Priority Level high M DTM EQU 380000 DMA Transfer Mode Mask DTM2 DTMO M DTMO EQU 19 DMA Transfer Mode 0 M DTMI EQU 20 DMA Transfer Mode 1 M DTM2 EQU 21 DMA Transfer Mode 2 M DIE EQU 22 DMA Interrupt Enable bit M DE EQU 23 DMA Channel Enable bit DMA Status Register M DTD EQU 3F Channel Transfer Done Status MAS
166. DS2 EQU 2 M SSFTD EQU 3 M SBK EQU 4 M WAKE EQU 5 M RWU EQU 6 M WOMS EQU 7 M SCRE EQU 8 M SCTE EQU 9 M ILIE EQU 10 M SCRIE EQU 11 M SCTIE EQU 12 M TMIE EQU 13 M TIR EQU 14 M SCKP EQU 15 M REIE EQU 16 Freescale Semiconductor Inc Word Select 1 Word Select 2 SCI Shift Direction Send Break Wakeup Mode Select Receiver Wakeup Enable Wired OR Mode Select SCI Receiver Enable SCI Transmitter Enable Idle Line Interrupt Enable SCI Receive Interrupt Enable SCI Transmit Interrupt Enable Timer Interrupt Enable Timer Interrupt Rate SCI Clock Polarity SCI Error Interrupt Enable REIE d SCI Status Register Bit Flags M TRNE EQU M TDRE EQU M RDRF EQU M IDLE EQU M OR EQU M PE EQU M R8 EQU 0 1 2 3 4 5 M FE EQU 6 7 Transmitter Empty Transmit Data Register Empty Receive Data Register Full Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 R8 Address SCI Clock Control Register M CD EQU FFF M COD EQU M SCP EQU M RCM EQU M TCM EQU 12 13 14 15 Clock Divider Mask CD0 CD11 Clock Out Divider Clock Prescaler Receive Clock Mode Source Bit Transmit Clock Source Bit Register Addresses Of SSIO M TX00 EQU M_TX01 EQU M TX02 EQU M TSRO EQU M RXO EQU Motorola FFFFBC SSIO Transmit Data Register 0 FFFFBB SSIO Transmit Data Register 1 FFFFBA SSIO Transmit Data Register 2 FFFFB9 SS
167. Definitions Continued Bit Number Bit Name Reset Value Description 13 ABE 0 Asynchronous Bus Arbitration Enable EN E Eliminates the setup and hold time requirements for BB and BG and substitutes a required non overlap interval between the deassertion of one BG input to a DSP56300 family device and the assertion of a second BG input to a second DSP56300 family device on the same bus When the ABE bit is set the BG and BB inputs are synchronized This synchronization causes a delay between a change in BG or BB until this change is actually accepted by the receiving device 12 BRT Bus Release Timing Selects between fast or slow bus release If BRT is cleared a Fast Bus Release mode is selected i e no additional cycles are added to the access and BB is not guaranteed to be the last Port A pin that is tri stated at the end of the access If BRT is set a Slow Bus Release mode is selected i e an additional cycle is added to the access and BB is the last Port A pin that is tri stated at the end of the access 11 TAS TA Synchronize Select 2M Selects the synchronization method for the input Port A pin TA Transfer Acknowledge If TAS is cleared you are responsible for asserting the TA pin in synchrony with the chip clock as described in the technical data sheet If TAS is set the TA input pin is synchronized inside the chip thus eliminating the need for an off chip synchronizer Note that
168. EC 06 Debug Request I TRAP EQU I VEC 08 Trap I NMI EQU I VEC 0A Non Maskable Interrupt LIRQA EQU I VEC4 10 IRQA IIRQB EQU I VEC 12 IRQB A 20 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc LIRQC EQU I VEC 14 IRQC IIRQD EQU I VEC4 16 IRQD I DMAO EQU I VEC 18 DMA Channel 0 I DMAI EQU I VEC 1IA DMA Channel 1 I DMA2 EQU I VEC 1IC DMA Channel 2 I DMA3 EQU I VEC IE DMA Channel 3 I DMA4 EQU I VEC 20 DMA Channel 4 I DMA5 EQU I VEC 22 DMA Channel 5 IMOC EQU I VEC 24 TIMER 0 compare IMOOF EQU I VEC 4 26 TIMER 0 overflow IMIC EQU I _VEC 28 TIMER 1 compare IMIOF EQU I VEC 2A TIMER 1 overflow IM2C EQU I VEC 4 2C TIMER 2 compare IM2O0F EQU I VEC 2E TIMER 2 overflow T T T T T T I_SIORD EQU I_SIORDE EQU I SIORLS EQU I SIOTD EQU I SIOTDE EQU I SIOTLS EQU I VEC 30 ESSIO Receive Data I VEC 32 ESSIO Receive Data With Exception Status I VEC 34 ESSIO Receive last slot I VEC 36 ESSIO Transmit data I VEC 38 ESSIO Transmit Data With Exception Status I VEC 3A ESSIO Transmit last slot I SIIRD EQU I VEC 40 ESSII Receive Data I SIIRDE EQU I_VEC 42 ESSII Receive Data With Exception Status I SIIRLS EQU I VEC 44 ESSII Receive last slot I SIITD EQU I VEC 46 ESSII Transmit data I SIITDE EQU I VEC 48 ESSII Transmit Data With Exception Status I SIITLS EQU I
169. Enable bit HA9EN 6 20 Host Address Strobe Polarity bit HASP 6 19 Host Base Address Register HBAR 6 17 Host base address register HBAR 6 13 Host Chip Select Enable 6 20 Host Chip Select Enable bit HCSEN 6 20 Host Chip Select Polarity bit HCSP 6 18 Host Control Register HCR 6 14 Host control register HCR 6 13 Host Data Direction Register HDDR 6 16 Host data receive register HRX 6 13 Host Data Register HDR 6 16 Host Data Strobe Polarity bit HDSP 6 19 Host data transmit register HTX 6 13 Host Dual Data Strobe bit HDDS 6 18 Host Enable bit HEN 6 19 Host GPIO data direction register HDDR 6 13 Host GPIO data register HDR 6 13 Host Interface 2 3 2 11 2 12 2 13 2 14 6 1 Host Little Endian bit HLEND 6 25 Host Multiplexed Bus bit HMU X 6 19 Host Port Control Register HPCR 2 11 2 12 2 13 2 14 6 13 6 17 6 22 6 32 6 33 B 4 B 23 host processor address space 6 23 Host Receive Data Full bit 6 7 Host Receive Data Register HRX 6 6 6 22 Host Receive Request HRRQ 6 9 Host Request Double 2 3 Single 2 3 host request line 6 4 host request pins 6 10 host requests 6 6 host requests enabling 6 9 Host Status Register HSR 6 15 Host status register HSR 6 13 Host Transmit Data Empty bit 6 7 Host Transmit Data Register HTX 6 21 Host Transmit Data register HTX 6 7 host to DSP transfers 6 6 HPCR 6 4 HPCR register 2 11 2 14 6 22 6 32 6 33 B 4 B 23 HR 2 3 HREQ bit 6 28 HREQ signal 6 26 HRX
170. FCOP K Constant Register FKIR FFB1 FFFFB1 EFCOP Data Output Register FDOR FFBO FFFFBO EFCOP Data Input Register FDIR FFAF FFFFAF Reserved FF80 FFFF80 B 2 Interrupt Sources and Priorities Table B 4 Interrupt Sources Interrupt Gino Andrei T Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 B 8 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Interrupt Sources and Priorities Table B 4 Interrupt Sources Continued Interrupt jones Interrupt Source Starting Address Level Range VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 Timer 0 Compare VBA 26 0 2 Timer 0 Overflow VBA 28 0 2 Timer 1 Compare VBA 2A 0 2 Timer 1 Overflow VBA 2C 0 2 Timer 2 Compare VBA 2E 0 2 Timer 2 Overflow VBA 30 0 2 ESSIO Receive Data VBA 32 0 2 ESSIO Receive Data With Exception Status VBA 34 0 2 ESSIO
171. FF80 Y Data External I O Internal I O External Memory Maps C000 C000 8000 Internal Program RAM 32K Internal X data RAM 48K Internal Y data RAM 48K 0000 0000 0000 Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 0 any 0 1 32K 48K 48K None 64K value 0000 3FFF 0000 BFFF 0000 BFFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 11 Memory Switch Off Cache Off 16 Bit Mode Motorola Memory Configuration For More Information On This Product Go to www freescale com 3 19 Freescale Semiconductor Inc Memory Maps Program X Data Y Data SPERE PERPE External I O Internal I O FFCO FF80 Internal I O FFFF FF80 External External External C000 C000 8000 Internal Program RAM Internal Internal 31K X data RAM Y data RAM 0400 48K 48K 0000 0000 0000 Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 0 any 1 1 31K 48K 48K Enabled 64K value 0400 7FFF 0000 BFFF 0000 BFFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controll
172. FFFFC9 Host port GPIO direction Register M HDR EQU FFFFCS8 Host port GPIO data Register M PCRC EQU FFFFBF Port C Control Register M PRRC EQU FFFFBE Port C Direction Register M PDRC EQU FFFFBD Port C GPIO Data Register M PCRD EQU FFFFAF Port D Control register M PRRD EQU FFFFAE Port D Direction Data Register M PDRD EQU FFFFAD Port D GPIO Data Register M PCRE EQU FFFF9F Port E Control register M PRRE EQU FFFF9E Port E Direction Register M PDRE EQU FFFF9D Port E Data Register M OGDB EQU FFFFFC OnCE GDB Register Register Addresses M HCR EQU FFFFC2 Host Control Register M HSR EQU FFFFC3 Host Status Register M HPCR EQU FFFFCA Host Polarity Control Register M HBAR EQU FFFFCS5 Host Base Address Register M HRX EQU FFFFC6 Host Receive Register M HTX EQU FFFFC7 Host Transmit Register I HCR bits definition Motorola Bootstrap Program A 9 For More Information On This Product Go to www freescale com Internal I O Equates M HRIE EQU 0 M HTIE EQU 1 M HCIE EQU 2 M HF2 EQU 3 M HF3 EQU 4 HSR bits definition M HRDF EQU 0 M HTDE EQU 1 M HCP EQU 2 M HFO EQU 3 M HFI EQU 4 HPCR bits definition M HGEN EQU 0 M HASEN EQU 1 M HA9EN EQU 2 M HCSEN EQU 3 M HREN EQU 4 M HAEN EQU 5 M HEN EQU 6 M HOD EQU 8 M HDSP EQU 9 M HASP EQU A M HMUX EQU B M HD HS EQU C M HCSP EQU D M HRP EQU E M HAP EQU F Register Addresses
173. Freescale Semiconductor Inc DSP56311 User s Manual 24 Bit Digital Signal Processor DSP56311UM D Revision 1 0 October 1999 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc OnCE and Mfax are trademarks of Motorola Inc Intel is a registered trademark of the Intel Corporation All other trademarks are those of their respective owners Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify Motorola of any such intended end use whereunon Motorola shall determine availability and suitability of its product or products for the use intended Motorola and j Motorola Inc is an Equal Employment Opportunity Affirmative Action Employer are registered trademarks of Motorola Inc How to reach us USA Europe Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 441 2447 1 303 675 2140 Motorola Fax Back System Mfax TOUCHTONE
174. GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure B 26 Port C Registers PCRC PRRC PDRC Motorola Programming Reference B 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets GPIO Port D ESSI1 STD1 SRD1SCK1 SC12 SC11 SC10 5 4 3 2 1 0 Port D Control Register H X Pcs Po4 Pca Pc2 Pci PCO ARETE XS FFFAE Reset PCn 1 Port Pin configured as ESSI PCn 0 5 Port Pin configured as GPIO Readwirite Reset 5 4 3 2 1 0 Port D Direction Register H Ppcs PDc4 Pbcs Pbc2 Pbc1 Pbco cz ill EE PDCn 1 gt Port Pin is Output PDCn 0 gt Port Pin is Input HeadWie Reset 5 4 3 2 1 0 Port D GPIO Data Register H Pps PD4 Pps PD2 Pb esol TTT tei pe If port pin n is GPIO input then PDn reflects the value on port pin n If port pin n is GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure B 27 Port D Registers PCRD PRRD PDRD B 38 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets GPIO Port E SCI SCLK TXD RXD 5 4 3 2 1 0 UUEBBRBPTT PCRE X SFFFF9F Hi 0j0 0 0 Reset PCn 1 Port Pin configured as SCI PCn 0 5 Port Pin configured as GPIO ReadWrite Reset 5 4 3 2 1 0
175. GRON GRO AAI Start FCON FIR Ll EN SRC ADDRS DST ADDRS SRC COUNT DST COUN FDBA ADDRS FCBA ADDRS main program DMA channel 1 initialisation M FDOR x M DSR1 DST ADDRS x M DDR DST COUNT x M DCO1 S8EB2C1 x M_DCR1 EFCOP initialisation FIR LEN 1 y M FCNT Motorola ORG move move rep move movep movep movep movep movep movep movep movep equ 00100 equ 001 equ 20 equ 3040 equ 3000 equ 006003 equ 8 equ 0 equ 0 p Start 0 x0 DST COUNT x0 x r0 4 FDBA ADDRS r0 main program starting address EFCOP FSCR register contents enable the EFCOP EFCOP FIR length DMA source address point to DATA bank address at which to begin output DMAO count 7 4 word transfers number of outputs generated Input samples Start Address x 0 Coeff Start Address y 0 A kkkkkxkxkxkxkxkkkkkxkxkxkxkkkkkxkxkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkkkkkkkkkkkxkxk A kkkkxkxkxkxkxkxkkkkkxkxkxkxkkkkkxkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkkkkkkkkkkkxkxk FDM memory area clear FDM memory area output from EFCOP DMA source address points to the EFCOP FDIR Init DMA destination address Init DMA count Start DMA 1 with FDOBF request FIR length FDBA ADDRS y M FDBA FIR input samples Start Address FCBA ADDRS y M FCBA FIR Coeff Start Address FCON y M FCSR Enable EFCOP Enhan
176. IE Timer Overflow Interrupt Enable Enables timer overflow interrupts When set TOIE enables overflow interrupt generation The timer counter can hold a maximum value of FFFFFF When the counter value is at the maximum value and a new event causes the counter to be incremented to 000000 the timer generates an overflow interrupt When cleared the TOIE bit disables overflow interrupt generation TE Timer Enable disables the timer pull down resistors Enables disables the timer When set TE enables the timer and clears the timer counter The counter starts counting according to the mode selected by the timer control TC 3 0 bit values When clear TE bit NOTE When all three timers are disabled and the signals are not in GPIO mode all three TIO signals are tri stated To prevent undesired spikes on the TIO signals when you switch from tri state into active state these signals should be tied to the high or low signal state by pull up or Table 9 4 Inverter INV Bit Operation Mode TIO Programmed as Input TIO Programmed as Output INV 0 INV z 1 INV 0 INV 1 GPIO signal on the TIO signal read directly GPIO signal on the TIO signal inverted Bit written to GPIO put on TIO signal directly Bit written to GPIO inverted and put on TIO signal Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the fall
177. INCLUDE ORG x D INCLUDE input asm ES ADDRS Reference signal D n desired asm Desired signal R n 10 8 Verification For All Exercises 10 8 1 dc dc dc dc dc dc dc dc dc dc dc Motorola Input Sequence input asm 000000 37cc8a 343fae 0563b1 0595b4 38f46e 6a4ea2 5e8562 2beda5 1b3cd0 42 452 Enhanced Filter Coprocessor EFCOP For More Information On This Product Go to www freescale com Verification For All Exercises H kkxkxkxkxkxkxkxkxkxkxkxkkkxkkxkxkkxkkkxkxkxkkkxkxkkxkxkkxkxkxkkkxkxkkxkkxkkxkxkxkxkkkxkkkkxkkkkkkkkxkxk H KKEKKKKKKKKKKKKKKKKKK Ik S Sk SK CC Ck S e e I A A A A A x x xx ORG y FCBA ADDRS 10 37 Freescale Semiconductor Inc Verification For All Exercises dc 684ca0 dc 5093b0 dc 128ab8 dc f74eel dc 15c13a dc 336e48 dc 15e98e dc d428d2 dc b76af5 dc d69eb3 dc S 749b6 dc dee460 dc a43601 dc 903d59 dc b9999a dc e5744e 10 8 2 Filter Coefficients coefs asm dc F8125C dc F77839 dc SF4E9EE dc F29373 dc SF2DC9A dc S F51D6E dc SF688CE dc SF6087E dc S F5B5D3 dc SF7E65E dc SFBEOF8 dc SFEC8B7 dc FF79F5 dc 000342 dc 02B24F dc 06C977 dc 096ADD dc 097556 dc 08FD54 dc 0A59A5 Motorola DSP56311 User s Manual 10 38 For More Information On This Product Go to www freescale com 10 8 3 d69ea ccae3 J 6 c48f2a Sbe8b2 bad8c
178. IO Time Slot Register FFFFB8 SSIO Receive Data Register M SSISROEQU FFFFB7 M CRBO EQU FFFFB6 M CRAO EQU S FFFFBS M TSMAO EQU FFFFB4 M TSMBO EQU FFFFB3 SSIO Status Register SSIO Control Register B SSIO Control Register A SSIO Transmit Slot Mask Register A SSIO Transmit Slot Mask Register B Bootstrap Program For More Information On This Product Go to www freescale com Internal I O Equates A 11 Internal I O Equates Freescale Semiconductor Inc M RSMAO EQU FFFFB2 SSIO Receive Slot Mask Register A M RSMBO EQU FFFFB1 SSIO Receive Slot Mask Register B Register Addresses Of SSII M TXIO EQU FFFFAC SSII Transmit Data Register 0 M_TX11 EQU FFFFAB SSI Transmit Data Register 1 M_TX12 EQU FFFFAA SSI Transmit Data Register 2 M TSRI EQU FFFFA9 SSII Time Slot Register M RXI EQU FFFFAS SSII Receive Data Register M SSISRI EQU SFFFFA7 SSII Status Register M CRBI EQU FFFFA6 SSII Control Register B M CRAI EQU FFFFAS SSI Control Register A M TSMAI EQU FFFFA4 SSII Transmit Slot Mask Register A M TSMBI EQU FFFFA3 SSI Transmit Slot Mask Register B M RSMAI EQU FFFFA2 SSI Receive Slot Mask Register A M_RSMBI1 EQU FFFFAI SSII Receive Slot Mask Register B SSI Control Register A Bit Flags M PM EQU M PSR EQU M DC EQU M ALC EQU M WL EQU M SSCI EQU FF 11 1F000 18 380000 22 Prescale Modulus Select Mask PMO PM7 Prescaler R
179. K M DTDO EQU 0 DMA Channel Transfer Done Status 0 M DTD1 EQU l DMA Channel Transfer Done Status 1 M_DTD2 EQU 2 DMA Channel Transfer Done Status 2 M_DTD3 EQU 3 DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 DMA Channel Transfer Done Status 5 M DACT EQU 8 DMA Active State M DCH EQU E00 DMA Active Channel Mask DCHO DCH2 M DCHO0 EQU 9 DMA Active Channel 0 M DCHI EQU 10 DMA Active Channel 1 M DCH2 EQU 11 DMA Active Channel 2 M FDIR EQU FFFFBO EFCOP Data Input Register M FDOR EQU FFFFBI EFCOP Data Output Register M FKIR EQU FFFFB2 EFCOP K Constant Register Motorola Bootstrap Program A 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Equates M FCNT EQU M FCSR EQU M FACR EQU M FDBA EQU M FCBA EQU M FDCH EQU FFFFB8 3 FFFFB3 FFFFB4 FFFFB5 FFFFB6 FFFFB7 EFCOP Filter Counter EFCOP Control Status Register EFCOP ALU Control Register EFCOP Data Base Address EFCOP Coefficient Base Address EFCOP Decimation Channel Register Register Addresses Of PLL M PCTL EQU FFFFFD 3 2 gt PLL Control Register MMF EQU FFF MDF EQU 7000 M_XTLR EQU M_XTLD EQU M_PSTP EQU M_PEN EQU M_PCOD EQU MPD EQU F00000 15 16 17 18 19 PLL Control Register Multiplication Factor Bits Mask MFO MF 11 Division Factor Bits Mas
180. LO EQU 6 IRQC Mode Interrupt Priority Level low Motorola Bootstrap Program For More Information On This Product Go to www freescale com A 13 Internal I O Equates M ICL1 EQU M ICL2 EQU M IDL EQU M IDLO EQU M IDL1 EQU M IDL2 EQU M DOL EQU M DOLO EQU M DOL1 EQU M DIL EQU M DILO EQU M DIL1 EQU M D2L EQU M D2LO EQU M D2L1 EQU M D3L EQU M D3LO EQU M D3L1 EQU M D4L EQU M D4LO EQU M D4L1 EQU M D5L EQU M D5LO EQU M DSL EQU 7 8 E00 9 10 11 3000 12 13 c000 14 15 30000 16 17 C0000 18 19 300000 20 21 C00000 22 23 Freescale Semiconductor Inc IRQC Mode Interrupt Priority Level high IRQC Mode Trigger Mode IRQD Mode Mask IRQD Mode Interrupt Priority Level low IRQD Mode Interrupt Priority Level high IRQD Mode Trigger Mode DMAO Interrupt priority Level Mask DMAO Interrupt Priority Level low DMAO Interrupt Priority Level high DMAI Interrupt Priority Level Mask DMAI Interrupt Priority Level low DMAI Interrupt Priority Level high gt 2 DMA2 Interrupt priority Level Mask DMA2 Interrupt Priority Level low DMA2 Interrupt Priority Level high DMA3 Interrupt Priority Level Mask DMA3 Interrupt Priority Level low DMA3 Interrupt Priority Level high DMAA Interrupt priority Level Mask DMAA Interrupt Priority Level low DMAA Interrupt Priority Level high DMAS Interrupt priority Level Mask DMAS Interrupt Priority
181. M DCRO R DCOO D 11 x M IPRP enable EFCOP interrupts in IPRP 8 SR 9 SR enable interrupts in SR 0 b 0 a DST COUNT b0 counter for output interrupt FDBA ADDRS r0 FDM memory area 0 x0 DST COUN x0 x r0 Clear FDM memory area DST ADDRS r0 Destination address FIR LEN 1 y M FCNT FIR length FDBA ADDRS y M FDBA FIR input samples Start Address FCBA ADDRS y M FCBA FIR Coeff Start Address FCON y M FCSR Enable EFCOP itialisation input to EFCOP SRC ADDRS x M DSRO DMA source address points to the DATA bank Init DMA destination address Init DMA count to line mode Init DMA control reg to line mode FDIBE Wait until FDOIE A offset reg is 1 exkxkxkxkxkxkxkxkkkkxkkxkkkkkkkxkkkkkkkkkkkkkkxkxkxkkkkkkkkkkkkkkkkkkkxkxkkkkkkkxkxk is cleared 10 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes pp OH Ck khe hehe hok ko ke e Re KK EER KR ER ERE ERK KER CK Ke E KOC RC KK Ke Ke CK eek ke Kee K ERE RK kdo Interrupt handler for EFCOP output movep y M FDOR x r0 Get y k from FDOR Store in destination memory space nop dec b jne cont nop bclr 11 y M_FCSR Disable output interrupt cont rti nop nop nop org X SRC ADDRS INCLUDE input asm org y FCBA ADDRS INCLUDE coefs asm 10 7 2 Real FIR Filter With Decimation by M An N tap real FIR filter with dec
182. M register at 6 and the TXL register at 7 Data can be written into the transmit byte registers when the ISR transmit data register empty TXDE bit is set The host processor can program the ICR TREQ bit to assert the external HREQ HTRQ signal when ISR TXDE is set This informs the host processor that the transmit byte registers are empty Writing to the data register at host address 7 clears the ISR TXDE bit The contents of the transmit byte registers are transferred as 24 bit data to the HRX register when both ISR TXDE and HSR HRDF are cleared This transfer operation sets HSR TXDE and HSR HRDF Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of those status bits within the next two cycles the bit will not reflect its current status For details see the DSP56300 Family Manual Appendix B Polling a Peripheral Device for Write 6 7 7 Host Side Registers After Reset Table 6 17 shows the result of the four kinds of reset on bits in each of the HIO8 registers seen by the host processor To cause a hardware reset assert the RESET signal To cause a software reset execute the RESET instruction To reset the HEN bit individually clear the HPCR HEN bit To cause a stop reset execute the STOP instruction Table 6 17 Host Side Registers After Reset Rese
183. MO ESSIO X FFFFB5 ESSI1 X FFFFAS Figure 7 2 ESSI Control Register A CRA Table 7 3 ESSI Control Register A CRA Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to 0 for future compatibility 7 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 3 ESSI Control Register A CRA Bit Definitions Continued Bit Number Bit Name Reset Value Description 22 SSC1 0 Select SC1 Controls the functionality of the SC1 signal If SSC1 is set the ESSI is configured in Synchronous mode the CRB synchronous asynchronous bit SYN is set and transmitter 2 is disabled transmit enable TE2 0 then the SC1 signal acts as the transmitter 0 driver enabled signal while the SC1 signal is configured as output SCD1 1 This configuration enables an external buffer for the transmitter O output If SSC1 is cleared the ESSI is configured in Synchronous mode SYN 1 and transmitter 2 is disabled TE2 0 then the SC1 acts as the serial I O flag while the SC1 signal is configured as output SCD1 1 21 19 WL 2 0 Word Length Control Select the length of the data words transferred via the ESSI Word lengths of 8 12 16 24 or 32 bits can be selected The ESSI data path p
184. Memory Configuration Program RAM instruction cache X data RAM and Y data RAM size are programmable as Table 1 2 shows Table 1 2 DSP56311 Switch Memory Configuration Program RAM Instruction X Data RAM Y Data RAM Instruction Switch MSW1 MSWO Size Cache Size Size Size Cache CE Mode MS 32 K x 24 bit 0 48 K x 24 bit 48 K x 24 bit disabled disabled 0 1 0 1 31 K x 24 bit 1024 x 24 bit 48 K x 24 bit 48 K x 24 bit enabled disabled 0 1 0 1 96 K x 24 bit 0 16 K x 24 bit 16 K x 24 bit disabled enabled 0 0 95 K x 24 bit 1024 x 24 bit 16 K x 24 bit 16 K x 24 bit enabled enabled 0 0 80 K x 24 bit 0 24 K x 24 bit 24 K x 24 bit disabled enabled 0 1 79 K x 24 bit 1024 x 24 bit 24 K x 24 bit 24 K x 24 bit enabled enabled 0 1 64 K x 24 bit 0 32 K x 24 bit 32 K x 24 bit disabled enabled 1 0 63 K x 24 bit 1024 x 24 bit 32 K x 24 bit 32 K x 24 bit enabled enabled 1 0 48 K x 24 bit 0 40 K x 24 bit 40 K x 24 bit disabled enabled 1 1 47 K x 24 bit 1024 x 24 bit 40 K x 24 bit 40 K x 24 bit enabled enabled 1 1 Includes 10 K x 24 bit shared memory i e memory shared by the core and the EFCOP Motorola Overview 1 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal Buses 1 5 7 Off Chip Memory Expansion Memory can be expanded off chip to the following capacities m Data memory expansion to two 256K x 24 bit word memory spaces or up t
185. Mode TRM 1 Mode 5 internal clock TRM 0 first event N write preload M write compare TE Clock CLK 2 or prescale CLK TLR DXCN Counter x 0 N N 1 M M 1 a Counter continues counting does not stop Interrupt Service reads TCR period M N clock periods Counter continues TCR M counting does TIO pin period being measured TCF Compare Interrupt if TCIE 1 not stop Overflow may occur TOF 1 Interrupt Service reads TCR period M N clock periods NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO loads TCR with count and the counter with N Figure 9 14 Period Measurement Mode TRM 0 9 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 2 3 Measurement Capture Mode 6 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 1 0 6 Capture Measurement Input Internal In Mode 6 the timer counts the number of clocks that elapse between when the timer starts and when an external signal is received At the first appropriate transition of the external clock detected on the TIO signal TCSR TCF is set and if the TCSR TCIE bit is set a compare interrupt is generated The counter halts The conten
186. Mode 7 the timer generates periodic pulses of a preset width When the counter equals the value in the TCPR the TIO output signal is toggled and TCSR TCF is set The contents of the counter are placed into the TCR If the TCSR TCIE bit is set a compare interrupt is generated The counter continues to increment on each timer clock If counter overflow occurs the TIO output signal is toggled TCSR TOF is set and an overflow interrupt is generated if the TCSR TOIE bit is set If the TCSR TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count resumes If the TCSR TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled When the TCSR TE bit is set and the counter starts the TIO signal assumes the value of INV On each subsequent toggle of the TIO signal the polarity of the TIO signal is reversed For example if the INV bit is set the TIO signal generates the following signal 1010 If the INV bit is cleared the TIO signal generates the following signal 0101 The value of the TLR determines the output period SFFFFFF TLR 1 The timer counter increments the initial TLR value and toggles the TIO signal when the counter value exceeds FFFFFF The duty cycle of the TIO signal is determined by the value in the TCPR When the value in the TLR increments to a value equal to the value in the TCPR the TIO signal is toggled The duty cy
187. NE bit 8 24 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers In Synchronous mode data is synchronized with the transmit clock That clock can have either an internal or external source as defined by the TCM bit in the SCCR The length and format of the serial word is defined by the WDSO WDS1 and WDS2 control bits in the SCR In Asynchronous mode the start bit the eight data bits with the LSB first if SSFTD 0 and the MSB first if SSFTD 1 the address data indicator bit or parity bit and the stop bit are transmitted in that order The data to be transmitted can be written to any one of the three STX addresses If SCKP is set and SSHTD is set SCI Synchronous mode is equivalent to the SSI operation in 8 bit data on demand mode Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of those status bits within the next two cycles the bit does not reflect its current status For details see the DSP56300 Family Manual 8 7 GPIO Signals and Registers Three registers control the GPIO functionality of port SCI Port E control register PCRE Port E direction register PRRE and Port E data register PDRE 8 7 1 Port E Control Register PCRE The read write PCRE controls the functionality of SCI GPIO signals Each of
188. Name Type Reset Signal Description D0 D23 Input Output Tri stated Data Bus When the DSP is the bus master D0 D23 are active high bidirectional input outputs that provide the bidirectional data bus for external program and data memory accesses Otherwise D0 D23 are tri stated These lines have weak keepers to maintain the last state even if all drivers are tri stated 2 5 3 External Bus Control Table 2 8 External Bus Control Signals State During Signal Name Type Reset Signal Description AA0 AA3 Output Tri stated Address Attribute When defined as AA these signals can be used as chip selects or additional address lines The default use defines a priority scheme under which only one AA signal can be asserted at a time Setting the AA priority disable APD bit Bit 14 of the OMR the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals Row Address Strobe When defined as RAS these signals can be used as RAS for DRAM interface These signals are tri statable RASO RAS3 Output outputs with programmable polarity RD Output Tri stated Read Enable When the DSP is the bus master RD is an active low output that is asserted to read external memory on the data bus DO D23 Otherwise RD is tri stated WR Output Tri stated Write Enable When the DSP is the bus master WR is an active lo
189. O FFFF80 FFFF8o Internal I O FFF000 FFF000 __Extemal Internal Reserved Internal Internal Reserved Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 External 180000 Reserved 010000 00C000 008000 Internal Program RAM 64K 000000 000000 External Reserved Internal X data RAM 32K 008000 000000 External 00C000 Reserved Internal Y data RAM 32K Memory Maps Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 10 0 0 64K 32K 32K None 16M 0000 FFFF 0000 7FFF 0000 7FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 7 Memory Switch On MSW 10 Cache Off 24 Bit Mode Motorola Memory Configuration For More Information On This Product Go to www freescale com 3 15 Freescale Semiconductor Inc Memory Maps Program FFFFFF FFFFFF FFFF80 Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 External 018000 010000 00C000 Internal 63K 000400 X Data Internal I O abis Internal Reserved External Program RAM 008000 E 3 Internal X data 000000 000000 RAM 32K FFFFFF FFFFCO FFFF80 FFF000 FF0000 008000 000000 Y Data
190. O DMA Offset Register 3 DOR3 DMAO FFEF FFFFEF DMA Source Address Register DSRO FFEE FFFFEE DMA Destination Address Register DDRO FFED FFFFED DMA Counter DCOO FFEC FFFFEC DMA Control Register DCRO DMA1 FFEB FFFFEB DMA Source Address Register DSR1 FFEA FFFFEA DMA Destination Address Register DDR1 FFE9 FFFFE9 DMA Counter DCO1 FFE8 FFFFE8 DMA Control Register DCR1 DMA2 FFE7 FFFFE7 DMA Source Address Register DSR2 FFE6 FFFFE6 DMA Destination Address Register DDR2 FFE5 FFFFE5 DMA Counter DCO2 FFE4 FFFFEA DMA Control Register DCR2 DMA3 FFE3 FFFFE3 DMA Source Address Register DSR3 FFE2 FFFFE2 DMA Destination Address Register DDR3 FFE1 FFFFE1 DMA Counter DCO3 FFEO FFFFEO DMA Control Register DCR3 Motorola Programming Reference B 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Memory Map Table B 2 Internal X I O Memory Map Continued Peripheral 16 Bit Address 24 Bit Address Register Name DMA4 FFDF FFFFDF DMA Source Address Register DSR4 FFDE FFFFDE DMA Destination Address Register DDR4 FFDD FFFFDD DMA Counter DCO4 FFDC FFFFDC DMA Control Register DCR4 DMA5 FFDB FFFFDB DMA Source Address Register DSR5 FFDA FFFFDA DMA Destination Address Register DDR5 FFD9 FFFFD9 DMA Counter D
191. O Memory Map Freescale Semiconductor Inc Table B 1 Guide to Programming Sheets HI08 Figure B 9 Host Receive and Host Transmit Data Registers page B 20 Figure B 10 Host Control and Host Status Registers page B 21 Figure B 11 Host Base Address and Host Port Control Registers page B 22 Figure B 12 Interrupt Control and Interrupt Status Registers page B 23 Figure B 13 Interrupt Vector and Command Vector Registers page B 24 Figure B 14 Host Receive and Host Transmit Data Registers page B 25 ESSI Figure B 15 ESSI Control Register A CRA page B 26 Figure B 16 ESSI Control Register B CRB page B 27 Figure B 17 ESSI Status Register SSISR page B 28 Figure B 18 ESSR Transmit and Receive Slot Mask Registers TSM RSM page B 29 SCI Figure B 19 SCI Control Register SCR page B 30 Figure B 20 SCI Status and Clock Control Registers SSR SCCR page B 31 Figure B 21 SCI Receive and Transmit Data Registers SRX TRX page B 32 Timers Figure B 22 Timer Prescaler Load Count Register TPLR TPCR page B 33 Figure B 23 Timer Control Status Register TCSR page B 34 Figure B 24 Timer Load Compare Count Registers TLR TCPR TCR page B 35 GPIO Figure B 25 Host Data Direction and Host Data Registers HDDR HDR page B 36 Figure B 26 Port C Registers PCRC PRRC PDRC page B 37 Figure B 27 Po
192. OF Overflow Interrupt if TOIE 1 float TIO pin INV 0 float high TIO pin INV 1 low TIO can connect to the RESET pin internal hardware preserves the TIO value and direction for an additional 2 5 clocks to ensure a reset of valid length Figure 9 19 Watchdog Toggle Mode 9 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model 9 3 4 3 Reserved Modes Modes 8 11 12 13 14 and 15 are reserved 9 3 5 Special Cases The following special cases apply during wait and stop state m Timer behavior during wait Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed If a timer interrupt is generated the DSP56311 leaves the wait state and services the interrupt m Timer behavior during stop During execution of the STOP instruction the timer clocks are disabled timer activity stops and the TIO signals are disconnected Any external changes that happen to the TIO signals are ignored when the DSP56311 is in stop state To ensure correct operation disable the timers before the DSP56311 is placed in stop state 9 3 6 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event The timer issues a DMA trigger on every event in all modes of operation To ensure that all DMA triggers ar
193. Operating Modes measurement modes In measurement modes 4 6 a compare exception occurs when the appropriate transition occurs on the TIO signal The Compare exception sets the TCF bit TCF is cleared when a value of one is written to it or when the timer compare interrupt is serviced To configure a timer exception perform the following steps The example at the right of each step shows the register settings for configuring a Timer 0 compare interrupt The order of the steps 1s optional except that the timer should not be enabled step 2e until all other exception configuration is complete 1 Configure the interrupt service routine ISR a Load vector base address register VBA b23 8 b Define I VEC to be equal to the VBA value if that is nonzero If it is defined I VEC must be defined for the assembler before the interrupt equate file is included c Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt p TIMOC 2 Configure the interrupt trigger a Enable and prioritize overall peripheral interrupt functionality IPRP TOL 1 0 b Enable a specific peripheral interrupt TCSRO TCIE c Unmask interrupts at the global level SR I 1 0 d Configure a peripheral interrupt generating function TCSRO TC 7 4 e Enable peripheral and associated signals TCSRO TE 9 3 Operating Modes Each timer has operating modes that meet
194. P FIR length SRC ADDRS equ 3040 DMA source address point to DATA bank Motorola DSP56311 User s Manual 10 28 For More Information On This Product Go to www freescale com DST ADDRS equ SRC COUNT equ DST COUNT equ FDBA ADDRS equ FCBA ADDRS equ jmp ORG jsr nop nop Freescale Semiconductor Inc 3000 f 006003 7 8 0 0 Start p 6a gt kdo Examples of Use in Different Modes address at which to begin output DMAO count 7 4 word transfers number of outputs generated Input samples Start Address x 0 Coeff Start Address y 0 H CK cC kk ko SK kk Ck kk KK Ik Sk SK CC I e e e A A x A A x x x org P 0 PARRA RUE AGRA KARA GK AC OR RT UC COR RAR cao col b o oe o oak aae eos ap RASS DE AE AS apnea esie e RAR aede main program 53 PACKCOR OK LA MAAK OR ORC RA ICR FA RRR KEEKEKE ea se ocio b OR AEE ol oc aae bois ap aleae ge ena Pe OS e ale a aee ORG p Start interrupt initialisation bset bset bclr bclr move move move move move rep move move movep movep movep movep movep movep movep movep request E nop nop waitl jset do nop endd nop nop stop_label nop EFCOP initialisation DMA channel 0 in movep 10 x M IPRP SRC COU 1 x M DORO 11 y M_FCSR P 140 endd jmp stop label Motorola Enhanced Filter Coprocessor EFCOP M FDIR x M DDRO T X 94AA04 x
195. P offers dual MAC capabilities Its dedicated modes make the EFCOP a very flexible filter coprocessor with operations optimized for cellular base station applications The EFCOP architecture also allows adaptive FIR filtering in which the filter coefficient update is performed using any fixed point standard or non standard adaptive algorithms for example the well known Least Mean Square LMS algorithm the Normalized LMS and customized update algorithms In a transceiver base station the EFCOP can perform complex matched filtering to maximize the signal to noise ratio SNR within an equalizer In a transcoder base station or a mobile switching center the EFCOP can perform all types of FIR and IIR filtering within a vocoder as well as LMS type echo cancellation The first half of this chapter describes the structure and function of the EFCOP examining its features architecture and programming model The remainder of the chapter covers programming topics such as transferring data to and from the EFCOP using it in different modes and examples of usage 10 1 Features m Fully programmable real complex filter machine with 24 bit resolution m FIR filter options Four modes of operation with optimized performance Mode 0 FIR machine with real taps Mode 1 FIR machine with complex taps Mode 2 Complex FIR machine generating pure real imaginary outputs alternately Mode 3 Magnitude calculate the square of each input
196. Pulse Width Measurement Mode TRM 1 9 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Mode 4 internal clock TRM 1 first event N write preload n M write compare TE Clock CLK 2 or prescale CLK TLR XN e Sam Counter N N 1 M IP lt did Next 0 to 1 edge M on TIO starts counter from current count and process width being measured repeats Overflow TIO pin may occur TOF 1 Interrupt Service TCF Compare Interrupt if TCIE 1 NE reads TCR for accumulated width NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO Or Ms Nees ponQds stops the counter and loads TCR with the count Figure 9 12 Pulse Width Measurement Mode TRM 0 TCR 9 3 2 2 Measurement Input Period Mode 5 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 0 1 5 Input period Measurement Input Internal In Mode 5 the timer counts the period between the reception of signal edges of the same polarity across the TIO signal The value of the INV bit determines whether the period is measured between consecutive low to high 0 to 1 transitions of TIO or between consecutive high to low 1 to 0 transitions of TIO If INV is set high
197. RE EE ERIS B 7 Interrupt Sources 122 ce ee 6 RRRS UR RR Ru pF RR EG ERES Ra RR B 8 Interrupt Source Priorities Within an IPL llle B 10 DSP56311 User s Manual xviii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 1 Overview This manual describes the DSP56311 24 bit digital signal processor DSP its memory operating modes and peripheral modules The DSP56311 is an implementation of the DSP56300 core with a unique configuration of on chip memory cache and peripherals Use this manual in conjunction with the DSP56300 Family Manual DSP56300FM AD which describes the CPU core programming models and instruction set The DSP56311 Technical Data DSP563 1 I D 4referred to as the data sheet provides DSP56311 electrical specifications timing pinout and packaging descriptions You can obtain these documents and the Motorola DSP development tools through a local Motorola Semiconductor Sales Office or authorized distributor To receive the latest information on this DSP access the Motorola DSP home page at the address given on the back cover of this document 1 1 Manual Organization This manual contains the following sections and appendices m Chapter 1 Overview Features list and block diagram related documentation organization of this manual and the notational conventions used m Chapter 2 Signals Connections DSP56311 signals and their functional groupings
198. RM 1 2 2 6 ccc cee ence eee e een ee ee 9 9 Toggle Mode TRM 20 2 0 05 cneeve bes Oost Ee ieee Shee bee bee S 9 9 Event Counter Mode TRM 1 0 0 00 ccc ee eee 9 10 Event Counter Mode TRM 0 0 0 0 eee eee 9 11 Pulse Width Measurement Mode TRM 1 008 9 12 Pulse Width Measurement Mode TRM 20 sees 9 13 Period Measurement Mode TRM 1 0 000000 cece eee 9 14 Period Measurement Mode TRM 0 0 0000 9 14 Capture Measurement Mode TRM 0 25245 op RE ER RESET 9 15 Pulse Width Modulation Toggle Mode TRM 21 9 17 Pulse Width Modulation Toggle Mode TRM 20 L 9 18 Watchdog Pulse Mode ded PERPE P E UR EVERY CERCA QUMECTA DE 9 19 Watchdog Toggle Mode ii isse ties Rem PERROS E EERE GER RR RR 9 20 Timer Module Programmer s Model 0 000 eee ee eee 9 22 Timer Prescalar Load Register TPLR 0 000 000 ee ee eee 9 23 xiii For More Information On This Product Go to www freescale com Figures Figure 9 22 Figure 9 23 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 11 Figure 10 10 Figure 10 12 Figure 10 13 Figure B 1 Figure B 2 Figure B 3 Figure B 4 Figure B 5 Figure B 6 Figure B 7 Figure B 8 Figure B 9 Figure B 10 Figure B 11 Figure B 12 Figure B 13 Figure B 14 Figure B 15 Figure B 1
199. RQD VBA 18 0 2 DMA channel 0 VBA 1A 0 2 DMA channel 1 VBA 1C 0 2 DMA channel 2 VBA 1E 0 2 DMA channel 3 VBA 20 0 2 DMA channel 4 VBA 22 0 2 DMA channel 5 VBA 24 0 2 TIMER 0 compare VBA 26 0 2 TIMER 0 overflow VBA 28 0 2 TIMER 1 compare VBA 2A 0 2 TIMER 1 overflow VBA 2C 0 2 TIMER 2 compare VBA 2E 0 2 TIMER 2 overflow VBA 30 0 2 ESSIO receive data Motorola Core Configuration 4 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Sources and Priorities Table 4 2 Interrupt Sources Continued ent Starting Address Range Interrupt Source VBA 32 0 2 ESSIO receive data with exception status VBA 34 0 2 ESSIO receive last slot VBA 36 0 2 ESSIO transmit data VBA 38 0 2 ESSIO transmit data with exception status VBA 3A 0 2 ESSIO transmit last slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 ESSI1 receive data VBA 42 0 2 ESSI1 receive data with exception status VBA 44 0 2 ESSI1 receive last slot VBA 46 0 2 ESSI1 transmit data VBA 48 0 2 ESSI1 transmit data with exception status VBA 4A 0 2 ESSI1 transmit last slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI receive data VBA 52 0 2 SCI receive data with exception status VBA 54 0 2 SCI transmit data VBA 56 0 2 SCI idle line VBA 58 0 2 SCI timer VBA 5A 0 2 Reserved VBA 5C 0 2 R
200. RSKAENEA AXE RERERS 6 5 HI08 Core Interrupt Operation ssleeeeee es 6 8 EIOS Host Request Str ctufe 2 choc sees ee rn rRrIa RR hr eee eoeees 6 10 HI08 Read and Write Operations in Little Endian Mode 6 11 HI08 Read and Write Operations in Big Endian Mode 6 12 Host Control Register HCR X FFFFC2 0 0 000 0 e eee 6 14 Host Status Register HSR X FFFFC3 000 c cece eee 6 15 Host Data Direction Register HDDR X FFFFC8 0005 6 16 Host Base Address Register HBAR X FFFFC5 0005 6 17 Self Chipsselegt Logic 222 092 samau ase m rd erede duda de dre rae ons a 6 17 Host Port Control Register HPCR X FFFFC4 00005 6 18 Single Strobe Bus 1 2 5 ssosius ee Rb p 9 ERR REESE 6 21 Dual Strobe Bus cao E3y e RE RR EOMORRES REDE RECETA E AREE 6 21 Interface Control Register UCR uv eswusvestep akeeskep9esaykx 6 24 Command Vector Register CVR lslleeeeeeeeeeee 6 27 Interface Status Registe SR s uos ae dete ReCRP x RERCRTA X RES RAR R 6 28 Interrupt Vector Register IVR i2 caasa ek hibha RE REI ER RE Rc 6 30 ESSI Block Diagram ois osaesuctes ce eee ee a eae da Pu ad e C 7 2 ESSI Control Register A CRA 2 0 0 eee ee eee 7 14 ESSI Clock Generator Functional Block Diagram 7 17 ESSI Frame Sync Generator Functional Block Diagram 7 18 ESSI Control Register B CRB 0 0 0 cee eee ee nee 7
201. Register DCR 4i sas esse serbe Rh nr Re 9n B 17 Interrupt Priority Register Core IPR C lseseseeeeeeeeee B 18 Interrupt Priority Register Peripherals IPR P 0 B 19 Phase Lock Loop Control Register PCTL seeesssss B 20 Host Receive and Host Transmit Data Registers 04 B 21 Host Control and Host Status Registers llle B 22 Host Base Address and Host Port Control Registers B 23 Interrupt Control and Interrupt Status Registers 04 B 24 Interrupt Vector and Command Vector Registers 0 5 B 25 Host Receive and Host Transmit Data Registers lesse B 26 ESSI Control Register A CRA amp ioocd kasd REVEXGARXRRCAY RH RR REAES B 27 ESSI Control Register B CRB 1 essescine a RR RR RE REESE B 28 ESSI Status Register SSISR 2 6 cc440ec4 24 RR ARE E RR ee RR RR Reg B 29 ESSR Transmit and Receive Slot Mask Registers TSM RSM B 30 SCI Control Register SCR 1 046020 sanodeoed XE OR RR SPP B 31 SCI Status and Clock Control Registers SSR SCCR B 32 SCI Receive and Transmit Data Registers SRX TRX B 33 Timer Prescaler Load Count Register TPLR TPCR B 34 Timer Control Status Register TCSR 0 0 0 B 35 DSP56311 User s Manual xiv For More Information On This Product Go to www freescale com Figure B 24 Figure B 25 Figure B 26 Figur
202. Reserved Program as 0 Y FFFFB5 Read Write Reset 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Base Address FDM Pointer EFCOP Data Base Address FDBA Y FFFFB6 Read Write Reset 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Coefficient Base Address FDM Pointer EFCOP Coefficient Base Address FCBA Y FFFFB7 Read Write Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Filler Deci BHHEEEHHEHEERS SHE EFCOP Decimation Channel Count Register FDCH Reserved Program as 0 Y FFFFB8 Read Write Reset 000000 Figure B 30 EFCOP FACR FDBA FCBA and FDCH Registers Motorola Programming Reference B 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets B 42 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Index A AAR see Address Attribute Registers adaptive filter 10 1 adder modulo 1 7 offset 1 7 reverse carry 1 7 Address Arithmetic Logic Unit Address ALU 1 7 Address Attribute Registers AARI AAR4 4 22 Address Generation Unit 1 7 Address Mode Wakeup 8 3 addressing modes 1 7 AGU see Address Generation Unit ALC bit 7 16 Alignment Control bit ALC 7 16 ALU see Address Arithmetic Logic Unit see Data Arithmetic Logic Unit asynchronous data transfer 8 2 Asynchronous mode 7 10 8 2 8 15 8 17 8 18 8 19 8 20 Asyn
203. SII GPIO 5 8 ESSI related program the GPIO pins as outputs or configure the pins in the PCR as ESSI signals 7 23 Programming the ESSI to use an internal frame sync 7 23 example of how to initialize the ESSI 7 7 expansion memory 3 1 external address bus 2 6 external bus control 2 6 2 8 2 9 external data bus 2 6 external memory expansion port 2 6 external Y I O space 3 7 F FCM 10 2 FDM 10 2 features of clock generator 8 19 filter adaptive 10 1 cross correlation 10 1 echo cancellation 10 31 Index 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FIR 10 1 IIR 10 1 10 2 multichannel 10 1 Filter ALU Control Register 10 11 10 12 Filter Coefficient Base Address 10 13 Filter Coefficient Memory 10 2 Filter Control Status Register 10 8 Filter Count Register 10 7 Filter Data Base Address 10 12 Filter Data Input Register 10 7 Filter Data Memory bank 10 2 Filter Data Output Register 10 7 Filter K Constant Input Register 10 7 Filter Multiplier and Accumulator 10 6 Finite Impulse Response filter 10 1 FIR decimation by 2 10 30 filter 10 1 mode 10 1 no decimation 10 22 no decimation polling 10 25 Real mode 0 10 22 10 25 10 30 single channel Adaptive mode no decimation 10 31 DMA and interrupts 10 34 polling 10 33 single channel 10 22 10 25 10 30 frame rate divider 7 10 frame sync I O signal 7 6 frame sync length ESSI 7 12 frame
204. T JCLR JSET JSCLR and JSSET The contents of the internal Y I O memory space are listed in Appendix A 3 3 4 External Y I O Space Off chip peripheral registers should be mapped into the top 112 locations SFFFF90 FFFFFF to take advantage of the move peripheral data MOVED instruction and the bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET This area is the external Y I O space 3 4 Dynamic Memory Configuration Switching When the internal memory configuration is altered by remapping RAM modules from X and Y data memories into program memory space and vice versa data contents of the switched RAM modules are preserved Any sequence that complies with the switch condition is valid For example if the program flow executes in the address range that is not affected by the switch the switch condition can be met very easily A switch can be accomplished just by changing the OMR MS MSW bits in the regular program flow assuming no accesses to the affected address ranges of the data memory occur up to three instructions after the instruction that changes the OMR bits CAUTION To ensure that dynamic switching is trouble free do not allow any accesses including instruction fetches to or from the affected address ranges in program and data memories during the switch cycle Motorola Memory Configuration 3 7 For More Information On This Product Go to www freescal
205. WU bit is cleared and the first frame of data is received If interrupts are enabled the CPU is interrupted and the interrupt routine reads the message header to determine whether the message is intended for this DSP If the message is for this DSP the message is received and RWU is set to wait for the next message If the message is not for this DSP the DSP immediately sets RWU Setting RWU causes the DSP to ignore the remainder of the message and wait for the next message Either a hardware RESET signal or a software RESET instruction clears RWU RWU is ignored in Synchronous mode WAKE Wakeup Mode Select When WAKE is cleared the wakeup on Idle Line mode is selected In the wakeup on idle line mode the SCI receiver is re enabled by an idle string of at least 10 or 11 depending on WDS mode consecutive ones The transmitter s software must provide this idle string between consecutive messages The idle string cannot occur within a valid message because each word frame there contains a start bit that is O When WAKE is set the wakeup on address bit mode is selected In the wakeup on address bit mode the SCI receiver is re enabled when the last eighth or ninth data bit received in a character frame is 1 The ninth data bit is the address bit R8 in the 11 bit multidrop mode the eighth data bit is the address bit in the 10 bit asynchronous and 11 bit asynchronous with parity modes Thus the received character is a
206. When SCD1 is set SC1 is an output Data present in bit OF1 is written to SC1 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode OFO Serial Output Flag 0 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0 the SCO signal is configured as ESSI flag 0 When SCDO is set the SCO signal is an output Data present in Bit OFO is written to SCO at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode 7 24 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Word Length FSL1 0 FSLO 0 Serial Clock RX TX Frame sew HQ RX TX Serial Data NOTE Frame sync occurs while data is valid One Bit Length FSL1 1 FSLO 0 Serial Clock RX TX Frame SYNC NOTE Frame sync occurs for one bit time preceding the data Mixed Frame Length FSL1 0 FSLO 1 Serial Clock RX Frame Sync RXSerial Data TX Frame SYNC TX Serial Data Mixed Frame Length FSL1 1 FSLO 1 Serial Clock RX Frame SYNC RX Serial Data TX Frame SYNC Jl Lb Dp L Figure 7 6 CRB FSLO and FSL1 Bit Operation FSR 0 Motorola Enhanced Synchronous Serial Interface ESSI 7 25 For More Information On This Product Go to www freescale com Freescale Semiconduct
207. X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 9 Memory Switch On MSW 11 Cache Off 24 Bit Mode Motorola Memory Configuration 3 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data FFFFFF SFFFFFF External I O Internal l O FFFFCO FFFFFF FFFF80 FFFF80 Internal I O siiis ib Internal Reserved Internal Internal FFO0CO Reserved Reserved FF0000 Bootstrap ROM FF0000 FF0000 External External External 018000 00C000 00C000 00C000 Internal 00A000 00A000 Program RAM 47K 000400 Internal X data Internal Y data Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 11 1 0 47K 40K 40K Enabled 16M 0400 BFFF 0000 9FFF 0000 9FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 10 Memory Switch On MSW 11 Cache On 24 Bit Mode 3 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Program FFFF External FFFF FF80 X Data Internal I O External FFFF FFCO
208. a Contents iii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 8 Enhanced Synchronous Serial Interface 0 llle 2 14 2 9 Enhanced Synchronous Serial Interface 1 0 0 0 eee ee eee 2 17 2 10 SC ls eens 2 19 2 11 J rg needed cededtet GS nude E E T oe Ree ober seeeoGe EE 2 19 2 12 JTAG and OnCE Interfaces suus rre dorm eee ued Vp deck we bee 2 20 Chapter 3 Memory Configuration 3 1 Program Memory Space assxexauweesastin esed iu egudeda VEA RU P a e 3 1 3 1 1 Internal Program Memory sseeeeeee ea 3 1 3 1 2 Memory Switch Modes Program Memory 0 0 eee eee eee eee 3 2 3 1 3 Instr ction Cache 1252s zara RR RR ERRARE de EEA TU E ORE ERE Ed RE EE 3 3 3 1 4 Program Bootstrap ROM is od 540 cde pase RED E P EEEdOPEEE REIR EE ES 3 3 3 2 X Data Memory SpB66 s 2434 erx eed rre WE bees REX RERRY RH EN enades 3 3 3 2 1 Internal X Data Memory ioco chi ex RO RR 8Gbbi GS RARE ERG RA PES 3 3 3 2 20 Memory Switch Modes X Data Memory 0 eee eee eee eee ee 3 4 3 2 3 Internal X WO Space 4v pua ud ERR snes sce kee ed Sone bese x d 3 5 33 Y Data Memory Spates ss Los Cuna Coh doe dese see eoed eet eee es 3 5 3 3 1 Internal Y Data Memory coss ess eckesssueuhe riassueissAeHhwadakskmeRs 3 5 3 3 2 Memory Switch Modes Y Data Memory 0 0 0 0 cece een 3 6 3 3 3 Internal YW Space os od Pes ex mara op
209. a DMA transfer takes place only if a DMA channel is activated and triggered by this event A write to the FDIR clears the FDIBE bit 13 FCONT Filter Contention When set this read only status bit indicates an attempt by both the DSP56300 core and the EFCOP to access the same 256 word bank in either the shared FDM or FCM A dual access could result in faulty data output in the FDOR Once set the FCONT bit is a sticky bit that can only be cleared by a hardware RESET signal a software RESET instruction or an individual reset 12 FSAT Filter Saturation When set this read only status bit indicates that an overflow or underflow occurred in the MAC result When an overflow occurs the FSAT bit is set and the result is saturated to the most positive number that is 7FFFFF When an underflow occurs the FSAT bit is set and the result is saturated to the most negative number that is 800000 FSAT is a sticky status bit that is set by hardware and can be cleared only by a hardware RESET signal a software RESET instruction or an individual reset 11 FDOIE Filter Data Output Interrupt Enable This read write control bit enables the filter data output interrupt If FDOIE is cleared the filter data output interrupt is disabled and the FDOBF status bit should be polled to determine whether the FDOR is full If both FDOIE and FDOBF are set the EFCOP requests a data output buffer full interrupt service f
210. a EERE RTR EEEE N 4 16 PLL Control Begister PC Ioue odes sper SEE cera DA 4 21 Identification Register Configuration Revision 0 lusus 4 22 Address Attribute Registers AARO AAR3 X FFFFF9 FFFFF6 ui uuzieuzkenhye Sud Re XR HE Ran Y qs 4 23 JTAG Identification Register Configuration Revision 0 4 25 Memory Mapping of Peripherals Control Registers 5 2 Port B Signals 222 isdesnericeeddeeducesoteicuessnetaseeenecigerss 5 7 Port Signals wn ssri resines perest sate bee eee MEER UN P Semele ee 5 7 DSP56311 User s Manual xi For More Information On This Product Go to www freescale com Figures Figure 5 4 Figure 5 5 Figure 5 6 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Motorola Freescale Semiconductor Inc Port D Signals 13 22 25 Re p 6 RE AR DE REG A px ERE ease PE Rr RE 5 8 Port E Signals exer daensseendereyce dates ver coo ee en ES ETATS REED 5 8 Irple Timet Signals 21 3265 unssaeees pees POE E EX E EP EE E se 5 9 EHOS Block DISBIHII s oceans 259 da E ERG E P EPPERE
211. a register of every enabled transmitter are transferred to the transmit shift register It is also set fora TSR disabled time slot period in Network mode as if data were being transmitted after the TSR has been written When TDE is set TDE data is written to all the TX registers of the enabled transmitters or to the TSR The TDE bit is cleared when the DSP writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot If the TIE bitis set a DSP transmit data interrupt request is issued when TDE is set 5 ROE 0 Receiver Overrun Error Flag Set when the serial receive shift register is filled and ready to transfer to the receive data register RX but RX is already full that is the RDF bit is set If the REIE bit is set a DSP receiver overrun error interrupt request is issued when the ROE bit is set The programmer clears ROE by reading the SSISR with the ROE bit set and then reading the RX Motorola Enhanced Synchronous Serial Interface ESSI 7 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 5 ESSI Status Register SSISR Bit Definitions Continued Bit Number Bit Name Reset Value Description 4 TUE 0 Transmitter Underrun Error Flag TUE is set when at least one of the enabled serial transmit shift registers is empty that is there is no
212. a variety of system requirements as follows m Timer GPIO mode 0 Internal timer interrupt generated by the internal clock Pulse mode 1 External timer pulse generated by the internal clock Toggle mode 2 Output timing signal toggled by the internal clock Event counter mode 3 Internal timer interrupt generated by an external clock 9 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes W Measurement Input width mode 4 Input pulse width measurement Input pulse mode 5 Input signal period measurement Capture mode 6 Capture external signal PWM mode 7 Pulse width modulation Watchdog Pulse mode 9 Output pulse internal clock Toggle mode 10 Output toggle internal clock Note To ensure proper operation the TCSR TC 3 0 bits should be changed only when the timer is disabled that is when TCSR TE is cleared 9 3 1 Triple Timer Modes For all triple timer modes the following points are true m The TCSR TE bit is set to clear the counter and enable the timer Clearing TCSR TE disables the timer m The value to which the timer is to count is loaded into the TCPR This is true for all modes except the measurement modes modes 4 through 6 m The counter is loaded with the TLR value on the first clock m Ifthe counter overflows TCSR TOF is set and if TCSR TOIE is set an ove
213. able for use as internals or event counters Chapter 10 Enhanced Filter Coprocessor EFCOP Structure and function of the EFCOP including features architecture and programming model programming topics such as data transfer to and from the EFCOP its use in different modes and examples of usage m Appendix A Bootstrap Code Bootstrap code for the DSP56311 B Appendix B Programming Reference Peripheral addresses interrupt addresses 1 2 and interrupt priorities for the DSP56311 programming sheets listing the contents of the major DSP56311 registers for programmer s reference Manual Conventions This manual uses the following conventions Bits within registers are always listed from most significant bit MSB to least significant bit LSB Bits within a register are indicated AA n m n m when more than one bit is involved in a description For purposes of description the bits are presented as if they are contiguous within a register However this is not always the case Refer to the programming model diagrams or to the programmer s sheets to see the exact location of bits within a register When a bit is described as set its value is 1 When a bit is described as cleared its value is 0 The word assert means that a high true active high signal is pulled high to Voc or that a low true active low signal is pulled low to ground The word deassert means that a high true signal is pu
214. ace Status Register ICR Interface Control Register CVR Command Vector Register IVR Interrupt Vector Register Figure 6 1 Host For More Information On This Product Go to Comparator ICR IVR Latch i Pa e F I I 24 24 24 Host 8 RXH Receive Register High RXM Receive Register Middle RXL Receive Register Low TXH Transmit Register High TXM Transmit Register Middle TXL Transmit Register Low Address l I HOST Bus Data Registers HIO8 Block Diagram Interface H108 6 5 www freescale com Freescale Semiconductor Inc Operation 6 4 Operation The HIOS is a slave only device so the host is the master of all bus transfers In host to DSP transfers the host writes data to the Transmit Byte Registers TXH M L In DSP to host transfers the host reads data from the Receive Byte Registers RXH M L The DSP side has access only to the Host Receive Data Register HRX and the Host Transmit Data Register HTX Data automatically moves between the host side data registers and the DSP side data registers when it is available This double buffered mechanism allows for fast data transfers but creates a pipeline that can either stall communication if the pipeline is either full or empty or cause erroneous data transfers new data to be overwritten or old data to be read twice The HIO8 port has several handshaking mechanisms to counter these buffering effects Suppose the host is writ
215. affected by the new TSM setting If the TSM is read it shows the current setting After a hardware RESET signal or software RESET instruction the TSM register is reset to FFFFFFFF enabling all 32 slots for data transmission 7 5 10 Receive Slot Mask Registers RSMA RSMB Both receive slot mask registers are read write registers In Network mode the receiver s use these registers to determine which action to take in the current time slot Depending on the setting of the bits the receiver s either tri state the receiver s data signal s or receive a data word and generate a receiver full condition 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 11 10 9 8 7 6 5 4 3 2 1 0 RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RSO ESSIO X FFFFB2 ESSI1 X FFFFA2 Figure 7 16 ESSI Receive Slot Mask Register A RSMA Motorola Enhanced Synchronous Serial Interface ESSI 7 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 23 22 21 20 19 18 17 16 15 14 13 12 RS31 RS30 RS29 RS28 11 10 9 8 7 6 5 4 3 2 1 0 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 Reserved Read as zero Write with zero for future compatibility ESSIO X FFFFB1 ESSI1 X FFFFA1
216. ag in a specified control register and therefore does not allow the core to execute other code at the same time For interrupts you can initialize the interrupt so it is triggered off one of the same flags that can also be polled Then the core does not have to continuously check a flag Once the interrupt is initialized and the flag is set the core is notified to execute a data transfer Until the flag is set the core can remain busy executing other sections of code Motorola Programming the Peripherals 5 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Transfer Methods When an interrupt occurs the core execution flow jumps to the interrupt start address defined in Table B 4 in Appendix B Programming Reference It executes code starting at the interrupt address If it is a short interrupt i e the service routine is two opcodes long the code automatically returns to the original program flow after executing two opcodes with no impact to the pipeline Otherwise if a longer service routine is required the programmer can place a jump to subroutine JSR instruction at the interrupt service address In this case the program executes that service routine and continues until a return from interrupt RTI instruction executes The execution flow then resumes from the position the program counter was in before the interrupt was triggered Configuring interrupts requires two steps 1 Setti
217. ale com Freescale Semiconductor Inc Bootstrap Code HA8EN 0 address 8 enable bit has no meaning non multiplexed bus HGEN 0 Host GPIO pins are disabled bra HIOSCONT HCIIHOSTLD movep 0000001000011000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negatice chip select input HD HS 0 Single strobe bus R W and DS HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 1 Negative data strobes polarity HROD 0 Host request is active when enabled spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified 2 HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no 3 meaning in non multiplexed bus HGEN 0 Host GPIO pins are disabled bra lt HIO8CONT I8051HOSTLD movep 0001110000011110 x M_ HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP O0 Negative host request HCSP 0 Negative chip select input HD HS 1 Dual strobes bus RD and WR HMUX 1 Multiplexed bus HASP 1 Positive address strobe polarity HDSP 0 Negative data strobes polarity HROD 0 Host request is active when enabled
218. ale com Freescale Semiconductor Inc Operation 4 Configure at least one signal as ESSI signal 5 f an external frame sync is used from the moment the ESSI is activated at least five 5 serial clocks are needed before the first external frame sync is supplied Otherwise improper operation may result When the PC 5 0 bits in the GPIO Port Control Register PCR are cleared during program execution the ESSI stops serial activity and enters the individual reset state All status bits of the interface are set to their reset state The contents of CRA and CRB are not affected The ESSI individual reset allows a program to reset each interface separately from the other internal peripherals During ESSI individual reset internal DMA accesses to the data registers of the ESSI are not valid and data read there are undefined To ensure proper operation of the ESSI use an ESSI individual reset when you change the ESSI control registers except for bits TEIE REIE TLIE RLIE TIE RIE TE2 TE1 TEO and RE Here is an example of how to initialize the ESSI 1 Put the ESSI in its individual reset state by clearing the PCR bits 2 Configure the control registers CRA CRB to set the operating mode Disable the transmitters and receiver by clearing the TE 2 0 and RE bits Set the interrupt enable bits for the operating mode chosen 3 Enable the ESSI by setting the PCR bits to activate the input output signals to be used 4 Wri
219. amming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 22 TEIE 0 Transmit Exception Interrupt Enable When the TEIE bit is set the DSP is interrupted when both TDE and TUE in the ESSI status register are set When TEIE is cleared this interrupt is disabled The use of the transmit interrupt is documented in Section 7 3 3 Exceptions on page 7 8 A read of the status register followed by a write to all the data registers of the enabled transmitters clears both TUE and the pending interrupt 21 RLIE 0 Receive Last Slot Interrupt Enable Enables disables an interrupt after the last slot of a frame ends when the ESSI is in Network mode When RLIE is set the DSP is interrupted after the last slot in a frame ends regardless of the receive mask register setting When RLIE is cleared the receive last slot interrupt is disabled The use of the receive last slot interrupt is documented in Section 7 3 3 Exceptions on page 7 8 RLIE is disabled when the ESSI is in On Demand mode DC 0 20 TLIE 0 Transmit Last Slot Interrupt Enable Enables disables an interrupt at the beginning of the last slot of a frame when the ESSI is in Network mode When TLIE is set the DSP is interrupted at the start of the last slot in a frame regardless of the transmit mask register setting When TLIE is cleared the transmit last slot interrupt is disabled The transmit last s
220. ange Frame Rate Divider Control Mask DCO DC7 Alignment Control ALC Word Length Control Mask WLO WL7 Select SC1 as TR 0 drive enable SSCI SSI Control Register B Bit Flags M OF0 EQU M OF1 EQU M SCD EQU M SCDO EQU M SCDI EQU M SCD2 EQU M SCKD EQU M SHFD EQU M FSL EQU M FSLO EQU M FSLI EQU M FSR EQU M FSP EQU M CKP EQU M SYN EQU M MOD EQU M SSTE EQU M SSTE2 EQU M SSTEI EQU M SSTEO EQU M SSRE EQU M SSTIE EQU M SSRIE EQU M STLIE EQU M SRLIE EQU A 12 M OF EQU 3 0 1 1C 13 1C000 14 15 16 17 18 19 20 21 Serial Output Flag Mask Serial Output Flag 0 Serial Output Flag 1 Serial Control Direction Mask Serial Control 0 Direction Serial Control 1 Direction Serial Control 2 Direction Clock Source Direction Shift Direction Frame Syne Length Mask FSLO FSL 1 Frame Sync Length 0 Frame Sync Length 1 Frame Sync Relative Timing Frame Syne Polarity Clock Polarity Sync Async Control SSI Mode Select SSI Transmit enable Mask SSI Transmit Z2 Enable SSI Transmit Z1 Enable SSI Transmit Z0 Enable SSI Receive Enable SSI Transmit Interrupt Enable SSI Receive Interrupt Enable SSI Transmit Last Slot Interrupt Enable SSI Receive Last Slot Interrupt Enable DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Equates M STEIE EQU 22 SSI Transmit Erro
221. ansmit and receive control bits are configured Whether it is necessary to use the INIT bit to initialize the HI08 hardware depends on the software design of the interface The type of initialization when the INIT bit is set depends on the state of TREQ and RREQ in the HI08 The INIT command which is local to the HI08 configures the HIO8 into the desired data transfer mode When the host sets the INIT bit the HI08 hardware executes the INIT command The interface hardware clears the INIT bit after the command executes After INIT Execution Transfer Direction TREQ Initialized PREQ 0 0 INIT 0 None 0 1 INIT 0 RXDF 0 HTDE 1 DSP to host INIT 0 TXDE 1 HRDF 0 Host to DSP INIT 0 RXDF 0 HTDE 1 TXDE 1 HRDF 0 Host to from DSP Reserved Write to 0 for future compatibility HLEND Host Little Endian If the HLEND bit is cleared the host can access the HI08 in Big Endian byte order If set the host can access the HI08 in Little Endian byte order If the HLEND bit is cleared the RXH TXH register is located at address 5 the RXM TXM register at 6 and the RXL TXL register at 7 If the HLEND bit is set the RXH TXH register is located at address 7 the RXM TXM register at 6 and the RXL TXL register at 5 HF1 Host Flag 1 A general purpose flag for host to DSP communication The host processor can set or clear HF1 and the DSP56311cannot chang
222. ansmits data from the serial transmit shift register STD1 is an output when data is being transmitted Port D 5 The default configuration following reset is GPIO input PD5 When configured as PD5 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal STD1 through PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated 2 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com 2 10 SCI Freescale Semiconductor Inc SCI The SCI provides a full duplex port for serial communication with other DSPs microprocessors or peripherals such as modems Table 2 13 Serial Communication Interface Signal Name Type State During Reset Signal Description RXD PEO Input Input or Output Input Serial Receive Data Receives byte oriented serial data and transfers it to the SCI receive shift register Port E 0 The default configuration following reset is GPIO input PEO When configured as PEO signal direction is controlled through the SCI port directions register PRR The signal can be configured as an SCI signal RXD through the SCI port control register PCR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated TXD PE1 Output Input or Output Input Serial Transmit Data Transmits data from the SCI
223. ase you select it by setting the FSL 1 0 bits in the CRA to 01 Figure 7 4 shows the ESSI frame sync generator functional block diagram 11 PSR Prescaler Range Controls a fixed divide by eight prescaler in series with the variable prescaler This bit extends the range of the prescaler when a slower bit clock is needed When PSR is set the fixed prescaler is bypassed When PSR is cleared the fixed divide by eight prescaler is operational as in Figure 7 3 This definition is reversed from that of the SSI in other DSP56000 family members The maximum allowed internally generated bit clock frequency is the internal DSP56311 clock frequency divided by 4 the minimum possible internally generated bit clock frequency is the DSP5631 1 internal clock frequency divided by 4096 NOTE The combination PSR 1 and PM 7 0 00 dividing Feore by 2 can cause synchronization problems and thus should not be used 10 8 Reserved Set to 0 for future compatibility 7 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 3 ESSI Control Register A CRA Bit Definitions Continued Bit Number Bit Name Reset Value Description 7 0 PM 0 Prescale Modulus Select Specify the divide ratio of the prescale divider in the ESSI clock generator A divide ratio from 1 to 256 PM 0 to FF
224. ata interrupts are disabled and the transmit data register empty TDRE bit in the SCI status register must be polled to determine whether the transmit data register is empty If both TIE and TDRE are set the SCI requests an SCI transmit data interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears TIE 11 RIE SCI Receive Interrupt Enable Enables disables the SCI receive data interrupt If RIE is cleared the receive data interrupt is disabled and the RDRF bit in the SCI status register must be polled to determine whether the receive data register is full If both RIE and RDRF are set the SCI requests an SCI receive data interrupt from the interrupt controller Receive interrupts with exception have higher priority than normal receive data interrupts Therefore if an exception occurs that is if PE FE or OR are set and REIE is set the SCI requests an SCI receive data with exception interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears RIE 10 ILIE Idle Line Interrupt Enable When ILIE is set the SCI interrupt occurs when IDLE SCI status register bit 3 is set When ILIE is cleared the IDLE interrupt is disabled Either a hardware RESET signal or a software RESET instruction clears ILIE An internal flag the shift register idle interrupt SRIINT flag is the interrupt request to the interrupt
225. ated by the timer has the timer has positive polarity negative polarity 9 4 5 Timer Load Register TLR The TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TCSR TE bit is set and a first event occurs Motorola In timer modes if the TCSR TRM bit is set the counter is reloaded each time after it reaches the value contained by the timer compare register and the new event occurs In measurement modes if TCSR TRM and TCSR TE are set the counter is reloaded with the value in the TLR on each appropriate edge of the input signal In PWM modes if TCSR TRM is set the counter is reloaded each time after it overflows and the new event occurs In watchdog modes if TCSR TRM is set the counter is reloaded each time after it reaches the value contained by the timer compare register and the new event occurs In this mode the counter is also reloaded whenever the TLR is written with a new value while TCSR TE is set In all modes if TCSR TRM is cleared TRM 0 the counter operates as a free running counter Triple Timer Module 9 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model 9 4 6 Timer Compare Register TCPR The TCPR is a 24 bit read write register that contains the value to be compared to the counter value These two values are compared every timer c
226. ation 12 Reserved Set to 0 for future compatibility 4 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Status Register SR Table 4 7 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 11 10 1 S0 0 Scaling Mode Specify the scaling to be performed in the Data ALU shifter limiter and the rounding position in the Data ALU MAC unit The Shifter limiter Scaling mode affects data read from the A or B accumulator registers out to the X data bus XDB and Y data bus YDB Different scaling modes can be used with the same program code to allow dynamic scaling One application of dynamic scaling is to facilitate block floating point arithmetic The scaling mode also affects the MAC rounding position to maintain proper rounding when different portions of the accumulator registers are read out to the XDB and YDB Scaling mode bits are cleared at the start of a long Interrupt Service Routine and during a hardware reset 11 10 11 Interrupt Mask Reflect the current Interrupt Priority Level IPL of the processor and indicate the IPL needed for an interrupt source to interrupt the processor The current IPL of the processor can be changed under software control The interrupt mask bits are set during hardware reset but not during software reset Exceptions
227. be accessed by the core and the EFCOP but not by the DMA controller Figure 3 5 Memory Switch On MSW 01 Cache Off 24 Bit Mode Motorola Memory Configuration For More Information On This Product Go to www freescale com 3 13 Freescale Semiconductor Inc Memory Maps Program X Data Y Data FFFFFF SFFFFFF External I O Internal O FFFFCO FFFF80 FFFF80 Internal I O External External FFF000 FFF000 FFFFFF Internal Reserved Internal Reserved Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 TN External External External 014000 Reserved 00C000 00C000 Internal Reserved Internal Internal Reserved Program RAM 79K 006000 006000 000400 Internal X data R d Internal Y data Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 01 1 0 79K 24K 24K Enabled 16M 0400 0000 5FFF 0000 5FFF 13FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 6 Memory Switch On MSW 01 Cache On 24 Bit Mode 3 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Program X Data Y Data FFFFFF FFFFFF FFFFFF External l O Internal I O FFFFC
228. be used to build time division multiplexed TDM networks In contrast the On Demand mode is for nonperiodic transfers of data This mode which offers a subset of the Motorola Serial Peripheral Interface SPI protocol can transfer data serially at high speed when the data become available Since each ESSI unit can be configured with one receiver and three transmitters the two units can be used together for surround sound applications which need two digital input channels and six digital output channels Motorola Enhanced Synchronous Serial Interface ESSI 7 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Enhancements 7 1 ESSI Enhancements The DSP56000 SSI is enhanced in the following ways to make the ESSI m Network enhancements Time slot mask registers receive and transmit End of frame interrupt Drive enable signal to be used with transmitter 0 GDB DDB RCLK RX SHIFT REG SRD STD SCO SC1 Interrupts Clock Frame Sync Generators and Control Logic SC2 SCK Figure 7 1 ESSI Block Diagram 7 2 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Data and Control Signals W Audio enhancements Three transmitters per ESSI for six channel surround sound W General enhancements Can trigger DMA interrupts receive or transmit Separate exception enable bit
229. bers are 24 bit buses The program data bus is also a 24 bit bus Figure 1 1 shows a block diagram of the DSP56311 I E Memory Expansion Area Triple Timer Enhanced Program ESSI Filter RAM P Co 32K x 24 or nt nterface processor Program X Data Y Data RAM 31K x 24 and RAM RAM SCI erface yum Instruction 48K x 24 48K x 24 Cache 1024 x 24 Peripheral Expansion Area x Address External 18 Generation Address Address External Bus 13 Interface and Cache Control Control Internal Data ab Switch Di M E LL L 2L Switch Data aj 1 1 o8 Ll JI Gen Program l Program le Program Data ALG JTAG Z erator Interrupt 1 1 Decode 1 Address 24 x 24 5656 bit MAC 1Controller Controller 1 Generaton Two 56 bit Acaumulatore E g DE 56 bit Barrel Shifter MODA IRQA MODB IRQB MODC IRQC MODD IRQD Figure1 1 DSP56311 Block Diagram PINIT NMI Note See Section 1 5 6 On Chip Memory on page 1 9 for details on memory size Motorola Overview 1 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DMA 1 8 DMA The DMA block has the following features Six DMA channels supporting internal and external accesses One two and three dimensional transfers including circular buffering End of block transfer interrupts Triggering from interrupt lines and all peripherals 1 9 Peripherals In addition
230. bit only when one or both of the following conditions is true the timer is disabled the TCSR TE bit is cleared The timer is in GPIO mode 9 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 7 4 TC 3 0 0 Timer Control Control the source of the timer clock the behavior of the TIO signal and the Timer mode of operation Section 9 3 Operating Modes on page 9 4 describes the timer operating modes in detail NOTE To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled that is when the TCSR TE bit is cleared NOTE If the clock is external the counter is incremented by the transitions on the TIO signal The external clock is internally synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 that is CLK 4 Bit Settings Mode Characteristics TC3 Tc2 rc1 rco Mode Mode TIO Clock Number Function Timer and 1 0 0 0 0 0 GPIO GPIO Internal 0 0 0 1 1 Timer pulse Output Internal 0 0 1 0 2 Timer toggle Output Internal 0 0 1 1 3 Event counter Input Exte
231. bled 0 L ze 1 HTRQ interrupt enabled 2 HDRQ Double Host Request 0 HREQ HTRQ HREQ 0 e HACK HRRQ HACK 1 HREQ HTRQ HTRQ HACK HRRQ HRRQ 3 HFO Host Flag 0 0 4 HF1 Host Flag 1 0 acd eres 5 HLEND Host Little Endian 0 Big Endian order 0 1 Little Endian order 7 INIT Initialize 1 Reset data paths according to 0 TREQ and RREQ SS OE ED MO a o a FC a sac LS ISR 0 RXDF Receive Data Register Full 0 Host Receive Register is empty 0 0 1 Host Receive Register is full 1 TXDE Transmit Data Register 1 Host Transmit Register is empty 1 1 Empty 0 Host Transmit Register is full 2 TRDY Transmitter Ready 1 transmit FIFO 6 deep is empty 1 1 transmit FIFO is not empty 3 HF2 Host Flag 2 0 e 4 HF3 Host Flag 3 0 7 HREQ Host Request 0 HREQ signal is deasserted 0 0 1 HREQ signal is asserted if enabled nt CVR 6 0 HV6 HVO Host Command Vector 32 CVR 7 HC Host Command 0 no host command pending 0 0 1 host command pending Pompeium M CE UI d H M Hr i E UU mr i ES RXH 7 0 Host Receive Data empty M L Register TXH 7 0 Host Transmit Data empty M L Register IVR 7 0 IV7 IVO Interrupt Register 68000 family vector register 0F Motorola Host Interface H108 6 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programm
232. ced Filter Coprocessor EFCOP 10 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes DMA channel 0 initialisation input to EFCOP movep movep movep movep movep request nop nop SRC_ADDRS x M_DSRO M_FDIR x M_DDRO SRC_COUNT x M DCOO 1 x M_DORO 94AA04 x M_DCRO Init DMA control reg to line mode FDIBE DMA source address points to the DATA bank Init DMA destination address Init DMA count to line mode DMA offset reg is 1 p TOO CK kk hehe hok REAR EER Kok ER ER ERE KEKE KER CK Ke EK ICK KK KK ERK CK eek ke KK Kee jclr 0 x M_DSTR jclr 1 x M_DSTR nop nop stop_label nop jmp stop_label org x SRC_ADDRS INCLUDE input asm org y FCBA_ADDRS INCLUDE 10 7 1 2 DMA Input Polling Output coefs asm The different stages of input polling are as follows 1 Setup Set the filter count register FCNT to the length of the filter coefficients 1 i e N 1 Set the data and coefficient base address pointers FDBA FCBA Set the operation mode FCSR 5 4 FOM 00 1 Set the initialization mode FCSR 7 FPRC 0 Set DMA registers DMA input as per channel 0 in Section 10 7 1 1 2 Initialization Enable EFCOP FCSR 0 FEN 1 Enable DMA input channel DCRO 23 DE 1 3 Processing Whenever the Inpu
233. ced Timer Compare Interrupt Enable Bit 2 1 Timer Compare has occurred 0 Compare Interrupts Disabled 1 Compare Interrupts Enabled Timer Overflow Flag Bit 20 0 1 has been written to TCSR TOF or timer Overflow interrupt serviced 1 Counter wraparound has occurred 23 22 21 20 19 18 17 16 15 14 13 12 11 k 3 crior k X k PE k k TRM Nv 108 1c2 re1 TCo 4 tcleE Tale TE Slol ojo 0 O 0 o i Timer Control Status Register x Reserved Program as 0 TCSRO FFFF8F Read Write TCSR1 FFFF8B Read Write TCSR2 FFFF87 Read Write Reset 000000 Figure B 23 Timer Control Status Register TCSR B 34 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Timers 23 22 21 20 19 18 17 16 15 1413 12 11 109 8 7 6 5 4 3 2 1 0 Timer Reload Value Timer Load Register TLRO FFFF8E Write Only TLR1 FFFF8A Write Only TLR2 FFFF86 Write Only Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O0 Value Compared to Counter Value Timer Compare Register TCPRO FFFF8D Read Write TCPR1 FFFF89 Read Write TCPR2 FFFF85 Read Write Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O Timer Count Value Timer Count Register TCRO FFFF8C Read Only TCR1 FFFF88 Read Only TCR2 FFFF84 Read Only Reset 000000 Figure B 24 Timer Load Co
234. chronized to the internal clock When asserted the chip is placed in the Reset state and the internal phase generator is reset The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably If RESET is deasserted synchronous to the internal clock exact start up timing is guaranteed allowing multiple processors to start synchronously and operate together in lock step When the RESET signal is deasserted the initial chip operating mode is latched from the MODA MODB MODC and MODD inputs The RESET signal must be asserted after power up MODA Input Input Mode Select A An active low Schmitt trigger input internally synchronized to the internal clock MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request A After reset this input becomes a IRQA Input level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If IRQA is asserted synchronous to the internal clock multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state If the processor is in the stop standby state and IRQA is asserted the processor will exit the stop state MODB Input Input Mode Select B An active low Schmitt trigger input internally synchronized to the internal clock MODA MODB
235. chronous modes 8 19 Asynchronous Multidrop mode 8 17 barrel shifter 1 6 BCHG 5 2 BCLR 5 2 bit 6 15 6 30 6 31 bit sticky 10 2 bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR AND JSSET 5 2 bootstrap 3 1 3 3 4 4 program 4 4 program options invoking 4 4 bootstrap code 8 7 Bootstrap mode 7 4 3 Boundary Scan Register BSR 4 25 BRCLR 5 2 break 8 16 BRSET 5 2 BSCLR 5 2 BSET 5 2 BSR see Boundary Scan Register BSSET 5 2 Motorola DSP56311 User s Manual BTST 5 2 bus address 2 3 data 2 3 external address 2 6 external data 2 6 internal 1 10 multiplexed 2 3 non multiplexed 2 3 C Capture Measurement mode 9 15 cellular base station 10 1 Central Processing Unit CPU 1 1 chip select signal 6 4 Chip Select logic 6 17 clock 1 5 2 5 Clock Generator CLKGEN 1 8 clock generator features 8 19 clock generator ESSI 7 11 Clock Out Divider bit COD 8 21 CMOS 1 5 COD bit 8 21 code compatible 1 5 real FIR filter with polling 10 25 codec systems 7 4 codecs 7 10 7 13 Command Vector Register CVR 6 27 Compare register TCPR 9 3 configure an ESSI exception 7 9 configure interrupt trigger 9 4 configuring a timer exception 9 4 control HIO8 operating mode 6 17 Control Register A 7 14 bit 18 Alignment Control bit ALC 7 16 see also ESSI Control Register B 7 18 see also ESSI counter overflow 9 25 counter preload operation 9 26 CRA see Control Register A CRB see Contro
236. cle is equal to SFFFFFF TCPR divided by SFFFFFF TLR 1 For a 50 percent duty cycle the value of TCPR is equal to SFFFFFF TLR 1 2 Note The value in TCPR must be greater than the value in TLR 9 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Period FFFFFF TLR 1 Duty cycle SF FFFFF TCPR g Ensure that TCPR gt TLR for correct functionalit Mode 7 internal clock TRM 1 2 5 N write preload first event M write compare TE Clock it PS CLK 2 or prescale CLK TLR P N N Counter TCR A 0 X TCPR gt lt if TCIE 1 0 N N 1 TCF Compare Interrupt TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width MENU mio Period Figure 9 16 Pulse Width Modulation Toggle Mode TRM 1 Motorola Triple Timer Module 9 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Period FFFFFF TLR 1 Duty cycle FFFFFF TCPR Mode 7 internal clock TRM 0 N write preload first event M write compare TE _ Clock a B CLK 2 or prescale CLK TLR N i Counter TCR Oo X N Ensure
237. clock in Synchronous mode The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4 These maximum rates are the same for internally or externally supplied clocks m The 16 x clock is necessary for Asynchronous modes to synchronize the SCI to the incoming data as shown in Figure 8 6 m For Asynchronous modes you must provide a 16 x clock if you want to use an external baud rate generator that is SCLK input Motorola Serial Communication Interface SCI 8 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model m For Asynchronous modes you can select either 1 x or 16 x for the output clock when using internal TX and RX clocks TCM 0 and RCM 0 m When SCKP is cleared the transmitted data on the TXD signal changes on the negative edge of the 1 x serial clock and is stable on the positive edge When SCKP is set the data changes on the positive edge and is stable on the negative edge m The received data on the RXD signal is sampled on the positive edge if SCKP 0 or on the negative edge if SCKP 1 of the 1 x serial clock W For Asynchronous mode the output clock is continuous m For Synchronous mode a 1 x clock is used for the output or input baud rate The maximum 1 x clock is the crystal frequency divided by 8 m ForSynchronous mode the clock is gated m For Synchronous mode the transmitt
238. d via the HIOS interface Do not issue a STOP command to the DSP via the HIO8 unless you provide some other mechanism to exit stop mode Table 6 13 Host Side Register Map Host Big Endian Little Endian Address HLEND 0 HLEND 1 0 ICR ICR Interface Control 1 CVR CVR Command Vector 2 ISR ISR Interface Status 3 IVR IVR Interrupt Vector 4 00000000 00000000 Unused 5 RXH TXH RXL TXL Receive Transmit 6 RXM TXM RXM TXM Bytes 7 RXL TXL RXH TXH 6 7 1 Interface Control Register ICR The ICR is an 8 bit read write control register by which the host processor controls the HIOS8 interrupts and flags The DSP core cannot access the ICR The ICR is a read write register which allows the use of bit manipulation instructions on control register bits Hardware and software reset clear the ICR bits 6 24 7 6 5 4 3 2 1 0 INIT HLEND HF1 HFO HDRQ TREQ RREQ Reserved bit read as 0 should be written with O for future compatibility Figure 6 14 Interface Control Register ICR DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Table 6 14 Freescale Semiconductor Inc Host Programmer s Model Interface Control Register ICR Bit Definitions Bit Number Bit Name Reset Value Description 7 INIT 0 Initialize The host processor uses the INIT bit to force initialization of the H108 hardware During initialization the HIO8 tr
239. data bidirectional tri state bus HADO HAD7 Input Host Address When HIO8 is programmed to interface a Output multiplexed host bus and the HI function is selected these signals are lines 0 7 of the address data bidirectional multiplexed tri state bus Port B 0 7 When the HIO8 is configured as GPIO through the PBO PB7 Input or host port control register HPCR these signals are individually Output programmed as inputs or outputs through the HIO8 data direction register HDDR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated Motorola Signals Connections 2 11 For More Information On This Product Go to www freescale com HI08 Freescale Semiconductor Inc Table 2 10 Host Interface Continued Signal Name Type State During Reset Signal Description HAO HAS HAS PB8 Input Input Input or Output Input Host Address Input 0 When the HIO8 is programmed to interface a nonmultiplexed host bus and the HI function is selected this signal is line 0 of the host address input bus Host Address Strobe When HIO8 is programmed to interface a multiplexed host bus and the HI function is selected this signal is the host address strobe HAS Schmitt trigger input The polarity of the address strobe is programmable but is configured active low HAS following reset Port B 8 When the HIO8 is configured as GPIO through the HPCR this signal is
240. ddresses Of TIMERI M TCSRI EQU SFFFF8B M TLRI EQU FFFF8A M TCPRI EQU SFFFF89 M TCRI EQU FFFF88 IIMERI Control Status Register IIMERI Load Reg TIMER1 Compare Register IIMERI Count Register Register Addresses Of TIMER2 M TCSR2 EQU FFFF87 M TLR2 EQU FFFF86 M TCPR2 EQU FFFF85 M TCR2 EQU FFFF84 M TPLR EQU FFFF83 M TPCR EQU FFFF82 IIMER2 Control Status Register IIMER2 Load Reg IIMER2 Compare Register TIMER2 Count Register TIMER Prescaler Load Register TIMER Prescaler Count Register Timer Control Status Register Bit Flags M TE EQU 0 M TOIE EQU 1 M TCIE EQU 2 M TC EQU F0 M TRM EQU 9 M DIR EQU 11 MDI EQU 12 M DO EQU 13 M PCE EQU 15 M TOF EQU 20 M TCF EQU 21 M INV EQU 8 Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Control Mask TCO TC3 Inverter Bit Timer Restart Mode Direction Bit Data Input Data Output Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag Timer Prescaler Register Bit Flags M PS EQU 600000 M PSO EQU M PS EQU Timer Control Bits M TCO M TCI M TC2 M TC3 Motorola EQU 4 EQU 5 EQU 6 EQU 7 Prescaler Source Mask 21 22 Timer Control 0 Timer Control 1 Timer Control 2 Timer Control 3 Bootstrap Program For More Information On This Product Go to www freescale com Internal I O Equates A 15 Freescale Semiconductor Inc
241. de only Each flag can be separately programmed The SCO flag is enabled when transmitter 1 is disabled TE1 0 The flag s direction is selected by the SCDO bit When SCDO is set SCO is configured as output When SCDO is cleared SCO is configured as input Similarly the SC1 flag is enabled when transmitter 2 is disabled TE2 0 and the SC1 signal is not configured as the transmitter 0 drive enabled signal Bit SSC1 0 The direction of SC1 is determined by the SCDI bit When SCD1 is set SC1 is an output flag When SCDI is cleared SC1 is an input flag When programmed as input flags the value of the SC 1 0 bits is latched at the same time as the first bit of the received data word is sampled Once the input is latched the signal on the input flag signal SCO and SC1 can change without affecting the input flag The value of SC 1 0 does not change until the first bit of the next data word is received When the received data word is latched by RX the latched values of SC 1 0 are latched by the SSISR IF 1 0 bits respectively and can be read by software When they are programmed as output flags the value of the SC 1 0 bits is taken from the value of the OF 1 0 bits The value of OF 1 0 is latched when the contents of TX transfer to the transmit shift register The value on SC 1 0 is stable from the time the first bit of the transmit data word transmits until the first bit of the next transmit data word
242. des ces ioa id LR ERR nanea 9 18 9 3 4 1 Watchdog Pulse Mode 9 uc sopa cS xy aero Saar eee Eadieee ny eee eea ES E 9 19 9 3 4 9 Watchdog Toggle Mode 10 2 2 0 cece eee eas 9 20 9 3 4 3 Reserve IMOUDS 4 aeu sire de toad end PEORES TRO ee ne EEE ONE 9 2 9 3 5 MMSODIESCT PPP 9 2 9 3 6 DMA Trigger uso pteend 9 tess E ORG IG eR ER bers bade da qe REA be eg 9 2 9 4 Triple Timer Module Programming Model 0 0 0 eee ee ee eee 9 21 9 4 1 Presealar Counlet 2 033062 4000402 RAS RET EREE RASAq AGGER a dee oes 9 21 942 Timer Prescalar Load Register IPLR osse o RE ERE RR 9 23 9 4 3 Timer Prescalar Count Register TPCR 0 0 00 e eee eee eee ene 9 24 9 4 4 Timer Control Status Register TCSR 0s cesses ce eee nbd Rye 9 24 9 4 5 dimer Load Revister TLR asd seta ideas ERO ERES AN ERES Ra Ss 9 29 9 4 6 Timer Compare Register TCPR 0 0 0 0 cece eee eee 9 30 9 4 7 Timer Count Register TCR daas sacoche me P RR ee REPRE 9 30 Chapter 10 Enhanced Filter Coprocessor EFCOP 10 1 BGatUt s 2 ps tado dre SORORE ws dieere EAE c tine oe pace EQ V de 10 1 10 2 Architecture Overview visa eas p REROREN OR ERU RA SG eee Soa ne aaa awe 10 3 10 21 BMIBIBICEL dO eoe ep ber Has m RICE I ERST Ae CqRRCTA P TEES eS RA 10 4 10 2 2 HPCOP Memory Banks o end oo wea RR sessed Meroe eed ee ERE Bac Era 10 4 10 2 3 Filter Multiplier and Accumulator FMAC 20 00 10 6 10 3 EFCOP Programming Model 6424042404 42824
243. do not change YO when running the double precision multiply algorithm If the Data ALU must be used in an interrupt service routine YO should be saved with other Data ALU registers to be used and restored before the interrupt routine terminates 13 SC Sixteen bit Compatibility mode Affects addressing functionality enabling full compatibility with object code written for the DSP56000 family When SC is set MOVE operations to from any of the following PCU registers clear the eight MSBs of the destination LA LC SP SSL SSH EP SZ VBA and SC If the source is either the SR or OMR then the eight MSBs of the destination are also cleared If the destination is either the SR or OMR then the eight MSBs of the destination are left unchanged To change the value of one of the eight MSBs of the SR or OMR clear SC SC also affects the contents of the Loop Counter Register If SC is cleared normal operation then a loop count value of zero causes the loop body to be skipped and a loop count value of FFFFFF causes the loop to execute the maximum number of 27 1 times If the SC bit is set a loop count value of zero causes the loop to execute 216 times and a loop count value of FFFFFF causes the loop to execute 218 1 times NOTE Due to pipelining a change in the SC bit takes effect only after three instruction cycles Insert three NOP instructions after the instruction that changes the value of this bit to ensure proper oper
244. dress line values of the host registers are taken from the internal latch If HMUX is cleared it indicates that the HIO8 is connected to a nonmultiplexed type of bus The values of the address lines are then taken from the HIO8 dedicated address signals 10 HASP 0 Host Address Strobe Polarity If HASP is cleared the host address strobe HAS signal is an active low input and the address on the host address data bus is sampled when the HAS signal is low If HASP is set HAS is an active high address strobe input and the address on the host address or data bus is sampled when the HAS signal is high 9 HDSP 0 Host Data Strobe Polarity If HDSP is cleared the data strobe signals are configured as active low inputs and data is transferred when the data strobe is low If HDSP is set the data strobe signals are configured as active high inputs and data is transferred when the data strobe is high The data strobe signals are either HDS by itself or both HRD and HWR together 8 HROD 0 Host Request Open Drain Controls the output drive of the host request signals In the single host request mode that is when HDRQ is cleared in ICR if HROD is cleared and host requests are enabled that is if HREN is set and HEN is set in the host port control register HPCR then the HREQ signal is always driven by the HIO8 If HROD is set and host requests are enabled the HREQ signal is an open drain output In the double host request mode that
245. ds at least three DSP phases inside each half of the serial clock Port C 3 The default configuration following reset is GPIO input PC3 When configured as PC3 signal direction is controlled through PRRO The signal can be configured as an ESSI signal SCKO through PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SRDO PC4 Input Output Input or Output Input Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SRDO is an input when data is being received Port C 4 The default configuration following reset is GPIO input PC4 When configured as PC4 signal direction is controlled through PRRO The signal can be configured as an ESSI signal SRDO through PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated STDO PC5 Input Output Input or Output Input Serial Transmit Data Transmits data from the serial transmit shift register STDO is an output when data is transmitted Port C 5 The default configuration following reset is GPIO input PC5 When configured as PC5 signal direction is controlled through PRRO The signal can be configured as an ESSI signal STDO through PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated 2 16 DSP56311 User s Manual Motorola For More
246. dware debugging support JTAG test access port TAP OnCE module Address trace mode reflects internal accesses at the external port Reduced power dissipation Very low power CMOS design Wait and stop low power standby modes Fully static design specified to operate at 0 Hz dc Optimized power management circuitry instruction dependent peripheral dependent and mode dependent DSP56300 Core Functional Blocks The functional blocks of the DSP56300 core are Data arithmetic logic unit ALU Address generation unit Program control unit PLL and clock oscillator JTAG TAP and OnCE module Memory In addition the DSP56311 provides a set of on chip peripherals discussed in Section 1 9 Peripherals on page 1 12 Motorola Overview 1 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56300 Core Functional Blocks 1 5 1 Data ALU The data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core These are the components of the data ALU m Fully pipelined 24 x 24 bit parallel multiplier accumulator m Bit field unit comprising a 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing Conditional ALU instructions Software controllable 24 bit 48 bit or 56 bit arithmetic support Four 24 bit or 48 bit input general purpose registers X1 X0 Y1 and YO Six data ALU register
247. e Network mode has a submode called On Demand mode Set the CRB MOD for Network mode and set the frame rate divider to 0 DC 00000 to select On Demand mode This submode does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The frame sync signal indicates the first time slot in the frame On Demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input For simplex operation Synchronous mode could be used however for full duplex operation Asynchronous mode must be used You can enable data transmission that is data driven by writing data into each TX Although the ESSI is double buffered only one word can be written to each TX even if the transmit shift register is empty The receive and transmit interrupts function normally using TDE and RDF however transmit underruns are impossible for On Demand transmission and are disabled This mode is useful for interfacing with CODECS requiring a continuous clock Note When the ESSI transmits data in On Demand mode that is MOD 1 in the CRB and DC 4 0 00000 in the CRA with WL 2 0 100 the transmission does not work properly To ensure correct operation do not use On Demand mode with the WL 2 0 2 100 32 bit word length mode 7 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
248. e B 27 Figure B 28 Figure B 29 Figure B 30 Motorola Freescale Semiconductor Inc Figures Timer Load Compare Count Registers TLR TCPR TCR B 36 Host Data Direction and Host Data Registers HDDR HDR B 37 Port C Registers PCRC PRRC PDBOO 25 540 co EE eREXREESEAEYXA B 38 Port D Registers PCRD PRRD PDRD 0 000 B 39 Port E Registers PCRE PRRE PDRE eee B 40 EFCOP Counter and Control Status Registers FCNT and FCSR B 41 EFCOP FACR FDBA FCBA and FDCH Registers B 42 XV For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figures Motorola DSP56311 User s Manual xvi For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tables Table 1 1 Table 1 2 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 5 1 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 Table 6 13 Table 6 14 Table 6 15 Table 6 16 Table 6 17 Table 6 18 Table 6 19 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Motorola High True Low True Signal Conventions 0 0 0 0 eese 1 3 DSP56311 Switch Memory Configuration 0 0 0 0 ce eee eee 1 9 DSP56311 Operating Modes s 2 226420044 Re REED LER D
249. e DSP56300 Family Manual especially the Expansion Port chapter for detailed information on using the external memory interface to access external program memory Note Program memory space at locations FFOOCO FFFFFF is reserved and should not be accessed 3 1 1 Internal Program Memory The default on chip program memory consists of a 24 bit wide high speed SRAM occupying the lowest 32K locations 0 7FFF in program memory space The on chip program RAM is organized in 32 banks with 1024 locations each You can make additional program memory available using the memory switch mode described in Section 3 1 2 Memory Switch Modes Program Memory Motorola Memory Configuration 3 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Program Memory Space 3 1 2 Memory Switch Modes Program Memory Memory switch mode allows reallocation of portions of X and Y data RAM as program RAM OMR 7 is the memory switch MS bit that controls this function as follows 3 2 When the MS bit is cleared program memory consists of the default 32K x 24 bit memory space described in the previous section In this default mode the lowest external program memory location is 8000 When the MS bit is set a portion of the higher locations of the internal X and Y data memory are switched to internal program memory The memory switch configuration MSW 1 0 bits also called M1 and MO in the OMR
250. e State Parity Error Flag Receive Data Register Full 0 No error 0 Receive Data Register Full 1 Incorrect Parity detected 1 Receive Data Register Empty Framing Error Flag Transmitter Data Register Empty 0 No error 0 Transmitter Data Register full 1 No Stop Bit detected 1 Transmitter Data Register empt Received Bit 8 Transmitter Empty 0 Data 0 Transmitter full 1 Address 1 Transmitter empty SCI Status Register SSR Address X FFFF93 Read Only Reset 000003 Reserved Program as 0 SCI Status Register SSR Clock Divider Bits CD11 CDO Clock Divider Bits CD11 CDO TX Clock RX Clock SCLK Pin Mode CD11 CDO lcyc Rate Internal Internal Output Synchronous Asynchronous 000 lcyc 1 Internal External Input Asynchronous only 001 lcyc 2 External Internal Input Asynchronous only 002 lcyc 3 External External Input Synchronous Asynchronous Transmitter Clock Mode Source Receiver Clock Mode Source 0 Internal clock for Transmitter 0 Internal clock for Receiver 1 External clock from SCLK 1 External clock from SCLK Clock Out Divider 0 Divide clock by 16 before feed to SCLK 1 Feed clock to directly to SCLK SCI Clock Prescaler 02 1 1 8 2 1 0 Reserved Program as 0 SCI Clock Control Register SCCR Figure B 20 SCI Status and Clock Control Registers SSR SCCR Motorola Programming Reference B 31 For More Informa
251. e clock at the CLKOUT pin When COD is set the CLKOUT output is pulled high When COD is cleared the CLKOUT pin provides a 50 percent duty cycle clock 18 PEN PLL Enable Enables PLL operation 17 PSTP PLL Stop State stop processing state Controls PLL and on chip crystal oscillator behavior during the 16 XTLD XTAL Disable oscillator Controls the on chip crystal oscillator XTAL output The XTLD bit is cleared during DSP56311 hardware reset so the XTAL output signal is active permitting normal operation of the crystal 15 XTLR 0 Crystal Range the DSP5631 1 this value is zero Controls the on chip crystal oscillator transconductance The XTLR bit is set to a predetermined value during hardware reset In 14 12 DF Division Factor as a power of two in the range from 2 to 27 Define the DF of the low power divider These bits specify the DF 11 0 MF 1 0 0 PLL Multiplication Factor reset and thus correspond to an MF of one Define the multiplication factor that is applied to the PLL input frequency The MF bits are cleared during DSP56311 hardware Motorola Core Configuration For More Information On This Product Go to www freescale com 4 21 Freescale Semiconductor Inc Device Identification Register IDR 4 7 Device Identification Register IDR The IDR is a read only factory programmed register that identifies DSP56300 family members It specifies the derivat
252. e com Freescale Semiconductor Inc Sixteen Bit Compatibility Mode Configuration Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition special care should be taken in relation to the interrupt vector routines CAUTION Pay special attention when executing a memory switch routine using the OnCE port Running the switch routine in trace mode for example can cause the switch to complete after the MS MSW bits change while the DSP is in Debug mode As a result subsequent instructions may be fetched according to the new memory configuration after the switch and thus may execute improperly 3 5 Sixteen Bit Compatibility Mode Configuration The sixteen bit compatibility SC mode allows the DSP56311 to use DSP56000 object code without change The SC bit Bit 13 in the SR is used to switch from the default 24 bit mode to this special 16 bit mode SC is cleared by reset You must set this bit to select the SC mode The address ranges described in the previous sections apply in the SC mode with regard to the reallocation of X and Y data memory to program memory in MS mode but the maximum addressing ranges are limited to FFFF and all data and program code are 16 bits wide 3 6 Memory Maps The following figures illustrate each of the memory space and RAM configurations defined by the settings of the MS and MSW 1 0 CE and SC bits The figures show the configurati
253. e handled properly outside P 0 3FF See the memory diagrams starting with Figure 3 2 Memory Switch Off Cache On 24 Bit Mode on page 3 10 3 1 4 Program Bootstrap ROM The program memory space occupying locations SFF0000 FFOOBF includes the internal bootstrap ROM This ROM contains the 192 word DSP56311 bootstrap program 3 2 X Data Memory Space The X data memory space consists of the following m Internal X data memory 48K by default down to 8K m Internal X I O space upper 128 locations m Optional off chip memory expansion as much as 128K in 16 bit mode or 256K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to the DSP56300 Family Manual especially Section 2 Expansion Port for details on using the external memory interface to access external X data memory Note The X memory space at locations SFF0000 SFFEFFF is reserved and should not be accessed 3 2 1 Internal X Data Memory The default on chip X data RAM is a 24 bit wide internal static memory occupying the lowest 48 K locations 0 BFFF in X memory space The on chip X data RAM is organized into 48 banks with 1024 locations each Available X data memory space is reduced and reallocated to program memory using the memory switch mode described in the next section Motorola Memory Configuration 3 3 For More Information On This Product Go to www freesca
254. e it HF1 is reflected in the HSR on the DSP side of the HIO8 HFO Host Flag 0 A general purpose flag for host to DSP communication The host processor can set or clear and the DSP56311 cannot change it HFO is reflected in the HSR on the DSP side of the HI08 HDRQ Double Host Request If cleared the HDRQ bit configures HREQ HTRQ and HACK HRRQ as HREQ and HACK respectively If HDRQ is set HREQ HTRQ is configured as HTRQ and HACK HRRQ is configured as HRRQ Motorola Host Interface H108 6 25 For More Information On This Product Go to www freescale com Host Programmer s Model Freescale Semiconductor Inc Table 6 14 Interface Control Register ICR Bit Definitions Continued Bit Number Bit Name Reset Value Description 1 TREQ 0 Transmit Request Enable Enables host requests via the host request HREQ or HTRQ signal when the transmit data register empty TXDE status bit in the ISR is set If TREQ is cleared TXDE interrupts are disabled If TREQ and TXDE are set the host request signal is asserted TREQ and RREQ modes HDRQ 0 TREQ RREQ HREQ Signal 0 0 No interrupts polling 0 1 RXDF request interrupt 1 0 TXDE request interrupt 1 1 RXDF and TXDE request interrupts TREQ and RREQ modes HDRQ 1 TREQ RREQ HTRQ Signal HRRQ Signal 0 0 No interrupts No interrupts polling polling 0 1 No interrupts RXDF request polling int
255. e serviced provide for the preceding DMA trigger to be serviced before the DMA channel receives the next trigger 9 4 Triple Timer Module Programming Model The timer programmer s model in Figure 9 20 shows the structure of the timer registers 9 4 1 Prescalar Counter The prescalar counter is a 21 bit counter that decrements on the rising edge of the prescalar input clock The counter is enabled when at least one of the three timers is enabled that is one or more of the timer enable bits are set and is using the prescalar output as its source that is one or more of the PCE bits are set Motorola Triple Timer Module 9 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Timer Prescalar Load TPLR FFFF83 Timer Prescalar Count TPLR FFFF82 23 22 21 20 19 18 17 16 Timer Control Status Register TCSR 14 13 12 11 TCSRO FFFF8F 15 10 9 8 Fe oo T or life reme TCSR2 FFFF87 7 6 5 4 3 2 1 0 fea espe pe lire roe T 23 0 Timer Load rr TLRO FFFF8E TLR1 FFFF8A TLR2 FFFF86 23 0 Timer Compare UU ee TCPRO FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 L0 E Register TCR TCRO FFFF8C TCR1 FFFF88 TCR2 FFFF84 OO Reserved bit Read as 0 Write with O for future compatibility Figure 9 20 Timer Module Programmer s Model 9 22 DSP56311 User s Manual Motorola For More Information On This Product Go to
256. e timer starts on the first high to low 1 to 0 signal transition on the TIO signal If the INV bit is cleared the timer starts on the first low to high that is 0 to 1 transition on the TIO signal When the first transition opposite in polarity to the INV bit setting occurs on the TIO signal the counter stops TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The value of the counter which measures the width of the TIO pulse is loaded into the TCR which can be read to determine the external signal pulse width If the TCSR TRM bit is set the counter is loaded with the TLR value on the first timer clock received following the next valid transition on the TIO input signal and the count resumes If TCSR TRM is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled Mode 4 internal clock TRM 1 first event N write preload M write compare TE Clock CLK 2 or prescale CLK TLR lt N i E Counter 0 bd N N n gt M 4 Next 0 to 1 edge on TIO loads TCR M counter and i process repeats TIO pin width being measured Interrupt Service ds TCR width TCF Compare Interrupt if TCIE 1 M oN die periods NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO stops the counter and loads TCR with the count Figure 9 11
257. ead 8 5 SCI Control Register SCR Bit Definitions sees 8 12 SCI Status Register SSR Bit Definitions 0 000 8 17 SCI Clock Control Register SCCR Bit Definitions 8 21 Port Control Register and Port Direction Register Bits 8 26 Timer Prescalar Load Register TPLR Bit Definitions 9 23 Timer Prescalar Count Register TPCR Bit Definitions 9 24 Timer Control Status Register TCSR Bit Definitions 9 24 Inverter INV Bit Operation sesleeeeee III 9 28 EFCOP Registers Accessible Through the PMB 4 10 4 EFCOP Registers and Base Addresses eese 10 6 Filter Count FCNT Register Bits lees 10 8 lud Bills PCT 10 9 EFCOP ALU Control Register FACR Bits 005 10 12 Decimation Channel Count Register FDCH Bits 10 14 EFCOP Interrupt Vectors A Los dee REESE RERRPA E ERE RASqUE REC RENS 10 14 BECOP DMA Request Sources is coss p zPRREEXE E REESE EIE Soe dedey x 10 14 EFCOP Operating Modes 0 cece ree 10 15 DMA Channel 0 Regisister Initialization 0 0000 e eee 10 23 DMA Channel 1 Register Initialization 0 0 00 000 e eee 10 24 Guide to Programming Sheets llle B 1 Internal X I O Memory Map 0 ee eee II B 2 Internal Y I O Memory Map iso sewsebpsERE ev EVPERe9 OPE
258. eceive Slot Mask A ESSIO FFFFB2 Read Write ESSI1 FFFFA2 Read Write Reset FFFF ESSI Receive Slot Mask B RSMBx ESSIO FFFFB1 Read Write ESSI1 FFFFA1 Read Write Reset FFFF Freescale Semiconductor Inc Programming Sheets ESSI Transmit Slot Mask 0 Ignore Time Slot 1 Active Time Slot ESSI Transmit Slot Mask A Reserved Program as 0 ESSI Transmit Slot Mask 0 Ignore Time Slot 1 Active Time Slot ESSI Transmit Slot Mask B Reserved Program as 0 ESSI Receive Slot Mask 0 Ignore Time Slot 1 Active Time Slot ESSI Receive Slot Mask A Reserved Program as 0 ESSI Receive Slot Mask 0 Ignore Time Slot 1 Active Time Slot ESSI Receive Slot Mask B x Reserved Program as 0 Figure B 18 ESSR Transmit and Receive Slot Mask Registers TSM RSM Motorola Programming Reference B 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Transmitter Enable 0 Transmitter Disable 1 Transmitter Enable Idle Line Interrupt Enable 0 Idle Line Interrupt Disabled 1 Idle Line Interrupt Enabled Receive Interrupt Enable 0 Receive Interrupt Disabled 1 Idle Line Interrupt Enabled Transmit Interrupt Enable 0 Transmit Interrupts Disabled 1 Transmit Interrupts Enabled Timer Interrupt Enable 0 Timer Interrupts Disabled 1 Timer Interrupts Enabled SCI Timer Interrupt Rate 0 32 1 31 SCI Clock Polari
259. ecutive ones depending on WDS giving you a convenient way to ensure that the line goes idle before a new message starts To force this separation of messages by the minimum idle line time we recommend the following sequence 1 Write the last byte of the first message to STX 2 Wait for TDRE to go high indicating the last byte has been transferred to the transmit shift register 3 Clear TE and set TE to queue an idle line preamble to follow immediately the transmission of the last character of the message including the stop bit 4 Write the first byte of the second message to STX In this sequence if the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission the transmit data line remains idle until STX is finally written RE Receiver Enable When RE is set the receiver is enabled When RE is cleared the receiver is disabled and data transfer from the receive shift register to the receive data register SRX is inhibited If RE is cleared while a character is being received the reception of the character completes before the receiver is disabled RE does not inhibit RDRF or receive interrupts Either a hardware RESET signal or a software RESET instruction clears RE WOMS Wired OR Mode Select When WOMS is set the SCI TXD driver is programmed to function as an open drain output and can be wired together with other TXD signals in an appropriate bus
260. egister 4 21 PLL control register PCTL 4 21 PMB 10 4 pointers EFCOP memory bank base address 10 2 polling 5 3 Port A 2 6 Port B 2 3 2 13 5 6 Port C 2 3 2 15 5 7 Port C and D control registers 7 36 Port C Control Register PCRC 7 36 Port C Data Register PDRC 7 38 Port C Direction Register PRRC 7 37 Port Control Register 7 23 Port D 2 3 2 17 5 8 Port D Control Register PCRD 7 36 Port D Data Register PDRD 7 38 Port D Direction Register PRRD 7 37 Port E 5 8 Port E Control Register PCRE 8 25 Port E Data Register PDRE 8 26 Port E Direction Register PRRE 8 26 position independent code 1 7 power 2 4 low 1 5 management 1 5 standby modes 1 5 prescale divider ESSI 7 17 Prescaler Counter 9 21 Prescaler Load Register TPLR 9 3 Program Address Bus PAB 1 10 Program Address Generator PAG 1 7 Program Control Unit PCU 1 7 Program Counter register PC 1 8 Program Data Bus PDB 1 10 Program Decode Controller PDC 1 7 Program Interrupt Controller PIC 1 7 Program Memory Expansion Bus 1 10 Program RAM 3 1 Program ROM bootstrap 3 1 programming model EFCOP 10 6 ESSI 7 14 SCI 8 9 PRRC register 7 37 PRRD register 7 37 PRRE register 8 26 ESSI Index 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CRA 7 3 Pulse width modulation mode Mode 7 9 11 R R8 bit 8 17 RAM Program 3 1 RCM bit 8 21 RE bit 8 14 readi
261. ent sample to each filter If FMLC is cleared multichannel mode is disabled and the EFCOP operates in single filter mode NOTE To ensure proper operation never change the FMLC bit unless the EFCOP is in individual reset state that is FEN 0 FOM Filter Operation Mode This pair of read write control bits defines one of four operation modes if the FIR filter is selected that is FLT is cleared FOM 00 Mode 0 Real FIR filter FOM 01 Mode 1 Full complex FIR filter FOM 10 Mode 2 Complex FIR filter with alternate real and imaginary outputs FOM 11 Mode 3 Magnitude NOTE To ensure proper operation never change the FOM bits unless the EFCOP is in the individual reset state that is FEN 0 Motorola DSP56311 User s Manual 10 10 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model Table 10 4 FCSR Bits Continued Bit Number Reset Bit Name Value Description FUPD 0 Filter Update This read write control status bit enables the EFCOP to start a single coefficient update session Upon completion of the session the FUPD bit is automatically cleared FUPD is automatically set when the EFCOP is in adaptive mode that is FADP 1 FADP 0 Filter Adaptive FADP Mode This read write control bit enables adaptive mode Adaptive mode is an efficient way to implement a LMS type filter and there
262. er Figure 3 12 Memory Switch Off Cache On 16 Bit Mode 3 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data SEPPER PEPP External I O Internal I O FFCO FF80 Internal I O FFFF FF80 Internal Program RAM oan C000 C000 Reserved Reserved 4000 4000 Internal X data Internal Y data 0000 0000 RAM 16K 0000 RAM 16K Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 00 0 1 64K 16K 16K None 64K 0000 FFFF 0000 3FFF 0000 3FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 13 Memory Switch On MSW 00 Cache Off 16 Bit Mode Motorola Memory Configuration 3 21 For More Information On This Product Go to www freescale com Memory Maps FFFF External Internal Program RAM 63K C000 Reserved 4000 0400 Internal X data 0000 0000 RAM 16K Freescale Semiconductor Inc Program FFFF FF80 X Data Internal I O Y Data FFFF External I O FFCO FF80 Internal I O External C000 4000 0000 Reserved Internal Y data RAM 16K Bit Settings Memory Configuration
263. er and receiver are synchronous with each other Select 8 or 9 bit Words M Idle Line 0 1 2 3 4 5 6 7 8 RX TX Data SSFTD 0 Start Stop Start x1 Clock SCKP 0 Figure 8 6 16 x Serial Clock The SCI clock determines the data transmission rate and can also establish a periodic interrupt that can act as an event timer or be used in any other timing function Bits CD11 CDO SCP and SCR STIR work together to determine the time base If SCR TMIE 1 when the periodic time out occurs the SCI timer interrupt is recognized and pending The SCI timer interrupt is automatically cleared when the interrupt is serviced This interrupt occurs every time the periodic timer times out 8 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 4 SCI Clock Control Register SCCR Bit Definitions Bit Number Bit Name Reset Value Description 23 16 0 Reserved Set to 0 for future compatibility 15 TCM 0 Transmit Clock Source Selects whether an internal or external clock is used for the transmitter If TOM is cleared the internal clock is used If TCM is set the external clock from the SCLK signal is used 14 RCM Receive Clock Mode Source Selects whether an internal or external clock is used for the receiver If RCM is cleared the internal clock is used If RCM is set the ext
264. erencing the OMR i e ANDI ORI and other instructions such as MOVEC that specify OMR as a destination The SCS byte is referenced implicitly by some instructions such as DO JSR and RTI or directly by the MOVEC instruction During processor reset the chip operating mode bits MD MC MB and MA are loaded from the external mode select pins MODD MODC MODB and MODA respectively Table 4 6 defines the DSP56311 OMR bits Table 4 6 Operating Mode Register OMR Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Set to 0 for future compatibility 22 21 MSW 1 0 0 Memory Switch Configuration Reallocate portions of X and Y data RAM as program RAM Memory Switch Mode is enabled when the Memory Switch bit OMR 7 is set The Memory Switch Configuration MSW bits determine what portion of the higher locations of internal X and Y data memory are switched to internal program memory when the Memory Switch Mode is enabled Motorola Core Configuration 4 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Mode Register OMR Table 4 6 Operating Mode Register OMR Bit Definitions Continued Bit Number Bit Name Reset Value Description 20 SEN 0 Stack Extension Enable Enables disables the stack extension in data memory If the SEN bit is set the extension is enabled Hardware reset clears this bit so the default o
265. eripherals During individual reset internal DMA accesses to the data registers of the SCI are not valid and the data is unknown W Stop processing state reset that is the STOP instruction Executing the STOP instruction halts operation of the SCI until the DSP is restarted causing the SCI Status Register SSR to be reset No other SCI registers are affected by the STOP instruction SCI After Reset Table 8 1 illustrates how each type of reset affects each register in the SCI Table 8 1 SCI Registers After Reset Reset Type Register Bit Mnemonic Bit Number HW Reset SW Reset IR Reset ST Reset REIE 16 0 0 SCKP 15 0 0 STIR 14 0 0 TMIE 13 0 0 TIE 12 0 0 RIE 11 0 0 ILIE 10 0 0 TE 9 0 0 SCR RE 8 0 0 WOMS 7 0 0 RWU 6 0 0 WAKE 5 0 0 SBK 4 0 0 SSFTD 3 0 0 WDS 2 0 2 0 0 0 SSR R8 7 0 0 0 0 FE 6 0 0 0 0 PE 5 0 0 0 0 OR 4 0 0 0 0 IDLE 3 0 0 0 0 RDRF 2 0 0 0 0 TDRE 1 1 1 1 1 TRNE 0 1 1 1 1 TCM 15 0 0 RCM 14 0 0 SCCR SCP 13 0 0 COD 12 0 0 CD 11 0 11 0 0 0 SRX SRX 23 0 23 16 15 8 7 0 STX STX 23 0 23 0 Motorola Serial Communication Interface SCI 8 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Initiali
266. ernal X data space accesses Bus Program Memory Enable Bit 3 0 Disable AA pin and logic during external program space accesses 1 Enable AA pin and logic during external program space accesses Bus Address Attribute Polarity Bit 2 0 AA RAS signal is active low 1 AA RAS signal is active high Bus Access Type Bits 1 0 BAT 1 0 Encoding 00 Reserved 01 SRAM access 10 DRAM access 11 Reserved external address in order to decide whether to assert the AA pin 22 21 20 Ei 1 10 2 1 Reserved Program as 0 B 14 Address Attribute Registers AAR3 AARO Reset 000000 BN 0 Figure B 3 Address Attribute Registers AAR3 AARO DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Programming Sheets Central Processor NOTE All BCR bits are read write control bits Bus State Bit 21 0 DSP is not bus master 1 DSP is bus master Default Area Wait Control Bits 20 16 Area 3 Wait Control Bits 15 13 Area 2 Wait Control Bits 12 10 Area 1 Wait Control Bits 9 5 Area 0 Wait Control Bits 4 0 These read write control bits define the number of wait states inserted into each external SRAM access to the designated area The value of these bits should not be programmed as zero Number of wait states BDFW
267. ernal clock from the SCLK signal is used TCM RCM TX RX SCLK Mode Clock Clock Signal 0 0 Internal Internal Output Synchronous asynchronous 0 1 Internal External Input Asynchronous only 1 0 External Internal Input Asynchronous only 1 1 External External Input Synchronous asynchronous 13 SCP Clock Prescaler Selects a divide by 1 SCP is cleared or divide by 8 SCP is set prescaler for the clock divider The output of the prescaler is further divided by 2 to form the SCI clock 12 COD Clock Out Divider The clock output divider is controlled by COD and the SCI mode If the SCI mode is synchronous the output divider is fixed at divide by 2 If the SCI mode is asynchronous either B if COD is cleared and SCLK is an output that is TCM and RCM are both cleared then the SCI clock is divided by 16 before being output to the SCLK signal Thus the SCLK output is a 1 X clock E if COD is set and SCLK is an output the SCI clock is fed directly out to the SCLK signal Thus the SCLK output is a 16 X baud clock 11 0 CD 11 0 Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator A divide ratio from 1 to 4096 CD 11 0 000 to FFF can be selected Motorola Serial Communication Interface SCI 8 21 For More Information On This Product Go to www freescale com Freescale Semiconductor
268. errupt 1 0 TXDE request No interrupts polling interrupt 1 1 TXDE request RXDF request interrupt interrupt 0 RREQ 0 Receive Request Enable Controls the HREQ signal for host receive data transfers RREQ enables host requests via the host request HREQ or HRRQ signal when the receive data register full RXDF status bit in the ISR is set If RREQ is cleared RXDF interrupts are disabled If RREQ and RXDF are set the host request signal HREQ or HRRQ is asserted 6 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Host Programmer s Model 6 7 2 Command Vector Register CVR The host processor uses the CVR to cause the DSP56311 to execute an interrupt The host command feature is independent of any of the data transfer mechanisms in the HIOS It can cause execution of any of the 128 possible interrupt routines in the DSP core Hardware software individual and stop resets clear the CVR bits 7 6 5 4 3 2 1 0 HC HV6 HV5 HV4 HV3 HV2 HV1 HVO Figure 6 15 Command Vector Register CVR Table 6 15 Command Vector Register CVR Bit Definitions Bit Number Bit Name Reset Value Description T HC 0 Host Command The host processor uses the HC bit to handshake the execution of host command interrupts Normally the host processor sets HC to request a host command interrupt from the DSP5
269. escale Semiconductor Inc HIO8 Interrupt and Mode Control Continued Signal Name Type State During Reset Signal Description MODD IRQD Input Input Input Mode Select D An active low Schmitt trigger input internally synchronized to the internal clock MODA MODB MODO and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request D After reset this input becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If IRQD is asserted synchronous to the internal clock multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state If the processor is in the stop standby state and IRQD is asserted the processor will exit the stop state 2 MHI08 The HIO08 provides a fast parallel data to 8 bit port that connects directly to the host bus The HIO08 supports a variety of standard buses and can directly connect to a number of industry standard microcomputers microprocessors DSPs and DMA hardware Table 2 10 Host Interface State During ae Signal Name Type Reset Signal Description H0 H7 Input Tri stated Host Data When the HI08 is programmed to interface a Output nonmultiplexed host bus and the HI function is selected these signals are lines 0 7 of the
270. escale Semiconductor Inc Programming Sheets Central Processor Chip Operating Mode Bits 3 0 Refer to the operating modes table in Chapter 4 Asynchronous Bus Arbitration Enable Bit 13 0 Synchronization disabled External Bus Disable Bit 4 1 Synchronization enabled 0 Enables external bus 1 Disables external bus Address Attribute Priority Disable Bit 14 Stop Delay Mode Bit 6 0 Priority mechanism enabled 0 Delay is 128K clock cycles 1 Priority mechanism disabled 1 Delay is 16 clock cycless Stack Extension X Y Select Bit 16 Memory Switch Mode Bit 7 0 Mapped to X memory 0 Memory switching disabled 1 Mapped to Y memory 1 Memory switching enabled Stack Extension Underflow Flag Bit 17 Core DMA Priority Bits 9 8 0 No stack underflow i 1 Stack underflow CPD 1 0 Description 00 Compare SR CP to Stack Extension Overflow Flag Bit 18 active DMA channel 0 No stack overflow priority 1 Stack overflow DMA has higher priority than core Stack Extension Wrap Flag Bit 19 DMA has same 0 No stack extension wrap priority as core 1 Stack extension wrap sticky bit DMA has lower priority than core Stack Extension Enable Bit 20 0 Stack extension disabled 1 Stack extension enabled Cache Burst Mode Enable Bit 10 0 Burst Mode disabled 1 Burst Mode enabled Memory Switch Configuration Bits 22 21 MSWT 1 0 Program Memory TA
271. eserved VBA 5E 0 2 Reserved VBA 60 0 2 Host receive data full VBA 62 0 2 Host transmit data empty VBA 64 0 2 Host command default VBA 66 0 2 Reserved VBA 68 0 2 EFCOP data input buffer empty VBA 6A 0 2 EFCOP data output buffer full VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA FE 0 2 Reserved 4 6 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Interrupt Sources and Priorities 4 3 2 Interrupt Priority Levels There are two interrupt priority registers in the DSP56311 The IPR C Figure 4 1 is dedicated to DSP56300 core interrupt sources and IPR P Figure 4 2 is dedicated to DSP56311 peripheral interrupt sources 22 21 2 0 19 18 17 1 6 15 14 13 12 23 DMAO IPL DMA1 IPL DMA2 IPL DMAS3 IPL DMA4 IPL DMAS IPL 11 10 9 8 7 6 5 4 3 2 1 0 EN IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD iPL IRQD mode Figure 4 1 Interrupt Priority Register C IPR C X FFFFFF 23 22 21 20 19 18 17 16 15 14 13 12 reserved 11 10 9 8 7 6 5 4 3 2 1 0 HIO8 IPL ESSIO IPL ESSI1 IPL SCIIPL TRIPLE TIMER IPL EFCOP IPL Figure 4 2 Interrupt Priority Register P IPR P X SFFFFFE Motorola Core Configuration 4 7 For More Information On This Product Go to www freescale com
272. eset state FEN 0 otherwise improper operation may result The number stored in FCHL is used by the EFCOP address generation logic to generate the correct address for the FDM bank and for the FCM bank in multichannel mode When the EFCOP enable bit FEN is cleared the EFCOP is in individual reset state In this state the EFCOP is inactive and the contents of FDCH register are preserved 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDOMS FDCM2 FDCM1 FDCMO FCHL5 FCHL4 FCHL3 FCHL2 FCHL1 FCHLO Reserved bit read as 0 should be written with O for future compatibility Figure 10 6 Decimation Channel Count Register FDCH Motorola Enhanced Filter Coprocessor EFCOP 10 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Table 10 6 Decimation Channel Count Register FDCH Bits Bit Bit Reset Number Name Value Description 23 12 0 These bits are reserved and unused They are read as 0 and should be written with O for future compatibility 11 8 FDCM 0 Filter Decimation These read write control bits select the decimation function There are 16 decimation factor options from 1 to 16 NOTE To ensure proper operation never change the FDCM bits unless the EFCOP is in the individual reset state FEN 0 7 6 0 Reserved and unused They are read as 0 and sho
273. essing FIR filter type and IIR filter type processing Various sub options are available with each filter type as described in the following sections 10 5 1 FIR Filter Type To select the FIR filter type clear FCSR FLT and perform the processing shown in Figure 10 7 based on the equation shown below The EFCOP takes an input x n from N w n gt Bx n i i 0 the FDIR saves the input while shifting the previous inputs down in the FDM multiplies each input in the FDM by the corresponding coefficient B stored in the FCM accumulates the multiplication results and places accumulation result w n in the FDOR This is done for each sample input to the FDIR FDM FCM FDIR gt xn Cone Bo FDOR x n 1 Come B x n 2 Cone Bo Y pm HX By Figure 10 7 FIR Filter Type Processing Motorola DSP56311 User s Manual 10 16 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation Summary There are four operating modes available with the FIR filter type real complex alternating complex and magnitude mode 10 5 1 1 Real Mode Real mode performs FIR type filtering with real data and is selected by clearing both FOM bits in the FCSR One sample the real input is written to the FDIR and the EFCOP processes the data Then one sample the real output is read from the FDOR Two other options are available wi
274. f the INV bit is set the pulse polarity is high logical 1 If INV is cleared the pulse polarity is low logical 0 The counter reloads when the TLR is written with a new value while the TCSR TE bit is set In Mode 9 internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the hardware RESET signal is asserted This convention ensures that a valid RESET signal is generated when the TIO signal resets the DSP56311 Mode 9 internal clock TRM 0 Software does not reset watchdog timer watchdog times out first event N write preload M write compare TE crock PL oF Ley LII CLK 2 or prescale CLK TRM 1 is not useful for watchdog function TLR N Counter TCR 0 N N 1 M M 1 0 1 TCPR M TCF Compare Interrupt if TCIE 1 TOF Overflow Interrupt if TOIE 1 float pulse width TIO pin INV 0 low timer clock period foa 1 float high TIO pin INV 1 TIO can connect to the RESET pin internal hardware preserves the TIO value and direction for an additional 2 5 clocks to ensure a reset of valid length Figure 9 18 Watchdog Pulse Mode Motorola Triple Timer Module 9 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 4 2 Watchdog Toggle Mode 10 Bit Settings Mode Characteristics TC3 TC2 TC
275. f the TE1 bit does not affect the generation of frame sync or output flags Motorola Enhanced Synchronous Serial Interface ESSI 7 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 14 TE2 0 Transmit 2 Enable Enables the transfer of data from TX2 to Transmit Shift Register 2 TE2 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode When TE2 is set and a frame sync is detected transmitter 2 is enabled for that frame When TE2 is cleared transmitter 2 is disabled after completing transmission of data currently in the ESSI transmit shift register Any data present in TX2 is not transmitted If TE2 is cleared data can be written to TX2 the TDE bit is cleared but data is not transferred to transmit shift register 2 If the TE2 bit is kept cleared until the start of the next frame it causes the SC1 signal to act as a serial I O flag from the start of the frame in both Normal mode and Network mode The transmit enable sequence in On Demand mode can be the same as in Normal mode or the TE2 bit can be left enabled NOTE The setting of the TE2 bit does not affect the generation of frame sync or output flags 13 MOD 0 Mode Select Selects the operational mode of the ESSI as i
276. factor of 32 Either a hardware RESET signal or a software RESET instruction clears this bit To ensure proper operation of the timer STIR must not be changed during timer operation that is if TMIE 1 8 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 13 TMIE 0 Timer Interrupt Enable Enables disables the SCI timer interrupt If TMIE is set timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock register The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller This feature allows DSP programmers to use the SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use if external clocks are used for the SCI or if periodic interrupts are needed at the SCI baud rate The SCI internal clock is divided by 16 to match the 1 x SCI baud rate for timer interrupt generation This timer does not require that any SCI signals be configured for SCI use to operate Either a hardware RESET signal or a software RESET instruction clears TMIE 12 TIE SCI Transmit Interrupt Enable Enables disables the SCI transmit data interrupt If TIE is cleared transmit d
277. ficients Mode This read write control bit is valid only when the EFCOP is operating in multichannel mode that is FMLC is set When FSCO is set the EFCOP uses the coefficients in the same memory area that is the same coefficients to implement the filter for each channel This mode is used when several channels are filtered through the same filter When the FSCO bit is cleared the EFCOP filter coefficients are stored sequentially in memory for each channel NOTE To ensure proper operation never change the FSCO bit unless the EFCOP is in individual reset state that is FEN 0 FPRC Filter Processing FPRC State Initialization Mode This read write control bit defines the EFCOP processing initialization mode When this bit is cleared the EFCOP starts processing after a state initialization The EFCOP machine starts computing once the FDM bank contains N input samples for an N tap filter When this bit is set the EFCOP starts processing with no state initialization The EFCOP machine starts computing as soon as the first data sample is available in the input buffer NOTE To ensure proper operation never change the FPRC bit unless the EFCOP is in individual reset state that is FEN 0 FMLC Filter Multichannel FMLC Mode This read write control bit enables multichannel mode allowing the EFCOP to process several filters defined by FCHL 5 0 bits in FDCH register concurrently by sequentially entering a differ
278. fore it is used when the EFCOP operates in FIR filter mode FLT 0 In adaptive mode processing of every input data sample consists of FIR processing followed by a coefficient update When FADP is set the EFCOP completes the FIR processing on the current data sample and immediately starts the coefficient update assuming that a K constant value is written to the FKIR If no value is written to the FKIR for the current data sample the EFCOP halts processing until the K constant is written to the FKIR During the coefficient update the FUPD bit is automatically set to indicate an update session After completion of the update the EFCOP starts processing the next data sample FLT 0 Filter FLT Type This read write control bit selects one of two available filter types FLT 0 FIR filter FLT 1 IIR filter NOTE To ensure proper operation never change the FLT bit unless the EFCOP is in the individual reset state that is FEN 0 FEN 0 Filter Enable This read write control bit enables the operation of the EFCOP When FEN is cleared operation is disabled and the EFCOP is in the individual reset state In the individual reset state the EFCOP is inactive internal logic and status bits assume the same state as that produced by a hardware RESET signal or a software RESET instruction the contents of the FCNT FDBA and FCBA registers are preserved and the control bits in FCSR and FACR remain unchanged 10
279. gister FDCH NOTE The EFCOP registers are mapped onto Y data memory space 10 3 1 Filter Data Input Register FDIR The FDIR is a 4 word deep 24 bit wide FIFO for DSP to EFCOP data transfers Up to four data samples can be written into the FDIR at the same address Data from the FDIR is transferred to the FDM for filter processing For proper operation write data to the FDIR only if the FDIBE status bit is set indicating that the FIFO is empty A write to the FDIR clears the FDIBE bit Data transfers can be triggered by an interrupt request for core transfers or a DMA request for DMA transfers The FDIR is accessible for writes by the DSP56300 core and the DMA controller 10 3 2 Filter Data Output Register FDOR The FDOR is a 24 bit read only register for EFCOP to DSP data transfers The result of the filter processing is transferred from the FMAC to the FDOR For proper operation read data from the FDOR only if the FDOBF status bit is set indicating that the FDOR contains data A read from the FDOR clears the FDOBE bit Data transfers can be triggered by an interrupt request for core transfers or a DMA request DMA transfers The FDOR is accessible for reads by the DSP56300 core and the DMA controller 10 3 3 Filter K Constant Input Register FKIR The Filter K Constant Input Register FKIR is a 24 bit write only register for DSP to EFCOP data transfers in adaptive mode where the value stored in FKIR represents the weight
280. gister STX are empty indicating that there is no data in the transmitter When TRNE is set data written to one of the three STX locations or to the transmit data address register STXA is transferred to the transmit shift register and is the first data transmitted TRNE is cleared when a write into STX or STXA clears TDRE or when an idle preamble or break is transmitted When set TRNE indicates that the transmitter is empty therefore the data written to STX or STXA is transmitted next That is there is no word in the transmit shift register being transmitted This procedure is useful when initiating the transfer of a message that is a string of characters 8 6 3 SCI Clock Control Register SCCR The SCCR is a 24 bit read write register that controls the selection of clock modes and baud rates for the transmit and receive sections of the SCI interface The SCCR is cleared by a hardware RESET signal 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TCM RCM SCP COD CD11 CD10 CD9 CD8 7 6 5 4 3 2 1 0 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CDO Reserved Read as 0 Write with 0 for future compatibility Figure 8 5 SCI Clock Control Register SCCR The basic features of the clock generator as shown in Figure 8 6 and Figure 8 7 follow m The SCI logic always uses a 16 x internal clock in Asynchronous mode and always uses a 2 x internal
281. gister 1 memory space Note Setting the DCOO and DCO1 must be considered carefully These registers must be loaded with one less than the number of items to be transferred Also the following equality must hold DCO1 input length filter length 6 Initialization Enable DMA channel 1 output DCR1 23 DE 1 Enable EFCOP FCSR 0 FEN 1 Enable DMA channel 0 input DCRO 23 DE 1 7 Processing Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDIR Compute F n The result is stored in FDOR and this triggers the DMA for an output data transfer Motorola DSP56311 User s Manual 10 24 For More Information On This Product Go to www freescale com Note Memory FDM Freescale Semiconductor Inc Examples of Use in Different Modes The filter coefficients are stored in reverse order as Figure 10 9 shows Data Bank p ee EET Output Data Stream Fo IO S o RS F4 RS Coefficient Memory Bank FCM Figure 10 9 Real FIR Filter Data stream Example 10 1 INCLUD E ioequ asm Real FIR Filter Using DMA Input DMA Output BUR RASOR ORDER RINT AE OR ARH EORR SI ANS ASUNT AIRE SUR OR ACTS UR AI NUNC ISO AO AE LACS TDN MR A MRT RTS E equates Ip po RR Ae A PEI RA AES SUN ee AeA IN EORORONUNUAUR IRAN EO ee I OUR IR He IS ASCARIS UICE Ae SR LCR I IN
282. gisters occupying four 24 bit words in the X data memory space The three timers are identical in structure and function Either standard polled or interrupt programming techniques can be used to service the timers A single generic timer is discussed in this chapter Motorola Triple Timer Module 9 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation The timer includes a 24 bit counter a 24 bit read write Timer Control and Status Register TCSR a 24 bit read only Timer Count Register TCR a 24 bit write only Timer Load Register TLR a 24 bit read write Timer Compare Register TCPR and logic for clock selection and interrupt DMA trigger generation GDB 24 24 24 TPCR 24 Timer Prescalar Count Register c Timer Prescalar Load Register Timer 1 Figure 9 1 Triple Timer Module Block Diagram The timer mode is controlled by the TC 3 0 bits of the Timer Control Status Register TCSR For a listing of the timer modes and descriptions of their operations see Section 9 3 Operating Modes on page 9 4 24 ES Counter CLK 2 TIOO TIO1 TIO2 9 2 Operation This section discusses timer basics reset state initialization and exceptions 9 2 1 Timer After Reset A hardware RESET signal or software RESET instruction clears the Timer Control Register thus configuring the timer as GPIO A timer is active only if TCSR TE is set 9 2 DSP56311 User s Ma
283. gnals multiplexed with the GPIO signals All Port C and D signals have keepers 4 Port E signals are the SCI port signals multiplexed with the GPIO signals All Port C signals have keepers 5 Alltimer signals have keepers Motorola Signals Connections 2 1 For More Information On This Product Go to www freescale com Note 2 2 Freescale Semiconductor Inc The Clock Output CLKOUT is not functional in the DSP56311 The CLKOUT output pin provides a 50 percent duty cycle output clock synchronized to the internal processor clock when the Phase Lock Loop PLL is enabled and locked At 150 MHz and above CLKOUT produces a low amplitude waveform that is not usable externally by other devices Several alternatives to using CLKOUT exist such as enabling bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit ABE in the Operating Mode register When set the ABE bit eliminates the setup and hold time requirements with respect to CLKOUT for BB and BG DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com VccP VccaL VocaH Voca Vccp Vccc VccH Vccs GNDp GNDpy GNDg GND GNDp GNDc GND GNDs EXTAL XTAL PCAP During After Reset Reset PINIT NMI A0 A17 D0 D23 AAO AA3 RASO RAS3 RD WR JA BR BG _BB CAS NOTES 1 DN PR Olo sp 18 24 Freescale Semiconductor Inc DSP56311 Power Inputs PLL Core Logic yo Address Bus
284. hange the PS 1 0 bits only when the prescalar counter is disabled Disable the prescalar counter by clearing TCSR TE of each of three timers PS1 PSO Prescalar Clock Source 0 0 Internal CLK 2 0 1 TIOO 1 0 TIO1 1 1 TIO2 20 0 PL 20 0 Prescalar Preload Value Contains the prescalar preload value which is loaded into the prescalar counter when the counter value reaches 0 or the counter switches state from disabled to enabled If PL 20 0 N then the prescalar counts N 1 source clock cycles before generating a prescalar clock pulse Therefore the prescalar divide factor preload value 1 Motorola Triple Timer Module 9 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model 9 4 3 Timer Prescalar Count Register TPCR The TPCR is a read only register that reflects the current value in the prescalar counter 23 22 21 20 19 18 17 16 15 14 13 12 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO Reserved bit read as 0 should be written with O for future compatibility Figure 9 22 Timer Prescalar Count
285. he bootstrap program is factory programmed into an internal 192 word by 24 bit bootstrap ROM at locations FFO000 to SFFOOBF of P memory This program can load program RAM segment from the HI08 host port When any of the modes in the preceding table are used the core begins executing the bootstrap program and configures the HIO8 based on the OMR mode bits The bootstrap program then expects the following data sequence when the user program is downloaded from the HI08 1 Three bytes least significant byte first indicating the number of 24 bit program words to be loaded 6 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model 2 Three bytes least significant byte first indicating the 24 bit starting address in P memory to load the user s program 3 The user s program three bytes least significant byte first for each program word Once the bootstrap program finishes loading the specified number of words it jumps to the specified starting address and executes the loaded program 6 6 DSP Core Programming Model The DSP56300 core treats the HI08 as a memory mapped peripheral occupying eight 24 bit words in X data memory space The DSP can use the HIOS8 as a normal memory mapped peripheral employing either standard polled or interrupt driven programming techniques Separate transmit and receive data registers are double buffered
286. he choice of which protocol to use is based on such system constraints as the amount of data to be transferred the timing requirements for the transfer and the availability of such resources as processing bandwidth and DMA channels All of these constraints are 6 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation discussed in the following sections The transfers described here occur asynchronously between the host and the DSP each transferring data at its own pace However use of the appropriate handshaking protocol allows data transfers to occur at optimum rates 6 4 4 Software Polling Software polling is the simplest data transfer method to use but it demands the greatest amount of the core s processing power Status bits are provided for the host or the DSP core to test and determine if the data registers are empty or full However the DSP core cannot be involved in other processing activities while it is polling these status bits On the DSP side for transfers from the DSP to the host host reads the DSP core must determine the state of Host Transmit Data register HTX In transfers from the host to the DSP host writes the DSP side should determine the state of the Host Receive Data Register HRX Thus two bits are provided to the core for polling m the Host Transmit Data Empty bit in the Host Status register HSR 1 HTDE m the H
287. he external world through one bidirectional signal When this signal is configured as an input the timer functions as an external event counter or measures external pulse width signal period When the signal is used as an output the timer functions as either a timer a watchdog or a pulse width modulator 1 9 6 EFCOP The EFCOP interfaces with the DSP core via the peripheral module bus It is a general purpose fully programmable coprocessor that performs filtering tasks concurrently with the DSP core with minimum core overhead The DSP core and the EFCOP can share data via an 8K word shared data memory DMA channels shuttle input and output data between the DSP core and the EFCOP The EFCOP supports a variety of filter modes some of which are optimized for cellular base station applications Real finite impulse response FIR with real taps Complex FIR with complex taps Complex FIR generating pure real or pure imaginary outputs alternately A 4 bit decimation factor in FIR filters thus providing a decimation ratio up to 16 Direct form 1 DFD infinite impulse response IIR filter Direct form 2 DFID IIR filter Four scaling factors 1 4 8 16 for IIR output Adaptive FIR filter with true least mean square LMS coefficient updates Adaptive FIR filter with delayed LMS coefficient updates The EFCOP supports up to 10K taps and 10K coefficients in any combination of number and length of filters e g eight filters of length 512 or 16 fil
288. he transmitters 7 7 DSP receive data interrupt request 7 29 enable transfer of data from TX1 to Transmit Shift Register 0 7 21 enable transfer of data from TX1 to Transmit Shift Register 1 7 21 enable transfer of data from TX2 to Transmit Shift Register 2 7 22 enable disable a DSP transmit interrupt 7 20 enable disable DSP receive data interrupt 7 20 enable disable receive portion 7 21 exceptions 7 8 receive data 7 8 receive data with exception status 7 8 receive last slot interrupt 7 8 transmit data 7 9 transmit data with exception status 7 8 transmit last slot interrupt 7 8 flags 7 13 frame rate divider 7 10 Frame Sync Generator 7 18 frame sync I O signal 7 6 frame sync length 7 12 frame sync polarity 7 12 frame sync selection 7 11 frame sync signal 7 7 7 10 frame sync signal format 7 11 frame sync word length 7 12 frame synchronization signals 7 18 Gated clock mode 7 3 GPIO 7 6 GPIO functionality 7 36 handle 24 bit fractional data 7 16 initialization 7 6 initialization example 7 7 internally generated clock and frame sync 7 7 interrupt service routine 7 9 interrupt trigger 7 9 interrupt trigger event 7 9 interrupts 7 8 multiple serial device selection 7 5 Network enhancements 7 2 Network mode 7 1 7 8 7 10 7 22 Normal and Network mode 7 21 Normal and On Demand modes 7 21 Normal mode 7 1 7 10 On Demand mode 7 10 7 15 7 21 operating modes 7 6 7 10 polling interrupts DMA 7 7 Port Control Register PCR 7 7 7 36 Por
289. hen HREQ HTRQ is configured as the host request HREQ output If HREN is cleared HREQ HTRQ and HACK HRRQ are configured as GPIO signals according to the value of the HDDR and HDR If HREN is set in the double host request mode that is if HDRQ is set in the ICR HREQ HTRQ is configured as the host transmit request HTRQ output and HACK HRRQ as the host receive request HRRQ output If HREN is cleared HREQ HTRQ and HACK HRRQ are configured as GPIO signals according to the value of the HDDR and HDR 3 HCSEN 0 Host Chip Select Enable If the HCSEN bit is set HCS HA10 is a host chip select HCS in the non multiplexed bus mode that is when HMUX is cleared and host address line 10 HA10 in the multiplexed bus mode that is when HMUX is set If this bit is cleared HCS HA10 is configured as a GPIO signal according to the value of the HDDR and HDR 2 HA9EN 0 Host Address Line 9 Enable If HA9EN is set and the HIO8 is in multiplexed bus mode then HA9 HA2 is host address line 9 HA9 If this bit is cleared and the HIO8 is in multiplexed bus mode then HA9 HA2 is configured as a GPIO signal according to the value of the HDDR and HDR NOTE HA9EN is ignored when the HIO8 is not in the multiplexed bus mode that is when HMUX is cleared 1 HA8EN 0 Host Address Line 8 Enable If HA8EN is set and the HIO8 is in multiplexed bus mode then HA8 A1 is host address line 8 HA8 If this bit is cleared and the HIO8 is in multiplexed b
290. heral dedicated signals No dedicated GPIO signals are provided All of these signals are GPIO by default after reset The control register settings of the DSP56311 peripherals determine whether these signals function as GPIO or as peripheral dedicated signals This section tells how signals can be used as GPIO Chapter 2 Signals Connections details the special uses of the 34 bidirectional signals These signals fall into five groups and are controlled separately or as a group Port B 16 GPIO signals shared with the HIOS signals Port C six GPIO signals shared with the ESSIO signals Port D six GPIO signals shared with the ESSII signals Port E three GPIO signals shared with the SCI signals Timers three GPIO signals shared with the triple timer signals 5 5 1 Port B Signals and Registers Each of the 16 Port B signals not used as an HIOS signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port B host control register HCR host port GPIO data register HDR and host port GPIO direction register HDDR Chapter 6 Host Interface HIO8 discusses these registers Motorola DSP56311 User s Manual 5 6 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Purpose Input Output GPIO DSP56311 Non Multiplexed Multiplexed Port B GPIO Bus Bus H0 H7 HADO HAD7 PBO PB7 HAO HAS HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS HCS HA10 PB13 Host In
291. hich the transmit and or receive baud rate is derived in Asynchronous mode and from which data is transferred in Synchronous mode SCLK can be programmed as a GPIO signal PE2 when the SCI SCLK function is not in use This signal can be programmed as PE2 when data is being transmitted on TXD since the clock does not need to be transmitted in Asynchronous mode Because SCLK is independent of SCI data I O there is no connection between programming the PE2 signal as SCLK and data coming out the TXD signal 8 3 SCI After Reset There are several different ways to reset the SCI m Hardware RESET signal W Software RESET instruction Both hardware and software resets clear the port control register bits which configure all I O as GPIO input The SCI remains in the Reset state as long as all SCI signals are programmed as GPIO PC2 PC1 and PCO all are cleared the SCI becomes active only when at least one of the SCI I O signals is not programmed as GPIO 8 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc m Individual reset During program execution the PC2 PC1 and PCO bits can all be cleared that is individually reset causing the SCI to stop serial activity and enter the Reset state All SCI status bits are set to their reset state However the contents of the SCR remain unaffected so the DSP program can reset the SCI separately from the other internal p
292. hift register If SHFD is set data is shifted in and out with the LSB first If SHFD is cleared data is shifted in and out with the MSB first as in Figure 7 12 on page 7 32 and Figure 7 13 on page 7 33 5 SCKD 0 Clock Source Direction Selects the source of the clock signal that clocks the transmit shift register in Asynchronous mode and both the transmit and receive shift registers in Synchronous mode If SCKD is set and the ESSI is in Synchronous mode the internal clock is the source of the clock signal used for all the transmit shift registers and the receive shift register If SCKD is set and the ESSI is in Asynchronous mode the internal clock source becomes the bit clock for the transmit shift register and word length divider The internal clock is output on the SCK signal When SCKD is cleared the external clock source is selected The internal clock generator is disconnected from the SCK signal and an external clock source may drive this signal 4 SCD2 0 Serial Control Direction 2 Controls the direction of the SC2 I O signal When SCD2 is set SC2 is an output when SCD2 is cleared SC2 is an input NOTE Programming the ESSI to use an internal frame sync that is SCD2 1 in CRB causes the SC2 and SC1 signals to be programmed as outputs However if the corresponding multiplexed pins are programmed by the Port Control Register PCR to be GPIOs the GPIO Port Direction Register PRR chooses their direction The ESSI uses a
293. hip Operating Mode Indicate the operating mode of the DSP56300 core On hardware reset these bits are loaded from the external mode select pins MODD MODC MODB and MODA respectively After the DSP56300 core leaves the Reset state MD MC MB and MA can be changed under program control The MD MA bits reflect the corresponding value of the mode input i e MODD MODC MODB or MODA respectively 4 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Status Register SR 4 5 Status Register SR The Status Register SR Figure 4 4 is a 24 bit register that indicates the current system state of the processor and the results of previous arithmetic computations The SR is pushed onto the system stack when program looping is initialized or a JSR is performed including long interrupts The SR consists of the following three special purpose 8 bit control registers m Extended Mode Register EMR SR 23 16 and Mode Register MR SR 15 8 Define the current system state of the processor The bits in both registers are affected by hardware reset exception processing ENDDO end current DO loop instructions RTI return from interrupt instructions and TRAP instructions In addition the EMR bits are affected by instructions that specify SR as their destination DO FOREVER instructions BRKcc instructions and instructions that
294. hows how the chip select logic uses HBAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA10 BA9 BA8 BA7 BA6 BAS BA4 BA3 Reserved bit read as 0 should be written with 0 for future compatibility Figure 6 9 Host Base Address Register HBAR X FFFFC5 Table 6 10 Host Base Address Register HBAR Bit Definitions Bit Number Bit Name Reset Value Description 15 8 0 Reserved Set to 0 for future compatibility 7 0 BA 10 3 80 Base Address Reflect the base address where the host side registers are mapped into the bus address space HAD 0 7 HAS HA 8 10 S g Chip select Base DSP Peripheral Address 8 Data Bus Register Figure 6 10 Self Chip Select Logic 6 6 6 Host Port Control Register HPCR The HPCR is a read write control register that controls the HIO8 operating mode HPCR bit initialization values s are discussed in Section 6 6 9 DSP Side Registers After Reset on page 6 22 Hardware and software reset clear the HPCR bits Motorola Host Interface H108 6 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HAP HRP HCSP HDDS HMUX HASP HDSP HROD HEN HAEN HREN HCSEN HA9EN HA8EN HGEN Note heser
295. ible as Table 6 4 shows Refer to the DSP56300 Family Manual to learn about DMA accesses Table 6 4 DMA Request Sources Requesting Device DCRx 15 11 DRS4 DRSO Host Receive Data Full HRDF 1 10011 Host Transmit Data Empty HTDE 1 10100 Note that DMA transfers do not access the host bus The host must determine when data is available in the host side data registers using an appropriate polling mechanism 6 4 4 Host Requests A set of signal lines allow the HIOS to request service from the host The request signal lines normally connect to the host interrupt request pins IRQx and indicate to the host when the DSP HIOS port requires service The HIO8 can be configured to use either a single Host Request HREQ line for both receive and transmit requests or two signal lines a Host Transmit Request HTRQ and a Host Receive Request HRRQ for each type of transfer Host requests are enabled on both the DSP side and host side On the DSP side the HPCR Host Request Enable bit HPCR 4 HREN is set to enable host requests On the host side clearing the ICR Double Host Request bit ICR 2 HDRQ configures the HI08 to use a single request line HREQ Setting the ICR 2 2HDRQ bit enables both transmit and request lines to be used Further the host uses the ICR Receive Request Enable bit ICR O RREQ and the ICR Transmit Request Enable bit ICR 1 2TREQ to enable Motorola Host Interface H108 6 9 For More Infor
296. ifted out to the serial transmit data signals by the selected whether internal or external bit clock when the associated frame sync I O is asserted The word length control bits in CRA determine the number of bits that must be shifted out before the shift registers are considered empty and can be written again Depending on the setting of the CRA the number of bits to be shifted out can be 8 12 16 24 or 32 Transmitted data is aligned according to the value of the ALC bit When ALC is cleared the MSB is Bit 23 and the least significant byte is unused When ALC is set the MSB is Bit 15 and the most significant byte is unused Unused bits are read as 0 Data shifts out of these registers MSB first if the SHFD bit is cleared and LSB first if SHFD is set Motorola Enhanced Synchronous Serial Interface ESSI 7 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 23 16 15 87 0 ESSI Receive Data Receive High Byte Receive Middle Byte Receive Low Byte Register 0 7 0 7 07 23 16 15 8 7 0 Receive High Byte Receive Middle Byte Receive Low Byte OMM lt a A lt lt __ O4 0 Seria Receive Shift Register WL1 WLO 8 bit Data 0 0 0 Least Significant Zero Fill MSB MSB l LSB 12 bit Data LSB 16 bit Data LSB 24 bit Data NOTES a Receive Registers Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 32
297. imation by M of a sequence of real numbers is represented by N 1 F n Iv gt H i D n i i 0 A DMA data transfer occurs in the following stages for both input and output The stages are the similar to the ones described in Section 10 7 1 1 The difference is set FDCH 11 8 FDCM M Processing 1 Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDM via FDIR 2 Compute F n the result is stored in FDOR the EFCOP triggers DMA output for an output data transfer 3 Repeat M times Get new data word EFCOP increments data memory pointer Motorola DSP56311 User s Manual 10 30 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes Output Data Stream F 0 FM F 2M F 3M FAM Coefficient Memory Bank FCM Figure 10 10 Real FIR Filter Data Stream With Decimation by M 10 7 3 Adaptive FIR Filter An adaptive FIR filter is represented in Figure 10 11 The goal of the FIR filter is to adjust the filter coefficients so that the output F n becomes as close as possible to the desired signal R n that is E n 0 R n D n F n E I Filter Update I Figure 10 11 Adaptive FIR Filter The adaptive FIR filter typically comprises four stages which are perfor
298. imized for DSP applications Refer to the chapter on interrupts in the DSP56300 Family Manual The interrupt table resides in the 256 locations of program memory to which the PCU vector base address VBA register points 4 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt Sources and Priorities 4 3 1 Interrupt Sources Each interrupt is allocated two instructions in the table resulting in 128 table entries for interrupt handling Table 4 2 shows the table entry address for each interrupt source The DSP56311 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions In the DSP56311 only some of the 128 vector addresses are used for specific interrupt sources The remaining interrupt vectors are reserved and can be used for host NMI IPL 3 or for host command interrupt IPL 2 Unused interrupt vector locations can be used for program or data storage Table 4 2 Interrupt Sources CENA EO Starting Address Range Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack error VBA 04 3 Illegal instruction VBA 06 3 Debug request interrupt VBA 08 3 Trap VBA 0A 3 Nonmaskable interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IRQA VBA 12 0 2 IROB VBA 14 0 2 IRQC VBA 16 0 2 I
299. ines are enabled and should be connected accordingly 32322232522222222222222222222222222232522222222222222222222222225225222522222525 If MD MC MB MA 1111 then the program RAM is loaded from the Host Interface programmed to operate in the MC68302 IMP bus mode in single strobe pin configuration The HOST MC68302 bootstrap code expects accesses that are byte wide The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words are stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address E page 132 55 0 0 0 opt mex insseebpass JBNBERAL EQUATES 5 132 53 BOOT equ D00000 this is the location in P memory on the external memory bus where the external byte wide EPROM would be located AARV equ D00409 AARI selects the EPROM as CE mapped as P from D00000 to Motorola Bootstrap Program A 3 For More Information On This Product Go to www f
300. ing Model Quick Reference 6 36 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 7 Enhanced Synchronous Serial Interface ESSI The ESSI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard CODECs other DSPs microprocessors and peripherals The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator There are two independent and identical ESSIs in the DSP56311 ESSIO and ESSII For simplicity a single generic ESSI is described here The ESSI block diagram is shown in Figure 7 1 This interface is synchronous because all serial transfers are synchronized to one clock Note This synchronous interface should not be confused with the asynchronous channels mode of the ESSI in which separate clocks are used for the receiver and transmitter In that mode the ESSI is still a synchronous device because all transfers are synchronized to these clocks Pin notations for the generic ESSI refer to the analogous pin of ESSIO PCx and ESSII PDx Additional synchronization signals delineate the word frames The Normal mode of operation transfers data at a periodic rate one word per period The Network mode is similar in that it is also for periodic transfers however it supports up to 32 words time slots per period The Network mode can
301. ing edge of the signal from the TIO signal 2 Counter is incremented on Counter is incremented on Initial output put on Initial output inverted the rising edge of the the falling edge of the TIO signal directly and put on TIO signal signal from the TIO signal signal from the TIO signal 3 Counter is incremented on Counter is incremented on the rising edge of the the falling edge of the signal from the TIO signal signal from the TIO signal uu o 9 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Table 9 4 Inverter INV Bit Operation Continued TIO Programmed as Input TIO Programmed as Output Mode INV 0 INV 1 INV 0 INV 1 4 Width of the high input Width of the low input pulse is measured pulse is measured 5 Period is measured Period is measured between the rising edges between the falling edges of the input signal of the input signal o _ 6 Event is captured on the Event is captured on the rising edge of the signal falling edge of the signal from the TIO signal from the TIO signal m E 7 Pulse generated by Pulse generated by uS the timer has the timer has positive polarity negative polarity 9 Pulse generated by Pulse generated by 2 the timer has the timer has positive polarity negative polarity 10 Pulse generated by Pulse gener
302. ing several pieces of data to the HIO8 port The host first uses one of the handshaking protocols to determine whether any data previously written to the Transmit Byte Registers TXH M L has successfully transferred to the DSP side If the host side Transmit Byte Registers TXH M L are empty the host writes the data to these registers The transfer to the DSP side Host Receive Data Register HRX occurs only if HRX is empty that is the DSP has read it The DSP core then uses an appropriate handshaking protocol to move data from the HRX to the receiving buffer or register Without handshaking the host might overwrite data not transferred to the DSP side or the DSP might receive stale data Similarly when the host performs multiple reads from the HIO8 port Receive Byte Registers RXH M L the DSP side uses an appropriate handshaking protocol to determine whether any data previously written to the Host Transmit Register HTX has successfully transferred to the host side registers If HTX is empty the DSP writes the data to this register Data transfers to the host side Receive Byte Registers RXH M L occur only if they are empty that is the host has read them The host can then use any of the available handshaking protocols to determine whether more data is ready to be read The DSP56311 HI08 port offers the following handshaking protocols for data transfers with the host Software polling Interrupts Core DMA access Host requests T
303. ipeline 6 6 polling techniques 6 23 6 29 receive and transmit data paths 6 4 Receive Byte Registers 6 6 Receive Byte Registers RXH RXM RXL 6 30 receive byte registers RXH RXM RXL contain data from DSP to be read by host processor 6 29 Receive Data Full bit in the Interface Status Register 6 7 Receive Data Registers 6 4 Receive Registers RXH RHM RHL 6 7 register banks 6 4 request service from host 6 9 reserved interrupt vector addresses for application specific service routines 6 8 resets hardware and software 6 4 6 13 RREQ and RXDF 6 26 select host command interrupt address for use by host command interrupt logic 6 27 Motorola DSP56311 User s Manual Index 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc select the interrupt address to be used 6 8 software polling 6 7 software reset 6 31 status register ISR 6 23 STOP command 6 24 STOP instruction 6 31 Stop mode 6 24 timing requirements 6 6 Transmit Byte Registers 6 6 Transmit Byte Registers TXH TXM TXL 6 30 transmit byte registers TXH TXM TXL are empty and can be written by host processor 6 29 Transmit Data Empty bit in the Interface Status Register 6 7 Transmit Data Registers 6 4 Transmit Registers TXH TXM TXL 6 7 TRDY 6 29 vector registers CVR and IVR 6 23 HI08 GPIO functions 6 4 HI08 ICR 6 30 6 31 HLEND bit 6 25 HMUX bit 6 19 Host Address Line 8 Enable bit HA8EN 6 20 Host Address Line 9
304. is when HDRQ is set in the ICR if HROD is cleared and host requests are enabled that is if HREN is set and HEN is set in the HPCR then the HTRQ and HRRQ signals are always driven If HROD is set and host requests are enabled the HTRQ and HRRQ signals are open drain outputs 7 0 Reserved Set to 0 for future compatibility 6 HEN 0 Host Enable If HEN is set the HIO8 operates as the host interface If HEN is cleared the HIO8 is not active and all the HIO8 signals are configured as GPIO signals according to the value of the HDDR and HDR 5 HAEN 0 Host Acknowledge Enable Controls the HACK signal In the single host request mode HDRQ is cleared in the ICR if HAEN and HREN are both set HACK HRRQ is configured as the host acknowledge HACK input If HAEN or HREN is cleared HACK HRRQ is configured as a GPIO signal according to the value of the HDDR and HDR In the double host request mode HDRQ is set in the ICR HAEN is ignored Motorola Host Interface H108 6 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model Table 6 11 Host Port Control Register HPCR Bit Definitions Bit Number Bit Name Reset Value Description 4 HREN 0 Host Request Enable Controls the host request signals If HREN is set and the HIO8 is in the single host request mode that is if HDRQ is cleared in the host interface control register ICR t
305. is a 16 bit read write counter register used as an address pointer to the EFCOP FCM bank FCBA points to the first location of the coefficient table The FCBA points to a modulo buffer of size M defined by the filter length M FCNT 11 0 1 The address range of this modulo buffer is defined by lower and upper address boundaries The lower address boundary is the FCBA value with 0 in the k LSBs where 2 gt M gt 2 it therefore must be a multiple of 2 The upper boundary is equal to the lower boundary plus M 1 Since M x 2 once M has been chosen that is FCNT has been assigned a sequential series of coefficient memory blocks each of length 25 is created where multiple circular buffers for multichannel filtering can be located If M 2 there will be a space between sequential circular buffers of 2 M The FCBA address pointer must be assigned to the lower address boundary that is it must have 0 in its k LSBs In a compute session the coefficient address pointer always starts at the lower boundary and ends at the upper address boundary Therefore a FCBA read always gives the value of the lower address boundary 10 3 9 Decimation Channel Count Register FDCH The FDCH is a read write register that sets the number of channels used in multichannel mode FCHL and sets the decimation ratio in FIR filter mode FDCH must be written before the FEN enables the EFCOP FDCH should be changed only when the EFCOP is in individual r
306. is set an interrupt is requested 1 0 HTRQ and HRRQ are cleared no host processor interrupts are requested 1 1 HTRQ or HRRQ are set an interrupt is requested 6 5 0 Reserved Set to 0 for future compatibility 4 HF3 0 Host Flag 3 Indicates the state of HF3 in the HCR on the DSP side HF3 can be changed only by the DSP56311 Hardware and software reset clear HF3 3 HF2 0 Host Flag 2 Indicates the state of HF2 in the HCR on the DSP side HF2 can be changed only by the DSP56311 Hardware and software reset clear HF2 6 28 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Table 6 16 Freescale Semiconductor Inc Host Programmer s Model Interface Status Register ISR Bit Definitions Continued Bit Number Bit Name Reset Value Description 2 TRDY Transmitter Ready Indicates that TXH TXM TXL and the HRX registers are empty If TRDY is set the data that the host processor writes to TXH TXM TXL is immediately transferred to the DSP side of the HIO8 This feature has many applications For example if the host processor issues a host command that causes the DSP56311 to read the HRX the host processor can be guaranteed that the data it just transferred to the HIO8 is that being received by the DSP5631 1 Hardware software individual and stop resets all set TRDY CAUTION TRDY z TXDE and HRDF TXDE Transmit Data Register Empty Indicates
307. ister to the receive data register SRX that is already full RDRF 1 The receive shift register data is not transferred to the SRX The OR flag indicates that character s in the received data stream may have been lost The only valid data is located in the SRX OR is cleared when the SCI status register is read followed by a read of SRX The OR bit clears the FE and PE bits that is overrun error has higher priority than FE or PE A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears OR IDLE Idle Line Flag Set when 10 or 11 consecutive ones are received IDLE is cleared by a start bit detection The IDLE status bit represents the status of the receive line The transition of IDLE from 0 to 1 can cause an IDLE interrupt ILIE RDRF Receive Data Register Full Set when a valid character is transferred to the SCI receive data register from the SCI receive shift register regardless of the error bits condition RDRF is cleared when the SCI receive data register is read TDRE Transmit Data Register Empty Set when the SCI transmit data register is empty When TDRE is set new data can be written to one of the SCI transmit data registers STX or the transmit data address register STXA TDRE is cleared when the SCI transmit data register is written Either a hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instr
308. it is not enabled the IFO bit is cleared 7 30 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 7 5 4 ESSI Receive Shift Register The 24 bit Receive Shift Register see Figure 7 12 and Figure 7 13 receives incoming data from the serial receive data signal The selected internal external bit clock shifts data in when the associated frame sync I O is asserted Data is received MSB first if SHFD is cleared and LSB first if SHFD is set Data transfers to the ESSI receive data register after 8 12 16 24 or 32 serial clock cycles are counted depending on the word length control bits in the CRA 7 5 5 ESSI Receive Data Register RX The Receive Data Register RX is a 24 bit read only register that accepts data from the receive shift register as it becomes full according to Figure 7 12 and Figure 7 13 The data read is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is bit 23 and the least significant byte is unused When the ALC bit is set the MSB is bit 15 and the most significant byte is unused Unused bits are read as 0 If the associated interrupt is enabled the DSP is interrupted whenever the RX register becomes full 7 5 6 ESSI Transmit Shift Registers The three 24 bit transmit shift registers contain the data being transmitted as in Figure 7 12 and Figure 7 13 Data is sh
309. it shift register The STD output is tri stated and any data present in TXO is not transmitted In other words data can be written to TXO with TEO cleared the TDE bit is cleared but data is not transferred to the transmit shift register 0 The transmit enable sequence in On Demand mode can be the same as in Normal mode or TEO can be left enabled NOTE Transmitter 0 is the only transmitter that can operate in Asynchronous mode SYN 0 The setting of the TEO bit does not affect the generation of frame sync or output flags 15 TE1 Transmit 1 Enable Enables the transfer of data from TX1 to Transmit Shift Register 1 TE1 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode When TE1 is set and a frame sync is detected transmitter 1 is enabled for that frame When TE1 is cleared transmitter 1 is disabled after completing transmission of data currently in the ESSI transmit shift register Any data present in TX1 is not transmitted If TE1 is cleared data can be written to TX1 the TDE bit is cleared but data is not transferred to transmit shift register 1 If the TE1 bit is kept cleared until the start of the next frame it causes the SCO signal to act as serial I O flag from the start of the frame in both Normal and Network mode The transmit enable sequence in On Demand mode can be the same as in Normal mode or the TE1 bit can be left enabled NOTE The setting o
310. ive and transmit frame sync signals When FSP is cleared the frame sync signal polarity is positive that is the frame start is indicated by the frame sync signal going high When FSP is set the frame sync signal polarity is negative that is the frame start is indicated by the frame sync signal going low 7 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 9 FSR 0 Frame Sync Relative Timing Determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines for word length frame sync only When FSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot When FSR is set the word length frame sync occurs one serial clock cycle earlier that is simultaneously with the last bit of the previous data word 7 8 FSL 1 0 0 Frame Sync Length Selects the length of frame sync to be generated or recognized as in Figure 7 6 on page 7 25 Figure 7 9 on page 7 28 and Figure 7 10 on page 7 28 F l FSi Frame Sync Length RX TX 0 0 word word 0 1 word bit 1 0 bit bit 1 1 bit word 6 SHFD 0 Shift Direction Determines the shift direction of the transmit or receive s
311. ive number and revision number of the device This information is used in testing or by software Figure 4 6 shows the contents of the IDR Revision numbers are assigned as follows 0 is revision 0 1 is revision A and so on Changing the following bits may cause the PLL to lose lock and re lock according to their new value PD 3 0 PEN XTLR and MF 23 16 15 12 11 0 Reserved Revision Number Derivative Number 00 0 311 Figure 4 6 Identification Register Configuration Revision 0 4 8 Address Attribute Registers AARO AAR3 The Address Attribute Registers AARO AAR3 are read write registers that control the activity of the AAOCAAS RASO RASS pins The associated AAn RASn pin is asserted if the address defined by the BAC bits in the associated AAR matches the exact number of external address bits defined by the BNC bits and the external address space X data Y data or program is enabled by the AAR Figure 4 7 shows an AAR register Table 4 9 lists the bit definitions Note that the DSP56311 does not support address multiplexing 4 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com 23 22 21 20 Freescale Semiconductor Inc 19 18 Address Attribute Registers AARO AAR3 17 16 15 14 13 12 11 10 9 8 7 6 ENCS BNC2 ENCT ENCO BPAQ EYEN EXEN EPEN BAAP BAT1 BATO Address to Compare 5 4 3 2 1 0
312. k DFO DF2 XTAL Range select bit XTAL Disable Bit STOP Processing State Bit PLL Enable Bit PLL Clock Output Disable Bit PreDivider Factor Bits Mask PDO PD3 Register Addresses Of BIU M BCR EQU FFFFFB M DCR EQU FFFFFA M AARO EQU M AARI EQU M AAR2 EQU M AAR3 EQU M IDR EQU FFFFF5 SFFFFF9 SFFFFFS8 SFFFFF7 SFFFFF6 Bus Control Register M BAOW EQU M BAIW EQU M BA2W EQU M BA3W EQU M BDFW EQU M BBS EQU 21 M BLH EQU 22 M BRH EQU 23 A 18 1F 3E0 1C00 E000 1F0000 Bus Control Register DRAM Control Register Address Attribute Register O Address Attribute Register 1 Address Attribute Register 2 Address Attribute Register 3 ID Register Area 0 Wait Control Mask BAOWO BAOW4 Area 1 Wait Control Mask BA1W0 BA14 Area 2 Wait Control Mask BA2W0 BA2W2 Area 3 Wait Control Mask BA3W0 BA3W3 Default Area Wait Control Mask BDFWO BDFWA4 Bus State Bus Lock Hold Bus Request Hold DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Equates DRAM Control Register M BCW EQU M BRW EQU M BPS EQU M BPLE EQU M BME EQU M BRE EQU M BSTR EQU M BRF EQU M BRP EQU 3 In Page Wait States Bits Mask BC W0 BCW1 C Out Of Page Wait States Bits Mask BRWO BRWI 300 DRAM Page Size Bits Mask BPSO BPS1 11 Page Logic Enable 12 Mastership Enable 13 Ref
313. k REE R EER ER EKER EEK deck ERE EER EERE EER ERK EER KEK EEE RER ERE KER KK ERK EKER KER RK E KEK RK ORG p Start interrupt initialisation bset 10 x M IPRP bset 11 x M IPRP bclr 8 SR bclr 9 SR move 0 b move 0 a move DST COUNT D0 FDM memory initialisation move FDBA_ADDRS r0 move 0 x0 rep F IR_LEN move x0 x r0 address register initialisation move DST_ADDRS r0 move DES_ADDRS r1 rep FIR_LEN 1 move rl EFCOP initialisation movep FIR_LEN 1 y M_FCNT movep FDBA_ADDRS y M_FDBA movep FCBA_ADDRS y M_FCBA Motorola Enhanced Filter Coprocessor EFCOP enable EFCOP interrupts in IPRP enable interrupts in SR counter for output interrupt FDM memory area clear FDM memory area Destination address Desired signal address Set reference pointer correctly FIR length FIR input samples Start Address FIR Coeff Start Address 10 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes movep FCON y M FCSR DMA channel 0 initialisation input to movep SRC_ADDRS x M_DSRO E movep M_FDIR x M DDRO F movep SRC_COUNT x M DCOO E movep 51 x M_DORO movep 94AA04 x M_DCRO E request nop nop Qa M ERAEAARELEARA ARE ERAR AAR ER ERA RR OSCURA SONT OS waitl jset 11 y M_FCSR A do 40 endd nop endd nop nop
314. l Register PCR The read write 24 bit PCR controls the functionality of the ESSI GPIO signals Each of the PC 5 0 bits controls the functionality of the corresponding port signal When a PC i bit is set the corresponding port signal is configured as an ESSI signal When a PCT bit is cleared the corresponding port signal is configured as a GPIO signal Either a hardware RESET signal or a software RESET instruction clears all PCR bits 7 36 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pcs Pca PC8 PC2 Pci PCo 0 GPIO 1 ESSI STDn SRDn SCKn SCn2 SCn1 SCn0 PRCR ESSIO PCRD ESSI ES Reserved Read as zero Write with zero for future compatibility Figure 7 18 Port Control Register PCR PCRC X FFFFBF PCRD X FFFAF 7 6 2 Port Direction Register PRR The read write 24 bit PRR controls the data direction of the ESSI GPIO signals When PRR i is set the corresponding signal is an output signal When PRR i is cleared the corresponding signal is an input signal Either a hardware RESET signal or a software RESET instruction clears all PRR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pps PDC4 PDC3 PDC2 PDC1 PDCO 0 Input 1 Output STDn SRDn SCKn SCn2 SCni SCn0d PRRC ESSIO PRRD ESSI1 Reserved Read as zero Write with zero for future compa
315. l Register B cross correlation filtering 10 1 crystal frequency 8 6 CVR see Command Vector Register Index 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D data and control host processor registers 6 13 Data Arithmetic Logic Unit 1 6 Multiplier Accumulator MAC 1 6 registers 1 6 data strobe 6 4 data transfer methods 5 3 interrupts 5 3 polling 5 3 data coefficient transfer contention bit 10 2 Debug mode entering 2 21 external indication 2 21 warning 3 8 decimation 10 1 10 4 10 7 10 13 10 14 example sequence of even real numbers 10 30 Decimation Channel Count Register 10 13 10 14 DFI 10 2 DFII 10 2 Direct Form 1 10 2 Direct Form 2 10 2 Direct Memory Access DMA 6 9 EFCOP and 10 2 Request Source bits DRSA DRSO 4 10 restrictions on EFCOP 10 5 triggered by timer 9 21 DMA 6 6 DMA see Direct Memory Access DMA transfers and host bus 6 9 DO loop 1 8 Double Data Strobe 2 3 Double Host Request bit HDRQ 6 25 DRAM 1 10 DS 2 3 DSP core programming model 6 13 DSP transmit interrupt 7 20 DSP56300 core 1 1 DSP56300 Family Manual 1 1 1 5 6 9 6 21 6 31 DSP56307 Technical Data 1 1 DSP to host transfers 6 6 dual host requests enabled 6 10 dynamic memory configuration switching 3 7 E echo cancellation 10 1 echo cancellation filter 10 31 EFCOP 1 2 1 14 control and status registers 10 4 core transfers 10 2 DMA restrictions 10 4 DMA transfers 10 2 FACR 10 11 10 12
316. l flag I O would be multiple device selection for addressing in CODEC systems If SCO is configured as a serial flag signal or receive clock signal its direction is determined by the serial control direction 0 SCDO bit in ESSI control register B CRB When configured as an output SCO functions as the serial output flag 0 OFO or as a receive shift register clock output If SCO is used as the serial output flag 0 its value is determined by the value of the serial output flag 0 OFO bit in the CRB If SCO is an input it functions as either serial Input Flag 0 or a receive shift register clock input As serial input flag 0 SCO controls the state of the serial input flag O IFO bit in the ESSI status register SSISR When SCO is configured as a transmit data signal it is always an output signal regardless of the SCDO bit value SCO is fully synchronized with the other transmit data signals STD and SC1 SCO can be programmed as a GPIO signal PO when the ESSI SCO function is not in use Note The ESSI can operate with more than one active transmitter only in Synchronous mode 7 4 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc ESSI Data and Control Signals 7 2 5 Serial Control Signal SC1 ESSI0 SC01 ESSI1 SCI11 To determine the function of SC1 select either Synchronous or Asynchronous mode according to Table 7 2 In Asynchronous mode as f
317. l the enabled transmitters and receivers in synchronous modes or by all the enabled transmitters in Asynchronous modes See Table 7 1 for details SCK can be programmed as a GPIO signal P3 when the ESSI SCK function is not in use Motorola Enhanced Synchronous Serial Interface ESSI 7 3 For More Information On This Product Go to www freescale com ESSI Data and Control Signals Freescale Semiconductor Inc Table 7 1 ESSI Clock Sources SYN SCKD SCDO RX Clock Source T TX Clock Source TX Clock Out Asynchronous 0 0 0 EXT SCO EXT SCK 0 0 1 INT Sco EXT SCK 0 1 0 EXT SCO INT SCK 0 1 1 INT SCO INT SCK Synchronous 1 0 0 1 EXT SCK EXT SCK 1 1 0 1 INT SCK INT SCK Note Although an external serial clock can be independent of and asynchronous to the DSP system clock the external ESSI clock frequency must not exceed F ore 3 and each ESSI phase must exceed the minimum of 1 5 CLKOUT cycles The internally sourced ESSI clock frequency must not exceed F 4 7 2 4 Serial Control Signal SCO ESSIO SC00 ESSI1 SC10 To determine the function of the SCO signal select either Synchronous or Asynchronous mode according to Table 7 2 In Asynchronous mode this signal is used for the receive clock I O In Synchronous mode this signal is the transmitter data out signal for transmit shift register TX1 or for serial flag I O A typical application of seria
318. le com Freescale Semiconductor Inc Chapter 8 Serial Communication Interface SCI The DSP56311 Serial Communication Interface SCI provides a full duplex port for serial communication with other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as RS232C RS422 and so on This interface uses three dedicated signals transmit data receive data and SCI serial clock It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission up to 8 25 Mbps for a 66 MHz clock SCI asynchronous protocols include a multidrop mode for master slave operation with wake up on idle line and wake up on address bit capability This mode allows the DSP56311 to share a single serial line efficiently with other peripherals The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator supplies the transmit and receive clocks An enable vector and an interrupt vector are included so that the baud rate generator can function as a general purpose timer when the SCI is not using it or when the interrupt timing is the same as that used by the SCI 8 1 Operating Modes The operating modes for the DSP56311 SCI are
319. le com Freescale Semiconductor Inc X Data Memory Space 3 2 2 Memory Switch Modes X Data Memory Memory switch mode reallocates of portions of X and Y data RAM as program RAM Bit 7 in the OMR is the MS bit that controls this function as follows Note 3 4 When the MS bit is cleared the X data memory consists of the default 48K x 24 bit memory space described in the previous section In this default mode the lowest external X data memory location is 6000 When the MS bit is set a portion of the higher locations of the internal X memory is switched to internal program memory The memory switch MSW 1 0 configuration bits in the OMR select one of the following options MSW 1 0 00 The 32K higher locations 4000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 3FFF The X memory space at the switched locations 4000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSWTL 1 0 01 The 24K higher locations 6000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 5FFF The X memory space at the switched locations 6000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSWTL 1 0 10 The 16K higher locations 8000 BFFF of the inter
320. lled low to ground or that a low true signal is pulled high to Vcc See Table 1 1 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Manual Conventions Table 1 1 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN1 True Asserted Ground PIN False Deasserted Voc PIN True Asserted Voc PIN False Deasserted Ground n PIN is a generic term for any pin on the chip 2 Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels typically a TTL logic low 3 Vcc is an acceptable high voltage level See the appropriate data sheet for the range of acceptable high voltage levels typically a TTL logic high Pins or signals that are asserted low made active when pulled to ground are indicated like this in text In text they have an overbar for example RESET is asserted low In code examples they have a tilde in front of their names In Example 1 1 line 3 refers to the SSO signal shown as S50 Sets of signals are indicated by the first and last signals in the set for instance HA1 HAS Input Output indicates a bidirectional signal Input or Output indicates a signal that is exclusively one or the other Code examples are displayed in a monospaced font as shown in Example 1 1 Example 1
321. lling edge of TCK TMS Input Input Test Mode Select An input signal to sequence the test controller s state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor TRST Input Input Test Reset A Schmitt trigger input signal to asynchronously initialize the test controller TRST has an internal pull up resistor TRST must be asserted after power up Input Output Input Debug Event An open drain signal As an input enters the Debug mode of operation from an external command controller As an output acknowledges that the chip has entered Debug mode When asserted as an input DE causes the DSP56300 core to finish the executing instruction save the instruction pipeline information enter the Debug mode and wait for commands to be entered from the debug serial input line This signal is asserted as an output for three clock cycles when the chip enters Debug mode as a result of a debug request or as a result of meeting a breakpoint condition The DE has an internal pull up resistor This is not a standard part of the JTAG TAP controller The signal connects directly to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the debug mode All other interface with the OnCE module must occur through the JTAG port Motorola Signals Connections 2 21 For More Information On This Product Go
322. lock after TCSR TE is set When the values match the timer compare flag bit is set and an interrupt is generated if interrupts are enabled that is the timer compare interrupt enable bit in the TCSR is set The TCPR is ignored in measurement modes 9 4 7 Timer Count Register TCR The TCR is a 24 bit read only register In timer and watchdog modes the contents of the counter can be read at any time from the TCR register In measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge of the input signal When the timer is in measurement mode the TIO signal is used for the input signal 9 30 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 10 Enhanced Filter Coprocessor EFCOP The EFCOP peripheral module functions as a general purpose fully programmable filter It has optimized modes of operation to perform real and complex finite impulse response FIR filtering infinite impulse response IIR filtering adaptive FIR filtering and multichannel FIR filtering EFCOP filter operations complete concurrently with DSP56300 core operations with minimal CPU intervention For optimal performance the EFCOP has one dedicated Filter Multiplier Accumulator FMAC unit Thus for filtering the combination Core EFCO
323. lot interrupt is documented in Section 7 3 3 Exceptions on page 7 8 TLIE is disabled when the ESSI is in On Demand mode DC 0 19 RIE 0 Receive Interrupt Enable Enables disables a DSP receive data interrupt the interrupt is generated when both the RIE and receive data register full RDF bit in the SSISR are set When RIE is cleared this interrupt is disabled The receive interrupt is documented in Section 7 3 3 Exceptions on page 7 8 When the receive data register is read it clears RDF and the pending interrupt Receive interrupts with exception have higher priority than normal receive data interrupts If the receiver overrun error ROE bit is set signaling that an exception has occurred and the REIE bit is set the ESSI requests an SSI receive data with exception interrupt from the interrupt controller 18 TIE 0 Transmit Interrupt Enable Enables disables a DSP transmit interrupt the interrupt is generated when both the TIE and the TDE bits in the ESSI status register are set When TIE is cleared the transmit interrupt is disabled The transmit interrupt is documented in Section 7 3 3 When data is written to the data registers of the enabled transmitters or to the TSR it clears TDE and also clears the interrupt Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts If the transmitter underrun error TUE bit is set signaling that an exception has occurred and
324. ly a write only null data register that prevents data transmission in the current transmit time slot For timing purposes TSR is a write only register that behaves as an alternative transmit data register except that rather than transmitting data the transmit data signals of all the enabled transmitters are in the high impedance state for the current time slot 7 5 9 Transmit Slot Mask Registers TSMA TSMB Both transmit slot mask registers are read write registers When the TSMA or TSMB is read to the internal data bus the register contents occupy the two low order bytes of the data bus and the high order byte is filled by 0 In Network mode the transmitter s use these registers to determine which action to take in the current transmission slot Depending on the bit settings the transmitter s either tri state the transmitter s data signal s or transmit a data word and generate a transmitter empty condition 23 22 21 20 19 18 17 16 15 14 13 12 TS15 TS14 TS13 TS12 11 10 9 8 7 6 5 4 3 2 1 0 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TSO ESSIO X FFFFB4 ESSI1 X FFFFA4 Figure 7 14 ESSI Transmit Slot Mask Register A TSMA 7 34 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model 23 22 21 20 19 18 17 16 15 14 13 12 TS31 TS30 TS
325. m 017 Receive Low Byte Receive Middle Byte Receive High Byte Not Used Receive Byte Registers 7 6 5 4 Read Only Reset 00 Receive Byte Registers Host Transmit Data usually loaded by program 047 Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers 7 6 5 4 Write Only Reset 00 Figure B 14 Host Receive and Host Transmit Data Registers Motorola Programming Reference B 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets 0 se weibolg paeniasay ll a awa awa X LE eE EL VE SE OL ii 8l pue OZ lc ec i Eu Led 9Gz 0 L 44 00 0 ZINd lt L 92 20 19ejes sninpojN 9je amp 2Ss8Jd sbuey 1ojeosajd MIOMJON 104 SIO S QUI JO OpOW EUulJON JO Ol eJ epiAIq ze o1 L 41 00 0 pod ue Iq40J SI ueL ppiq10 s 00 0 Z INd pue uSd jBiuos dep ele oureid GL Iq 0 pause yo erep 4q 94 1 Ez q 0 pause yo ejep 119 91 0 101 u09 u wu iy Jeynq euje1xe O XL JO o qeue J9Aup Se suonouni Bey O I jeues se suonounj LOS 0 ejqeue aAup O XL Se LOS 199 o5 p m s y p m s y sud pz 1se ut e1ep Ze 000000 19s59H SII yz 1s4J ut ejep ze eiu w peeu sv4444 LISSA eiu peeu sg44 44 0ISS3 ve 9I xv v 1e1siDeu jo1uo2 Issa cl 8 Oo JO JO xe OC Ie OO Jr m O JO xe Ie O Oo JO JO Jr m pJOM
326. mation On This Product Go to www freescale com Freescale Semiconductor Inc Operation receive and transmit requests respectively When host requests are enabled the host request pins operate as shown in Figure 6 3 Status 7 qM A neo o o wes wes ev voe sor Host Request Asserted 2 Host Request Signals HRRQ HREQ HTRQ 0 EE Enable Figure 6 3 HI08 Host Request Structure Table 6 5 shows the operation of the HREQ pin when a single request line is used The host can test these ICR bits to determine the interrupt source Table 6 5 HREQ Pin Operation In Single Request Mode ICR 2 HDRQ 0 ICR 1 TREQ ICR 0 RREQ HREQ Pin 0 0 No interrupts 0 1 RXDF request enabled 1 0 TXDE Request enabled 1 1 RXDF and TXDE request enabled Table 6 6 shows the operation of the transmit request HTRQ and receive request HRRQ lines with dual host requests enabled Table 6 6 HTRQ and HRRQ Pin Operation In Double Request Mode ICR 2 HDRQ 1 ICR 1 TREQ ICR 0 RREQ HTRQ Pin HRRQ Pin 0 0 No interrupts No interrupts 0 1 No interrupts RXDF request enabled 1 0 TXDE Request enabled No interrupts 1 1 TXDE Request enabled RXDF request enabled 6 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation 6 4 5 Endian Modes The Host Little Endian bit in
327. med for each input sample at time n m Stage 1 The FIR filter output value is calculated for the EFCOP FIR session according to this equation N 1 F n gt H i D n i i 0 where H 1 are the filter coefficients at time n D n is the input signal and F n is the filter output at time n This stage requires N MAC operations calculated by the EFCOP FMAC unit Motorola Enhanced Filter Coprocessor EFCOP 10 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes m Stage 2 The core calculates the error signal E n in software according to the following equation E n R n F n where R n is the desired signal at time n This stage requires a single arithmetic operation m Stage 3 The core calculates the weight multiplier Ke n in software according to the following equation Ke n K E n where K is the convergence factor of the algorithm After calculating the weight multiplier Kg the core must write it into the FKIR m Stage 4 The coefficients are updated by the EFCOP update session H 40 H O Ke D n i where H 1 are the adaptive filter coefficients at time n 1 Ke n is the weight multiplier at time n and D n is the input signal This stage starts immediately after K n is written in the FKIR if Adaptive mode is enabled Motorola DSP56311 User s Manual 10 32 For More Information On This Product Go to
328. mer signal Each timer can also function as an event counter to capture an event or to measure the width or period of a signal 9 1 Overview The timer module contains a common 21 bit prescalar and three independent and identical general purpose 24 bit timer event counters each with its own register set Each timer has the following capabilities W uses internal or external clocking m interrupts the DSP56311 after a specified number of events clocks or signals an external device after counting internal events m triggers DMA transfers after a specified number of events clocks occurs W connects to the external world through one bidirectional signal designated TIO 0 2 for timers 0 2 When the TIO signal is configured as input the timer functions as an external event counter or measures external pulse width signal period When the TIO signal is configured as an output the timer functions as a timer a watchdog timer or a pulse width modulator When the timer is not using the TIO signal TIO can be used as a GPIO signal also called TIO O 2 Figure 9 1 shows a block diagram of the triple timer module Notice the 24 bit timer Prescalar Load Register TPLR and the 24 bit Timer Prescalar Count Register TPCR Each of the three timers can use the prescalar clock as its clock source The timer block diagram in Figure 9 2 shows the structure of a timer module The DSP56311 treats each timer as a memory mapped peripheral with four re
329. mmer wants to set the ninth bit the address bit When STXA is written the data from the low byte on the data bus is stored in it The address data bit is cleared in 11 bit asynchronous multidrop mode when any of STXL STXM or STXH is written When either STX STXL STXM or STXH or STXA is written TDRE is cleared The transfer from either STX or STXA to the transmit shift register occurs automatically but not immediately after the last bit from the previous word is shifted out that is the transmit shift register is empty Like the receiver the transmitter is double buffered However a delay of two to four serial clock cycles occurs between when the data is transferred from either STX or STXA to the transmit shift register and when the first bit appears on the TXD signal A serial clock cycle is the time required to transmit one data bit The transmit shift register is not directly addressable and there is no dedicated flag for this register Because of this fact and the two to four cycle delay two bytes cannot be written consecutively to STX or STXA without polling because the second byte might overwrite the first byte Thus you should always poll the TDRE flag prior to writing STX or STXA to prevent overruns unless transmit interrupts are enabled Either STX or STXA is usually written as part of the interrupt service routine An interrupt is generated only if TDRE is set The transmit shift register is indirectly visible via the SSR TR
330. mpare Count Registers TLR TCPR TCR Motorola Programming Reference B 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets GPIO Port B HIO8 Host Data Direction Register 14 1 15 3 12 11 10 9 8 7 6 5 4 3 2 1 0 EESTI DRn 1 gt Hlx is Output DRx 0 gt Hlx is Input X FFFFC8 Write Reset 0 Host Data Register 14 1 10 X FFFFC9 Write Reset Undefined 15 3 12 9 8 7 6 5 A4 3 2 1 0 LLL EEE EEE yee DRn holds value of corresponding HI08 GPIO pin Function depends on HDDR Figure B 25 Host Data Direction and Host Data Registers HDDR HDR B 36 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets GPIO Port C ESSIO STDO SRDOSCKO SC02 SC01 SC00 5 4 3 2 1 0 Port C Control Register H Pcs Pca Pes pce Pc Pco eT lial T ReadWrite Reset PCn 1 Port Pin configured as ESSI PCn 0 5 Port Pin configured as GPIO ReadWite Reset 5 4 3 2 1 0 Port C Direction Register H Pbc5 Poca Pocs Pbce Pbc1 Pbco wR ITTE E yo PDCn 1 gt Port Pin is Output PDCn 0 5 Port Pin is Input Readwritel Reset 5 4 3 2 1 0 Port C GPIO Data Register H Pps PD4 Pps Pp Ppt SETETE v yp If port pin n is GPIO input then PDn reflects the value on port pin n If port pin n is
331. n address that has to be processed by all sleeping processors that is each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters Motorola Serial Communication Interface SCI 8 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 4 SBK 0 Send Break A break is an all zero word frame a start bit 0 characters of all zeros including any parity and a stop bit O that is ten or eleven zeros depending on the mode selected If SBK is set and then cleared the transmitter finishes transmitting the current frame sends 10 or 11 Os and reverts to idle or sending data If SBK remains set the transmitter continually sends whole frames of Os 10 or 11 bits with no stop bit At the end of the break code the transmitter sends at least one high set bit before transmitting any data to guarantee recognition of a valid start bit Break can signal an unusual condition message and so on by forcing a frame error the frame error is caused by a missing stop bit SSFTD SCI Shift Direction Determines the order in which the SCI data shift registers shift data in or out MSB first when set LSB first when cleared The parity and data type bits do
332. n Figure 7 8 on page 7 27 Figure 7 9 on page 7 28 and Figure 7 10 on page 7 28 When MOD is cleared the Normal mode is selected when MOD is set the Network mode is selected In Normal mode the frame rate divider determines the word transfer rate one word is transferred per frame sync during the frame sync time slot In Network mode a word can be transferred every time slot For details see Section 7 3 12 SYN 0 Synchronous Asynchronous Controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to each other See Figure 7 7 on page 7 26 When SYN is cleared the ESSI is in Asynchronous mode and separate clock and frame sync signals are used for the transmit and receive sections When SYN is set the ESSI is in Synchronous mode and the transmit and receive sections use common clock and frame sync signals Only in Synchronous mode can more than one transmitter be enabled 11 CKP 0 Clock Polarity Controls which bit clock edge data and frame sync are clocked out and latched in If CKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock If CKP is set the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock 10 FSP 0 Frame Sync Polarity Determines the polarity of the rece
333. n external frame sync if GPIO is selected To assure correct operation either program the GPIO pins as outputs or configure the pins in the PCR as ESSI signals The default selection for these signals after reset is GPIO This note applies to both ESSIO and ESSI Motorola Enhanced Synchronous Serial Interface ESSI 7 23 For More Information On This Product Go to www freescale com ESSI Programming Model Freescale Semiconductor Inc Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description SCD1 0 Serial Control Direction 1 In Synchronous mode SYN 1 when transmitter 2 is disabled TE2 0 or in Asynchronous mode SYN 0 SCD1 controls the direction of the SC1 I O signal When SCD1 is set SC1 is an output when SCD1 is cleared SC1 is an input When TE2 is set the value of SCD1 is ignored and the SC1 signal is always an output SCDO Serial Control Direction 0 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0 or in Asynchronous mode SYN 0 SCDO controls the direction of the SCO I O signal When SCDO is set SCO is an output when SCDO is cleared SCO is an input When TE1 is set the value of SCDO is ignored and the SCO signal is always an output OF1 Serial Output Flag 1 In Synchronous mode SYN 1 when transmitter 2 is disabled TE2 0 the SC1 signal is configured as ESSI flag 1
334. n have the same or another format The selection is made by programming the CRB FSL 1 0 FSR and FSP bits 7 4 A Frame Sync Signal Format CRB FSL 1 controls the frame sync signal format m If CRB FSL1 is cleared the RX frame sync is asserted during the entire data transfer period This frame sync length is compatible with Motorola CODECSs serial peripherals that conform to the Motorola SPI serial A D and D A converters shift registers and telecommunication pulse code modulation serial I O m If CRB FSL1 is set the RX frame sync pulses active for one bit clock immediately before the data transfer period This frame sync length is compatible with Intel and National Semiconductor Corporation components CODECs and telecommunication pulse code modulation serial I O 1 Intel is a registered trademark of Intel Corporation Motorola Enhanced Synchronous Serial Interface ESSI 7 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Normal Network and On Demand 7 4 5 Frame Sync Length for Multiple Devices The ability to mix frame sync lengths is useful to configure systems in which data is received from one type of device for example CODEC and transmitted to a different type of device CRB FSL O0 controls whether RX and TX have the same frame sync length m If CRB FSLO is cleared both RX and TX have the same frame sync length m If CRB FSLO is set
335. nal X memory are switched to internal program memory and therefore the highest internal X memory location is 7FFF The X memory space at the switched locations 8000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSWTL 1 0 11 The 8K higher locations A000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 9FFF The X memory space at the switched locations A000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 The 10K lowest locations 0 27FF of the internal X memory are shared memory which is accessible to both the core and the EFCOP The EFCOP connects to the shared memory instead of the DMA bus so there is no DMA accessibility to shared memory Simultaneous accesses by the core and the EFCOP to the same memory bank 1024 locations of the shared memory are not permitted It is the programmer s responsibility to prevent such simultaneous accesses DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Y Data Memory Space 3 2 3 Internal X I O Space One part of the on chip peripheral registers and some of the DSP56311 core registers occupy the top 128 locations of the X data memory FFFF80 FFFFFF This area is referred to as the internal X I O space and
336. nc Data Transfer 10 6 Data Transfer This section describes how to transfer data to and from the EFCOP using an FIR filter configuration Here we provide background information to help you understand the examples in Section 10 7 Examples of Use in Different Modes on page 10 22 The examples employ the following notations m D n Data sample at time n m H n Filter coefficient at time n m Fn Output result at time n a filter_count Number of coefficient values in the coefficient memory bank FCM it is equal to the initial value written to the FCNT register plus 1 m Compute Perform all calculations to determine one filter output F n for a specific set of input data samples To transfer data to from the EFCOP input output registers the Filter Data Input Register FDIR and the Filter Data Output Register FDOR are triggered by three different methods m Direct Memory Access DMA m Interrupts m Polling Two FCSR bits FDIBE and FDOBF indicate the status of the FDIR and the FDOR respectively All three data transfer methods use these two FCSR bits as their control mechanism If FDIBE is set the input buffer is empty if FDOBF is set the output buffer is full Because these bits come into full operation only when the EFCOP is enabled FCSR FEN is set the polling DMA or interrupt methods can be initialized either before or after the EFCOP is enabled No service request is issued until the EFCOP is enabled since FDIBE
337. nc Frames do not have to be adjacent that is a new frame sync does not have to follow the previous frame immediately Gaps of arbitrary periods can occur between frames AII the enabled transmitters are tri stated during these gaps 7 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Normal Network and On Demand 7 4 8 Byte Format LSB MSB for the Transmitter Some devices such as CODECs require a MSB first data format Other devices such as those that use the AES EBU digital audio format require the LSB first To be compatible with all formats the shift registers in the ESSI are bidirectional You select either MSB or LSB by programming CRB SHFD m If CRB SHFD is cleared data is shifted into the receive shift register MSB first and shifted out of the transmit shift register MSB first m If CRB SHFD is set data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first 7 4 9 Flags Two ESSI signals SC 1 0 are available for use as serial I O flags Their operation is controlled by the SYN SCD 1 0 SSCI and TE 2 1 bits in the CRB CRA The control bits OF 1 0 and status bits IF 1 0 are double buffered to and from SC 1 0 Double buffering the flags keeps the flags in sync with TX and RX The SC 1 0 flags are available in Synchronous mo
338. nce is to write data to one or more transmit data registers or the time slot register TSR before you set the TE bit The normal transmit disable sequence is to set the transmit data empty TDE bit and then to clear the TE transmit interrupt enable TIE and transmit exception interrupt enable TEIE bits In Network mode if you clear the appropriate TE bit and set it again then you disable the corresponding transmitter 0 1 or 2 after transmission of the current data word The transmitter remains disabled until the beginning of the next frame During that time period the corresponding SC or STD in the case of TXO signal remains in a high impedance state The CRB bits are cleared by either a hardware RESET signal or a software RESET instruction Table 7 4 ESSI Control Register B CRB Bit Definitions Bit Number Bit Name Reset Value Description 23 REIE 0 Receive Exception Interrupt Enable When the REIE bit is set the DSP is interrupted when both RDF and ROE in the ESSI status register are set When REIE is cleared this interrupt is disabled The receive interrupt is documented in Section 7 3 3 Exceptions on page 7 8 A read of the status register followed by a read of the receive data register clears both ROE and the pending interrupt Motorola Enhanced Synchronous Serial Interface ESSI 7 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Progr
339. nctions as a GPIO signal only when the TC 3 0 bits are cleared If any of the TC 3 0 bits are set then the GPIO function is disabled and the DIR bit has no effect 10 Reserved Write to zero for future compatibility TRM Timer Reload Mode Controls the counter preload operation In timer 0 3 and watchdog 9 10 modes the counter is preloaded with the TLR value after the TCSR TE bit is set and the first internal or external clock signal is received If the TRM bit is set the counter is reloaded each time after it reaches the value contained by the TCR In PWM mode 7 the counter is reloaded each time counter overflow occurs In measurement 4 5 modes if the TRM and the TCSR TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running counter and is incremented on each incoming event INV Inverter Affects the polarity definition of the incoming signal on the TIO signal when TIO is programmed as input It also affects the polarity of the output pulse generated on the TIO signal when TIO is programmed as output See Table 9 4 Inverter INV Bit Operation on page 9 28 The INV bit does not affect the polarity of the prescalar source when the TIO is input to the prescalar NOTE The INV bit affects both the timer and GPIO modes of operation To ensure correct operation change this
340. nel 0 01 0 0 0 1 FIR Complex Alternating single channel 0 10 0 0 0 1 FIR Magnitude single channel 0 11 0 0 0 1 IIR Real single channel 0 00 0 0 1 1 IIR Real multichannel 1 00 0 0 1 1 NOTES 1 An x indicates that the specified value can be 1 or O 2 If the user sets the FUPD bit the EFCOP updates the coefficients and clears the FUPD bit The adaptive mode that is FADP 1 sets the FUPD bit which causes the EFCOP to update the coefficients and then automatically clear the FUPD bit Therefore the value assigned to the FUPD bit in this table refers only to its initial setting and not its dynamic state during operation 3 All bit combinations not defined by this table are reserved for future development Motorola Enhanced Filter Coprocessor EFCOP 10 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation Summary 10 5 Operation Summary The EFCOP is very easy to use To define the type of filtering to perform you need only set the following registers the settings in the FDCH and FACR are optional and then enable the EFCOP by setting FCSR FEN m FCNT m FDBA m FCBA m FCSR Polling DMA or interrupts can then be used to write data to the FDIR and read data from the FDOR As Table 10 9 shows the EFCOP operates in many different modes based on the settings of the control registers However the EFCOP performs only two basic types of proc
341. new data to be transmitted and a transmit time slot occurs When a transmit underrun error occurs the previous data which is still present in the TX registers not written is retransmitted In Normal mode there is only one transmit time slot per frame In Network mode there can be up to 32 transmit time slots per frame If the TEIE bit is set a DSP transmit underrun error interrupt request is issued when the TUE bit is set The programmer can also clear TUE by first reading the SSISR with the TUE bit set then writing to all the enabled transmit data registers or to the TSR 3 RFS 0 Receive Frame Sync Flag When set the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register In other words the data word is from the first time slot in the frame When the RFS bit is cleared and a word is received it indicates only in Network mode that the frame sync did not occur during reception of that word RFS is valid only if the receiver is enabled that is if the RE bit is set NOTE In Normal mode RFS is always read as 1 when data is read because there is only one time slot per frame the frame sync time slot 2 TFS 0 Transmit Frame Sync Flag When set TFS indicates that a transmit frame sync occurred in the current time slot TFS is set at the start of the first time slot in the frame and cleared during all other time slots If the transmitter is enabled data written to a
342. nformation On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview 10 2 1 PMB Interface The PMB interface block contains control and status registers buffers the internal bus from the PMB decodes and generates addresses and controls the handshake signals required for DMA and interrupt operations The block generates interrupt and DMA trigger signals for data transfers The interface registers accessible to the DSP56300 core through the PMB are summarized in Table 10 1 Table 10 1 EFCOP Registers Accessible Through the PMB Register Name Description Filter Data Input Register FDIR A 4 word deep 24 bit wide FIFO used for DSP to EFCOP data transfers Data from the FDIR is transferred to the FDM for filter processing Filter Data Output Register FDOR A 24 bit wide register used for EFCOP to DSP data transfers Data is transferred to FDOR after processing of all filter taps is completed for a specific set of input samples Filter K Constant Input Register FKIR A 24 bit register for DSP to EFCOP constant transfers Filter Count FCNT Register A 24 bit register that specifies the number of filter taps The count stored in the FCNT register is used by the EFCOP address generation logic to generate correct addressing to the FDM and FCM EFCOP Control Status Register FCSR A 24 bit read write register used by the DSP56300 core to program the EFCOP and t
343. ng Complex Mode Alternating Complex mode performs FIR type filtering with complex data providing alternating real and complex results based on the following equations N 1 Y Re H Re D n i ImQTG Im D n i i 0 N 1 Im F n 4g Y ReGHG ImQX n i ImQHG Re D n i i 0 Re F n even where H n is the coefficients D n is the input data and F n is the output data at time n Two samples the real part then the imaginary part of the input are written to the FDIR The EFCOP processes the data Then one sample alternating between the real part and the imaginary part of the output is read from the FDOR Alternating Complex mode is selected by setting the FCSR FOM bits to 10 In Alternating Complex mode the number written to the FCNT register should be twice the number of filter coefficients Also the coefficients should be stored in the FCM with the real part of the coefficient in the memory location preceding the memory location holding the imaginary part of the coefficient Motorola DSP56311 User s Manual 10 18 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation Summary 10 5 1 1 5 Magnitude Mode Magnitude mode calculates the magnitude of an input signal based on the following equation IN Fn Y D n iy i 0 where D n is the input data and F n is the output data at time n One sample the real input is written to the FDIR
344. ng status registers 5 2 receive and transmit data paths 6 4 Receive Byte Registers 6 6 Receive Byte Registers RXH RXM RXL 6 30 Receive Clock Mode Source bit RCM 8 21 Receive Data Register RX 7 31 Receive Data signal RXD 8 4 Receive Exception Interrupt Enable bit REIE 7 19 Receive Exception Interrupt enable 7 19 receive frame sync edge ESSI 7 12 Receive Frame Sync Flag bit RFS 7 30 Receive Shift Register 7 31 Receive Slot Mask Registers RSMA RSMB 7 35 Received Bit 8 Address bit R8 8 17 Receiver Enable bit RE 8 14 Receiver Wakeup Enable bit SBK 8 15 register banks 6 4 REIE bit 7 19 RESET 2 10 reset bus signals 2 6 2 7 clock signals 2 5 essi signals 2 15 2 17 host interface signals 2 11 interrupt signals 2 10 JTAG signals 2 21 mode control 2 10 OnCE signals 2 21 phase lock loop signals 2 6 sci signals 2 19 timers 2 20 resets hardware and software 6 4 reverse carry adder 1 7 RFS bit 7 30 ROM bootstrap 3 1 3 3 RSMA and RSMB 7 14 7 35 RSMA RSMB registers 7 35 RWU bit 8 15 RX 7 14 7 31 RX register 7 31 RXD 8 4 RXD signal 8 4 RXH RXM RXL registers 6 30 Motorola DSP56311 User s Manual S saturation status bit 10 2 SBK bit 8 16 SC register 1 8 SCO 7 4 SCO signal 7 4 7 5 SC1 7 5 SC2 7 6 SC2 and SC1 signals programmed as outputs 7 23 SCCR 8 19 SCDO bit 7 24 SCDI bit 7 24 SCI 1 13 2 3 2 19 5 2 8 9 Clock Control Register 8 19 Control Register 8 12 data registers 8 22 e
345. ng up the interrupt routine The interrupt handler is located at the interrupt starting address The interrupt routines can be short only two opcodes long or long more than two opcodes and requiring a JSR instruction 2 Enabling the interrupts a Setthe corresponding bits in the applicable peripheral control register b Enable peripheral interrupts in the Interrupt Priority Register IPRP c Enable global interrupts in the Mode Register MR portion of the Status Register SR Events that change bits in the peripheral control registers can then trigger the interrupt Depending on the peripheral from two to six peripheral interrupt sources are available to the programmer Example 5 2 shows a short interrupt programmed for the HIO8 The main program enables the Host Receive Interrupt in the Host Control Register HCR When the interrupt is triggered during code execution the core processing jumps to the Host Receive Interrupt routine location at p 60 and executes the code there Since this is a short interrupt the core returns to normal code execution after executing the two move instructions and an RTI instruction is not necessary Example 5 2 Interrupts bset 4M HRIE x M HCR enable host receive interrupt Short Interrupt Routine org P 60 movep x M HRX xl HI08 Receive Data Full interrupt move x1 y r0 Motorola DSP56311 User s Manual 5 4 For More Information On This Product Go to
346. not change their position in the frame and they remain adjacent to the stop bit WDS 2 0 Word Select Select the format of transmitted and received data Asynchronous modes are compatible with most UART type serial devices and they support standard RS232C communication links Multidrop Asynchronous mode is compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface Synchronous data mode is essentially a high speed shift register for I O expansion and stream mode channel interfaces You can synchronize data by using a gated transmit and receive clock compatible with the Intel 8051 serial interface mode 0 When odd parity is selected the transmitter counts the number of ones in the data word If the total is not an odd number the parity bit is set thus producing an odd number If the receiver counts an even number of ones an error in transmission has occurred When even parity is selected an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred WDS2 WDS1 WDSO Mode Word Formats 0 0 0 O 8 Bit Synchronous Data shift register mode Reserved 10 Bit Asynchronous 1 start 8 data 1 stop Reserved 11 Bit Asynchronous 1 start 8 data 1 even parity 1 stop 11 Bit Asynchronous 1 start 8 data 1 odd parity 1 stop 11 Bit Multidrop Asynchronous 1 start 8 data 1 data type
347. nterrupt DMA Channel Enable Bit 23 0 Disables channel operation 1 Enables channel operation 23 22 21 20 19 18 17 Y Wu pow 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DMA Destination Space Bits 3 2 DSS 1 0 DMA Destination Memory 00 X Memory Space 01 Y Memory Space 10 P Memory Space 11 Reserved DMA Source Space Bits 1 0 DSS 1 0 DMA Source Memory 00 X Memory Space 01 Y Memory Space 10 P Memory Space 11 Reserved Y 1 DMA Control Registers DCR5 DCRO Reset 000000 B 16 Figure B 5 DMA Control Register DCR DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Programming Sheets eiuw peeu 3344344 X OTVI VIVI c1VI ogar 21 crar 0101 ss NH 10g rioa ce v G 9 2 8 6 OI O udl 49181694 Kjuoug 1dnueiu ra oxa riza oiea r1ea oira ara orsa Isa LL ZL EF VE SL OL ZL 8L 6L OS Ie ce ez 6p4 DeN L 1949 0 1ebBu p e1di 3spowW qoul 96p3 DeN L ON leae 0 paiqeu3 bu p z1al 9po N goul obp3 ben 19497 so66uL L 0 L ON 0 0191 peiqeu3 I 01VI epo DOU obp3 ben
348. nterrupt Enable Enables disables the SCI receive data with exception interrupt If REIE is cleared the receive data with exception interrupt is disabled If both REIE and RDRF are set and PE FE and OR are not all cleared the SCI requests an SCI receive data with exception interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears REIE 15 SCKP 0 SCI Clock Polarity Controls the clock polarity sourced or received on the clock signal SCLK eliminating the need for an external inverter When SCKP is cleared the clock polarity is positive when SCKP is set the clock polarity is negative In Synchronous mode positive polarity means that the clock is normally positive and transitions negative during valid data Negative polarity means that the clock is normally negative and transitions positive during valid data In Asynchronous mode positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid Negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid Either a hardware RESET signal or a software RESET instruction clears SCKP 14 STIR 0 Timer Interrupt Rate Controls a divide by 32 in the SCI Timer interrupt generator When STIR is cleared the divide by 32 is inserted in the chain When STIR is set the divide by 32 is bypassed thereby increasing timer resolution by a
349. nterrupt equate file is included Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt pir STOTB 2 Configure interrupt trigger preload transmit data a mone oF Note Motorola Enable and prioritize overall peripheral interrupt functionality IPRP S0L1 0 Write data to all enabled transmit registers TX00 Enable a peripheral interrupt generating function CRB TEO Enable a specific peripheral interrupt CRBO TIE Enable peripheral and associated signals PCRC POC 5 9 Unmask interrupts at the global level SR I1 w 0 The example material to the right of the steps shows register settings for configuring an ESSIO transmit interrupt using transmitter 0 The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration is complete Since step c may cause an immediate transmit without generating an interrupt perform the transmit data preload in step b before step c to ensure that valid data is sent in the first transmission After the first transmit subsequent transmit values are typically loaded into TXnn by the ISR one value per register per interrupt Therefore if N items are to be sent from a particular TXnn the ISR needs to load the transmit register N 1 times Steps c and d can be performed in step a as a single instruction If an interrupt trigger event occur
350. ntervention Core concurrent operation with minimal core intervention 1 For details on DFI and DFII modes refer to the Motorola application note entitled Implementing IIR FIR Filters with Motorola s DSP56000 DSP56001 APR7 D Motorola DSP56311 User s Manual 10 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview 10 2 Architecture Overview As Figure 10 1 shows the EFCOP comprises these main functional blocks m Peripheral module bus PMB interface including Data input buffer Constant input buffer Output buffer Filter counter m Filter data memory FDM bank m Filter coefficient memory FCM bank m Filter multiplier accumulator FMAC machine m Address generator m Control logic DMA BUS PMB Interface GDB BUS Y Memory Shared 4 Word FBIR Data Input Buffer FONT RAM Control Filter Count 1 Logic FCBA l FCM I poo 70 Coeff Base Ad I I X Memory I FDM I FDBA COEFFICIENT Shared I r Data Base Ad Memory Bank RAM DATA 24 bit I I l Memory Bank Address L J 24 bit Generator L T ol FKIR FMAC Filter Constant a 24x24 gt 56 bit gt Rounding amp Limiting Output Buffer FDOR Figure 10 1 EFCOP Block Diagram Motorola Enhanced Filter Coprocessor EFCOP 10 3 For More I
351. ntiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The host MCU can terminate the loading process by setting the HF1 0 and HFO 1 When the downloading is terminated the program starts executing the leaded program from the specified starting address The HI08 boot ROM program enables the following buses to download programs through the HI08 port 1 ISA Dual strobe non multiplexed bus with negative strobe pulses dual positive request 2 HCII Single strobe non multiplexed bus with positive strobe pulse single negative request 4 18051 Dual strobe multiplexed bus with negative strobe pulses dual negative request A 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Code 5 MC68302 Single strobe non multiplexed bus with negative strobe pulse single negative request gt MC68302HOSTLD movep 0000000000111000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negative chip select input HD HS 0 Single strobe bus R W and DS HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 0 Negative data strobes polarity HROD 0 Host reques
352. nual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 24 R Control Status TL Load Count Compare Register Register Register Register 24 24 24 Timer Control B Counter Logic TIO CLK 2 Prescalar CLK Timer interrupt DMA request Operation GDB 24 Figure 9 2 Timer Module Block Diagram 9 2 2 Timer Initialization To initialize a timer do the following 1 Ensure that the timer is not active either by sending a reset or clearing the TCSR TE bit 2 Configure the control register TCSR to set the timer operating mode Set the interrupt enable bits as needed for the application 3 Configure other registers Prescalar Load Register TPLR Load register TLR and Compare register TCPR as needed for the application 4 Enable the timer by setting the TCSR TE bit 9 2 3 Timer Exceptions Each timer can generate two different exceptions m Timer Overflow highest priority Occurs when the timer counter reaches the overflow value This exception sets the TOF bit TOF is cleared when a value of one is written to it or when the timer overflow exception is serviced m Timer Compare lowest priority Occurs when the timer counter reaches the value given in the Timer Compare Register TCPR for all modes except Motorola Triple Timer Module 9 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
353. o examine the status of the EFCOP module EFCOP ALU Control Register FACR A 24 bit read write register used by the DSP56300 core to program the EFCOP data ALU operating modes EFCOP Data Buffer Base Address FDBA A 16 bit read write register used by the DSP56300 core to indicate the EFCOP the data buffer base start address pointer in FDM RAM EFCOP Coefficient Buffer Base Address FCBA A 16 bit read write register by which the DSP56300 core indicates the EFCOP coefficient buffer base start address pointer in FCM RAM Decimation Channel Count Register FDCH A 24 bit register that sets the number of channels in multichannel mode and the filter decimation ratio The EFCOP address generation logic uses this information to supply the correct addressing to the FDM and FCM 10 2 2 EFCOP Memory Banks The EFCOP contains two memory banks m Filter Data Memory FDM This 24 bit wide memory bank is mapped as X memory and stores input data samples for EFCOP filter processing The FDM is written via a 4 word FIFO FDIR and its addressing is generated by the EFCOP address generation logic The input data samples are read sequentially from the FDM into the MAC The FDM is accessible for writes by the core and the DMA controller and is shared with the 10K lowest locations 0 2800 of the on chip internal X memory Motorola DSP56311 User s Manual For More Information On This Product Go to w
354. o can be programmed from 1 to 16 For Real and Magnitude modes the decimation ratio number of samples must be written to the FDIR before an output sample is read from the FDOR For Complex mode two times the decimation ratio number of samples one for the real part and one for the imaginary part of the input must be written to the FDIR before two output samples one for the real part and one for the imaginary part of the output can be read from the FDOR For Alternating Complex mode two times the decimation ratio number of samples must be written to the FDIR one for the real part and one for the imaginary part of the input before one output sample alternating between the real part and the imaginary part of the output can be read from the FDOR Motorola Enhanced Filter Coprocessor EFCOP 10 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation Summary 10 5 2 IIR Filter Type To select the IIR filter type set the FCSR FLT bit and perform the processing shown in Figure 10 8 based on the equation shown here The EFCOP multiplies each previous M y n sme y Ap j 1 output value in the FDM by the corresponding coefficient A stored in the FCM accumulates the multiplication results adds the input w n from the FDIR which is optionally not scaled by S depending on the FACR FISL bit setting places the accumulation result y n in the FDOR and saves the output while shif
355. o two 4M x 24 bit word memory spaces by using the Address Attribute AAO AA3 signals m Program memory expansion to one 256K x 24 bit word memory space or up to one 4M x 24 bit word memory spaces by using the Address Attribute AAO AA3 signals Further features of off chip memory include the following m External memory expansion port W Simultaneous glueless interface to static RAM SRAM and dynamic RAM DRAM 1 6 Internal Buses To provide data exchange between the blocks the DSP56311 implements the following buses Peripheral I O expansion bus to peripherals Program memory expansion bus to program ROM X memory expansion bus to X memory Y memory expansion bus to Y memory Global data bus between PCU and other core structures Program data bus for carrying program data throughout the core X memory data bus for carrying X data throughout the core Y memory data bus for carrying Y data throughout the core Program address bus for carrying program memory addresses throughout the core X memory address bus for carrying X memory addresses throughout the core Y memory address bus for carrying Y memory addresses throughout the core The block diagram in Figure 1 1 illustrates these buses among other components 1 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Block Diagram 1 7 Block Diagram All internal buses on the DSP56300 family mem
356. o written to the TCF bit has no effect The bit is also cleared when the timer compare interrupt is serviced The TCF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TCSR TE bit to disable the timer NOTE The TOF and TCF bits are cleared by a 1 written to the specific bit To ensure that only the target bit is cleared do not use the BSET command The proper way to clear these bits is to write 1 using a MOVEP instruction to the flag to be cleared and O to the other flag 20 TOF 0 Timer Overflow Flag Indicates that a counter overflow has occurred This bit is cleared by a one written to the TOF bit A zero written to TOF has no effect The bit is also cleared when the timer overflow interrupt is serviced The TOF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TCSR TE bit to disable the timer 19 16 0 Reserved Write to zero for future compatibility 15 PCE 0 Prescalar Clock Enable Selects the prescalar clock as the timer source clock When PCE is cleared the timer uses either an internal CLK 2 signal or an external TIO signal as its source clock When PCE is set the prescalar output is the timer source clock for the counter regardless of the timer operating mode To ensure proper operation the PCE bit is changed only when the timer is disabled The PS 1 0 bits of the TPLR dete
357. ol Register PCR PCRC X FFFFBF PCRD X FEFAF oeeadetamneterdi4excu ohh Shee dade her Bua 7 37 Port Direction Register PRR PRRC X FFFFBE PRRD X SEPBEAXEJ s ua x vauo n REenREWERTAXS XA A4 RkaswR Ra E Ra 7 37 Port Data Register PDR PDRC X FFFFBD PDRD X FFFFAD 2 scncadaaceneteenecudadwsoeaekeweegnes 7 38 SCI Data Word Formats SSFTD21 1 0 0 0 eee eee 8 10 SCI Data Word Formats SSFTD 0 2 eeeees 8 11 SCI Control Register OCIO usoRsre arena exar e eee RAE eaves 8 12 SCI Status Register 25 o 2ceendece de Da Ree ERG HEX YR EO RR 8 17 SCI Clock Control Register SCCR 054 u dE Re RRIPEERRSERPER 8 19 Tox Serial Clock assu xh ao gen qe bte vr Sues wie RERO ac dde Y DS 8 20 SCI Baud Rate Generar iussus n esxe EA RS RES EATASAECENR 8 22 SCI Programming Model Data Registers llle 8 23 Port E Control Register PORE 4 1004043 censeo he mw ren 8 25 Pott E Direction Register PRRE ecu ees seeds RR ER RE RE 8 26 Port E Data Register PDRE 0 0 0 cece eee eee 8 27 Triple Timer Module Block Diagram 0 00 00 ee eee eee 9 2 Timer Module Block Diagram 225294 2os Se em x ERR EERE REY RR xS 9 3 Timer Mode TRM l u og uacua ade EORR RR CR a Eae Salk DR s a 9 6 Tuner Mode TRM ud us Loa pd E Ra E E RERO E PEAN d Re DPI xs 9 6 Pulse Mode TRM SS T sess reanna dre ace epee eee ed ace epar 9 7 Pulse Mode TRM U os uus sx ERE tet eee RICE e RR 9 8 Toggle Mode T
358. on and describe the bit settings memory sizes and memory locations Note In 16 bit mode if the MS mode bit in the Operating Mode Register OMR is set external program memory is not accessible so enabling the instruction cache is of little benefit In addition certain 16 bit modes prevent you from accessing the entire internal DSP56311 memory space 3 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Program FFFFFF FFFFFF FFFF80 FFFO000 Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 External Default X Data Internal Reserved External FFFFFF Internal I O SFFFFCO FFFF80 FFF000 FF0000 Y Data External O Internal I O Internal Reserved External Memory Maps 00C000 00C000 008000 Internal Program RAM Internal X data RAM 48K Internal Y data RAM 32K 48K 000000 000000 000000 Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 0 any 0 0 32K 48K 48K None 16M value 0000 7FFF 0000 BFFF 0000 BFFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Motorola Figure 3 1 Memory Switch Off Cache Off 24 Bit Mode Default Memo
359. ootstrap program sets the host interface to interface with the Motorola HC11 microcontroller through the HIO8 The HI08 pin configuration is optimized for connection to the Motorola HC1 1 nonmultiplexed bus FF0000 HI08 bootstrap in 8051 multiplexed bus mode The bootstrap program sets the host interface to interface with the Intel 8051 bus through the HI08 The program stored in this location after testing MODA MODB MODC and MODD bootstraps through HI08 The HI08 pin configuration is optimized for connection to the Intel 8051 multiplexed bus FF0000 HI08 bootstrap in MC68302 bus mode The bootstrap program sets the host interface to interface with the Motorola MC68302 or MC68360 bus through the HIO8 The HI08 pin configuration is optimized for connection to a Motorola MC68302 or MC68360 bus Motorola Core Configuration 4 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program 4 2 Bootstrap Program The bootstrap program is factory programmed in an internal 192 word by 24 bit bootstrap ROM located in program memory space at locations FFOOO0 FFOOBF The bootstrap program can load any program RAM segment from an external byte wide EPROM the SCI or the host port The bootstrap program code is listed in Appendix A Upon exiting the Reset state the DSP56311 samples the MODA MODD signal lines and loads their values into OMR MA
360. or Inc 10 5 1 1 4 Alternating Complex Mode 0 0 0 eee ee eee ees 10 5 1 1 5 Magnit d NIOUB s s pcan Rb PetibRPREE ia BER PR PLE RETI A ROSE RES 10 5 1 1 6 Dutalzult 124 0 eossdte4 teehee en hooks on Peeks E ERR KNEE LA sees 10 5 1 1 7 Decimation eerder SuxeeeeS ect seev sO cedere Geese RARE ERE BAUR EE 10 5 2 TIR Filter VypG sc non dep utut RICERCA see GC ODER IR a blo actore Ml ecc 10 6 Data Transfer iis caca shige ER GA Ria p Ede RE HE Exe E Sd e ipe RES 10 7 Examples of Use in Different Modes z 3 2scs2cecss4 RE RXTuRIE Ea RE 10 7 1 Real FIR Filter Mode U edessos es ach ere hx REX Te Re Rx T Sed 10 7 1 1 DMA Inpu DMA Output 2 2 ne 10 7 2 DMA Inp t Polling Quint cedes dyaed ee RD ER n owen dg DX REUS 10 7 1 3 DMA Input Interrupt Output leseeeeeeeee IRI 10 7 2 Real FIR Filter With Decimation byM 0 0 0 cee eee eee eee 10 7 3 Adaptive FIR Filler iocus RE RERR RR RR ARR RR RRERE E ER AER 10 7 3 1 Implementation Using Polling eseeeeee BRI 10 7 3 2 Implementation Using DMA Input and Interrupt Output 10 7 3 3 Updating an FIR Mier sus bd ci Ee RE EEUU IZ PERPE RUTAS A PERSE AE 10 8 Verification For All Bxereises osse os edess cede beer DRESSER RE ERG E 10 8 1 Input Sequence input asm 1 0 IRI 10 8 2 Filter Coefficients coefs asm 0 cee e 10 8 3 Output Sequence for Examples D 1 D 2 and D 3 040 10 8 4 Desired Signal for Example D 4
361. or Inc ESSI Programming Model Asynchronous SYN 0 Transmitter Frame SYNC External Transmit Frame ESSI Bit Internal Frame SYNC Frame SYNC Receiver NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 Transmitter Frame SYNC External Frame SYNC Internal Frame SYNC 4 sck gt External Clock n ESSI Bit Internal Clock Clock Receiver NOTE Transmitter and receiver may have the same clock frame syncs Figure 7 7 CRB SYN Bit Operation 7 26 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model peuiejsueJ eq ACW pJo e pue 1oJs awy Aaaa 1n990 sjdnueju 3 LON 19S she 4 pue jisenbeu WING JO 1dnue1ju 19418909H Y Y Y Y Y Y Y Y Y Y pue jsenbay WIG 10 sidnueiu JoyIWWSUe L ONAS 9UJEJ4 390 E HeSs L GOW PON 10M 9N ouAS BWed Jed BOUO paJJeJsueJ si eyep pue jn290 sjdnueju 3 LON Y sDe J pue 1senbeu Ywa 10 1dnueju 19419284 Y Y pue jsonbey Ya 10 1dnueju 1emiuusuei L Y ONAS 9UJEJ4 31H WQV3u GYD g 13481694 01u09 SS yoo D eues 0 GOW PON jeuuoN Figure 7 8 CRB MOD Bit Operation 7 27 Enhanced Synchronous Serial Interface ESSI Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Frame
362. or a single CODEC with asynchronous transmit and receive SC1 is the receiver frame sync I O In Synchronous mode SC1 is the transmitter data out signal of transmit shift register TX2 for the transmitter O drive enabled signal or for serial flag I O As serial flag I O SC1 operates like SCO SCO and SClare independent flags but can be used together for multiple serial device selection they can be unencoded to select up to two CODECS or decoded externally to select up to four CODECs If SC1 is configured as a serial flag or receive frame sync signal the Serial Control Direction 1 CRB SCD1 bit determines its direction Table 7 2 Mode and Signal Definitions Control Bits ESSI Signals SYN TEO TE1 TE2 RE SCO SC1 SC2 SCK STD SRD 0 0 X X 0 U U U U U U 0 0 X X 1 RXC FSR U U U RD 0 1 X X 0 U U FST TXC TDO U 0 1 X X 1 RXC FSR FST TXC TDO RD 1 0 0 0 0 U U U U U U 1 0 0 0 1 FO U F1 TOD U FS XC U RD 1 0 0 1 0 FO U TD2 FS XC U U 1 0 0 1 1 FO U TD2 FS XC U RD 1 0 1 0 0 TD1 F1 TOD U FS XC U U 1 0 1 0 1 TD1 F1 TOD U FS XC U RD 1 0 1 1 0 TD1 TD2 FS XC U U 1 0 1 1 1 TD1 TD2 FS XC U RD 1 1 0 0 0 FO U F1 TOD U FS XC TDO U 1 1 0 0 1 FO U F1 TOD U FS XC TDO RD 1 1 0 1 0 FO U TD2 FS XC TDO U 1 1 0 1 1 FO U TD2 FS XC TDO RD 1 1 1 0 0 TD1 F1 TOD U FS XC TDO U 1 1 1 0 1 TD1 F1 TOD U FS XC TDO RD 1 1 1 1 0 TD1 TD2 FS XC TDO U 1 1 1 1 1 TD1 TD2 FS XC TDO R
363. or asynchronous mode this signal will be used for the receive clock I O Schmitt trigger input For synchronous mode this signal is used either for transmitter 1 output or for serial I O flag 0 Port C 0 The default configuration following reset is GPIO input PCO When configured as PCO signal direction is controlled through the port directions register PRRO The signal can be configured as ESSI signal SC00 through the port control register PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SCO01 PC1 Input Output Input or Output Input Serial Control 1 The function of this signal is determined by the selection of either synchronous or asynchronous mode For asynchronous mode this signal is the receiver frame sync I O For synchronous mode this signal is used either for transmitter 2 output or for serial I O flag 1 Port C 1 The default configuration following reset is GPIO input PC1 When configured as PC1 signal direction is controlled through PRRO The signal can be configured as an ESSI signal SC01 through PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SCO02 PC2 Input Output Input or Output Input Serial Control Signal 2 Used for frame sync I O SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in a
364. os Port Vector Required No Vector Required GPIO Mode ignal HREQ HREQ HREQ HTRQ HTRQ PB14 HTRQ HACK HACK HACK HRRQ HRRQ PB15 HRRQ The HIOS8 port can operate in multiplexed or non multiplexed mode In multiplexed mode HPCR 11 HMUX 1 the lower eight address signals multiplex with the eight data lines In non multiplexed mode HPCR 11 HMUX 0 the HI08 requires a chip select signal and three address lines to select one of the eight registers accessible to the host Eight lines are used for data The HI08 port can also be programmed to use a single or dual read write data strobe and single or double host request line Software and hardware resets clear all DSP side control registers and configure the HI08 as GPIO with all 16 signals disconnected To select GPIO functions clear HPCR bits 6 through 1 to select other HIO8 functions set those same bits If the HI08 is in GPIO mode the HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set For details see Section 6 6 3 Host Data Direction Register HDDR on page 6 16 and Section 6 6 4 Host Data Register HDR on page 6 16 6 3 Overview The HIOS is partitioned into two register banks as Figure 6 1 shows The host side register bank is accessible only to the host and the DSP side register bank is accessible only to the DSP core For the host the HI08 appears as eight byte wide locations map
365. ost Receive Data Full bit in the Host Status register HSR 0 HRDF A similar mechanism is available on the host side to determine the state of the Transmit Registers TXH TXM TXL and Receive Registers RXH RHM RHL Two bits are provided to the host for polling m the Transmit Data Empty bit in the Interface Status Register ISR 1 TXDE W the Receive Data Full bit in the Interface Status Register ISR 0 RXDF The HIOS also offers four general purpose flags for communication between the host and the DSP The DSP side uses the HSR Host Flag bits HCR 4 3 HF3 HEF2 to pass application specific information to the host The status of HF3 HF2 is reflected in the host side ISR Host Flag bits ISR 4 3 HF3 HF2 Similarly the host side can use the ICR Host Flag bits ICR 4 3 HF1 HF0 to pass application specific information to the DSP The status of HF1 HFO is reflected in the DSP side HSR Host Flag bits HSR 4 3 2HF1 HF0 6 4 2 Core Interrupts and Host Commands The HIO08 can request interrupt service from the DSP56311 core The DSP56311 core interrupts are internal and do not require the use of an external interrupt signal When the appropriate interrupt enable bit in the HCR is set an interrupt condition caused by the host interface sets the appropriate bit in the HSR generating an interrupt request to the DSP56311 interrupt controller see Figure 6 2 The DSP56311 acknowledges interrupts Motorola Host Interface H108 6 7
366. ost bus and the HI function is selected this signal is the host write data strobe HWR Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HWR following reset Port B 12 When the HIO8 is configured as GPIO through the HPCR this signal is individually programmed as an input or PB12 Input or output through the HDDR Output NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated HCS Input Input Host Chip Select When HIO8 is programmed to interface a nonmultiplexed host bus and the HI function is selected this signal is the host chip select HCS input The polarity of the chip select is programmable but is configured active low HCS after reset Host Address 10 When HIO8 is programmed to interface a HATO Input multiplexed host bus and the HI function is selected this signal is line 10 of the host address HA10 input bus Port B 13 When the HIO8 is configured as GPIO through the PB13 Input or HPCR this signal is individually programmed as an input or Output output through the HDDR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated Motorola Signals Connections 2 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Synchronous Serial Interface 0 Table 2 10 Host Interface Continued State
367. ounter TCR gt 0 N N 1 M 1d 1 0 gt 1 TCPR gt lt TCF Compare Interrupt if TCIE 1 NEN TOF Overflow Interrupt if TCIE 1 NOTE If INV 1 counter is clocked on 1 to 0 clock transitions instead of 0 to 1 transitions Figure 9 10 Event Counter Mode TRM 0 9 3 2 Signal Measurement Modes The following signal measurement and pulse width modulation modes are provided Measurement input width Mode 4 Measurement input period Mode 5 Measurement capture Mode 6 Pulse width modulation mode Mode 7 The external signal synchronizes with the internal clock that increments the counter This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle Motorola Triple Timer Module 9 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 2 1 Measurement Input Width Mode 4 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 0 0 4 Input width Measurement Input Internal In Mode 4 the timer counts the number of clocks that occur between opposite edges of an input signal After the first appropriate transition as determined by the TCSR INV bit occurs on the TIO input signal the counter is loaded with the TLR value If TCSR INV is set th
368. p 128 words of X data memory SFFFF80 FFFFFF Referred to as the internal I O space the control registers are accessed by move MOVE MOVEP instructions and bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The contents of the internal X I O memory space are listed in Appendix B Programming Reference Table B 2 X Data Memory FFFFFF Internal I O Peripherals Control Registers Memory Space FFFF80 FFFOOO Internal Reserved FF0000 External 00C000 Internal X Data RAM 48K default 000000 Figure 5 1 Memory Mapping of Peripherals Control Registers 5 3 Reading Status Registers Each peripheral has a read only status register that indicate the state of the peripheral at a given time The HIO8 ESSI and SCI have dedicated status registers The triple timer has status bits embedded within a control status register Changes in the status bits can generate interrupt conditions For example the HIO8 has a host status register with two host flag bits that can be encoded by the host to generate an interrupt in the DSP Motorola DSP56311 User s Manual 5 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Transfer Methods 5 4 Data Transfer Methods Peripheral I O on the DSP56311 can be accomplished in three ways m Polling m Interrupts m DMA 5 4 1 Polling Polling is the easiest method for data tran
369. ped in its external address space The DSP side registers appear to the DSP core as six 24 bit registers mapped into internal I O X memory space and therefore accessible via standard DSP56300 instructions and addressing modes In GPIO mode two additional registers HDDR and HDR are related to the HIOS peripheral The separate receive and transmit data paths are double buffered for efficient high speed asynchronous transfers The host side transmit data path host writes is also the DSP side receive path the host side receive data path host reads is also the DSP side transmit path The Receive RXH M L and Transmit Data Registers TXH M L use the same host address During host writes to these addresses the data is transferred to the Transmit Data Registers while reads are performed from the Receive Data Registers 6 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com HCR G HDDR HBAR HPCR HTX HRX Jai lae Motorola 24 Freescale Semiconductor Inc DSP Side Registers Control Registers HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HBAR Host Base Address Register Overview Data Registers HTX Host Transmit Register HRX Host Receive Register HDDR Host Data Direction Register HDR Host Data Register Core DMA Data Bus DSP Peripheral Data Bus LE sf 8 8 8 Host Side Registers Control Registers ISR Interf
370. processors can load or store data at their maximum programmed I O instruction rate without testing the handshake flags for each transfer If full handshake is not needed the host processor can treat the DSP56311 as a fast device and data can be transferred between the host processor and the DSP56311 at the fastest data rate of the host processor One of the most innovative features of the host interface is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP56311 The host can select any of 128 DSP interrupt routines for execution by writing a vector address register in the HIOS8 This flexibility allows the host processor to execute up to 128 pre programmed functions inside the DSP56311 For example the DSP56311 host interrupts allow the host processor to read or write DSP registers X Y or program Motorola Host Interface H108 6 23 For More Information On This Product Go to www freescale com Host Programmer s Model Freescale Semiconductor Inc memory locations force interrupt handlers for example SSI SCI IRQA IRQB interrupt routines and perform control or debugging operations Note When the DSP enters Stop mode the HIOS8 signals are electrically disconnected internally thus disabling the HI08 until the core leaves stop mode While the HIO08 configuration remains unchanged in Stop mode the core cannot be restarte
371. r CVR NOTE If more than one interrupt request source is asserted and enabled for example HRDF is set HCP is set HRIE is set and HCIE is set the HIO8 generates interrupt requests according to priorities shown here The bit value is indeterminate after an individual reset Priority Interrupt Source Highest Host Command HCP 1 Transmit Data HTDE 1 Lowest Receive Data HRDF 1 1 HTIE 0 Host Transmit Interrupt Enable Generates a host transmit data interrupt request if the host transmit data empty HTDE bit in the HSR is set The HTDE bit is set when data is transferred from the HTX to the RXH RXM or RXL registers If HTIE is cleared HTDE interrupts are disabled The bit value is indeterminate after an individual reset 6 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model Table 6 7 Host Control Register HCR Bit Definitions Bit Number Bit Name Reset Value Description 0 HRIE 0 Host Receive Interrupt Enable Generates a host receive data interrupt request if the host receive data full HRDF bit in the host status register HSR Bit 0 is set The HRDF bit is set when data is transferred to the HRX from the TXH TXM or TXL registers If HRIE is cleared HRDF interrupts are disabled The bit value is indeterminate after an individual reset 6 6 2 Host
372. r Interrupt Enable M SREIE EQU 23 SSI Receive Error Interrupt Enable 3 SSI Status Register Bit Flags M IF EQU 3 Serial Input Flag Mask M_IFO EQU 0 Serial Input Flag 0 M_IF1 EQU Serial Input Flag 1 M TFS EQU 2 Iransmit Frame Sync Flag M RFS EQU 3 Receive Frame Sync Flag M TUE EQU 4 Transmitter Underrun Error FLag M ROE EQU 5 Receiver Overrun Error Flag M TDE EQU 6 Iransmit Data Register Empty M RDF EQU 7 Receive Data Register Full d SSI Transmit Slot Mask Register A M SSTSA EQU FFFF SSI Transmit Slot Bits Mask A TS0 TS15 3 SSI Transmit Slot Mask Register B M SSTSB EQU FFFF SSI Transmit Slot Bits Mask B TS16 TS31 3 SSI Receive Slot Mask Register A M SSRSA EQU FFFF SSI Receive Slot Bits Mask A RSO RS15 B SSI Receive Slot Mask Register B M SSRSB EQU SFFFF SSI Receive Slot Bits Mask B RS16 RS31 Register Addresses M IPRC EQU FFFFFF Interrupt Priority Register Core M IPRP EQU FFFFFE Interrupt Priority Register Peripheral Interrupt Priority Register Core IPRC MIAL EQU 7 IRQA Mode Mask M IALO EQU 0 IRQA Mode Interrupt Priority Level low M IALI EQU 1 IRQA Mode Interrupt Priority Level high M IAL2 EQU 2 IRQA Mode Trigger Mode M IBL EQU 38 IRQB Mode Mask M IBLO EQU 3 IRQB Mode Interrupt Priority Level low M IBLI EQU 4 IRQB Mode Interrupt Priority Level high M IBL2 EQU 5 IRQB Mode Trigger Mode M ICL EQU 1C0 IRQC Mode Mask M IC
373. r Output Input Timer 0 Schmitt Trigger Input Output When Timer 0 functions as an external event counter or in measurement mode TIOO is used as input When Timer 0 functions in watchdog timer or pulse modulation mode TIOO is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer I O through the timer 0 control status register TCSRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated TIO1 Input or Output Input Timer 1 Schmitt Trigger Input Output When Timer 1 functions as an external event counter or in measurement mode TIO1 is used as input When Timer 1 functions in watchdog timer or pulse modulation mode TIO1 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer I O through the timer 1 control status register TCSR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated TIO2 Input or Output Input Timer 2 Schmitt Trigger Input Output When timer 2 functions as an external event counter or in measurement mode TIO2 is used as input When timer 2 functions in watchdog timer or pulse modulation mode TIO2 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer I O through the timer 2 control status regi
374. ram 1 configures the SCI 2 loads the program size 3 loads the location where the program begins loading in program memory and 4 loads the program First the SCI Control Register is set to 0302 which enables the transmitter and receiver and configures the SCI for 10 bits asynchronous with one start bit 8 data bits one stop bit and no parity Next the SCI Clock Control Register is set to C000 which configures the Motorola Serial Communication Interface SCI 8 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exceptions SCI to use external receive and transmit clocks on the SCLK pin This clock must be 16 times the serial data rate The next step is to receive the program size and then the starting address to load the program These two numbers are three bytes each loaded least significant byte first Each byte is echoed back as it is received After both numbers are loaded the program size is in AO and the starting address is in A1 The program is then loaded one byte at a time least significant byte first After the program is loaded the operating mode is set to zero the CCR is cleared and the DSP begins execution with the first instruction loaded 8 5 Exceptions The SCI can cause five different exceptions in the DSP discussed here from the highest to the lowest priority 1 SCIreceive data with exception status occurs when the receive data register is full with
375. rchitecture Problems with testing high density circuit boards led to the development of this standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG The DSP56300 core implementation supports circuit board test strategies based on this standard The test logic includes a TAP with four dedicated signals a 16 state controller and three test data registers A boundary scan register links all device signals into a single shift register The test logic implemented utilizing static logic design is independent of the device system logic For details on the JT AG port consult the DSP56300 Family Manual The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that you can examine registers memory or on chip peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP signals For details on the OnCE module consult the DSP56300 Family Manual 1 5 6 On Chip Memory The memory space of the DSP56300 core is partitioned into program X data and Y data memory space The data memory space is divided into X and Y data memory in order to work with the two address ALUS and to feed two operands simultaneously to the data ALU Memory space includes internal RAM and ROM and can be expanded off chip under software control There is an on chip 192 x 24 bit bootstrap ROM For details on internal memory see Chapter 3
376. read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address A 2 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Code If MD MC MB MA 1110 then the program RAM is loaded from the Host Interface programmed to operate in the 8051 multiplexed bus mode in double strobe pin configuration The HOST 8051 bootstrap code expects accesses that are byte wide The HOST 8051 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words are stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address The base address of the HI08 in multiplexed mode is 0x80 and is not modified by the bootstrap code All the address l
377. receiver RE 1 according to use Operation starts as follows m For an internally generated clock the SCLK signal starts operation immediately after the SCI is enabled Step 3 above for Asynchronous modes In Synchronous mode the SCLK signal is active only while transmitting that is a gated clock m Data is received only when the receiver is enabled RE 1 and after the occurrence of the SCI receive sequence on the RXD signal as defined by the operating mode that is idle line sequence m Data is transmitted only after the transmitter is enabled TE 1 and after the initialization sequence has been transmitted depending on the operating mode 8 4 1 Preamble Break and Data Transmission Priority Two or three transmission commands can be set simultaneously m A preamble TE is set m A break SBK is set or is cleared m An indication that there is data for transmission TDRE is cleared After the current character transmission if two or more of these commands are set the transmitter executes them in the following order preamble break data 8 4 2 Bootstrap Loading Through the SCI Operating Mode 6 When the DSP comes out of reset it checks the MODD MODC MODB and MODA pins and sets the corresponding mode bits in the Operating Mode Register OMR If the mode bits are set to 1010 respectively the DSP loads the program RAM from the SCI Appendix A Bootstrap Program shows the complete bootstrap code This prog
378. reescale com Freescale Semiconductor Inc Chapter 4 Core Configuration This chapter presents DSP56300 core configuration details specific to the DSP56311 These configuration details include the following Operating modes Bootstrap program Interrupt sources and priorities DMA request sources OMR PLL control register AA control registers JTAG boundary scan register For information on specific registers or modules in the DSP56300 core refer to the DSP56300 Family Manual 4 1 Operating Modes The DSP56311 begins operation by leaving the Reset state and going into one of eight operating modes As the DSP56311 exits the Reset state it loads the values of MODA MODB MODC and MODD into bits MA MB MC and MD of the OMR These bit settings determine the chip s operating mode which in turn determines the bootstrap program option the chip uses to start up Software can also directly set the OMR MA MD bits A jump directly to the bootstrap program entry point SFF0000 after the OMR bits are set causes the DSP56311 to execute the specified bootstrap program option except modes 0 and 8 Table 4 1 shows the DSP56311 bootstrap operation modes the corresponding settings of the external operational mode signal lines the OMR MA MD bits and the reset vector address to which the DSP56311 jumps once it leaves the Reset state Motorola Core Configuration 4 1 For More Information On This Product Go to www freescale com
379. reescale com Freescale Semiconductor Inc Bootstrap Code DFFFFF active low Sioa DSP VO REGISTERS 22358252 M_SSR EQU FFFF93 SCI Status Register M STXL EQU FFFF95 SCI Transmit Data Register low M SRXL EQU FFFF98 SCI Receive Data Register low M SCCR EQU FFFF9B SCI Clock Control Register M SCR EQU FFFF9C SCI Control Register M PCRE EQU FFFF9F Port E Control register M AARI EQU SFFFFF8 Address Attribute Register 1 M HPCR EQU SFFFFCA Host Polarity Control Register M HSR EQU FFFFC3 Host Status Register M HRX EQU FFFFC6 Host Receive Register HRDF EQU 0 Host Receive Data Full HFO EQU 3 Host Flag 0 HEN EQU 6 Host Enable ORG PL ff0000 PL ff0000 bootstrap code starts at ff0000 START clr a 0 15 clear a and init R5 with 0 jelr 3 omr OMROXXX If MD MC MB MA 0xxx go to OMROXXX jclr 2 omr EPRSCILD If MD MC MB MA 10xx go load from EPROM SCI jelr 1 omr OMRIISO IF MD MC MB MA 110x go to look for ISA HC11 jelr 0 omr I8051HOSTLD If MD MC MB MA 1110 go load from 8051 Host If MD MC MB MA 1111 go load from MC68302 Host This routine loads a program through the HIOS8 host port The program is downloaded from the host MCU with the following rules 1 3 bytes Define the program length 2 3 bytes Define the address to which to start loading the program 3 3n bytes while n is any integer number The program words 1s strobed in co
380. repeated for consecutive time periods Filtering can be done with the same filter or different filters for each channel by using the FCSR FSCO bit If FCSR FSCO is set the same set of coefficients are used for all channels If FSCO is clear the coefficients for each filter are stored sequentially in memory for each channel Motorola Enhanced Filter Coprocessor EFCOP 10 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation Summary 10 5 1 1 3 Complex Mode Complex mode performs FIR type filtering with complex data based on the following equations IN 1 Re F n 2 Re H i Re D n i Im H i Im D n i A 9 Im F n gt Re H i Im D n i Im H i Re D n i i 0 where H n is the coefficients D n is the input data and F n is the output data at time n Two samples the real part then the imaginary part of the input are written to the FDIR The EFCOP processes the data and then two samples the real and then the imaginary part of the output are read from the FDOR Complex mode is selected by setting the FCSR FOM bits to 01 In Complex mode the number written to the FCNT register should be twice the number of filter coefficients Also the coefficients are stored in the FCM with the real part of the coefficient in the memory location preceding the memory location holding the imaginary part of the coefficient 10 5 1 1 4 Alternati
381. resh Enable 14 Software Triggered Refresh 7F 8000 Refresh Rate Bits Mask BRFO BRF7 23 Refresh prescaler Address Attribute Registers 2 M BAT EQU 3 External Access Type and Pin Definition Bits Mask BATO BAT 1 M BAAP EQU 2 Address Attribute Pin Polarity M_BPEN EQU 3 Program Space Enable M_BXEN EQU 4 X Data Space Enable M BYEN EQU 5 Y Data Space Enable M BAM EQU 6 Address Muxing M BPAC EQU 7 Packing Enable M BNC EQU F00 Number of Address Bits to Compare Mask M BAC EQU FFF000 Address to Compare Bits Mask BACO BACII control and status bits in SR M CP EQU c00000 mask for CORE DMA priority bits in SR MCA EQU 0 Carry MV EQU 1 Overflow MZ EQU 2 Zero MN EQU 3 Negative MU EQU 4 Unnormalized ME EQU 5 Extension ML EQU 6 Limit MS EQU 7 Scaling Bit MIO EQU 8 Interrupt Mask Bit 0 MII EQU 9 Interrupt Mask Bit 1 M S0 EQU 10 Scaling Mode Bit 0 MSI EQU 11 Scaling Mode Bit 1 M SC EQU 13 Sixteen Bit Compatibility M DM EQU 14 Double Precision Multiply M LF EQU 15 DO Loop Flag M FV EQU 16 DO Forever Flag M SA EQU 17 Sixteen Bit Arithmetic M CE EQU 19 Instruction Cache Enable M SM EQU 20 Arithmetic Saturation M RM EQU 21 Rounding Mode M_CPO EQU 22 bit O of priority bits in SR M CP EQU 23 bit 1 of priority bits in SR control and status bits in OMR M CDP EQU 300 mask for CORE DMA priority bits in OMR Motorola Bootstrap Program A
382. rflow interrupt is generated m You can read the counter contents at any time from the Timer Count Register TCR 9 3 1 1 Timer GPIO Mode 0 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 0 0 0 GPIO Timer GPIO Internal In Mode 0 the timer generates an internal interrupt when a counter value is reached if the timer compare interrupt is enabled see Figure 9 3 and Figure 9 4 When the counter equals the TCPR value TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is reloaded with the TLR value at the next timer clock and the count is resumed If TCSR TRM is cleared the counter continues to increment on each timer clock signal This process repeats until the timer is disabled Motorola Triple Timer Module 9 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Mode 0 internal clock no timer output TRM 1 N write preload first event last event M write compare TE Clock NL NL II CLK 2 or prescale CLK TLR bd N 1 1 Counter TCR 0 N N 1 M N X N 1 TCPR gt lt TCF Compare Interrupt if TCIE 1 C Figure 9 3 Timer Mode TRM 1 Mode O0 internal clock no timer output TRM 0 N write preload firs
383. rigger event 7 9 interrupt trigger configuring 7 9 interrupts 5 3 interrupts HIO8 HI08 handshaking protocols interrupts 6 6 interrupts receive and transmit 7 11 IPR P 4 7 ISR Host Request bit HREQ 6 28 ISR register 6 28 IVR register 6 30 J JCLR 5 2 Joint Test Action Group JTAG 1 5 1 9 BSR 4 25 interface 2 20 JSCLR 5 2 JSET 5 2 JSSET 5 2 JTAG 1 9 K K constant 10 1 L LA register 1 8 Motorola DSP56311 User s Manual LC register 1 8 Load register TLR 9 3 logic 1 5 Loop Address register LA 1 8 Loop Counter register LC 1 8 M68HC11 SCI interface 8 16 MAC 1 6 Manual Conventions 1 2 mapping control registers 5 2 MC68000 family 6 30 MC68681 DUART 8 16 Measurement 9 11 Measurement capture Mode 6 9 11 Measurement input period Mode 5 9 11 Measurement input width Mode 4 9 11 memory allocation switching 3 2 configuration 3 7 dynamic switching 3 7 expansion 1 10 3 1 external expansion port 1 10 maps 3 8 off chip 1 10 on chip 1 9 shared 10 2 memory maps 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 Memory Switch mode 3 2 X data Memory 3 4 Y data Memory 3 6 MIPS 1 5 mobile switching center 10 1 MODD MODC MODB and MODA 8 7 mode control 2 9 modulo adder 1 7 move MOVE MOVEP instructions 5 2 MOVEP instruction 6 13 multichannel filter 10 1 Multidrop mode 8 2 multiple serial device selection 7 5 mul
384. rithmetic FSA Mode When set this read write control bit enables FSA mode In this mode the rounding of the arithmetic operation is performed on Bit 31 of the 56 accumulator instead of the usual bit 23 of the 56 bit accumulator The scaling of the EFCOP data ALU is affected accordingly 4 FSM 0 Filter Saturation Mode When set this read write control bit selects automatic saturation on 48 bits for the results going to the accumulator A special circuit inside the EFCOP MAC unit then saturates those results The purpose of this bit is to provide arithmetic saturation mode for algorithms that do not recognize or cannot take advantage of the extension accumulator 3 2 FRM 0 Filter Rounding Mode These read write control bits select the type of rounding performed by the EFCOP data ALU during arithmetic operation FRM 00 Convergent rounding FRM 01 Two s complement rounding FRM 10 Truncation no rounding FRM 11 Reserved for future expansion These bits affect operation of the EFCOP data ALU 1 0 FSCL 0 Filter Scaling FSCL These read write control bits select the scaling factor of the FMAC result FSCL 00 Scaling factor 1 no shift FSCL 01 Scaling factor 8 3 bit arithmetic left shift FSCL 10 Scaling factor 16 4 bit arithmetic left shift FSCL 11 Reserved for future expansion To ensure proper operation never change the FSCL bits unless the EFCOP is in the individual reset state
385. rmine which source clock is used for the prescalar A timer can be clocked by a prescalar clock that is derived from the TIO of another timer 14 0 Reserved Write to zero for future compatibility 13 DO 0 Data Output The source of the TIO value when it is a data output signal The TIO signal is a data output when the GPIO mode is enabled and DIR is set A value written to the DO bit is written to the TIO signal If the INV bit is set the value of the DO bit is inverted when written to the TIO signal When the INV bit is cleared the value of the DO bit is written directly to the TIO signal When GPIO mode is disabled writing to the DO bit has no effect 12 DI 0 Data Input Reflects the value of the TIO signal If the INV bit is set the value of the TIO signal is inverted before it is written to the DI bit If the INV bit is cleared the value of the TIO signal is written directly to the DI bit Motorola Triple Timer Module 9 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 11 DIR Direction Determines the behavior of the TIO signal when it functions as a GPIO signal When DIR is set the TIO signal is an output when DIR is cleared the TIO signal is an input The TIO signal fu
386. rnal 0 1 01 0 4 Input width i it Internal measurement 0 1 0 1 5 Input peri d Input Internal measurement 0 1 1 0 6 Capture event Input Internal 0 1 1 1 7 Pulse width ut Internal modulation 1 0 0 0 8 Reserved 1 0 0 1 9 Watchdog Output Internal pulse 1 0 1 0 10 Watchdog Output Internal Toggle 1 0 1 1 11 Reserved 1 1 0 0 12 Reserved 1 1 0 1 13 Reserved 1 1 1 0 14 Reserved 1 1 1 1 15 Reserved Note 1 The GPIO function is enabled only if all of the TC 3 0 bits are 0 3 0 Reserved Write to zero for future compatibility Motorola Triple Timer Module 9 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Triple Timer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 2 TCIE 0 Timer Compare Interrupt Enable Enables disables the timer compare interrupts When set TCIE enables the compare interrupts In the timer pulse width modulation PWM or watchdog modes a compare interrupt is generated after the counter value matches the value of the TCPR The counter starts counting up from the number loaded from the TLR and if the TCPR value is M an interrupt occurs after M N 1 events where N is the value of TLR When cleared the TCSR TCIE bit disables the compare interrupts TO
387. rnal program memory according to the memory space table of the specific DSP56300 core based device NOTE To ensure proper operation do not clear Cache Enable mode while Burst mode is enabled OMR BE is set 18 0 Reserved Write to zero for future compatibility 17 SA 0 Sixteen Bit Arithmetic Mode Affects data width functionality enabling the Sixteen bit Arithmetic mode of operation When SA is set the core uses 16 bit operations instead of 24 bit operations In this mode 16 bit data is right aligned in the 24 bit memory locations registers and 24 bit register portions Shifting limiting rounding arithmetic instructions and moves are performed accordingly For details on Sixteen Bit Arithmetic mode consult the DSP56300 Family Manual 16 FV 0 DO FOREVER Flag Set when a DO FOREVER loop executes The FV flag like the LF flag is restored from the stack when a DO FOREVER loop terminates Stacking and restoring the FV flag when initiating and exiting a DO FOREVER loop respectively allow program loops to be nested When returning from the long interrupt with an RTI instruction the system stack is pulled and the value of the FV bit is restored 15 LF 0 Do Loop Flag When a program loop is in progress enables the detection of the end of the loop The LF is restored from stack when a program loop terminates Stacking and restoring the LF when initiating and exiting a program loop respectively allow p
388. roduct Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Mode 0 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO emus imme oo oe 0s oo or One Byte From Shift Register Lo 1 0 10 bit Asynchronous 1 Start 8 Data 1 Stop WDSO Mode 4 11 bit Asynchronous 1 Start 8 Data 1 Even Parity 1 Stop WDS2 WDS1 WDSO TX SSFTD 0 Data Type 1 Address Byte 0 Data Byte Note 1 Modes 1 3 and 7 are reserved 2 DO LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 Figure 8 2 SCI Data Word Formats SSFTD 0 2 Motorola Serial Communication Interface SCI 8 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model 8 6 1 SCI Control Register SCR The SCR is a read write register that controls the serial interface operation Seventeen of its 24 bits are defined 23 22 21 20 19 18 17 16 REIE 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE RIE ILIE TE RE 7 6 5 4 3 2 1 0 WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDSO Figure 8 3 SCI Control Register SCR Table 8 2 SCI Control Register SCR Bit Definitions Bit Number Bit Name Reset Value Description 23 17 0 Reserved Set to 0 for future compatibility 16 REIE 0 Receive with Exception I
389. rogram loops to be nested When returning from the long interrupt with an RTI instruction the System Stack is pulled and the LF bit value is restored Motorola Core Configuration 4 17 For More Information On This Product Go to www freescale com Status Register SR Freescale Semiconductor Inc Table 4 7 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 14 DM 0 Double Precision Multiply Mode Enables four multiply MAC operations to implement a double precision algorithm that multiplies two 48 bit operands with a 96 bit result Clearing the DM bit disables the mode NOTE The Double Precision Multiply mode is supported to maintain object code compatibility with devices in the DSP56000 family For a more efficient way of executing double precision multiply refer to the chapter on the Data Arithmetic Logic Unit in the DSP56300 Family Manual In Double Precision Multiply mode the behavior of the four specific operations listed in the double precision algorithm is modified Therefore do not use these operations with those specific register combinations in Double Precision Multiply mode for any purpose other than the double precision multiply algorithm All other Data ALU operations or the four listed operations but with other register combinations can be used The double precision multiply algorithm uses the YO Register at all stages Therefore
390. rogramming model in Figure 7 12 and Figure 7 13 shows additional information on how to select different lengths for data words The ESSI data registers are 24 bits long The ESSI transmits 32 bit words in one of two ways Wi by duplicating the last bit 8 times when WL 2 0 100 W by duplicating the first bit 8 times when WL 2 0 101 NOTE When WL 2 0 100 the ESSI is designed to duplicate the last bit of the 24 bit transmission eight times to fill the 32 bit shifter Instead after the 24 bit word is shifted correctly eight zeros Os are shifted ESSI Word Length Selection WL2 WL1 WLO Number of Bits Word 0 0 0 8 0 0 1 12 0 1 0 16 0 1 1 24 1 0 0 32 valid data in the first 24 bits 1 0 1 32 valid data in the last 24 bits 1 1 0 Reserved 1 1 1 Reserved NOTE When the ESSI transmits data in On Demand mode that is MOD 1 in the CRB and DC 4 0 00000 in the CRA with WL 2 0 100 the transmission does not work properly To ensure correct operation do not use On Demand mode with the WL 2 0 100 32 bit word length mode Motorola Enhanced Synchronous Serial Interface ESSI 7 15 For More Information On This Product Go to www freescale com ESSI Programming Model Freescale Semiconductor Inc Table 7 3 ESSI Control Register A CRA Bit Definitions Continued Bit Number Bit Name Reset Value Description
391. rom the DSP56300 core A DMA transfer is enabled if a DMA channel is activated and triggered by this event NOTE For proper operation enable the interrupt service routine and the corresponding interrupt for core processing or enable the DMA transfer and configure the proper trigger for the selected channel Never enable both simultaneously Motorola Enhanced Filter Coprocessor EFCOP 10 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming Model Table 10 4 FCSR Bits Continued Bit Number Bit Name Reset Value Description 10 FDIIE Filter Data Input Interrupt Enable This read write control bit enables the data input buffer empty interrupt If FDIIE is cleared the data input buffer empty interrupt is disabled and the FDIBE status bit should be polled to determine whether the FDIR is empty If both FDIIE and FDIBE are set the EFCOP requests a data input buffer empty interrupt service from the DSP56300 core DMA transfer is enabled if a DMA channel is activated and triggered by this event NOTE For proper operation enable the interrupt service routine and the corresponding interrupt for core processing or enable the DMA transfer and configure the proper trigger for the selected channel Never enable both simultaneously Reserved It is read as 0 and should be written with O for future compatibility FSCO Filter Shared Coef
392. rrupt request pins IRQx 6 9 host issues command requests to DSP 6 8 host issues vectored interrupt requests 6 23 host performs multiple reads from the HI08 port Receive Byte Registers 6 6 Host Port Control Register HPCR 2 11 2 12 2 13 2 14 6 17 6 22 6 32 6 33 B 4 B 23 host processor registers 6 13 Host Receive Data Register HRX 6 6 6 22 Host Receive Request HRRQ 6 9 host request line 6 4 host request pins 6 10 host side Command Vector Register CVR 6 27 Interface Control Register ICR 6 24 Interface Status Register ISR 6 28 Interface Vector Register IVR 6 30 Index 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Receive Byte Registers RXH RXM RXL 6 30 registers after reset 6 31 Transmit Byte Registers TXH TXM TXL 6 30 Host Status Register HSR 6 15 host to DSP data word 6 1 handshaking protocols 6 1 instructions 6 1 mapping 6 1 Host Transmit Data Register HTX 6 21 Host Transmit Data register HTX 6 7 host side register map 6 24 host to DSP data transfers 6 6 6 22 HPCR 6 4 Host Acknowledge Enable 6 19 Host Acknowledge Polarity 6 18 Host Address Line 8 Enable 6 20 Host Address Line 9 Enable 6 20 Host Address Strobe Polarity 6 19 Host Chip Select Enable 6 20 Host Chip Select Polarity 6 18 Host Data Strobe Polarity 6 19 Host Dual Data Strobe 6 18 Host Enable 6 19 Host GPIO Port Enable 6 20 Host Multiplexed Bus
393. rt D Registers PCRD PRRD PDRD page B 38 Figure B 28 Port E Registers PCRE PRRE PDRE page B 39 EFCOP Figure B 29 EFCOP Counter and Control Status Registers FONT and FCSR page B 40 Figure B 30 EFCOP FACR FDBA FCBA and FDCH Registers page B 41 B 1 Internal I O Memory Map Table B 2 Internal X I O Memory Map Peripheral 16 Bit Address 24 Bit Address Register Name IPR FFFF FFFFFF Interrupt Priority Register Core IPR C FFFE FFFFFE Interrupt Priority Register Peripheral IPR P PLL FFFD FFFFFD PLL Control Register PCTL OnCE FFFC FFFFFC OnCE GDB Register OGDB B 2 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Memory Map Table B 2 Internal X I O Memory Map Continued Peripheral 16 Bit Address 24 Bit Address Register Name BIU FFFB FFFFFB Bus Control Register BCR FFFA FFFFFA DRAM Control Register DCR FFF9 FFFFF9 Address Attribute Register 0 AARO FFF8 FFFFF8 Address Attribute Register 1 AAR1 FFF7 FFFFF7 Address Attribute Register 2 AAR2 FFF6 FFFFF6 Address Attribute Register 3 AAR3 FFF5 FFFFF5 ID Register IDR DMA FFF4 FFFFF4 DMA Status Register DSTR FFF3 FFFFF3 DMA Offset Register 0 DORO FFF2 FFFFF2 DMA Offset Register 1 DOR1 FFF1 FFFFF1 DMA Offset Register 2 DOR2 FFFO FFFFF
394. rtion otherwise improper operation may result TA can operate synchronously or asynchronously depending on the setting of the OMR TAS bit TA functionality must not be used while DRAM accesses are performed otherwise improper operation may result Output Output deasserted Bus Request An active low output never tri stated BR is asserted when the DSP requests bus mastership BR is deasserted when the DSP no longer needs the bus BR may be asserted or deasserted independently of whether the DSP56311 is a bus master or a bus slave Bus parking allows BR to be deasserted even though the DSP56311 is the bus master See the description of bus parking in the BB signal description The bus request hole BRH bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus BR is typically sent to an external bus arbitrator that controls the priority parking and tenure of each master on the same external bus BR is only affected by DSP requests for the external bus never for the internal bus During hardware reset BR is deasserted and the arbitration is reset to the bus slave state 2 8 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupt and Mode Control Table 2 8 External Bus Control Signals Continued State During Signal Name Type Reset Signal Description
395. ry Configuration For More Information On This Product Go to www freescale com 3 9 Memory Maps FFFFFF FFOOCO FF0000 008000 000400 000000 Program Internal Reserved Bootstrap ROM FF0000 External Internal Program RAM 31K 000000 FFFFFF FFFF80 FFF000 00C000 X Data Internal Reserved External Internal X data RAM 48K FFFFFF Internal I O SFFFFCO FFFF80 FFFO00 FF0000 00C000 000000 Freescale Semiconductor Inc Y Data External I O Internal I O External Internal Reserved External Internal Y data RAM 48K Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 0 any 1 0 31K 48K 48K Enabled 16M value 0400 7FFF 0000 BFFF 0000 BFFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 2 Memory Switch Off Cache On 24 Bit Mode DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com 3 10 Freescale Semiconductor Inc Memory Maps Program X Data Y Data FFFFFF FFFFFF FFFFFF External l O Internal I O FFFFCO FFFF80 FFFF80 Internal I O FFFO000 External FFF000 External Reserved Internal Internal FFO0CO Reserved Re
396. ry cose dece MR ECLENA REED edhe eset ens eexhedaue REGE 1 9 1 57 Off Chip Memory Expansion 55 24302205 94 S4 REREERRIWIRERBA XY ERE SYTE 1 10 1 6 Internal Buses sede r4ezec bbc o Qa be Res RE rbeQAA PI Pe ARE CAT ea 1 10 1 7 Block Diara ses cse e SEE ARE EDI ERN SEN Ri ae eee ses aa 1 11 1 8 la ee ee re ee eS ee er E ee eee ere 1 12 1 9 Peripherals a oai opesn suse ur meret ppd faye towered ebd weg db aed 1 12 1 9 1 GPIO F nctionality lt 4 Jenks eon denice cates eee PERRA eR REESE E EE 1 12 IT EE D P r LETT 1 12 1 9 3 lo rm 1 13 L94 S lui oeipbR GR RR E RE SEREdR E ERR PR REREREG URP RR RES ER ACRES PE EE 1 13 1 9 5 Tiger Mod le oo vasa pa E Ree eC oO SEED eden Ye deo X doce ded p eg 1 14 905 BECOP Loses educ ber eee Red ua ERE V eee b Ra UH E E RR RE 1 14 Chapter 2 Signals Connections 2 1 POWET Lillehawa494do ddoRa e aX P tice REX ARR C RR REA ds 2 4 2 4 COUN MEM 2 4 2 3 nc rm 2 5 2 4 PED dees eee diadt oi 80455 ceed osbhe duces csodeehbebaudss WM Q 2 6 2 5 External Memory Expansion Port Port A 0 0 0 ee eee eee eee 2 6 2 5 1 External Address Bus sss asa Rx be RAGU RR UR EES RE RN RR ER 2 6 29 2 External Data BUS ua d ice scm o dero oap ec de Vol s c dolet a Ro On 2 7 2 5 3 External Bus Control ico 2i pa px a EX HERR XR Ode GR Ra DA RRS 2 7 2 6 Interrupt and Mode Control oeeRec deeb RE T PRARER amp E EP CREP ERE dE bene 2 9 2 7 IOS PR M 2 11 Motorol
397. s A2 Al AO B2 B1 and BO that are concatenated into two general purpose 56 bit accumulators A and B accumulator shifters m Two data bus shifter limiter circuits 1 5 1 1 Data ALU Registers The data ALU registers are read or written over the X data bus and the Y data bus as 16 or 32 bit operands The source operands for the data ALU can be 16 32 or 40 bits and always originate from data ALU registers The results of all data ALU operations are stored in an accumulator Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction can be initiated in every clock cycle yielding an effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be a source operand for the immediately following operation without penalty 1 5 1 2 Multiplier Accumulator MAC The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands For arithmetic instructions the unit accepts as many as three input operands and outputs one 56 bit result of the following form extension most significant product least significant product EXT MSP LSP The multiplier executes 24 bit x 24 bit parallel fractional multiplies between twos complement signed unsigned or mixed operands The 48 bit product is right justified and added to the 56 bit contents of either the A or B accumulator A 56 bit result can be stored as a
398. s if the FCSR FPRC bit is cleared the core can initialize the coefficient bank while the DMA controller concurrently transfers initial data values to the data bank The EFCOP state machine starts computation as soon as filter_count data samples are input If no initialization mode is used the FCSR FPRC bit is set the EFCOP starts computation as soon as the first data sample is available in the input buffer The filter coefficient bank must therefore be initialized before an input data transfer starts The DMA input channel can continue transferring data whenever the input FIFO becomes empty while the EFCOP state machine takes data words from the FIFO whenever required 10 7 Examples of Use in Different Modes The following sections provide examples of how to use the EFCOP in Real FIR Filter Mode 0 and Adaptive FIR filter mode 10 7 1 Real FIR Filter Mode 0 In this example an N tap FIR filter is represented as follows F n gt H i D n i i 0 The filter is implemented with three different data transfers using the EFCOP in data initialization mode 1 DMA input DMA output 2 DMA input Polling output 3 DMA input Interrupt output This transfer combination is only one of many possible combinations 1 For information on DMA transfers refer to the Motorola application note entitled Using the DSP56300 Direct Memory Access Controller APR23 D Motorola DSP56311 User s Manual 10 22 For More Information On This
399. s m Other changes One divide by 2 removed from the internal clock source chain Control register A prescaler range CRA PSR bit definition is reversed Gated clock mode not available 7 2 ESSI Data and Control Signals Three to six signals are required for ESSI operation depending on the operating mode selected The serial transmit data STD signal and serial control SCO and SC1 signals are fully synchronized to the clock if they are programmed as transmit data signals 7 2 4 Serial Transmit Data Signal STD The STD signal transmits data from the serial transmit shift register STD is an output when data is transmitted from the TXO shift register With an internally generated bit clock the STD signal becomes a high impedance output signal for a full clock period after the last data bit is transmitted if another data word does not follow immediately If sequential data words are transmitted the STD signal does not assume a high impedance state The STD signal can be programmed as a GPIO signal P5 when the ESSI STD function is not in use 7 2 2 Serial Receive Data Signal SRD The SRD signal receives serial data and transfers the data to the receive shift register SRD can be programmed as a GPIO signal P4 when the SRD function is not in use 7 2 3 Serial Clock SCK The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI interface The SCK signal is a clock input or output used by al
400. s ALU can update one address register from its own address register file during one instruction cycle The contents of the associated modifier register specify the type of arithmetic used in the address register update calculation The modifier value is decoded in the address ALU 1 5 3 Program Control Unit PCU The PCU fetches and decodes instructions controls hardware DO loops and processes exceptions Its seven stage pipeline controls the different processing states of the DSP56300 core The PCU consists of three hardware blocks m Program decode controller decodes the 24 bit instruction loaded into the instruction latch and generates all signals for pipeline control m Program address generator contains all the hardware needed for program address generation system stack and loop control W Program interrupt controller arbitrates among all interrupt requests internal interrupts as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include the following Position independent code support m Addressing modes optimized for DSP applications including immediate offsets m On chip instruction cache controller Motorola Overview 1 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56300 Core Functional Blocks m On chip memory expandable hardware stack m Nested hardware
401. s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Mode Register OMR 4 4 Operating Mode Register OMR The OMR is a read write register divided into three byte sized units The lowest two bytes EOM and COM control the chip s operating mode The high byte SCS controls and monitors the stack extension The OMR control bits are shown in Figure 4 3 SCS EOM COM 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 MSW 1 0 SENWRPEOVEUNXYS APDIABEBRT TAS BE CDP1 0 MS SD EBD MD MC MB MA MSW1 MS Memory Switch Mode Mswo Memory Switch Configuration Abb Address Attribute Priority SD Stop Delay Disable SEN Stack Extension Enable ABE Async Bus Arbitration Enable EBD External Bus Disable WRP Stack Extension Wrap Flag BRT Bus Release Timing MD Chip Operating Mode D EOV Stack Extension Overflow Flag TAS TA Synchronize Select MC Chip Operating Mode C EUN Stack Extension Underflow BE Cache Burst Mode Enable MB Chip Operating Mode B Flag XYS Stack Extension Space Select CDP1 Core DMA Priority 1 MA Chip Operating Mode A CDPO Core DMA Priority 0 Reserved bit read as zero should be written with zero for future compatibility Figure 4 3 DSP56311 Operating Mode Register OMR Format The EOM and COM bytes are affected only by processor reset and by instructions directly ref
402. s before all interrupt trigger configuration steps are performed the event is ignored and not queued If interrupts derived from Enhanced Synchronous Serial Interface ESSI 7 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Normal Network and On Demand the core or other peripherals need to be enabled at the same time as ESSI interrupts step g should be performed last 7 4 Operating Modes Normal Network and On Demand The ESSI has three basic operating modes and several data and operation formats These modes are programmed via the ESSI control registers The data and operation formats available to the ESSI are selected when you set or clear control bits in the CRA and CRB These control bits are WL 2 1 MOD SYN FSL 1 0 FSR FSP CKP and SHFD 7 4 4 Normal Network On Demand Mode Selection To select either Normal mode or Network mode clear or set CRB MOD In Normal mode the ESSI sends or receives one data word per frame per enabled receiver or transmitter In Network mode 2 to 32 time slots per frame can be selected During each frame 0 to 32 data words are received or transmitted from each enabled receiver or transmitter In either case the transfers are periodic The Normal mode typically transfers data to or from a single device Network mode is typically used in time division multiplexed networks of CODECs or DSPs with multiple words per fram
403. sample Motorola Enhanced Filter Coprocessor EFCOP 10 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Features 4 bit decimation factor in FIR filters providing up to 1 16 decimation ratio Easy to use adaptive mode supporting true or delayed LMS type algorithms K constant input register for coefficient updates in adaptive mode m IIR filter options Direct form 1 DFI and direct form 2 DFID configurations Three optional output scaling factors 1 8 or 16 m Multichannel mode to process multiple equal length filter channels up to 64 simultaneously with minimal core intervention Optional input scaling for both FIR and IIR filters Two filter initialization modes No initialization Data initialization Sixteen bit arithmetic mode support Three rounding options available No rounding Convergent rounding Two s complement rounding Arithmetic saturation mode support for bit exact applications Sticky saturation status bit indication Sticky data coefficient transfer contention status bit 4 word deep input data buffer for maximum performance EFCOP shared and core shared 10K word filter data memory bank and 10K word filter coefficient memory bank m Two memory bank base address pointers one for data memory shared with X memory and one for coefficient memory shared with Y memory I O data transfers via core or DMA with minimal core i
404. served FF0000 Bootstrap ROM FF0000 FF0000 f External a External External 018000 00C000 00C000 Internal Reserved Internal Internal Reserved Program RAM 004000 004000 Internal Y data Internal X data 000000 PAM 16K 000000 PAM 16K 96 K 000000 Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 00 0 0 96K 16K 16K None 16M 0000 0000 3FFF 0000 3FFF 17FFF Lowest 10K of X data RAM and 410K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 3 Memory Switch On MSW 00 Cache Off 24 Bit Mode Motorola Memory Configuration 3 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program FFFFFF Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 External 018000 Internal Program RAM 95K 000400 000000 000000 FFFFFF FFFF80 FFFO000 00C000 004000 X Data Internal I O Internal Reserved External Internal Reserved Internal X data RAM 16K 004000 000000 FFFF80 FFFO000 Y Data FFFFFF External l O FFFFCO Internal I O External Internal Reserved FF0000 00C000 External Internal Reserved Internal Y data RAM 16K
405. sfer to receive data register RX but RX is full 7 29 Serial Transmit Data 7 3 Serial Transmit Data signal STD 7 3 set timer operating mode 9 3 shared memory 10 2 signal measurement modes 9 11 signals ESSI data and control 7 3 functional grouping 2 3 Single Data Strobe 2 3 single strobe bus 6 21 Sixteen bit Compatibility mode 3 8 Size register SZ 1 8 software polling 6 6 SP 1 8 SR register 1 8 SRAM interfacing 1 10 SRD 7 3 SRD signal 7 3 SRX 8 23 read as SRXL SRXM SRXH 8 23 SRX register 8 23 SSISR 7 6 7 14 7 29 SSISR register 7 29 SSR 8 17 SSR register 8 17 Stack Counter register SC 1 8 Stack Pointer SP 1 8 standby mode Stop 1 5 Wait 1 5 Status Register SR 1 8 status registers reading 5 2 STD 7 3 STD signal 7 3 sticky bits 10 2 stop standby mode 1 5 STOP instruction 6 22 8 6 STX 8 24 STX register read as STXL STXM STXH and STXA 8 24 switching memory configuration dynamically 3 7 switching memory sizes 3 2 Synchronous mod 8 19 Synchronous mode 7 10 7 11 7 13 8 2 8 18 synchronous mode 7 4 SZ register 1 8 Motorola DSP56311 User s Manual y TAP 1 9 TCPR register 9 30 TCR register 9 30 TCSR register 9 24 TE bit 8 14 9 24 TEIE bit 7 20 Test Access Port TAP 1 9 TFS bit 7 30 Time Slot Register TSR 7 34 timer control counter preload operation 9 26 control timer clock source behavior of TIO signal and timer mode of operation 9 27 indicate a counter overflow 9 25 indicate that event
406. sferred from the HTX register to the receive byte register at host address 7 the ISR Receive Data Register Full RXDF bit is set The host processor can program the RREQ bit to assert the external HREQ signal when ISR RXDF is set This indicates that the HIOS8 has a full word either 8 16 or 24 bits for the host processor The host processor can program the RREQ bit to assert the external HREQ signal when ISR RXDF is set Assertion of the HREQ signal informs the host processor that the receive byte registers have data to be read When the host reads the receive byte register at host address 7 the ISR RXDF bit is cleared 6 7 6 Transmit Byte Registers TXH TXM TXL The host processor views the transmit byte registers as three 8 bit write only registers These registers are the transmit high register TXH the transmit middle register TXM and the transmit low register TXL These registers send data to the high middle and low bytes respectively of the HRX register and are selected by the external host address inputs HA 2 0 during a host processor write operation 6 30 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Host Programmer s Model If ICR HLEND is set the TXH register is located at address 7 the TXM register at 6 and the TXL register at 5 If the HLEND bit in the ICR is cleared the TXH register is located at address 5 the TX
407. sfers When polling is chosen the DSP56311 core continuously checks a specified register flag waiting for an event to happen One example would be setting an overflow flag in one of the Timers Once the event occurs the DSP56311 is free to continue with its next task However while it is waiting for the event to occur the DSP56311 core is not executing any other code Polling is the easiest transfer method since it does not require register initializations but it is also the least efficient use of the DSP core Each peripheral has its own set of flags which may be polled to determine when data is ready to be transferred For example the ESSI control registers provide bits that tell the core when data is ready to be transferred to or from the peripheral The core polls these bits to determine when to interact with the peripheral Similar flags exist for each peripheral Example 5 1 shows software polling programmed in an application using the HI08 Example 5 1 Software Polling jelt 1 x M_HSR loop if HSR 1 HTDE 0 move y TBUFF_PTR x1 move data to xl Gl In this example the core waits until the Host Status Register s HSR Host Transmit Data Empty HTDE flag is set When the flag is set the core moves data from Y memory to the X1 register 5 4 2 Interrupts Interrupts are more efficient than polling but interrupts also require additional register initializations Polling requires the core to remain busy checking a fl
408. smit Frame Sync Flag 7 30 Transmitter Underrun Error Flag 7 30 STD 7 3 SYN bit 7 11 Synchronous mode 7 13 synchronous mode multiple active transmitters 7 4 Synchronous modes 7 11 synchronous operating mode 7 11 synchronous or asynchronous mode 7 4 7 5 TE bit 7 19 Time Slot Register 7 34 Transmit Data Registers 7 34 transmit data signal 7 4 transmit enable bits 7 19 transmit enable sequence in On Demand mode 7 22 transmit interrupt is enabled 7 9 Transmit Shift Registers 7 31 Transmit Slot Mask Registers 7 14 7 34 transmitter data out signal of transmit shift register TX2 7 5 TSR 7 9 TX and RX clocks 7 11 variable prescaler 7 16 word length frame sync 7 12 word length frame sync timing 7 12 ESSI Control Register A CRA 7 14 ESSI Control Registers 7 14 see also Control Register A B ESSI data and control signals SCO 7 4 SCK 7 3 SRD 7 3 STD 7 3 ESSI programming model 7 14 ESSI Receive Data Register RX 7 31 ESSI Receive Exception Interrupt Enable bit REIE 7 19 ESSI Receive Shift Register 7 31 ESSI Receive Slot Mask Registers RSMA RSMB 7 35 ESSI Status Register SSISR 7 29 ESSI Status Register SSISR bit definitions 7 29 ESSI Time Slot Register TSR 7 34 ESSI Transmit Data Registers 7 14 ESSI Transmit Data registers TX2 TX1 TX0 7 34 ESSI Transmit Exception Interrupt Enable bit TEIE 7 20 ESSI Transmit Shift Registers 7 31 ESSI Transmit Slot Mask Registers TSMA TSMB 7 34 ESSIO GPIO 5 7 ES
409. st internal Y memory location is 7FFF The Y memory space at the switched locations 8000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 MSWTL 1 0 11 The 4K higher locations A000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 9FFF The Y memory space at the switched locations A000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 The 10K lowest locations 0 27FF of the internal Y memory are shared memory which is accessible both to the core and the EFCOP The EFCOP connects to the shared memory in place of the DMA bus Therefore DMA cannot access the shared memory and simultaneous accesses by the core and EFCOP to the same memory bank of 256 locations of the shared memory are not permitted It is your responsibility to prevent such simultaneous accesses DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Dynamic Memory Configuration Switching 3 3 3 Internal Y I O Space The second part of the on chip peripheral registers occupies 16 locations SFFFF80 FFFF8F of the Y data memory This area is the internal Y I O space and it can be accessed by MOVE MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSE
410. start of the last slot of the frame This exception occurs regardless of the transmit mask register setting The transmit last slot interrupt can signal that the transmit mask slot register can be reset the DMA channels can be reconfigured and data memory pointers can be reassigned Using the Transmit Last Slot interrupt guarantees that the previous frame is serviced with the previous frame settings and the new frame is serviced with the new frame settings without synchronization problems DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Note Freescale Semiconductor Inc Operation The maximum transmit last slot interrupt service time should not exceed N 1 ESSI bits service time where N is the number of bits in a slot m ESSI transmit data Occurs when the transmit interrupt is enabled at least one of the enabled transmit data registers is empty and no transmitter error conditions exist Write to all the enabled TX registers or to the TSR to clear this interrupt This error free interrupt uses a fast interrupt service routine for minimum overhead if no more than two transmitters are used To configure an ESSI exception perform the following steps 1 Configure the interrupt service routine ISR Load vector base address register VBA b23 8 Define I VEC to be equal to the VBA value if that is nonzero If it is defined I VEC must be defined for the assembler before the i
411. status register to interrogate the HI08 status and flags The host processor can write to this address without affecting the internal state of the HIO8 The DSP core cannot access the ISR 6 5 4 3 2 1 0 HREQ HF3 HF2 TRDY TXDE RXDF Reserved bit read as 0 should be written with 0 for future compatibility Figure 6 16 Interface Status Registe ISR Table 6 16 Interface Status Register ISR Bit Definitions Bit Number Bit Name Reset Value Description 7 HREQ 0 Hardware Host Request and Software If HDRQ is set the HREQ bit indicates the status of the external reset transmit and receive request output signals HTRQ and HRRQ If 1 Individual HDRQ is cleared HREQ indicates the status of the external host reset and request output signal HREQ The HREQ bit is set from either or both of TREQ is set two conditions the receive byte registers are full or the transmit byte 1 Stop reset registers are empty These conditions are indicated by status bits ISR and TREQ is RXDF indicates that the receive byte registers are full and ISR TXDE set indicates that the transmit byte registers are empty If the interrupt source is enabled by the associated request enable bit in the ICR HREQ is set if one or more of the two enabled interrupt sources is set HDRQ HREQ Effect 0 0 HREQ is cleared no host processor interrupts are requested 0 1 HREQ
412. ster TCSR2 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated 2 12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit board test strategies based on the JEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG The OnCE module interfaces nonintrusively with the DSP56300 core and its peripherals so that you can examine registers memory or on chip peripherals Functions of the OnCE module are provided through the JTAG TAP signals 2 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG and OnCE Interface Table 2 15 OnCE JTAG Interface Signal Name Type State During Reset Signal Description TCK Input Input Test Clock A test clock input signal to synchronize the JTAG test logic TDI Input Input Test Data Input A test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and has an internal pull up resistor TDO Output Tri stated Test Data Output A test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the fa
413. ster A TSMA1 FFA3 FFFFA3 ESSI 1 Transmit Slot Mask Register B TSMB1 FFA2 FFFFA2 ESSI 1 Receive Slot Mask Register A RSMA1 FFA1 FFFFA1 ESSI 1 Receive Slot Mask Register B RSMB1 FFAO FFFFAO Reserved Port E FF9F FFFF9F Port E Control Register PCRE FF9E FFFF9E Port E Direction Register PRRE FF9D FFFF9D Port E GPIO Data Register PDRE SCI FF9C FFFF9C SCI Control Register SCR FF9B FFFF9B SCI Clock Control Register SCCR FF9A FFFF9A SCI Receive Data Register High SRXH FF99 FFFF99 SCI Receive Data Register Middle SRXM FF98 FFFF98 SCI Recieve Data Register Low SRXL FF97 FFFF97 SCI Transmit Data Register High STXH FF96 FFFF96 SCI Transmit Data Register Middle STXM FF95 FFFF95 SCI Transmit Data Register Low STXL FF94 FFFF94 SCI Transmit Address Register STXA FF93 FFFF93 SCI Status Register SSR FF92 FFFF92 Reserved FF91 FFFF91 Reserved FF90 FFFF90 Reserved B 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal I O Memory Map Table B 2 Internal X I O Memory Map Continued Peripheral 16 Bit Address 24 Bit Address Register Name Triple Timer FF8F FFFF8F Timer 0 Control Status Register TCSRO FF8E FFFF8E Timer 0 Load Register TLRO FF8D FFFF8D
414. stop_label nop jmp stop_ label p UE RR I De NG ty omae omoi kcu AUR eue aar de qae kdo movep y M FDOR x r0 ARE CARA Calculate Ke KKK KKK KKK Wait until FDOI Interrupt handler for Get F n Enable EFCOP EFCOP DMA source address points to the DATA bank Init DMA destination address Init DMA count to line mode DMA offset reg is 1 Init DMA control reg to line mode FDIBE Ck ckckckckckckckck ckckckckckckckckckckckckck ck F m is cleared kckckckckckckck ckckckckckckckckckckckckckckckck EFCOP output from FDOR Store in destination memory space move x rl a Retrieve desired value R n move x r0 y0 sub y0 a calculate E n R n F n move MU2 yO move a yl E mpy yO yl a calculate Ke mu 2 E n PRRAREARERAAAAREREREARER ERE RARER movep al y M_FKIR b cont dec jne nop bclr d11 y M FCSR cont rea nop nop nop Motorola DSP56311 User s Manual store Ke in FKIR Disable output interrupt 10 36 For More Information On This Product Go to www freescale com dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc Freescale Semiconductor Inc 000000 000000 000000 000000 000000 000000 000000 0000 00 00 00 00 00 00 00 00 00 00 0000 0 23 13 13 31 3 C3 C37 C3 C2 C2 000000 000000 ORG x SRC ADDRS
415. struction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations 10000 17FFF are considered reserved and should not be accessed MSWTL 1 0 11 The 8K higher locations A000 BFFF of the internal X memory and the 8K higher locations A000 BFFF of the internal Y memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 48K locations 0 BFFF in the program memory space The instruction cache if enabled occupies the DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc X Data Memory Space lowest 1 K program words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations C000 17FFF are considered reserved and should not be accessed 3 1 3 Instruction Cache In program memory space the lowest 1024 1K program words at locations 0 3FF function as an internal instruction cache When the instruction cache is enabled that is the CE bit in the SR is set the lowest 1K program words are reserved for the instruction cache and should not be accessed for other purposes Note When using an enabled instruction cache you must assign a valid value for the vector address bus so that interrupts can b
416. synchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in synchronous operation Port C 2 The default configuration following reset is GPIO input PC2 When configured as PC2 signal direction is controlled through PRRO The signal can be configured as an ESSI signal SC02 through PCRO NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated Motorola Signals Connections 2 15 For More Information On This Product Go to www freescale com Table 2 11 Freescale Semiconductor Inc Enhanced Synchronous Serial Interface 0 Enhanced Synchronous Serial Interface 0 Continued Signal Name Type State During Reset Signal Description SCKO PC3 Input Output Input or Output Input Serial Clock A bidirectional Schmitt trigger input signal providing the serial bit rate clock for the ESSI The SCKO is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes Although an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6T i e the system clock frequency must be at least three times the external ESSI clock frequency The ESSI nee
417. t When the DSP56311 reads the HRX register the HSR HRDF bit is cleared 6 6 9 DSP Side Registers After Reset Table 6 12 shows the results of the four reset types on the bits in each of the HIO8 registers accessible to the DSP56311 The hardware reset HW is caused by the RESET signal The software reset SW is caused by execution of the RESET instruction The individual reset IR occurs when HPCR HEN is cleared The stop reset ST occurs when the STOP instruction executes Table 6 12 DSP Side Registers After Reset Reset Type Register Register Name Data HW SW IR ST Reset Reset Reset Reset HCR All bits 0 0 1 HPCR All bits 0 0 HSR HF 1 0 0 0 HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 HBAR BA 10 3 80 80 HDDR DR 15 0 0 0 HDR D 15 0 HRX HRX 23 0 empty empty empty empty HTX HTX 23 0 empty empty empty empty 1 The bit value is indeterminate after reset 6 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Host Programmer s Model 6 7 Host Programmer s Model The HI08 provides a simple high speed interface to a host processor To the host bus the HI08 appears to be eight byte wide registers Separate transmit and receive data paths are double buffered to allow the DSP core and host processor to transfer data efficiently
418. t high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TCSR TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled Mode 3 internal clock TRM 1 N write preload first event M write compare X TE if clock source is from TIO pin Clock TIO CPUCLK 4 TIO pin or prescale CLK TLR DXCN Counter TCR X 0 X N N 1 M N TCPR gt lt gt interrupts every TCF Compare Interrupt if TCIE 1 q M N clock periods NOTE If INV 1 counter is clocked on 1 to 0 clock transitions instead of 0 to 1 transitions Figure 9 9 Event Counter Mode TRM 1 9 10 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Modes internal clock TEM z0 if clock source is from TIO pin N write preload first event TIO lt CPUCLK 4 M write compare Y TIO pin or prescale CLK TLR lt N 4 C
419. t 1s active when enabled spare 0 This bit should be set to 0 for i future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 1 Host acknowledge is enabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no l meaning in non multiplexed bus HASEN O address 8 enable bit has no meaning in non multiplexed bus HGEN 0 Host GPIO pins are disabled bra HIOSCONT OMRIISO jset 0 omr HCIIHOSTLD If MD MC MB MA 1101 go load from HC11 Host If MD MC MB MA 1100 go load from ISA HOST ISAHOSTLD movep 0101000000011000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 1 Positive host request HCSP 0 Negative chip select input HD HS 1 Dual strobes bus RD and WR HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 0 Negative data strobes polarity HROD 0 Host request 1s active when enabled spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus Motorola Bootstrap Program A 5 For More Information On This Product Go to www freesc
420. t Control Registers C and D 7 36 Port Data Register PDR 7 38 Port Data Registers C and D 7 38 Port Direction Register PRR 7 37 Port Direction Registers C and D 7 37 programming model 7 14 receive and transmit interrupts 7 11 Receive Data Register 7 31 receive frame sync edge 7 12 receive frame sync occurred during reception of word in serial receive data register 7 30 Receive Shift Register 7 31 Receive Slot Mask Registers 7 14 7 35 DSP56311 User s Manual Index 3 For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Received Data Register 7 14 reset 7 6 RX frame sync 7 11 RX frame sync pulses active 7 11 SCO 7 4 SCI 7 5 SC2 7 6 SCD2 bit in the CRB 7 6 SCK 7 3 select length of data words transferred via ESSI 7 15 select length of frame sync to be generated or recognized 7 23 select source of clock signal 7 23 Serial Control Direction 1 bit 7 5 serial flag signal or receive clock signal 7 4 serial output flag 0 OFO bit in the CRB 7 4 single codec with asynchronous transmit and receive 7 5 specify divide ratio of prescale divider in ESSI clock generator 7 17 SPI protocol 7 1 SRD 7 3 SSISR 7 6 Status Register 7 29 status register 7 14 Status Register SSISR Receive Data Register Full 7 29 Receive Frame Sync Flag 7 30 Receiver Overrun Error Flag 7 29 Serial Input Flag 0 7 31 Serial Input Flag 1 7 30 Transmit Data Register Empty 7 29 Tran
421. t Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDM via FDIR Compute F n the result is stored in FDOR The core keeps polling the FCSR FDOBF bit and stores the data in memory Motorola DSP56311 User s Manual 10 26 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Examples of Use in Different Modes Example 10 2 Real FIR Filtering using DMA input Polling output INCLUDE ioequ asm P3 AAA AIK A RAL ABA CUR COR UR cU COR De UK ae cao cos BT DIOR BIE E al alg eese ap alea cole KS e equates ERKEK RUE AOA AK ON OK AA AOR COR GR cU COR D KA eoe olco ub o ocu a ae aoo alae coti DE RS p a esie RAR aede Start FCON FIR LEN SRC ADDRS DST ADDRS SRC COUNT DST COUN FDBA ADDRS FCBA ADDRS equ main program equ equ equ equ equ equ equ equ 00100 001 i 20 3040 3000 006003 8 0 0 main program starting address EFCOP FSCR enable the DMA source address at register contents EFCOP EFCOP FIR length address point to DATA bank which to begin output DMAO count 7 4 word transfers number of outputs generated Input samples Start Address x 0 Coeff Start Address y 0 A Ck ck kk Ck Ck Ck CK CK IIS Sk SK CK CC I e e e A A x A A x x x ELLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLDLLLLLLLLLLLLLLLLLLLLI TF
422. t PD1 When configured as PD1 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal SC11 through PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SC12 PD2 Input Output Input or Output Input Serial Control Signal 2 For frame sync I O SC12 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in synchronous operation Port D 2 The default configuration following reset is GPIO input PD2 When configured as PD2 signal direction is controlled through PRR1 The signal can be configured as an ESSI signal SC12 through PCR1 NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated Motorola Signals Connections For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Enhanced Synchronous Serial Interface 1 Table 2 12 Enhanced Serial Synchronous Interface 1 Continued Signal Name Type State During Reset Signal Description SCK1 PD3 Input Output Input or Output Input Serial Clock A bidirectional Schmitt trigger
423. t Request When HIO8 is programmed to interface HRRQ Output a double host request host bus and the HI function is selected HRRQ this signal is the receive host request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request may be programmed as a driven or open drain output Port B 15 When the HIO08 is configured as GPIO through the HPCR this signal is individually programmed as an input or PB15 Input or output through the HDDR Output NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated 2 8 Enhanced Synchronous Serial Interface 0 Two synchronous serial interfaces ESSIO and ESSI1 provide a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard CODECs other DSPs microprocessors and peripherals that implement the Motorola serial peripheral interface SPI 2 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 2 11 Enhanced Synchronous Serial Interface 0 Enhanced Synchronous Serial Interface 0 Signal Name Type State During Reset Signal Description SCO00 PCO Input or Output Input Serial Control 0 The function of SCOO is determined by the selection of either synchronous or asynchronous mode F
424. t Type Register Register Name Data HW SW IR ST Reset Reset Reset Reset ICR All bits 0 0 mE CVR HC 0 0 0 0 HV 0 6 32 32 ISR HREQ 0 0 1 if TREQ is set 1 if TREQ is set 0 otherwise 0 otherwise HF3 HF2 0 0 TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR IV 0 7 0F 0F RX RXH RXM RXL empty empty empty empty TX TXH TXM TXL empty empty empty empty Motorola Host Interface H108 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Model Quick Reference 6 8 Programming Model Quick Reference Table 6 18 summarizes the HIO8 programming model Table 6 18 HI08 Programming Model DSP Side Bit Reset Type Reg HW Name Value Function sw IR ST HCR HRIE Receive 0 HRRQ interrupt disabled 0 Interrupt 1 HRRQ interrupt enabled Enable HTIE Transmit 0 HTRQ interrupt disabled 0 Interrupt 1 HTRQ interrupt enabled Enable HCIE Host Command 0 HCP interrupt disabled 0 Interrupt 1 HCP interrupt enabled Enable HF2 Host Flag 2 0 HF3 Host Flag 3 0 Se HPCR HGEN Host GPIO 0 GPIO signal disconnected 0 Enable 1 GPIO signals active HA8EN Host Address 0 HA8 A1 GPIO 0 Line 8 Enable 1 HA8 A1 HA8 HA9EN Host Address 0 HA9 A2 GPIO 0 Line 9 Enable 1 HA9 A2 HA9 HCSEN Host Chip 0 HCS A10 GPIO 0 Select Enable 1 HCS A10 HCS Motorola Host
425. t data empty 6 8 CVR Host Command 6 27 Host Vector 6 27 data registers RXH TXH RXM TXM and RXL TXL 6 23 data strobe 6 4 Direct Memory Access DMA 6 9 DMA transfers and host bus 6 9 double buffered mechanism 6 6 Index 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP core 6 6 DSP core interrupts 6 7 DSP interrupt routines 6 23 DSP side control registers 6 13 DSP side data registers 6 13 DSP side registers after reset 6 22 DSP to host data word 6 2 handshaking protocols 6 2 interrupts 6 2 mapping 6 2 transfer modes 6 2 DSP side conrol registers Host status register HSR 6 13 DSP side control registers Host base address register HBAR 6 13 Host control register HCR 6 13 Host GPIO data direction register HDDR 6 13 Host GPIO data register HDR 6 13 Host Port Control Register HPCR 6 13 DSP side registers after reset 6 22 DSP to host data transfers 6 21 DSP to host transfers 6 6 dual host requests enabled 6 10 dual strobe bus 6 21 enable host requests via host request HREQ or HTRQ signal 6 26 enable disable signals configured as GPIO 6 20 enabling host requests 6 9 external host address inputs 6 30 external host programmer s model 6 23 force execution of any interrupt handler 6 8 force initialization of HI08 hardware 6 25 four kinds of reset 6 31 four reset types 6 22 free core to use its processing power on functions other than polling or interrupt routines 6
426. t event last event M write compare Y TE TLR bw N d Counter TCR 0 N Clock CLK 2 or prescale CLK l N 1 TEE 0 x1 TCPR DX M TCF Compare Interrupt if TCIE 1 a TOF Overflow Interrupt if TCIE 1 Se Figure 9 4 Timer Mode TRM 0 9 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 1 2 Timer Pulse Mode 1 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 0 1 1 Timer Pulse Timer Output Internal In Mode 1 the timer generates an external pulse on its TIO signal when the timer count reaches a pre set value The TIO signal is loaded with the value of the TCSR INV bit When the counter matches the TCPR value TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The polarity of the TIO signal is inverted for one timer clock period If TCSR TRM is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If TCSR TRM is cleared the counter continues to increment on each timer clock This process repeats until TCSR TE is cleared disabling the timer The TLR value in the TCPR sets the delay between starting the timer and generating the output pulse To generate successive output pulses with a delay of X
427. ta 0400 RAM 24K 0000 0000 Freescale Semiconductor Inc Program FFFF FF80 X Data Internal I O Y Data External I O Internal I O FFFF FFCO FF80 External C000 Reserved Internal Y data RAM 24K 6000 0000 0400 FFFF 0000 5FFF Bit Settings Memory Configuration MSW Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 01 1 1 63K 24K 24K Enabled 64K 0000 5FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller 3 24 Figure 3 16 Memory Switch On MSW 01 Cache On 16 Bit Mode DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Maps Program X Data Y Data ala IPEFF External I O Internal I O FFCO FF80 FF80 Internal I O FFFF External External C000 C000 8000 8000 Internal Program RAM 64K Internal X data Internal Y data 0000 0000 RAM 32K 0000 RAM 32K Bit Settings Memory Configuration MSW m Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 10 0 1 64K 32K 32K None 64K 0000 FFFF 0000 7FFF 0000 7FFF Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that
428. ta receive data and SCI serial clock It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission up to 12 5 Mbps for a 100 MHz clock SCI asynchronous protocols include a multidrop mode for master slave operation with wakeup on idle line and wakeup on address bit capability This mode allows the DSP56311 to share a single serial line efficiently with other peripherals Separate SCI transmit and receive sections can operate asynchronously with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector allow the baud rate generator to function as a general purpose timer when the SCI is not using it or when the interrupt timing is the same as that used by the SCI Motorola Overview 1 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Peripherals 1 9 5 Timer Module The triple timer module is composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each with its own memory mapped register set Each timer has the following properties m A single signal that can function as a GPIO signal or as a timer signal m Uses internal or external clocking and can interrupt the DSP after a specified number of events clocks or signal an external device after counting internal events W Connection to t
429. tate During Name Type Reset Signal Description EXTAL Input Input External Clock Crystal Input EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock XTAL Output Chip driven Crystal Output XTAL connects the internal crystal oscillator output to an external crystal If an external clock is used leave XTAL unconnected Note The Clock Output CLKOUT is not functional in the DSP56311 The CLKOUT output pin provides a 50 percent duty cycle output clock synchronized to the internal processor clock when the Phase Lock Loop PLL is enabled and locked At 150 MHz and above CLKOUT produces a low amplitude waveform that is not usable externally by other devices Several alternatives to using CLKOUT exist such as enabling bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit ABE in the Operating Mode register When set the ABE bit eliminates the setup and hold time requirements with respect to CLKOUT for BB and BG Motorola Signals Connections 2 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PLL Table 2 5 Phase Locked Loop Signals State During P Signal Name Type Reset Signal Description PCAP Input Input PLL Capacitor PCAP is an input connecting an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to Vocp If the PLL is not used PCAP may be tied to
430. te initial data to the transmitters that are in use during operation This step is needed even 1f DMA services the transmitters 5 Enable the transmitters and receiver to be used Now the ESSI can be serviced by polling interrupts or DMA Once the ESSI is enabled Step 3 operation starts as follows 1 For internally generated clock and frame sync these signals start activity immediately after the ESSI is enabled 2 The ESSI receives data after a frame sync signal either internally or externally generated only when the receive enable RE bit is set 3 Data is transmitted after a frame sync signal either internally or externally generated only when the transmitter enable TE 2 0 bit is set Motorola Enhanced Synchronous Serial Interface ESSI 7 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operation 7 3 3 Exceptions The ESSI can generate six different exceptions They are discussed in the following paragraphs ordered from the highest to the lowest exception priority Note 7 8 ESSI receive data with exception status Occurs when the receive exception interrupt is enabled the receive data register is full and a receiver overrun error has occurred This exception sets the ROE bit The ROE bit is cleared when you first read the SSISR and then read the Receive Data Register RX ESSI receive data Occurs when the receive interrupt is enabled the recei
431. ter SCCR in Figure 8 5 m Status SCI Status Register SSR in Figure 8 4 m Data transfer SCI Receive Data Registers SRX in Figure 8 8 SCI Transmit Data Registers STX in Figure 8 8 SCI Transmit Data Address Register STXA in Figure 8 8 The SCI includes the GPIO functions described in Section 8 7 GPIO Signals and Registers on page 8 25 The next subsections describe the registers and their bits Motorola Serial Communication Interface SCI 8 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Mode 0 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO CA D7 D5 D4 v3 D2 DI SSFTD 1 One Byte From Shift Register 8 1 9 10 bit Asynchronous 1 Start 8 Data 1 Stop WDS2 WDS1 WDSO X SSFTD 1 1 0 0 11 bit Asynchronous 1 Start 8 Data 1 Even Parity 1 Stop WDS2 WDS1 WDSO TX SSFTD 1 L3 oo 4 11 bit Asynchronous 1 Start 8 Data 1 Odd Parity 1 Stop WDS2 WDS1 WDSO TX SSFTD 1 Stop Bit TX SSFTD 1 Data Type 1 Address Byte Note 1 Modes 1 3 and 7 are reserved 0 Data Byte 2 DO LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 Figure 8 1 SCI Data Word Formats SSFTD 1 1 8 10 DSP56311 User s Manual Motorola For More Information On This P
432. terface Single DS Double DS HI08 Port HRW HRD HRD PB11 HDS HDS HWR HWR PB12 Single HR Double HR HREQ HREQ HTRQ HTRQ PB14 HACK HACK HRRQ HRRQ PB15 Figure 5 2 Port B Signals 5 5 2 Port C Signals and Registers Each of the six Port C signals not used as an ESSIO signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port C Port C control register PCRC Port C direction register PRRC and Port C data register PDRC Chapter 7 Enhanced Synchronous Serial Interface ESSI discusses these registers Port C GPIO DSP56311 SC00 SC02 PCO PC2 Enhanced Synchronous SCKO PC3 Serial Interface Port 1 ESSIO SRDO PC4 STDO PC5 Figure 5 3 Port C Signals Motorola Programming the Peripherals 5 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Purpose Input Output GPIO 5 5 3 Port D Signals and Registers Each of the six Port D signals not used as an ESSII signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port D Port D control register PCRD Port D direction register PRRD and Port D data register PDRD Chapter 7 Enhanced Synchronous Serial Interface ESSI discusses these registers DSP56311 Port C GPIO SC10 SC02 PDO PD2 Enhanced Synchronous 4 SCK1 PD3 Serial Interface Port 1 ESSH SRD1 PD4 STD PD5 Figure 5
433. ters of length 256 It performs either 24 bit or 16 bit precision arithmetic with full support for saturation arithmetic A cost effective and power efficient coprocessor the EFCOP accelerates filtering tasks such as echo cancellation or correlation concurrently with software running on the DSP core 1 14 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Chapter 2 Freescale Semiconductor Inc Signals Connections The DSP56311 input and output signals are organized into functional groups as shown in Table 2 1 and illustrated in Figure 2 1 Table 2 1 DSP56311 Functional Signal Groupings Functional Group Number of Signals Description Power Voc 20 Table 2 2 Ground GND 19 Table 2 3 Clock 2 Table 2 4 PLL 3 Table 2 5 Address bus 18 Table 2 6 Port A Data bus 24 Table 2 7 Bus control 13 Table 2 8 Interrupt and mode control 5 Table 2 9 HI08 Port B 16 Table 2 10 ESSI Ports C and D 12 Table 2 11 Table 2 12 SCI Port E 3 Table 2 13 Time 3 Table 2 14 OnCE JTAG Port 6 Table 2 15 NOTES 1 Port A signals define the external memory interface port including the external address bus data bus and control signals The data bus lines have internal keepers 2 Port BB signals are the HIO8 port signals multiplexed with the GPIO signals All Port B signals have keepers 3 Port C and D signals are the two ESSI port si
434. th the real FIR filter type adaptive and multichannel modes These modes can be used individually or together 10 5 1 1 1 Adaptive Mode Adaptive mode provides a way to update the coefficients based on filter input x n using the following equation h h i K n x n i where h i is the ith coefficient at time n The coefficients are updated when FSCR FUPD is set The EFCOP checks to see if a value has been written to the FKIR If no value is written the EFCOP halts processing until a value is written to the FKIR When a value is written to the FKIR the EFCOP updates all the coefficients based on the above equation using the value in the FKIR for K n The EFCOP automatically clears FSCR FUPD when the coefficient update is complete If the coefficients are to be updated after every input sample Adaptive mode is enabled by setting the FCSR FADP In Adaptive mode the EFCOP automatically sets the FUDP bit after each input sample is processed This allows for continuous processing using interrupts that includes a filter session and a coefficient update session with minimal core intervention 10 5 1 1 2 Multichannel Mode Multichannel mode allows several channels of data to be processed concurrently and is selected by setting the FCSR FMLC The number of channels to process is one plus the number in the FDCH FDCM bits For each time period the EFCOP expects to receive the samples for each channel sequentially This is
435. that is if HREN is set and HEN is set then the HTRQ and HRRQ signals are active low outputs If HRP is set and host requests are enabled the HTRQ and HRRQ signals are active high outputs 13 HCSP Host Chip Select Polarity If the HCSP bit is cleared the host chip select HCS signal is configured as an active low input and the HIO8 is selected when the HCS signal is low If the HCSP signal is set HCS is configured as an active high input and the HIO8 is selected when the HCS signal is high 12 HDDS Host Dual Data Strobe If the HDDS bit is cleared the HIO8 operates in single strobe bus mode In this mode the bus has a single data strobe signal for both reads and writes If the HDDS bit is set the HIO8 operates in dual strobe bus mode In this mode the bus has two separate data strobes one for data reads the other for data writes See Figure 6 12 on page 6 21 and Figure 6 13 on page 6 21 for more information on dual and single strobe modes 6 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model Table 6 11 Host Port Control Register HPCR Bit Definitions Bit Number Bit Name Reset Value Description 11 HMUX 0 Host Multiplexed Bus If HMUX is set the HIO8 operates in multiplex mode latching the lower portion of a multiplexed address data bus In this mode the internal ad
436. the DSP puts out a clock on the SCLK pin To select master mode choose the internal transmit and receive clocks set TCM and RCM 0 As a peripheral synchronous slave the DSP accepts an input clock from the SCLK pin To select the slave mode choose the external transmit and receive clocks TCM and RCM 1 Since there is no frame signal if a clock is missed because of noise or any other reason the receiver loses synchronization with the data without any error signal being generated You can detect an error of this type with an error detecting protocol or with external circuitry such as a watchdog timer The simplest way to recover synchronization is to reset the SCI 8 1 2 Asynchronous Mode Asynchronous data uses a data format with embedded word sync which allows an unsynchronized data clock to be synchronized with the word if the clock rate and number of bits per word is known Thus the clock can be generated by the receiver rather than requiring a separate clock signal The transmitter and receiver both use an internal clock that is 16 x the data rate to allow the SCI to synchronize the data The data format requires that each data byte have an additional start bit and stop bit Also two of the word formats have a parity bit The Multidrop mode used when SCIs are on a common bus has an additional data type bit The SCI can operate in full duplex or half duplex modes since the transmitter and receiver are independent 8 1 3 Multidrop Mode
437. the TAS bit has no effect when the TA pin is deasserted you are responsible for deasserting the TA pin in synchrony with the chip clock regardless of the value of TAS 10 BE Cache Burst Mode Enable Enables disables Burst mode in the memory expansion port during an instruction cache miss If the bit is cleared Burst mode is disabled and only one program word is fetched from the external memory when an instruction cache miss condition is detected If the bit is set Burst mode is enabled and up to four program words are fetched from the external memory when an instruction cache miss is detected CDP 11 Core DMA Priority Specify the priority of core and DMA accesses to the external bus 00 Determined by comparing status register CP 1 0 to the active DMA channel priority 01 DMA accesses have higher priority than core accesses 10 DMA accesses have the same priority as the core accesses 11 DMA accesses have lower priority than the core accesses Motorola Core Configuration 4 13 For More Information On This Product Go to www freescale com Operating Mode Register OMR Freescale Semiconductor Inc Table 4 6 Operating Mode Register OMR Bit Definitions Continued Bit Number Bit Name Reset Value Description 7 MS 0 Memory Switch Mode Allows some internal data memory X Y or both to become part of the chip internal Program RAM Notes 1
438. the TEIE bit is set the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller 7 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ESSI Programming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 17 RE 0 Receive Enable Enables disables the receive portion of the ESSI When RE is cleared the receiver is disabled data transfer into RX is inhibited If data is being received while this bit is cleared the remainder of the word is shifted in and transferred to the ESSI receive data register RE must be set in both Normal and On Demand modes for the ESSI to receive data In Network mode clearing RE and setting it again disables the receiver after reception of the current data word The receiver remains disabled until the beginning of the next data frame NOTE The setting of the RE bit does not affect the generation of a frame sync 16 TEO Transmit 0 Enable Enables the transfer of data from TX1 to Transmit Shift Register 0 TEO is functional when the ESSI is in either synchronous or Asynchronous mode When TEO is set and a frame sync is detected the transmitter 0 is enabled for that frame When TEO is cleared transmitter O is disabled after the transmission of data currently in the ESSI transm
439. the host side Interface Control Register ICR 5 ZHLEND allows the host to access the HI08 data registers in Big Endian or Little Endian mode In Little Endian mode HLEND 1 a host transfer occurs as shown in the Figure 6 4 HTX HRX Bit Number 23 0 aa bb cc DSP side A Host side Y Low Byte cc bb aa lt High Byte read write last Host bus address 5 6 7 Host 32 bit bb ES XX cc internal register Figure 6 4 HI08 Read and Write Operations in Little Endian Mode The host can transfer one byte at a time so a 24 bit datum would be transferred using three store or load byte operations ensuring that the data byte at host bus address 7 is written last since this causes the transfer of the data to the DSP side HRX However the host bus controller may be sophisticated enough that the host can transfer all bytes in a single operation instruction For example in the Power PC MPC860 processor the General Purpose Controller Module GPCM in the memory controller can be programmed so that the host can execute a single read load word LDW or write store word STW instruction to the HIOS port and cause four byte transfers to occur on the host bus The 32 bit datum transfer shown in Figure 6 4 has byte data xx written to HI08 address 4 byte aa to address 5 byte bb to address 6 and byte cc to address 7 this assumes the 24 bit datum is contained in the lo
440. the last state even if all drivers are tri stated 2 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HIO8 Table 2 10 Host Interface Continued 3 State During ES Signal Name Type Reset Signal Description HRW Input Input Host Read Write When HI08 is programmed to interface a single data strobe host bus and the HI function is selected this signal is the Host Read Write HRW input m Host Read Data When HI08 is programmed to interface a HRD HRD Input double data strobe host bus and the HI function is selected this signal is the HRD strobe Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HRD after reset Port B 11 When the HIO08 is configured as GPIO through the HPCR this signal is individually programmed as an input or PB11 Input or output through the HDDR Output NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated HDS HDS Input Input Host Data Strobe When HI08 is programmed to interface a single data strobe host bus and the HI function is selected this signal is the host data strobe HDS Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HDS following reset Host Write Data When HIO8 is programmed to interface a HWR HWR Input double data strobe h
441. the transmitters are not in use A protocol is still needed to prevent two transmitters from simultaneously driving the bus The SCI multidrop word format provides an address field to support this protocol 8 1 3 3 Idle Line Wakeup A wakeup mode frees a DSP from reading messages intended for other processors The usual operational procedure is for each DSP to suspend SCI reception the DSP can continue processing until the beginning of a message Each DSP compares the address in the message header with the DSP s address If the addresses do not match the SCI again suspends reception until the next address If the address matches the DSP reads and processes the message and then suspends reception until the next address The Idle Line Wakeup mode wakes up the SCI to read a message before the first character arrives 8 1 3 4 Address Mode Wakeup The purpose and basic operational procedure for Address Mode Wakeup is the same as for Idle Line Wakeup The difference is that Address Mode Wakeup re enables the SCI when the ninth bit in a character is set to one if cleared this bit marks a character as data if set an address As a result an idle line is not needed which eliminates the dead time between messages 8 2 I O Signals Each of the three SCI signals RXD TXD and SCLK can be configured as either a GPIO signal or as a specific SCI signal Each signal is independent of the others For example if only the TXD signal is needed the RXD
442. tibility Figure 7 19 Port Direction Register PRR PRRC X FFFFBE PRRD X FFFFAE The following table shows the port signal configurations PC i PDC i Port Signal i Function 1 X ESSI 0 0 GPIO input 0 1 GPIO output X The signal setting is irrelevant to the Port Signal i function Motorola Enhanced Synchronous Serial Interface ESSI 7 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GPIO Signals and Registers 7 6 3 Port Data Register PDR The read write 24 bit PDR reads or writes data to and from the ESSI GPIO signals The PD 5 0 bits read or write data from and to the corresponding port signals if they are configured as GPIO signals If a port signal i is configured as a GPIO input the corresponding PD i bit reflects the value present on this signal If a port signal i is configured as a GPIO output the value written into the corresponding PD i bit is reflected on this signal Either a hardware RESET signal or a software RESET instruction clears all PDR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD5 PD4 Pps PD2 PDt PDO STDn SRDn SCKn SCn2 SCni SCn0 PDRC ESSIO PDRD ESSI1 C Reserved Read as zero Write with zero for future compatibility Figure 7 20 Port Data Register PDR PDRC X FFFFBD PDRD X FFFFAD 7 38 DSP56311 User s Manual Motorola For More Information On This Product Go to www freesca
443. ting the previous outputs down in the FDM This is done for each sample input to the FDIR To process a complete IIR filter a FIR filter type session followed by an IIR filter type session is needed FDM FCM y n 1 lt gt Ao HE med FDOR y n 2 gt A 3 e gt A 4 FDIR bam Cone An Figure 10 8 IIR Filter Type Processing Real mode is one of two operating modes available with the IIR filter type Thus the FCSR FOM bits are ignored when the IIR filter type is in use Real mode performs IIR type filtering with real data One sample the real input is written to the FDIR and the EFCOP processes the data Then one sample the real output is read from the FDOR Another option available for the IIR filter type is Multichannel mode Multichannel mode for IIR filter type works exactly the same as it does for FIR filter type as explained in Section 10 5 1 1 2 Multichannel Mode on page 10 17 Decimation and Adaptive modes are not available with the IIR filter type Initialization is always disabled with the IIR filter type and the FCSR FPRC bit is ignored Thus the DSP56300 core must write the initial input values before the EFCOP is enabled The first value written to FDIR is always the first sample to be filtered Motorola DSP56311 User s Manual 10 20 For More Information On This Product Go to www freescale com Freescale Semiconductor I
444. tion On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets SCI Transmit Data Registers X FFFF97 Address X FFFF95 X FFFF97 X SFFFF96 Write Reset xxxxxx X SFFFF95 SCI Receive Data Registers X FFFF9A Address X FFFF98 X FFFF9A X FFFF99 Read Reset xxxxxx X GFFFF98 NOTE STX is the same register decoded at three different addresses SCI Receive Data Registers Figure B 21 SCI Receive and Transmit Data Registers SRX TRX B 32 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Timers PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIOO 10 TIO1 11 TIO2 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 PS1 PSO Hida Prescaler Preload Value PL 0 20 Timer Prescaler Load Register x Reserved Program as 0 TPLR FFFF83 Read Write Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 Current Value of Prescaler Counter PC 0 20 Timer Prescaler Count Register Reserved Program as 0 TPCR FFFF82 Read Only Reset 000000 Figure B 22 Timer Prescaler Load Count Register TPLR TPCR Motorola Programming Reference B 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming Sheets Inverter Bit 8 0 0 to 1 transitions on TIO
445. tion of how the control registers are mapped in the DSP56311 data transfer methods that are available when the various peripherals are used and information on General Purpose Input Output GPIO configuration 5 1 Peripheral Initialization Steps Each peripheral has its own initialization process However all four peripherals share some common steps which follow 1 Determine the Register values to be programmed Find the peripheral register descriptions in the manual Choose the appropriate modes to configure for a given application Determine the bit settings for programming those modes 2 Make sure the peripheral is in individual reset state or disabled Peripheral registers should not be modified while the peripheral is active 3 Configure the registers by writing the predetermined values to them Write the register values determined in step 1 into the appropriate register locations 4 Enable the peripheral Once the peripheral is enabled it operates according the programmed modes determined in step 1 For detailed initialization procedures unique to each peripheral consult the initialization section within each peripheral s chapter Motorola Programming the Peripherals 5 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mapping the Control Registers 5 2 Mapping the Control Registers The I O peripherals are controlled through registers mapped to the to
446. tiplexed bus 2 3 multiplexed bus mode 6 20 multiplexed bus modes 6 17 multiplexed mode 6 4 Multiplier Accumulator MAC 1 6 N network enhancements to ESSI 7 2 Network mode 7 8 Index 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Network mode interrupt ESSI 7 20 non multiplexed bus 2 3 non multiplexed mode 6 4 O OFO0 OFI bits 7 19 off chip memory expansion 3 1 offset adder 1 7 OMR 1 8 4 11 OnCE 1 5 OnCE module 1 9 interface 2 20 OnCE JTAG 2 3 On Chip Emulation OnCE module 1 9 on chip memory 1 9 On Demand mode 7 10 Operating 4 1 operating mode 4 1 4 2 ESSI 7 10 synchronous ESSI 7 11 Operating Mode Register 4 11 Operating Mode Register OMR 1 8 operating mode HI08 6 17 operating modes 4 1 operational mode select ESSI 7 22 P PAB 1 10 PAG 1 7 Parity Error bit PE 8 17 PC register 1 8 PCRC register 7 36 PCRD register 7 36 PCRE register 8 25 PCTL 4 21 PCTL register 4 21 PCU 1 7 PDB 1 10 PDC 1 7 PDRC register 7 38 PDRD register 7 38 PDRE register 8 26 PE bit 8 17 Peripheral I O Expansion Bus 1 10 peripherals programming bit oriented instructions 5 2 data transfer methods 5 3 individual reset state 5 1 initializat steps 5 1 interrupts 5 3 mapping control registers 5 2 move MOVE MOVED instructions 5 2 polling 5 3 reading status registers 5 2 peripherals programming guidelines 5 1 PIC 1 7 PLL 1 8 2 5 PLL Control R
447. to www freescale com Freescale Semiconductor Inc JTAG and OnCE Interface 2 22 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 3 Memory Configuration Like all members of the DSP56300 core family the DSP56311 can address three sets of 16 M x 24 bit memory internally program X data and Y data Each of these memory spaces includes both on chip and external memory accessed through the external memory interface The DSP56311 is extremely flexible because it has several modes to allocate on chip memory between the program memory and the two data memory spaces You can also configure it to operate in a special sixteen bit compatibility mode that allows the chip to use DSP56000 object code without any change this can result in higher performance of existing code for applications that do not require a larger address space This section provides detailed information on each of these memory spaces 3 1 Program Memory Space Program memory space consists of the following W Internal program memory program RAM 32K by default up to 96K m Optional instruction cache 1K formed from program RAM W Bootstrap program ROM 192 x 24 bit a Optional off chip memory expansion as much as 128K in 16 bit mode or 256K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to th
448. to low signal transitions are selected If INV is cleared low to high signal transitions are selected After the first appropriate transition occurs on the TIO input signal the counter is loaded with the TLR value On the next signal transition of the same polarity that occurs on TIO TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The contents of the counter load into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO signal After the second signal transition if the TCSR TRM bit is set the TCSR TE bit is set to clear the counter and enable the timer The counter is repeatedly loaded and incremented until the timer is disabled If the TCSR TRM bit is cleared the counter continues to increment until it overflows Motorola Triple Timer Module 9 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes Mode 5 internal clock TRM 1 first event N write preload 4 M write compare TE Clock CLK 2 or prescale CLK TLR DLN Counter x 0 N N 1 M N TCR M a TIO pin period being measured TCF Compare Interrupt if TCIE 1 NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO loads TCR with count and the counter with N Figure 9 13 Period Measurement
449. to the core features the DSP56311 provides the following peripherals As many as 34 user configurable GPIO signals HI08 to external hosts Dual ESSI SCI Triple timer module Memory switch mode Four external interrupt mode control lines 1 9 1 GPIO Functionality The GPIO port consists of up to 34 programmable signals also used by the peripherals HIOS8 ESSI SCI and timer There are no dedicated GPIO signals After a reset the signals are automatically configured as GPIO Three memory mapped registers per peripheral control GPIO functionality Programming techniques for these registers to control GPIO functionality are detailed in Chapter 5 Programming the Peripherals 1 9 2 HI08 The HIOS is a byte wide full duplex double buffered parallel port that can connect directly to the data bus of a host processor The HIO8 supports a variety of buses and provides connection with a number of industry standard DSPs microcomputers and microprocessors without requiring any additional logic The DSP core treats the HIO8 as a memory mapped peripheral occupying eight 24 bit words in data memory space The DSP can use the HI08 as a memory mapped peripheral using either standard polled or interrupt programming techniques Separate double buffered transmit and receive data registers allow the DSP and host processor to transfer data efficiently at high speed Memory 1 12 DSP56311 User s Manual Motorola For More Information On This Product
450. torola Core Configuration 4 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Attribute Registers AARO AARS3 Table 4 9 Address Attribute Registers AARO AAR3 Bit Definitions Bit Number Bit Name Reset Value Description 7 BPAC 0 Bus Packing Enable Enables disables the internal packing unpacking logic When BPAC is set packing is enabled In this mode each DMA external access initiates three external accesses to an 8 bit wide external memory the addresses for these accesses are DAB then DAB 1 and then DAB 2 Packing to a 24 bit word or unpacking from a 24 bit word to three 8 bit words is done automatically by the expansion port control hardware The external memory should reside in the eight Least Significant Bits LSBs of the external data bus and the packing or unpacking for external write accesses occurs in Little Endian order i e the low byte is stored in the lowest of the three memory locations and is transferred first the middle byte is stored transferred next and the high byte is stored transferred last When this bit is cleared the expansion port control logic assumes a 24 bit wide external memory NOTES 1 BPAC is used only for DMA accesses and not core accesses 2 To ensure sequential external accesses the DMA address should advance three steps at a time in two dimensional mode with a row length of one and an
451. transmit data register Port E 1 The default configuration following reset is GPIO input PE1 When configured as PE1 signal direction is controlled through the SCI PRR The signal can be configured as an SCI signal TXD through the SCI PCR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated SCLK PE2 Input Output Input or Output Input Serial Clock The bidirectional Schmitt trigger input signal providing the input or output clock used by the transmitter and or the receiver Port E 2 The default configuration following reset is GPIO input PE2 When configured as PE2 signal direction is controlled through the SCI PRR The signal can be configured as an SCI signal SCLK through the SCI PCR NOTE This signal has a weak keeper to maintain the last state even if all drivers are tri stated 2 11 Timers The DSP56311 has three identical and independent timers Each timer can use internal or external clocking and either interrupt the DSP56311 after a specified number of events clocks or signal an external device after counting a specific number of internal events Motorola Signals Connections 2 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG and OnCE Interface Table 2 14 Triple Timer Signals Signal Name Type State During Reset Signal Description TIOO Input o
452. trol Register HCR This read write register controls the HIOS8 interrupt operation Initialization values for HCR bits are presented in Section 6 6 9 DSP Side Registers After Reset on page 6 22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF3 HF2 HCIE HTIE HRIE heserved bit read as 0 should be written with 0 for future compatibility Figure 6 6 Host Control Register HCR X FFFFC2 Table 6 7 Host Control Register HCR Bit Definitions Bit Number Bit Name Reset Value Description 15 5 0 Reserved Set to 0 for future compatibility 4 3 HF 3 2 0 Host Flags 2 3 General purpose flags for DSP to host communication The DSP core can set or clear HF 3 2 The values of HF 3 2 are reflected in the interface status register ISR that is if they are modified by the DSP software the host processor can read the modified values by reading the ISR These two general purpose flags can be used individually or as encoded pairs in a simple DSP to host communication protocol implemented in both the DSP and the host processor software The bit value is indeterminate after an individual reset 2 HCIE 0 Host Command Interrupt Enable Generates a host command interrupt request if the host command pending HCP status bit in the HSR is set If HCIE is cleared HCP interrupts are disabled The interrupt address is determined by the host command vector registe
453. trol Signal SC2 ESSI0 SC02 ESSI1 SC12 SC2 is a frame sync I O signal for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode The direction of this signal is determined by the SCD2 bit in the CRB When configured as an output this signal outputs the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter in Asynchronous mode and for both the transmitter and receiver when in Synchronous mode SC2 can be programmed as a GPIO signal P2 when the ESSI SC2 function is not in use 7 3 Operation This section discusses ESSI basics reset state initialization and exceptions 7 3 14 ESSI After Reset A hardware RESET signal or software RESET instruction clears the port control register and the port direction control register thus configuring all the ESSI signals as GPIO The ESSI is in the reset state while all ESSI signals are programmed as GPIO it is active only if at least one of the ESSI I O signals is programmed as an ESSI signal 7 3 2 Initialization To initialize the ESSI do the following 1 Sendareset hardware RESET signal software RESET instruction ESSI individual reset or STOP instruction reset 2 Program the ESSI control and time slot registers 3 Write data to all the enabled transmitters 7 6 DSP56311 User s Manual Motorola For More Information On This Product Go to www freesc
454. ts of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TCSR TE bit and the detection of the first clock edge signal on the TIO signal The value of the INV bit determines whether a high to low 1 to 0 or low to high 0 to 1 transition of the external clock signals the end of the timing period If the INV bit is set a high to low transition signals the end of the timing period If INV is cleared a low to high transition signals the end of the timing period Mode 6 internal clock TRM 1 first event N write preload l M write compare TE Clock M CLK 2 or prescale CLK TLR GEN Counter stops Counter X 0 N N 1 M XN counting overflow may occur before capture TOF 1 TCR M TIO pin delay being measured Interrupt Service reads TCR delay TCF Compare Interrupt if TCIE 1 mis cle NOTE If INV 1 a 1 to 0 edge on TIO loads TCR with count and stops the counter Figure 9 15 Capture Measurement Mode TRM 0 Motorola Triple Timer Module 9 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Modes 9 3 3 Pulse Width Modulation PWM Mode 7 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 1 1 7 Pulse width modulation PWM Output Internal In
455. ty 0 Clock Polarity is Positive 1 Clock Polarity is Negative SCI Receive Exception Inerrupt 0 Receive Interrupt Disable 1 Receive Interrupt Enable SCI Control Register SCR Address X FFFF9C Read Write Port E Pin Control 0 General Purpose I O Pin 1 SCI pin x Reserved Program as 0 Port E Control Register PCRE Word Select Bits 0 0 8 bit Synchronous Data Shift Register Mode Reserved 10 bit Asynchronous 1 Start 8 Data 1 Stop Reserved 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 11 bit Multidrop 1 Start 8 Data Data Type 1 Stop Reserved i 4 0O0C000 01 10 11 00 01 10 11 SCI Shift Direction 0 LSB First 1 MSB First Receiver Wakeup Enable 0 receiver has awakened 1 Wakeup function enabled Wired Or Mode Select 1 Multidrop 0 Point to Point Send Break 0 Send break then revert 1 Continually send breaks Receiver Enable 0 Receiver Disabled 1 Receiver Enabled Wakeup Mode Select 0 Idle Line Wakeup 1 Address Bit Wakeup x Reserved Program as 0 SCI Control Register SCR Figure B 19 SCI Control Register SCR B 30 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Programming Sheets Overrun Error Flag Idle Line Flag 0 No error 0 Idle not detected 1 Overrun detected 1 Idl
456. ty SCI transmit data register 8 18 enable receiver 8 14 enable transmitter 8 14 enable wakeup function 8 15 enable disable SCI receive data interrupt 8 13 enable disable SCI receive data with exception interrupt 8 12 enable disables SCI transmit data interrupt 8 13 establish a periodic interrupt 8 20 Idle Line Wakeup mode 8 3 incorrect parity bit is detected in received character 8 17 individual reset state PCR 0 8 6 Inter processor messages 8 2 interrupts 8 6 maximum internal clock 8 19 Multidrop mode 8 2 recover synchronization 8 2 SCR SCCR 8 6 select format of transmitted and received data 8 16 select wakeup on idle line mode 8 15 select whether internal or external clock is used for transmitter 8 21 Serial Clock 8 20 STX or STXA 8 22 transmit and receive shift registers 8 2 Wired OR mode 8 3 Serial Communications Interface SCI 1 13 8 1 Synchronous mode 8 2 Serial Control 0 7 4 Serial Control 0 Direction bit SCDO 7 24 serial control 0 signal SCO 7 4 7 5 Serial Control 1 7 5 Serial Control 1 Direction bit SCD1 7 24 Serial Control 2 7 6 serial flag signal or receive clock signal 7 4 Serial Input Flag 0 bit IFO 7 31 Serial Output Flag bits OF0 OFI1 7 19 Index 12 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Serial Receive Data 7 3 Serial Receive Data signal SRD 7 3 serial receive shift register is filled and ready to tran
457. u can photocopy these sheets and reuse them for each application development project For details on the instruction set of the DSP56300 family of DSPs see the DSP56300 Family Manual m Table B 2 Internal X I O Memory Map on page B 2 and Table B 3 Internal Y I O Memory Map on page B 7 list the memory addresses of all on chip peripherals m Table B 4 Interrupt Sources on page B 8 lists the interrupt starting addresses and sources m Table B 5 Interrupt Source Priorities Within an IPL on page B 10 lists the priorities of specific interrupts within interrupt priority levels m The programming sheets appear in this manual as figures listed in Table B 1 they show the major programmable registers on the DSP56311 Table B 1 Guide to Programming Sheets Module Programming Sheet Page Central Figure B 1 Status Register SR page B 12 pipgessot Figure B 2 Operating Mode Register page B 13 Figure B 3 Address Attribute Registers AAR3 AARO page B 14 Figure B 4 Bus Control Register BCR page B 15 Figure B 5 DMA Control Register DCR page B 16 Figure B 6 Interrupt Priority Register Core IPR C page B 17 Figure B 7 Interrupt Priority Register Peripherals IPR P page B 18 PLL Figure B 8 Phase Lock Loop Control Register PCTL page B 19 Motorola Programming Reference B 1 For More Information On This Product Go to www freescale com Internal I
458. uction sets TDRE In Synchronous mode when the internal SCI clock is in use there is a delay of up to 5 5 serial clock cycles between the time that STX is written until TDRE is set indicating the data has been transferred from the STX to the transmit shift register There is a delay of 2 to 4 serial clock cycles between writing STX and loading the transmit shift register in addition TDRE is set in the middle of transmitting the second bit When using an external serial transmit clock if the clock stops the SCI transmitter stops TDRE is not set until the middle of the second bit transmitted after the external clock starts Gating the external clock off after the first bit has been transmitted delays TDRE indefinitely In Asynchronous mode the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the transmit shift register nor when the word first begins to be shifted out TDRE is set 2 cycles of the 16 x clock after the start bit that is 2 16 x clock cycles into the transmission time of the first data bit 8 18 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Programming Model Table 8 3 SCI Status Register SSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 0 TRNE 1 Transmitter Empty This flag bit is set when both the transmit shift register and transmit data re
459. uctor Inc EFCOP Programming Model Table 10 4 FCSR Bits Bit Number Bit Name Reset Value Description 23 16 These bits are reserved and unused They are read as 0 and should be written with O for future compatibility 15 FDOBF Filter Data Output Buffer Full When set this read only status bit indicates that the FDOR is full and the DSP can read data from the FDOR The FDOBF bit is set when a result from FMAC is transferred to the FDOR For proper operation read data from the FDOR only if the FDOBF status bit is set When FDOBF is set the EFCOP generates an FDOBF interrupt request to the DSP56300 core if that interrupt is enabled that is FDOIE 1 A DMA request is always generated when the FDOBF bit is set but a DMA transfer takes place only if a DMA channel is activated and triggered by this event A read from the FDOR clears the FDOBF bit 14 FDIBE Filter Data Input Buffer Empty When set this read only status bit indicates that the FDIR is empty and the DSP can write data to the FDIR The FDIBE bit is set when all four FDIR locations are empty For proper operation write data to the FDIR only if FDIBE is set After the EFCOP is enabled by setting FEN FDIBE is set indicating that the FDIR is empty When FDIBE is set the EFCOP generates an FDIR empty interrupt request to the DSP56300 core if enabled that is FDIIE 2 1 A DMA request is always generated when the FDIBE bit is set but
460. uld be written with O for future compatibility 5 0 FCHL 0 Filter Channels These read write control bits determine the number of filter channels to process simultaneously from 1 to 64 in multichannel mode The number represented by the FCHL bits is one less than the number of channels to be processed that is if FCHL 0 then 1 channel is processed if FCHL 1 then 2 channels are processed and so on NOTE To ensure proper operation never change the FCHL bits unless the EFCOP is in the individual reset state FEN 0 10 3 10 EFCOP Interrupt Vectors Table 10 7 shows the EFCOP interrupt vectors and Table 10 8 shows the DMA request sources Table 10 7 EFCOP Interrupt Vectors Interrupt X Interrupt Interrupt Address mermupt etit Priority Enable Conditions VBA 68 Data input buffer empty Highest FDIIE FDIBE 1 VBA 6A Data output buffer full Lowest FDOIE FDOBF 1 Table 10 8 EFCOP DMA Request Sources Requesting Device Number Request Conditions Peripheral equest MDRQ EFCOP input buffer empty FDIBE 1 MDRQ11 EFCOP output buffer full FDOBF 1 MDRQ12 10 4 EFCOP Programming The DSP56311 Enhanced Filter Coprocessor EFCOP supports both Finite Impulse Response FIR filters and Infinite Impulse Response IIR filters This section discusses the different ways data can be transferred in and out of the EFCOP and presents some programming examples in
461. ull ISR RXDF on the host side bits are cleared This transfer operation sets the ISR RXDF and HSR HTDE bits The DSP56311 can set the HCR HTIE bit to cause a host transmit data interrupt when HSR HTDE is set To prevent the previous data from being overwritten data should not be written to the HTX until HSR HTDE is set Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of the status bits within the next two cycles the bit does not reflect its current status For details see the DSP56300 Family Manual Appendix B Polling a Peripheral Device for Write Motorola Host Interface H108 6 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model 6 6 8 Host Receive Data Register HRX The HRX register performs host to DSP data transfers The DSP56311 views it as a 24 bit read only register Its address is X SFFFFCO It is loaded with 24 bit data from the transmit data registers TXH TXM TXL on the host side when both the transmit data register empty ISR TXDE on the host side and host receive data full HSR HRDF on the DSP side are cleared The transfer operation sets both ISR TXDE and HSR HRDF When the HSR HRDF is set the HRX register contains valid data The DSP56311 can set the HCR HRIE to cause a host receive data interrupt when HSR HRDF is se
462. umber of words do a0 LOOPIO read program words do 3 LOOPII Each instruction has 3 bytes movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into Al LOOPII Go get another byte movem al p r0 Store 24 bit result in P mem nop pipeline delay LOOPIO and go get another 24 bit word Boot from EPROM done FINISH This 1s the exit handler that returns execution to normal expanded mode and jumps to the RESET vector andi 0 cer Clear CCR as if RESET to 0 jmp r1 Then go to starting Prog addr 3 The following modes are reserved some of which are used for internal testing Can be implemented in future OMROXXX jelr 2 omr RESERVED MD MC MB MA 00xx is reserved jelr 1 omr RESERVED MD MC MB MA 010x is reserved jelr 0 omr RESERVED MD MC MB MA 0110 is reserved MD MC MB MA 0111 is reserved RESERVED bra end A 8 DSP56311 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Internal I O Equates A 2 Internal I O Equates E GLLLLLLLLLLILILLLILLLLLLLLLLLLLLLLLLLLLLLLLLILLLLLLLLLLLLLLLILLLLLLLLLLLLELLI gt EQUATES for DSP56311 I O registers and ports Last update February 20 1999 gt AEE EE S a IR DC HE o a 2 o o OIE k oe 2 k o o e o a 2 k DC k k k k k k k k k kk kk kk k kk k k gt page 132 55 0 0 0 opt mex loequ ident 1 0 Register Addresses M HDDR EQU
463. us in a round robin pattern e g P X Y DMA P X Y Priority Core DMA OMR Mode Priority Priority CDP 1 0 SR CP 1 0 Dynamic 0 Determined 00 00 Lowest by DCRn DPR 1 0 1 for active oy El 2 DMA 00 10 channel 3 00 11 Highest Static core DMA 01 Xx core DMA 10 XX core gt DMA 11 XX 4 16 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Status Register SR Table 4 7 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 21 RM 0 Rounding Mode Selects the type of rounding performed by the Data ALU during arithmetic operations If RM is cleared convergent rounding is selected If RM is set two s complement rounding is selected 20 SM 0 Arithmetic Saturation Mode Selects automatic saturation on 48 bits for the results going to the accumulator This saturation is performed by a special circuit inside the MAC unit The purpose of this bit is to provide an Arithmetic Saturation mode for algorithms that do not recognize or cannot take advantage of the extension accumulator 19 CE 0 Cache Enable Enables disables the instruction cache controller If CE is set the cache is enabled and instructions are cached into and fetched from the internal Program RAM If CE is cleared the cache is disabled and the DSP56300 core fetches instructions from external or inte
464. us mode then HA8 HA1 is a GPIO signal according to the value of the HDDR and HDR NOTE HA8EN is ignored when the HIO8 is not in the multiplexed bus mode that is when HMUX is cleared 0 HGEN 0 Host GPIO Port Enable Enables disables signals configured as GPIO If this bit is cleared signals configured as GPIO are disconnected outputs are high impedance inputs are electrically disconnected Signals configured as HIO8 are not affected by the value of HGEN 6 20 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Core Programming Model In a single strobe bus a DS data strobe signal qualifies the access while a R W Read Write signal specifies the direction of the access Figure 6 12 Single Strobe Bus HWR Write Cycle N Data X ReadDataout X Data Out HRD Read Cycle In dual strobe bus separate HRD and HWR signals specify the access as a read or write access respectively Figure 6 13 Dual Strobe Bus 6 6 7 Host Transmit Data Register HTX The HTX register performs DSP to host data transfers The DSP56311 views it as a 24 bit write only register Its address is X SFFFFC7 Writing to the HTX register clears the host transfer data empty bit HSR HTDE on the DSP side The contents of the HTX register are transferred as 24 bit data to the receive byte registers RXH RXM RXL when both HSR HTDE and receive data f
465. ut of reset is a disabled stack extension 19 WRP 0 Stack Extension Wrap Flag Set when copying from the on chip hardware stack System Stack Register file to the stack extension memory begins You can use this flag during the debugging phase of the software development to evaluate and increase the speed of software implemented algorithms The WRP flag is a sticky bit i e cleared only by hardware reset or by an explicit MOVEC operation to the OMR 18 EOV 0 Stack Extension Overflow Flag Set when a stack overflow occurs in Stack Extended mode Extended stack overflow is recognized when a push operation is requested while SP SZ Stack Size register and the Extended mode is enabled by the SEN bit The EOV flag is a sticky bit i e cleared only by hardware reset or by an explicit MOVEC operation to the OMR The transition of the EOV flag from zero to one causes a Priority Level 3 Non maskable stack error exception 17 EUN 0 Stack Extension Underflow Flag Set when a stack underflow occurs in Extended Stack mode Extended stack underflow is recognized when a pull operation is requested SP 0 and the SEN bit enables Extended mode The EUN flag is a sticky bit i e cleared only by hardware reset or by an explicit MOVEC operation to the OMR Transition of the EUN flag from zero to one causes a Priority Level 3 Non maskable stack error exception NOTE While the chip is in Extended Stack mode the UF bit in the SP acts like
466. ve data register is full and no receive error conditions exist A read of RX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead ESSI receive last slot interrupt Occurs when the ESSI is in Network mode and the last slot of the frame has ended This interrupt is generated regardless of the receive mask register setting The receive last slot interrupt can signal that the receive mask slot register can be reset the DMA channels can be reconfigured and data memory pointers can be reassigned Using the receive last slot interrupt guarantees that the previous frame is serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems The maximum time it takes to service a receive last slot interrupt should not exceed N 1 ESSI bits service time where N is the number of bits the ESSI can transmit per time slot ESSI transmit data with exception status Occurs when the transmit exception interrupt is enabled at least one transmit data register of the enabled transmitters is empty and a transmitter underrun error has occurred This exception sets the TUE bit The TUE bit is cleared when you first read the SSISR and then write to all the transmit data registers of the enabled transmitters or when you write to TSR to clear the pending interrupt ESSI transmit last slot interrupt Occurs when the ESSI is in Network mode at the
467. ved bit read as 0 should be written with 0 for future compatibility Figure 6 11 Host Port Control Register HPCR X FFFFC4 To assure proper operation of the DSP56311 the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN and HREN should be changed only if HEN is cleared Similarly the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN and HASEN should not be set when HEN is set nor at the time HEN is set Table 6 11 Host Port Control Register HPCR Bit Definitions Bit Number Bit Name Reset Value Description 15 HAP 0 Host Acknowledge Polarity If HAP is cleared the host acknowledge HACK signal is configured as an active low input The HIO8 drives the contents of the IVR onto the host bus when the HACK signal is low If the HAP bit is set the HACK signal is configured as an active high input The HI08 outputs the contents of the IVR when the HACK signal is high 14 HRP Host Request Polarity Controls the polarity of the host request signals In single host request mode that is when HDRQ is cleared in the ICR if HRP is cleared and host requests are enabled that is if HREN is set and HEN is set then the HREQ signal is an active low output If HRP is set and host requests are enabled the HREQ signal is an active high output In the double host request mode that is when HDRQ is set in the ICR if HRP is cleared and host requests are enabled
468. w output that is asserted to write external memory on the data bus DO D23 Otherwise the signals are tri stated Motorola Signals Connections 2 7 For More Information On This Product Go to www freescale com External Memory Expansion Port Port A Freescale Semiconductor Inc Table 2 8 External Bus Control Signals Continued Signal Name Type State During Reset Signal Description Input Ignored Input Transfer Acknowledge lf the DSP56311 is the bus master and there is no external bus activity or the DSP56311 is not the bus master the TA input is ignored The TA input is a data transfer acknowledge DTACK function that can extend an external bus cycle indefinitely Any number of wait states 1 2 infinity may be added to the wait states inserted by the bus control register BCR by keeping TA deasserted In typical operation TA is deasserted at the start of a bus cycle is asserted to enable completion of the bus cycle and is deasserted before the next bus cycle The current bus cycle completes one clock period after TA is asserted synchronous to the internal clock The number of wait states is determined by the TA input or by the BCR whichever is longer The BCR can be used to set the minimum number of wait states in external bus cycles To use the TA functionality the BCR must be programmed to at least one wait state A zero wait state access cannot be extended by TA deasse
469. wer All DSP56300 core family members contain the DSP56300 core and additional modules The modules are chosen from a library of standard predesigned elements such as memories and peripherals New modules can be added to the library to meet customer specifications A standard interface between the DSP56300 core and the on chip memory and peripherals supports a wide variety of memory and peripheral configurations In particular the DSP56311 includes Motorola s JTAG port and OnCE module The DSP56311 with its large on chip memory array of 128K words and its EFCOP is well suited for high end multichannel telecommunication applications such as wireless infrastructure multi line voice data FA X processing video conferencing and general digital signal processing 1 4 DSP56311 User s Manual Motorola For More Information On This Product Go to www freescale com 1 4 Freescale Semiconductor Inc DSP56300 Core DSP56300 Core Core features are fully described in the DSP56300 Family Manual This manual in contrast documents pinout memory and peripheral features Core features are as follows 1 5 150 MIPS 255 MIPS using the EFCOP in filtering applications with a 150 MHz clock at 1 8 V Object code compatible with the DSP56000 core Highly parallel instruction set Large on chip RAM memory of 128K words EFCOP running concurrently with the core capable of executing 100 million filter taps per second at peak performance Har
470. wer 24 bits of the host s 32 bit data register as shown A similar operation occurs when the HIOS is initialized in Big Endian mode by clearing the Host Little Endian bit ICR 5 ZHLEND Big Endian mode is depicted in Figure 6 5 Motorola Host Interface H108 6 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Boot up Using the HI08 Host Port HTX HRX Register 23 0 aa bb cc DSP side i Host side Y High Byte aa bb cc Low Byte read write last Host bus address 5 6 7 Host Pep T i internal register Figure 6 5 HI08 Read and Write Operations in Big Endian Mode 6 5 Boot up Using the HI08 Host Port The DSP56300 core has eight bootstrap operating modes to start up after reset As the processor exits the Reset state the value at the external mode pins MODA IRQA MODB IRQB MODC IRQC and MODD IRQD are loaded into the Chip Operating Mode bits MA MB MC and MD of the Operating Mode Register OMR These bits determine the bootstrap operating mode Modes C D E and F use the HI08 host port to bootstrap the application code to the DSP The following table describes these modes Mode MODD MODC MODB MODA HI08 Bootstrap Description C 1 1 0 0 ISA DSP5630x mode D 1 1 0 1 HC11 non multiplexed bus mode E 1 1 1 0 8051 multiplexed bus mode F 1 1 1 1 MC68302 bus mode T
471. which such transfers are performed for FIR and IIR filters 1 For details on FIR and IIR filters refer to the Motorola application note entitled Implementing IIR FIR Filters with Motorola s DSP56000 DSP56001 APR7 D Motorola DSP56311 User s Manual 10 14 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EFCOP Programming EFCOP operation is determined by the control bits in the EFCOP Control Status Register FCSR described in Section 10 3 5 Further filtering operations are enabled via the appropriate bits in the FACR and FDCH registers After the FCSR is configured to the mode of choice enable the EFCOP by setting FCSR FEN To ensure proper EFCOP operation most FCSR bits must not be changed while the EFCOP is enabled Table 10 9 summarizes the EFCOP operating modes Table 10 9 EFCOP Operating Modes FCSR Bits Mode Description 6 5 4 3 2 1 0 FMLC FOM FUPD2 FADP2 FLT FEN EFCOP Disabled x x x x x 0 FIR Real single channel 0 00 0 0 0 1 FIR Real adaptive single channel 0 00 0 1 0 1 FIR Real coeff update single channel 0 00 1 0 0 1 FIR Real adaptive coeff update 0 00 1 1 0 1 single channel FIR Real multichannel 1 00 0 0 0 1 FIR Real adaptive multichannel 1 00 0 1 0 1 FIR Real coeff update multichannel 1 00 1 0 0 1 FIR Real adaptive coeff update 1 00 1 1 0 1 multichannel FIR Full Complex single chan
472. ww freescale com 10 4 Freescale Semiconductor Inc Architecture Overview m Filter Coefficient Memory FCM This 24 bit wide memory bank is mapped as Y memory and stores filter coefficients for EFCOP filter processing The FCM is written via the DSP56300 core and the EFCOP address generation logic generates its addressing The filter coefficients are read sequentially from the FCM into the MAC The FCM is accessible for writes only by the core The FCM is shared with the 10K lowest locations 0 2800 of the on chip internal Y memory Note The filter coefficients H n are stored in reverse order where H N 1 is stored at the lowest address of the FCM register as shown in Figure 10 2 Coefficient Memory Bank FCM Figure 10 2 Storage of Filter Coefficients The EFCOP connects to the shared memory in place of the DMA bus Simultaneous core and EFCOP accesses to the same memory module block 256 locations of shared memory are not permitted It is your responsibility to prevent such simultaneous accesses Figure 10 3 illustrates the memory shared between the core and the EFCOP X RAM Y RAM Data Coefficients X RAM Y RAM P RAM FDM FCM f A t A YDB i PDB XDB FDB CDB i Yo Y Y DDB E aa EFCOP pe GDB ea CORE Figure 10 3 EFCOP Memory Organization Motorola Enhanced Filter Coprocessor EFCOP
473. xceptions 8 8 Idle Line 8 8 Receive Data 8 8 Receive Data with Exception Status 8 8 Timer 8 8 Transmit Data 8 8 GPIO functionality 8 25 I O signals 8 3 initialization 8 6 operating mode Asynchronous 8 1 Synchronous 8 1 operating modes 8 1 Asynchronous 8 1 programming model 8 9 Receive Data 8 4 Receive Register 8 23 reset 8 4 state after reset 8 5 Serial Clock 8 4 Status Register 8 17 transmission priority preamble break and data 8 7 Transmit Data 8 4 Transmit Register 8 24 SCI GPIO 5 8 SCI Clock Control Register 8 7 SCI Clock Control Register SCCR 8 9 8 19 Clock Divider 8 21 Clock Out Divider 8 21 Receive Clock Mode Source 8 21 Transmit Clock Source 8 21 SCI Clock Control register SCCR Clock Prescaler 8 21 SCI Clock Control Register SCCR Bit Definitions 8 21 SCI Control Register 8 7 Index 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCI Control Register SCR 8 9 8 12 Idle Line Interrupt Enable 8 13 Receive with Exception Interrupt Enable 8 12 Receiver Wakeup Enable 8 15 SCI Clock Polarity 8 12 SCI Receive Interrupt Enable 8 13 SCI Shift Direction 8 16 SCI Transmit Interrupt Enable 8 13 Send Break 8 16 Timer Interrupt Enable 8 13 Timer Interrupt Rate 8 12 Transmitter Enable 8 14 Wakeup Mode Select 8 15 Word Select 8 16 SCI Control Register SCR Bit Definitions 8 12 SCI Data Registers 8 22 SCI Data Word Formats 8 10 SCI exceptions Receive Data 8 8
474. za ke e REP A hese p esea e Gea bese Red Rd 6 3 6 3 o au MMEFTPHII u E 6 4 6 4 Operation ici pr RERTECRELEepE RA GUAE hbRS Uer e REER E CAPE 6 6 6 4 1 Software Pole v cour E RAD HR E Od ee Ge FOE Eddie Ee x edidere eun 6 7 6 4 2 Core Interrupts and Host Commands 0 0c cece eee eee 6 7 6 4 3 Core DMA ACCESS 24 443 ebb caoeeehewidersedcavecsneeiGerthctandensd 6 9 6 4 4 Host Reques 6 ois oou cucu ties eae ep x Pho ware q Nar Gand ak eee cake 6 9 6 4 5 Endian Modes 44d ae erdan GR RESQUE EG RATS RE Ra c RE eda eg 6 11 6 5 Boot up Using the HIO8 Host Port 6 12 6 6 DSP Core Programming Model 0 0 cece eee een eens 6 13 6 6 1 Host Control Register HCR 424205 e0eein eRe ester Geceeee RPEREMA EE 6 14 6 6 2 Host Status Register HSR iilud uu e hera erwee gue een ey dA X REY EXE 6 15 6 6 3 Host Data Direction Register HDDR 0 0 0 0 cece eee IR 6 16 6 6 4 Host Data Register HDR caa dd2ces ear sep ERES PAESE XM EXPE RIPEPDOEEES 6 16 6 6 5 Host Base Address Register HBAR 0 0 eee 6 17 6 6 6 Host Port Control Register HPCBO Loss axe xU ERUCORRERPS AU MESE RP ES 6 17 6 6 7 Host Transmit Data Register HTX leseeeeeeeee eh 6 21 6 6 8 Host Receive Data Register HRX oleae Var tr XA ERPapcAR Sed Ere eee kee 6 22 6 6 9 DSP Side Registers After Keset c 2 222 4scceestavedeeeaeeseeseeeuedeenas 6 22 6 7 Host Programmer s Model 0 0 0 0 0c cece eee teens 6 23
475. zation Table 8 1 SCI Registers After Reset Continued Reset Type Register Bit Mnemonic Bit Number HW Reset SW Reset IR Reset ST Reset SRSH SRS 8 0 8 0 STSH STS 8 0 8 0 SRSH SCI receive shift register STSH SCI transmit shift register HW Hardware reset is caused by asserting the external RESET signal SW Software reset is caused by executing the RESET instruction IR Individual reset is caused by clearing PCRE bits 0 2 configured for GPIO ST Stop reset is caused by executing the STOP instruction 1 The bit is set during this reset 0 The bit is cleared during this reset The bit is not changed during this reset 8 4 SCI Initialization The SCI is initialized as follows 1 Ensure that the SCI is in its individual reset state PCRE 0 Use a hardware RESET signal or software RESET instruction 2 Program the SCI control registers 3 Configure at least one SCI signal as and SCI signal If interrupts are to be used the signals must be selected and global interrupts must be enabled and unmasked before the SCI can operate The order does not matter any one of these three requirements for interrupts can enable the SCI but the interrupts should be unmasked last that is I 1 0 bits in the Status Register SR should be changed last Synchronous applications usually require exact frequencies so the crystal frequency must

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