Arp 1601 Sequencer Service Manual
Contents
1. 3NOL 310HM MH3NNV2S HOLVH3N39 1541 dny szol gt A 078090 SVj wl 101 M gavos lOZLIZ ASSY 10786025 avi assy 9808 r 1601 SEQUENCER JACK BOARDS ASSEMBLY BOARD LAYOUT COMPONENT SIDE VIEW POWER SUPPLY LAYOUT BOARD NO 2904 003 MOUNTING ALTERNATES TRANSISTORS ONStsat 245454 MOUNTING ALTERNATE TRANSISTOR 64004 2N6179 21 00 P062 JILYWIH S 979 14415 HAMOd ig iei QUNPNL ENADO ARIA ISVS gm W KQ HUR Py 2232148 6 ses GD DIT SO WBE C3 focal god d JY yu YAYAN M SEVA 391619304 TERING u z O eus Qj WNUBAAD u3Mc4d Q awo d OL YNK WDA BOARO 1 REFERENCE CR1 2 20 23 24 4 19 94 5 Q1 2 3 9 11 27 Q6 7 8 10 29 36 74 5 Z18 12 26 29 34 35 z23 29 27 Z3 31 32 33 21 6 12 15 25 22 28 230 225 210 213 14 zg Z21 22 216 17 211 220 222 226 217 216 R19 26 206 207 R15 25 57 60 63 66 69 72 75 78 82 85 B8 91 96 97 100 103 C1 2 1 3 23 2 21 54 55 20 22 P23 27 EOARD 2 REFERENCE CR22 41 6 10 15 20 22 BOARD 3 REFERENCE 12 5 4 5 7 4 16 17 12 19 30 31 32 22 425 26 27 POWER SUFPLY REFERENCE CR1 4 91 5 64 5 92 3 21 85 11 4 eis Ti F1 ARP2. Controlled Pulse Width 10 to 100 less 5 msec Pinse Width Modulation Accepts to 10 volts Frequency Banga 0 2 Hz to 100 Hz FM input Sensitivity 2V OCT max Clock Output 14 V pulse wave Warm Up Drift QUANTIZER Rounds off voltages to nearest 1 12 V semitone Maximum Input Voltage A amp 10 V Maximum Quantized CV Output A amp 8 2 octaves 1 3 Function Description 2 2 T 1 La 1 1 Position Assignment Switches Supplies a 414 volt gate to one of three bused outputs Foot Switei Input Fear Pune Sup plizs 14 volt gate to the Foot Switch Out jack the front ganel Position Gste Sus Outputs 14 voti gate outputs which are usually c nnerted to ex ernal ermvetope wnerators Position 1 Output Supplies 18 volt gate on position 1 only to synchronize additions sequencers or synthesizers Clocked Gate Out the selection of particular pcxition gates Gate Bus 1 with control of the pulse width Clock Clock Out Supplies 14 voli clock puise which trigger external emveiape generators Quaintizes Outputs Provides con tral voltage in 1 12 volt incraments 0 to 2 vult ranga which controls the pitch of external oscillators The a
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4. Skip amp Reset Z11B is a high speed oscillator approx 5 microsec Whan 216A pin is a logic 1 2118 produces a high frequency pulse chain on pin 9 When 2162 pin 3 is at a logic 0 ground 211 stops oscillating With slide switch 527 in the Random position 210 pin 10 will enable turn on the high speed oscillator 211 through 216 2118 will then provide a pulse chain to Mask circuit When pulsed by the clock cscilator the one shot will momentarily turn off the high speed oscillator through Z10C pin 12 amp 13 to allow the latch in the Counter Latch circuit to memorize a random position Dur ng this mode 27B ganerates random voltage lavels ta the fre quency of 2118 to insure a random sampling of positions With 521 in the Sequential mode 210 will not affect the frequency of the high speed oscillator When 22 is in the skip Position pin 8 of 29 is at logic 0 When the J point is also at logic 0 Z9C pin 10 then turns am the high speed oscillator which quickly advance the sequencer to the next position via Z160 In the reset position the gate signal on the J point is supplied through 22 to Z9D When tha J point is at logic 0 29D supplies a logic 1 which resets the cunter to position 1 via 2168 External reset gates may be applied to 027 and by depressing the reset push button 523 3 5 Mask Circuit Z15A pin is logic 1 when the sequencer is n the sequential mode which allows the la
5. PART NUMBER 1200301 5704801 7500801 1502901 1203001 1400501 5 01801 5601901 149430 1404201 1420691 1404401 1404501 1400901 1404601 1404701 1404801 1404901 1405101 1405201 1405301 5704101 1000904 1000956 1006935 5709703 5730702 1150612 1933001 1922401 1950701 1930601 2152901 2122801 ARP PART NUMBER 5704501 2101201 2503301 ARP PART NUMGER 2101201 2101803 ARP PART NUMBER 1200401 1303401 1309901 1303001 1401301 1009915 1103612 1101701 5701101 1700402 PARTS LIST ARP MFG NUMBER 148 243904 2N3906 CA3085 CD4001AE CD4007AE CD4011AE CDAO13AE CD4016A CD4024AE CO4025AE 04028 CD4C42AE CD4O51A C D407 BE CD4520BE MC14528CP 02018106 uU201R25s2B U201R1G4B G 0 010 G 20 0 51 01 091 481 0006 01 481 0005 01 461 O064 09 64 1067 10 18 2031 ARP MFG NUMBER ARP MFG NUMBER 1424 02 52 3062 NUMBER 184448 286179 2N3304 2N3906 U6A 723393C 820181948 G 0 010 G 20 0 B41010 250 50 C2804 008 MDV 1 8 DESCRIPTION DIODE SIGNAL DIODE LIGHT EMITTING TSTR ASSY NPN PNP TSTR GP TSTR PNP GP IC TSTR ARRAY C AMPL DUAL 1C OP AMPL SELECTED IC GATE 4x21 NOR IC MOS PAIR PLUS INVERTER IC GATE 4X1 NAND 1C DUAL D FF SET RESET IC QUAD BILATERAL SWITCH IC BINARY COUNTER 7 BIT GATE 3X31 NO R 1 BCD TO DECIMAL DECODER 1 QUAD CLOCKED D LATCH IC SINGLE CHANNE
6. se quential voltage generator A voltege ievel slider is Provided far each of the 16 steps to adjust the voit output fram to 19 volts The sequencer may be used 2 mode so that cutputs 1 through B bank and 2 through 16 bank B sequence in parailel The outputs of banks A and are prewired to a voltage quantizer which effectively rounds off the sequencsr s voltage to the nearest whole twelfth of a volt This allows precise tuning since all ARP products are tuned to a 1 volt par actave stand ard 1 12 volt per semitone A low frequency voltage controlled clock governs the stepping spsed of the sequancer and can be started stopped gated or speeded up either manually or externally Position gates provide a constant voltage output 10 for as long as the sequencer 5 on Selected position The position gate outputs are bused to one of the position gate outputs Gate 1 2 or 3 12 Specifications SEQUENCER Number of positions Maximum funquantized control voltsge output Maximum Gets output voltage 16 X 1 Mode Channels and are common 8 X 2 Mode Channels A and B are separate FIG 1 1 CONNECTIONS TO SYNTHESIZER Use theta controls tp tune each position ncer E H EHECEEHEHU HOHE a 9 9 5 0 9 9 s9 Step Reset Start Stop and Start Stag jack inputs Accepts 3 V to 10 V Gate CLOCK
7. the sequencer is in the random mode the Randomizer circuit advances the counter at an extremely high frequency For each cycle of the low frequency clock a position number on the NNN SEQ RAND SWITCH IN SEQUENTIAL POSTION FIG 2 1 SIGNAL FLOW output of the counter is memorized and held until the next clock pulse Since the counter is being advanced so fast the position numbers which are memorized will be random 2 2 Quantizer Vottages which are to be quantized to the nearest whole twelfth of a volt are applied the A or B8 input of the quantizer Ona quantizer circuit is multiplexed by switching between one of the two inputs and to provide two independent quan tized control voltage outputs The voltages are quantized and stored extremely quickly sif that two different voltages are quantized one at a time faster than cen be detected by the As in a standard keyboard a resistor chain of equal value make up a voltage divider to generate a voltage reference The voltages produced by this reference CV generator are volts 1 12V 2 12V 3 12V 2V 2 octave range high frequency oscillator steps a counter which enables the CV generator voltages to be scanned one at a time 0 volts 10 2 volts The input vottage which is to be quantized is compared to the reference CV on the scanner output if the scanner output is lower than the input voltage the counter edvances
8. 16 ATOR 2 Put all other sliders fully DOWN ov 3 Start the Sequencer 1 Put the CLOCK FREQ slider at X 2 Pur all other sliders fully DOWN 3 Start the Sequencer ONE SHOT 1 Put the CLOCK FREQ slider at X 2 Put ali other sliders fully DOWN 3 Start the Sequencer MASK t Put the CLOCK FREO slider at ADVANCE 2 Put all other sliders fully DOWN 3 Start the Sequercer 1 Put tha CLOCK FREQ slider ac mses a 0107 15 2 Put all other sliders fully DOWN sy 3 Start the Sequencer ov TP 10 ADVANCE 1 Put the CLOCK FREQ slidar at 8 usec tyoicat 2 Put all other sliders fully DOWN 3 Start tha Sequencer Ths following test points ali use the same panel settings QUANTIZER za T gt TP 13 TP 14 3 Ix 3 3 21 3 8 FUNCTION 2 CLOCK 31 c LOCK SCANNER SCANNER SCANNER SCANNEF OUTPUT COMPAR ATOR SAMPLE RESET are 15 V pulse waves Put the SEO RAND switch in the SEQUENTIAL position Put the GATE TRIG switch in tha GATE position Put the mode switch in the B X 2 position Depress the RESET button position 1 LED should be li Put the POSITION 1 slider about 1 3 up Put the POSITION 9 slider about 2 3 up SPECIFICATIONS e 120 usec parlod typical 6 Hz 1 I 2 0 i A CHAN BdM i s CHAN A CHAN a
9. ARE SEQUENCER MODEL 1601 SERVICE MANUAL ARP INSTRUMENTS INC 320 Needham Street Newton MA 02164 617 965 9700 Document Number 9001901 September 1976 ARP INSTRUMENTS INC THE INFORMATION CONTAINED HEREIN IS CONFIDENTIAL AND PROPRIETARY TO ARP NSTRUMENTS INC IT JS DISCLOSED TO YOU SOLELY FOR PURPOSES OF INSTRUCTION AS TO OPERATION OF THE EQUIPMENT AND AS APPROPRIATE IT IS NOT BE USED 8Y YOU FDA ANY OTHER PURPOSE NOR 15 IT TO BE DISCLOSED TO OTHERS WITHOUT THE EXPRESS PERMISSION OF ARP INSTRUMENTS INC G ARP SEQUENCER MODEL 1601 SERVICE MANUAL TABLE OF CONTENTS 1 INTRODUCTION 1 1 Product Description 1 2 Specifications 1 3 Function Description 2 THEORY OF OPERATION 2 1 Sequencer 22 Osantizer 3 CIRCUIT DESCRIPTIONS SEQUENCER 31 3 2 3 3 3 4 Randomizer Skip amp Reset 35 Mask Circuit 3 6 3 7 38 Counter Latch 9 3 10 Gate Output Processing QUANTIZER 3 11 Current Source amp Sevnitone Shift 3 12 CV Generator amp Scanner 3 13 Counter 3 14 Comparator 3 15 Sample Control 3 16 External CV Input SEQUENCER TEST POINTS CALIBRATIONS ASSEMBLY DISASSEMBLY BLOCK DIAGRAM GENERAL INFORMATION COSMOS integrated Circuits 13 SCHEMATICS amp LAYOUTS m 14 15 16 17 18 19 10 PARTS LIST SECTION 1 INTRODUCTION T1 Product Description The AHP Sequencer model 1601 is a 16 step
10. B CHAN B CV IN EXAMPLE FROM SEQUENCER A CV IN EXAMPLE as FROM SEQUENCER TIR 60 usec 130 usec typical 70 usec typice e j 5 usac typical NOTE Te t paint4 11 17 aid 19 20 SECTIONS CALIBRATIONS 5 1 Sequencer amp Quantizar R19 FREQ CAL 1 Put the CLOCK FREQUENCY SLIDER fully UP 2 Monitor the CLOCK OUTPUT with a frequency counter or oscilloscope 3 Put all other sliders fully DOWN 4 Adjust trimmer R19 for 10 msac period waveform 1060Hz R 26 PULSE WIOTH 1 Put ali GATE ASSIGNMENT switches fully UP Gate Bus 1 position 2 Monitor thee CLOCKEO GATE 1 OUTPUT with an oscilloscope 3 Put the GATE TRIG switch in the TRIGGER mode 4 Depress tha START STC button to START the sequencer 5 Put the CLOCK FREQUENCY slicer fully UP 6 Put the CLOCK FM slider fully DOWN 7 Put the CLOCK PULSE WIDTH slider fully UP 8 Turn trimmer R26 fully CLOCKWISE 9 SLOWLY tura trimmer R26 COUNTER CLOCKWISE until waveform disappears constant 14 volts TURN NO FURTHER R206 amp AOFFSET amp 1 Connect 2 patch cord from INPUT A jack to INPUT B jack isolates R207 OFFSET Guantizer inputs ADJUST 2 Adjust trimmer 9206 for volts 005 V on QUANTIZED A OUTPUT 3 Adjust trimmer R207 for volts 005 V on QUANTIZED OUTPUT R226 amp QUANTIZER 1 Put all sliders on the sequencar fully DOWN R222 CV 2 Put the TRIG GATE switch in the GATE made 3 Put
11. Bus 3 Clacked Gate 1 Clock Output and Position 1 Output The Gate Bus 1 2 and 3 outputs are driven from the 3 position slide switches in the Decoder circuit Z15C and 215D are a flip flop which supplies the Clocked Gate 1 Output and turns on the clock indicator CR22 The position 1 output obtains signal from Position 1 011 base in the Decoder circuit so that more than ons sequencer can be synchronized QUANTIZER 3 11 Current Source amp Semitone Shift 629 supplies constant current through 13 equal resistors 100ohm located in resistor pack 220 The voltage drop across each resistor is 2 12 of a volt two semitones or one whole tone Q36 supplias an offset voltage to 3 of 229A to shift or raise the output af the current source and there fore pins 1 through 14 of 220 up 1 12 of 2 volt 3 12 CV Generator amp Scanner Z21 and 222 sre digitally controlled analog switches which are connected to the CV generator autputs 1220 The three binary inputs B and C select one of eight switches to be turned and connect an input pins 13 14 15 12 1 5 2 or 4 to the output pin 3 All of the switches are off when a logic 1 is on pin 6 The A B and inputs of 221 driyan by 225 3 13 COUNTER 225 generates a binary number which counts from 00000 to 11111 The first bit inhibits either 221 or 222 so that only voitage from 220 is ever on at the s
12. L MLTPLX IC GATE 4X2F OR I DUAL BINARY JP COUNTER DUAL MONOSTABLE MULTIVIS 10 RESISTOR PACK POT ROTARY V 30 POT ROTARY 2 5K 30 POT ROTARY 100K ww 30 POT SLIDE LIN 100K 2 3 30 POT SLIDE ALD 100K 1 SW 20 CAP TANT 1OUF 35V 20 SWITCH MOMENTAAY SP SWITCH SLIDE DPOT SWITCH SLIDE 4PDT SWITCH SLIDE OPTT CONN FLUG WAPER amp PIN CONN RECEPTACLE 3 PIN DESCRIPTION DICE JACK TINO CLIP MOUNTING LEO JESCAIPTION JACK TIMI D CONN BOOY PLUG 6 PIN DESCRIPTION RECTIFIER SILICON 75V 200MA NPN PWR TSTR SILON NPN SILICON PNP IC VOLTAGE REGULATOR AOTARY LIN SW 10 100K CAF TANT 38V S0 20 1047 CAP ELECT 50V 50 16 250UF TRANSFORMER FUSE PIGTAIL 1 95 Z50V
13. LY DISASSEMBLY Set R5 15 volts first 2 Put the digital voltmetzr s ground lead on the power supply s 15 voft output and put the meter s plus lead on che power supply s ground output 3 Adjust R11 for exactly 15 00 volts reversed polarity 1 To Prevent shock when trouble shooting unplug tha sequencer and mount tha power supply on the outside rear panel see above ifhxstration 2 To remove the main printed circuit board remove 11 bolts ifustreted above remove all slider Knobs on the front panel and gently push on the shafts of tha slidars until the board pops loose 3 To remove the lower jeck board assembly remove the jack nuts on tha lower frant panel Then pull the bottom of the power switch out s that the jack beard ciears the power switch see i fusiration to right WvHu5vig 35018 HAONINDO3S LOSL z ane 1 333 bus www 0M MM M7 s ino pnt 5 5 tay 1903 an ang AD v 36 Y uper 9 WASIN induit v NI AD Anal A gt A H3LMMS 1004 Csansino oi 0300730 VVNIB 83 w3ZINCGNTH 33390230 gt x m nns ss I3HNVH2 shane 232110916 BLNO 379975 70 1 546 34v9 586 34 SNI SS IJOY 31 9 LNd LAO 109110 5 3 3114 3NQ11W3S 3340 2 u318602 O v inan
14. ame time The next three bits pins 6 9 and 11 of 220 turn on channels 13 14 15 12 1 etc ora at a time sequentially The remaining bit LSB on the Counter output pin 12 is supplied to the Current Source to shift the resistor chain level up 1 12 af walt ta obtan two voltage levels per resistor in 220 3 14 Comparator The scanner output 2298 pin 7 is supplied to the inverting input of the Comparator 223 An external control voltage which is to be quantized is supplied to the noninverting input of ts Compara tor via the Input Channel Sefector Initially the Comparator output is logic 1 15 volts which permits the counter to be advanced by the Clock through 2240 As the Counter advances the voltage on pin 2 of 223 steps 1 12 volt incre ments until it exceeds tha voltage level on pin 3 of 223 The output of the Comparator then changes to logic 0 which immediately stops the Counter The voltage on the Scanner output now constant is tha nearest 1 12 of a volt level to the input control volt age therefore it is supplied to the Channel Memory vis Z30 to be stored 3 15 Sample Control 230 is enabled when the Sample Control provides a logic 1 to the clock input of 728 228 then turns on ane of the transmission gates either channel B for a time period of half a clock cycle After the quant zed control voltage fram 2200 has been supplied to one of the memory circuits Z27C resats bot the Sampl
15. e Latch circuit tc one of 16 positions When S4B is in the 16 X 1 made Q11 through 26 will tum on one at a time sequentially 1 through 15 In the 8 X 2 mode 213 and 214 decode in parallel position 1 8 and 9 16 In the random mode the counter adyances at the rate of the High Oscillator Z11B schematic 1 but in this mode Z8 holds the cede which is supplied to the decoders constant Tha strobe input of the ZB allows a random binary numher to be memorized on each clock pulse which is supplied to the decoder Q11 and 026 tumed on one a time and supply voltages to one of the three gate bus lines through the three positian gate switches At the same time the LED is lit indicating which positian is on The three position slide switches provide the path to ground for the LEDs The voltages fram the deccder chips are also supplied to 100K sliders R57 through R103 to provide a variable voltage level 0 to 10 for each position Voltages from the A bank sliders and the B bank sliders are summed in the output amplifier circuit Z19A and ZiBA When the sequencer is in the 16 X T position the output of the A and channels are summed together so that the cutputs of Z19B and 218B will be the same The Sequencer output voltages supplied Sy the output amplifiers are routed to the quantizer schematic 3 3 10 Gate Output Processing Gate Output Processing circuit provides 6 outputs Gate Bus 1 Gate Bus 2 Gate
16. e Contrat and the Counter Addi tionally the outputs of 228 reverse state to switch from one channel to the other A to B for exampla The Quantizer is naw ready to quantize the voltage waiting an the other input 3 16 Extemal CV Input The External CV input allows 3 control voltage from another synthesizer to be summed with the output of the two Quarrtizer circuits The keyboard CV of other instruments can be added to the sequencer s voltage to change the key in which the saquencer plays simply by playing an external keyboard The test points on the following two pages illustrate the oparstion of the circuits in the sequencer relation te 00 another SECTION 4 SEQUENCER TEST POINTS 2 FREQ j 1 Put the SEQ RAND switch in 1 the RANDOM mode w ais 2 Put the SEQ RANO switch in i the SEQUENTIAL mode G volts constant CLOCK 1 Put the TRIG GATE switch in 157 ON OFF the GATE position Depress the Start Siop button held town 4 START STOP button 0v 2 Put the TRIG GATE switch in Alternates between 15 V and 0 V when START STOP the TRIGGER position Depress is depressed the START STOP button ONE SHOT 1 Put the CLOCK FREQ slider at X 2 Put all other sliders fully DOWN 3 Start the Sequancer CLOCK 1 Put the CLOCK FREQ slider at X SAWTOOTH 2 Put all other slicers fully DOWN 3 Start the Sequencer COMPAR 1 Put the CLOCK FREQ slider at X 29 ty gical
17. he ore shot is supplied to _ 1 the Clock Oscilator to reset the sawtooth 2 the Reset circuit to lengthen the external reset pulsa if applied when the E point is at a logic 1 and 3 the Randomizer ckcoit momentarily disable the high frequency oscifiator random mode only 3 3 Clock Osciiltartor Theee circuits comprise the Clock Oscillator the Voltage Controlled Oscillator Sawtooth to Pulse Converier and Comparator T Sawtooth Oscillator Voltages from the clock FM input jack and the clock rate slider are summed on the basa of 04 04 and QS a linear voltage to exponential current converter Capacitor C7 is initially charged to 16 volts and discharges toward ground through 05 23 and Q fallow the wattage level on C7 and su3ply it to the comaarator and the sawtooth to pulse converter The output of the comparator pin 13 8 will switch to 15 volts logic 1 when the sawtooth voltage falls below 7 5 volts The comparator output is supplied to the ona shot which reset capacitor C7 to 15 volts Sawtooth To Pulse Converter Voltages from the Pulse Width Modulation jack and the Pulse Width slider are applied 24 and Z4B to set the clock pulse width The collector of Q8 will be a pulse wave with a pulse width fram 20 to 100 depending on the position of the pulse width slicer The pulse output of the cloc oscillator i5 routed to the Gate Output Processing circuit schematic 21 34 Randomizer
18. nd 8 out puss siw in the 16 X 1 moda bu separate in the 8 X 2 mode CV Allnves externa control veltagas fram a keyboard for example to summed with tha sequenzer s voltage to shift the key in which the sequencer plays Quantizer inputs Allows voltages to be guantized rounded to neamst 1 12 Prepaschad to the sequencer out puts Sequancar Cutputs Proekos O 10 10 volt angiog control voltage Common convenience jacks SERR 23 25 Pulse Width Varies the pulse width of the cock Clovk Allows external control veit ag s tg increase the speed of the clock prawired to Gata Bus 1 Gock Freguaeccy Marssally varies the clock rate from 2 2 1 approx 100 Hz StartStop Adtemately starts and stops the saquercar Trig Gate Trigger moce slows tha sequenrer 10 be triggered In tbe Gate mode the sequencer is on while the stert button is held Extamatly stivts the sequencer ExternaNy stops the 9pqoencer Step Advances the sequencer to the next postion Amat Rewts tha sequencer to position 1 saquential mode only StipMeset Allows particular positions gate bus 3 to althar skip past retet on particular positions Sequential Randoee Albows clock to edvance to cach successive pocition or advance a random poitian Mode Switch Stapi the cequencer 16 timas or steps tanks A and B 8 times in p
19. o ovo wet v AWOMS 04 Inr d BERTAN CMOS INTEGRATED CIRCUITS CD4001AE QUAD 2 INPUT NOR CD4007AE mb Tripla laverinrs y gt OLEK ATA A DUAL COMPLEMENTARY PAIR PLUS INVERTER Terminal 16 Terminal No Wes CD40114E QUAD 2 INPUT WAND CD4913AE FLIP FLOP CD4016AE QUAD BILATERAL SWITCH Onaga GA Oa O CD4024AE 7 STAGE BINARY COUNTER CD4025AE TRIPLE 3 INPUT NOR CD4028BAE BINARY TO OCTAL DECODER TABLE 1 TRUTH TABLE q 9o 059 8 9 G O6O484808 eo gw 04061 MULTIPLEXER SIGNAL GATE CD4071BE QUAD 2 INPUT OR CD4520BE DUAL BINARY UP COUNTER MC14528CP DUAL MONOSTABLE AUL TIVIERATOR Rx 003 Cy ane oseoonante vpo Pa tt Vag FS 40 L 9LVIW3HOS 1091 w9 1 80 23NMO2 BOVLIOA Aldons O35 NOLNSANOO Old PRRI 1630 5 om 4 i08 POS UHL vu O6 NZ Suv 920 nar HD L sovevions MI SINIYA WOLOWdWw gt Ti SO BSW INATA WHOLIS TW CAA93465 SIMUL SSN s 3017711250 12015 1 210N SIVNINIA OMUOGOT Smal 3aSva sooo L so z 222 92 4 A eo eztets ozs nwu ss a TER 9 5 v UNDYDD SVW 13834 abis H321NOQNVH 38402 WOR lt
20. oallet 24 LED Light Emitting Diodes Indicates which pasitian op Positiun Turing Sliders Tunes individual positions adjusts CV level SECTION 2 THEORY OF OPERATION 2 1 Sequencer The heart of tha sequencer is the Counter Latch circuit which produces a four bit binary number When initially reset the output of the counter is 0000 Position 1 code or zero Each time the counter receives a pulse from the Mask circuit the counter advances to tha next binary number 0001 0010 0011 0100 1111 The highest binary number 1111 corresponds to position 16 This coda amp supplied to the Decoder circuit which decodes the binary number to one of 16 outputs For example when the cade 0000 is present on the output of tha counter the decoder will turn on the position 1 output only when tha code 0001 is present on the output of the counter the decoder will turn on anly the position 2 output etc When in the B X 2 mode a three bit code is supplied from the counter instead of four Positions 1 through B and 9 through 16 in the Decoder circuit simultaneously decode so that banx A 1 8 and B 9 16 sequence in parallel The Voltage Corirolled Low Frequency Clock determines when the counter is advanced to the next position by pulsing one shot circuit The one shot in turn supplies a pulse to the Mask circuit which advances the counter and disables masks the gate outputs during the count advance When
21. tch Z8 in the Counter Latch circuit to transmit data con tinuously When of 215A is logic 0 random mode only Z8 in the Counter Latch circuit holds or stores the datz an the counter output The one shot pulsa will causa tie Q and bar out puts of 22 to momentarily reversa statu The output of the high speed oscillatac Z11B and the Q bar output of Z2A are then combined on Z16C which advances the counter in the Counter Lateh circuit A mask pulse is generated by combining the one shot pulse 4 msec duration and the pulse from 22 8 microsac duration on the output of Z1BB pin 4 to turn off ail the gate outputs during the time the coumer is advanced from one position to the next 3 8 Step When gate signals are applied to the step jac amp or from the step push button Z6A pin 3 provides a pulse to the One Shot circuit and the Gate Output Processing circuit 3 7 Foot Switch Jack The foot switch jack on the front panel provides a 10 volts gate for as long as the foot switch is held and can be patched to any of the input jacks on the front panel 8 Counter Latch 27 is a divide by 16 counter providing a 4 bit code to Z8 28 is a latch circuit but normally transmits data to the Decoder circuit unaffected ZOB and 29 are connected the and Q bar outputs of ZB to enable 213 and 214 in the Decoder circuit one at a time sequentiaily 3 9 Decoder Z13 and 214 decode the binary number from th
22. the sequencer mode switch the 16 X 1 POSITION 4 Put the SEQ RAND switch in th SEQUENTIAL position 5 Depress the RESET button position 1 LED should be litl 6 Put the POSITION 1 SLIDER fully UP 7 Adjust trimmer R266 for 2 00 votes on the QUANTIZED OUTPUT jack 8 Adjust trirmmer R222 for 2 00 volts the QUANTIZED OUTPUT B Jack MOD ADJUST 1 Put all the sliders on the sequencer fully DOWN B MOD ADJUST 2 Put the GATE TRIG switch in the GATE made 3 Put the mode switch im the 18 X t POSITION 4 Put the SEQ RAND switch in the SEQUENTIAL position 5 Depress the RESET button position 1 LED should be diti 6 Connect a patch cord from INPUT A jack te INPUT B jack isolates quantizer inputs 7 Monitor the A SEQUENCER OUTPUT with DVM 8 Raise the FOSITION 1 SLIDER to 9 Measure ard racord the EXACT VOLTAGE leyal on the A sequencer autput sould be near 5 voits 10 Connect a patch cord from the A SEQUENCER OUTPUT jack to the CV iN jack a 11 Monitor tha QUANTIZER OUTPUT with a DVM 12 Adjust trimmer R217 for EXACTLY the seme voltage as measured in step 9 unity gain 13 Monitor the QUANTIZED OUTPUT 8 with a DVM 14 Adjust trimmer R218 for EXACTLY the same voltage as maasured in step 9 unity gain 6 2 Powar Supply 1 Monitor the power sugply s 15 volt output with a digital voltmeter R5 5 VOLT SET amp 2 Adjust R5 for exactly 15 00 volts SECTION 6 ASSEMB
23. until the scanner voltage is just higher than the input voltage The counter is then stopped by the Comparator circuit and the voltage on the output of the scanner is memorized The counter is then reset ta zero so that the voltage other input may be quantized next 9 1611 121314 1516 POSITION OUTPUTS ORIVES LEDS amp CY SLIDERS a e POSITIONS D 10 17 12 13 14 45 15 Clack Clocked Gate t Pos Bus 3 i FIG 22 SEQUENCER OUTPUTS SECTION 3 CIRCUIT DESCRIPTIONS 3 1 Clock Ou Oft Gate signals applied to the start jack set the Q output of Z2B to logi 1 15 volts and Q bar to logic 0 0 volts Gate signals applied to the stop jack set the Q output of Z2B to logic 0 and tha Q bar to logic 1 Each time a gate signal is applied to the start stop jack or when the start stop bution is depressed the Q output of ZZB assumes the logic level of the O bar output so that the O and Q bar outputs reverse state When tha Gate Trigger switch S2 is in the gate position the output will assume a logic 1 state for as long as gate ki present on the start stop jack Summary For a clock on state the Q output of Z2B point will be a logic 1 For a clock off state the Q output is a logic 0 3 2 One Shot 4 millisecond pulse occurs ou the output of Z11A when pulsed on the A input pin 5 The pulse on output of t
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