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88F5182 Open Source Community Programmers' User Guide

1. 356 Offset SRO 0x60A04 SR1 0x60A0C SR2 0x60A14 SR3 0x60A1C SR4 0x60A24 SR5 0x60A2C SR6 0x60A34 SR7 0x60A3C High Address Remap x Reglister iicet ise teet Rien tede reads Mea Da pera tbe Poo da SE Segen in 356 Offset Register 0 Ox60A60 Register 1 0x60A64 Register 2 0x60A68 Register 3 Ox60A6C Base Address Enable Register trier Een te Fee Y ee ee cete uae eoe ERE ERR Ed 357 Offset Ox60A80 Channelx Access Protect Heiser Ave 357 Offset Channel 0 0x60A70 Channel 1 0x60A74 Channel 2 0x60A78 Channel 3 0x60A7C Channel Control Eow Reglister 2 rere tre teer terere sas Fe ete ket Mera Lnd 358 Offset Channel 0 0x60840 Channel 1 0x60844 Channel 2 0x60848 Channel 3 0x6084C Channel Control High Register neris rte etre eterne aite ba tone these Fir da eain Rada 360 Offset Channel 0 0x60880 Channel 1 0x60884 Channel 2 0x60888 Channel 3 0x6088C interrupt Cause Register nna eene Loire Fe ee EXIRET RE Le EUER e SERA KE Elea eds 360 Offset OxX608CO Interrupt EI dist 361 Offset 0x608C4 Error Address Heglster itt rct t err t ere t e b e pe ebd eeu tgo eu 362 Offset 0x608C8 Iisdem 363 Offset Ox608CC MOR Engine Ee EC 364 XOR Engine Channel Arbiter XECHAR eese nennen nennen enne etree trennen 366 Offset 0x60900 XOR Engine 0 1
2. Table 55 CPU Configuration Register Offset 0x20100 Bits Field Type Description InitVal 0 EndPointlF RW When the 88F5182 functions as Endpoint this bit defines the interface con Sample nected to host at reset The default value of this bit is 0 when PCI Expresso functions as Endpoint The default value of this bit is 1 when PCI ExpressO functions as Root Com plex 0 PCI Express Host is connected to PCI Express interface 1 PCI Host is connected to PCI interface 1 VeclnitLoc RW Determines the reset location of the boot starting address 0x1 0 0x00000000 Boot starting address is 0x00000000 1 OxFFFF0000 Boot starting address is OxFFFFOOOO 2 AHBErrorProp RW AHB Error propogation 0x1 0 Error not propagated Error indications are not propagated to AHB bus The transactions are completed normally 1 Error propagated Error indications are propagated to AHB bus 3 Endianlnit RW Endian Initialization Sample Determines the endianess of the 88F5182 CPU core operation after reset at reset This bit defines the initial value of bit 7 lt B gt of the Control Register R1 value of 0 Little Endian Little Endian mode DEV D 1 Big Endian Big Endian mode 17 4 Reserved RSVD Reserved 0x0 5 MMU Disabled RW MMU Disabled 0x0 When set to 1 this bit disables the MMU and activates the MPU instead 22 6 Reserved RSVD Reserved 0x0 23 PexLinkdownR RW PCI Express Link Down Reset of CPU esetCpu 0x0 0 P
3. ssseee 330 Offset Ox9DE04 Table 486 Security Accelerator Descriptor Pointer Session 1 Register 0 0 0 0 cece cece eee e eee eeeeeteeeseeeteeeeeseeeeaees 330 Offset 0x9DE14 Table 487 Security Accelerator Configuration Heiser 331 Offset Ox9DE08 Table 488 Security Accelerator Status Register eee eee eee eeee eee ceeeceae sess sae seaeseaeseaeseaeseeeseeesaessaeseaeseaeseaeeeaees 331 Offset Ox9DE0C Table 489 Cryptographic Engines and Security Accelerator Interrupt Cause Register sssessssssss 332 Offset OXODE20 Table 490 Cryptographic Engines and Security Accelerator Interrupt Mask Register cccceseeeeeeeeeeeeeteeeeeeeees 334 Offset OXODE24 A 12 Two Wire Serial Interface TWSI Registers ecce eneneennn 335 Table 492 TWSI Slave Addi6ss rrt ean cene ciet de ee ash e bere det ed v cao eiia 335 Offset 0x11000 Table 493 TWSI Extended Slave Address eese ennt eene rentre ener 335 Offset 0x11010 ebe Er M RN S RET 336 Offset 0x11004 IUe Mesum 336 Offset 0x11008 Walle 496 TWSIStAtUs IP 338 Offset 0x1100C EcL UCTAMBMRMURIEIUDRILUR RP 339 Offset 0x1100C Table 498 TWSISORIROS Cts EI 339 Offset 0
4. Table 50 Window6 Control Register Continued Offset 0x20060 Bits Field Type Description InitVal 1 WinWrProt RW Window6 Write Protection 0x0 When this bit is set to 1 the window is write protected and a write transac tion to this window responds to the Marvell processor core with an indica tion 0 Not protected Not write protected 1 Protected Write protected 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x1 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface 0x1B See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size 0x07FF See the Window0 Control Register Table 34 p 91 Table 51 Window6 Base Register Offset 0x20064 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxF000 See the Window0 Base Register Table 52 Window Control Register Offset 0x20070 Bits Field Type Description InitVal 0 win en RW Window7 Enable 0x1 See the Window0 Control Register Table 34 p 91 1 WinWrProt RW Window7 Write Protection 0x0 When this bit is set to 1 the window is write protected and a write transac tion to this window responds to the Marvell processor core with an error indication 0 Not protected Not write protected 1 Protected Write protected 3 2 Reserved RSVD Reserved 0x0
5. Offset 0x04 Bits Field Type Description InitVal 5 VGA RO VGA Palette Snoops 0x0 Not supported Read only 0 6 PErrEn RW Controls the 88F5182 s ability to respond to parity errors on the PCI 0x0 If this bit is disable the 88F5182 ignores any Parity Errors 0 Disable 1 Enable NOTE The 88F5182 asserts PCI PERRn only when detects data parity error 7 AddrStep RW Address Stepping Enable 0x0 The 88F5182 PCI master performs address stepping only on configuration accesses NOTE Read only from the PCI 8 SErrEn RW Controls the 88F5182 s ability to assert the PCI SERRn pin 0x0 0 Disable 1 Enable 9 FastBTBEn RW Controls the 88F5182 s ability to generate fast back to back 0x0 transactions 0 Disable 1 Enable 19 10 Reserved RO Read only 0x0 20 CapList RW Capability List Support 0x1 Indicates that the 88F5182 configuration header includes capability list NOTE Read only from the PCI 21 66MHzEn RW 66 MHz Capable 0x1 Indicates that the 88F5182 PCI interface is capable of running at 66 MHz NOTE Read only from PCI 22 Reserved RES Read only 0x0 23 TarFastBB RW Indicates that the 88F5182 is capable of accepting fast back to back 0x1 transactions on the PCI bus NOTE Read only from the PCI 24 DataPerr RWC Set by the 88F5182 Master when detects or generates Perr 0x0 Clear only by writing 1 26 25 DevSelTim RW Indicates the 88F5182 s DEVSEL timing medium 0x1 NOTE Read only from the PCI 27 SlaveTabort
6. Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x0 Table 198 Base Address Registers Enable Offset 0x30C3C Bits Field Type Description InitVal 0 CSOEn RW CSn 0 BAR Enable 0x0 0 Enable 1 Disable 1 CS1En RW CSn 1 BAR Enable 0x0 0 Enable 1 Disable 2 CS2En RW CSn 2 BAR Enable 0x0 0 Enable 1 Disable 3 CS3En RW CSn 3 BAR Enable 0x0 0 Enable 1 Disable 4 DevCSOEn RW DevCSn 0 BAR Enable 0x1 0 Enable 1 Disable 5 DevCS1En RW DevCSn 1 BAR Enable 0x1 0 Enable 1 Disable Doc No MV S400130 00 Rev 0 5 Page 175 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 198 Base Address Registers Enable Continued Offset 0x30C3C Bits Field Type Description InitVal 6 DevCS2En RW DevCSn 2 BAR Enable 0x0 0 Enable 1 Disable 7 Reserved RW Must be 1 0x1 8 BootCSEn RW BootCSn BAR Enable 0x0 0 Enable 1 Disable 9 IntMemEn RW Memory Mapped Internal Registers BAR Enable 0x0 0 Enable 1 Disable 10 IntlOEn RW UO Mapped Internal Registers BAR Enable 0x1 0 Enable 1 Disable NOTE The 88F5182 prevents disabling both memory mapped and I O mapped BARs bits 9 and 10 cannot simultaneously be set to 1 11 P2PMemOEn RW P2P Mem BAR Enable 0x1 0 Enable 1 Disable 12 Reserved RW
7. 88F5182 marveL Open Source Community Programmer s User Guide Table 388 SDMA Configuration SDC Offset 0x7241C Bits Field Type Description InitVal 0 RIFB RW Receive Interrupt on Frame Boundaries 0x0 When set the SDMA Rx generates interrupts only on frame boundaries i e after writing the frame status to the descriptor See also the lt IPGIntRx gt field description bits 21 8 for further masking 3 1 RxBSZ RW Rx Burst Size 0x4 Sets the maximum burst size for Rx SDMA transactions 000 Burst is limited to 1 64 bit words 001 Burst is limited to 2 64 bit words 010 Burst is limited to 4 64 bit words 011 Burst is limited to 8 64 bit words 100 Burst is limited to 16 64 bit words NOTE This field effects only data transfers Descriptor fetch is done always with 4LW burst size Should not be changed other values degrade performance However a larger value is optimal for DDR SDRAM performance 4 BLMR RW Big Little Endian Receive Mode 0x1 The DMA supports Big or Little Endian configurations per channel The BLMR bit only affects data transfer to memory 1 No swap 0 Byte swap 5 BLMT RW Big Little Endian Transmit Mode 0x1 The DMA supports Big or Little Endian configurations per channel The BLMT bit only affects data transfer from memory 1 No swap 0 Byte swap 6 SwapMode RW Swap mode 0x0 The DMA supports swapping for descriptors only for both receive and
8. Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 110 88F5182 marveL Open Source Community Programmer s User Guide Table 80 CS 1 n Size Register Offset 0x0150C Bits Field Type Description InitVal 0 En RW Window Enable 0x1 0 Disable 1 Enable 15 1 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved OxFF 31 24 Size RW CS 1 n Bank Size OxOF Corresponds to Base Address bits 31 24 Must be programmed from LSB to MSB as a sequence of 1 s followed by a sequence of 0 s Table 81 CS 2 n Base Address Register Offset 0x01510 Bits Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved OxFF 31 24 Base RW CS 2 Base Address 0x20 Corresponds to Marvell processor core address bits 31 24 Table 82 CS 2 n Size Register Offset 0x01514 Bits Field Type Description InitVal 0 En RW Window Enable 0x1 0 Disable 1 Enable 15 1 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved OxFF 31 24 Size RW CS 2 n Bank Size 0x0F Corresponds to Base Address bits 31 24 Must be programmed from LSB to MSB as a sequence of 1 s followed by a sequence of 0 s Doc No MV S400130 00 Rev 0 5 Page 111 Document Classification Proprietary Copyright 2007 Marvell J
9. Table 391 IP Differentiated Services CodePoint 2 to Priority DSCP2 DSCP3 DSCP4 DSCP5 Offset DSCP2 0x72428 DSCP3 0x7242C DSCP4 0x72430 DSCP5 0x72434 Bits Field Type Description InitVal 29 0 TOS Q 89 60 RW The Priority queue mapping of received frames with DSCP values 20 corre 0x0 sponding to TOS_Q 62 60 through 29 corresponding to TOS_Q 89 87 NOTE The initial value means that ToS does not effect queue decisions 31 30 Reserved RO Reserved 0x0 Table 392 IP Differentiated Services CodePoint 6 to Priority DSCP6 Offset 0x72438 Bits Field Type Description InitVal 11 0 TOS Q 191 18 RW The Priority queue mapping of received frames with DSCP values 60 corre 0 0x0 sponding to TOS Q 2 0 through 63 corresponding to TOS Q 191 180 NOTE The initial value means that ToS does not effect queue decisions 31 12 Reserved RO Reserved 0x0 N Note The following steps for changing the value of the Port Serial Control register bits do not apply to Force Link Pass bit 1 lt ForceFCMode gt bits 6 5 ForceBPMode bits 8 7 and lt ForceLinkFail gt bit 10 Doc No MV S400130 00 Rev 0 5 Page 283 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers When changing the value of the Port Serial Control register bits the following steps must b
10. PCI Interface Registers Table 227 PCI Access Control Size 1 Offset Ox31E18 Bits Field Type Description InitVal 31 0 Various RES Same as in PCI Access Control Size 0 RW 0x0 Table 228 PCI Access Control Base 2 Low Offset Ox31E20 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 Low RES 0x0 Table 229 PCI Access Control Base 2 High Offset Ox31E24 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 High 0x0 Table 230 PCI Access Control Size 2 Offset Ox31E28 Bits Field Type Description InitVal 31 0 Various RES Same as in PCI Access Control Size 0 RW 0x0 Table 231 PCI Access Control Base 3 Low Offset 0x31E30 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 Low RES 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 190 88F5182 marveL Open Source Community Programmer s User Guide Table 232 PCI Access Control Base 3 High Offset Ox31E34 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 High 0x0 Table 233 PCI Access Control Size 3 Offset Ox31E38 Bits Field Type Descripti
11. multiple hit access protect write protect Once the address is latched no new address is latched until SW reads it Read access to XEEAR SW should read XEECR first and than XEEAR Doc No MV S400130 00 Rev 0 5 Page 371 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary XOR Engine Registers A 16 3 XOR Engine Descriptor Registers Table 549 XOR Engine 0 1 Next Descriptor Pointer XExNDPR Offset XORO 0x60B00 XOR1 0x60B04 Bit Field Type Description InitVal 31 0 NextDescPtr 4 0 RO XOR Engine s next descriptor address pointer 0x0 In XOR mode bits 5 0 must be zero 31 5 RW In CRC DMA mode bits 4 0 must be zero 0x0 NOTE The value 0x0 is reserved for end of chain NULL indication Descriptors must not be placed at address 0x0 The XOR Engine will ignore attempts to read a descriptor from that address Table 550 XOR Engine 0 1 Current Descriptor Pointer XExCDPR Offset XORO 0x60B10 XOR1 0x60B14 Bit Field Type Description InitVal 31 0 CurrentDescPtr RO XOR Engine current descriptor address pointer points to the last descrip 0x0 tor that was fetched Table 551 XOR Engine 0 1 Byte Count XExBCR Offset XORO 0x60B20 XOR1 0x60B24 Bit Field Type Description InitVal 31 0 ByteCnt RO Number of bytes left for the XOR Engine to execute the current descriptor 0x0 operatio
12. Table 15 ePRD DWORD 3 Bits Field Description 31 0 Reserved Reserved 7 2 8 8 Command Response Queue The response queue is the interface that the EDMA uses to notify the CPU software that a data transaction between the system memory and the device was completed The response queue is a 128 32 entry circular queue FIFO whose location is configured by the EDMA Response Queue In Pointer Register Table 319 p 234 and the EDMA Response Queue Out Pointer Register Table 320 p 235 The queue status is determined by comparing the two pointers e A queue is empty when the Response Queue Out pointer reaches the Response Queue In pointer A queue is full when Response Queue In pointer is written with same value as a Response Queue Out pointer A full queue contains 128 32 entries as configured in the xeEDMAQueLen field in the EDMA Configuration Register Table 228 p 228 e A queue contains N entries when the Response Queue Out pointer is N less than the Response Queue lIn pointer taking into account the wraparound condition Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 30 88F5182 marveL Open Source Community Programmer s User Guide S Note The EDMA may write over existing entries when the queue is full See Figure 4 Command Response Queue 32 Entries on page 23 and Figure 6 C
13. Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 132 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 113 PCI Express Interrupt Cause Continued Offset 0x41900 NOTE AN bits except bits 27 24 are Read Write Clear only A cause bit sets upon an event occurrence A write of 0 clears the bit A write of 1 has no affect Bits 24 27 are set and cleared upon reception of interrupt emulation messages Bits Field Type InitVal Description 22 PexSIvLb RWOC 0x0 Slave Loopback Indication The bit sets when the opposite device on the PCI Express port is acting as a loopback master and loopback mode was entered NOTE Sticky bit not initialized by reset 23 PexLinkFail RWOC 0x0 Link Failure indication PCI Express link dropped from active state LO LOs or L1 to Detect state due to link errors NOTE When dropping to Detect via Hot Reset Disable Link or Loopback states the interrupt is not asserted Sticky bit not initialized by reset 24 RevintA RO 0x0 IntA status Reflects IntA Interrupt message emulation status Set when IntA_Assert message received Cleared when IntA Deassert message received or upon link failure sce nario DI down NOTE This bit is not RWOC as some other bits in this register since it is cleared by the inte
14. enabled 6 4 RXQArp RW Default Rx Queue for ARP Broadcasts if receiving ARP Broadcasts is 0x0 enabled 7 RB RW Reject mode of MAC Broadcasts that are not IP or ARP Broadcast 0x0 0 Receive to the RXQ queue 1 Reject 8 RBIP RW Reject mode of MAC Broadcasts that are IP Ethertype 0x800 0x0 0 Receive to the RXQ queue 1 Reject 9 RBArp RW Reject mode of MAC Broadcasts that are ARP Ethertype 0x806 0x0 0 Receive to RXQArp queue 1 Reject 11 10 Reserved RW Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 277 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 381 Port Configuration PxC Continued Offset 0x72400 Bits Field Type Description InitVal 12 AMNOTXxES RW Automatic mode not updating Error Summary in Tx descriptor 0x0 The advantage of using this bit is that it avoids another write to memory to update the error status 13 Reserved RW Reserved 0x0 Must be set to 0 14 TCP_CapEn RW Capture TCP frames to lt TCPQ gt 0x0 1 Enable 0 Disable 15 UDP_CapEn RW Capture UDP frames to lt UDPQ gt 0x0 1 Enable 0 Disable 18 16 TCPQ RW Captured TCP frames are directed to this Queue number 0x0 21 19 UDPQ RW Captured UDP frames are directed to this Queue number 0x0 24 22 BPDUQ RW Captured BPDU frames if PCXR Span is set are directed to this Queue Ox7 number 25 RxCS RW R
15. Bits Field Type Description InitVal 31 0 AesEncKeyCol6 RW Contains Column 6 of the AES encryption key or Column 6 of the decryption 0x0 key when AES Key Read Mode is set Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 324 88F5182 marveL Open Source Community Programmer s User Guide Table 468 AES Encryption Key Column 5 Register Offset Ox9DD88 Bits Field Type Description InitVal 31 0 AesEncKeyCol5 RW Contains Column 5 of the AES encryption key or Column 5 of the decryption 0x0 key when AES Key Read Mode is set Table 469 AES Encryption Key Column 4 Register Offset Ox9DD8C Bits Field Type Description InitVal 31 0 AesEncKeyCol4 RW Contains Column 4 of the AES encryption key or Column 4 of the decryption 0x0 key when AES Key Read Mode is set Table 470 AES Encryption Command Register Offset Ox9DDBO Bits Field Type Description InitVal 1 0 AesEncKeyMode RW This field specifies the AES128 key size used 0x0 00 128 bit key 01 192 bit key 10 256 bit key 11 Reserved 3 2 Reserved RES Reserved 0x0 4 DataByteSwap RW This bit controls whether data byte swap is activated on input 0x0 0 No byte swap 1 Byte swap 7 5 Reserved RES Reserved 0x0 8 OutByteSwap RW This bit controls whether byte sw
16. Bits Field Type Description InitVal 6 4 SrcBurstLimit RW Burst Limit in each source read request access over the Internal Crossbar 0x4 0x0 Reserved 0x1 Reserved 0x2 32 Bytes 0x3 64 Bytes 0x4 128 Bytes 0x5 Reserved 0x5 Reserved 0x7 Reserved 7 Reserved RW Reserved 0x0 10 8 DstBurstLimit RW Burst Limit in each destination write request access over the Internal 0x4 Crossbar 0x0 Reserved 0x1 Reserved 0x2 32 Bytes 0x3 64 Bytes 0x4 128 Bytes 0x5 Reserved 0x5 Reserved 0x7 Reserved NOTE When using cache coherency the burst limit must not exceed 32 bytes 11 Reserved RW Reserved 0x0 12 DrdResSwp RW Data Read Response Endianess Swap control 0x0 0 Do not swap endianess 1 Swap endianess If swapping is enabled byteO is exchanged with byte7 byte1 with byte 6 etc 13 DwrReqSwp RW Data Write request Endianess Swap control 0x0 0 Do not swap endianess 1 Swap endianess If swapping is enabled byteO is exchanged with byte7 byte1 with byte 6 etc 14 DesSwp RW Descriptor read write Endianess Swap control 0x0 0 Do not swap endianess 1 Swap endianess If swapping is enabled byteO is exchanged with byte7 byte1 with byte 6 etc Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 367 Document Classification Proprietary June 25 2007 Preliminary XOR Engine Registers Table 543 XOR Engine 0 1 Configuration XEx
17. June 25 2007 Copyright O 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 388 LLL EH EH MARVELL Marvell Semiconductor Inc 5488 Marvell Lane Santa Clara CA 95054 USA Tel 1 408 222 2500 Fax 1 408 752 9028 www marvell com Marvell Moving Forward Faster
18. 88F5182 marveL Open Source Community Programmer s User Guide Table 398 Port Interrupt Cause IC Continued Offset 0x72460 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 2 RxBufferQueue RW Rx Buffer Return in Priority Queue 0 indicates a Rx buffer returned to CPU 0 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 0 3 RxBufferQueue RW Rx Buffer Return in Priority Queue 1 indicates a Rx buffer returned to CPU 1 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 1 4 RxBufferQueue RW Rx Buffer Return in Priority Queue 2 indicates a Rx buffer returned to CPU 2 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 2 5 RxBufferQueue RW Rx Buffer Return in Priority Queue 3 indicates a Rx buffer returned to CPU 3 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 3 6 RxBufferQueue RW Rx Buffer Return in Priority Queue 4 indicates a Rx buffer returned to CPU 4 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 4 7 RxBufferQueue RW Rx Buffer Return in Priority Queue 5 indicates a Rx buffer returned to CPU 5 0x0 ownership or that the port completed reception of a
19. Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxF000 Table 129 PCI Express Window4 Remap Register Offset 0x4186C Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 139 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 130 PCI Express Window5 Control Register Offset 0x41880 Bits Field Type Description InitVal 0 WinEn RW Window Enable 0x1 1 BarMap RW Mapping To BAR 0x1 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x1 15 8 Attr RW Target specific attributes depending on the target interface OxOF 31 16 Size RW Window Size 0x07FF A value of 0x07FF specifies 128 MByte Table 131 PCI Express Window5 Base Register Offset 0x41884 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxF800 Table 132 PCI Express Window5 Remap Register Offset 0x4188C Bits Field Type Description I
20. Bits Field Type Function InitVal 0 win_en RW Window0 Enable 0x0 0x0 Window is disabled 0x1 Window is enabled 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the target interface associated with this window 0x0 See Section 2 10 Default Address Map on page 14 15 8 Attr RW Specifies the target interface attributes associated with this window 0x0 See Section 2 10 Default Address Map on page 14 31 16 Size RW Window Size 0x0 Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window e g a value of OxOOFF specifies 256x64k 16 MB Table 427 USB 2 0 Window0 Base Register 0x50324 Porti 0xA0324 Offset Port Bits Field Type Function InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x0 Used with the size field to set the address window size and location Corresponds to transaction address 31 16 Table 428 USB 2 0 Window1 Control Register 0x50330 Port1 0xA0330 Offset Port Bits Field Type Function InitVal 0 win en RW Window0 Enable 0x0 0x0 Window is disabled 0x1 Window is enabled 3 1 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 309 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary USB 2 0 Register
21. Doc No MV S400130 00 Rev 0 5 Page 97 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Local to System Bridge Registers Table 52 Window Control Register Continued Offset 0x20070 Bits Field Type Description InitVal 7 4 Target RW Specifies the unit ID target interface associated with this window 0x1 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface OxOF See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size 0x07FF See the Window0 Control Register Table 34 p 91 Table 53 Window Base Register Offset 0x20074 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxF800 See the Window0 Base Register Table 54 88F5182 Internal Registers Base Address Register Offset 0x20080 Bits Field Type Description InitVal 19 0 Reserved RSVD Reserved 0x0 The size of the 88F5182 Internal registers address space is 1 MByte 31 20 Base RW Internal registers Base Address 0xD00 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 98 MARVELL 88F5182 Open Source Community Programmer s User Guide A 4 2 CPU Control and Status Registers
22. Table 137 PCI Express Status Register Offset 0x41A04 Bits Field Type Description InitVal 0 DLDown RO DL Down indication 0 Active DL is up 1 Inactive DL is down 4 1 Reserved RSVD Reserved 0x0 7 5 Reserved RSVD Reserved 0x0 15 8 PexBusNum RW Bus Number Indication 0x0 This field is used in the RequesterlD field of the transmitted TLPs In Endpoint mode the field updates whenever a CfgWr access is received 20 16 PexDevNum RW Device Number Indication 0x0 This field is used in the RequesterlD field of the transmitted TLPs In Endpoint mode the field updates whenever a CfgWr access is received 23 21 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 143 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 137 PCI Express Status Register Continued Offset 0x41A04 Bits Field Type Description InitVal 24 PexSlvHot RO Slave Hot Reset Indication Reset 0x0 This field sets when the opposite device on the PCI Express port acts as a hot reset master and a hot reset indication is received 25 PexSlvDisLink RO Slave Disable Link Indication 0x0 This field sets when the opposite device on the PCI Express port acts as a disable link master and a link disabled indication is received 26 PexSlvLb RO Slave Loopback Indication 0x0 This field sets when the opposite d
23. BootCSn Base Address Remap Offset 0x30D54 P2P Mem0 Base Address Remap Low Offset OXG0D5C P2P Mem0 Base Address Remap High Offset OXS0D60 P2P I O Base Address Remap Offset Ox30D6C Expansion ROM Base Address Remap Offset OXS0F38 DRAM BAR Bank Geet Offset 0x30C1C PCI Address Decode Control Offset OX80D3C PCI DLL Control Offset 0x31D20 PCI MPP Pads Calibration Offset 0x31D1C PCI Commande Offset 0x30C00 PCI Mode Offset OX80D00 PCL B bee Breng Offset 0x30C04 PCI Discard Timer ccccccccccccccesssssssseeeeeeeeeees Offset OX30D04 MSI Trigger Timer ee eee eee eeeeee rete Offset 0x30C38 PCI Arbiter Control Offset 0x31D00 PCI P2P Configuration sess Offset 0x31D14 PCI Access Control Base 0 Low Offset 0x31E00 PCI Access Control Base 0 High Offset 0x31E04 PCI Access Control Gizen Offset 0x31E08 PCI Access Control Base 1 Low Offset 0x31E10 PCI Access Control Base 1 High Offset 0x31E14 PCI Access Control Gize Offset 0x31E18 PCI Access Control Base 2 Low Offset 0x31E20 Copyright 2007 Marvell June 25 2007 Preliminary Document Classifi
24. Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 206 88F5182 marveL Open Source Community Programmer s User Guide Table 267 PCI MSI Message Control Continued Offset 0x50 Bits Field Type Description InitVal 23 Addr64 RW 64 bit Addressing Capable 0x1 Indicates whether the 88F5182 is capable of generating 64 bit message address Read only from PCI 0 Not capable 1 Capable 31 24 Reserved RO Read only 0 0x0 Table 268 PCI MSI Message Address Offset 0x54 Bits Field Type Description InitVal 31 0 Addr RW Message Address 0x0 Table 269 PCI MSI Message Upper Address Offset 0x58 Bits Field Type Description InitVal 31 0 Addr RW Message Upper Address 0x0 32 upper address bits If set to a value other than 0 the 88F5182 issues MSI message as DAC cycle Table 270 PCI Message Data Offset 0x5C Bits Field Type Description InitVal 15 0 Data RW Message Data 0x0 Initiated by the system 31 16 Reserved RES Read only 0 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 207 Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 271 CompactPCI HotSwap Offset 0x68 Bits Field Type Description InitVal 7 0 CapID RW Capability I
25. Table 351 Serial ATA Interface Test Control Register Offset Port 0 0x82348 Port 1 0x84348 Bits Field Type Description InitVal 0 MBistEn RW Memory BIST Enable 0x0 Start Memory BIST test in MBIST mode 0 Memory BIST test disabled 1 Memory BIST test enabled 1 TransFrmSizExt RW Maximum Transmit Frame Size Extended 0x0 See field lt TransFrmSiz gt 15 14 3 2 Reserved RW Reserved 0x0 5 4 Reserved RO Reserved 0x0 7 6 Reserved RW Reserved 0x0 8 LBEnable RW PHY Loopback Enable 0x0 This bit enables SATA near end PHY loopback 0 PHY near end Loopback disabled 1 PHY near end Loopback enabled 12 9 LBPattern RW PHY Loopback pattern 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 258 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 351 Serial ATA Interface Test Control Register Continued Offset Port 0 0x82348 Port 1 0x84348 Bits Field Type Description InitVal 13 LBStartRd RW Loopback Start 0x0 BIST DW1 Register Table 347 p 254 is used as a User specified test pat tern low DWORD BIST DW2 Register Table 348 p 254 is used as a User specified test pat tern high DWORD These registers must be initiated before this bit is set 0 Disable 1 Enable Loopback Start 15 14 TransFrmSiz RW Maximum Transmit Frame Size 0x0 When lt Tr
26. transmit ports on every access to memory space 0 No swapping 1 Byte swap In every 64 bit word of the descriptor the byte order is swapped such that byte 0 is placed in byte 7 byte 7 is placed in byte 0 byte 1 is placed in byte 6 byte 6 is placed in byte 1 byte 2 is placed in byte 5 etc 7 Reserved RW Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 281 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 388 SDMA Configuration SDC Continued Offset 0x7241C Bits Field Type Description InitVal 21 8 IPGIntRx RW Rx frame IPG between interrupts counter and enable 0x0 This field provides a way to force a delay from the last ICR RxBufferQueue interrupt from any of the queues to the next RxBufferQueue interrupt from any of the queues The ICR bits still reflect the new interrupt but this masking is reflected by potentially not propagating to the chip main interrupt cause register This provides a way for interrupt coalescing on receive packet events The time is calculated in multiples of 64 clock cycles Valid values are 0 No delay between packets to CPU the counter is effec tively disabled through OxSFFF 1 048 544 clock cycles 24 22 TxBSZ RW Tx Burst Size 0x4 Sets the maximum burst size for Tx SDMA transactions 000 Burst is limited to 1 64 bit words 001 Burst is limited to 2 64 b
27. 0x0 NOTE Hot sticky bit not initialized by hot reset 13 Reserved SC Reserved 0x0 NOTE Sticky bit not initialized by hot reset 14 CmpTOErr SC Completion Timeout Status 0x0 NOTE Sticky bit not initialized by hot reset 15 CAErr SC Completer Abort Status 0x0 NOTE Sticky bit not initialized by hot reset 16 UnexpCmpErr SC Unexpected Completion Status 0x0 NOTE Sticky bit not initialized by hot reset 17 Reserved SC Reserved 0x0 NOTE Sticky bit not initialized by hot reset 18 MalfTlpErr SC Malformed TLP Status 0x0 NOTE Sticky bit not initialized by hot reset 19 Reserved RSVD Reserved 0x0 20 URErr SC Unsupported Request Error Status 0x0 NOTE Sticky bit not initialized by hot reset 31 21 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 164 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 169 PCI Express Uncorrectable Error Mask Register Offset 0x40108 Configuration 0x108 NOTE AU fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Mask RW When an error is indicated in the PCI Express Uncorrectable Error Status 0x0 Register Table 168 p 163 and the corresponding bit is set the header is not logged in the Header Log Register the First Error Pointer
28. Bits Field Type Description InitVal 31 2 MSIAddr RW Message Address 0x0 This field corresponds to Address 31 2 of the MSI MWr TLP Table 160 PCI Express MSI Message Address High Register Offset 0x40058 Configuration 0x58 Bits Field Type Description InitVal 31 0 MSIAddrh RW Message Upper Address 0x0 This field corresponds to Address 63 32 of the MSI MWr TLP Table 161 PCI Express MSI Message Data Register Offset 0x4005C Configuration 0x5C Bits Field Type Description InitVal 15 0 MSIData RW Message Data 0x0 31 16 Reserved RSVD Reserved 0x0 Table 162 PCI Express Capability Register Offset 0x40060 Configuration 0x60 Bits Field Type Description InitVal 7 0 CapID RO Capability ID 0x10 The current value of this field identifies the PCI PE capability 15 8 NextPtr RO Next Item Pointer 0x0 The current value of this field points to the end of the capability list NULL 19 16 CapVer RO Capability Version 0x1 This field indicates the PCI Express Base spec 1 0 version of the PCI Express capability 23 20 DevType RO Device Port Type 0x0 24 Slotlmp RO Slot Implemented 0x0 hardwired to 0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 156 88F5182 marveL Open Source Community Programmer s User Guide Table 162 PCI Expr
29. Bits Field Type Description InitVal 7 0 CapID RO Capability ID 0x5 The current value of this field identifies the PCI MSI capability 15 8 NextPtr RO Next Item Pointer 0x60 The current value of this field points to PCI Express capability 16 MSIEn RW MSI Enable 0x0 This bit controls the 88F5182 interrupt signaling mechanism 0 Disabled Interrupts are signalled through the interrupt emulation messages 1 Enabled Interrupts are signaled through MSI mechanism 19 17 MultiCap RO Multiple Message Capable 0x0 The 88F5182 is capable of driving a single message 22 20 MultiEn RW Multiple Messages Enable 0x0 The number of messages the system allocates to the 88F5182 This num ber must be smaller or equal to what is in the lt MultiCap gt field 23 Addr64 RO 64 bit Addressing Capable 0x1 This field indicates whether the 88F5182 is capable of generating a 64 bit message address 0 Not Capable 1 Capable 31 24 Reserved RSVD Reserved 0x0 Table 159 PCI Express MSI Message Address Register Offset 0x40054 Configuration 0x54 Bits Field Type Description InitVal 1 0 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 155 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 159 PCI Express MSI Message Address Register Continued Offset 0x40054 Configuration 0x54
30. Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 457 SHA 1 MD5 Authentication Command Register Continued Offset Ox9DD18 Bits Field Type Description InitVal 2 DataByteSwap RW This bit controls whether data byte swap is activated 0x0 0 No byte swap data to engine WO W15 0x01234567 1 Byte swap data to engine WO W15 0x67452301 Packet data written to the engine can be used as is or swapped by the engine before processing The main purpose of this field is for processing different notations of packet data data may be annotated as Big Endian or Little Endian 3 Reserved RES Reserved 0x0 4 IVByteSwap RW This bit controls whether initial value byte swap is activated 0x0 0 No byte swap 1 Byte swap This is the same as the data swap but only for initial values written to the IV Digest registers 30 5 Reserved RES Reserved 0x0 31 Termination RO This bit is set by the engine to indicate completion of a hash calculation pro 0x1 cess Any write to the Authentication engine will clear this bit A 11 3 AES Encryption Interface Registers Table 458 AES Encryption Data In Out Column 3 Register Offset OX9DDAO Bits Field Type Description InitVal 31 0 AesEncDatCol3 RW At first this field contains Column 3 of the input data block to be encrypted NA When the AES
31. DDR2 Refer to the Design Considerations for this product 0x0 DDR1 SDRAM Reserved must be set to 0x0 DDR1 0x0 9 7 Reserved RW Reserved 0x0 10 DQS RW DDR2 SDRAM Single ended DQS must be 0x1 DDR2 DDR1 SDRAM Reserved must be set to 0x0 0x1 DDR1 0x0 11 RDQS RW DDR2 SDRAM Read DQS DDR2 0 RDQS disabled 0x0 1 RDQS enabled DDR1 Must be 0x0 0x0 NOTE Read DQS is not supported DDR1 SDRAM Reserved must be set to 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 120 88F5182 marveL Open Source Community Programmer s User Guide Table 96 Extended DDR SDRAM Mode Register Continued Offset 0x01420 NOTE If configured to DDR1 SDRAM bits 13 2 are not relevant and must be set to 0x0 Bits Field Type Description InitVal 12 Qoff RW DDR2 SDRAM DDR SDRAM output buffer enable DDR2 0 Enabled 0x0 1 Disabled DDR1 DDR1 SDRAM Reserved must be set to 0x0 0x0 13 Reserved RW Reserved 0x0 31 14 Reserved RO Reserved 0x0 Table 97 DDR SDRAM Initialization Control Register Offset 0x01480 Bits Field Type Description InitVal 0 InitEn SC Initialization enable 0x0 DDR SDRAM initialization sequence starts upon setting this bit to 1 This bit is cleared when initialization completes 31 1 Reserved RO Reserved 0x0 Table 98 DDR SDRAM Address Contro
32. Reserved RO Reserved 0x0 28 24 Offset RO NOTE Reserved for Marvel usage 0x0 30 29 Reserved RO Reserved 0x0 31 WrEn RW Write Enable CPU Pads Calibration register 0x0 0 Register is read only except for bit 31 1 Register is writable Table 375 Ethernet Unit Control EUC Offset 0x720B0 Bits Field Type Description InitVal 0 Porto DPPar RW Gigabit Ethernet port data path parity select 0x0 0 Even parity 1 Odd parity NOTE Should be set to even parity for normal operation Odd parity is for debugging only 2 1 Reserved RW Reserved 0x0 3 Top DPPar RW Gigabit Ethernet Top data path parity select 0x0 0 Even parity 1 Odd parity NOTE Should be set to even parity for normal operation Odd parity is for debugging only 15 4 Reserved RO Reserved 0x0 16 Pot DW RW Gigabit Ethernet port power management 0x1 0 Power Down port deactivate 1 Power Up normal operation NOTE Reserved for Marvell usage Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 274 88F5182 marveL Open Source Community Programmer s User Guide Table 375 Ethernet Unit Control EUC Continued Offset 0x720B0 Bits Field Type Description InitVal 18 17 Reserved RW Reserved 0x0 31 19 Reserved RO Reserved 0x0 Table 376 Base Address Offset BAO
33. Slave received slave address acknowledge transmitted 0x68 Master lost arbitration during address transmit address is targeted to the slave write access acknowledge transmitted 0x70 General call received acknowledge transmitted 0x78 Master lost arbitration during address transmit general call address received acknowledge transmitted 0x80 Slave received write data after receiving slave address acknowledge transmitted 0x88 Slave received write data after receiving slave address acknowledge not transmitted 0x90 Slave received write data after receiving general call acknowledge transmitted 0x98 Slave received write data after receiving general call acknowledge not transmitted OxA0 Slave received stop or repeated start condition 0xA8 Slave received address read bit acknowledge transmitted OxBO Master lost arbitration during address transmit address is targeted to the slave read access acknowledge transmitted 0xB8 Slave transmitted read data acknowledge received 0xCO Slave transmitted read data acknowledge not received 0xC8 Slave transmitted last read byte acknowledge received OxDO Second address write bit transmitted acknowledge received OxD8 Second address write bit transmitted acknowledge not received OxEO Second address read bit transmitted acknowledge received OxE8 Second address read bit transmitted acknowledge not received OxF8 No relevant stat
34. 0x0 15 8 Attr RW Target specific attributes depending on the target interface 0x07 31 16 Size RW Window Size OxOFFF Table 125 PCI Express Window3 Base Register Offset 0x41854 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x3000 Table 126 PCI Express Window3 Remap Register Offset 0x4185C Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 138 88F5182 marveL Open Source Community Programmer s User Guide Table 127 PCI Express Window4 Control Register Offset 0x41860 Bits Field Type Description InitVal 0 WinEn RW Window Enable 0x1 1 BarMap RW Mapping To BAR 0x1 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x1 15 8 Attr RW Target specific attributes depending on the target interface 0x1B 31 16 Size RW Window Size 0x07FF A value of 0x07FF specifies 128 MByte Table 128 PCI Express Window4 Base Register Offset 0x41864
35. 0x110 NOTE AN fields in this register are sticky not initialized or modified by hot reset All fields in this register except for reserved fields are SC write 1 to clear Bits Field Type Description InitVal 6 BadTlpErr SC Bad TLP Status 0x0 7 BadDIlpErr SC Bad DLLP Status 0x0 8 RplyRllovrErr SC Replay Number Rollover Status 0x0 11 9 Reserved RSVD Reserved 0x0 12 RplyTOErr SC Replay Timer Timeout status 0x0 31 18 Reserved RSVD Reserved 0x0 Table 172 PCI Express Correctable Error Mask Register Offset 0x40114 Configuration 0x114 NOTE AN fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Mask RW If set an error message is not generated upon occurrence of a Receiver 0x0 error 0 Not masked 1 Masked Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 166 e E 88F5182 marveL Open Source Community Programmer s User Guide Table 173 PCI Express Advanced Error Capability and Control Register Offset 0x40118 Configuration 0x118 Bits Field Type Description InitVal 4 0 FrstErrPtr RO First Error Pointer 0x0 This field reports the bit position of the first error reported in the Table 168 PCI Express Uncorrectable Error Status Register This field locks upon receipt of the first
36. 0x72684 Bits Field Type Description InitVal 31 0 TxCDP RO Transmit Current Descriptor Pointer 0x0 Table 411 Transmit Current Queue Descriptor Pointer TCQDP Offset Q0 0x726C0 Type Description InitVal TxCDP Transmit Current Queue Descriptor Pointer a Table 412 Transmit Queue Token Bucket Counter TOxTBC Offset Q0 0x72700 Q1 0x72710 Q2 0x72720 Q3 0x72730 Q4 0x72740 Q5 0x72750 Q6 0x72760 Q7 0x72770 NOTE Transmit Queues 1 7 are reserved Bits Field Type Description InitVal 29 0 Reserved RW Reserved Undefined NOTE Queue 0 offset 0x72700 must be programmed to Ox3FFFFFFF Must be Queue 1 through 7 offset 0x72710 0x72720 0x72730 0x72740 initialized 0x72750 0x72760 0x72770 must be programmed to 0x0 31 30 Reserved RO Read only 0x0 Table 413 Transmit Queue Token Bucket Configuration TQxTBC Offset Q0 0x72704 Q1 0x72714 Q2 0x72724 Q3 0x72734 Q4 0x72744 Q5 0x72754 Q6 0x72764 Q7 0x72774 NOTE Transmit Queues 1 7 are reserved Bits Field Type Description InitVal 25 0 Reserved RW Reserved Undefined NOTE Queue 0 offset 0x72704 must be programmed to Ox3FFFFFF Must be Queue 1 through 7 offset 0x72714 0x72724 0x72734 0x72744 initialized 0x72754 0x72764 0x72774 must be programmed to 0x0 31 26 Reserved RO Read Only 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 20
37. 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 484 Security Accelerator Command Register Continued Offset Ox9DEOO0 Bits Field Type Description InitVal 1 EnSecurityAccl1 RW Setting this bit activates session 1 of the accelerator After operation 0x0 completion this bit is cleared to zero by the hardware Writing zero to this bit has no effect Security acceleration assures in order execution and completion If session 1 is activated before session 0 by setting this bit before bit lt EnSecurityAccl0 gt the Security acceleration always execute session 1 before session 0 0 Session 0 is idle 1 Session 0 is set to active 2 DsSecurityAccl ARZ Disable accelerator 0x0 This bit is self negated When this bit is set to 1 the accelerator aborts the current command and then clears bits AcclntO Accint1 NOTE ARZ Auto Reset to Zero after the AcclntO Accint1 bits are cleared 31 3 Reserved RO Reserved 0x0 Table 485 Security Accelerator Descriptor Pointer Session 0 Register Offset 0x9DE04 Bits Field Type Description InitVal 15 0 SecurityAcclIDesc RW Security accelerator descriptor pointer for session 0 DWORD aligned PtrO 0x0 Bits 0 1 2 13 14 and 15 are reserved and are assumed to be and are read as 0 regardless of programming 31 116 Reserved RW Reserved 0x0 Table 486 Security Accelerator Descrip
38. 226 A 8 3 EDMA Registers Map Each port contains an independent set of the following registers Table 290 EDMA Registers Map Register Offset Table Page EDMA Configuration Register Port 0 0x82000 Port 1 0x84000 Table 311 p 226 EDMA Timer Register Port 0 0x82004 Port 1 0x84004 Table 312 p 230 EDMA Interrupt Error Cause Register Port 0 0x82008 Port 1 0x84008 Table 313 p 230 EDMA Interrupt Error Mask Register Port 0 0x8200C Port 1 0x8400C Table 314 p 233 EDMA Request Queue Base Address High Port 0 0x82010 Port 1 0x84010 Table 315 p 233 Register EDMA Request Queue In Pointer Register Port 0 0x82014 Port 1 0x84014 Table 316 p 233 EDMA Request Queue Out Pointer Register Port 0 0x82018 Port 1 0x84018 Table 317 p 234 EDMA Response Queue Base Address High Port 0 0x8201C Port 1 0x8401C Table 318 p 234 Register EDMA Response Queue In Pointer Register Port 0 0x82020 Port 1 0x84020 Table 319 p 234 EDMA Response Queue Out Pointer Register Port 0 0x82024 Port 1 0x84024 Table 320 p 235 EDMA Command Register Port 0 0x82028 Port 1 0x84028 Table 321 p 236 EDMA Test Control Register Port 0 0x8202C Port 1 0x8402C Table 322 p 237 EDMA Status Register Port 0 0x82030 Port 1 0x84030 Table 323 p 238 EDMA IORdy Timeout Register Port 0 0x82034 Port 1 0x84034 Table 324 p 239 EDMA Command Delay Threshold Register Port 0 0x82040 Port 1 0
39. 3 DMA Setup FIS FISWait4Rdy 4 Data FIS first DW FISWait4Rdy 5 Data FIS entire FIS FISWait4Rdy 7 6 Reserved 0 No interrupt indication 1 Corresponding interrupt occurs For any FIS other than data FIS the corresponding bit is set when the entire FIS is received from the link layer without an error that is FIS DWO Register through FIS DW6 Register are updated with the content of the FIS see Table 357 on page 265 Table 363 on page 266 If the non data FIS length is shorter than 7 DWORDS only the relevant reg isters are updated with the content of the FIS If the non data FIS length is longer than 7 DWORDS FIS DWO Register through FIS DW6 Register are updated with the content of the FIS The rest of FIS is dropped For data FIS FISWait4Rdy 4 is set when the first DWORD of the FIS is received from the link layer and FISWait4Rdy 5 is set when the entire FIS is received from the link layer regardless of whether or not an error occurred Only FIS DWO Register is updated with the content of the FIS FIS DW1 Register through FIS DW6 Register are not updated When at least one bit in this field is set and the corresponding bit in the FISWait4RdyEn s field in the FIS Configuration Register Table 354 p 262 is enabled set to 1 the transport layer prevents assertion of the primitive H RDY and the reception of the next FIS Doc No MV S400130 00 Rev 0 5 Page 263 Copyright O 2007 Marvell Documen
40. 31 1 Register is writable Table 99 DDR SDRAM Data Pads Calibration Register Offset 0x014C4 Bits Field Type Description InitVal 31 0 Various RW Same as the DDR SDRAM Address Control Pads Calibration Register RO register 0x144 Table 100 DDR2 SDRAM ODT Control Low Register Offset 0x01494 Bits Field Type Description InitVal 3 0 ODTORd RW M ODTT 0 control for read transactions 0x0 Bit 0 if set to 1 M_ODT 0 is asserted during read from DDR SDRAM bank 0 Bit 1 if set to 1 M_ODT 0 is asserted during read from DDR SDRAM bank 1 Bit 2 if set to 1 M_ODT 0 is asserted during read from DDR SDRAM bank 2 Bit 3 if set to 1 M_ODT 0 is asserted during read from DDR SDRAM bank 3 Refer to the Design Considerations for this product Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 122 MARVELL e 88F5182 E Open Source Community Programmer s User Guide Table 100 DDR2 SDRAM ODT Control Low Register Continued Offset 0x01494 Bits Field Type Description InitVal 7 4 ODT1Rd RW M_ODT 1 control for read transactions 0x0 Same as ODTORd 11 8 ODT2Rd RW M ODTT2 control for read transactions 0x0 Same as ODTORd 15 12 ODT3Rd RW M_ODT 3 control for read transactions 0x0 Same as lt ODTORd gt 19 16 ODTOWr
41. 8 SATA registers 64 KByte 512K 576K 0x80000 0x8FFFF 9 Cryptographic Engine and 64 KByte 576K 640K 0x90000 0x9FFFF Security Accelerator registers A USB Registers Port 1 64 KByte 640K 704K 0xA0000 0xAFFFF B F Reserved S 704K 1024K 0xB0000 0xFFFFF Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 89 Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers AA Local to System Bridge Registers Table 33 CPU Register Map Register Name Offset Table Number and Page Number CPU Address Map Registers Window0 Control Register 0x20000 Table 34 p 91 Window0 Base Register 0x20004 Table 35 p 92 Window0 Remap Low Register 0x20008 Table 36 p 92 Window0 Remap High Register 0x2000C Table 37 p 92 Window1 Control Register 0x20010 Table 38 p 92 Window1 Base Register 0x20014 Table 39 p 93 Window1 Remap Low Register 0x20018 Table 40 p 93 Window1 Remap High Register 0x2001C Table 41 p 93 Window2 Control Register 0x20020 Table 42 p 94 Window2 Base Register 0x20024 Table 43 p 94 Window Control Register 0x20030 Table 44 p 94 Window3 Base Register 0x20034 Table 45 p 95 Window4 Control Register 0x20040 Table 46 p 95 Window4 Base Register 0x20044 Table 47 p 95 Window5 Control Register 0x20050 Table 48 p 96 Window5 Base Register 0x20054 Table 49 p 96 Window6 Control Register 0x20060 Table 50 p 96
42. InitVal 31 0 Various RW Same as CSn 0 Base Address Remap OxE0000000 Table 211 DRAM BAR Bank Select Offset 0x30C1C Bits Field Type Description InitVal 1 0 DBO RW DRAM CSO0n BAR select 0x0 0x0 CSOn 0x1 CS1n 0x2 CS2n 0x3 CS3n 3 2 DB1 RW Same as lt DB0 gt 0x1 5 4 DB2 RW Same as lt DB0 gt 0x2 7 6 DB3 RW Same as lt DB0 gt 0x3 31 8 Reserved RO Reserved 0x0 Table 212 PCI Address Decode Control Offset Ox30D3C Bits Field Type Description InitVal 0 RemapWrDis RW Address Remap Registers Write Disable 0x0 0 Writes to a BAR result in updating the corresponding remap register with the new value of the BAR 1 Writes to a BAR have no affect on the corresponding Remap register value 2 1 Reserved RES 0x0 3 Reserved RW Reserved 0x1 7 4 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 179 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 212 PCI Address Decode Control Continued Offset Ox30D3C Bits Field Type Description InitVal 24 8 VPDHighAddr RW Bits 31 15 of the VPD address 0x0 31 25 Reserved RES Reserved 0x0 A 7 2 PCI Control Registers Table 213 PCI DLL Control Offset 0x31D20 Bits Field Type Description InitVal 0 En RW DLL Enable 0x0 0 Disabled 1 Enabled 2 1 Mode RW
43. Offset 0x10 Table 254 PCI CSn 0 Base Address High ssessssssssssseseseneeeeneennenennen nennen nennen n reset resins nnns 201 Offset 0x14 Table 255 PCI CSn 1 Base Address Low 202 Offset 0x18 Table 256 PCI CSn 1 Base Address High sssesssssssesssseseneeneeee nennen nnne nennt nnne renes 202 Offset 0x1C Table 257 PCI Internal Registers Memory Mapped Base Address Low 202 Offset 0x20 Table 258 PCI Internal Registers Memory Mapped Base Address Hab 202 Offset 0x24 Table 259 PCI Subsystem Device and Vendor ID 203 Offset 0x2C Table 260 PCI Expansion ROM Base Address Heglster eene 203 Offset 0x30 Table 261 PCI Capability List Pointer Register nennen nennen nnne reset nennen 203 Offset 0x34 Table 262 PCI Interrupt Pin and Line nennen nennen nnne nnns en nnne daa Ki sitne nennen entries 203 Offset 0x3C Table 263 PCI Power Management ken 204 Offset 0x40 Table 264 PCI Power Management Control and Giats enne nnne nnne 205 Offset 0x44 able 265 1PCIVPD Address ee eee e a rd e a ee 205 Offset 0x48 Table 266 PGI VPD Dalaran no dees oed ob iR dE eee en Pes 206 Offset 0x4C Table 267 PCI MSI Message Control 206 Offset 0x50 Table 268 PCI MSI Message Address A 207 Offset 0x54 Table 269 PCI MSI Message Upper Address 207 Offset 0x58 Table 270 PGl Message Data ehe pete ead o o texte o i RE ERR Qu eda da o t et ge ee e 207 Offset 0x5C EIE
44. OxF the first data sampled by the 88F5182 and the cycle containing the next data sampled Minimal value 0x2 NOTE This field uses an additional bit in field lt Acc2NextExt gt bit 24 13 11 ALE2Wr RW Defines the number of cycles in a write access from the DEV_ALE 0 0x7 negation to the assertion of DEV WEn Number of cycles lt ALE2Wr gt 3 Minimal value 0x4 NOTE This field uses an additional bit in field lt ALE2WrExt gt bit 25 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 348 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 513 Device Bank Parameters Register Continued Offset 0x1045C Bits Field Type Description InitVal 16 14 WrLow RW The number of cycles in a write access that the DEV WEn signal is kept 0x7 active NOTE This field uses an additional bit in field lt WrLowExt gt bit 26 19 47 WrHigh RW The number of cycles in a burst write access that the DEV_WEn signal is 0x7 kept de asserted NOTE This field uses an additional bit in field lt WrHighExt gt bit 27 21 20 DevWidth RW Device Width Sampled 00 8 bits at reset 01 16 bits 10 Reserved 11 Reserved 22 TurnOffExt RW TurnOff Extension 0x1 The MSB of the TurnOff parameter 23 Acc2FirstExt RW Acc2First Extension 0x1 The MSB of the Acc2First paramet
45. PCI Configuration Function 4 Register Map Register Offsets Page PCI P2P Mem0 Base Address Low 0x10 Table 284 p 211 PCI P2P Memo Base Address High 0x14 Table 285 p 211 PCI P2P UO Base Address 0x20 Table 286 p 211 PCI Internal Registers I O Mapped Base Address 0x24 Table 287 p 212 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 172 88F5182 marveL Open Source Community Programmer s User Guide A 7 1 PCI Slave Address Decoding Registers Table 187 CSn 0 BAR Size Offset 0x30C08 Bits Field Type Description InitVal 11 0 Reserved RO Read only 0x0 31 12 BARSize RW CSn 0 BAR Address Bank Size OxOFFFF Must be programmed from LSB to MSB as sequence of 1s followed by sequence of Os For example a OXOFFF F000 size register value represents a BAR size of 256 MB Table 188 CSn 1 BAR Size Offset 0x30D08 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW OxOFFFFO000 Table 189 CSn 2 BAR Size Offset Ox30COC Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW OxOFFFFO000 Table 190 CSn 3 BAR Size Offset 0x30D0C Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW OxOFFFFO000 Doc
46. PCI VPD Address 0x48 Table 265 p 205 PCI VPD Data 0x4C Table 266 p 206 PCI MSI Message Control 0x50 Table 267 p 206 PCI MSI Message Address 0x54 Table 268 p 207 PCI MSI Message Upper Address 0x58 Table 269 p 207 PCI Message Data 0x5C Table 270 p 207 CompactPCI HotSwap 0x68 Table 271 p 208 Doc No MV S400130 00 Rev 0 5 Page 171 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 183 PCI Configuration Function 1 Register Map Register Offsets Page PCI CSn 2 Base Address Low 0x10 Table 272 p 208 PCI CSn 2 Base Address High 0x14 Table 273 p 209 PCI CSn 3 Base Address Low 0x18 Table 274 p 209 PCI CSn 3 Base Address High 0x1C Table 275 p 209 Table 184 PCI Configuration Function 2 Register Map Register Offsets Page PCI DevCS 0 Base Address Low 0x10 Table 276 p 209 PCI DevCSn 0 Base Address High 0x14 Table 277 p 210 PCI DevCSn 1 Base Address Low 0x18 Table 278 p 210 PCI DevCSn 1 Base Address High 0x1C Table 279 p 210 PCI DevCSn 2 Base Address Low 0x20 Table 280 p 210 PCI DevCSn 2 Base Address High 0x24 Table 281 p 210 Table 185 PCI Configuration Function 3 Register Map Register Offsets Page PCI BootCS Base Address Low 0x18 Table 282 p 211 PCI BootCSn Base Address High 0x1C Table 283 p 211 Table 186
47. Q0 0x7260C Q1 0x7261C Q2 0x7262C Q3 0x7263C Q4 0x7264C Q5 0x7265C Q6 0x7266C Q7 0x7267C Bits Field Type Description InitVal 31 0 RxCDP RW Receive Current Queue Descriptor Pointer 0x0 Copyright O 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 296 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 409 Receive Queue Command RQC Bits Offset Field 0x72680 Type InitVal Description 7 0 ENQ RW 0x0 Enable Queue 7 0 One bit per each queue Writing these bits set to 1 enables the queue The Receive DMA will fetch the first descriptor programmed to the RxCDP regis ter for that queue and start the Receive process Writing 1 to ENQ bit resets the matching lt DISQ gt bit Writing 1 to ENQ bit of a DMA that is already in enable state has not effect Writing 0 to ENQ bit has no effect When the receive DMA encounters a queue ended by a null terminated descriptor pointer or a descriptor with a parity error the DMA will clear the ENQ bit for that queue Thus reading these bits reports the active enable status for each queue NOTE Reaching a CPU owned descriptor a null terminated descriptor or a descriptor that is read with a parity error in the middle of a packet will result in closing the status of the packet with a resource error condition Reaching a CPU
48. Table 88 DDR SDRAM Timing High Register A 115 Offset 0x0140C Table 89 DDR2 SDRAM Timing Low Register nennen eren nennen 116 Offset 0x01428 Table 90 DDR2 SDRAM Timing High Register sese entrent neret 116 Offset 0x0147C Table 91 DDR SDRAM Address Control Register A 117 Offset 0x01410 Table 92 DDR SDRAM Open Pages Control Register A 117 Offset 0x01414 Table 93 DDR SDRAM Operation Register eese nnne nnne nere reete nente tnnt 118 Offset 0x01418 Table 94 DDR SDRAM Operation Control Register esses trennen nee nrennen 118 Offset 0x0142C Table 95 DDR SDRAM Mode Register ener rennen mene tne treten reete enne nnne 118 Offset 0x0141C Table 96 Extended DDR SDRAM Mode Register tret rennen nre treten rennen 120 Offset 0x01420 Table 97 DDR SDRAM Initialization Control Register ener rennen 121 Offset 0x01480 Table 98 DDR SDRAM Address Control Pads Calibration Register eee ee cece eee ceee eee eeee tae eeeteaeeeeeeeneeeaees 121 Offset 0x014C0 Table 99 DDR SDRAM Data Pads Calibration Register c cee cece eee e cece eee eeee cess sae eeeeeeaeeeaeesaaeseeeseeeaeseaeeeaees 122 Offset 0x014C4 Table 100 DDR2 SDRAM ODT Control Low Register 122 Offset 0x01494 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 67 Document Classification Proprietary June 25 2007 Preliminary Table 101 Table 102 Table 103 Table 10
49. VPT2P 0x72440 Table 394 p 287 Ethernet Port Status PS 0x72444 Table 395 p 287 Transmit Queue Command TQC 0x72448 Table 396 p 289 Reserved 0x72454 Maximum Transmit Unit MTU 0x72458 Table 397 p 290 Port Interrupt Cause IC 0x72460 Table 398 p 290 Port Interrupt Cause Extend ICE 0x72464 Table 399 p 292 Port Interrupt Mask PIM 0x72468 Table 400 p 294 Port Extend Interrupt Mask PEIM 0x7246C Table 401 p 294 Port Rx FIFO Urgent Threshold PRFUT 0x72470 Table 402 p 294 Port Tx FIFO Urgent Threshold PTFUT 0x72474 Table 403 p 294 Port Rx Minimal Frame Size PMFS 0x7247C Table 404 p 295 Port Rx Discard Frame Counter PxDFC 0x72484 Table 405 p 295 Port Overrun Frame Counter POFC 0x72488 Table 406 p 296 Port Internal Address Error EUIAE 0x72494 Table 407 p 296 Ethernet Current Receive Descriptor Pointers CRDP QO 0x7260C Table 408 p 296 Q1 0x7261C Q2 0x7262C Q3 0x7263C Q4 0x7264C Q5 0x7265C Q6 0x7266C Q7 0x7267C Receive Queue Command RQC 0x72680 Table 409 p 297 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 268 88F5182 marveL Open Source Community Programmer s User Guide Table 364 Ethernet Unit Global Registers Map Continued Description Offset Table Page Transmit Current Served Descriptor Pointer 0x72684 Read Only Table 410 p 298 Transmit C
50. XESMR2 0x60B78 XESMR3 0x60B7C XESMR 4 0x60B80 XESMRS5 0x60B84 XESMR6 0x60B88 XESMR7 0x60B8C Table 555 XOR Engine High Address Remap XEHARRYX sess rennes nnne nnns nnns 374 Offset XEHARRO 0x60B90 XEHARR1 0x60B94 XEHARR2 0x60B98 XEHARR3 0x60B9C Table 556 XOR Engine 0 1 Address Override Control XExAOCR essent 375 Offset XEOAOCR 0x60BAO0 XE1AOCR 0x60BA4 Table 557 XOR Engine 0 1 Destination Pointer GG ENDPPRO nennen nennen nenne 377 Offset XORO 0x60BBO XOR1 0x60BB4 Table 558 XOR Engine 0 1 Block Size XExBSR A 377 Offset XORO 0x60BCO0 XOR1 0x60BC4 Table 559 XOR Engine Timer Mode Control XETMCR retinere ter trennen 377 Offset OXG0BDO Table 560 XOR Engine Timer Mode Initial Value XETMIVR essent nnns 378 Offset OXG0BD4 Table 561 XOR Engine Timer Mode Current Value GETMCND ener nnns nen enne nnns 378 Offset OXG0BD8 Table 562 XOR Engine Initial Value Low XEIVRL rennen en rrren rennen 378 Offset OXGOBEO Table 563 XOR Engine Initial Value High XEIVRH esses net renretre terne tree trennen 379 Offset OXG0BE4 A 17 General Purpose Port Registers ueeeseeeeeesseeeseeeeeeee nennen nnn nn nnn nennt 380 Table 565 GPIO D ata Out Register Eeer ICD LR ele eee Ren Ren 380 Offset 0x10100 Table 566 GPIO Data Out Enable Control Register A 380 Offset 0x10104 Table 567 GPIO Blink Enable Register iniii aaran nae aiaa
51. ow e e e e 127 Empty 1024 127 CRPB 1024 7 2 2 EDMA Configuration The EDMA configuration is determined according to EDMA Configuration Register Table 311 p 226 The registers listed below may be changed only when the lt eEnEDMAs field in the EDMA Command Register Table 236 p 236 is cleared and the EDMA is disabled These registers must not be changed when eEnEDMA is set e nthe SATAHC Address Space Table 288 p 213 SATAHC Configuration Register Inthe EDMA Registers Map Table A 8 3 p 214 EDMA Configuration Register EDMA Command Delay Threshold Register e All registers in the Shadow Register Block Registers Map Table A 8 4 p 215 except that the host is allowed to change the HOB bit bit 7 in the ATA Device Control register offset 0x82120 while the EDMA is active All registers in the Basic DMA Registers Map Table A 8 5 p 216 All registers in the Serial ATA Registers Map field in the Table 217 p 217 FIS Interrupt Cause Register FIS Interrupt Mask Register 7 2 8 EDMA Data Structures 7 2 3 1 Command Request Queue The request queue is the interface that the CPU software uses to request data transactions between the system memory and the device The request queue has a length of 32 entries the lt eEDMAQueLens gt field in the EDMA Configuration Register Table 228 p 228 0 or 128 entries field lt eEDMAQueLen gt 1 The request q
52. 0 accepted in the last command NOTE When the EDMA is in NCQ mode ignore this field since the value of this field may reflect the status of other commands 7 Reserved Reserved This bit is always 0 15 8 cDevSts CRPB Device Status This field contains a copy of the device status register accepted in the last read of the register from the device Table 19 CRPB Time Stamp Register Offset 0x04 Bits Field Description 31 0 cTS CRPB TS When the command is completed the content of the EDMA Timer Register see Table 312 on page 230 is written into this field This data may be used to estimate the command execution time Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 32 88F5182 marveL Open Source Community Programmer s User Guide Section 8 Gigabit Ethernet Controller Interface The Gigabit Ethernet controller operates at 10 100 and 1000 Mbps It interfaces with the PHY via a MII GMII or RGMII interface The interface is also configurable as a proprietary 200 Mbps Marvell MII MMII interface For full details on the different pinout configurations see the applicable Gigabit Ethernet pin multiplexing sections and the Reset Configuration section in the 88F5182 88F5182 based Storage Networking Platforms Datasheet 8 1 Functional Description The Gigabit Ethernet p
53. 0 5 Copyright 2007 Marvell Page 265 Document Classification Proprietary June 25 2007 Preliminary Table 359 FIS DW2 Register Serial ATA Host Controller SATAHC Registers Offset Port 0 0x82378 Port 1 0x84378 Bits Name Type Description InitVal 31 0 RxFISDW2 RO This field contains DWORD 2 of the incoming non data FIS 0x0 Table 360 FIS DW3 Register Offset Port 0 0x8237C Port 1 0x8437C Bits Name Type Description InitVal 31 0 RxFISDW3 RO This field contains DWORD 3 of the incoming non data FIS 0x0 Table 361 FIS DW4 Register Offset Port 0 0x82380 Port 1 0x84380 Bits Name Type Description InitVal 31 0 RxFISDW4 RO This field contains DWORD 4 of the incoming non data FIS 0x0 Table 362 FIS DW5 Register 0x82384 Port 1 0x84384 Offset Port 0 Bits Name Type Description InitVal 31 0 RxFISDW5 RO This field contains DWORD 5 of the incoming non data FIS 0x0 Table 363 FIS DW6 Register 0x82388 Port 1 0x84388 Offset Port 0 Bits Name Type Description InitVal 31 0 RxFISDW6 RO This field contains DWORD 6 of the incoming non data FIS 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 266 88F5182 marveL Open Source Community Programmer s User Guide A 9 Gigabit Ethe
54. 00 Rev 0 5 Copyright 2007 Marvell Page 51 Document Classification Proprietary June 25 2007 Preliminary XOR Engine Theory of Operation Section 15 XOR Engine The XOR engine is a generic acceleration engine for storage applications that provides a low latency high throughput xor calculation capabilities enabling CPU xor calculation off loading in various RAID implementations In addition the XOR engine provides iSCSI CRC32C calculation DMA operation memory initialization and mem ory ECC errors cleanup operation support The XOR engine enables PC Server manufactures ROM Internal RAID Controllers and External RAID systems to speed up overall system performance XOR engine features Two separate channels for enabling concurrent operation e g concurrent XOR and iSCSI CRC32C calcula tions 1KB temporary result store queue per channel Arranged as 128 X 8B buffer e Support packing unpacking of unaligned data transfers e XOR calculation for up to eight data block sources Data block size up to 16 MB e Programmable maximum burst size on read and write Descriptor chain mechanism Hotinsertion of new descriptors to chain e iSCSI CRC32C calculation that is compliant with IPS iSCSI version 13 draft DMA operation Memory initialization support e Memory ECC cleanup support Write access protection of configuration registers 15 1 Theory of Operation XOR engine unit XEunit has five mai
55. 0x0 Table 302 SATAHC Main Interrupt Mask Register Offset 0x80024 Bits Field Type Description InitVal 31 0 Mask RW Mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of interrupt pins It does not affect the set ting of bits in the Cause register Table 303 Window0 Control Register Offset 0x80030 Bits Field Type Description InitVal 0 WinEn RW Window 0 Enable 0x1 0x0 Window is disabled 0x1 Window is enabled 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the target interface associated with this window 0x0 See Section 2 10 Default Address Map on page 14 NOTE Do not configure this field to the SDRAM Controller 15 8 Attr RW Specifies the target interface attributes associated with this window Ox0E See Section 2 10 Default Address Map on page 14 Doc No MV S400130 00 Rev 0 5 Page 223 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 303 Window0 Control Register Continued Offset 0x80030 Bits Field Type Description InitVal 31 16 Size RW Window Size OxOFFF Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the w
56. 0x72200 BA1 0x72208 BA2 0x72210 BA3 0x72218 BA4 0x72220 BA5 0x72228 Bits Field Type Description InitVal 3 0 Target RW Specifies the target resource associated with this window 0x0 See Address Decoding chapter for full details 7 4 Reserved RO Reserved 0x0 15 8 Attr RW Specifies target specific attributes depending on the target interface 0x0 See Address Decoding chapter for full details 31 16 Base RW Base address 0x0 Used together with the size register to set the address window size and location within the range of 4 GB space An address driven by one of the Ethernet SDMAs is considered as a window hit if address size base size Table 377 Size S Offset SRO 0x72204 SR1 0x7220C SR2 0x72214 SR3 0x7221C SR4 0x72224 SR5 0x7222C Bits Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 31 16 Size RW Window size 0x0 Used together with the size register to set the address window size and location within the range of 4 GB space Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window in 64 KB granularity for example a value of OxOOFF specifies 256x64k 16 MB An address driven by one of the Ethernet MACs is considered as a window hit if address size base size Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 275 Document Classific
57. 1 RW Reserved N A Must be set to 0 1543 Unused 1 RO Reserved N A 16 Pass 2 RW Determines whether to filter or accept for pointer index 2 N A 0 Reject filter frame 1 Accept frame 19 17 Queue 2 RW For pointer index 2 Determines the Queue number if Pass 2 1 N A Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 299 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 415 Destination Address Filter Special Multicast Table DFSMT Continued Offset 0x 73400 0x734FC NOTE Every register holds four entries A total of 64 registers appear in the table in consecutive order Bits Field Type Description InitVal 20 Reserved 2 RW Reserved N A Must be set to 0 23 21 Unused 2 RO Reserved N A 24 Pass 3 RW Determines whether to filter or accept for pointer index 3 N A 0 Reject filter frame 1 Accept frame 27 25 Queue 3 RW For pointer index 0 Determines the Queue number if Pass 3 1 N A 28 Reserved 3 RW Reserved N A Must be set to 0 31 29 Unused 3 RO Reserved N A Table 416 Destination Address Filter Other Multicast Table DFUT Offset 0x73500 0x735FC NOTE Every register holds four entries A total of 64 registers appear in this table in consecutive order Bits Field Type Description InitVal 0 Pass 0 RW Determines whether to filter or accept for pointer index
58. 25 2007 Preliminary Document Classification Proprietary Page 346 MARVELL E 88F5182 Open Source Community Programmer s User Guide Table 509 Line Status Register LSR Continued Offset UART 0 0x12014 UART 1 0x12114 Bits Field Type Description InitVal 31 8 Reserved RSVD Reserved 0x0 Table 510 Modem Status Register MSR Offset UART 0 0x12018 UART 1 0x12118 Bits Field Type Description InitVal 0 DCTS RW The DCTS bit records whether the modem control line UA0 CTSn 0x0 UA1 CTSn has changed since the last time the Marvell processor core read the MSR In Loopback mode DCTS reflects changes on Modem Control Regis ter MCR Register Table 508 p 345 bit 1 lt RTS gt 3 1 Reserved RSVD Reserved 4 CTS RSVD The CTS Modem Status bit lt CTS gt contains information on the cur rent state of the modem control line CTS is the compliment of UAO CTSn UA1 CTSn In Loopback Mode CTS is the same as Modem Control Register MCR Register Table 508 p 345 bit 1 lt RTS gt 31 5 Reserved RSVD Reserved Table 511 Scratch Pad Register SCR Offset UART 0 0x1201C UART 1 0x1211C Bits Field Type Description InitVal 7 0 Scratch RW The SCR register is an 8 bit read write register for programmers to use 0x0 as a temporary storage space 31 8 Reserved RSVD Reserved Doc No MV S400130 00 Rev 0 5 Page 347 Copyright
59. 26 of this register are cleared Activation procedure 1 Set this bit to trigger a hot reset cycle 2 Poll DLDown de assertion PCI Express Status Register bit 0 to ensure hot reset cycle is done 3 Clear this bit to exit to detect and re establish the PCI Express link NOTE This bit should be used only when working in Root Complex mode 25 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 142 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 136 PCI Express Control Register Continued Offset 0x41A00 Bits Field Type Description InitVal 26 ConfMstrLb RW Master Loopback 0x0 When set a loopback command is transmitted downstream causing the downstream device to transmit back the traffic that it receives This bit can be set only if bits 24 of this register and lt LnkDis gt in the PCI Express Link Control Status Register are cleared NOTE Use this bit only when working in Root Complex mode 27 ConfMstrDis RW Master Disable Scrambling Scrmb 0x0 When set a scrambling disable command is transmitted downstream caus ing the scrambling to be disabled on both sides of the link NOTE This should be programmed before the start of link initialization 28 Reserved RSVD Reserved 0x0 Must write 0 31 29 Reserved RSVD Reserved 0x0
60. 348 BIST DW2 Register Offset Port 0 0x8233C Port 1 0x8433C Bits Name Type Description InitVal 31 0 BistDw2 WO In BIST mode 0x0 Field lt BISTEn gt is set to 1 This field is the third DWORD of the BIST Activate FIS In PHY Loopback mode Field lt LBEnable gt is set to 1 This field is the low DWORD 31 0 of the user specified loopback pattern of the BIST Activate FIS Table 349 Serial ATA Interface Configuration Register Offset Port 0 0x82050 Port 1 0x84050 NOTE After any modification in this register the host must set bit 2 lt eAtaRst gt field in the EDMA Command Register Table 321 p 236 Bits Field Type Description InitVal 1 0 RefClkCnf RW PHY PLL Reference clock frequency 0x01 00 20 MHz 01 25 MHz 10 30 MHz 11 40 MHz NOTE Must be set to 01 3 2 RefClkDiv RW PHY PLL Reference clock divider 0x01 00 Divided by 1 01 Divided by 2 Used when PHY PLL Reference clock is 20 MHz or 25 MHz 10 Divided by 4 Used when PHY PLL Reference clock is 40 MHz 11 Divided by 3 Used when PHY PLL Reference clock is 30 MHz NOTE Must be set to 01 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 254 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 349 Serial ATA Interface Configuration Register Continued Offset Port 0 0x820
61. Channel 2 0x60808 Channel 3 0x6080C Channel IDMA Source Address Register sess neret nennen nenne 355 Offset Channel 0 0x60810 Channel 1 0x60814 Channel 2 0x60818 Channel 3 0x6081C Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 84 88F5182 marveL Open Source Community Programmer s User Guide Table 527 Table 528 Table 529 Table 530 Table 531 Table 532 Table 533 Table 534 Table 535 Table 536 Table 537 Table 538 Table 539 Table 540 A 16 Table 542 Table 543 Table 544 Table 545 Table 546 Table 547 Table 548 Table 549 Channel IDMA Destination Address Register c cece eeseeeeeeseeeeeeeeeeaeeeaeseaeseaeseaeseaeeeaeseaseeeeseeeeeeenaes 355 Offset Channel 0 0x60820 Channel 1 0x60824 Channel 2 0x60828 Channel 3 0x6082C Channel Next Descriptor Pointer Heiser 355 Offset Channel 0 0x60830 Channel 1 0x60834 Channel 2 0x60838 Channel 3 0x6083C Channel Current Descriptor Pointer Register nennt 355 Offset Channel 0 0x60870 Channel 1 0x60874 Channel 2 0x60878 Channel 3 0x6087C Base Address Hegister x 2 2 2 2 d i see iesi caevacedicersaa che EO F LITE er PCS PEE cadecdayeusviesionnatcaseats 356 Offset BARO 0x60A00 BAR1 0x60A08 BAR2 0x60A10 BAR3 0x60A18 BAR4 0x60A20 BAR5 0x60A28 BAR6 0x60A30 BAR7 0x60A38 EN Ee d
62. Copyright 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 262 PCI Interrupt Pin and Line Continued Offset Ox3C Bits Field Type Description InitVal 31 16 Reserved RES Read only 0x0 Table 263 PCI Power Management pin Each bit corresponds to different state bit 0 DO bit 1 D1 bit 2 D2 bit 3 D3 hot bit 4 D3 cold For example 001001 stands for supporting PCI_PMEn only on DO and D3 hot states NOTE Read only from PCI Offset 0x40 Bits Field Type Description InitVal 7 0 CapID RW Capability ID 0x1 NOTE Read only from PCI 15 8 NextPtr RW Next Item Pointer 0x48 NOTE Read only from PCI 18 16 PMCVer RW PCI Power Management Spec Revision 0x2 NOTE Read only from PCI 19 PMECIk RW PME Clock 0x1 Indicates that the PCI clock is required for the 88F5182 to assert PCI_PMEn NOTE Read only from PCI 20 Reserved RES Read only from PCI 0x0 21 DSI RW Device Specific Initialization 0x0 NOTE Read only from PCI 24 22 AuxCur RW Auxiliary Current Requirements 0x0 NOTE Read only from PCI 25 D1Sup RW D1 Power Management State Support 0x1 0 Not supported 1 Supported NOTE Read only from PCI 26 D2Sup RW D2 Power Management State Support 0x1 0 Not supported 1 Supported NOTE Read only from PCI 31 27 PMESup RW PCI_PMEn Signal Support Oxf Indicates in which power states the 88F5182 suppo
63. DLL Mode 0x1 Only relevant if lt En gt is enabled 0x0 Use PCLK as reference clock 0x1 Use inverted PCLK as reference clock 0x2 Reserved 0x3 Reserved 4 3 Err RO DLL Error indication DLL reach delay line boundary 0x0 0x0 No error 0x1 Delay line pointer at start and down count 0x2 Delay line pointer at end and up count 0x3 Reserved 8 5 RCnt RO Row Counter Current row number of the delay line Calculate the TAPs 0x0 number using row and column numbers Read only 12 9 CCnt RO Column Counter Current column number of the delay line Calculate 0x0 the TAPs number using row and column numbers Read only 1443 Init RW Delay line initial state 0x0 0x0 4 Taps from the beginning of delay line 0x1 8 Taps from the beginning of delay line 0x2 16 Taps from the beginning of delay line 0x3 50 Taps from the beginning of delay line 15 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 180 88F5182 marveL Open Source Community Programmer s User Guide Table 213 PCI DLL Control Continued Offset 0x31D20 Bits Field Type Description InitVal 16 CompEn RW Enable Pad Delay Compensation 0x0 0 Disable 1 Enable 19 17 Reserved RW Reserved 0x0 21 20 DLLDelicateTun RW DLL Delicate Tune Control e 0x1 30 22
64. E ERU EE 248 Offset Port 0 0x82340 Port 1 0x84340 lues EE 248 Offset Port 0 0x82308 Port 1 0x84308 LTM do ROg STO 249 Offset Port 0 0x8230C Port 1 0x8430C PHY Mode 3 Registen gc 250 Offset Port 0 0x82310 Port 1 0x84310 PHY Mode e e EE 251 Offset Port 0 0x82314 Port 1 0x84314 PHY Model Register ep e E eet dep elite ice ace e Ferr as e pne rr dx EY nie ebd eer cule dug 252 Offset Port 0 0x8232C Port 1 0x8432C s cu 252 Offset Port 0 0x82330 Port 1 0x84330 BIST Control ReGISter e M 253 Offset Port 0 0x82334 Port 1 0x84334 BIST DW T ICT 254 Offset Port 0 0x82338 Port 1 0x84338 ei EE RU TEE 254 Offset Port 0 0x8233C Port 1 0x8433C Serial ATA Interface Configuration Register eee eee eee ceee tees eens sees eaeeseeesaeeseeeteeseeeseeseaeseeeeeneeags 254 Offset Port 0 0x82050 Port 1 0x84050 Serial ATA Interface Control Register nennen nnne rennen nnne 256 Offset Port 0 0x82344 Port 1 0x84344 Serial ATA Interface Test Control Hegtster eee eee eee eee eee eeaeetaeeeeeeteeeeaeesaeseaeseaeesaeteeeeeeseeeneeeaes 258 Offset Port 0 0x82348 Port 1 0x84348 Serial ATA Interface Status Register 0 0 0 0 eseesseeseecseeeseeeseesseesaeesaeseaeesaeeeaeesaeeeaeesaeeeaseseeseenseeeeenesene
65. ECB mode Table 442 DES Key0 Low Register Offset Ox9DD48 Bits Field Type Description InitVal 31 0 DESKeyOLo RW Contains the low bits of the DES key or of the first key of the Triple DES keys 0x0 Table 443 DES Key0 High Register Offset 0x9DD4C Bits Field Type Description InitVal 31 0 DESKey0Hi RW Contains the high bits of the DES key or of the first key of the Triple DES keys 0x0 Table 444 DES Key1 Low Register Offset 0x9DD50 Bits Field Type Description InitVal 31 0 DESKey1Lo RW Contains the low bits of the second key of the Triple DES keys This register 0x0 is ignored in DES mode Table 445 DES Key1 High Register Offset Ox9DD54 Bits Field Type Description InitVal 31 0 DESKey1Hi RW Contains the high bits of the second key of the Triple DES keys This register 0x0 is ignored in DES mode Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 317 Document Classification Proprietary June 25 2007 Preliminary Table 446 DES Key2 Low Register Offset Ox9DD60 Cryptographic Engine and Security Accelerator Registers Bits Field Type Description InitVal 31 0 DESKey2Lo RW Contains the low bits of the third key of the Triple DES keys This register is 0x0 ignored in DES mode Table 447 DES Key2 High Register Offset Ox9DD64 Bits
66. Enable Queue 0x0 Writing 1 enables the queue The transmit DMA will fetch the first descriptor programmed to the FDP register for the queue and starts the transmit pro cess Writing 1 to the ENQ bit resets the matching DISQ bit Writing 1 to the ENQ bit of a DMA that is already in enable state has not effect Writing 0 to the ENQ bit has no effect When transmit DMA encounters queue end either by a null terminated descriptor pointer or a descriptor with a parity error or a CPU owned descrip tor The DMA will clear the ENQ bit for that queue Thus reading these bits reports the active enable status for each queue NOTE The ENQ bits will be cleared on link down After link is up the CPU has to restart the DMA set ENQ bits 7 1 Reserved RW Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 289 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 396 Transmit Queue Command TQC Continued Offset 0x72448 Bits Field Type Description InitVal 8 DISQ RW Disable Queue 0x0 Writing 1 disables the queue The transmit DMA will stop the transmit pro cess from this queue on next packet boundary Writing 1 to the DISQ bit resets the matching ENQ bit when the DMA is fin ished with the queue and if the current active queue has been disabled Writing 0 to the DISQ bit has no effect When transmit DMA encounters queue end either by
67. Field Type Description InitVal 31 0 DESKey2Hi RW Contains the high bits of the third key of the Triple DES keys This register is 0x0 ignored in DES mode Table 448 DES Command Register Offset Ox9DD58 Bits Field Type Description InitVal 0 Direction RW This bit controls the direction of the operation encryption or decryption 0x0 0 Encryption 1 Decryption 1 Algorithm RW This bit controls whether the DES or Triple DES algorithm is used 0x0 0 DES 1 Triple DES 3DES 2 TripleDESMode RW This bit controls the Triple DES encryption decryption mode 0x0 0 EEE 1 EDE 3 DESMode RW This bit controls the DEC encryption decryption mode 0x0 0 ECB 1 CBC 4 DataByteSwap RW This bit controls whether data byte swap is activated on input 0x0 0 No byte swap 1 Byte swap 5 Reserved RES Reserved 0x0 6 IVByteSwap RW This bit controls whether initial value byte swap is activated 0x0 0 No byte swap 1 Byte swap 7 Reserved RES Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 318 88F5182 marveL Open Source Community Programmer s User Guide Table 448 DES Command Register Continued Offset Ox9DD58 Bits Field Type Description InitVal 8 OutByteSwap RES This bit controls whether byte swap is activated for output 0x0 0 N
68. Intel Lucent Microsoft NEC Philips e Enhanced Host Controller Interface Specification for Universal Serial Bus Revision 0 95 November 2000 Intel Corporation e USB HS High Speed Controller Core reference RFC 1321 The MD5 Message Digest Algorithm FIBS 180 1 Secure Hash Standard e FIBS 46 2 Data Encryption Standard e FIBS 81 DES Modes of Operation e RFC 2104 HMAC Keyed Hashing for Message Authentication e RFC 2405 The ESP DES CBC Cipher Algorithm With Explicit IV e RFC 1851 The ESP Triple DES Transform e FIBS draft Advanced Encryption Standard Rijndeal Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 9 Document Classification Proprietary June 25 2007 Preliminary Preface Document Conventions Document Conventions This document has the following name and usage conventions Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related signals The first number in the range indicates the most significant bit MSb and the last number indicates the least significant bit LSb Example DB AD 81 0 Active Low Signalsn A n symbol at the end of a signal name indicates that the signal s active state occurs when voltage is low Example INTn State Names State names are indicated in italic font Example inkfail Register Naming Register field names are enclosed in angle brackets Conventions Example lt Dw
69. KByte 1 1024 1024 KByte 2 2048 2048 KByte 3 4093 4096 KByte 31 22 Reserved RSVD Reserved 0x0 A 6 2 PCI Express Configuration Cycles Generation Registers Table 111 PCI Express Configuration Address Register Offset 0x418F8 NOTE Bits Field Type Description InitVal 1 0 Reserved RSVD Reserved 0x0 7 2 RegNum RW Register Number 0x0 10 8 FunctNum RW Function Number 0x0 15 11 DevNum RW Device Number 0x0 23 16 BusNum RW Bus Number 0x0 27 24 ExtRegNum RW Extended Register Number 0x0 30 28 Reserved RSVD Reserved 0x0 31 ConfigEn RW Configuration Enable Bit 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 130 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 112 PCI Express Configuration Data Register Offset 0x418FC NOTE Bits Field Type Description InitVal 31 0 ConfigData RW Write access to this register generates a corresponding Configuration 0x0 TLP on the PCI Express port or an access to the PCI Express port config uration header registers A 6 3 PCI Express Interrupt Registers Table 113 PCI Express Interrupt Cause Offset 0x41900 NOTE AN bits except bits 27 24 are Read Write Clear only A cause bit sets upon an event occurrence A write of 0 clears the bit A write of 1 has no affect Bits 24 27 are set and cleared upon rec
70. Map 215 Table 292 Basic DMA Register Map irssi iiinn a E E aTi 216 Table 293 Serial ATA Interface Registers Map 217 Table 364 Ethernet Unit Global Registers Map 267 Table 419 USB 2 0 Controller Register Map Offsets Port0 0x50000 0x502FF Port OsAOO0OO ONAO2EF 305 Table 420 USB 2 0 Bridge Register Map Port0 0x50300 0x503FF Port1 0xA0300 0xAO3FF 306 Table 421 USB 2 0 PHY Register Map Pom 0x50400 Port1 DxAO200 307 Table 435 Cryptographic Engine and Security Accelerator Register Map 314 Table 491 TWSI Interface Register Map 335 Table 499 UART Interface Registers Map 340 Table 512 Device Registers Map EE 348 Table 521 IDMA Descriptor Register Map 353 Table 522 IDMA Address Decoding Register Map nennen 353 Table 523 IDMA Control Register Map 354 Table 524 IDMA Interrupt Register Map 354 Table 541 XOR Engine Register Map 364 Table 564 GPIO Registers Map 380 Table 573 MPP Register Map itte hi Pe troie PRD FRI E eene Se ERE p En nasa e epe Esei 384 EE e oA B Revision HIStory EE 388 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 7 Document Classification Proprietary June 25 2007 Preliminary List of Figures List of Figures Figure 1 88F5182 Interface Block Diagram sese nee 11 Figure 2 SATAHC Block Diagram Figure 3 Command Request Queue 32 Entries nennen 22 Figure 4 Command
71. Near end Loopback Pass 0x0 This bit indicates if the Near end Loopback test passed 0 Fail 1 Pass 18 DMAAct RO DMA Active 0x0 This bit indicates if the transport DMA FSM is active 0 Idle 1 Active 19 PIOAct RO PIO Active 0x0 This bit indicates if the transport PIO FSM is active 0 Idle 1 Active 20 RxHdAct RO Rx Header Active 0x0 This bit indicates if the transport Rx Header FSM is active 0 Idle 1 Active 21 TxHdAct RO Tx Header Active 0x0 This bit indicates if the transport Tx Header FSM is active 0 Idle 1 Active Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 260 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 352 Serial ATA Interface Status Register Continued Offset Port 0 0x8234C Port 1 0x8434C Bits Field Type Description InitVal 22 Plugin RO Cable plug in indicator and device presence indication 0x0 This signal becomes invalid when the core is in SATA Power Management modes This indicator is also reflected in the lt X gt field in the SError Register Table 338 p 248 0 Device presence not detected 1 Device presence detected 23 LinkDown RO SATA communication is not ready Primitives or FISs 0x1 are not able to be transmitted or received 0 Link is ready 1 Link is not ready 28 24 TransFsmSts RO Transport Layer FSM status 0x0 0x00 Transport layer is idle 0x00 0x1F
72. No MV S400130 00 Rev 0 5 Page 173 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary Table 191 DevCSn 0 BAR Size Offset 0x30C10 PCI Interface Registers Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x07FFF000 Table 192 DevCSn 1 BAR Size Offset Ox30D10 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x07FFF000 Table 193 DevCSn 2 BAR Size Offset 0x30D18 Table 194 Boot CSn BAR Size Offset 0x30D14 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x07FFFO0O Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x07FFFO0O Table 195 P2P Mem0 BAR Size Offset 0x30D1C Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x1FFFFO000 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 174 88F5182 marveL Open Source Community Programmer s User Guide Table 196 P2P I O BAR Size Offset 0x30D24 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 BAR Size RW 0x0000F000 Table 197 Expansion ROM BAR Size Offset Ox30D2C
73. O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Device Controller Registers A 14 Device Controller Registers Table 512 Device Registers Map Register Offset Table Page Device BankO Parameters Register 0x1045C Table 513 p 348 Device Bank1 Parameters Register 0x10460 Table 514 p 349 Device Bank2 Parameters Register 0x10464 Table 515 p 350 Boot Device Parameters Register 0x1046C Table 516 p 350 NAND Flash Control Register 0x104E80x104 Table 517 p 350 E8 Device Interface Control 0x104C0 Table 518 p 351 Device Interrupt Cause 0x104D0 Table 519 p 352 Device Interrupt Mask Register 0x104D4 Table 520 p 352 Table 513 Device Bank Parameters Register Offset 0x1045C Bits Field Type Description InitVal 2 0 TurnOff RW The number of cycles in a read access between the negation of DEV_CEn 0x7 to a new Device bus cycle Minimal value 0x2 NOTE This field uses an additional bit in field lt TurnOffExt gt bit 22 6 3 Acc2First RW Defines the number of cycles in a read access between the negation of OxF DEV_ALE 0 and the cycle containing the first data sampled by the 88F5182 Number of cycles lt Acc2First gt 3 Minimal value 0x NOTE This field uses an additional bit in field lt Acc2FirstExt gt bit 23 10 7 Acc2Next RW The number of cycles in a burst read access between the cycle containing
74. Offset 0x20 Bits Field Type Description InitVal 0 lOSpace RO UO Space Indicator 0x1 11 1 Reserved RO Read only 0x0 31 12 Various RW Same as CSn 0 Base Address Low 0xC0000 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 211 Document Classification Proprietary June 25 2007 Preliminary Table 287 PCI Internal Registers UO Mapped Base Address PCI Interface Registers Copyright O 2007 Marvell June 25 2007 Preliminary Offset 0x24 Bits Field Type Description InitVal 0 lOSpace RO UO Space Indicator 0x1 11 1 Reserved RO Read only 0x0 31 12 Various RW Same as CSn 0 Base Address 0xD0000 Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 212 88F5182 marveL Open Source Community Programmer s User Guide A 8 Serial ATA Host Controller SATAHC Registers A 8 1 SATAHC Address Space The SATAHC contains two SATA ports In the address space of the SATAHC three regions are allocated one region per port and an additional region for the common registers See Figure 16 and Table 288 Reading from non existing address space results in reading a data of 0 Figure 16 SATAHC Address Space SATAHC Arbiter Registers EDMA Port 1 EDMA Port 0 Registers Registers Table 288 SATAHC Address Space Offset Target 80000 81FFF SATAHC Arbiter Registers 83000 83FFF ED
75. PCI Express BIST Header Type and Cache Line Size Hegieier eee cece eeeeeee tee eeeeteeteeeteneeaees 149 Offset 0x4000C Table 146 PCI Express BARO Internal Register esssssssssssssseseeeeneeee tenete nennen nennen nennen 150 Offset 0x40010 Table 147 PCI Express BARO Internal High Hegtster A 150 Offset 0x40014 Table 148 PCI Ee Ae e EE 150 Offset 0x40018 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 69 Document Classification Proprietary June 25 2007 Preliminary List of Registers Table 149 PCI Express BAR1 High Register sess rennen nrenrenren rentre n nenne 151 Offset 0x4001C Table 150 PCI Express BAR2 Register eene enne eene eren 151 Offset 0x40020 Table 151 PCI Express BAR2 High Register ren rennen renreenren restet nennt 152 Offset 0x40024 Table 152 PCI Express Subsystem Device and Vendor ID 152 Offset 0x4002C Table 153 PCI Express Expansion ROM BAR Heotster nennen nennt 152 Offset 0x40030 Table 154 PCI Express Capability List Pointer Register AA 153 Offset 0x40034 Table 155 PCI Express Interrupt Pin and Line Register rennen 153 Offset 0x4003C Table 156 PCI Express Power Management Capability Header Register sese 153 Offset 0x40040 Table 157 PCI Express Power Management Control and Status Register sssssseeeeen 154 Offset 0x40044 Table 158 PCI Express MSI Message Control Regi
76. PCI Express Command and Status Register is set 1 NFErrRepEn RW Non Fatal Error Reporting Enable 0x0 0 Disabled ERR_NONFATAL error messages are masked Status bit is not masked 1 Enabled ERR_NONFATAL error messages enabled In Root Complex mode reporting of errors is internal to status registers only An external error message must not be generated therefore always write 0x0 NOTE ERR NONFATAL error messages are still enabled when this field is 0 if the lt SErrEn gt bit in Table 143 PCI Express Command and Status Register is set Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 158 88F5182 marveL Open Source Community Programmer s User Guide Table 164 PCI Express Device Control Status Register Continued Offset 0x40068 Configuration 0x68 Bits Field Type Description InitVal 2 FErrRepEn RW Fatal Error Reporting Enable 0x0 0 Disabled ERR FATAL error messages are masked Status bit is still affected 1 Enabled ERR FATAL error messages enabled In Root Complex mode reporting of errors is internal to status registers only An external error message must not be generated therefore always write 0x0 NOTE ERR_FATAL error messages are still enabled when this field is O if the lt SErrEn gt bit in Table 143 PCI Express Command and Status Register is set 3 URRepE
77. PCI Express Window5 Base Heglster rennen rennen nennen 140 Offset 0x41884 Table 132 PCI Express Window5 Remap Register A 140 Offset 0x4188C Table 133 PCI Express Default Window Control Register essent 141 Offset 0x418B0 Table 134 PCI Express Expansion ROM Window Control Register eccecece eee ceeeeee test eeeeeeeeteeeseeeteeeeeeeeneeeaees 141 Offset 0x418C0 Table 135 PCI Express Expansion ROM Window Remap Register essessessesserserrerneriernsrnsrnsrnsrnernsrnnrnsrnnrnnrnernennnna 141 Offset 0x418C4 Table 136 PCI Express Control Register eicere ritieni tentent ite rb tea Fes tk ded one Ee ER date ENEE 142 Offset 0x41A00 Table 137 PCI Express Status EE 143 Offset 0x41A04 Table 138 PCI Express Completion Timeout Heite 144 Offset 0x41A10 Table 139 PCI Express Flow Control Register eeseseeesseeeeeeeeenee nne rentre enne 145 Offset 0x41A20 Table 140 PCI Express Acknowledge Timers 1X Register 145 Offset 0x41A40 Table 141 PCI Express TL Control Register siirretiin kaaa nne trennen rentre enne tenen 146 Offset 0x41ABO Table 142 PCI Express Device and Vendor ID Heoieter AA 146 Offset 0x40000 Table 143 PCI Express Command and Status Register enne 146 Offset 0x40004 Table 144 PCI Express Class Code and Revision ID Register eee ee cece eeee eee teee eens sees eaeeseeseaeeeeeseaeeaeseaeeeaees 149 Offset 0x40008 Table 145
78. Prefetch Water Mark 2 0x0 Defines at which point the 88F5182 PCI slave prefetches the next buffer from memory 0 Fetches next buffer after driving one 64 bit word on the bus 1 Fetches after driving two 64 bit words on the bus and so on 9 8 WrMBurst RW Write Max Burst 0x0 Specifies the maximum burst size for a single write transaction between a PCI slave and the other interfaces 00 32 bytes 01 64 bytes 10 128 bytes 11 Reserved 10 Aggr RW Aggressive Prefetch Enable 0x0 If set to 1 RdSize setting is ignored and the 88F5182 PCI slave prefetches read data as long as the requester does not DISCONNECT 11 PciOR RW PCI Ordering required 0x0 0 Hardware does not support PCI ordering 1 Hardware enforced PCI ordering 31 12 Size RW PCI access window size 0x0 Must be programmed from LSB to MSB as sequence of 1s followed by sequence of Os For example a OxOOFFF size register value represents a window size of 16 MB Table 225 PCI Access Control Base 1 Low Offset Ox31E10 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 Low RES 0x0 Table 226 PCI Access Control Base 1 High Offset 0x31E14 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 High 0x0 Doc No MV S400130 00 Rev 0 5 Page 189 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary
79. Proprietary June 25 2007 Preliminary Local to System Bridge Registers Table 42 Window2 Control Register Offset 0x20020 Bits Field Type Description InitVal 0 win en RW Window2 Enable 0x1 See the Window0 Control Register Table 34 p 91 3 1 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x4 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface 0x51 See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size 0x0 See the Window0 Control Register Table 34 p 91 Table 43 Window2 Base Register Offset 0x20024 NOTE Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxC000 See the Window0 Base Register Table 44 Window3 Control Register Offset 0x20030 Bits Field Type Description InitVal 0 win en RW Window3 Enable 0x1 See the Window0 Control Register Table 34 p 91 3 1 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x3 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface 0x51 See the Window0 Control Register Table 34 p 91 Copyright 2007 Marvell June 25 2007 Preliminary Doc
80. RW M ODTT0 control for write transactions 0x0 Bit 0 if set to 1 M_ODT 0 is asserted during write to DDR SDRAM bank 0 Bit 1 if set to 1 M ODTT O0 is asserted during write to DDR SDRAM bank 1 Bit 2 if set to 1 M ODTT O0 is asserted during write to DDR SDRAM bank 2 Bit 3 if set to 1 M ODTT O0 is asserted during write to DDR SDRAM bank 3 Refer to the Design Considerations for this product 23 20 ODT1Wr RW M_ODT 1 control for write transactions 0x0 Same as lt ODTOWrs gt 27 24 ODT2Wr RW M ODTT2 control for write transactions 0x0 Same as lt ODTOWrs gt 31 28 ODT3Wr RW M ODTTS control for write transactions 0x0 Same as lt ODTOWrs gt Table 101 DDR2 SDRAM ODT Control High Register Offset 0x01498 Bits Field Type Description InitVal 1 0 ODTOEn RW M ODT 0 Enable 0x0 0x0 0x2 M ODT 0 assertion de assertion is controlled by DDR2 SDRAM ODT Control Low register 0x1 2 M_ODT 0 is never active 0x3 M_ODT 0 is always active Refer to the Design Considerations for this product 3 2 ODT1En RW M_ODT 1 Enable 0x0 Same as lt ODTOEn gt 5 4 ODT2En RW M_ODT 2 Enable 0x0 Same as lt ODTOEn gt 7 6 ODT3En RW M_ODT 3 Enable 0x0 Same as lt ODTOEn gt Doc No MV S400130 00 Rev 0 5 Page 123 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary DDR SDRAM Controller Registers Table 101 DDR2 SDRAM ODT Control High Reg
81. Register 0x01508 Table 79 p 110 CS 1 n Size Register 0x0150C Table 80 p 111 CS 2 n Base Address Register 0x01510 Table 81 p 111 CS 2 n Size Register 0x01514 Table 82 p 111 CS 3 n Base Address Register 0x01518 Table 83 p 112 CS 3 n Size Register 0x0151C Table 84 p 112 DDR SDRAM Control Registers DDR SDRAM Configuration Register 0x01400 Table 85 p 112 DDR SDRAM Control Register 0x01404 Table 86 p 113 DDR SDRAM Timing Low Register 0x01408 Table 87 p 114 DDR SDRAM Timing High Register 0x0140C Table 88 p 115 DDR2 SDRAM Timing Low Register 0x01428 Table 89 p 116 DDR2 SDRAM Timing High Register 0x0147C Table 90 p 116 DDR SDRAM Address Control Register 0x01410 Table 91 p 117 DDR SDRAM Open Pages Control Register 0x01414 Table 92 p 117 DDR SDRAM Operation Register 0x01418 Table 93 p 118 DDR SDRAM Operation Control Register 0x0142C Table 94 p 118 DDR SDRAM Mode Register 0x0141C Table 95 p 118 Extended DDR SDRAM Mode Register 0x01420 Table 96 p 120 DDR SDRAM Initialization Control Register 0x01480 Table 97 p 121 DDR SDRAM Address Control Pads Calibration 0x014C0 Table 98 p 121 Register DDR SDRAM Data Pads Calibration Register 0x014C4 Table 99 p 122 DDR2 SDRAM ODT Control Low Register 0x01494 Table 100 p 122 DDR2 SDRAM ODT Control High Register 0x01498 Table 101 p 123 DDR2 SDRAM ODT Control Register 0x0149C Table 102 p 124 DDR SDRAM Interface Mbus Control Low Register 0x01430 Table 103 p 125 DDR SDRAM Interface Mbus Con
82. Response Queue 32 Entree 23 Figure 5 Command Request Queue 128 Entree 23 Figure 6 Command Response Queue 128 Entries sessi 24 Figure 7 TWSI Examples ote eege Ee 41 Figure 8 Device Block Diagram Example sse nne nnne 48 Figure 9 Address Multiplexing E 49 Figure 10 Mask ALE during NAND Flash Read Data Phase AAA 49 Figure 11 Generate Dedicated NAND Flash WE Gong 49 Figure 12 Generate CE Covers All NAND Flash Transaction nennen 49 Fig re KEE Ee e 51 Figure 14 XOR Descriptor Format iiiter teet Lee reed e Leda do do ER de tnde dod 54 Figure 15 88F5182 Interrupt Controller Gcheme ennemi 61 Figure 16 SATAHC Address Space ente e ce b ae enced stele ieee e d de qe auos 213 Copyright O 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 8 88F5182 marveL Open Source Community Programmer s User Guide Preface About This Document This document provides a product overview interface descriptions and registers for the 88F5182 Related Documents e ARM Architect Reference Manual Second Edition e AMBA Specification Rev 2 0 e PCI Local Bus Specification Revision 2 2 e PCI Express Base Specification Revision 1 0a Serial ATA Il Phase 1 0 Specification Extension to SATA I Specification Universal Serial Bus Specification Revision 2 0 April 2000 Compaq Hewlett Packard
83. SDRAM Address Control Register Offset 0x01410 Bits Field Type Description InitVal 3 0 Reserved RO Reserved 0x0 5 4 DSize RW 0x0 128 Mbits 0x1 NOTE 128 Mbits DDR SDRAM is relevant only to DDR1 0x1 256 Mbits 0x2 512 Mbits 0x3 Reserved 31 6 Reserved RO Reserved 0x0 Table 92 DDR SDRAM Open Pages Control Register Offset 0x01414 Bits Field Type Description InitVal 0 OPEn RW Open Page Enable 0x0 0 The DDR Controller keeps the corresponding bank page open whenever it can 1 The DDR Controller always closes the page at the end of the transaction 31 1 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 117 Document Classification Proprietary June 25 2007 Preliminary DDR SDRAM Controller Registers Table 93 DDR SDRAM Operation Register Offset 0x01418 Bits Field Type Description InitVal 3 0 Cmd SC DDR SDRAM Mode Select 0x0 0x0 Normal SDRAM Mode 0x1 Precharge all banks command 0x2 Refresh all banks command 0x3 Mode Register Set MRS command 0x4 Extended Mode Register Set EMRS command 0x5 NOP command 0x6 Reserved 0x7 Enter self refresh 0x8 EMRS2 command DDR2 only 0x9 EMRS3 command DDR2 only OxA OxF Reserved Setting this field results in the DDR Controller execution of the required command to the DDR SDRAM Then the DDR Controller resets this field to the defa
84. SR3 0x7221C SR4 0x72224 SR5 0x7222C Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 78 88F5182 marveL Open Source Community Programmer s User Guide Table 378 High Address Remap HA nette rre ERR aoaia a EIER NESE Aap Eae APGE ETE E EErEE 276 Offset HARRO 0x72280 HARR1 0x72284 HARR2 0x72288 HARR3 0x7228C Table 379 Base Address Enable GARE NENNEN 276 Offset 0x72290 Table 380 Ethernet Port Access Protect EPAP AE 276 Offset 0x72294 Table 381 Port Configuration PXO re H 277 Offset 0x72400 Table 382 Port Configuration Extend DCH 278 Offset 0x72404 Table 383 MII Serial Parameters ine ia a I R4 aa aada ERIS EE RS E Eaa E aiia 279 Offset 0x72408 Table 384 EIER a 280 Offset 0x7240C Table 385 VLAN Ether Type EVEANE orit eroapen aA i a aaaea EAS a ENKARA E aE cache 280 Offset 0x72410 Table 386 MAC Address Low MACAL sese nete net nenne trennen ree tntt entre tnnen 280 Offset 0x72414 Table 387 MAC Address High MACAH A 280 Offset 0x72418 Table 388 SDMA Configuration DC 281 Offset 0x7241C Table 389 IP Differentiated Services CodePoint 0 to Priority DSCPO sese 282 Offset 0x72420 Table 390 IP Differentiated Services CodePoint 1 to Priority DCH 283 Offset 0x72424 Table 391 IP Differentiated Services C
85. Source Community Programmer s User Guide Table 355 FIS Interrupt Cause Register Continued Offset Port 0 0x82364 Port 1 0x84364 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Name Type Description InitVal 31 26 Reserved RO Reserved 0x0 Table 356 FIS Interrupt Mask Register Offset Port 0 0x82368 Port 1 0x84368 Bits Name Type Description InitVal 25 0 FISIntMask RW FIS Interrupt Error Mask Bits 0x0000A Each of these bits mask the corresponding bit in the FIS Interrupt Cause 00 Register Table 355 p 263 If a bit in the FIS Interrupt Cause Register is set and the corresponding bit in this register is set to 1 the eTranslInt field in the EDMA Interrupt Error Cause Register Table 313 p 231 in EDMA Interrupt Error Cause Register Table 313 p 230 is also set to 1 0 Mask 1 Do not mask 31 26 Reserved RO Reserved 0x0 Table 357 FIS DWO Register Offset Port 0 0x82370 Port 1 0x84370 Bits Name Type Description InitVal 31 0 RxFISDWO RO This field contains DWORD 0 of the incoming data or non data FIS 0x0 Table 358 FIS DW1 Register Offset Port 0 0x82374 Port 1 0x84374 Bits Name Type Description InitVal 31 0 RxFISDW1 RO This field contains DWORD 1 of the incoming non data FIS 0x0 Doc No MV S400130 00 Rev
86. Specifies the target interface attributes associated with this window 0x0 See Section 2 10 Default Address Map on page 14 31 16 Size RW Window Size 0x0 Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window e g a value of OxOOFF specifies 256x64k 16 MB Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 310 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 431 USB 2 0 Window2 Base Register Offset Port0 0x50344 Port1 0xA0344 Bits Field Type Function InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x0 Used with the size field to set the address window size and location Corresponds to transaction address 31 16 Table 432 USB 2 0 Window3 Control Register 0x50350 Port1 0xA0350 Offset Port Bits Field Type Function InitVal 0 win_en RW Window0 Enable 0x0 0 Window is disabled 1 Window is enabled 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the target interface associated with this window 0x0 See Section 2 10 Default Address Map on page 14 15 8 Attr RW Specifies the target interface attributes associated with this window 0x0 See Section 2 10 Def
87. Subsystem Device and Vendor ID Offset 0x4002C Configuration 0x2C Bits Field Type Description InitVal 15 0 SSVenID RO Subsystem Manufacturer ID Number 0x11AB_ The default is the Marvell Vendor ID 31 16 SSDevID RO Subsystem Device ID Number 0x11AB The default is the Marvell Vendor ID Table 153 PCI Express Expansion ROM BAR Register Offset 0x40030 Configuration 0x30 NOTE If expansion ROM is not enabled via the ExpROMEn bit 0 in Table 110 PCI Express Expansion ROM BAR Control Register this register is Reserved Bits Field Type Description InitVal 0 RomEn RW Expansion ROM Enable 0x0 0 Disabled 1 Enabled NOTE 88F5182 expansion ROM address space is enabled only if both this bit RomEn and lt MemEn gt in the PCI Express Command and Status Register Table 143 p 146 are set 18 1 Reserved RSVD Reserved 0x0 21 19 RomBase RSVD These bits are defined according to field lt ExpROMSz gt in the PCI Express Reserved 0x0 Expansion ROM BAR Control Register Table 110 p 130 When ROM Size is 0 512KByteSpace Bits 21 19 are used as Expansion ROM Base Address 21 19 1 1MByteSpace Bits 21 20 are used as Expansion ROM Base Address 21 20 and bit 19 is reserved 2 2MByteSpace Bits 21 used as Expansion ROM Base Address 21 and bits 20 19 are reserved 3 4MByteSpace Bits 21 19 are reserved 31 22 RomBase RW Expansion ROM Base Address 31 2
88. Table 119 p 136 PCI Express Window1 Remap Register 0x4183C Table 120 p 136 PCI Express Window2 Control Register 0x41840 Table 121 p 137 PCI Express Window2 Base Register 0x41844 Table 122 p 137 PCI Express Window2 Remap Register 0x4184C Table 123 p 137 PCI Express Window3 Control Register 0x41850 Table 124 p 138 PCI Express Window3 Base Register 0x41854 Table 125 p 138 PCI Express Window3 Remap Register 0x4185C Table 126 p 138 PCI Express Window4 Control Register 0x41860 Table 127 p 139 PCI Express Window4 Base Register 0x41864 Table 128 p 139 PCI Express Window4 Remap Register 0x4186C Table 129 p 139 PCI Express Window5 Control Register 0x41880 Table 130 p 140 PCI Express Window5 Base Register 0x41884 Table 131 p 140 PCI Express Window5 Remap Register 0x4188C Table 132 p 140 PCI Express Default Window Control Register 0x418B0 Table 133 p 141 PCI Express Expansion ROM Window Control Register 0x418C0 Table 134 p 141 PCI Express Expansion ROM Window Remap Register 0x418C4 Table 135 p 141 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 127 Document Classification Proprietary June 25 2007 Preliminary Table 107 PCI Express Register Map Table Continued PCI Express Interface Registers Register Name Offset Table amp Page PCI Express Control and Status Registers PCI Expres
89. Table 142 PCI Express Device and Vendor ID Register Offset 0x40000 Configuration 0x0 Bits Field Type Description InitVal 15 0 VenID RO Vendor ID 0x11AB This field identifies Marvell as the Vendor of the device 31 16 DevID RO Device ID 0x5182 Table 143 PCI Express Command and Status Register Offset 0x40004 Configuration 0x4 Bits Field Type Description InitVal 0 IOEn RW IO Space Enable 0x0 The IO space is not enabled therefore this bit is not functional 1 MemEn RW Memory Space Enable 0x0 Controls 88F5182 response to PCI Express memory accesses 0 Disable All Memory accesses from PCI Express are completed as Unsupported Requests 1 Enable Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 146 88F5182 marveL Open Source Community Programmer s User Guide Table 143 PCI Express Command and Status Register Continued Offset 0x40004 Configuration 0x4 Bits Field Type Description InitVal 2 MasEn RW Master Enable 0x0 This bit controls the ability of the 88F5182 to act as a master on the PCI Express port When set to 0 no memory or I O read write request packets are generated to PCI Express 0 Disable Neither memory nor I O requests are transmitted to the PCI E port 1 Enable Memory and I O requests are transmitted to the PCI E port NOTE Me
90. Table 423 USB 2 0 Bridge Interrupt Cause Register Continued 0x50310 Port1 0xA0310 Offset Por Bit Field Type Description InitVal 3 1 Reserved RWC Reserved 0x0 31 4 Reserved RO Reserved 0x0 1 All cause bits are clear only They are set to 1 upon an interrupt event and cleared when the software writes a value of 0 Writing 1 has no affect Table 424 USB 2 0 Bridge Interrupt Mask Register Offset Port0 0x50314 Port1 0xA0314 Bit Field Type Description InitVal 0 Mask RW If set to 1 the related interrupt is enabled 0x0 3 1 Reserved RW Reserved 0x0 31 4 Reserved RES Reserved 0x0 Table 425 USB 2 0 Bridge Error Address Register Offset Port0 0x5031C Port1 0xA031C Bit Field Type Description InitVal 31 0 ErrAddr RO Error Address 0x0 Latched upon any of the address decoding errors address miss multiple hit Once the address is latched no new address is latched until SW reads it Read access to USB 2 0 Bridge Error Address Register Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 308 MARVELL A 10 3 e 88F5182 E Open Source Community Programmer s User Guide USB 2 0 Bridge Address Decoding Registers Table 426 USB 2 0 Window0 Control Register 0x50320 Port1 0xA0320 Offset Port0
91. The OE PE and FE bits are reset when a read on the Line Control Register LCR Register Table 507 p 344 is per formed 4 Bl ROC The Bl bit is set whenever the serial input sin is held in a logic 0 state 0x0 for longer than the sum of start time data bits parity stop bits In the FIFO mode the BI indication is carried through the FIFO and is revealed when the character is at the top of the FIFO Reading the Line Control Register LCR Register Table 507 p 344 clears the Bl 5 THRE RO Transmit Holding If the lt THRE gt bit is set the device can accept a new 0x1 character for transmission If interrupts are enabled it can cause an inter rupt to occur when data from the Transmit Holding Register THR Register Table 501 p 341 is transmitted to the transmit shift register 0 Do not accept a new character for transmission 1 Accept a new character for transmission 6 TxEmpty RO Transmitter Empty bit 0x1 In FIFO mode this bit is set whenever the Transmit Holding Register THR Register Table 501 p 341 the Transmitter Shift Register and the FIFO are all empty 7 RxFIFOErr ROC This bit is only active when FIFOs are enabled It is set when there is at 0x1 least one parity error framing error or break indication in the FIFO This bit is cleared when the Line Control Register LCR Register Table 507 p 344 is read Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June
92. The request queue is the interface that the host CPU uses to queue ATA DMA commands as a request between the system memory and the device The response queue is the interface that the EDMA uses to notify the host CPU that a data transaction between the system memory and the device was completed Each entry in the request queue consists of an ATA DMA command and the EDMA parameters and descriptors to initiate the device and to perform the data transaction Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 21 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation The EDMA is further responsible for parsing the commands initializing the device controlling the data transactions verifying the device status and updating the response queue when the command is completed This all occurs without CPU intervention Direct access to the device is also supported for device initialization and error handling 7 2 4 EDMA Request and Response Queues The request queue and the response queue are each located in CPU memory and organized as a length of 32 or 128 entries circular queues FIFO whose location is configured by the Queue In Pointer and the Queue Out Pointer entries The entry length is set using lt eEDMAQueLens field in the EDMA Configuration Register Table 228 p 228 for 32 entries lt eEDMAQueLen gt 0 for 128 entries field lt eEDMAQueLen gt 1 Since these po
93. Timer1 is disabled 1 Timer1 is enabled 3 CPUTimer1Auto RW CPU Timer 1 Auto Mode 0x0 When this bit is clear to 0 and lt CPUTimer1 gt has reached to zero lt CPUTimer1 gt stops counting When this bit is set to 1 and lt CPUTimer1 gt has reached zero CPUTimer1Rel is reload to lt CPUTimer1 gt then it continues to count 4 CPUWDTimerE RW CPU Watchdog Timer Enable n Sample 0 Watchdog timer is disabled at reset 1 Watchdog timer is enabled 5 CPUWDTimerA RW CPU Watchdog Timer Auto Mode uto 0x0 When this bit is clear to 0 and lt CPUWDTimer gt has reached zero CPU WDTimer gt stops counting When this bit is set to 1 and lt CPUWDTimer gt has reached zero CPUTimerORel is reload to lt CPUWDTimers then it continues to count 31 6 Reserved RW Reserved 0x0 Table 66 CPU Timer0 Reload Register Offset 0x20310 Bits Field Type Description InitVal 31 0 CPUTimerORel RW CPU Timer 0 Reload 0x0 This field contains the reload value of timer 0 it is used as the reload value in Periodic mode Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 105 Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers Table 67 CPU Timer 0 Register Offset 0x20314 Bits Field Type Description InitVal 31 0 CPUTimerO RW CPU Timer 0 0x0 This 32 bit counter is decremented every 88F51 82 internal clock When lt CPUTimer0En
94. Type Description InitVal 31 0 InitValH RW MSB of Initial Value to be written cyclically to target block in Memlnit mode 0x0 Mapped to bits 63 32 of initial value This register is shared between the two XOR Engine channels The XOR Engine will compose a 64 bit Initial Value out of InitValL and InitValH registers and write it cyclically to the target block Target block can be of any alignment NOTE Valid only on Memlnit modes Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 379 Document Classification Proprietary June 25 2007 Preliminary General Purpose Port Registers A 17 General Purpose Port Registers Table 564 GPIO Registers Map Register Offset Table Page GPIO Data Out Register 0x10100 Table 565 p 380 GPIO Data Out Enable Control Register 0x10104 Table 566 p 380 GPIO Blink Enable Register 0x10108 Table 567 p 381 GPIO Data In Polarity Register 0x1010C Table 568 p 381 GPIO Data In Register 0x10110 Table 569 p 381 GPIO Interrupt Cause Register 0x10114 Table 570 p 382 GPIO Interrupt Mask Register 0x10118 Table 571 p 382 GPIO Interrupt Level Mask Register 0x1011C Table 572 p 382 A 17 1 GPIO Registers Description Table 565 GPIO Data Out Register Offset 0x10100 Bits Field Type Description InitVal 25 0 GPIODOut RW GPIO Output Pins Value bit per each GPIO pin 0x0 31 26 Reserved RW Reserved 0x0 T
95. Wake 0x0 When set to 1 this bit indicates that a Comm Wake signal was detected by the PHY since the last time this bit was cleared 19 B RW 10 bit to 8 bit Decode Error 0x0 When set to 1 this bit indicates that one or more 10 bit to 8 bit decoding errors occurred since the bit was last cleared 20 D RW Disparity Error 0x0 When set to one this bit indicates that incorrect disparity was detected one or more times since the last time the bit was cleared 21 C RW CRC Error 0x0 When set to 1 this bit indicates that one or more CRC errors occurred with the Link Layer since the bit was last cleared 22 H RW Handshake Error 0x0 When set to one this bits indicates that one or more R ERR handshake responses was received in response to frame transmission Such errors may be the result of a CRC error detected by the recipient a disparity or 10 bit to 8 bit decoding error or other error conditions leading to a negative handshake on a transmitted frame 23 S RW Link Sequence Error 0x0 When set to 1 this bit indicates that one or more Link state machine error conditions was encountered since the last time this bit was cleared The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition 24 T RW Transport state transition error 0x0 When set to 1 this bit indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time th
96. a e nennen eene nennen 381 Offset 0x10108 Table 568 GPIO Data In Polarity Heoieier ener rennen rre nret rre trren reet ren rennes 381 Offset 0x1010C Table 569 GPIO Data In Reglister eec teen oie Eee neat bec ICE RR E RED ea rc Ed 381 Offset 0x10110 Table 570 GPIO Interrupt Cause Register rennen nretnretrretre nnne eren rent en rentre 382 Offset 0x10114 Table 571 GPIO Interrupt Mask Register cece cece eens eee teas eeee seas eeaeeeaeseaeseaeseaeseaeseeesaaeseaeseaesaesnaeesaeseaeseaeeeaeeaes 382 Offset 0x10118 Table 572 GPIO Interrupt Level Mask Heotsier nennen rennen nretren rennen rennes 382 Offset 0x1011C Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 86 88F5182 marveL Open Source Community Programmer s User Guide A 18 Pins Multiplexing Interface Registers cccceseeenesseseeeeeeseeeeeeseeseeeeeeeesneeneeseeeneenenenes 384 Table 574 MPP Control O Register tee ertet ttr ri ene acticin SERE e dain einen 384 Offset 0x10000 Table 575 MPP Control 1 egister oe iier tee tenet serena se IE Fei eruptio kiere ie EEGEN 385 Offset 0x10004 Table 576 MPP Control 2 Register ten nter rie trt hee ret rte e edere Goose dg 385 Offset 0x10050 Table 577 Device Multiplex Control Register eeiseeeseeseeeeeeeeeennee nennen rennen nenne reete nennen 386 Offset 0x1000
97. a null terminated descriptor pointer or by a CPU owned descriptor or by a descriptor with a parity error the DMA will disable the queue but not set the DISQ bit for the queue thus reading DISQ and ENQ bits discriminates between queues dis ables by the CPU and those stopped by DMA due to null pointer or CPU owned descriptor or parity error on descriptor NOTE The DISQ bits will be cleared on link down 31 9 Reserved RO Reserved 0x0 Table 397 Maximum Transmit Unit MTU Offset 0x72458 Bits Field Type Description InitVal 5 0 Reserved RW Reserved 9KB 256 NOTE Must be programmed to 0x0 36 20x24 31 6 Reserved RO Reserved 0x0 Table 398 Port Interrupt Cause IC Offset 0x72460 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 0 RxBuffer RW Rx Buffer Return 0x0 Indicates a Rx buffer returned to CPU ownership or that the port finished reception of a Rx frame in either priority queues NOTE To get a Rx Buffer return per priority queue use bits 9 2 To limit the interrupts to frame rather than buffer boundaries the user should set the SDCR RIFB bit 1 Extend RW Interrupt Cause Extend register ICERx of this port has a bit set 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 290
98. activated 12 10 Reserved RO Reserved 0x0 31 13 AcclState RO Internal State of the accelerator 0x0 A 11 6 Interrupt Cause Registers Table 489 Cryptographic Engines and Security Accelerator Interrupt Cause Register Offset Ox9DE20 NOTE The cryptographic engine has a dedicated Interrupt Cause register This register is set by events occurring in the engine Clearing this register s bits is done by writing 0 to the cause bits Writing 1 to a bit has no effect This register is shared by the DES and the Authentication engine Bits Field Type Description InitVal 0 ZintO RWO This bit is the authentication termination clear indication The interrupt is set 0x0 when the authentication engine finishes the calculation process 1 Zinti RWO This bit is the DES encryption all termination clear indication The interrupt is 0x0 set when the encryption engine finishes the calculation process 2 Zin2 RWO This bit is the AES encryption termination clear indication The interrupt is set 0x0 when the AES encryption engine finishes the calculation process 3 Zint3 RWO This bit is the AES decryption termination clear indication The interrupt is set 0x0 when the AES decryption engine finishes the calculation process 4 Zint4 RWO This bit is the encryption termination clear indication The interrupt is set when 0x0 the encryption engine finishes the calculation process 5 AccintO RWO This bit is the Securit
99. can also be used as the interrupt controller for external devices generating interrupts to the Marvell CPU core via GPIO inputs The interrupt controller can also receive interrupt messages from an external PCI Express device The 88F5182 can also act as a PCI or PCI Express Endpoint As such it can generate the PCI Express INTA emulation message or the INTAn signal 17 2 Local Interrupt Cause and Mask Registers The 88F5182 handles interrupts in two stages The first stage is specific unit cause and mask registers that distinguish between a specific interrupt events within the unit Once an interrupt event occurs its corresponding bit in the unit cause register is set to 1 If the interrupt is not masked by the unit mask register it is marked in the Main Interrupt Cause register The unit local mask register has no affect on the setting of interrupt bits in the unit local cause register It only affects the setting of the interrupt bit in the Main Interrupt Cause register When working in level mode the GPIO Data In register must be used Do not use the GPIO Interrupt Cause register The different units cause registers are Local to System Bridge Interrupt Cause register e PCI Express Interrupt Cause registers e PCI Interrupt Cause register e SATAHC Main Interrupt Cause register e GbE Port Interrupt Cause register e USBO Interrupt Cause register e Cryptographic Engine Security Accelerator Cause register e TWSI Interrupt Cause
100. command must be 4 byte aligned Table 11 ePRD Table Data Structure Map Descriptor Table Page ePRD DWORD 0 Table 12 p 29 ePRD DWORD 1 Table 13 p 30 ePRD DWORD 2 Table 14 p 30 ePRD DWORD 3 Table 15 p 30 Table 12 ePRD DWORD 0 Bits Field Description 0 Reserved Reserved 31 1 PRDBA 31 1 The byte address of a physical memory region corresponds to address bits 31 1 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 29 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation Table 13 ePRD DWORD 1 Bits Field Description 15 0 ByteCount Byte Count The count of the region in bytes Bit 0 is force to 0 There is a 64 KB maximum A value of 0 indicates 64 KB The data in the buffer must not cross the boundary of the 32 bit address space that is the 32 bit high address of all data in the buffer must be identical 30 16 Reserved Reserved 31 EOT End Of Table The data transfer operation terminates when the last descriptor has been retired 0 Not end of table 1 End of table NOTE The total number of bytes in the PRD table total byte count in DMA command must be 4 byte aligned Table 14 ePRD DWORD 2 Bits Field Description 31 0 PRDBA 63 32 The byte address of a physical memory region corresponds to bits 64 32 Must be set to 0x0
101. completes the calculation this field will contain the Column 3 of the AES result Table 459 AES Encryption Data In Out Column 2 Register Offset 0x9DDA4 Type Bits Field InitVal Description 31 0 AesEncDatCol2 RW At first this field contains Column 2 of the input data block to be encrypted NA When the AES completes the calculation this field will contain the Column 2 of the AES result Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 322 88F5182 marveL Open Source Community Programmer s User Guide Table 460 AES Encryption Data In Out Column 1 Register Offset Ox9DDA8 Bits Field Type Description InitVal 31 0 AesEncDatCol1 RW At first this field contains Column 1 of the input data block to be encrypted NA When the AES completes the calculation this field will contain the Column 1 of the AES result Table 461 AES Encryption Data In Out Column 0 Register Offset OX9DDAC Bits Field Type Description InitVal 31 0 AesEncDatCol0 RW At first this field contains Column 0 of the input data block to be encrypted NA When the AES completes the calculation this field will contain the Column 0 of the AES result Table 462 AES Encryption Key Column 3 Register Offset Ox9DD90 Bits Field Type Description InitVal 31 0
102. core must place the slave address or write data to be transmitted In the case of read access it contains received data need to be read by the Marvell core In slave mode the Data register contains data received from master on write access or data to be transmitted written by the Marvell core on read access TWSI Data register MSB contains the first bit to be transmitted or being received 11 1 3 TWSI Control An 8 bit TWSI Control Table 495 p 336 register is used both in master and slave modes 11 1 4 TWSI Status An 8 bit TWSI Status Table 496 p 338 register is used both in master and slave modes This 8 bit register contains the current status of the TWSI interface Bits 7 3 are the status code bits 2 0 are Reserved read only 0 11 1 5 Baud Rate Register TWSI specification defines TW SCK frequency of 100 KHz 400 KHz in fast mode The TWSI module contains a clock divider to generate the TW SCK clock Setting bits 6 0 of TWSI Baud Rate Table 497 p 339 register offset 0x1100C defines TW SCK frequency as follows Table 21 Setting the Baud Rate Register TCIk N M TWSI Frequency in kHz 3 10 94 3 3 13 74 1 166 MHz 4 9 51 8 6 12 99 7 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 42 e E 88F5182 marveL Open Source Community Programmer s User Guide As defined in the TWSI spec
103. dace ENEE 318 Offset OX9DD64 Table 448 DES Command Register c c cccesoossstesctescesscesssaesdsdscnssncessacisconcesacsedisssonnstcensesanestbedessodtuseesivanoneattessnes 318 Offset OX9DD58 Table 449 SHA 1 MD5 Data In Register essen eene nne nennen etre trennen nente entente 319 Offset OX9DD38 Table 450 SHA 1 MD5 Bit Count Low Register AAA 319 Offset 0x9DD20 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 81 Document Classification Proprietary June 25 2007 Preliminary List of Registers Table 451 SHA 1 MD5 Bit Count High Register A 319 Offset OX9DD24 Table 452 SHA 1 MD5 Initial Value Digest A Register ener nenne 320 Offset 0x9DD00 Table 453 SHA 1 MD5 Initial Value Digest B Register ener 320 Offset OX9DD04 Table 454 SHA 1 MD5 Initial Value Digest C Hegieter rennen 320 Offset OX9DD08 Table 455 SHA 1 MD5 Initial Value Digest D Hegieter ener nnne 320 Offset OX9DDOC Table 456 SHA 1 Initial Value Digest E Register A 320 Offset 0x9DD10 Table 457 SHA 1 MD5 Authentication Command Register 321 Offset 0x9DD18 Table 458 AES Encryption Data In Out Column 3 Register eene nennen enne nnns 322 Offset OXODDAO Table 459 AES Encryption Data In Out Column 2 Register nennen nnns 322 Offset Ox9DDA4 Table 460 AES Encryption Data In Out Column 1 Register 323 Offset Ox9DDA8 Table 461 AES Encryption Data In Out Column 0 Register eene nennen nnne nnns 323 Off
104. gt 0 lt CPUTimer0 gt stop When lt CPUTimer0En gt 1 and lt CPUTimer0Auto gt 0 CPUTimer0 is decremented until it reaches to 0 then it stops When lt CPUTimer0En gt 1 and CPUTimerOAuto 1 lt CPUTimer0 gt is decremented until it reaches to 0 then CPUTimerORel is reload to lt CPUTimer0 gt and then lt CPUTimer0 gt continues to count When lt CPUTimer0 gt reaches 0 bit CPUTimerOIntReq is set to 1 in Local to System Bridge Interrupt Cause Registers Table 68 CPU Timer1 Reload Register Offset 0x20318 Bits Field Type Description InitVal 31 0 CPUTimer1R RW CPU Timer 1 Reload el 0x0 See the CPU TimerO Reload Register Table 69 CPU Timer 1 Register Offset 0x2031C Bits Field Type Description InitVal 31 0 CPUTimer1 RW CPU Timer 0 0x0 See the CPU Timer 0 Register Table 70 CPU Watchdog Timer Reload Register Offset 0x20320 Bits Field Type Description InitVal 31 0 CPUWDTim RW CPU Timer 1 Length erLen 0x0 See the CPU TimerO Reload Register Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 106 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 71 CPU Watchdog Timer Register Offset 0x20324 Bits Field Type Description InitVal 31 0 CPUWDTim RW CPU Watchdog Timer er Ox7
105. in the link state down gt up up gt down 21 Reserved RW Reserved 0x0 22 Reserved RW Reserved 0x0 23 InternalAddr RW Internal Address Error is set when there is an access to an illegal offset of Error 0x0 the internal registers When set the Internal Address Error register locks the address that caused the error 30 24 Reserved RO Reserved 0x0 31 EtherlntSum RO Ethernet Interrupt Extend Summary 0x0 This bit is a logical OR of the unmasked bits 30 0 in the Interrupt Cause Extend register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 293 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 400 Port Interrupt Mask PIM Offset 0x72468 Bits Field Type Description InitVal 26 0 Various RW Mask bits for Interrupt Cause register 0x0 0 Mask 1 Do not mask 31 27 Reserved RO Reserved 0x0 Table 401 Port Extend Interrupt Mask PEIM Offset 0x7246C Bits Field Type Description InitVal 23 0 Various RW Mask bits for Port Extend Interrupt Cause register 0x0 0 Mask 1 Do not mask 31 24 Reserved RO Reserved 0x0 Table 402 Port Rx FIFO Urgent Threshold PRFUT Offset 0x72470 Bits Field Type Description InitVal 4 0 RxUThreshold RW Contains the Rx FIFO Threshold to start an Urgent indication 0x10 0x0 Disable Urgent 0x1 0x1F Thr
106. in this field is set and the corresponding bit in lt CPUIntCsMask gt 0x0 in the CPU to Host Doorbell Mask Register is also set bit lt Host2CPUDoorbell gt is set in the Main Interrupt Cause Register An CPU write of 1 set the bits in this field An CPU write of 0 has no affect A Host write of 0 clear the bits in this field A Host write of 1 has no affect Table 75 CPU to Host Doorbell Mask Register Offset 0x2040C Bits Field Type Description InitVal 31 0 CPUIntCsMa RW CPU Interrupt Cause Mask Sk 0x0 Mask bit per each cause bit in lt CPUIntCs gt field in the CPU to Host Door bell Register 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of the interrupt bit in the Main Interrupt Cause Register It does not affect the setting of bits in the CPU to Host Doorbell Register Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 108 88F5182 marveL Open Source Community Programmer s User Guide A 5 DDR SDRAM Controller Registers Table 76 DDR SDRAM Register Map Register Name Offset Table and Page DDR SDRAM Controller Address Decode Registers CS 0 n Base Address Register 0x01500 Table 77 p 110 CS 0 n Size Register 0x01504 Table 78 p 110 CS 1 n Base Address
107. integrates a PCI bus arbiter to support up to six masters 5 2 PCI Master Operation The 88F5182 PCI master supports the following transactions e Memory Read e Memory Write e Memory Read Line e Memory Read Multiple e Memory Write amp Invalidate e O Read e WO Write Configuration Read e Configuration Write Interrupt Acknowledge e Special Cycle e Dual Address Cycles N Note Only partial UO transactions are supported The master generates a Memory Write and Invalidate transaction if e The transaction accessing the PCI memory space requests a data transfer size equal to multiples of the PCI cache line size with all byte enables active e The transaction address is cache aligned e Memory Write and Invalidate Enable bit in the Configuration Command register is set The master generates a Memory Read Line transaction if e The transaction accessing the PCI memory space requests a data transfer size equal to multiples of the PCI cache line size The transaction address is cache aligned A Memory Read Multiple transaction is carried out when the transaction accessing the PCI memory space requests a data transfer that crosses the PCI cache line size boundary Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 18 88F5182 E marveL Open Source Community Programmer s User Guide S Note The 88F5182 sup
108. is assigned to the DMA queue based upon a highly configurable analysis which evaluates the DA MAC IP ToS Type of Service 802 1P priority tag and protocol ARP TCP or UDP An example for use of this feature is the implementation of differentiated services in a router interface or for real time jitter sensitive voice video traffic intermixed with data traffic As each queue has its own buffering blocking is avoided and latency is reduced for service by the CPU Detailed status is given for each receive frame in the packet descriptors while statistics are accumulated for received and transmitted traffic in the MIB counters on a per port basis The 10 100 1000 Mbps Gigabit Ethernet unit handles all functionality associated with moving packet data between local memory and the Ethernet ports The port s speed 10 100 or 1000 Mbps is auto negotiated through the PHY and does not require user intervention Auto Negotiation for MII and GMIII is according to 802 3ab draft 5 0 using the SMI interface The 1000 Mbps unit operates only in full duplex mode The 100 and 10 Mbps units operate either in half or full duplex mode with the selection of the duplex mode auto negotiated through the PHY without user intervention There is no Auto Negotiation for speed on the PCS GMII only supports symmetric flow control S Note When Auto Negotiation is disabled the link must be forced down when changing port speed There are eight receive
109. is disabled lt ANSpeed gt 1 and 0x1 SetGMIISpeed 0 then this bit should set the speed of the MII interface 0 Port works in 10 Mbps 1 Port works in 100 Mbps NOTE This bit is meaningless when lt ANSpeeds gt is enabled 25 Reserved RW Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 286 88F5182 marveL Open Source Community Programmer s User Guide Table 393 Port Serial Control PSC Continued Offset 0x7243C Bits Field Type Description InitVal 27 26 Reserved RW Reserved 0x0 Must be 0 31 28 Reserved RO Read Only 0x0 Table 394 VLAN Priority Tag to Priority VPT2P Offset 0x72440 Bits Field Type Description InitVal 23 0 Priority 23 0 RW The Priority queue mapping of received frames with 802 1p priority field val 0x0 ues 0 corresponding to Priority 2 0 through 7 corresponding to Prior ity 23 21 NOTE The initial value means that Priority does not effect the queue decisions 31 24 Reserved RO Reserved 0x0 Table 395 Ethernet Port Status PS Offset 0x72444 Bits Field Type Description InitVal 0 Reserved RO Reserved Sam pled at reset 0x0 Link 1 LinkUp RO The Link Status 0x0 0 Link is down 1 Link is up This bit is set forced to 1 when Force Link Pass 1 This bi
110. is not updated an error message is not generated Status bit is set regardless of the mask setting 0x0 Not masked 0x1 Masked Table 170 PCI Express Uncorrectable Error Severity Register Offset 0x4010C Configuration 0x10C NOTE AN fields in this register are hot sticky not initialized or modified by reset Bits Field Type Description InitVal 31 0 Severity RW Uncorrectable Error Severity Control 0x00060 Controls the severity indication of the Uncorrectable errors Each bit controls 010 the error type of the corresponding bit in the PCI Express Uncorrectable Error Status Register Table 168 p 163 0 Error type is Non Fatal 1 Error type is Fatal Table 171 PCI Express Correctable Error Status Register Offset 0x40110 Configuration 0x110 NOTE AU fields in this register are sticky not initialized or modified by hot reset All fields in this register except for reserved fields are SC write 1 to clear Bits Field Type Description InitVal 0 RcvErr SC Receiver Error Status 0x0 NOTE When set this bit indicates that a Receiver error has occurred 5 1 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 165 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 171 PCI Express Correctable Error Status Register Continued Offset 0x40110 Configuration
111. mode operation This bit may be set only when bit 11 lt ComChannel gt is also set 0 Target 1 Initiator 11 ComChannel RW 0x0 Communication Channel Operating Mode This bit defines if the Serial ATA port functions in Target mode operation 0 Disk controller 1 Target mode operation NOTE In Target mode the ATA task registers are updated when the Register Device to Host FIS is received regardless to the value of lt BSY gt bit in the ATA Status register see Table 291 Shadow Register Block Reg isters Map on page 215 Doc No MV S400130 00 Rev 0 5 Page 255 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 349 Serial ATA Interface Configuration Register Continued Offset Port 0 0x82050 Port 1 0x84050 NOTE After any modification in this register the host must set bit 2 lt eAtaRst gt field in the EDMA Command Register Table 321 p 236 Bits Field Type InitVal Description 23 12 Reserved RW 0x9B7 Reserved This field must be written with a value of 0x9B7 24 IgnoreBsy RW 0x0 When this bit is set to 1 the ATA task registers are updated when Register Device to Host FIS is received or when the host writes to the ATA Status regis ters regardless of the value of the lt BSY gt bit in the ATA Status register see Table 291 Shadow Regist
112. of these bits are written when field lt eEnEDMAs is set the write transaction will cause unpredictable behavior Bits Field Type Description InitVal 31 0 DataRe RW DataRegion gion 31 0 0x0 This DWORD contains bit 31 1 of the current physical region starting address Bit 0 must be 0 This field is updated by the DMA and indicates the completion status of the DMA when BasicDMAActive is cleared to 0 The host must not write to this bit when the Basic DMA is active Table 336 Data Region High Address Register Offset Port 0 0x82238 Port 1 0x84238 NOTE The CPU accesses this register for direct access to the device when the EDMA is disabled Field lt eEnEDMAs in EDMA Command Register see Table 321 on page 236 is cleared While the EDMA is enabled the host must not write this register If any of these bits are written when field lt eEnEDMAs is set the write transaction will cause unpredictable behavior Bits Field Type Description InitVal 31 0 DataRe RW DataRegion gion 63 32 0x0 This DWORD contains bits 64 32 of the current physical region starting address This field is updated by the DMA and indicates the completion status of the DMA when BasicDMAActive is cleared to 0 The host must not write to this bit when the Basic DMA is active Doc No MV S400130 00 Rev 0 5 Page 245 Copyright O 2007 Marvell Document Classification Proprietary June 25 2
113. owned descriptor either in the middle or on start of new packet will not result in disabling the DMA and DMA will continue to read the descriptor it is using when a new packet arrives to this queue until it gets ownership of it For these cases a not owned descriptor a null terminated descriptor or a parity error on descriptor the DMA will assert the resource RxErrorQueue interrupt 15 8 DISQ RW 0x0 Disable Queue 7 0 One bit per each queue Writing these bits set to 1 disables the queue The transmit DMA will stop the Receive process to this queue on the next packet boundary Writing 1 to DISQ bit resets the matching ENQ bit after the RxDMA finished processing the queue if the ENQ bit was used while the CPU wrote the DISQ for it Writing O to DISQ bit has no effect When transmit DMA encounters a queue ended either by a null terminated descriptor pointer or a descriptor with a parity error the DMA will disable the queue but not set the DISQ bit for that queue thus reading DISQ and ENQ bits discriminates between queues disables by CPU and those stopped by DMA due to a null pointer or a parity error on descriptor 31 16 Reserved RO 0x0 Doc No MV S400130 00 Rev 0 5 Page 297 Read Only Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 410 Transmit Current Served Descriptor Pointer Offset
114. programmed to 0 or 1 11 7 IPG RW These five bits determine the IPG JAM to DATA The step is 4 bit times The JAM TO DATA 0x10 value may vary between 4 and 128 bit times NOTE These bits can only be changed when lt PortEn gt field is set to 0 in the Port Control Register Port is disabled 16 12 IPG DATA RW Inter Packet Gap IPG 0x18 The step is 4 bit times The value may vary between 12 and 124 bit times NOTE These bits can only be changed when lt PortEn gt field is set to 0 in the Port Control Register Port is disabled 21 17 DataBlind RW Data Blinder 0x10 The number of nibbles from the beginning of the IFG in which the port restarts the IFG counter when detecting a carrier activity Following this value the port enters the Data Blinder zone and does not reset the IFG counter This ensures fair access to the medium The value must be written in hexadecimal format The default is 10 hex 64 bit times 2 3 of the default IPG The step is 4 bit times Valid range is 3 to 1F hex nibbles NOTE These bits can only be changed when lt PortEn gt field is set to 0 in the Port Control Register Port is disabled 31 22 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 279 Document Classification Proprietary June 25 2007 Preliminary Table 384 GMII Serial Parameters Gigabit Ethernet Controller Registers Offset 0x7240
115. reaches 0 1 Interrupt asserted when the Next Descriptor pointer is NULL and the IDMA byte count reaches 0 NOTE IntMode is only relevant in chain mode 11 Reserved RW Reserved 0x0 Must be set to 1 12 ChanEn RW Channel Enable 0x0 0 The channel is suspended 1 The channel is activated Re setting the bit to 1 allows the channel to continue the IDMA transfer Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 358 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 535 Channel Control Low Register Continued Offset Channel 0 0x60840 Channel 1 0x60844 Channel 2 0x60848 Channel 3 0x6084C Doc No MV S400130 00 Rev 0 5 Page 359 Bits Field Type Description 13 FetchND RWC Fetch Next Descriptor 0x0 If set to 1 forces a fetch of the next descriptor Cleared after the fetch is completed NOTE FetchND is only relevant in chain mode 14 ChanAct RO IDMA Channel Active 0x0 Read only 0 Channel is not active 1 Channel is active 16 15 Reserved RW Reserved 0x0 17 CDEn RW Close Descriptor Enable 0x0 If enabled the IDMA writes the upper byte s of the byte count field back to memory In 64K descriptor mode it writes the remainder byte count into bits 31 16 of the byte count field In n16M descriptor mode it writes the ownership and status bits in
116. register e UARTO 1 Interrupt Cause registers e Device Interrupt Cause register e GPIO Interrupt Cause register IDMA Interrupt Cause register e XOR Engine Interrupt Cause register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 59 Document Classification Proprietary June 25 2007 Preliminary Interrupt Controller Main Interrupt Cause and Mask Registers 17 3 Main Interrupt Cause and Mask Registers The second stage includes the Main Interrupt Cause register and Main Interrupt mask registers that summarize the interrupts generated by each unit The interrupt handler first reads the main cause register and then reads the specific unit cause register N Note The Main Interrupt Cause register bits are Read Only To clear an interrupt cause the software needs to clear the active bit s in the specific unit cause register There are two mask registers corresponding to the two CPU interrupt lines IRQ and FIQ Setting these registers allows the reporting of different interrupt events on the different interrupt lines If a bit in the mask register is set to 1 the corresponding interrupt event is enabled The setting of the mask bits has no affect on the value registered in the Main Interrupt Cause register it only affects the assertion of the interrupt pin An interrupt is asserted if at least one of the non masked bits in the cause register is set to 1 When the 88F5182 functions as Endpoint a third mask r
117. state restrictions 0001 Transition to the PARTIAL power management state disabled 0010 Transition to the SLUMBER power management state disabled 0011 Transition to both the PARTIAL and SLUMBER power management states disabled All other values are reserved 15 12 SPM RO This field is used to select a power management state A value written to 0x0 this field is treated as a one shot This field will be read as 0000 0000 No power management state transition requested 0001 Transition to the PARTIAL power management state initiated 0010 Transition to the SLUMBER power management state initiated 0100 Transition to the active power management state initiated All other values are reserved This field is read only 0000 31 16 Reserved RES Reserved 0x0 Table 341 LTMode Register Offset Port 0 0x8230C Port 1 0x8430C Bits Name Type Description InitVal 5 0 RcvWaterMark RW WaterMark Receiving flow control settings values in DWORDs When the 0x30 Rx FIFO s available entry is less than this value Serial ATA flow control is performed by sending HOLD primitives 6 Reserved RES Reserved 0x0 7 NearEndLBEn RW Near End Loopback Enable 0x1 0 Near end loopback BIST is disabled 1 Near end loopback BIST is enabled Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 249 Document Classification Proprietary June 25 2007 Preliminary Ser
118. ter PCI Express Header Log First DWORD Register 0x4011C Table 174 p 167 PCI Express Header Log Second DWORD Register 0x40120 Table 175 p 168 PCI Express Header Log Third DWORD Register 0x40124 Table 176 p 168 PCI Express Header Log Fourth DWORD Register 0x40128 Table 177 p 168 A 6 1 PCI Express BAR Control Registers Table 108 PCI Express BAR1 Control Register Offset 0x41804 Bits Field Type Description InitVal 0 Bar1En RW BAR1 Enable 0x1 15 1 Reserved RSVD Reserved 0x0 31 16 Bart Size RW BAR1 Size Ox3FFF BAR sizes range from 64 KByte to 4 GByte in powers of 2 default value O3FFF 1 GByte Table 109 PCI Express BAR2 Control Register Offset 0x41808 Bits Field Type Description InitVal 0 Bar2En RW BAR2 Enable 0x1 15 1 Reserved RSVD Reserved 0x0 31 16 Bar2Size RW BAR2 Size OxOFFF BAR sizes range from 64 KByte to 4 GByte in powers of 2 default value OxOFFF 256 MByte Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 129 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 110 PCI Express Expansion ROM BAR Control Register Offset 0x4180C Bits Field Type Description InitVal 0 ExpROMEn RW Expansion ROM BAR Enable 0x0 18 1 Reserved RSVD Reserved 0x0 21 19 ExpROMSz RW Expansion ROM Address Bank Size 0x0 0 512 512
119. that is not masked the field locks again until cleared as described above This lock and clear process continues to repeat itself Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 167 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 175 PCI Express Header Log Second DWORD Register Offset 0x40120 Configuration 0x120 NOTE AN fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Hdrlog2DW RO Header Log Second DWORD 0x0 Table 176 PCI Express Header Log Third DWORD Register Offset 0x40124 Configuration 0x124 NOTE Al fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Hdrlog3DW RO Header Log Third DWORD 0x0 Table 177 PCI Express Header Log Fourth DWORD Register Offset 0x40128 Configuration 0x128 NOTE A fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Hdrlog4DW RO Header Log Fourth DWORD 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 168 88F5182 marveL Open Source Community Programmer s User Guide A 7 PCI Interface Registers The PC
120. the system in the event of unpredictable software behavior After the watchdog is enabled it is a free running counter that needs to be serviced periodically to prevent its expiration After reset the watchdog is enabled or disabled according to sample at reset pin value When the watchdog timer expires and bit lt WDRstOutEn gt is set to 1 in the RSTOUTn Mask Register Table 57 p 100 the SYSRST OUTn output signal is set N Note See Section A 4 4 CPU Timers Registers on page 105 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 62 MARVELL 88F5182 Register Set Copyright 2007 Marvell CONFIDENTIAL Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 63 88F5182 marveL Open Source Community Programmer s User Guide THIS PAGE INTENTIONALLY LEFT BLANK Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 64 Document Classification Proprietary June 25 2007 Preliminary 88F5182 marveL Open Source Community Programmer s User Guide List of Registers A 1 Register Description saiserssna 88 A 2 Register Types st eee ee SR Re ey 88 A 3 Internal Registers Address Map cccesseecccesesseeeeeeseeeneeseeseseneeeseseeeneeeseseeeneeeseseeseeneens 89 A 4 Local to System Bridge Registers Table 34 Window0 Contro
121. then each time that Auto Negotiation is performed the value in the lt GMllSpeed gt field may change When this bit is 0 the MlISpeed defines whether it is 10 Mbps or 100 Mbps When the lt ANSpeeds bit is disabled this bit is set by the management in the PSCR lt SetGMllSpeed gt 5 MlilSpeed RO MII Speed Auto This field is meaningful only when lt GMIlSpeed gt 10 100 Mbps Negotia 0 2 Port works at 10 Mbps tion for 1 Port works at 100 Mbps duplex If lt ANSpeed gt is enabled then each time that Auto Negotiation is per mode formed the value in the lt MllSpeed gt may change when When lt ANSpeeds is disabled this bit is set by the management in PSCR AN Spe SetMllSpeed ed is enabled Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 288 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 395 Ethernet Port Status PS Continued Offset 0x72444 Bits Field Type Description InitVal 7 TxInProg RO Transmit in Progress 0x0 Indicates that the port s transmitter is in an active transmission state 9 8 Reserved RO Reserved 0x0 10 TxFIFOEmp RO Set when the port Transmit FIFO is empty 0x0 31 11 Reserved RO Read Only 0x0 Table 396 Transmit Queue Command TQC Offset 0x72448 Bits Field Type Description InitVal 0 ENQ RW
122. uncorrectable error that is not masked It remains locked until software clears it by writing 1 to the corre sponding status bit Upon receipt of the next uncorrectable error that is not masked the field locks again until cleared as described above This lock and clear process continues to repeat itself NOTE The bits in this field are sticky bits they are not initialized or modified by reset 4 DLP Data Link Protocol Error 12 TLP Poisoned TLP Error 13 FCP Flow Control Protocol Error 14 CT Completion Timeout Error 15 CAS Completer Abort Status 16 UCE Unexpected Completion Error 17 ROE Receiver Overflow Error 18 Mutant TLP Malformed TLP Error 19 Reserved 20 URE Unsupported Request Error Other Reserved 31 5 Reserved RSVD Reserved 0x0 Bits 5 and 7 are Read Only and are hardwired to 0 Table 174 PCI Express Header Log First DWORD Register Offset 0x4011C Configuration 0x11C NOTE All fields in this register are sticky not initialized or modified by hot reset Bits Field Type Description InitVal 31 0 Hdrlogi DW RO Header Log First DWORD 0x0 Logs the header of the first error reported in the Table 168 PCI Express Uncorrectable Error Status Register This field locks upon receipt of the first uncorrectable error that is not masked It remains locked until software clears it by writing 1 to the corre sponding status bit Upon receipt of the next uncorrectable error
123. upon bad parity detection during split completion to a write transaction initiated by the master 7 Reserved RES Reserved 0x0 8 MMabort RW If setto 1 asserts PCI SERRn upon a PCI master generation of master 0x0 abort 9 MTabort RW If set to 1 asserts PCI SERRn upon a PCI master detection of target 0x0 abort 10 MDis RW If set to 1 assert PCI_SERRn upon an attempt to generate a PCI 0x0 transaction while master is disabled 11 MRetry RW If set to 1 asserts PCI_SERRn upon a PCI master reaching retry 0x0 counter limit 16 12 Reserved RES Reserved 0x0 17 STabort RW If set to 1 asserts PCI SERRn upon a PCI slave generate Target Abort 0x0 19 18 Reserved RES Reserved 0x0 20 SRdBuf RW If set to 1 asserts PCI SERRn if the PCI slave s read buffer discard 0x0 timer expires 21 Arb RW If set to 1 asserts PCI_SERRn upon the internal PCI arbiter detection of 0x0 a broken PCI master Doc No MV S400130 00 Rev 0 5 Page 194 MARV Ki 88F5182 e tte Open Source Community Programmer s User Guide Table 243 PCI SERRn Mask Continued Offset 0x30C28 NOTE 88F5182 only asserts PCI SERRn if the PCI Status and Command register s lt SErrEn gt bit 8 is enabled see Table 250 on page 198 Bits Field Type Description InitVal 31 22 Reserved RES Reserved 0x0 N Note Error Address is not latched with the following interrupt events lt MDis gt bit 10 lt SRdBuf gt b
124. will be taken 0x0 Target and attributes are taken from XEBARO Address 63 32 taken from XEHARRO 0x1 Target and attributes are taken from XEBAR1 Address 63 32 taken from XEHARR1 0x2 Target and attributes are taken from XEBAR2 Address 63 32 taken from XEHARR2 0x3 Target and attributes are taken from XEBAR3 Address 63 32 taken from XEHARR3 NOTE Valid only if SAOOvrEn is set 3 SA1OvrEn RW Override Source Address 1 Control 0x0 5 4 SA1OvrPtr RW Override Source Address 1 Pointer 0x0 NOTE Valid only if SA1OvrEn is set 6 SA2OvrEn RW Override Source Address 2 Control 0x0 8 7 SA2OvrPtr RW Override Source Address 2 Pointer 0x0 NOTE Valid only if SA2OvrEn is set 9 SASOvrEn RW Override Source Address 3 Control 0x0 11 10 SA3OvrPtr RW Override Source Address 3 Pointer 0x0 NOTE Valid only if SASOvrEn is set 12 SA4OvrEn RW Override Source Address 4 Control 0x0 14 13 SA4OvrPtr RW Override Source Address 4 Pointer 0x0 NOTE Valid only if SA4OvrEn is set 15 SA5OvrEn RW Override Source Address 5 Control 0x0 17 16 SA5OvrPtr RW Override Source Address 5 Pointer 0x0 NOTE Valid only if SA5OvrEn is set 18 SA6OvrEn RW Override Source Address 6 Control 0x0 20 19 SA6OvrPtr RW Override Source Address 6 Pointer 0x0 NOTE Valid only if SA6OvrEn is set Doc No MV S400130 00 Rev 0 5 Page 375 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary XOR Engine Registers Tab
125. 0 N A 0 Reject filter frame 1 Accept frame 3 1 Queue 0 RW For pointer index 0 Determines the Queue number if Pass 0 1 N A 4 Reserved 0 RW Reserved N A Must be set to 0 7 5 Unused 0 RO Reserved N A 8 Pass 1 RW Determines whether to filter or accept for pointer index 1 N A 0 Reject filter frame 1 Accept frame 11 9 Queue 1 RW For pointer index 1 Determines the Queue number if Pass 1 1 N A 12 Reserved 1 RW Reserved N A Must be set to 0 1543 Unused 1 RO Reserved N A Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 300 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 416 Destination Address Filter Other Multicast Table DFUT Continued Offset 0x73500 0x735FC NOTE Every register holds four entries A total of 64 registers appear in this table in consecutive order Bits Field Type Description InitVal 16 Pass 2 RW Determines whether to filter or accept for pointer index 2 N A 0 Reject filter frame 1 Accept frame 19 17 Queue 2 RW For pointer index 2 Determines the Queue number if Pass 2 1 N A 20 Reserved 2 RW Reserved N A Must be set to 0 23 21 Unused 2 RO Reserved N A 24 Pass 3 RW Determines whether to filter or accept for pointer index 3 N A 0 Reject filter frame 1 Accept frame 27 25 Queue 3 R
126. 0 Channel 1 0x60844 Channel 2 0x60848 Channel 3 0x6084C Bits Field Type Description 30 27 Reserved RW Reserved 0x0 31 DescMode RW Descriptor Mode 0x0 0 64K descriptor mode 1 16M descriptor mode Table 536 Channel Control High Register Offset Channel 0 0x60880 Channel 1 0x60884 Channel 2 0x60888 Channel 3 0x6088C Bits Field Type Description 7 0 Reserved RW Reserved 0x0 Must be set to 0x3 31 8 Reserved RO Read Only 0x0 A 15 4 IDMA interrupt Registers Table 537 Interrupt Cause Register Offset 0x608CO Bits Field Type Description 0 Comp RW Channel IDMA Completion 0x0 1 AddrMiss RW ChannelO Address Miss 0x0 Failed address decoding 2 AccProt RW ChannelO Access Protect Violation 0x0 3 WrProt RW ChannelO Write Protect 0x0 4 Own RW ChannelO Descriptor Ownership Violation 0x0 Attempt to access the descriptor owned by the CPU 7 5 Reserved RW Reserved 0x0 12 8 Various RW Same as channel cause bits 0x0 15 13 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 360 88F5182 marveL Open Source Community Programmer s User Guide Table 537 Interrupt Cause Register Continued Offset 0x608C0 Bits Field Type Description 20 16 Various RW Same as channel c
127. 007 Preliminary Serial ATA Host Controller SATAHC Registers A 8 10 Serial ATA Interface Registers Table 337 SStatus Register Offset Port 0 0x82300 Port 1 0x84300 NOTE See the Serial ATA specification for a detailed description Bits Name Type Description InitVal 3 0 DET RO These bits set the interface device detection and PHY state 0x4 0000 No device detected and PHY communication is not established 0001 Device presence detected but PHY communication is not estab lished 0011 Device presence detected and PHY communication is established 0100 PHY in offline mode as a result of the interface being disabled or running in a loopback mode All other values are reserved 7 4 SPD RO These bits set whether the negotiated interface communication speed is 0x0 established 0000 No negotiated speed The device is not present or communication is not established 0001 Generation 1 communication rate negotiated 0010 Generation 2 communication rate negotiated All other values are reserved 11 8 IPM RO These bits set the current interface power management state 0x0 0000 Device not present or communication not established 0001 Interface in active state 0010 Interface in PARTIAL power management state 0110 Interface in SLUMBER power management state All other values are reserved 31 12 Reserved RES Reserved 0x0 Table 338 SError Register Offset Port 0 0x82304 Port 1
128. 01 l 6 mA V 300 mVp p 010 l 8 mA V 400 mVp p 011 21210 mA V 500 mVp p 100 1212 mA V 600 mVp p 101 21214 mA V 700 mVp p 110 1216 mA V 800 mVp p 111 1218 mA V 900 mVp p 11 Loopback RW Loopback function as near end loopback 0x0 0 Analog PHY is in Normal mode 1 Analog PHY is in Loopback mode 19 12 Reserved RW Reserved 0x0 NOTE Must write the value 8h 09 to this field on every access 23 20 Reserved RW Reserved 0x9 NOTE Perform a read modify write access to this field to avoid the con tents being changed 25 24 Reserved RW Reserved 0x0 NOTE Must write the value 0x0 to this field on every access Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 252 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 345 PHY Mode 2 Register Continued Offset Port 0 0x82330 Port 1 0x84330 NOTE This register must be fully written on every write access to any of its fields Bits Name Type Description InitVal 29 26 Reserved RW Reserved 0x9 NOTE Perform a read modify write access to this field to avoid the con tents being changed 31 30 Reserved RW Reserved 0x0 NOTE Must write the value 0x0 to this field on every access Table 346 BIST Control Register 0x82334 Port 1 0x84334 Offset Port 0 Bits Name Type Descriptio
129. 07 Preliminary Document Classification Proprietary Page 298 88F5182 marveL Open Source Community Programmer s User Guide Table 414 Transmit Queue Arbiter Configuration TQxAC Offset Q0 0x72708 Q1 0x72718 Q2 0x72728 Q3 0x72738 Q4 0x72748 Q5 0x72758 Q6 0x72768 Q7 0x72778 NOTE Transmit Queues 1 7 are reserved Bits Field Type Description InitVal 25 0 Reserved RW Reserved Undefined NOTE Queue 0 offset 0x72708 must be programmed to OxFF Must be Queue 1 through 7 offset 0x72718 0x72728 0x72738 0x72748 initialized 0x72758 0x72768 0x72778 must be programmed to 0x0 31 25 Reserved RO Reserved 0x0 Table 415 Destination Address Filter Special Multicast Table DFSMT Offset 0x 73400 0x734FC NOTE Every register holds four entries A total of 64 registers appear in the table in consecutive order Bits Field Type Description InitVal 0 Pass 0 RW Determines whether to filter or accept for pointer index 0 N A 0 Reject filter frame 1 Accept frame 3 1 Queue 0 RW For pointer index 0 Determines the Queue number if Pass 0 1 N A 4 Reserved 0 RW Reserved N A Must be set to 0 7 5 Unused 0 RO Reserved N A 8 Pass 1 RW Determines whether to filter or accept for pointer index 1 N A 0 Reject filter frame 1 Accept frame 11 9 Queue 1 RW For pointer index 1 Determines the Queue number if Pass 1 1 N A 12 Reserved
130. 07 Preliminary Document Classification Proprietary Page 386 88F5182 MARVELL Open Source Community Programmer s User Guide Note S For additional information about the reset pins referred to in the Sample at Reset Register see the Reset Configuration table in the 88F5182 88F5182 based Storage Networking Platforms Datasheet for this device Table 578 Sample at Reset Register Offset 0x10010 NOTE Writing to this register has no effect on the reset strapped features This is a status register only For further details on the functionality of each bit see the reset section in the 88F5182 Datasheet Bits Field Type InitVal Description 25 0 SampleAtReset RW Sample during reset 0 DEV_OEn 1 DEV_WEn 1 2 DEV WEn 0 3 DEV_BURSTn 4 DEV_AD 14 5 DEV_AD 13 6 Reserved 10 7 DEV AD 11 8 11 DEV A 2 13 12 DEN A 1 0 15 14 DEV_ALE 1 0 17 16 DEN AD 7 6 18 DEV_AD 12 19 DEV_AD 15 20 DEN AD 4 21 DEN AD 2 22 DEV_AD 5 23 DEN AD 3 25 24 DEN AD 1 0 31 26 Reserved RW 0x0 Reserved Doc No MV S400130 00 Rev 0 5 Page 387 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Appendix B Revision History Revision History Table 579 Revision History Document Type Revision Date Preliminary 0 5
131. 0A74 Channel 2 0x60A78 Channel 3 0x60A7C Table 534 p 357 Doc No MV S400130 00 Rev 0 5 Page 353 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary Table 523 IDMA Control Register Map IDMA Controller Interface Registers Register Offset Page Channel Control Low Register Channel 0 0x60840 Channel 1 Table 535 p 358 0x60844 Channel 2 0x60848 Channel 3 0x6084C Channel Control High Register Channel 0 0x60880 Channel 1 Table 536 p 360 0x60884 Channel 2 0x60888 Channel 3 0x6088C Table 524 IDMA Interrupt Register Map Register Offset Page Interrupt Cause Register 0x608C0 Table 537 p 360 Interrupt Mask Register 0x608C4 Table 538 p 361 Error Address Register 0x608C8 Table 539 p 362 Error Select Register 0x608CC Table 540 p 363 A 15 1 IDMA Descriptor Registers Table 525 Channel IDMA Byte Count Register Offset Channel 0 0x60800 Channel 1 0x60804 Channel 2 0x60808 Channel 3 0x6080C Bits Field Type Description 23 0 ByteCnt RW Number of bytes left for the IDMA to transfer 0x0 When running in 64K descriptor mode the byte count is 16 bit only bits 15 0 29 24 Reserved RES Reserved 0x0 30 BCLeft RW Left Byte Count 0x0 When running in 16M descriptor mode and when closing a descriptor indicates whether the whole byte count was completely transferred 0 The whole byte cou
132. 0x0 DAC transaction meaning the address is composed of Error Address Low and High registers 31 5 Reserved RES Reserved 0x0 A 7 5 Function 0 Configuration Registers Table 249 PCI Device and Vendor ID Offset 0x00 Bits Field Type Description InitVal 15 0 VenID RW Marvell s Vendor ID 0x11AB Read only from PCI 31 16 DevID RW 88F5182 Device ID 0x5182 Read only from PCI Table 250 PCI Status and Command Offset 0x04 Bits Field Type Description InitVal 0 IOEn RW Controls the 88F5182 s ability to response to PCI I O accesses 0x0 0 Disable 1 Enable 1 MEMEn RW Controls the 88F5182 s ability to response to PCI Memory accesses 0x0 0 Disable 1 Enable 2 MasEn RW Controls the 88F5182 s ability to act as a master on the PCI bus 0x0 0 Disable 1 Enable 3 SpecialEn RO Controls the 88F5182 s ability to respond to PCI special cycles 0x0 Read only 0 88F5182 PCI slave does not support special cycles 4 MemWrlInv RW Controls the 88F5182 s ability to generate memory write and invalidate 0x0 commands on the PCI bus 0 Disable 1 Enable Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 198 88F5182 MARVELL Open Source Community Programmer s User Guide Table 250 PCI Status and Command Continued
133. 0x0 This bit is set to 1 if the EDMA encounters error and clears lt eEnEDMA gt 0 EDMA was not self disabled 1 EDMA was self disabled 8 eTransint RWO Transport Layer Interrupt 0x0 This bit is set when at least one bit in the FIS Interrupt Cause Register see Table 355 on page 263 is set to 1 and the corresponding bit in the FIS Interrupt Mask Register see Table 356 on page 265 is set to 1 enabled 0 Transport layer does not wait for host 1 Transport layer waits for host NOTE This bit should be cleared only after clearing the FIS Interrupt Cause Register 11 9 Reserved RWO Reserved 0x0 12 elORdyErr RWO EDMA IORgy Error 0x0 IORdy timeout occurred See Table 324 EDMA IORdy Timeout Register on page 239 NOTE This bit is only set when the EDMA is disabled 16 13 LinkCtIRxErr RWO Link Control Receive Error 0x0 This field indicates when a control FIS is received with errors Bit 0 of this field i e bit 13 of this register is set to 1 when a SATA CRC error occurs Bit 1 of this field is set to 1 when an internal FIFO error occurs Bit 2 of this field is set to 1 when the Link Layer is reset to Idle state by the reception of SYNC primitives from the device Bit 3 of this field is set to 1 when Link state errors coding errors or run ning disparity errors occur during FIS reception 20 17 LinkDataRxErr RWO Link Data Receive Error 0x0 This field indicates when a data FIS is received with errors Bit 0 of this f
134. 0x15 Reserved 0x16 Reserved 0x17 Reserved 0x18 0x1F Reserved Table 245 PCI Interrupt Mask Offset 0x31D5C Bits Field Type Description InitVal 26 0 Mask RW Mask bit per cause bit If a bit is set to 1 the corresponding event is 0x0 enabled Mask does not affect setting of the Interrupt Cause register bits it only affects the assertion of interrupt 31 27 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 196 88F5182 marveL Open Source Community Programmer s User Guide Table 246 PCI Error Address Low Offset 0x31D40 Bits Field Type Description InitVal 31 0 ErrAddr RO PCI address bits 31 0 are latched as a result of an error latched in the 0x0 Interrupt Cause Register Upon address latched no new address can be registered due to another error until the register is being read An error which is masked in the Interrupt Mask Register will not set this register In case of a split completion by an external completer with any error the PCI address error samples the address of split completion NOTE Do not compare the four least significant bits of the seven address bits of the completion address to the original crossbar request address The master always issues transaction on the PCI with address aligned to 32 bits In case the inte
135. 0x73000 0x7307C NOTE MIB counters are ROC Read Only Clear Read from MIB counter resets the value to 0 Offset Width Counter Name Description 0x10 32 GoodFramesReceived The number of Ethernet frames received that are not Bad Ethernet frames or MAC Control packets NOTE This does include Bridge Control packets OxC 32 MACTransError The number of frames not transmitted correctly or dropped due to internal MAC transmit error for example underrun 0x14 32 BadFramesReceived The number of bad Ethernet frames received 0x18 32 BroadcastFramesRe The number of good frames received that had a Broadcast desti ceived nation MAC address 0x1C 32 MulticastFramesReceived The number of good frames received that had a Multicast destina tion MAC address NOTE This does not include 802 3 Flow Control messages as they are considered MAC Control messages 0x20 32 Frames64Octets The total number of received and transmitted Good and Bad frames that are 64 bytes in size or are between the minimum size as specified in lt RxMFS 6 2 gt in the Port Rx Minimal Frame Size PMFS Table 404 p 295 register and 64 bytes NOTE This does not include MAC Control frames 0x24 32 Frames65to127Octets The total number of received and transmitted Good and Bad frames that are 65 to 127 bytes in size NOTE This does not include MAC Control frames 0x28 32 Frames128to255Octets The total number of received an
136. 0x82010 Port 1 0x84010 EDMA Request Queue In Pointer Register nennen 233 Offset Port 0 0x82014 Port 1 0x84014 EDMA Request Queue Out Pointer Register 234 Offset Port 0 0x82018 Port 1 0x84018 EDMA Response Queue Base Address High Register sssssseeeeenee 234 Offset Port 0 0x8201C Port 1 0x8401C EDMA Response Queue In Pointer Register 234 Offset Port 0 0x82020 Port 1 0x84020 EDMA Response Queue Out Pointer Register nennen 235 Offset Port 0 0x82024 Port 1 0x84024 EDMA Command Register erret cavhovectsceepitnenevesceuteoascuven schunssuctescavecus ESO 236 Offset Port 0 0x82028 Port 1 0x84028 EDMA Test Control Register oreet E re Roe b ina 237 Offset Port 0 0x8202C Port 1 0x8402C EDMA Status Register ipo obe ees o extre i de Fee bn t reb tds ee o CE en n ene 238 Offset Port 0 0x82030 Port 1 0x84030 EDMA IORady Timeout Hegtster Ask 239 Offset Port 0 0x82034 Port 1 0x84034 EDMA Command Delay Threshold Register A 239 Offset Port 0 0x82040 Port 1 0x84040 EDMA Halt Conditions Register AAA 239 Offset Port 0 0x82060 Port 1 0x84060 EDMA NCQO Done TCQ0 Outstanding Status Heiser 240 Offset Port 0 0x82094 Port 1 0x84094 EDMA NCQ1 Done TCQ1 Outstanding Status Register 240 Offset Port 0 0x82098 Port 1 0x84098 EDMA NCQ2 Done TCQ2 Outstanding Status Heiser 240 Offset Port 0 0x8209C Port 1 0x8409C Copyright 2007 Marvell Doc No MV
137. 0x84304 NOTE A write of 1 clears the bits in this register A write of 0 has no affect Bits Name Type Description InitVal 0 Reserved RES Reserved 0x0 1 M RW Recovered communication error 0x0 Communication between the device and host was temporarily lost but was re established This can arise from a device temporarily being removed from a temporary loss of PHY synchronization or from other causes and may be derived from the PhyNRdy signal between the PHY and Link layers No action is required by the host software since the operation ultimately succeeded however the host software may elect to track such recovered errors to gauge overall communications integrity and potentially step down the negotiated communication speed Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 246 88F5182 marveL Open Source Community Programmer s User Guide Table 338 SError Register Continued Offset Port 0 0x82304 Port 1 0x84304 NOTE A write of 1 clears the bits in this register A write of 0 has no affect Bits Name Type Description InitVal 10 2 Reserved RES Reserved 0x0 15 11 Reserved RES Reserved 0x0 16 N RW PhyRdy change 0x0 When set to 1 this bit indicates that the PhyRdy changed state since the last time this bit was cleared 17 Reserved RES Reserved 0x0 18 Ww RW Comm
138. 1 12 0x00000 Table 254 PCI CSn 0 Base Address High Offset 0x14 Bits Field Type Description InitVal 31 0 Base RW Base address 0x0 Corresponds to address bits 63 32 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell June 25 2007 Preliminary Page 201 Document Classification Proprietary Table 255 PCI CSn 1 Base Address Low PCI Interface Registers Offset 0x18 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Low 0x10000000 Table 256 PCI CSn 1 Base Address High Offset Ox1C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 Table 257 PCI Internal Registers Memory Mapped Base Address Low Offset 0x20 Bits Field Type Description InitVal 0 MemSpace RO Memory Space Indicator 0x0 2 1 Type RW BAR Type Initial Value InitVal 0x2 Located anywhere in 64 bit address space NOTE Read only from PCI 3 Prefetch RW Prefetch Enable 0x0 NOTE Read only from PCI 15 4 Reserved RES Read only 0x0 31 16 Base RW Base Address 0xD0000 Corresponds to address bits 31 16 Table 258 PCI Internal Registers Memory Mapped Base Address High Offset 0x24 Bits Field Type Description InitVal 31 0 Base RW Base address 0x0 Corresponds to address bits 63 32 Copyright 2007
139. 130 00 Rev 0 5 Page 369 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Table 545 XOR Engine Interrupt Cause XEICR Continued Offset 0x60930 XOR Engine Registers Bit Field Type Description InitVal 9 XbarErrO RW Crossbar Parity error 0x0 Caused by erroneous read response from the Crossbar 15 10 Reserved RO Reserved 0x0 25 16 Channel 1 CO Same for XOR Engine channel 1 0x0 31 26 Reserved RO Reserved 0x0 1 All cause bits are clear only They are set to 1 upon an interrupt event and cleared when the software writes a value of 0 Writing 1 has no affect don t care XOR Engine will disregard such write attempts Table 546 XOR Engine Interrupt Mask XEIMR Offset 0x60940 Bit Field Type Description InitVal 0 EODMask0 RW If set to 1 EOD interrupt is enabled 0x0 1 EOCMask0 RW If set to 1 EOC interrupt is enabled 0x0 2 StoppedMask0O RW If set to 1 Stopped interrupt is enabled 0x0 3 PauseMaskO RW If set to 1 Paused interrupt is enabled 0x0 4 AddrDecodeMaskO RW If set to 1 AddrDecode interrupt is enabled 0x0 5 AccProtMaskO RW If set to 1 AccProt interrupt is enabled 0x0 6 WrProtMaskO RW If set to 1 WrProt interrupt is enabled 0x0 7 OwnMaskO RW If set to 1 OwnErr interrupt is enabled 0x0 8 IntParityMaskO RW If set to 1 IntParityErr interrupt is enabled 0x0 9 X
140. 175 Offset 0x30D24 Table 197 Expansion ROM BAR SIZOG tren pane rrr retreat aec tarnanta igap iiaea denser ivis eases dyed aein yoia 175 Offset OX30D2C Table 198 Base Address Registers Enable seen enne trennen enne 175 Offset 0x30C3C Table 199 CSn 0 Base Address Rema nnne nennen nnne ntn rennes ntn entres enne nnne 176 Offset 0x30C48 Table 200 CSn 1 Base Address Remap ccccecesceeeeeeceeeeeeaeeeeaeeeeeaeeseaeeeseaeeseaeeeeaeeesaaeeseaeeeseaeeseaeeseaeeseaeeseeeeseaeess 177 Offset 0x30D48 Table 201 CSn 2 Base Address Hemap nnne nennen nnne nter enrnretnns etre senes rennen 177 Offset 0x30C4C Table 202 CSn 3 Base Address Rema enne enne nnnennnnnentnns ennt ri trn sete sr nnn see nnnei 177 Offset 0x30D4C Table 203 DevCSn 0 Base Address Hemap nennen nennen enne nnni nnns rnnt 177 Offset 0x30C50 Table 204 DevCSn 1 Base Address Hemap 177 Offset 0x30D50 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 71 Document Classification Proprietary June 25 2007 Preliminary Table 205 Table 206 Table 207 Table 208 Table 209 Table 210 Table 211 Table 212 Table 213 Table 214 Table 215 Table 216 Table 217 Table 218 Table 219 Table 220 Table 221 Table 222 Table 223 Table 224 Table 225 Table 226 Table 227 Table 228 DevCSn 2 Base Address Remap Offset OX80D58
141. 182 contains a 26 bit General Purpose Port UO GPIO The GPIO interface provides the following features N Note Each of the GPIO pins can be assigned to act as a general purpose input or output pin A dedicated register provides the GPIO input value Each of the GPIO input pins can be programmed to generate an Edge sensitive or a Level sensitive maskable interrupt A dedicated register provides the GPIO output value Each of the GPIO outputs can be programmed for the LED to blink every 100 ms The GPIO interface is multiplexed on the external pins as described in Section A 18 1 MPP Registers on page 384 For the 88F5182 GPIO registers see Table 564 GPIO Registers Map on page 380 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 58 88F5182 marveL Open Source Community Programmer s User Guide Section 17 Interrupt Controller 17 1 Functional Description The 88F5182 includes an interrupt controller that routes internal interrupt requests as well as external interrupt requests GPIOs to the Marvell processor core The 88F5182 interrupt controller drives two interrupt signals to the Marvell CPU core FIQ high priority and IRQ regular priority All interrupts are level sensitive The interrupt is kept active as long as there is at least one non masked cause bit set in the Interrupt Cause register The 88F5182
142. 2 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 152 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 154 PCI Express Capability List Pointer Register Offset 0x40034 Configuration 0x34 Bits Field Type Description InitVal 7 0 CapPtr RO Capability List Pointer 0x40 The current value in this field points to the PCI Power Management capabil ity set in the PCI Express Power Management Capability Header Register Table 156 p 153 at offset 0x40 31 8 Reserved RSVD Reserved 0x0 Table 155 PCI Express Interrupt Pin and Line Register Offset 0x4003C Configuration 0x3C Bits Field Type Description InitVal 7 0 IntLine RW Provides interrupt line routing information 0x00 15 8 IntPin RO Indicates that 88F5182 is using INTA in the interrupt emulation messages 0x01 31 16 Reserved RSVD Does not apply to PCI Express 0x0 This field is hardwired to 0 Table 156 PCI Express Power Management Capability Header Register Offset 0x40040 Configuration 0x40 Bits Field Type Description InitVal 7 0 CapID RO Capability ID 0x01 Current value identifies the PCI Power Management capability 15 8 NextPtr RO Next Item Pointer 0x50 Current value points to MSI capability 18 16 PMCVer RO PCI Power Manageme
143. 20 p 186 PCI P2P Configuration 0x31D14 Table 221 p 187 PCI Access Control Base 0 Low 0x31E00 Table 222 p 187 PCI Access Control Base 0 High 0x31E04 Table 223 p 188 PCI Access Control Size 0 0x31E08 Table 224 p 188 PCI Access Control Base 1 Low 0x31E10 Table 225 p 189 PCI Access Control Base 1 High 0x31E14 Table 226 p 189 PCI Access Control Size 1 0x31E18 Table 227 p 190 PCI Access Control Base 2 Low 0x31E20 Table 228 p 190 PCI Access Control Base 2 High 0x31E24 Table 229 p 190 PCI Access Control Size 2 0x31E28 Table 230 p 190 PCI Access Control Base 3 Low 0x31E30 Table 231 p 190 PCI Access Control Base 3 High 0x31E34 Table 232 p 191 PCI Access Control Size 3 0x31E38 Table 233 p 191 PCI Access Control Base 4 Low 0x31E40 Table 234 p 191 PCI Access Control Base 4 High 0x31E44 Table 235 p 191 PCI Access Control Size 4 Ox31E48 Table 236 p 191 PCI Access Control Base 5 Low Ox31E50 Table 237 p 192 PCI Access Control Base 5 High Ox31E54 Table 238 p 192 PCI Access Control Size 5 Ox31E58 Table 239 p 192 Register Offsets Page PCI Configuration Address 0x30C78 Table 240 p 192 PCI Configuration Data 0x30C7C Table 241 p 193 PCI Interrupt Acknowledge 0x30C34 Table 242 p 193 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 88F5182 marveL Open Source Community Programmer s User Gu
144. 2007 Preliminary Document Classification Proprietary Page 270 88F5182 marveL Open Source Community Programmer s User Guide Table 367 Ethernet Unit Default Address EUDA Offset 0x72008 Bits Field Type Description InitVal 31 0 DAR RW Specifies the Default Address to which the Ethernet unit directs no match 0x0 multiple address hits and address protect violations Occurrence of this event may be the result of programming errors of the descriptor pointers or buffer pointers Table 368 Ethernet Unit Default ID EUDID Offset 0x7200C Bits Field Type Description InitVal 3 0 DIDR RW Specifies the ID of the target unit to which the Ethernet unit directs no match 0x0 and address protect violations Identical to Base Address register s lt Target gt field encoding 11 4 DATTR RW Specifies the Default Attribute of the target unit to which the Ethernet unit OxE directs no match and address protect violations Identical to Base Address register s lt Attr gt field encoding 31 12 Reserved RO Read Only 0x0 Table 369 Ethernet Unit Reserved EU Offset 0x72014 Bits Field Type Description InitVal 0 Fast MDC RW Use Faster MDC 0x0 0 Normal mode 1 MDC clock will be set to TCLK dividing by 16 1 ACCS RW Accelerate Slot Time 0x0 0 Normal mode 1 MDC clock will be set to TCLK dividing by 8 31 2 Reserved RO Read On
145. 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 479 AES Decryption Key Column 7 Register Offset 0x9DDCO Bits Field Type Description InitVal 31 0 AesDecKeyCol7 RW Contains Column 7 of the AES decryption key 0x0 Table 480 AES Decryption Key Column 6 Register Offset OX9DDCA Bits Field Type Description InitVal 31 0 AesDecKeyCol6 DW Contains Column 6 of the AES decryption key 0x0 Table 481 AES Decryption Key Column 5 Register Offset Ox9DDC8 Bits Field Type Description InitVal 31 0 AesDecKeyColb RW Contains Column 5 of the AES decryption key 0x0 Table 482 AES Decryption Key Column 4 Register Offset OX9DDCC Bits Field Type Description InitVal 31 0 AesDecKeyCol4 RW Contains Column 4 of the AES decryption key 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 328 88F5182 marveL Open Source Community Programmer s User Guide Table 483 AES Decryption Command Register Offset Ox9DDFO Bits Field Type Description InitVal 1 0 AesDecKeyMode RW These bits specify what AES128 key size is used 0x0 00 128 bit key 01 192 bit key 10 256 bit key 11 Reserved 2 AesDecMakeKey RW Thi
146. 316 DES Data Buffer Low Register Ox9DD70 Table 438 p 316 DES Data Buffer High Register Ox9DD74 Table 439 p 316 DES Initial Value Low Register Ox9DD40 Table 440 p 316 DES Initial Value High Register Ox9DD44 Table 441 p 317 DES Key0 Low Register Ox9DD48 Table 442 p 317 DES Key0 High Register Ox9DD4C Table 443 p 317 DES Key1 Low Register Ox9DD50 Table 444 p 317 DES Key1 High Register Ox9DD54 Table 445 p 317 DES Key2 Low Register Ox9DD60 Table 446 p 318 DES Key High Register Ox9DD64 Table 447 p 318 DES Command Register Ox9DD58 Table 448 p 318 SHA 1 and MD5 Interface Registers SHA 1 MD5 Data In Register Ox9DD38 Table 449 p 319 SHA 1 MD5 Bit Count Low Register Ox9DD20 Table 450 p 319 SHA 1 MD5 Bit Count High Register Ox9DD24 Table 451 p 319 SHA 1 MD5 Initial Value Digest A Register 0x9DD00 Table 452 p 320 SHA 1 MD5 Initial Value Digest B Register 0x9DD04 Table 453 p 320 SHA 1 MD5 Initial Value Digest C Register 0x9DD08 Table 454 p 320 SHA 1 MD5 Initial Value Digest D Register Ox9DDOC Table 455 p 320 SHA 1 Initial Value Digest E Register Ox9DD10 Table 456 p 320 SHA 1 MD5 Authentication Command Register Ox9DD18 Table 457 p 321 AES Encryption Interface Registers AES Encryption Data In Out Column 3 Register Ox9DDAO Table 458 p 322 AES Encryption Data In Out Column 2 Register Ox9DDA4 Table 459 p 322 AES Encryption Data In Out Column 1 Register Ox9DDA8 Table 460 p 323 AES Encryption Data In Out Column 0 RegisterA Ox
147. 4 Table 105 Table 106 A 6 Table 108 List of Registers DDR2 SDRAM ODT Control High Register sssssseseeeeneneeneeneenrennrenennrenrennennns 123 Offset 0x01498 DDR2 SDRAM ODT Control Register AAA 124 Offset 0x0149C DDR SDRAM Interface Mbus Control Low Register AA 125 Offset 0x01430 DDR SDRAM Interface Mbus Control High Register AA 125 Offset 0x01434 DDR SDRAM Interface Mbus Timeout Register sess ementi 126 Offset 0x01438 DDR SDRAM MMask Register 5 oett ten eterni e ettet me Ere enne nnde da 126 Offset 0x014B0 PCI Express Interface Registers eeseeeseseeeeeses essen eeee eene nnne nnn nn nnns nnnn nnn 127 PCI Express BAR1 Control Register Offset 0x41804 Table 109 PCI Express BAR2 Control Register A 129 Offset 0x41808 Table 110 PCI Express Expansion ROM BAR Control Register nennen 130 Offset 0x4180C Table 111 PCI Express Configuration Address Heglsier enne nennen nennen 130 Offset 0x418F8 Table 112 PCI Express Configuration Data Register sssessssessseeeeeeeeeennenen nennen nennen renes 131 Offset 0x418FC Table 113 POI Express Interrupt Cause operto eene odere ca Det daeadenn diena 131 Offset 0x41900 Table 114 PCI Express Interrupt Mask reen 134 Offset 0x41910 Table 115 PCI Express Window0 Control Hegtsier A 134 Offset 0x41820 Table 116 PCI Express Window0 Base Register rett
148. 48 Window5 Control Register eessssssessesesseeeeee eene nennen nnne mene trennen tentent nennen 96 Offset 0x20050 Table49 Window5 Base Hegister eere nennt tiet nnne tette tbe ark bos dbe Eo PR sms ia Paene inet baies 96 Offset 0x20054 Table 50 Window6 Control Register nter eni ee ter ea edea e Yee e aadis 96 Offset 0x20060 Table 51 Window6 Base Register enne tnet nennen nennen nennen 97 Offset 0x20064 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 65 Document Classification Proprietary June 25 2007 Preliminary List of Registers Table 52 Window7 Control Heoieier AA 97 Offset 0x20070 Table 53 Window7 Base Ftegister iere esee er SEENEN a Exe ars e ee dct rade rou de dns 98 Offset 0x20074 Table 54 88F5182 Internal Registers Base Address Register A 98 Offset 0x20080 Table 55 CPU Configuration Register eeseseseseeeeeeneneeneenne nne nennen enne trennen emnes 99 Offset 0x20100 Table 56 CPU Control and Status Hegleter nennen een eennee neret et rretren rennen nnns 100 Offset 0x20104 Table 57 RSTOUTn Mask Register cre iei etre trainee e ce entes aee edo Eege 100 Offset 0x20108 Table 58 System Soft Reset Register e a a aare T a a a E E a aa aa E enne mener mener mre 101 Offset 0x2010C Table 59 Local to System Bridge Interrupt Cause Register 0 0 0 0 ee ee ee cece eens eter eee seas eeaeeeeeeeaeseeeesaes
149. 4DqDq RW DDR Controller I O Buffer ODT Select for DQ DOS and DM sDm 0x0 0x0 Turned off 0x1 150 ohm 0x2 75 ohm 0x3 50 ohm 31 12 Reserved RO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 124 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 103 DDR SDRAM Interface Mbus Control Low Register Offset 0x01430 Bits Field Type Description InitVal 3 0 ArbO RW Slice 0 of device controller Mbus SDRAM arbiter 0x0 7 4 Arb1 RW Slice 1 of device controller Mbus SDRAM arbiter 0x1 11 8 Arb2 RW Slice 2 of device controller Mbus SDRAM arbiter 0x2 15 12 Arb3 RW Slice 3 of device controller Mbus SDRAM arbiter 0x3 19 16 Arb4 RW Slice 4 of device controller Mbus SDRAM arbiter 0x4 23 20 Arb5 RW Slice 5 of device controller Mbus SDRAM arbiter 0x5 27 24 Arb6 RW Slice 6 of device controller Mbus SDRAM arbiter 0x6 31 28 Arb7 RW Slice 7 of device controller Mbus SDRAM arbiter 0x7 Table 104 DDR SDRAM Interface Mbus Control High Register Offset 0x01434 Bits Field Type Description InitVal 3 0 Arb8 RW Slice 8 of device controller Mbus SDRAM arbiter 0x8 7 4 Arb9 RW Slice 9 of device controller Mbus SDRAM arbiter 0x9 11 8 Arb10 RW Slice 10 of device controller Mbus SDRAM arbiter OxA 15 12 Arb11 RW Slic
150. 50 Port 1 0x84050 NOTE After any modification in this register the host must set bit 2 lt eAtaRst gt field in the EDMA Command Register Table 321 p 236 Bits Field Type InitVal Description 5 4 RefClkFeedDiv RW 0x01 PHY PLL Reference clock feedback divider Its setting is configured according to bit lt Gen2En gt When Gen2En is set to 0 00 Divided by 50 01 Divided by 60 Used when PHY PLL Reference clock is 25 MHz 10 Divided by 75 Used when PHY PLL Reference clock is 20 MHz 30 MHz or 40 MHz 11 Divided by 90 When Gen2En is set to 1 00 Divided by 100 01 Divided by 120 Used when PHY PLL Reference clock is 25 MHz 10 Divided by 150 Used when PHY PLL Reference clock is 20 MHz 30 MHz or 40 MHz 11 Divided by 180 NOTE Must be set to 01 PhySSCEn RW 0x0 SSC enable 0 SSC disable 1 SSC enable Gen2En RW 0x1 Generation 2 communication speed support 0 Disabled 1 Enabled CommEn RW 0x0 PHY communication enable signal to override field lt DET gt field in the SCon trol Register Table 340 p 248 setting 0 DET setting is not overridden 1 If DET value is 0x4 its value is overridden with a value of 0x0 PhyShutdown RW 0x0 PHY shutdown 0 PHY is functional 1 PHY is in Shutdown mode 10 TargetMode RW 0x0 Target Mode This bit defines the Serial ATA port that functions as a target during Target
151. 501B0 Port1 0xA01BO ENDPTFLUSH PortO 0x501B4 Port1 0xA01B4 ENDPTSTATUS PortO 0x501B8 Port1 0xA01B8 ENDPTCOMPLETE Port0 0x501BC Port1 OXA01BC ENDPTCTRLO Port0 0x501C0 Port1 0xA01CO ENDPTCTRL1 Port0 0x501C4 Port1 0xA01C4 ENDPTCTRL2 Port0 0x501C8 Port1 0xA01C8 ENDPTCTRL3 Pom 0x501CC Port1 OXA01CC Table 420 USB 2 0 Bridge Register Map Port0 0x50300 0x503FF Porti 0xA0300 0xA03FF Register Offset Page Bridge Control And Status Registers USB 2 0 Bridge Control Register PortO 0x50300 Table 422 p 307 Porti 0xA0300 Bridge Interrupt and Error Registers USB 2 0 Bridge Interrupt Cause Register PortO 0x50310 Table 423 p 307 Port1 0xA0310 USB 2 0 Bridge Interrupt Mask Register PortO 0x50314 Table 424 p 308 Port1 0xA0314 USB 2 0 Bridge Error Address Register Port0 0x5031C Table 425 p 308 Port1 OXA031C Bridge Address Decoding Registers USB 2 0 Window0 Control Register Pont 0x50320 Table 426 p 309 Port1 0xA0320 USB 2 0 Window0 Base Register Pom 0x50324 Table 427 p 309 Port1 0xA0324 USB 2 0 Window1 Control Register Pont 0x50330 Table 428 p 309 Port1 0xA0330 USB 2 0 Window1 Base Register Port0 0x50334 Table 429 p 310 Port1 0xA0334 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 306 e MARVELL 88F5182 Open Source Commu
152. 56 bit key width Block data Block of 512 bits in the authentication engine CBC Cipher Block Chain CFB Cipher Feedback DES Data Encryption Standard 3DES Triple Data Encryption Standard ECB Electronic Code Book EDE Encryption Decryption Encryption EEE Encryption Encryption Encryption IV Initial Vector Initial Value MD5 Message Digest 5 OFB Output Feedback SHA 1 Secure Hash Algorithm 1 WO W15 Designates the 16 words in an authentication input data block WO is the first word and W15 is the last word WORD 32 bit Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 37 Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engines and Security Accelerator Cryptographic Engines Operational Description 10 1 2 Functionality There are four cryptographic engines that operate independently They implement the following algorithms e Encryption DES ECB and CBC mode and Triple DES ECB and CBC mode EDE and EEE e Encryption AES128 128 AES128 192 AES128 256 e Authentication SHA 1 and MD5 10 1 3 Cryptographic Engine Features e Authentication in the MD5 or SHA algorithm selectable by the user e Authentication Continue mode enables chaining between blocks e Authentication Automatic Padding mode e Encryption and Decryption in Single DES Single ECB or Block CBC mode or 3DES EEE or EDE mode selectable by the user e DES write pipeline e Optimal external update of Authentication
153. 6 Pass 2 RW Determines whether to filter or accept for pointer index 2 N A 0 Reject filter frame 1 Accept frame 19 17 Queue 2 RW For pointer index 2 Determines the Queue number if Pass 2 1 N A 20 Reserved 2 RW Reserved N A Must be set to 0 23 21 Unused 2 RO Reserved N A 24 Pass 3 RW Determines whether to filter or accept for pointer index 3 N A 0 Reject filter frame 1 Accept frame 27 25 Queue 3 RW For pointer index 3 Determines the Queue number if Pass 3 1 N A 28 Reserved 3 RW Reserved N A Must be set to 0 31 29 Unused 3 RO Reserved N A A 9 3 Port MIB Counter Register Table 418 MAC MIB Counters Offset 0x73000 0x7307C NOTE MIB counters are ROC Read Only Clear Read from MIB counter resets the value to 0 Offset Width Counter Name Description 0x0 64 GoodOctetsReceived The sum of lengths of all good Ethernet frames received frames that are not Bad frames NOR MAC Control frames NOTE This does not include 802 3x pause messages but does include bridge control packets like LCAP and BPDU 0x8 32 BadOctetsReceived The sum of lengths of all bad Ethernet frames received Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 302 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 418 MAC MIB Counters Continued Offset
154. 8 Table 578 Sample at Heset Hagister iscritti eed GREASE E E CHR CLR aa anaa EUH R PEE SR Aa e EE SAP REX RA SE PAR TAREA 387 Offset 0x10010 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 87 Document Classification Proprietary June 25 2007 Preliminary 88F5182 Register Set Register Description Appendix A 88F5182 Register Set This appendix provides full definitions for the 88F5182 registers A 1 Register Description All registers are 32 bits wide 31 0 The 88F5182 registers use the PCI Byte Ordering Little Endian in which the Most Significant Byte MSB of a multi byte expression is located in the highest address The bits within a given byte are always ordered so that Bit 7 is the Most Significant Bit MSb and Bit 0 is the Least Significant Bit LSb A 2 Register Types The 88F5182 registers are made up of up to 32 bit fields where each field is associated with one or more bits Each of these register fields have a unique programming functionality and their operation is defined by the field s type The following list describes the function of each type Type Description RES Reserved for future use All reserved bits are read as zero unless otherwise noted RO Read Only Writing to this type of field may cause unpredictable results ROC Read Only Clear After read the register field is cleared to zero Writing to this type of field may cause unpredictable results RW Read and Writ
155. 82 11 DstateChange RWOC Dstate Change Indication 0x0 Any change in the Dstate asserts this bit NOTE This bit is relevant only for Endpoint 12 BIST RWOC PCI Express BIST activated 0x0 BIST is not supported 15 13 Reserved RWOC Reserved 0x0 16 RevErrFatal RWOC Received ERR FATAL message 0x0 Set when a downstream device detected the error and sent an error mes sage upstream Relevant for Root Complex only 17 RevErrNonFatal RWOC Received ERR_NONFATAL message 0x0 Set when a downstream device detected the error and sent an error mes sage upstream Relevant for Root Complex only 18 RevErrCor RWOC Received ERR COR message 0x0 Set when a downstream device detected the error and sent an error mes sage upstream Relevant for Root Complex only 19 RcvCRS RWOC Received CRS completion status 0x0 A downstream PCI Express device can respond to a configuration request with CRS Configuration Request Retry Status if it is not ready yet to serve the request RcvCRS interrupt is set when such a completion status is received 20 PexSlvHot RWOC Received Hot Reset Indication Reset 0x0 The bit sets when a hot reset indication is received from the opposite device on the PCI Express port NOTE Sticky bit not initialized by reset 21 PexSlvDisLink RWOC Slave Disable Link Indication 0x0 The bit sets when the opposite device on the PCI Express port is acting as a disable link master and link was disabled NOTE Sticky bit not initialized by reset
156. 91 and Appendix A 5 1 DDR SDRAM Controller Address Decode Registers on page 110 For default address map see Table 1 88F5182 Default Address Map on page 14 2 2 PCI Express Address Map The PCI Express interface address map consists of three BARs that map the chip address space One BAR is dedicated for the chip internal registers while the other two are further sub decoded by six programmable address windows to the different interfaces of the chip See Appendix A 6 1 PCI Express BAR Control Registers on page 129 For the default address map see Table 1 with following exceptions By default access from the PCI Express interface to PCI interface is disabled By default access from the PCI Express to Device CSO and Device CS1 is disabled 2 3 PCI Address Map The PCI interface address map consists of 12 BARS address windows for the different interfaces For the default address map see Table 1 with following exceptions By default access from the PCI interface to the PCI Express interface is disabled By default access from the PCI interface to Device CSO and Device CS1 is disabled By default I O access from the PCI interface to the chip internal registers is disabled Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 13 Document Classification Proprietary June 25 2007 Preliminary Address Map SATA Address Map 2 4 SATA Address Map The SATAHC interface address map consists of four programma
157. 91 on page 215 15 8 Sector Count This field contains the contents of the Sector Count exp Sector Count Previous Exp register of the Shadow Register Block 31 16 Reserved Reserved When the EDMA is in Non Queued mode The following commands are supported READ DMA READ DMA EXT READ STREAM DMA WRITE DMA WRITE DMA EXT WRITE DMA FUA EXT WRITE STREAM DMA Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 28 88F5182 marveL Open Source Community Programmer s User Guide When the EDMA is in Queued mode The following commands are supported e READ DMA QUEUED e READ DMA QUEUED EXT e WRITE DMA QUEUED e WRITE DMA QUEUED EXT e WRITE DMA QUEUED FUA EXT When the EDMA is in Native Command Queuing mode The following commands are supported e Read FPDMA Queued e Write FPDMA Queued S Note Other commands cause unpredictable results 7 2 3 3 EDMA Physical Region Descriptors ePRD Table Data Structure The physical memory region to be transferred is described by the EDMA Physical Region Descriptor ePRD for DWORDs 0 3 The data transfer proceeds until all regions described by the ePRDs in the table have been transferred The starting address of this table must be 16B aligned i e bits 3 0 of the table base address must be 0x0 y Note The total number of bytes in the PRD table total byte count in DMA
158. 9DDAC Table 461 p 323 AES Encryption Key Column 3 Register Ox9DD90 Table 462 p 323 AES Encryption Key Column 2 Register Ox9DD94 Table 463 p 323 AES Encryption Key Column 1 Register Ox9DD98 Table 464 p 324 AES Encryption Key Column 0 Register Ox9DD9C Table 465 p 324 AES Encryption Key Column 7 Register Ox9DD80 Table 466 p 324 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 314 e 88F5182 marveL Open Source Community Programmer s User Guide Table 435 Cryptographic Engine and Security Accelerator Register Map Continued Register Offset Table Page AES Encryption Key Column 6 Register Ox9DD84 Table 467 p 324 AES Encryption Key Column 5 Register Ox9DD88 Table 468 p 325 AES Encryption Key Column 4 Register Ox9DD8C Table 468 p 325 AES Encryption Command Register Ox9DDBO Table 470 p 325 AES Decryption Interface Registers AES Decryption Data In Out Column 3 Register Ox9DDEO Table 471 p 326 AES Decryption Data In Out Column 2 Register Ox9DDE4 Table 472 p 326 AES Decryption Data In Out Column 1 Register Ox9DDE8 Table 473 p 326 AES Decryption Data In Out Column 0 Register Ox9DDEC Table 474 p 326 AES Decryption Key Column 3 Register Ox9DDDO Table 475 p 327 AES Decryption Key Column 2 Register Ox9DDD4 Table 476 p 327 AES Decryption Ke
159. A Controller Interface Registers Register Offsets Page Channel IDMA Byte Count Register Channel 0 0x60800 Channel 1 0x60804 Channel 2 0x60808 Channel 3 0x6080C Table 525 p 354 Channel IDMA Source Address Register Channel 0 0x60810 Channel 1 0x60814 Channel 2 0x60818 Channel 3 0x6081C Table 526 p 355 Channel IDMA Destination Address Register Channel 0 0x60820 Channel 1 0x60824 Channel 2 0x60828 Channel 3 0x6082C Table 527 p 355 Channel Next Descriptor Pointer Register Channel 0 0x60830 Channel 1 0x60834 Channel 2 0x60838 Channel 3 0x6083C Table 528 p 355 Channel Current Descriptor Pointer Register Channel 0 0x60870 Channel 1 0x60874 Channel 2 0x60878 Channel 3 0x6087C Table 529 p 355 Table 522 IDMA Address Decoding Register Map Register Offset s Page Base Address Register x BARO 0x60A00 BAR1 0x60A08 BAR2 0x60A10 BAR3 0x60A18 BAR4 0x60A20 BARS 0x60A28 BAR6 0x60A30 BAR7 0x60A38 Table 530 p 356 Size Register x SRO 0x60A04 SR1 Ox60A0C SR2 0x60A14 SR3 0x60A1C SR4 0x60A24 SR5 0x60A2C SR6 0x60A34 SR7 0x60A3C Table 531 p 356 High Address Remap x Register Register 0 0x60A60 Register 1 0x60A64 Register 2 0x60A68 Register 3 0x60A6C Table 532 p 356 Base Address Enable Register 0x60A80 Table 533 p 357 Channelx Access Protect Register Channel 0 0x60A70 Channel 1 0x6
160. AR signal 1 In case of erroneous data indication the PCI interface drives bad parity on the PAR signal PCI slave read data or PCI master write data 20 SSwapEn RW PCI Slave Swap Enable 0x0 0 PCI slave data swapping is determined via lt SByteSwap gt and lt SWordSwap gt bits bits 16 and 11 1 PCI slave data swapping is determined via lt PCISwap gt bits 7 6 in the PCI Access Control registers NOTE If PCI address does not match any of the Access Control windows the PCI slave data swapping works according to SByteSwap and lt SWordSwap gt bits even if the lt SSwapEn gt bit is set to 1 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 183 Document Classification Proprietary June 25 2007 Preliminary Table 215 PCI Command Continued PCI Interface Registers Offset 0x30C00 Bits Field Type Description InitVal 21 MSwapEn RW PCI Master Swap Enable 0x0 0 PCI master data swapping is determined via lt MByteSwap gt and MWordSwap bits bits 0 and 10 1 PCI master data swapping is determined via lt PClSwap gt bits in the different unit Base Address registers 23 22 Reserved RW Reserved 0x0 Must be 0x0 25 24 SIntSwap RW PCI Slave data swap control on PCI accesses to the 88F5182 internal 0x1 and configuration registers 00 Byte Swap 01 No swapping 10 Both byte and word swap 11 Word swap 27 26 Reserved RW Reserv
161. ATA port1 error 0x0 3 Sata1Done RO SATA porti command done 0x0 This bit is set when one of the following occurs g lt SaCrpb1Done DMA1Done gt of the SATAHC is set e lt SaDevlnterrupti gt of the SATAHC is set 4 Sata0DmaDone RO SATA port0 DMA done 0x0 This bit is set when both of the following occur e lt SaCrpbODone DMAODones gt field in Table 299 SATAHC Interrupt Cause Register on page 220 of SATAHC is set e lt SaDevinterrupt0 gt in Table 299 SATAHC Interrupt Cause Register on page 220 of the SATAHC is set Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 222 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 301 SATAHC Main Interrupt Cause Register Continued Offset 0x80020 NOTE The bits in this register mirror the interrupt indications coming from the other SATAHC interrupt cause registers Bits Field Type Description InitVal 5 Sata1DmaDone RO SATA port1 DMA done 0x0 This bit is set when both of the following occur e lt SaCrpb1Done DMA1Done gt of SATAHC is set e lt SaDevinterrupt1 gt of the SATAHC is set 6 7 Reserved RO Reserved 0x0 8 SataCoalDone RO SATA ports coalescing done 0x0 This bit is set when field lt SalntCoal gt of SATAHC is set NOTE SATA completion fields Sata0Done and lt SataiDone gt must be masked to use this bit 31 9 Reserved RO Reserved
162. Address Map Table 1 88F5182 Default Address Map Target Interface Target Target Address Address Range in Interface Interface Space Size Hexadecimal ID Attribute DDR SDRAM CS0 0 OxOE 256 MByte 0000 0000 0FFF FFFF DDR SDRAM CS1 0 0x0D 256 MByte 1000 0000 1FFF FFFF DDR SDRAM CS2 0 0x0B 256 MByte 2000 0000 2FFF FFFF DDR SDRAM CS3 0 0x07 256 MByte 3000 0000 3FFF FFFF Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 14 e 88F5182 E MARVELL Open Source Community Programmer s User Guide Table 1 88F5182 Default Address Map Continued Target Interface Target Target Address Address Range in Interface Interface Space Size Hexadecimal ID Attribute Reserved 1 GByte 4000 0000 7FFF FFFF PCI Express Memory 4 0x59 512 MByte 8000 0000 9FFF FFFF PCI Memory 3 0x59 512 MByte A000 0000 BFFF FFFF PCI Express I O 4 0x51 64 KByte C000 0000 C000 FFFF Reserved s S C001 0000 C7FF FFFF PCI I O 3 0x51 64 KByte C800 0000 C800 FFFF Security Accelerator Internal SRAM 9 0x00 64 KByte C801 0000 C801 FFFF Memory NOTE Only 8 KB SRAM NOTE There is no access to Security is implemented Accelerator Internal SRAM Memory from the PCI interface Reserved S C802 0000 CFFF FFFF Internal Address Space 1 MByte D000 0000 DOOF FFFF Reserved D010 0000 DFFF FFFF Device CSO 1
163. AesEncKeyCol3 RW Contains Column 3 of the AES encryption key or Column 3 of the decryption 0x0 key when AES Key Read Mode is set Table 463 AES Encryption Key Column 2 Register Offset Ox9DD94 Bits Field Type Description InitVal 31 0 AesEncKeyCol2 RW Contains Column 2 of the AES encryption key or Column 2 of the decryption 0x0 key when AES Key Read Mode is set Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 323 Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 464 AES Encryption Key Column 1 Register Offset Ox9DD98 Bits Field Type InitVal 31 0 AesEncKeyCol1 RW Contains Column 1 of the AES encryption key or Column 1 of the decryption 0x0 key when AES Key Read Mode is set Description Table 465 AES Encryption Key Column 0 Register Offset Ox9DD9C Bits Field Type Description InitVal 31 0 AesEncKeyCol0 RW Contains Column 0 of the AES encryption key or Column 0 of the decryption 0x0 key when AES Key Read Mode is set Table 466 AES Encryption Key Column 7 Register Offset Ox9DD80 Bits Field Type Description InitVal 31 0 AesEncKeyCol7 RW Contains Column 7 of the AES encryption key or Column 7 of the decryption 0x0 key when AES Key Read Mode is set Table 467 AES Encryption Key Column 6 Register Offset Ox9DD84
164. Alaska Fastwriter Datacom Systems on Silicon Libertas Link Street NetGX PHYAdvantage Prestera Raising The Technology Bar The Technology Within Virtual Cable Tester and Yukon are registered trademarks of Marvell Ants AnyVoltage Discovery DSP Switcher Feroceon GalNet GalTis Horizon Marvell Makes It All Possible RADLAN UniMAC and VCT are trademarks of Marvell All other trademarks are the property of their respective owners Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 2 Document Classification Proprietary June 25 2007 Preliminary MSE sss marveL Open Source Community Programmer s User Guide Table of Contents ul 9 ApOUt This DOGUMEM Ls 9 Related Documents EL 9 Document Conventions isipin eaaa aaa a aaa aaa aaa Eaa aa akeen aa 10 Section NEG 11 Section 2 Address Map EE 13 2 1 Marvell Processor Core Address Map 13 22 PCI Express Address Map eiae datnr etx edere Iuno v E nea due E Mu ox Dead 13 29 uel Eie BIET UR 13 24 SATA Address ET EEN 14 2 5 Gigabit Ethernet Address Map 14 2 6 USBO Address Map aen cire eee aee eed ue a aed odi red dex ebd sott und ue 14 2 7 USB1 Address Map iei Iit emet ete caet amieta pde e e Ee EE Rec deine E ere did 14 2 8 IDMA Address Map pL 14 29 XOR Address Map eiie Ete eer eed o daa EE EEN 14 2 10 Default Address Map cem cnt erem Lari ertet edu
165. Bit Field Description 29 0 Reserved Reserved 30 Success Successful descriptor execution indication Indicates whether the operation completed successfully 0 Completed unsuccessfully Transfer terminated before the whole byte count was transferred 1 Completed successfully The whole byte count transferred That field is updated upon closing the descriptor NOTE In ECC cleanup mode the success bit indicates successful execution even if ECC errors where found and not corrected 31 Own Ownership Bit Indicates whether the descriptor is owned by the CPU or the XOR engine 0 CPU owned 1 XOR engine owned That field is updated upon closing a descriptor XOR engine gives back ownership to the CPU by clearing the own bit Table 26 Descriptor CRC 32 Result Word Definition Bit Field Description 31 0 CRCresult Result of CRC 32 calculation Valid only in the last descriptor of a CRC source block chain after it was closed by the XOR engine NOTE Valid only in CRC mode Table 27 Descriptor Command Word Definition Bit Field Description 0 SrcoCmd Specifies the type of operation to be carried out on the data pointed by SA 0 Source Address 0 word of the descriptor 0x0 Null Command Data from Source will be disregarded in the current descriptor oper ation 0x1 XOR Command Data from source will be transferred and will be significant in the XOR calculation NOTE Relevant only on XOR oper
166. Bits Field Type Description InitVal 21 18 Lock RO When auto calibration is enabled this field represent the final locked 0x0 value of the driving strength Read Only 30 22 Reserved RES Reserved 0x0 31 WrEn RW PCI MPP Pads Calibration Register Write Enable 0x0 0 The register becomes read only except for bit 31 1 The register can be written to If set to 1 this register is writable If set to 0 the register becomes read only except for bit 31 Table 215 PCI Command Offset 0x30C00 Bits Field Type Description InitVal 0 MByteSwap RW PCI Master Byte Swap 0x1 When set to 0 the 88F5182 PCI master swaps the bytes of the incoming and outgoing PCI data swap the 8 bytes of a long word 3 1 Reserved RES Read Only 0x0 4 MWrCom RW PCI Master Write Combine Enable 0x1 When set to 1 write combining is enabled NOTE Write combining must not be enabled when using cache line size of 4 5 MRdCom RW PCI Master Read Combine Enable 0x1 When set to 1 read combining is enabled 6 MWrTrig RW PCI Master Write Trigger 0x1 0 Accesses the PCI bus only when the whole burst is written into the master write buffer 1 Accesses the PCI bus when the first data is written into the master write buffer 7 MRdTrig RW PCI Master Read Trigger 0x0 0 Returns read data to the initiating unit only when the whole burst is written into master read buffer 1 Returns read data to the initiating unit when the first rea
167. C Bits Field Type Description InitVal 2 0 IPG DATA RW Inter Packet Gap IPG 0x6 The step is 16 bit times The value may vary between 48 to 112 bit times GMII is full duplex only NOTE These bits may be changed only when PortEn field is set to 0 in the Port Control Register Port is disabled 31 3 Reserved RO Reserved 0x0 Table 385 VLAN EtherType EVLANE Offset 0x72410 Bits Field Type Description InitVal 15 0 VL EtherType RW The Ethertype for packets carrying the VLAN tag for 802 1p priority field 0x8100 processing and for continued parsing of the received frames Layer3 4 headers 31 16 Reserved RO Reserved 0x0 Table 386 MAC Address Low MACAL Offset 0x72414 Bits Field Type Description InitVal 15 0 MAC 15 0 RW The least significant bits of the MAC Address 0x0 Used for both flow control Pause frames as a source address as well as for address filtering 31 16 Reserved RO Read Only 0x0 Table 387 MAC Address High MACAH Offset 0x72418 Bits Field Type Description InitVal 31 0 MAC 47 16 RW The most significant bits of the MAC Address 0x0 Used for both flow control Pause frames as source address as well as for address filtering NOTE MAC 40 is the Multicast Unicast bit Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 280
168. C RW Enable Auto Negotiation for Flow Control 0x1 0 Enable 1 Disable When enabled the port can either advertise no flow control or symmetric flow control according to the Port Serial Control Register s lt Pause_Adv gt bit Asymmetric flow control advertisement is not supported Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 284 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 393 Port Serial Control PSC Continued Offset 0x7243C Bits Field Type Description InitVal 4 Pause Adv RW Flow control advertise Ox1 0 Advertise no flow control 1 Advertise symmetric flow control support in Auto Negotiation The port does not modify this bit as result of the Auto Negotiation process unlike the Port Status Register s lt EnFC gt bit which may be modified based on Auto Negotiation results 6 5 ForceFCMode RW The port will transmit Pause enable and disable frames depending on the 0x0 CPU writing 00 and 01 values conditioned with the flow control operation enable as reflected in the PSR EnFC bit being set in the following way 00 No Pause disable frames are sent However when the value of the field is changed by the CPU from 01 to 00 the port will send a single Pause enable packet timer 0x0000 to enable the other side to transmit 01 When this field is set to 01 value
169. C Table 68 p 106 CPU Watchdog Timer Reload Register 0x20320 Table 70 p 106 CPU Watchdog Timer Register 0x20324 Table 71 p 107 CPU Doorbell Registers Host to CPU Doorbell Register 0x20400 Table 72 p 107 Host to CPU Doorbell Mask Register 0x20404 Table 73 p 107 CPU to Host Doorbell Register 0x20408 Table 74 p 108 CPU to Host Doorbell Mask Register 0x2040C Table 75 p 108 A 4 1 CPU Address Map Registers Table 34 Window0 Control Register Offset 0x20000 Bits Field Type Description InitVal 0 win en RW Window0 Enable 0x1 0 Disabled Window is disabled 1 Enabled Window is enabled 3 1 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the target interface associated with this window 0x4 See Section 2 10 Default Address Map on page 14 NOTE Do not configure this field to the SDRAM Controller 15 8 Attr RW Specifies the target interface attributes associated with this window 0x59 See Section 2 10 Default Address Map on page 14 31 16 Size RW Window Size 0x1FFF Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window in 64 KByte granularity e g a value of OxOOFF specifies 256 16 MByte NOTE A value of 0x0 specifies 64 KByte size Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell June 25 2007 Preliminary Page 91 Doc
170. CI Express link down value does not affect CPU reset 1 CPU reset remains asserted when PCI Express link down is asserted 31 24 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 99 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers Table 56 CPU Control and Status Register Offset 0x20104 Bits Field Type Description InitVal 0 PCIDs RW When this bit is set to 1 0x1 PCI transaction towards 88F5182 address space is terminated with retry and PCI Express link negotiation is disabled This is used to block PCI Express from access 88F5182 while CPU boot is still in progress 0 PCI and PCI Express Enable 1 PCI and PCI Express Disable 1 CPUReset RO CPU Reset CPU When this bit is set to 1 the Marvell processor core is reset RW other 0x0 2 Selfint SC When set to 1 bit zCPUSelflnt in Local to System Bridge Interrupt Cause 0x0 Register gt is also set to 1 14 3 Reserved RSVD Reserved 0x0 15 BigEndian RO Big Endian 0x0 Reflects the value of the Big Endian field of the Marvell processor core CP15 register 0x0 Little Endian mode 0x1 Big Endian mode 31 16 Reserved RSVD Reserved 0x0 Table 57 RSTOUTn Mask Register Offset 0x20108 Bits Field Type Description InitVal 0 PexRstOutEn RW If set to 1 the 88F5182 asserts RSTOUTn upon rec
171. CR Continued Offset XORO 0x60910 XOR1 0x60914 Bits Field Type Description InitVal 15 RegAccProtect RW Internal Register Access protection Enable 0x1 0 Access protection mechanism is disabled 1 Access protection mechanism is enabled 31 16 Reserved RO Reserved 0x0 Table 544 XOR Engine 0 1 Activation XEXACTR Offset XORO 0x60920 XOR1 0x60924 Bits Field Type Description InitVal 0 XEStart WO 0 Clearing this bit has no meaning and will be disregarded by XOR 0x0 Engine 1 XOR Engine Start When the software sets this bit it activates the relevant XOR Engine channel Setting it again after XOR Engine entered inactive state initiates a new operation Setting it again after XOR Engine channel entered pause state re activates the channel and resumes the suspended operation execution After entering active state XOR Engine will signal the software by setting the XEactive bit NOTE Software must confirm that XOR Engine is inactive before setting XEstart Setting it when XOR Engine is active will be disregarded 1 XEstop WO 0 Clearing this bit has no meaning and will be disregarded by XOR 0x0 Engine 1 XOR Engine Stop When the software sets this bit it de activates the relevant XOR Engine channel XOR Engine will stop the current operation at the earliest opportunity refer to Stop Operation section After entering de active state XOR Engine will signal the soft
172. Collisions The number of collision events seen by the MAC 0x7C 32 Late Collision The number of late collisions seen by the MAC S Note The 802 3 Single Collision Frames and 802 3 Multiple Collision Frames are not implement Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 304 88F5182 MARVELL A 10 USB 2 0 Registers Open Source Community Programmer s User Guide S Note USB 2 0 Controller Registers 0x50000 0x502FF refer to ARC USB HS OTG High Speed Controller Core reference V 4 0 1 The base address for the controller registers is 0x50000 The offsets remain the same as in the above document Table 419 USB 2 0 Controller Register Map Offsets Port0 0x50000 0x502FF Porti 0xA0000 0xAO02FF Register Offset ID Pont 0x50000 Port1 0xA0000 HWGENERAL Port0 0x50004 Port1 0xA0004 HWHOST Port0 0x50008 Port 0xA0008 HWDEVICE Port0 0x5000C Port 0xA000C HWTXBUF Port0 0x50010 Port1 0xA0010 HWRXBUF PortO 0x50014 Port1 0xA0014 HWTTTXBUF Port0 0x50018 Port1 0xA0018 HWTTRXBUF Port0 0x5001C Port1 OxA001C Reserved Port0 0x50020 0x500FC Port1 0xA0020 0xA00FC CAPLENGTH Port0 0x50100 Port1 0xA0100 Reserved PortO 0x50101 Port1 0xAO101 HCIVERSION PortO 0x50102 Port1 0xA0102 HCSPARAMS Por
173. Configuration GESCHT 366 Offset XORO 0x60910 XOR1 0x60914 XOR Engine 0 1 Activation G SACTH nent nen retener rnrennet nitens terrere 368 Offset XORO 0x60920 XOR1 0x60924 XOR Engine Interrupt Cause EICH 369 Offset 0x60930 XOR Engine Interrupt Mask XEIMR A 370 Offset 0x60940 XOR Engine ege ER EN 371 Offset 0x60950 XOR Engine Error Address XEEAE ciiisean tbe boe sao Eee Era Ern ea EUER ed eae EES 371 Offset 0x60960 XOR Engine 0 1 Next Descriptor Pointer GGESNDPP nennen 372 Offset XORO 0x60B00 XOR1 0x60B04 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 85 Document Classification Proprietary June 25 2007 Preliminary Table 550 Table 551 Table 552 Table 553 Table 554 List of Registers XOR Engine 0 1 Current Descriptor Pointer GENCDPR nennen 372 Offset XORO 0x60B10 XOR1 0x60B14 XOR Engine 0 1 Byte Count XEXBCR sessi nnne nneennennerennetn retener erste 372 Offset XORO 0x60B20 XOR1 0x60B24 XOR Engine 0 1 Window Control NENWCH nee nnen ren rrenrs eter ennene 372 Offset XORO 0x60B40 XOR1 0x60B44 XOR Engine Base Address XEBARYX sssssssssssseeeeeseeeenee nente nennen rerit entretenir enes stent net 374 Offset XEBARO 0x60B50 XEBAR1 0x60B54 XEBAR2 0x60B58 XEBAR3 0x60B5C XEBAR4 0x60B60 XEBARS5 0x60B64 XEBAR6 0x60B68 XEBAR7 0x60B6C XOR Engine Size Mask XESMRX ua 374 Offset XESMRO 0x60B70 XESMR1 0x60B74
174. D 0x6 NOTE Read only from PCI 15 8 NextPtr RO Next Item Pointer 0x0 NOTE Read only from PCI This is a null pointer 16 Reserved RES Read only 0 0x0 17 EIM RW PCI_ENUMnh Interrupt Mask 0x0 0 Enable signal 1 Mask signal 18 Reserved RES Read only 0 0x0 19 LOO RW LED On Off 0x0 0 LED off 1 LED on 21 20 Reserved RES Read only 0 0x0 22 Ext RWC Extraction 0x0 Indicates that the board is about to be extracted set to 1 NOTE Write 1 to clear 23 Ins RWC Insertion 0x0 Indicates that the board has just been inserted set to 1 NOTE Write 1 to clear 31 24 Reserved RES Read only 0 0x0 A 7 6 Function 1 Configuration Registers Table 272 PCI CSn 2 Base Address Low Offset 0x10 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 Base Address Low 0x0 See Table 253 PCI CSn 0 Base Address Low on page 201 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 208 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 273 PCI CSn 2 Base Address High Offset 0x14 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 See Table 254 PCI CSn 0 Base Address High on page 201 Table 274 PCI CSn 3 Base Address Low Offset 0x18 Bits Field Typ
175. DAC Cycles The 88F5182 does not act as a target for Interrupt Acknowledge and Special cycles these cycles are ignored The 88F5182 does not support Exclusive Accesses It treats Locked transactions as regular transactions it does not support LOCKn pin Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 19 Document Classification Proprietary June 25 2007 Preliminary SATA II Interface Section 6 SATA II Interface This section provides technical information about the Serial ATA SATA II interface Based on the Marvell SATA host controllers SATAHC and SATA proven technology The 88F5182 is fully com patible with SATA II phase 1 0 specification Extension to SATA I specification The 88F5182 employs the latest SATA II PHY technology with 3 0 Gbps Gen2i and backwards compatible with 1 5 Gbps Gen1i SATA I The Marvell 88F5182 SATA II PHY accommodates the following features e SATA II 3 Gb s speed Backwards compatible with SATA PHYs and devices e Support Spread Spectrum Clocking SSC e Programmable PHY for industry leading backplane drive capability e SATA II power management compliant e SATA II Device Hot Swap compliant e Low power consumption Less then 200 mW per SATA Il PHY e PHY isolation Debug mode The SATA Il interface supports the following protocols e Non Data type command e PIO read command e PIO write command e DMA read command e DMA write command e Queued DMA rea
176. DMAQueLen gt 0 This field serves as the EDMA Request Queue Base Address 11 10 lt eEDMAQueLen gt 1 This field serves as the EDMA Request Queue In Pointer 6 5 31 12 eRqQBA 31 12 RW EDMA Request Queue Base Address corresponds to bits 31 12 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 233 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 317 EDMA Request Queue Out Pointer Register 0x82018 Port 1 0x84018 Offset Port 0 Bits Field Type Description InitVal 4 0 Reserved RES Reserved 0x0 9 5 eRqQOP RW EDMA Request Queue Out Pointer 0x0 The EDMA request queue out pointer is updated increment by the EDMA each time a CRQB is copied from the command queue into the EDMA inter nal memory The system driver reads this register to determine if the request queue is full 11 10 eRqQOP RW Function of this field depends on lt eEDMAQueLen gt 0x0 lt eEDMAQueLen gt 0 This field is reserved lt eEDMAQueLen gt 1 This field serve as EDMA Request Queue Out Pointer 6 5 31 12 Reserved RES Reserved 0x0 Table 318 EDMA Response Queue Base Address High Register 0x8201C Port 1 0x8401C Offset Port 0 Bits Field Type Description InitVal 31 0 eRpQBA 63 32 RW The EDMA Response Queue Base Address corresponds to bits 63 32 0x0 Table 319 EDMA Response Queue I
177. DMAs field in the Security Accelerator Configuration Register Table 487 p 331 is set to 0 lt AccAndIDMAInt1 gt is set after the security accelerator completes the process and data is valid in the local SRAM Doc No MV S400130 00 Rev 0 5 Page 333 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 490 Cryptographic Engines and Security Accelerator Interrupt Mask Register Offset 0x9DE24 Bits Field Type Description InitVal 31 0 Mask RW Mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of interrupt pins It does not affect the setting of bits in the Cause register Copyright O 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 334 88F5182 marveL Open Source Community Programmer s User Guide A 12 Two Wire Serial Interface TWSI Registers Table 491 TWSI Interface Register Map Register Offset Page TWSI Slave Address 0xt00 Table492 p335 TWSI Extended Slave Address 0x11010 Table 493 p 335 TWSI Data 0x11004 Table 494 p 336 TWSI Control 0x11008 Table 495 p 336 TWSI Status 0x1100C Table 496 p 338 TWSI Baud Rate 0x1100C Table 497 p 339 TWSI Soft Reset 0x1101C Table 498 p 339 A 12 1 TWSI Reg
178. Dade adeo REO EIE Ud 14 Section 3 DDR SDRAM Controller Interface eeeeeeeeeee eene 16 Section 4 PCI Express Interface eeeeeeeeeeeeeeeeeeeeeee eene eene nnne nnn nnne nnn nnn 17 Section 5 PCI len E 18 Dek Funcional Descriptio EE 18 5 2 PCI Master Operation eene le ee es es 18 5 3 PCI Target Operation e ier trino n d er ka c Ne aiaia iaaa aa adaa 19 Section 6 SATA M 9 lt a pe edid ein id ba ccce e SE Een eR usta EE PURUS 20 Section 7 Serial ATA Il Host Controller SATAHC eeessseeees 21 A SATAHG Block Diagram orte cete tete DEENEN abodes kanes ede nities SLE eee a due end 21 3 2 EDMA Operation acera Beetle a etaed sede UR a edo ada E Rn ande uod E eee daa Add au dd Fives 21 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 3 Document Classification Proprietary June 25 2007 Preliminary Table of Contents Section 8 Gigabit Ethernet Controller Interface e seeeeee esses 33 BI Functional Description i csi rientro aie tee edt aa a eue die 33 8 2 Port Features iuter E d ets 34 Section 9 USB 2 0 Intemace oo ihe ei ee EE 36 9 1 Functional Re lee EE 36 Section 10 Cryptographic Engines and Security Accelerator 37 10 1 F nctiorial OVervIeW otio re eit eto e iet edi Dee E a iie 37 10 2 Cryptographic Engines Operational Descri
179. Data Region High Address Register Port 0 0x82238 Port 1 0x84238 Table 336 p 245 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 216 MHZ sss marveL Open Source Community Programmer s User Guide A 8 6 Serial ATA Registers Map Table 293 Serial ATA Interface Registers Map Register Offset Table Page SStatus Register Port 0 0x82300 Port 1 0x84300 Table 337 p 246 SError Register Port 0 0x82304 Port 1 0x84304 Table 338 p 246 SError Interrupt Mask Register Port 0 0x82340 Port 1 0x84340 Table 339 p 248 SControl Register Port 0 0x82308 Port 1 0x84308 Table 340 p 248 LTMode Register Port 0 0x8230C Port 1 0x8430C Table 341 p 249 PHY Mode 3 Register Port 0 0x82310 Port 1 0x84310 Table 342 p 250 PHY Mode 4 Register Port 0 0x82314 Port 1 0x84314 Table 343 p 251 PHY Mode 1 Register Port 0 0x8232C Port 1 0x8432C Table 344 p 252 PHY Mode 2 Register Port 0 0x82330 Port 1 0x84330 Table 345 p 252 BIST Control Register Port 0 0x82334 Port 1 0x84334 Table 346 p 253 BIST DW1 Register Port 0 0x82338 Port 1 0x84338 Table 347 p 254 BIST DW2 Register Port 0 0x8233C Port 1 0x8433C Table 348 p 254 Serial ATA Interface Configuration Register Port 0 0x82050 Port 1 0x84050 Table 349 p 254 Serial ATA Int
180. Description InitVal 14 12 MaxRdRqSz RW Maximum Read Request Size 0x2 This field limits the 88F5182 maximum read request size as a requestor master 0 128B 1 256B 2 512B 3 1 KByte 4 2 KByte 5 4 KByte Other Reserved 15 Reserved RSVD Reserved 0x0 16 CorErrDet SC Correctable Error Detected 0x0 This bit indicates the status of the correctable errors detected by the 88F5182 Write 1 to clear 17 NFErrDet SC Non Fatal Error Detected 0x0 This bit indicates the status of the Non Fatal errors detected by the 88F5182 Write 1 to clear 18 FErrDet SC Fatal Error Detected 0x0 This bit indicates the status of the Fatal errors detected by the 88F5182 Write 1 to clear 19 URDet SC Unsupported Request Detected 0x0 This bit indicates that the 88F5182 received an unsupported request Write 1 to clear 20 Reserved RSVD Reserved 0x0 21 TransPend RO Transactions Pending 0x0 This bit indicates that the 88F5182 has issued Non Posted requests that have not been completed 0 Completed All NP requests have been completed or terminated by the Completion Timeout Mechanism 1 Uncompleted Not all NP requests have been completed or terminated 31 22 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 160 88F5182 marveL Open Source Community Programmer s User Guide Table 165 PCI Express Link Capabilities Regis
181. Detection Enable 0x0 If set to 1 broken master detection is enabled A master is said to be broken if it fails to respond to grant assertion within a window specified in BV field 2 Reserved RES Reserved 0x0 6 3 BV RW Broken Value 0x6 The value sets the maximum number of cycles that the arbiter waits for a PCI master to respond to its grant assertion If a PCI master fails to assert PCI FRAMEn within this time the PCI arbiter aborts the transaction and performs a new arbitration cycle and a maskable interrupt is generated NOTE Must be greater than 1 13 7 Reserved RES Reserved 0x0 20 14 PD 6 0 RW Parking Disable 0x0 When a PD bit is set to 1 parking on the associated PCI master is disabled NOTE The arbiter parks on the last master granted unless disabled through the PD bit Also if PD bits are all 1 the PCI arbiter parks on the internal PCI master PDO corresponds to the internal master PD1 corresponds to PCI_GNTn 30 21 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 186 88F5182 marveL Open Source Community Programmer s User Guide Table 220 PCI Arbiter Control Continued Offset 0x31D00 NOTE Arbiter setting can not be changed while in work It should only be set once Bits Field Type Description InitVal 31 EN RW Enable Internal Arb
182. Dis RW Interrupt Disable 0x0 This bit controls the ability of the 88F5182 to generate interrupt emulation messages When set interrupt messages are not generated 0 Enabled Interrupt messages enabled 1 Disabled Interrupt messages disabled Root Complex mode this bit has no affect received interrupt messages are still forwarded to the internal interface Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 147 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 143 PCI Express Command and Status Register Continued Offset 0x40004 Configuration 0x4 Bits Field Type Description InitVal 18 11 Reserved RSVD This bit is hardwired to 0 0x0 19 IntStat RO Interrupt Status 0x0 When set this bit indicates that an interrupt message is pending internally in the device 0 Disabled No interrupt asserted 1 Enabled Interrupt asserted 20 CapList RO Capability List Support 0x1 This bit indicates that the 88F5182 configuration header includes capability list This bit is hardwired to 1 since this is always supported in PCI Express 23 21 Reserved RSVD This bit is hardwired to 0 0x0 24 MasDataPerr SC Master Data Parity Error 0x0 Set by the 88F5182 when poisoned data is detected as a requestor mas ter Set when PErrEn bit 6 is set and either e Poisoned completion is received for the PCI E port or e Poisoned TLP is t
183. ER 344 Offset UART 0 0x1200C UART 1 0x1210C Modem Control Register MCR NENNEN 345 Offset UART 0 0x12010 UART 1 0x12110 Line status Fegister AE SEU EE 346 Offset UART 0 0x12014 UART 1 0x12114 Modem Status Register MSR rentes ertet rele Haee e ERR ener dera cba dax edens 347 Offset UART 0 0x12018 UART 1 0x12118 Scratch Pad Register CH ENEE trennen T 347 Offset UART 0 0x1201C UART 1 0x1211C Device Controller Registers eeeeeeeeeeeeeeee sees eee nenne nnn nnnm nnne tnnt nnn nnns 348 Device BankO Parameters Register Auen 348 Offset 0x1045C Device Bank Parameters Register eterne trennen rrennren rennes 349 Offset 0x10460 Device Bank Parameters Register esses nne emnes 350 Offset 0x10464 Boot Device Parameters Register sssssssssssssssssssseseseeeenen rennen nret rnnt en ree trennen 350 Offset 0x1046C NAND Flash Control Hegleter nao eee de ep oe etu shi ER etd de o p cte eau ea 350 Offset 0x104E8 Device Interface Control Io ic HEP Hera DE e eee 351 Offset 0x104C0 Device Interrupt Cause iiri nee rep pde er edel ea de ue ree ee ee d redi pu lib e pct e o due dee 352 Offset 0x104D0 Device Interrupt Mask Register x eth ede etie Per ES 352 Offset 0x104D4 IDMA Controller Interface Registers eese nennen nnn 353 Channel IDMA Byte Count Register Offset Channel 0 0x60800 Channel 1 0x60804
184. FFF See the CPU Timer 0 Register _FFFF A 4 5 CPU Doorbell Registers Table 72 Host to CPU Doorbell Register Offset 0x20400 Bits Field Type Description InitVal 31 0 HostlntCs Host RW1 Host Command Cause CPU RWC When this bit is not zero and the corresponding bit lt HostIntCsMask gt in the 0x0 Host to CPU Doorbell Mask Register is set bit lt Host2CPUDoorbell gt is set in the Main Interrupt Cause Register A Host write of 1 set the bits in this field A Host write of 0 has no affect An CPU write of 0 clear the bits in this field An CPU write of 1 has no affect Table 73 Host to CPU Doorbell Mask Register Offset 0x20404 Bits Field Type Description InitVal 31 0 HostIntCsMa RW Host Interrupt Cause Mask sk 0x0 Mask bit per each cause bit in the HostlntCs field in the Host to CPU Doorbell Register 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of interrupt bit in Main Interrupt Cause Reg ister It does not affect the setting of bits in the Host to CPU Doorbell Regis ter Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 107 Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers Table 74 CPU to Host Doorbell Register Offset 0x20408 Bits Field Type Description InitVal 31 0 CPUIntCs CPU RW1 CPU Interrupt Cause Host RWC When a bit
185. I Configuration Data and PCI Interrupt Acknowledge registers are only accessible by CPU They must not be accessed from PCI Table 240 PCI Configuration Address Offset 0x30C78 NOTE This register is also accessible via the a PCI slave read and write transaction Bits Field Type Description InitVal 1 0 Reserved RES Read Only 0x0 7 2 RegNum RW Register number 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 192 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 240 PCI Configuration Address Continued Offset 0x30C78 NOTE This register is also accessible via the a PCI slave read and write transaction Bits Field Type Description InitVal 10 8 FunctNum RW Description number 0x0 15 11 DevNum RW Device number 0x0 23 16 BusNum RW Bus number 0x0 30 24 Reserved RES Read Only 0x0 31 ConfigEn RW When set an access to the Configuration Data register is translated into 0x0 a Configuration or Special cycle on the PCI bus Table 241 PCI Configuration Data Offset 0x30C7C Bits Field Type Description InitVal 31 0 ConfigData RW The data is transferred to from the PCI bus when the CPU accesses this 0x0 register and the ConfigEn bit in the Configuration Address register is set A CPU access to this register cause
186. I interface registers consist of configuration registers PCI configuration header and internal registers The internal registers are part of the entire chip internal registers map They can be accesses from the local CPU They can also be accessed from external PCI host via Memory mapped or I O mapped Internal registers BAR space The specified register offset is in respect to the Internal registers window base address The configuration registers are located at their standard offset as defined in PCI specification They can be accessed from the local CPU using Configuration Address and Configuration Data registers They can also be accessed by an external PCI host using type 0 configuration cycle The specified register offset is the address within the PCI configuration header of the specific function number Table 178 PCI Slave Address Decoding Register Map Register Offsets Page CSn 0 BAR Size 0x30C08 Table 187 p 173 CSn 1 BAR Size Ox30D08 Table 188 p 173 CSn 2 BAR Size 0x30C0C Table 189 p 173 CSn 3 BAR Size 0x30D0C Table 190 p 173 DevCSn 0 BAR Size 0x30C10 Table 191 p 174 DevCSn 1 BAR Size 0x30D10 Table 192 p 174 DevCSn 2 BAR Size 0x30D18 Table 193 p 174 Boot CSn BAR Size 0x30D14 Table 194 p 174 P2P Mem0 BAR Size 0x30D1C Table 195 p 174 P2P I O BAR Size 0x30D24 Table 196 p 175 Expansion ROM BAR Size 0x30D2C Table 197 p 175 Base Addre
187. LCR The output baud rate is equal to the input clock frequency divided by sixteen times the value of the baud rate divisor baud clock frequency 16 divisor 31 8 Reserved RSVD Reserved Table 503 Interrupt Enable Register IER Offset UART 0 0x12004 UART 1 0x12104 NOTE lt DivLatchRdWrt gt bit 7 of the Line Control Register LCR Register Table 507 p 344 must be set to 0 Bits Field Type Description InitVal 0 RxDatalntEn RW Enable Received Data Available Interrupt ERBFI 0x0 0 Disable interrupt 1 Enable interrupt When the FIFO mode is set in FIFO Control Register this interrupt pro vides a character timeout indication 1 TxHoldintEn RW Enable Transmitter Holding Register Empty Interrupt ETBEI 0x0 0 Disable interrupt 1 Enable interrupt 2 RxLineStatIntEn RW Enable Receiver Line Status Interrupt ELSI 0x0 0 Disable interrupt 1 Enable interrupt 3 ModStatIntEn RW Enable Modem Status Interrupt EDSSI 0x0 0 Disable interrupt 1 Enable interrupt 31 4 Reserved RSVD Reserved Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 342 88F5182 E MARvELL e Open Source Community Programmer s User Guide Table 504 Divisor Latch High DLH Register Offset UART 0 0x12004 UART 1 0x12104 NOTE DivLatchRdaWrt bit 7 of the Line Control Register LCR Register Table 507 p 344
188. MA Port 0 Registers 84000 85FFF EDMA Port 1 Registers A 8 2 SATAHC Arbiter Registers Map Table 289 SATAHC Arbiter Registers Map Register Offset Table Page SATAHC Configuration Register 0x80000 Table 294 p 218 SATAHC Request Queue Out Pointer Register 0x80004 Table 295 p 218 SATAHC Response Queue In Pointer Register 0x80008 Table 296 p 219 SATAHC Interrupt Coalescing Threshold Register 0x8000C Table 297 p 219 SATAHC Interrupt Time Threshold Register 0x80010 Table 298 p 220 SATAHC Interrupt Cause Register 0x80014 Table 299 p 220 Reserved Register 0x80018 Table 300 p 222 SATAHC Main Interrupt Cause Register 0x80020 Table 301 p 222 SATAHC Main Interrupt Mask Register 0x80024 Table 302 p 223 Doc No MV S400130 00 Rev 0 5 Page 213 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 289 SATAHC Arbiter Registers Map Continued Register Offset Table Page Window0 Control Register 0x80030 Table 303 p 223 Window0 Base Register 0x80034 Table 304 p 224 Window1 Control Register 0x80040 Table 305 p 224 Window1 Base Register 0x80044 Table 306 p 224 Window2 Control Register 0x80050 Table 307 p 225 Window2 Base Register 0x80054 Table 308 p 225 Window3 Control Register 0x80060 Table 309 p 225 Window3 Base Register 0x80064 Table 310 p
189. MA engines The IDMA engines optimize system performance by moving large amounts of data without significant CPU intervention Each IDMA engine can move data between any source to any destination It can transfer a single data buffer of up to 16 MB It can also run in chain mode in that mode each buffer has its own descriptor 14 1 Functional Description IDMA unit contains four 512 byte buffers one buffer per IDMA channel When a channel is activated data is read from the source into the buffer and then written to the destination Read and write transactions are handled independently The IDMA engine transfers the buffer in chunks of from 8 up to 128 bytes The IDMA engine reads from the source as long as it has place in the buffer It writes to the destination as long as there is valid data in the buffer to be transferred This independency results in concurrent reads and writes and maximum utilization of the IDMA interface The four channels share the same resources They use fixed round robin arbitration 14 2 IDMA Descriptors Each IDMA Channel Descriptor consists of four 32 bit registers Each channel can be configured to work in 64 KB Descriptor mode or in 16 MB Descriptor mode as shown in Figure 13 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 50 88F5182 marveL Open Source Community Programmer s User Guide Figure 13 IDMA D
190. Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 202 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 259 PCI Subsystem Device and Vendor ID Offset 0x2C Bits Field Type Description InitVal 15 0 VenID RW Subsystem Manufacturer ID Number 0x0 NOTE Read only from PCI 31 16 DevID RW Subsystem Device ID Number 0x0 NOTE Read only from PCI Table 260 PCI Expansion ROM Base Address Register Offset 0x30 NOTE If Expansion ROM is not enabled PCI Mode register this register is Reserved Read Only 0 Bits Field Type Description InitVal 0 ExpROMEn RW Expansion ROM Enable 0x0 0 Disable 1 Enable 11 1 Reserved RES Reserved 0x0 31 12 Base RW Expansion ROM Base Address OxE0000 Table 261 PCI Capability List Pointer Register Table 262 PCI Interrupt Pin and Line Offset 0x34 Bits Field Type Description InitVal 7 0 CapPtr RW Capability List Pointer 0x40 NOTE Read only from PCI 31 8 Reserved RES Reserved 0x0 Offset 0x3C Bits Field Type Description InitVal 7 0 IntLine RW Provides interrupt line routing information 0x0 15 8 IntPin RW Indicates which interrupt pin is used by the 88F5182 0x1 NOTE Read only from PCI Doc No MV S400130 00 Rev 0 5 Page 203 Document Classification Proprietary
191. Mask Register Offset 0x1011C Bits Field Type Description InitVal 25 0 GP1OlIntLevel RW GPIO Interrupt Level Sensitive Mask Mask 0x0 The mask bit for each bit in the lt GPIODIn gt field of the GPIO Data In Register see Table 569 on page 381 0 Interrupt is masked 1 Interrupt is enabled The mask only affects the assertion of the interrupt bit in Main Interrupt Cause Register It does not affect the value of bits in the GPIO Data In Register 31 26 Reserved RW Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 382 88F5182 marveL Open Source Community Programmer s User Guide S Note To set an edge sensitive interrupt set the corresponding bit in GPIO Interrupt Mask Register To set a level sensitive interrupt set the corresponding bit in GPIO Interrupt Level Mask Register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 383 Document Classification Proprietary June 25 2007 Preliminary Pins Multiplexing Interface Registers A 18 Pins Multiplexing Interface Registers Table 573 MPP Register Map Register Offset Page MPP Control 0 Register 0x10000 Table 574 p 384 MPP Control 1 Register 0x10004 Table 575 p 385 MPP Control 2 Register 0x10050 Table 576 p 385 Device Multiplex Control Register 0x10008 Table 577 p 386 Sample at
192. ND Flash Initialization Sequence Disabled SAR 0 Enabled Initialization Sequence 1 Disabled Initialization Sequence Sampled at reset 13 9 NFOEnW RW Defines DEV_OEn high width lt NFOEnHW 1 Core clocks Applies to all OxC NAND Flash devices connected to DEV BootCEn DEV CEn0 DEV_CEn1 and DEV CEn2 For the default OxOE the calculation is 15 166 MHz 90 ns 1844 NFTr RW NAND Flash Time Ready Ox1F Defines the maximum time it takes the boot NAND Flash to transfer the data from the array to the register lt NFTr 1 x 1024 Core clocks The CPU is forced to reset during this time before it starts the boot procedures For the default value Ox1F the calculation is 32x1024 166 MHz 197 us 19 NFOEnDel RW See lt NFActCEn0 gt description 0x0 0 Delay the falling edge of DEV_OEn by one cycle after the DEV_CEn falling edge in access to don t care NAND Flash 1 DEV_OEn and DEV_CEn fall on the same edge 31 20 Reserved RW Reserved 0x0 Table 518 Device Interface Control Offset 0x104CO Bits Field Type Description InitVal 15 0 Timeout RW Timeout Timer Preset Value OxFFFF If the device access is not completed within period of this preset value due to a lack of READYn assertion the Device controller completes the transaction as if READYn was asserted and it asserts an interrupt NOTE If set to 0x0 the Device controller waits for READYn assertion forever 16 Reserved RO Must be cleared t
193. No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 94 e 88F5182 marveL Open Source Community Programmer s User Guide Table 44 Window3 Control Register Continued Offset 0x20030 Bits Field Type Description InitVal 31 16 Size RW Window Size 0x0 See the Window0 Control Register Table 34 p 91 Table 45 Window3 Base Register Offset 0x20034 NOTE Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address OxC800 See the Window0 Base Register Table 46 Window4 Control Register Offset 0x20040 Bits Field Type Description InitVal 0 win_en RW Window4 Enable 0x1 See the Window0 Control Register Table 34 p 91 31 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x9 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface 0x0 See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size 0x0 See the Window0 Control Register Table 34 p 91 Table 47 Window4 Base Register Offset 0x20044 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell June 25 2007 Preliminary Page 95 Document Classification Proprietary Loca
194. O 0x0 SATA Device Interrupt Port 1 This bit is set if field lt eEnEDMAs is cleared and the ATA interrupt line in port 1 is active 0 The ATA interrupt line in port 1 was not active 1 The ATA interrupt line in port 1 was active Doc No MV S400130 00 Rev 0 5 Page 221 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 299 SATAHC Interrupt Cause Register Continued Offset 0x80014 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 31 10 Reserved RES Reserved 0x0 Table 300 Reserved Register Offset 0x80018 Type Description InitVal 31 0 RW Reserved Reserved 0x0 Table 301 SATAHC Main Interrupt Cause Register Offset 0x80020 NOTE The bits in this register mirror the interrupt indications coming from the other SATAHC interrupt cause registers Bits Field Type Description InitVal 0 SataOErr RO SATA pont error 0x0 1 Sata0Done RO SATA port0 command done 0x0 This bit is set when one of the following occurs e The SaCrpbODone DMAODone field in the SATAHC Inter rupt Cause Register Table 299 p 220 of the SATAHC is set e The lt SaDevinterrupt0 gt of the same register of the SATAHC is set 2 Sata1Err RO S
195. Offset 0x31E58 Table 240 PCI Configuration Address rte terit eene tociens batte sera cendo tbe deba oed Eo Ep EES ode Rena 192 Offset 0x30C78 Table 241 Ke Configuration Data WEE 193 Offset 0x30C7C Table 242 PCI Interrupt ele Ee CN 193 Offset 0x30C34 Table 243 PCUSERRN Mask aie eee Encore wile do rep s tton ee deii Eo enne acia pesi EEEE coup aoa 194 Offset 0x30C28 Table 244 PCL Interrupt Cause R M 195 Offset OX31D58 Table245 PCUInterrupt Mask tiere taret tat tte ek ei rre a Ee rH DELI LER II DL EE RE Xe e ELO ERE ERE EG 196 Offset 0x31D5C Table 246 PCI Error Address LOW retenti etit terrebat te than eb abba ne E ERE De dare Teka n 197 Offset 0x31D40 Table 247 PGI Error Address High rte cte tret tret ner er thee tirer ede ter Goose rg 197 Offset 0x31D44 Eo 248 PCUEmOor Command m 197 Offset OX31D50 Table 249 PCI Device and Vendor ID 198 Offset 0x00 Table 250 PCI Status and Commande 198 Offset 0x04 Table 251 PCI Class Code and Revision ID 200 Offset 0x08 Table 252 PCI BIST Header Type Initial Value Latency Timer and Cache Line ssseseessieseesirerrsesrerrrserrenrnnne 200 Offset 0x0C Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 73 Document Classification Proprietary June 25 2007 Preliminary List of Registers Table 253 PCI CSn 0 Base Address Low 201
196. Offset 0x60900 Bits Field Type Description InitVal 0 Sliced RW Slice 0 of the channel pizza arbiter 0x0 0 slice is owned by channel 0 1 slice is owned by channel 1 1 Slice1 RW Slice 1 of the channel pizza arbiter 0x1 2 Slice2 RW Slice 2 of the channel pizza arbiter 0x0 3 Slice3 RW Slice 3 of the channel pizza arbiter 0x1 4 Slice4 RW Slice 4 of the channel pizza arbiter 0x0 5 Slice5 RW Slice 5 of the channel pizza arbiter 0x1 6 Slice6 RW Slice 6 of the channel pizza arbiter 0x0 7 Slice7 RW Slice 7 of the channel pizza arbiter 0x1 31 8 Reserved RO Reserved 0x0 Table 543 XOR Engine 0 1 Configuration XExCR Offset XORO 0x60910 XOR1 0x60914 Bits Field Type Description InitVal 2 0 OperationMode RW Specifies the type of operation to be carried out by XOR Engine 0x0 0x0 XOR calculate operation 0x1 CRC 32 calculate operation 0x2 DMA operation 0x3 ECC cleanup operation 0x4 Memory Initialization operation 0x5 Reserved 0x6 Reserved 0x7 Reserved 3 Reserved RW Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 366 88F5182 marveL Open Source Community Programmer s User Guide Table 543 XOR Engine 0 1 Configuration XExCR Continued Offset XORO 0x60910 XOR1 0x60914
197. Ox1E 128 MByte E000 0000 E7FF FFFF Device CS1 1 0x1D 128 MByte E800 0000 EFFF FFFF Device CS2 1 0x1B 128 MByte F000 0000 F7FF FFFF Flash Boot CS 1 OxOF 128 MByte F800 0000 FFFF FFFF 1 Defines field Target in the window control registers See Appendix A 4 1 CPU Address Map Registers on page 91 and Appendix A 6 4 PCI Express Address Window Control Registers on page 134 2 Defines field lt Attr gt in the window control registers See Appendix A 4 1 CPU Address Map Registers on page 91 and Appendix A 6 4 PCI Express Address Window Control Registers on page 134 3 For the 88F5182 Internal Address Map see Table 32 on page 89 Doc No MV S400130 00 Rev 0 5 Page 15 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary DDR SDRAM Controller Interface Section 3 DDR SDRAM Controller Interface The DDR SDRAM Double Data Rate Synchronous DRAM controller supports Both 16 and 32 bit DDR SDRAM interfaces Supports DDR1 and DDR2 Up to two dual sided DIMMs four physical banks A variety of DDR SDRAM components x8 and x16 devices at densities of 128 Mbits 256 Mbits and 512 Mbits Up to 1 GByte 32 bit interface and 0 5 GByte 16 bit interface total memory space Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 16 88F5182 marveL Open Source Community Pr
198. Page 238 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 324 EDMA IORdy Timeout Register Offset Port 0 0x82034 Port 1 0x84034 Bits Field Type Description InitVal 15 0 elORdyTimeout RW EDMA IORdy Signal Timeout Value OxBC If SATAHC unit is not ready to complete the transaction for the number of system cycles set in this field a timeout will occur and the transaction will be completed If the transaction is terminated as a result of the IORdy time out field lt elORdyErr gt is set 0 elORdy timeout is ignored the transaction will not be aborted x Timeout will occur after x system clocks 31 16 Reserved RES Reserved 0x0 Table 325 EDMA Command Delay Threshold Register Offset Port 0 0x82040 Port 1 0x84040 Bits Field Type Description InitVal 15 0 CmdDelayThrshd RW This field indicates the length of delay to insert before sending a 0x0 command to the drive when 31 lt CMDDataoutDelayEn gt is enabled 30 16 Reserved RES Reserved 0x0 31 CMDDataoutDelayEn RW When this bit is set to 1 when the DMA completes write data trans 0x0 action the content of field 15 0 CmdDelayThrshd is written to a 16 bit counter This counter is decrement every 16 clock cycles until it reaches 0 Then it stops A new command is issue to the drive only when the value of this counter is 0 i e a delay of lt CmdDelayThrshd gt 16 clock cyc
199. Port0 0x50320 Port1 0xA0320 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 80 88F5182 marveL Open Source Community Programmer s User Guide Table 427 Table 428 Table 429 Table 430 Table 431 Table 432 Table 433 Table 434 USB 2 0 WindowO Base EE 309 Offset Port0 0x50324 Port1 0xA0324 USB 2 0 Window1 Control Register ANNER nennen tenente 309 Offset Port0 0x50330 Port1 0xA0330 USB 2 0 Window1 Base Register neret p RERO AEG RAPERE M FERRE SNRMARADENO SPERARE ERR RAE 310 Offset Port0 0x50334 Port1 0xA0334 USB 2 0 Wiridow2 Control FlegIster 1 toii tet rente estre ett ined erii nre Ee eoe E Eee eb ev rab Een 310 Offset Port0 0x50340 Port1 0xA0340 USB 2 0 Window Base EE 311 Offset Port0 0x50344 Port1 0xA0344 USB 2 0 Windows Control Register ierit enne iae ten tha tnum kae Sinks e o ELK reap annaa 311 Offset Port0 0x50350 Port1 0xA0350 USB 2 0 Windows Base EE 311 Offset Port0 0x50354 Port1 0xA0354 USB 2 0 Power Control Reglister 2 e eu Lee NEESS AER BEES Er bnc ee ea oap cases nba etra See 312 Offset Port0 0x50400 Port1 0xA0400 A 11 Cryptographic Engine and Security Accelerator Registers 314 Table 436 DES Data Out Low Register scccseessssesccsseecssesscessnnescessneessensc
200. R eeler E Nee DEE 208 Offset 0x68 Table 272 PCI CSn 2 e KICHE UE 208 Offset 0x10 Table 273 PCI CSn 2 Base Address High ssessersssrusnensersereresesrererrassnrerenucnesosnsssudernetenurrascenertescrscnesonnereneoineseneree 209 Offset 0x14 Table 274 PCI CSn 3 Base Address LOW esent enne nete trementes 209 Offset 0x18 Table 275 PCI CSn 3 Base Address High rrr cnn riana aeda riae nennen nennen resins nnns 209 Offset 0x1C Table 276 PCI DevCS 0 Base Address Low rennen retrenren rer tren rennes 209 Offset 0x10 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 74 88F5182 marveL Open Source Community Programmer s User Guide Table 277 PCI DevCSn 0 Base Address Hoh 210 Offset 0x14 Table 278 PCI DevCSn 1 Base Address Low 210 Offset 0x18 Table 279 PCI DevCSn 1 Base Address Hoh 210 Offset 0x1C Table 280 PCI DevCSn 2 Base Address Low ceeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeseaeeeeeeeeseeeseaeeseaaeeseaeeseaaeeseeeseaeeeseeeseaeess 210 Offset 0x20 Table 281 PCI DevCSn 2 Base Address Hoh 210 Offset 0x24 Table 282 PCI BootCS Base Address Low een 211 Offset 0x18 Table 283 PCI BootCSn Base Address Hab 211 Offset 0x1C Table 284 PCI P2P Mem Base Address Low 211 Offset 0x10 Table 285 PCI P2P Mem Base Address High sees nenn
201. R1 0x72284 HARR2 0x72288 HARR3 0x7228C Base Address Enable BARE 0x72290 Table 379 p 276 Ethernet Port Access Protect EPAP 0x72294 Table 380 p 276 Ethernet Unit Port Registers Port Configuration PxC 0x72400 Table 381 p 277 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 267 Document Classification Proprietary June 25 2007 Preliminary Table 364 Ethernet Unit Global Registers Map Continued Gigabit Ethernet Controller Registers IP Differentiated Services CodePoint 2 to Priority DSCP2 DSCP3 DSCP4 DSCP5 Description Offset Table Page Port Configuration Extend PxCX 0x72404 Table 382 p 278 MII Serial Parameters 0x72408 Table 383 p 279 GMII Serial Parameters 0x7240C Table 384 p 280 VLAN EtherType EVLANE 0x72410 Table 385 p 280 MAC Address Low MACAL 0x72414 Table 386 p 280 MAC Address High MACAH 0x72418 Table 387 p 280 SDMA Configuration SDC 0x7241C Table 388 p 281 IP Differentiated Services CodePoint 0 to Priority DSCPO 0x72420 Table 389 p 282 IP Differentiated Services CodePoint 1 to Priority DSCP1 0x72424 Table 390 p 283 DSCP2 0x72428 DSCP3 0x7242C DSCP4 0x72430 DSCP5 0x72434 Table 391 p 283 IP Differentiated Services CodePoint 6 to Priority DSCP6 0x72438 Table 392 p 283 Port Serial Control PSC 0x7243C Table 393 p 284 VLAN Priority Tag to Priority
202. RVELL A 13 1 e 88F5182 Open Source Community Programmer s User Guide UART Interface Registers Table 500 Receive Buffer Register RBR Offset UART 0 0x12000 UART 1 0x12100 NOTE lt DivLatchRdWrt gt bit 7 of the Line Control Register LCR Register Table 507 p 344 must be set to 0 Bits Field Type InitVal Description 7 0 RxBuf RO 0x0 The RBR is a read only register that contains the data byte transmitted to the serial port The data in this register is valid only if the LSR lt DataRx Stat bit in the Line Status Register LSR is set see Table 509 on page 346 In the non FIFO mode fifo mode 0 the data in the RBR must be read before the next data arrives otherwise it will be overwritten resulting in an overrun error In the FIFO mode fifo mode 1 this register accesses the head of the receive FIFO If the receive FIFO is full and this register is not read before the next data word arrives then the data already in the FIFO will be preserved but any incoming data will be lost 31 8 Reserved RSVD Reserved Table 501 Transmit Holding Register THR Offset UART 0 0x12000 UART 1 0x12100 NOTE lt DivLatchRdWrt gt bit 7 of the Line Control Register LCR Register Table 507 p 344 must be set to 0 Bits Field Type InitVal Description 7 0 TxHold WO 0x0 The THR is a write only register that contains
203. RWC Set when the 88F5182 s slave terminates a transaction with Target 0x0 Abort Clear only by writing 1 Doc No MV S400130 00 Rev 0 5 Page 199 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 250 PCI Status and Command Continued Offset 0x04 Bits Field Type Description InitVal 28 MasterTabort RWC Set when the 88F5182 s master detects a Target Abort termination 0x0 Clear only by writing 1 29 MAbort RWC Set when the 88F5182 s master generates a Master Abort except of 0x0 special cycle Clear only by writing 1 30 SysErr RWC Set when the 88F5182 asserts PCI SERRn 0x0 Clear only by writing 1 31 DetParErr RWC Set upon the 88F5182 detection of Parity error both as master and 0x0 slave Clear only by writing 1 Table 251 PCI Class Code and Revision ID Offset 0x08 Bits Field Type Description InitVal 7 0 RevID RW Indicates the Revision number Rev A1 0x1 NOTE Read only from PCI Rev A2 0x2 15 8 Reserved RO Read only 0x0 23 16 SubClass RW Indicates the Subclass 0x80 NOTE Read only from PCI 31 24 BaseClass RW Indicates the Base Class 0x05 NOTE Read only from PCI Table 252 PCI BIST Header Type Initial Value Latency Timer and Cache Line Offset OxOC Bits Field Type Description InitVal 7 0 CacheLine RW Specifies the 88F5182
204. Reg Interrupt Mask Reg Main Interrupt Controller Main Interrupt Cause Reg Main IRQ Interrupt Mask Reg Main FIQ Interrupt Mask Reg Main PCI PCI Express Interrupt Mask Reg Doc No MV S400130 00 Rev 0 5 Page 61 UNIT N Interrupt Cause Reg Interrupt Mask Reg Document Classification Proprietary PEX P PCI L re bit masks routing to PEX and PCI Copyright 2007 Marvell June 25 2007 Preliminary Timers Functional Description Section 18 Timers 18 1 Functional Description The 88F5182 provides two general purpose timers and one watchdog timer 18 2 32 bit wide Timers The 88F5182 provides two 32 bit wide timers Each timer decrements with every TCLK rising edge if the corresponding enabled bit is enabled Reads and write from to the timer are done to the counter itself The timers provide auto mode When the timers are set to auto mode disabled and the timers reach to 0 the timers stop counting When the timers are set to auto mode enabled and the timers reach to 0 the timers preload and continue counting Regardless of whether auto mode is enabled or disabled when the timers reach 0 a maskable interrupt is generated 18 3 Watchdog Timer The 88F5182 internal watchdog timer is a 32 bit count down counter that can be used to generate a maskable interrupt or reset
205. Reserved 0x1 13 P2PIOEn RW P2P IO BAR Enable 0x1 0 Enable 1 Disable 15 14 Reserved RW Reserved 0x3 Must be 0x3 31 16 Reserved RES Reserved OxFFFF Table 199 CSn 0 Base Address Remap Offset 0x30C48 Bits Field Type Description InitVal 11 0 Reserved RO Read only 0x0 31 12 CSORemap RW CSn 0 BAR Remap Address 0x00000 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 176 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 200 CSn 1 Base Address Remap Offset 0x30D48 Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 Base Address Remap RW 0x10000000 Table 201 CSn 2 Base Address Remap Offset 0x30C4C Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 Base Address Remap RW 0x20000000 Table 202 CSn 3 Base Address Remap Offset 0x30D4C Bits Field Type Description InitVal 31 0 Various RO Same as CSn 0 Base Address Remap RW 0x30000000 Table 203 DevCSn 0 Base Address Remap Offset 0x30C50 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap OxE0000000 Table 204 DevCSn 1 Base Address Remap Doc No MV S400130 00 Rev 0 5 Page 177 Offset Ox30D50 Bits F
206. Reserved RES Reserved 0x0 31 WrEn RW DLL Status and Control Register Write Enable 0x0 0 The register becomes read only except for bit 31 1 The register can be written to Only applicable when MPPSetEN 0 Table 214 PCI MPP Pads Calibration Offset Ox31D1C Bits Field Type Description InitVal 3 0 DrvN RW PCI Pad Driving N Strength OxF NOTE Only applicable when auto calibration is disabled 7 4 MppDrvPO RES MPP Pad Driving P Strength OxF NOTE Only applicable when lt MPPSetEn gt 1 11 8 MppDrvN1 RW MPP Pad Driving N Strength OxF Useful for changing MPP drive N strength after the automatic tuning completes NOTE Only applicable when lt MPPSetEn gt 0 15 12 MppDrvP1 RES MPP Pad Driving P Strength OxF Useful for changing MPP drive P strength after the automatic tuning completes NOTE Only applicable when lt MPPSetEn gt 0 16 TuneEn RW Auto calibration of Pad Driving Strength 0x1 0 Disabled 1 Enabled 17 MPPSetEn RW MPP Drive Strength Enable 0x1 0 Enables changing the drive strength of the MPPs via lt MppDrvN1 gt and lt MppDrvP1 gt 1 The drive strength of the MPPs is equal to lt DrvN gt and lt MppDrvP0 gt Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 181 Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 214 PCI MPP Pads Calibration Continued Offset Ox31D1C
207. Reset Register 0x10010 Table 578 p 387 A 18 1 MPP Registers Table 574 MPP Control 0 Register Offset 0x10000 Bits Field Type Description InitVal 3 0 MPPSel0 RW MPPO Select Sample See the MPP Function Summary table and the Reset Configuration table in at reset the 88F5182 88F5182 based Storage Networking Platforms Datasheet 7 4 MPPSel1 RW MPP1 Select Sample See field MPPSel0 at reset 11 8 MPPSel2 RW MPP2 Select Sample See field MPPSel0 at reset 15 12 MPPSel3 RW MPP3 Select Sample See field MPPSel0 at reset 19 16 MPPSel4 RW MPP4 Select Sample See field MPPSel0 at reset 23 20 MPPSel5 RW MPP5 Select Sample See field MPPSel0 at reset 27 24 MPPSel6 RW MPP6 Select Sample See field MPPSel0 at reset 31 28 MPPSel7 RW MPP7 Select Sample See field MPPSel0 at reset Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 384 88F5182 marveL Open Source Community Programmer s User Guide Table 575 MPP Control 1 Register Offset 0x10004 Bits Field Type Description InitVal 3 0 MPPSel8 RW MPP8 Select Sample See the MPP Function Summary table in the 88F5182 88F5182 based at reset Storage Networking Platforms Datasheet 7 4 MPPSel9 RW MPP9 Select Sample See field MPPSel8 at reset 11 8 MPPSel10 RW MPP10 Select Sample See field MPPSel8 at re
208. Rx frame in receive pri ority queue 5 8 RxBufferQueue RW Rx Buffer Return in Priority Queue 6 indicates a Rx buffer returned to CPU 6 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 6 9 RxBufferQueue RW Rx Buffer Return in Priority Queue 7 indicates a Rx buffer returned to CPU 7 0x0 ownership or that the port completed reception of a Rx frame in receive pri ority queue 7 10 RxError RW Rx Resource Error indicates a Rx resource error event in either Rx priority 0x0 queues To get a Rx Resource Error Indication per priority queue use bits 18 11 11 RxErrorQueue RW Rx Resource Error in Priority Queue 0 indicates a Rx resource error event 0 0x0 in receive priority queue 0 12 RxErrorQueue RW Rx Resource Error in Priority Queue 1 indicates a Rx resource error event 1 0x0 in receive priority queue 1 13 RxErrorQueue RW Rx Resource Error in Priority Queue 2 indicates a Rx resource error event 2 0x0 in receive priority queue 2 14 RxErrorQueue RW Rx Resource Error in Priority Queue 3 indicates a Rx resource error event 3 0x0 in receive priority queue 3 15 RxErrorQueue RW Rx Resource Error in Priority Queue 0 indicates a Rx resource error event 4 0x0 in receive priority queue 4 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 291 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 398 Port I
209. S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 76 88F5182 marveL Open Source Community Programmer s User Guide Table 330 Table 331 Table 332 Table 333 Table 334 Table 335 Table 336 Table 337 Table 338 Table 339 Table 340 Table 341 Table 342 Table 343 Table 344 Table 345 Table 346 Table 347 Table 348 Table 349 Table 350 Table 351 Table 352 Table 353 EDMA NCQ3 Done TCQ3 Outstanding Status Heotsier A 241 Offset Port 0 0x820A0 Port 1 0x840A0 Basic DMA Command Register soies aident ia kana aaa anaia nennen treten nennen neret 241 Offset Port 0 0x82224 Port 1 0x84224 Basic DMA Status E EE 243 Offset Port 0 0x82228 Port 1 0x84228 Descriptor Table Low Base Address Register eene 244 Offset Port 0 0x8222C Port 1 0x8422C Descriptor Table High Base Address Hegtster A 244 Offset Port 0 0x82230 Port 1 0x84230 Data Region Low Address Register sees enne rennen mener 245 Offset Port 0 0x82234 Port 1 0x84234 Data Region High Address Register seeseeeseeeeeneenen enne nee 245 Offset Port 0 0x82238 Port 1 0x84238 SStat s E 246 Offset Port 0 0x82300 Port 1 0x84300 lge EE 246 Offset Port 0 0x82304 Port 1 0x84304 SError Interr pt Mask Ftegister cei been tet eret Dante Ee pat e ix dee
210. SB e NRZI encoding decoding with bit stuffing unstuffing Bit stuff error detections Bit stuffing unstuffing bit stuff error detection Holding registers to stage transmit and receive data e Supports USB 2 0 Test Modes e Ability to switch between FS and HS terminations signaling S Note For more details refer to controller specification document USB HS High Speed Controller Core Reference Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 36 MSE sss marveL Open Source Community Programmer s User Guide Section 10 Cryptographic Engines and Security Accelerator 10 4 Functional Overview The 88F5182 integrates hardware based cryptographic engines and security accelerator These engines have been designed for the purpose of performing time consuming cryptographic operations such as AES DES 3DES encryption and MD5 SHA1 authentication to reduce CPU packet processing overhead 10 1 1 Acronyms Abbreviations and Definitions The acronyms abbreviations and definitions shown in Table 20 are used in this section of the datasheet Table 20 Acronyms Abbreviations and Definitions Acronym Definition AES Advanced Encryption Standard AES128 128 128 data bits AES with 128 bit key width AES128 192 128 data bits AES with 192 bit key width AES128 256 128 data bits AES with 2
211. SHA mode requires a 5 word initial value to produce the 5 word SHA signature Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 320 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 457 SHA 1 MD5 Authentication Command Register Offset 0x9DD18 Bits Field Type Description InitVal 0 Algorithm RW This bit controls the mode of operation SHA 1 or MD5 0x0 0 MD5 1 SHA1 These are two different algorithms for calculating the authentication signature They are described in the references SHA calculation takes 85 clock cycles where MD5 takes 65 clock cycles SHA mode results in a 5 word signature and a 5 word initial value is required where MD5 results in a 4 word signature and a 4 word initial value is required The MD5 is byte swapped compared to the SHA These algorithms differ in their complexity and security levels and it is left to the user to choose the algorithm 1 Mode RW This bit controls whether the initial value is used or the operation continues 0x0 from the last value 0 Use initial value 1 Continue from the last value Both SHA and MD5 algorithms do a computational process on chunks of 512 bits where the last 64 bits in the last chunk are reserved for packet size When a packet length is less then 448 bits the host must add one bit of 1 to the end of
212. Table 280 PCI DevCSn 2 Base Address Low Offset 0x20 Bits Field Type Description InitVal 31 0 Various 0x0 Same as DevCSn 0 Base Address Low Table 281 PCI DevCSn 2 Base Address High Offset 0x24 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 210 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 282 PCI BootCS Base Address Low Offset 0x18 Bits Field Type Description InitVal 31 0 Various OxF8000000 Same as DevCSn 0 Base Address Low See Table 276 PCI DevCS 0 Base Address Low on page 209 Table 283 PCI BootCSn Base Address High Offset 0x1C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 Table 284 PCI P2P Mem0 Base Address Low Offset 0x10 Bits Field Type Description InitVal 31 0 Various 0x80000000 Same as CSn 0 Base Address Low See Table 253 PCI CSn 0 Base Address Low on page 201 Table 285 PCI P2P Mem0 Base Address High Offset 0x14 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 Table 286 PCI P2P I O Base Address
213. The EDMA response queue out pointer is updated increment by the system driver after the driver completes processing the CRPB pointed to by this register The EDMA compares the EDMA Response Queue Out Pointer to the EDMA Response Queue In Pointer to determine if the response queue is full 9 8 eRPQBA eRp RW The function of this field depends on lt eEDMAQueLen gt QIP 0x0 lt eEDMAQueLen gt 0 The EDMA Response Queue base address corresponds to bits 9 8 lt eEDMAQueLen gt 1 This field serves as the EDMA Response Queue Out Pointer 6 5 31 10 eRPQBA 31 10 RW The EDMA Response Queue base address corresponds to bits 31 10 0x0 Doc No MV S400130 00 Rev 0 5 Page 235 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 321 EDMA Command Register Offset Port 0 0x82028 Port 1 0x84028 Bits Field Type Description InitVal 0 eEnEDMA RW Enable EDMA 0x0 When this bit is set to 1 the EDMA is activated All control registers request queues and response queues must be initial ized before this bit is set to 1 The EDMA clears this bit when 1 Bit eDsEDMA bit 1 is set or 2 Anerror condition occurs and not masked corresponding bit in EDMA Halt Conditions Register Table 326 p 239 or 3 Linkis down and not masked corresponding bit in EDMA Halt Condi tions Register Writing O to this bit is
214. The PCI Express interface includes a single PCI Express X1 host port with an integrated low power SERDES The PCI Express port can also be configured as an Endpoint port PCI The 88F5182 integrates a 32 bit conventional PCI interface Doc No MV S400130 00 Rev 0 5 Page 11 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary SATA II Gigabit Ethernet USB 2 0 Cryptographic Engine and Security Accelerator Two Wire Serial Interface TWSI UART Device Bus IDMA Engines XOR Engine General Purpose IO Port Interrupt Controller Timers Internal Architecture Copyright 2007 Marvell Overview The 88F5182 accommodates a total of two SATA II ports It is fully compliant with SATA II Phase 1 0 specification Extension to SATA specification supporting SATA II Native command queuing e Backwards compatibility to SATA 1 5 Gbps speed and devices In addition to full support of SATA II Phase 1 0 specification Extension to SATA I specifi cation the 88F5182 supports the following advanced SATA II Phase 2 0 specification features e SATA II 3 Gbps speed e Advanced SATA PHY characteristics for SATA backplane support e SATA II Port Multiplier Advanced Support SATAII Port Selector control Generates the protocol based OOB sequence to select the active host of the SATA II Port Selector The Gigabit Ethernet interface consists of a single 10 100 1000 Mbps full du
215. Transport layer is not idle 29 Reserved RO Reserved 0x0 30 RxBIST RO Set to 1 when BIST FIS is received 0x0 NOTE This bit is cleared when the ClearStatus field in the Serial ATA Interface Control Register Table 350 p 258 is set to 1 31 N RO Set to 1 when the Set Devices Bits FIS is received with the Notification N 0x0 bit set to 1 NOTE This bit is cleared when the ClearStatus field is set to 1 Table 353 Vendor Unique Register Offset Port 0 0x8235C Port 1 0x8435C Bits Name Type Description InitVal 31 0 VendorUqDw RW Vendor Unique DWORD 0x0 The data written to this register is transmitted as a vendor unique FIS This Data includes the FIS header as well as the payload Doc No MV S400130 00 Rev 0 5 Page 261 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 354 FIS Configuration Register Offset Port 0 0x82360 Port 1 0x84360 Bits Name Type InitVal Description 7 0 15 8 FISWait4RdyEn FISWait4HostR dyEn RW 0x0 RW 0x0 This field identifies whether the transport layer waits for the upper layer EDMA or host to acknowledge reception of the current FIS before enabling the link layer to response with R_RDY for the next FIS When lt eEnEDMA gt is set to 1 the transport layer ignores the value of bits 4 0 of this field and assume a value o
216. W For pointer index 3 Determines the Queue number if Pass 3 1 N A 28 Reserved 3 RW Reserved N A Must be set to 0 31 29 Unused 3 RO Reserved N A Table 417 Destination Address Filter Unicast Table DFUT Offset 0x73600 0x7360C NOTE Every register holds four entries A total of four registers appear in this table in consecutive order Bits Field Type Description InitVal 0 Pass 0 RW Determines whether to filter or accept for pointer index 0 N A 0 Reject filter frame 1 Accept frame 3 1 Queue 0 RW For pointer index 0 Determines the Queue number if Pass 0 1 N A 4 Reserved 0 RW Reserved N A Must be set to 0 7 5 Unused 0 RO Reserved N A 8 Pass 1 RW Determines whether to filter or accept for pointer index 1 N A 0 Reject filter frame 1 Accept frame Doc No MV S400130 00 Rev 0 5 Page 301 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 417 Destination Address Filter Unicast Table DFUT Continued Offset 0x73600 0x7360C NOTE Every register holds four entries A total of four registers appear in this table in consecutive order Bits Field Type Description InitVal 11 9 Queue 1 RW For pointer index 1 Determines the Queue number if Pass 1 1 N A 12 Reserved 1 RW Reserved N A Must be set to 0 1543 Unused 1 RO Reserved N A 1
217. Window6 Base Register 0x20064 Table 51 p 97 Window7 Control Register 0x20070 Table 52 p 97 Window Base Register 0x20074 Table 53 p 98 88F5182 Internal Registers Base Address Register 0x20080 Table 54 p 98 CPU Control and Status Registers CPU Configuration Register 0x20100 Table 55 p 99 CPU Control and Status Register 0x20104 Table 56 p 100 RSTOUTn Mask Register 0x20108 Table 57 p 100 System Soft Reset Register 0x2010C Table 58 p 101 Local to System Bridge Interrupt Cause Register 0x20110 Table 59 p 101 Local to System Bridge Interrupt Mask Register 0x20114 Table 60 p 101 Main Interrupt Controller Registers Main Interrupt Cause Register 0x20200 Table 61 p 102 Main IRQ Interrupt Mask Register 0x20204 Table 62 p 104 Main FIQ Interrupt Mask Register 0x20208 Table 63 p 104 Endpoint Interrupt Mask Register 0x2020C Table 64 p 104 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 90 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 33 CPU Register Map Continued Register Name Offset Table Number and Page Number CPU Timers Registers CPU Timers Control Register 0x20300 Table 65 p 105 CPU TimerO Reload Register 0x20310 Table 66 p 105 CPU Timer 0 Register 0x20314 Table 67 p 106 CPU Timer1 Reload Register 0x20318 Table 67 p 106 CPU Timer 1 Register 0x2031
218. able 566 GPIO Data Out Enable Control Register Offset 0x10104 Bits Field Type Description InitVal 25 0 GPIODOutEn RW GPIO Port Output Enable OxFFFF This field is active low Data is driven when the corresponding bit value is 0 31 26 Reserved RW Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 380 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 567 GPIO Blink Enable Register Offset 0x10108 Bits Field Type Description InitVal 25 0 GPIODBlink RW GPIO Data Blink 0x0 When set and the corresponding bit in GPIO Data Out Enable Control Register is enabled the GPIO pin blinks every 100 ms a period of 2 24 TCLK clocks When set and the corresponding pin on the MPP interface is set for the SATA LED indication then the LED blinks every 100 ms a period of 2424 TCLK clocks 31 26 Reserved RW Reserved 0x0 Table 568 GPIO Data In Polarity Register Offset 0x1010C Bits Field Type Description InitVal 25 0 GPIODatalnAct RW GPIO Data in Active Low Low 0x0 When set to 1 GPIO Data In Register reflects the inverted value of the corresponding pin 31 26 Reserved RW Reserved 0x0 Table 569 GPIO Data In Register Offset 0x10110 Bits Field Type Description InitVal 25 0 GPIODIn RO E
219. able 73 Host to CPU Doorbell Mask Register nnne nnne nnne 107 Offset 0x20404 Table 74 CPU to Host Doorbell Register esee eene nennen nennen nnne tenete nns 108 Offset 0x20408 Table 75 CPU to Host Doorbell Mask Heotster A 108 Offset 0x2040C Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 66 88F5182 marveL Open Source Community Programmer s User Guide A 5 DDR SDRAM Controller Registers e eeeeeeeeee eese esee enne nennen nnn nnns 109 Table 77 CS 0 n Base Address Register NENNEN 110 Offset 0x01500 Table TL E LE EE 110 Offset 0x01504 Table 79 CS 1 n Base Address Register eese enne nnne rennen enne 110 Offset 0x01508 Table 80 STRE E ET M 111 Offset 0x0150C Table 81 CS 2 n Base Address Register eese nennen nnne rennen enne 111 Offset 0x01510 able 82 GS 2 n Size E E EE 111 Offset 0x01514 Table 83 CS 3 n Base Address Register A 112 Offset 0x01518 Ree RE E EC EE 112 Offset 0x0151C Table 85 DDR SDRAM Configuration Heiser 112 Offset 0x01400 Table 86 DDR SDRAM Control Register AAA 113 Offset 0x01404 Table 87 DDR SDRAM Timing Low Register ssssssssseseseeeseeeeneenneenee nennen neret en nernnren nre nrenneen 114 Offset 0x01408
220. ach bit in this field reflects the value of the corresponding GPIO pin 0x0 If corresponding bit in GPIO Data In Polarity Register is cleared to 0 the bit reflects the pin value with no change If corresponding bit in GPIO Data In Polarity Register is set to 1 the bit reflects the pin inverted value 31 26 Reserved RW Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 381 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary General Purpose Port Registers Table 570 GPIO Interrupt Cause Register Offset 0x10114 Bits Field Type Description InitVal 25 0 GPIOInt RWO A bit in this field is set on the transition of the corresponding bit in the 0x0 GPIODIn field in the GPIO Data In Register from 0 to 1 31 26 Reserved RW Reserved 0x0 Table 571 GPIO Interrupt Mask Register Offset 0x10118 Bits Field Type Description InitVal 25 0 GPlOIntEdge RW GPIO Interrupt Edge Sensitive Mask Mask 0x0 The mask bit for each cause bit in the lt GP OlInt gt field of the GPIO Interrupt Cause Register see Table 570 on page 382 0 Interrupt is masked 1 Interrupt is enabled The mask only affects the assertion of the interrupt bits in Main Interrupt Cause Register Table 61 p 102 It does not affect the setting of bits in the GPIO Interrupt Cause Register 31 26 Reserved RW Reserved 0x0 Table 572 GPIO Interrupt Level
221. address exactly the same as in the case of write access with the exception that the status code after the first address byte transmit is 0x40 and after 2nd address byte transmit in case of 10 bit address is OxEO 3 Read data being received from the target device is placed in the data register and acknowledge is driven on the bus Also an interrupt flag is set and status code of 0x50 is registered in the Status register The Marvell Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 43 Document Classification Proprietary June 25 2007 Preliminary Two Wire Serial Interface TWSI TWSI Slave Operation processor core reads data from Data register and clears the Interrupt flag to continue receiving next read data byte This loop is continued as long as the Marvell processor core wishes to read data from the target device 4 Toterminate the read access needs to respond with no acknowledge to the last data It then generates a stop condition or generates a new start condition to restart a new transaction With last data the Marvell processor core clears the TWSI Control register s Acknowledge bit when clearing the Interrupt bit causing the TWSI master interface to respond with no acknowledge to last received read data In this case the Interrupt flag is set with status code of 0x58 Now the Marvell processor core can issue a stop condition or a new start condition N Note The above sequence describes a normal operatio
222. and Encryption in CBC initial values enabling flexibility of use multi packet calculation sharing between resources e Byte Swap support for Data input and initial values e Byte Swap support for DES 3DES and AES data output e Automatic Engine activation when the required data block is loaded Saves write cycles e Authentication and encryption can be done simultaneously e Authentication and encryption termination interrupts e Supports DES OFB and CFB modes with additional software e AES encryption and decryption completely separate engines that can work simultaneously 10 1 4 Security Accelerator Features e Performs a complete over the packet operation with no software intervention e Supports two consecutive sessions allowing pipelining in packets processing e Supports four types of operation Authentication only MD5 SHA 1 HMAC MD5 HMAC SHA1 Encryption Decryption only DES SDES AES both ECB and CBC Authentication followed by Decryption Encryption Decryption Encryption followed by Authentication 10 2 Cryptographic Engines Operational Description 10 2 1 General The unit combines four separate engines e DES encryption decryption engine e AES128 encryption engine AES128 decryption engine Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 38 88F5182 marveL Open Source Community Progra
223. and Flow control is enabled The PSR EnFC bit is set then Pause disable frames timer OxFFFF are retransmitted at least every 4 2 msec 1000 Mbps 42 msec 100 Mbps or 420 msec 10 Mbps 10 Reserved 11 Reserved NOTE Only one mode is supported for enabling flow control When the link falls this field goes to disabled 0x00 and must be reprogrammed only after the link is up 8 7 ForceBPMode RW When this bit is set the port will start transmitting JAM on the line Back 0x0 pressure in half duplex which is only supported in 10 100 Mbps according to the following settings 00 No JAM no backpressure 01 JAM is transmitted continuously on next frame boundary 10 Reserved 11 Reserved NOTE When the link falls this field goes to disabled 0x00 and must be reprogrammed only after the link is up 9 Reserved RW Reserved 0x1 Must be set to 1 10 ForceLinkFail RW Force Link status on port to Link DOWN state 0x0 0 Force Link Fail 1 Do NOT Force Link Fail 12 11 Reserved RW Reserved 0x0 13 ANSpeed RW Enable Auto Negotiation of interface speed in GMII mode 0x0 0 Enable update 1 Disable update Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 285 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 393 Port Serial Control PSC Continued Offset 0x7243C Bits Field Type Descriptio
224. ansFrmSizExt gt is 0 00 Maximum Transmit Frame Size is 8 KB 01 Maximum Transmit Frame Size is 512B 10 Maximum Transmit Frame Size is 64B 11 Maximum Transmit Frame Size is 128B When lt TransFrmSizExt gt is 1 00 Maximum Transmit Frame Size is 256B 01 Maximum Transmit Frame Size is 1 KB 10 Maximum Transmit Frame Size is 2 KB 11 Maximum Transmit Frame Size is 4 KB 31 16 PortNumDevErr RO Each bit in this field is set to 1 when Register Device to Host FIS or Set 0x0 Device Bits FIS is received with bit lt ERR gt from the corresponding PM port setto 1 All bits in this field are cleared to 0 when the value of the lt eEnEDMAs field is changed from O to 1 Table 352 Serial ATA Interface Status Register Offset Port 0 0x8234C Port 1 0x8434C Bits Field Type Description InitVal 7 0 FISTypeRx RO FIS Type Received 0x0 This field specifies the FIS Type of the last received FIS 11 8 PMportRx RO Port Multiplier Received 0x0 This field specifies the Port Multiplier bits 11 8 in DWO of the FIS header of the last received FIS It also specifies the Port Multiplier bits 11 8 in DWO of the FIS header of the next Data Host to Device transmit FISs 12 VendorUqDn RO Vendor Unique FIS Transmission Done 0x0 This bit is set when the Vendor Unique FIS transmission has completed 0 Vendor Unique FIS transmission has not completed 1 Vendor Unique FIS transmission
225. ap is activated for output 0x0 0 No byte swap 1 Byte swap 30 9 Reserved RES Reserved 0x0 31 Termination RO This bit is set by the engine to indicate completion of a AES calculation pro 0x1 cess Any write to the encryption engine will clear this bit Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 325 Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers A 11 4 AES Decryption Interface Registers Table 471 AES Decryption Data In Out Column 3 Register Offset Ox9DDEO Bits Field Type Description InitVal 31 0 AesDecDatCol3 RW At first this field contains Column 3 of the input data block to be decrypted NA When the AES completes the calculation this field will contain the Column 3 of the AES result Table 472 AES Decryption Data In Out Column 2 Register Offset Ox9DDE4 Bits Field Type Description InitVal 31 0 AesDecDatCol2 RW At first this field contains Column 2 of the input data block to be decrypted NA When the AES completes the calculation this field will contain the Column 2 of the AES result Table 473 AES Decryption Data In Out Column 1 Register Offset Ox9DDE8 Bits Field Type Description InitVal 31 0 AesDecDatCol1 RW At first this field contains Column 1 of the input data block to be decrypted NA When the AES completes the calculation this field will contai
226. ar without the DEV prefix Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 48 MHZ sss MARvELL e Open Source Community Programmer s User Guide 13 4 Address Multiplexing Figure 9 provides a diagram of the address multiplexing Figure 9 Address Multiplexing TCIk ALE 1 ALEIO A 2 0 B A 5 3 X A 18 16 X A 2 0 L Al2 0 1 NK Address D 7 0 MK 5 5 X A 26 9 Dal MK Apa OO ATS Address OEn A 15 X WEn O0 A 16 CEn 13 5 NAND Flash Controller Implementation The NAND Flash controller implementation is shown in detailed in Figure 10 through Figure 12 It is controlled by NAND Flash Control Register Table 517 p 350 Burst transactions are supported by toggling the RE signal every read cycle as described in Figure 10 Figure 10 Mask ALE during NAND Flash Read Data Phase A 1 NEGET pe A 1 New Figure 11 Generate Dedicated NAND Flash WE Signal SENT __ Bw WEn O0 i connected to MPP i f Figure 12 Generate CE Covers All NAND Flash Transaction NF 4 SNFActCEn i a CEn i New CEn i Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 49 Document Classification Proprietary June 25 2007 Preliminary IDMA Controller Functional Description Section 14 IDMA Controller The 88F5182 has four independent ID
227. ary June 25 2007 Preliminary PCI Express Interface Registers Table 118 PCI Express Window1 Control Register Offset 0x41830 Bits Field Type Description InitVal 0 WinEn RW Window Enable 0x1 1 BarMap RW Mapping To BAR 0x0 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 15 8 Attr RW Target specific attributes depending on the target interface 0x0D 31 16 Size RW Window Size OxOFFF A value of OxOFFF specifies 256 MByte Table 119 PCI Express Window1 Base Register Offset 0x41834 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x1000 Table 120 PCI Express Window1 Remap Register Offset 0x4183C Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 136 88F5182 marveL Open Source Community Programmer s User Guide Table 121 PCI Express Window2 Control Register Offset 0x41840 Bits Field Type Description InitVal 0 Wi
228. ask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of Marvell processor core FIQ interrupt line It does not affect the setting of bits in the Cause register Table 64 Endpoint Interrupt Mask Register Offset 0x2020C Bits Field Type Description InitVal 31 0 Mask RW Mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of the interrupt pin It does not affect the set ting of bits in the Cause register The interrupt pin is asserted in the appro priate interface as defined by bit lt EndPointIF gt in the CPU Configuration Register Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 104 e 88F5182 E marveL Open Source Community Programmer s User Guide AAA CPU Timers Registers Table 65 CPU Timers Control Register Offset 0x20300 Bits Field Type Description InitVal 0 CPUTimerOEn RW CPU Timer 0 Enable 0x0 0 TimerO is disabled 1 Timer is enabled 1 CPUTimerOAuto RW CPU Timer 0 Auto Mode 0x0 When this bit is cleared to 0 and lt CPUTimer0 gt has reached zero lt CPUTimer0 gt stops counting When this bit is set to 1 and lt CPUTimer0 gt has reached zero CPUTimerORel is reload to lt CPUTimer0 gt then it continues to count 2 CPUTimer1En RW CPU Timer 1 Enable 0x0 0
229. assification Proprietary Page 226 MARVE Ki 88F5182 L1 Open Source Community Programmer s User Guide Table 311 EDMA Configuration Register Continued Offset Port 0 0x82000 Port 1 0x84000 Bits Field Type Description InitVal 10 Reserved RW Reserved 0x0 11 eRdBSzExt RO EDMA Burst Size Ext 0x0 This bit sets the maximum burst size initiated by the DMA to the Mbus RW This bit is related to the read operation 0x0 0 EDMA Burst size is configured according to field lt eRdBSz gt 1 Reserved NOTE This field must be set to 0 12 Reserved RW Reserved 0x1 This field must be set to Ox1 13 eWrBufferLen RW EDMA Write Buffers Length 0x0 This bit defines the length of the write buffers 0 Write buffer is 256B 1 Reserved NOTE This field must be set to 0 NOTE This bit value is ignored and assumed to be 0 if lt eRdBSZExt gt is cleared to 0 15 14 Reserved RW Reserved 0x0 16 eEDMAFBS RW EDMA FIS Frame Information Structure Based Switching 0x0 When cleared to 0 the EDMA issue a new command only when the pre vious command was completed or released by the drive When set to 1 EDMA issues a new command to the drive as soon as the target device is available regardless to the status of all of the other devices 17 eCutThroughEn RW This bit enables Basic DMA cut though operation when writing data to 0x0 the drive When the maximum read burst size initiated by the DMA to the Mb
230. ation Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 378 High Address Remap HA Offset HARRO 0x72280 HARR1 0x72284 HARR2 0x72288 HARR3 0x7228C Bits Field Type Description InitVal 31 0 Remap RW Remap address 0x0 Specifies address bits 63 32 to be driven to the target interface Relevant only for target interfaces that supports more than 4 GB of address space 1 Remap 0 corresponds to Base Address register 0 Remap 1 to Base Address register 1 Remap 2 to Base Address register 2 and Remap 3 to Base Address register 3 Table 379 Base Address Enable BARE Offset 0x72290 Bits Field Type Description InitVal 5 0 En RW Address window enable Ox3F This is one bit per window If it is set to 0 the corresponding address window is enabled Bit 0 matches to the Window0 bit 1 matches to Window1 etc 0 Enable 1 Disable 31 6 Reserved RO Reserved 0x0 Table 380 Ethernet Port Access Protect EPAP Offset 0x72294 Bits Field Type Description InitVal 1 0 Wino RW Window0 access control 0x3 0x0 No access allowed 0x1 Read Only 0x2 Reserved 0x3 Full access read or write In case of access violation for example write data to a read only region an interrupt is set and the transaction is written or read from the default address as specified in the default address register 3 2 Wi
231. ation mode disregarded in all other operation modes 1 Src1Cmd Specifies the type of operation to be carried out on the data pointed by SA 1 Source Address 1 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes 2 Src2Cmd Specifies the type of operation to be carried out on the data pointed by SA 2 Source Address 2 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes 3 Src3Cmd Specifies the type of operation to be carried out on the data pointed by SA 3 Source Address 3 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 55 Document Classification Proprietary June 25 2007 Preliminary XOR Engine Descriptor Chain Table 27 Descriptor Command Word Definition Continued Bit Field Description 4 Src4Cmd Specifies the type of operation to be carried out on the data pointed by SA 4 Source Address 4 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes 5 Src5Cmd Specifies the type of operation to be carried out on the data pointed by SA 5 Source Address 5 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes 6 Src6Cmd Specifies the type of operation to be carri
232. ator channel 0 activates the IDMA channel 0 when bit 5 in the Cryptographic Engines and Security Accelerator Interrupt Cause Register Table 489 p 332 is set to 1 10 Ch1ActivatelDMA RW Channel 1 Activation for IDMA 0x0 When set to 1 Security accelerator channel 1 activates the IDMA channel 1 when bit 6 in the Cryptographic Engines and Security Accelerator Interrupt Cause Register Table 489 p 332 is set to 1 31 11 Reserved RES Reserved 0x0 Table 488 Security Accelerator Status Register Offset 0x9DE0C Bits Field Type Description InitVal 0 SecurityActiveO RO State of the session 0 0x0 This bit equals lt AcclInt0 gt 0 Session 0 is idle 1 Session 0 is active 1 SecurityActive RO State of the session 1 0x0 This bit equals lt Acclnt1 gt 0 Session 0 is idle 1 Session 0 is active 7 2 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 331 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 488 Security Accelerator Status Register Continued Offset Ox9DEOC Bits Field Type Description InitVal 8 DecodeDigestErr RO Signals a decode digest error during session 0 This bit is cleared when ses 0 0x0 sion 0 is activated 9 DecodeDigestErr RO Signals a decode digest error during session 1 This bit is cleared when ses 1 0x0 sion 1 is
233. ault Address Map on page 14 31 16 Size RW Window Size 0x0 Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window e g a value of OxOOff specifies 256x64k 16 MB Table 433 USB 2 0 Window3 Base Register 0x50354 Port1 0xA0354 Offset Porto Bits Field Type Function InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x0 Used with the size field to set the address window size and location Corresponds to transaction address 31 16 Doc No MV S400130 00 Rev 0 5 Page 311 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary A 10 4 USB 2 0 Registers USB 2 0 PHY Registers Table 434 USB 2 0 Power Control Register 0x50400 Port1 0xA0400 Offset Port Bits Field Type Function InitVal 0 Pu RW Input Power Up 0x1 1 PuPII RW Input Power Up PLL 0x1 2 SUSPENDM RW Input SUSPENDM 0x1 3 VBUS_PWR_ RW Vbus Power Fault FAULT 0x0 Connect to the Core not to the PHY 4 PWRCTL_ RW USB Power Control Wake Up WAKEUP 0x0 Connect to the Core not to the PHY 5 PuRef RW Power Up Reference 0x1 Connect to ana_grp 7 6 BG_VSEL RW BG VSEL 0x1 Connect to ana_grp 8 REG_ARC_DP RW 0 Use register programmed pulldown DM_MODE 0x1 1 Use
234. ause bits 0x0 23 21 Reserved RES Reserved 0x0 28 24 Various RW Same as channel0 cause bits 0x0 31 29 Reserved RES Reserved 0x0 1 All cause bits are clear only They are set to 1 upon an interrupt event and cleared when the software writes a value of 0 Writing 1 has no affect Table 538 Interrupt Mask Register Offset 0x608C4 Bits Field Type Description 0 Comp RW Comp Interrupt 0x0 0 Disable 1 Enable 1 AddrMiss RW Address Miss Interrupt 0x0 0 Disable 1 Enable 2 AccProt RW Access Protection Interrupt 0x0 0 Disable 1 Enable 3 WrProt RW Write Protection Interrupt 0x0 0 Disable 1 Enable 4 Own RW Ownership Violation Interrupt 0x0 0 Disable 1 Enable 7 5 Reserved RES Reserved 0x0 12 8 Various RW Same as channel0 mask bits 0x0 15 13 Reserved RES Reserved 0x0 20 16 Various RW Same as channel0 mask bits 0x0 23 21 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 361 Document Classification Proprietary June 25 2007 Preliminary IDMA Controller Interface Registers Table 538 Interrupt Mask Register Continued Offset 0x608C4 Bits Field Type Description 28 24 Various RW Same as channel0 mask bits 0x0 31 29 Reserved RES Reserved 0x0 Table 539 Error Address Register Offset 0x608C8 Bits Field Type Description 31 0 ErrAddr RW Bits 31 0 of Error Address 0x0 Latched
235. barMaskO RW If set to 1 XbarErr interrupt is enabled 0x0 15 10 Reserved RW Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 370 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 546 XOR Engine Interrupt Mask XEIMR Continued Offset 0x60940 Bit Field Type Description InitVal 25 16 Channel 1 RO Same for XOR Engine Channel 1 0x0 31 26 Reserved RO Reserved 0x0 Table 547 XOR Engine Error Cause XEECR Offset 0x60950 Bit Field Type Description InitVal 4 0 ErrorType ROC Specifies the error event currently reported in the Error Address register 0x0 0x0 Null 0x1 0x3 Reserved 0x4 AddrDecodeO 0x5 AccProtO 0x6 WrProtO 0x7 0x13 Reserved 0x14 AddrDecode1 0x15 AccProt1 0x16 WrProt1 0x17 0x1F Reserved This field is self cleared by reading the Error Address Register XEEAR Once the error cause is latched no new error cause or address is latched to XEECR or XEEAR until SW reads XEEAR The Software should read XEECR first and than XEEAR 31 5 Reserved RO Reserved 0x0 Table 548 XOR Engine Error Address XEEAR Offset 0x60960 Bit Field Type Description InitVal 31 0 ErrAddr RO Bits 31 0 of Error Address 0x0 Latched upon any of the address windows violation event address miss
236. ble address windows for the different interfaces See Section A 8 7 SATAHC Arbiter Registers on page 218 By default the SATAHC address map is enabled and addressed to the DRAM as specified in Table 1 88F5182 Default Address Map on page 14 2 5 Gigabit Ethernet Address Map The Gigabit Ethernet interface address map consists of six programmable address windows for the different interfaces By default the Gigabit Ethernet MAC address map is disabled 2 6 USBO Address Map The USBO interface address map consists of four programmable address windows for the different interfaces By default the USBO address map is disabled 2 7 USB1 Address Map The USB1 interface address map consists of four programmable address windows for the different interfaces By default the USB1 address map is disabled 2 8 IDMA Address Map The IDMA interface address map consists of eight programmable address windows for the different interfaces See Section A 15 2 IDMA Address Decoding Registers on page 356 By default the IDMA address map is disabled 2 9 XOR Address Map The XOR interface address map consists of eight programmable address windows for the different interfaces See Section A 16 4 XOR Engine Address Decoding Registers on page 372 By default the XOR address map is disabled y Note Windows base addresses of the 88F5182 must be aligned to their size for example a 128 KB address window should be aligned to 128 KB 2 10 Default
237. c DMA directly it is recommended to clear this bit to 0 0 Early DMA completion disabled 1 Early DMA completion enabled 19 eEDMAQueLen RW EDMA response queue and request queues length 0x0 0 32 entries 1 128 entries 21 20 Reserved RW Reserved 0x0 22 eHostQueue RW EDMA Host Queue Cache Enable CacheEn 0x0 When set to 1 the EDMA is capable of storing up to four commands internally before sending the commands to the drive This bit enables the EDMA to send multiple commands across multiple drives much faster It also enables the EDMA to send commands to any available drive while other drives are busy executing previous com mands 0 Host Queue Cache is disabled EDMA stores a single command internally Only when the command is sent to the drive it fetches a new command from the CRQB 1 Host Queue Cache is enabled 23 eMaskRxPM RW This bit masks the PM field in the incoming FISs 0x0 0 Mask the PM field in incoming FISs 1 Do not mask 24 ResumeDis RW When set to 1 the EDMA never sets the lt ContFromPrev gt field in the 0x0 Basic DMA Command Register Table 331 p 242 When cleared to 0 the EDMA sets field lt ContFromPrev gt whenever possible Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 228 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 311 EDMA Config
238. cation List of Registers Doc No MV S400130 00 Rev 0 5 Proprietary Page 72 88F5182 marveL Open Source Community Programmer s User Guide Table 229 PCI Access Control Base 2 High esseseeseeeeeeeeeenennee nennen rentre enne 190 Offset 0x31E24 Table 230 PCI Access Control Size 2 iced asse cat ea anian aei daakinii mah iaa iiihana keii ea 190 Offset 0x31E28 Table 231 PCI Access Control Base 3 Low ener nennen trennen rennen enne 190 Offset 0x31E30 Table 232 PCI Access Control Base 3 High eese seen nete nannten antennae nennen 191 Offset 0x31E34 Table 233 PCI Access Control Size 3 nennen enne aieas Enean TEA BENOSA ENEKI nnns 191 Offset 0x31E38 Table 234 PCI Access Control Base 4 Low nennen treten enne reete nennen 191 Offset 0x31E40 Table 235 PCI Access Control Base 4 High esee nnnm nennen ene rennen eterne 191 Offset 0x31E44 Table 236 PCI Access Control Size 4 u aiiis eee estie ane i ducc a aei NR ER ede addas AEAN ENEE 191 Offset 0x31E48 Table 237 PCI Access Control Base 5 Low nennen nne enne rentre nenne teen 192 Offset 0x31E50 Table 238 PCI Access Control Base 5 High eeeseessseseeeeceeeeeeaceseesaeesaeesaneeaesseaesaesneseaeseaensaeseesseseneeseeseaneaees 192 Offset 0x31E54 Table 239 PCI Access Control Gizeb nne nennen et nnns eres e tennrnn serre n trn snnt seen 192
239. cation Proprietary Page 344 88F5182 marveL Open Source Community Programmer s User Guide Table 507 Line Control Register LCR Continued Offset UART 0 0x1200C UART 1 0x1210C Bits Field Type Description InitVal 6 Break RW The Break bit sends a break signal by holding the SOUT line low until 0x0 the Break bit is reset 0 Do not send a break signal 1 Send a break signal 7 DivLatchRdWrt RW This bit must be set to address reading and writing of the Divisor Latch 0x0 Low DLL Register Register Table 502 p 342 and Divisor Latch High DLH Register Register Table 504 p 343 to set the baud rate of the UART This bit must be cleared to address the Receive Buffer Register RBR Register Table 500 p 341 Transmit Holding Register THR Register Table 501 p 341 and the Interrupt Enable Register IER Register Table 503 p 342 31 8 Reserved RSVD Reserved Table 508 Modem Control Register MCR Offset UART 0 0x12010 UART 1 0x12110 Bits Field Type Description InitVal 0 Reserved RSVD Reserved 1 RTS RW Request To Send 0x0 The lt RTS gt bit is inverted and then drives the corresponding UAO_RTSn and UA1_RTSn output 3 2 Reserved RSVD Reserved 4 Loopback RW Loopback 0x0 The lt Loopback gt bit loops the data on the sout line back to the sin line In this mode all the interrupts are fully functional This feature is used for diagnostic purp
240. ccessfully and returns the ownership of the descriptor to the CPU N Note Chain descriptor operation is valid only in XOR CRC and DMA operation modes In ECC and Meminit modes the XOR engine gets the operation data directly from its internal registers Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 53 Document Classification Proprietary June 25 2007 Preliminary XOR Engine Descriptor Chain Figure 14 XOR Descriptor Format 81 0 0x0 Status 0x4 CRC 32 Result 0x8 Command CRC amp DMA OxC Next Descriptor Address EES 0x10 Byte Count 0x14 Destination Address 0x18 Source Address 0 XOR Ox1C Source Address 1 Gees 0x20 Source Address 2 0x24 Source Address 3 0x28 Source Address 4 0x2C Source Address 5 0x30 Source Address 6 0x34 Source Address 7 0x38 Reserved Ox3C Reserved y Note The XOR descriptor must be 64 Bytes aligned Address 5 0 0 The CRC and DMA descriptors must be 32 Bytes aligned Address 4 0 0 There are no restrictions on source or destination data block alignment Source and destination blocks can have different alignments Different source blocks can have different alignments as well Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 54 88F5182 marveL Open Source Community Programmer s User Guide Table 25 Descriptor Status Word Definition
241. ceived with bit ERR set to 1 3 eDevDis RWO EDMA Device Disconnect 0x0 This bit is set to 1 if the device is disconnected 0 Device was not disconnected 1 Device was disconnected NOTE After DevDis interrupt device hard reset is required Set the lt eAtaRst gt field in the EDMA Command Register Table 321 p 236 to 1 4 eDevCon RWO EDMA Device Connected 0x0 This bit is set to 1 if the device was disconnected and is connected again 0 Device was not reconnected 1 Device was reconnected 5 Serrint RWO This bit is setto 1 when at least one bit in SError Register see Table 338 on 0x0 page 246 is set to 1and the corresponding bit in SError Interrupt Mask Register see Table 339 on page 248 is enabled 0 A bit in SError Register was not set to 1 1 A bit in SError Register was set to 1 NOTE This bit should be cleared only after clearing the SError Register 6 Reserved RWO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 230 e MARVELL 88F5182 Open Source Community Programmer s User Guide Table 313 EDMA Interrupt Error Cause Register Continued Offset Port 0 0x82008 Port 1 0x84008 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 7 eSelfDis RWO EDMA Self Disable
242. ceiver is powered down a simple CMOS receiver is activated NOTE This mode is only valid when working with a 16 bit DDR interface 31 9 Reserved RES Reserved Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 126 MSE sss marveL Open Source Community Programmer s User Guide A 6 PCI Express Interface Registers Table 107 PCI Express Register Map Table Register Name Offset Table amp Page PCI Express BAR Control Registers PCI Express BAR1 Control Register 0x41804 Table 108 p 129 PCI Express BAR2 Control Register 0x41808 Table 109 p 129 PCI Express Expansion ROM BAR Control Register 0x4180C Table 110 p 130 PCI Express Configuration Requests Generation Registers PCI Express Configuration Address Register 0x418F8 Table 111 p 130 PCI Express Configuration Data Register 0x418FC Table 112 p 131 PCI Express Interrupt Registers PCI Express Interrupt Cause 0x41900 Table 113 p 131 PCI Express Interrupt Mask 0x41910 Table 114 p 134 PCI Express Address Window Control Registers PCI Express Window0 Control Register 0x41820 Table 115 p 134 PCI Express Window0 Base Register 0x41824 Table 116 p 135 PCI Express Window0 Remap Register 0x4182C Table 117 p 135 PCI Express Window1 Control Register 0x41830 Table 118 p 136 PCI Express Window1 Base Register 0x41834
243. cked until the register is read Used for software debug after address violation interrupt is raised This field is read only Table 373 Ethernet Unit Internal Address Error EUIAE Offset 0x72098 Bits Field Type Description InitVal 8 0 Internal RO If there is an address violation of unmapped access to the Gigabit Ethernet Address 0x0 unit top registers locks the relevant internal address bits bit 12 and bits 9 2 The Address is locked until the register is read NOTE This field is used for software debugging after an address violation interrupt is raised 31 9 Reserved RO Reserved 0x0 Table 374 Ethernet Unit Port Pads Calibration EUPCR Offset 0x720A0 Bits Field Type Description InitVal 4 0 DrvN RW Pad Nchannel Driving Strength 0xB NOTE Only applicable when auto calibration is disabled Doc No MV S400130 00 Rev 0 5 Page 273 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Gigabit Ethernet Controller Registers Table 374 Ethernet Unit Port Pads Calibration EUPCR Continued Offset 0x720A0 Bits Field Type Description InitVal 15 5 Reserved RO Reserved 0x0 16 TuneEn RW Set to 1 enables the auto calibration of pad driving strength 0x0 21 17 LockN RO When auto calibration is enabled represents the final locked value of the 0x0 Nchannel Driving Strength Read Only 23 22
244. criptor Byte Count Word 56 Table 30 Descriptor Destination Address Word 57 Table 31 Descriptor Source Address N Words eene enne nnne nnns 57 Table 32 88F5182 Internal Registers Address Map 89 Table33 GPU Register Map iiit e e GRE ER PETERE DURER Ea ETE HARE 90 Table 76 DDR SDRAM Register Map 109 Table 107 PCI Express Register Map Table 127 Table 178 PCI Slave Address Decoding Register Map 169 Table 179 PGlI Control Register Map cette eite tereti gre ro m sheng a rendue deeg ee reco 170 Table 180 PCI Configuration Access Register Map nennen nennen nnne nnn 170 Table 181 PCI Error Report Register Map 171 Table 182 PCI Configuration Function 0 Register Map 171 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 6 MSE sss marveL Open Source Community Programmer s User Guide Table 183 PCI Configuration Function 1 Register Map 172 Table 184 PCI Configuration Function 2 Register Map 172 Table 185 PCI Configuration Function 3 Register Map 172 Table 186 PCI Configuration Function 4 Register Map 172 Table 288 SATAHC Address Gpace eene nnne nennen rns etn tn nere trn enne Enn nnne nnne 213 Table 289 SATAHC Arbiter Registers Map 213 Table 290 EDMA Registers Map eeeseesssseeesseeeeeeeeee enne nenne rentre senten nnn nnn rin trenes nennen nein aE ENE 214 Table 291 Shadow Register Block Registers
245. d command e Queued DMA write command e Read FPDMAQueued command e Write FPDMAQueued command The SATA II interface does not support the following protocols ATAPI Packet command e CEA commands 1 AC coupling is still required while working with Gen1 devices Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 20 e 88F5182 marveL Open Source Community Programmer s User Guide Section 7 Serial ATA Il Host Controller SATAHC The 88F5182 incorporates a Serial ATA SATA host controller SATAHC The SATAHC integrates two independent SATA ports A dedicated Enhanced DMA EDMA controls each port 7 1 SATAHC Block Diagram The 88F5182 SATAHC consists of an arbiter two EDMAs and two SATA ports Both EDMAs are independent and may work concurrently see Figure 2 Figure 2 SATAHC Block Diagram MBUS Interface SATAHC Arbiter Unit EDMA EDMA Port 1 Port 0 SATA SATA Interface Interface ZEE SATA Port 1 SATA Port 0 7 2 EDMA Operation The SATAHC contains two EDMAs This document only describes the operation of a single EDMA within the SATAHC See Figure 2 SATAHC Block Diagram on page 21 and refer to Appendix A 8 Serial ATA Host Controller SATAHC Registers on page 213 The interface between host CPU and each EDMA consists of two queues the request queue and the response queue
246. d data is written into master read buffer 8 MRdLine RW PCI Master Memory Read Line Enable 0x1 0 Disable 1 Enable Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 182 88F5182 marveL Open Source Community Programmer s User Guide Table 215 PCI Command Continued Offset 0x30C00 Bits Field Type Description InitVal 9 MRdMul RW PCI Master Memory Read Multiple Enable Ox1 0 Disable 1 Enable 10 MWordSwap RW PCI Master Word Swap 0x0 When set to 1 the 88F5182 PCI master swaps the 32 bit words of the incoming and outgoing PCI data 11 SWordSwap RW PCI Slave Word Swap 0x0 When set to 1 the 88F5182 PCI slave swaps the bytes of the incoming and outgoing PCI data swaps the two words of a long word 12 Reserved RES Reserved 0x0 13 Reserved RES Reserved 0x1 14 Reserved RW Reserved 0x1 15 Reserved RES Reserved 0x0 16 SByteSwap RW PCI Slave Byte Swap 0x1 When set to 0 the 88F5182 PCI slave swaps the bytes of the incoming and outgoing PCI data swap the 8 bytes of a long word 17 MDACEn RW PCI Master DAC Enable 0x1 0 The PCI master never drives the DAC cycle 1 The PCI master drives the DAC cycle if the upper 32 bit address is not 0 18 Reserved RES Reserved 0x0 19 PErrProp RW Parity ECC Errors Propagation Enable 0x0 0 The PCI interface always drives correct parity on the P
247. d from the device after a service command TCQ or when the tag is read from the device in DMA Setup FIS NCQ 0 System memory to device 1 Device to system memory 6 eCacheEmpty RO Cache Empty 0x1 This field indicates if EDMA cache is empty 0 Cache not empty 1 Cache empty 7 EDMAldle RO This bit is set to 1 when all of the following conditions occur 0x0 e Nocommands are pending in EDMA request queue AND All command EDMAs taken from the EDMA request queue were delivered to the drive AND All command completions EDMA received from the drive were delivered to the host response queue AND A All commands sent to the drives were either completed or released AND e EDMAisin idle state e EDMAis enabled NOTE This bit may be set when a command is still pending in the drive 15 8 eSTATE RO EDMA State 0x0 These bits indicate the current state of the machine 21 16 elOld RO EDMA IO ID 0x0 This field indicates the IO ID of the last command used by the EDMA The EDMA updates this field when a new command is written to the device or when the device sends a completion FIS NonQ TCQ RegD2H with REL bit cleared and lt DRQ gt bit cleared NCQ reception of SDB FIS or when the DMA is activated after a reception of DMA Activate FIS or a reception of a DATA FIS 31 22 Reserved RES Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary
248. d transmitted Good and Bad frames that are 128 to 255 bytes in size NOTE This does not include MAC Control frames 0x2C 32 Frames256to511Octets The total number of received and transmitted Good and Bad frames that are 256 to 511 bytes in size NOTE This does not include MAC Control frames 0x30 32 Frames512to1023Octets The total number of received and transmitted Good and Bad frames that are 512 to 1023 bytes in size NOTE This does not include MAC Control frames 0x34 32 Frames1024toMaxOctets The total number of received and transmitted Good and Bad frames that are more than 1023 bytes in size and less than the MRU NOTE This does not include MAC Control frames 0x38 64 GoodOctetsSent The sum of lengths of all good Ethernet frames sent from this MAC This does not include 802 3 Flow Control frames NOR pack ets dropped due to excessive collision NOR packets with an Tx Error Event 0x40 32 GoodFramesSent The number of Ethernet frames sent from this MAC This does not include 802 3 Flow Control frames NOR packets dropped due to excessive collision NOR packets with an Tx Error Event Doc No MV S400130 00 Rev 0 5 Page 303 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary Table 418 MAC MIB Counters Continued Gigabit Ethernet Controller Registers Offset 0x73000 0x7307C NOTE MIB counters are ROC Read Only Clear R
249. data to be transmitted from the serial port Any time that the Transmit Holding Register Empty lt THRE gt bit of the Line Status Register LSR is set see Table 509 on page 346 data can be written to the LSR lt TxEmpty gt to be transmitted from the serial port If FIFOs are not enabled and THRE is set writing a single word to the THR resets the THRE and any additional writes to the THR before the THRE is set again causes the THR data to be overwritten If FIFOs are enabled and lt THRE gt is set up to 16 words of data may be written to the THR before the FIFO is full Any attempt to write data when the FIFO is full results in the write data being lost 31 8 Reserved RSVD Reserved Doc No MV S400130 00 Rev 0 5 Page 341 Copyright O 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary UART Interface Registers Table 502 Divisor Latch Low DLL Register Offset UART 0 0x12000 UART 1 0x12100 NOTE lt DivLatchRdWrt gt bit 7 of the Line Control Register LCR Register Table 507 p 344 must be set to 1 Bits Field Type Description InitVal 7 0 DivLatchLow WO The DLH Divisor Latch High register in conjunction with DLL Divisor 0x0 Latch Low register forms a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART It is accessed by first setting the DivLatchRdWrt bit in the Line Control Register
250. ddressing See Section 7 2 3 3 EDMA Physical Region Descriptors ePRD Table Data Structure on page 29 The CPU accesses this register for direct access to the device when the EDMA is disabled Bits Field Type Description InitVal 3 0 Reserved RES Reserved 0x0 31 4 Descriptor Table RW The Descriptor Table Base Address corresponds to address A 31 4 The Base Address 0x0 descriptor table must be 16 byte aligned Table 334 Descriptor Table High Base Address Register Offset Port 0 0x82230 Port 1 0x84230 NOTE Enhanced Physical Region Descriptors are in use to enable 64 bit memory addressing See Section 7 2 3 3 EDMA Physical Region Descriptors ePRD Table Data Structure on page 29 Bits Field Type Description InitVal 31 0 Descriptor Table RW The Descriptor Table Base Address corresponds to address A 63 32 Base Address 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 244 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 335 Data Region Low Address Register Offset Port 0 0x82234 Port 1 0x84234 NOTE The CPU accesses this register for direct access to the device when the EDMA is disabled Field lt eEnEDMAs in EDMA Command Register see Table 321 on page 236 is cleared While the EDMA is enabled the host must not write this register If any
251. dow2 access control 0x3 23 22 Win3acc RW Windows access control 0x3 25 24 Win4acc RW Window4 access control 0x3 27 26 Winbacc RW Window5 access control 0x3 29 28 Win6acc RW Window6 access control 0x3 31 30 Win7acc RW Window7 access control 0x3 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 373 Document Classification Proprietary June 25 2007 Preliminary XOR Engine Registers Table 553 XOR Engine Base Address XEBARx Offset XEBARO 0x60B50 XEBAR1 0x60B54 XEBAR2 0x60B58 XEBAR3 0x60B5C XEBAR4 0x60B60 XEBAR5 0x60B64 XEBAR6 0x60B68 XEBAR7 0x60B6C Bit Field Type Description InitVal 3 0 Target RW Specifies the target interface associated with this window 0x0 See Address Decoding chapter for full details 7 4 Reserved RO Reserved 0x0 15 8 Attr RW Specifies target specific attributes depending on the target interface 0x0 See Table 1 88F5182 Default Address Map on page 14 31 16 Base RW Base Address 0x0 Used with the size register to set the address window size and location within the range of 4 GB space Table 554 XOR Engine Size Mask XESMRx Offset XESMRO 0x60B70 XESMR1 0x60B74 XESMR2 0x60B78 XESMR3 0x60B7C XESMRA 0x60B80 XESMR5 0x60B84 XESMR6 0x60B88 XESMR7 0x60B8C Bit Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 31 16 SizeMask RW Window Size 0x0 Used with the size register to set the address window size and l
252. dp_pulldown and dm_pulldown from controller core 9 REG_DP_PULL RW Register DP Pull DOWN 0x0 0 No DP pulldown 1 Pull down DP 10 REG_DM_PUL RW Register DM Pull LDOWN 0x0 0 No DM pulldown 1 Pull down DM 22 11 Reserved RW Reserved 0x0 23 utmi_sessend RW UTMI Session End 0x0 24 utmi_vbus_valid RW UTMI Vbus Valid 0x1 25 utmi_avalid RW UTMI A Valid 0x1 26 utmi_bvalid RW UTMI B Valid 0x1 27 TX_BIT_STUFF RW Transmit Bit Stuff 0x1 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 312 88F5182 MARVELL Open Source Community Programmer s User Guide Table 434 USB 2 0 Power Control Register Continued Offset Port 0x50400 Port1 0xA0400 Bits Field Type Function InitVal 31 28 Reserved RW Reserved Ox1F Doc No MV S400130 00 Rev 0 5 Page 313 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers A 11 Cryptographic Engine and Security Accelerator Registers Table 435 Cryptographic Engine and Security Accelerator Register Map Register Offset Table Page DES Engine Registers DES Data Out Low Register Ox9DD78 Table 436 p 316 DES Data Out High Register Ox9DD7C Table 437 p
253. dress 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 141 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers A 6 5 PCI Express Control and Status Registers Table 136 PCI Express Control Register Offset 0x41A00 Bits Field Type Description InitVal 0 Reserved RSVD Reserved 0x1 Must write 1 1 ConfRoot RO PCI Express Device Type Control Complex 0x0 0 Endpoint Endpoint device downstream device upstream link 1 Root Root Complex device upstream device downstream link NOTE Cannot be configured during operation must be configured only by reset strapping or from TWSI during auto_loader 2 CfgMapTo RW Configuration Header Mapping to Memory Space Enable MemEn 0x1 When enabled the configuration header registers can be accessed directly through the memory space Access is enabled both from the internal bus and from the PCI Express port 0x0 Disabled Mapping disabled 0x1 Enabled Mapping enabled 7 3 Reserved RSVD Reserved 0x1 9 8 Reserved RSVD Reserved 0x3 Must write 0x3 15 10 Reserved RSVD Reserved 0x0 23 16 Reserved RSVD Reserved 0x14 Must write 0x14 24 ConfMstr RW Master Hot Reset HotReset 0x0 When set a hot reset command is transmitted downstream causing the downstream PCI Express hierarchy to enter a hot reset cycle This bit can be set only if LnkDis in the PCI Express Link Control Status Register and bit
254. e SS Les a MARVELL 88F5182 based Storage Networking Platforms Open Source Community Programmer s User Guide Marvell Moving Forward Faster Doc No MV S400130 00 Rev 0 5 June 25 2007 Document Classification Proprietary 88F5182 MARVELL OpenSource Community Programmer s User Guide Document Conventions N Note Provides related information or information of special importance Caution Indicates potential damage to hardware or software or loss of data e Warning Indicates a risk of personal injury Document Status Doc Status Preliminary Technical Publication 0 x For more information visit our website at www marvell com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means electronic or mechanical including photocopying and recording for any purpose without the express written permission of Marvell Marvell retains the right to make changes to this document at any time without notice Marvell makes no warranty of any kind expressed or implied with regard to any information contained in this document including but not limited to the implied warranties of merchantability or fitness for any particular purpose Further Marvell does not warrant the accuracy or completeness of the information text graphics or other items contained within this document Marvell products are not designed for use in life support equipment or applications
255. e Description InitVal 31 12 Various RO Same as CSn 0 Base Address Low 0x0 Table 275 PCI CSn 3 Base Address High Offset 0x1C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 A 7 7 Function 2 Configuration Registers Table 276 PCI DevCS 0 Base Address Low Doc No MV S400130 00 Rev 0 5 Page 209 Document Classification Proprietary Offset 0x10 Bits Field Type Description InitVal 0 MemSpace RO Memory Space Indicator 0x0 2 1 Type RW BAR Type Initial Value InitVal 0x2 Located anywhere in 64 bit address space NOTE Read only from PCI 3 Prefetch RW Prefetch Enable 0x0 NOTE Read only from PCI 11 4 Reserved RES Read only 0x0 31 12 Various RW Same as CSn 0 Base Address Low 0xE0000 Copyright 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 277 PCI DevCSn 0 Base Address High Offset 0x14 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0 Table 278 PCI DevCSn 1 Base Address Low Offset 0x18 Bits Field Type Description InitVal 31 0 Various 0x0 Same as DevCSn 0 Base Address Low Table 279 PCI DevCSn 1 Base Address High Offset 0x1C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address High 0x0
256. e Reset 0 DDR1 Strap 1 DDR2 17 RegDIMM RW Registered DIMM enable 0x0 0 Non buffered DIMM 1 Registered DIMM NOTE Even if using DDR SDRAM devices on board this register can still be used to buffer DDR SDRAM address control signals In that case set lt RegDIMM gt bit to 1 18 Perr RW Erroneous write data policy 0x1 0 Ignore erroneous data indication Write data to DDR SDRAM 1 Do not write to DDR SDRAM upon erroneous data indication 19 Reserved RW Reserved 0x0 21 20 DCfg RW DDR SDRAM devices configuration 0x2 0x0 Reserved 0x1 x16 devices 0x2 x8 devices 0x3 Reserved 23 22 Reserved RO Reserved 0x0 24 SRMode RW Reserved 0x1 Must be 0x1 25 SRCIk RW Clock drive upon self refresh 0x1 0 Clock is kept driven during self refresh 1 Clock is gated during self refresh 31 26 Reserved RO Reserved 0x0 Table 86 DDR SDRAM Control Register Offset 0x01404 Bits Field Type Description InitVal 5 0 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 113 Document Classification Proprietary June 25 2007 Preliminary DDR SDRAM Controller Registers Table 86 DDR SDRAM Control Register Continued Offset 0x01404 Bits Field Type Description InitVal 6 CtrlPos RW Address Control Output Timing 0x1 0 Toggle on falling edge of clock 1 Toggle on rising edge of clock NOTE Set according
257. e 11 of device controller Mbus SDRAM arbiter OxB 19 16 Arb12 RW Slice 12 of device controller Mbus SDRAM arbiter OxC 23 20 Arb13 RW Slice 13 of device controller Mbus SDRAM arbiter OxD 27 24 Arb14 RW Slice 14 of device controller Mbus SDRAM arbiter OxE Doc No MV S400130 00 Rev 0 5 Page 125 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary DDR SDRAM Controller Registers Table 104 DDR SDRAM Interface Mbus Control High Register Continued Offset 0x01434 Bits Field Type Description InitVal 31 28 Arb15 RW Slice 15 of device controller Mbus SDRAM arbiter OxF Table 105 DDR SDRAM Interface Mbus Timeout Register Offset 0x01438 Bits Field Type Description InitVal 7 0 Timeout RW Mbus SDRAM Arbiter Timeout Preset Value OxFF 15 8 Reserved RO Reserved 0x0 16 TimeoutEn RW Mbus SDRAM Arbiter Timer Enable 0x1 0 Enable 1 Disable 31 17 Reserved RO Reserved 0x0 Table 106 DDR SDRAM MMask Register Offset 0x014B0 Bits Field Type Description InitVal 1 0 Reserved RES Reserved 3 2 ODTSel4StatB RW DDR Controller UO Buffer ODT Select for StartBurst urst 0x00 0 Turned off 12150 ohm 2 75ohm 3 50 ohm 4 ODTEn4StartB RW DDR Controller I O Buffer ODT Enable urst 0x0 0 ODT disable 1 ODT enable 8 5 DDR2PADCom 0 Power down of DDR1 DDR2 PAD receiver pPowerDown OxF When the re
258. e PCI Master when acting as a requester A 0x00 value means a retry forever 31 24 Reserved RES Reserved 0x0 Table 218 PCI Discard Timer Offset 0x30D04 NOTE This register should not be updated while read buffers are not cleared Bits Field Type Description InitVal 15 0 Timer RW Specifies the number of PCLK cycles the 88F5182 PCI slave keeps a 0x0 non accessed read buffers non completed delayed read before invalidating the buffer Set to 0 to disable the timer The PCI slave waits for delayed read completion forever NOTE Must be set to a number greater than 0x7F unless using the wait for ever setting 0x0 Must not be updated while there are pending read requests 31 16 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 185 Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 219 MSI Trigger Timer Offset 0x30C38 Bits Field Type Description InitVal 15 0 Timer RW Specifies the number of TCLK cycles between consecutive MSI OxFFFF requests NOTE If set to 0x0 the timer is disabled 31 16 Reserved RES Reserved 0x0 Table 220 PCI Arbiter Control Offset 0x31D00 NOTE Arbiter setting can not be changed while in work It should only be set once Bits Field Type Description InitVal 0 Reserved RES Reserved 0x0 1 BDEn RW Broken
259. e Receive Buffer Register RBR Transmit Holding Register THR and Interrupt Enable Register IER Table 499 UART interface Registers Map Register Offset Table Page Type lt DivLatchRdWrt gt Setting Receive Buffer Register RBR UART 0 0x12000 Table 500 p 341 RO 0 UART 1 0x12100 Transmit Holding Register THR UART 0 0x12000 Table 501 p 341 WO 0 UART 1 0x12100 Divisor Latch Low DLL Register UART 0 0x12000 Table 502 p 342 RW 1 UART 1 0x12100 Interrupt Enable Register IER UART 0 0x12004 Table 503 p 342 RW 0 UART 1 0x12104 Divisor Latch High DLH Register UART 0 0x12004 Table 504 p 343 RW 1 UART 1 0x12104 Interrupt Identity Register IIR UART 0 0x12008 Table 505 p 343 RO NA UART 1 0x12108 FIFO Control Register FCR UART 0 0x12008 Table 506 p 343 WO NA UART 1 0x12108 Line Control Register LCR UART 0 0x1200C Table 507 p 344 RW NA UART 1 0x1210C Modem Control Register MCR UART 0 0x12010 Table 508 p 345 RW NA UART 1 0x12110 Line Status Register LSR UART 0 0x12014 Table 509 p 346 RO NA UART 1 0x12114 Modem Status Register MSR UART 0 0x12018 Table 510 p 347 RO NA UART 1 0x12118 Scratch Pad Register SCR UART 0 0x1201C Table 511 p 347 RW NA UART 1 0x1211C Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 340 MA
260. e TCP and UDP checksum calculations are put into the receive descriptor and are compared with the frame checksum for non IP fragmented frames even for frames over 9 KB The Ethernet port provides a great amount of flexibility with many programmable features The TCP UDP and IP checksums are generated on any frame size This is programmable per frame by command settings in the first descriptor of the frame In addition Cyclic Redundancy Check CRC generation is programmable for each frame There are separate programmable transmit and receive interrupt coalescing mechanisms to aggregate several interrupts on a time based masking window before sending an indication to the CPU The unit provides programmable zero padding of short frames frames less that 64 bytes A transmit buffer of any byte alignment and any size greater than 8 bytes is supported Minimum packet size is 32 bytes In the event of collision frames are retransmitted automatically without additional fetch An Error and Collision report is provided in the last buffer descriptor 8 2 Port Features The 10 100 1000 Mbps Gigabit Ethernet port provide the following features e IEEE 802 3 compliant MAC layer function e EEE 802 3u compliant MII interface e 1000 Mbps operation full duplex e 10 100 Mbps operation half and full duplex e GMII symmetric flow control IEEE 802 3x flow control for full duplex operation mode MII symmetric flow control Backpressure f
261. e device is performed the data written to the link layer is written into an 8 bit temporary register which receives the last 8 bits of data in the store command When in load it duplicates the 8 bit data either four times or eight times depending on the PCI bus width For every PCI width data phase either 64 bits or 32 bits the loopback data is inverted i e for example in 32 bit PCI if the last 8 bits in store were 0 the data returned on load would be 32 b0 32 b1 32 b0 0 EDMA Loopback mode disabled 1 EDMA Loopback mode enabled 31 2 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 237 Document Classification Proprietary June 25 2007 Preliminary Table 323 EDMA Status Register Offset Port 0 0x82030 Port 1 0x84030 Serial ATA Host Controller SATAHC Registers Bits Field Type Description InitVal 4 0 eDevQueTAG RO EDMA Tag 0x0 This field indicates the tag of the last command used by the EDMA The EDMA updates this field with field lt cDeviceQueTag gt of the CRQB When anew command is written to the device or e When the tag is read from the device after a service command TCQ or When the tag is read from the device in DMA Setup SU FIS NCQ 5 eDevDir RO Device Direction 0x0 The EDMA updates this field with field lt cDIR gt of the CRQB when a new command is written to the device or when the tag is rea
262. e host may write to the Vendor Unique Register Table 353 p 261 When this bit is cleared the VendorUgDn field and the lt VendorUgErr gt field in the Serial ATA Interface Status Register Table 352 p 260 are also cleared Before setting this bit the Host must verify e No pending commands are in progress e The EDMA is disabled field lt eEnEDMAs is cleared 9 VendorUgSend RW Send vendor Unique FIS 0x0 This bit is set to 1 by the host SW to indicate that the next DWORD written to the Vendor Unique Register is the last DWORD in the payload Field lt VendorUqDns gt is set when the transmission is completed field lt VendorUgErr gt of that same register is also set if the transmission ends with an error When the host SW writes to the Vendor Unique Register with this bit set to 1 the Serial ATA transport layer closes the FIS and clears this bit 15 10 Reserved RES Reserved 0x0 16 eDMAActivate RW DMA Activate 0x0 This bit has an effect only if the Serial ATA port is in Target mode operation i e the lt ComChannel gt field in the Serial ATA Interface Configuration Register Table 349 p 255 is set When this bit is set the transport layer sends multiple data FISs as long as the DMA is active to complete the data transaction associated with the command When the port functions as a target in Target mode operation this bit is set by the target host SW to activate read data transactions from the targe
263. e master generates a stop condition after driving an acknowledge bit the TWSI slave interface returns back to idle state 11 3 2 Slave Write Access Upon detecting a new address driven on the bus with write bit indication the TWSI slave interface compares the address against the address programmed in the Slave Address register and if it matches responds with acknowledge It also sets an Interrupt flag and sets status code to 0x60 0x70 in case of general call address if general call is enabled Following each write byte received the TWSI slave interface responds with acknowledge sets an Interrupt flag and sets status code to 0x80 0x90 in case of general call access The Marvell processor core then reads the received data from Data register and clears Interrupt flag to allow transfer to continue Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 44 88F5182 marveL Open Source Community Programmer s User Guide If a stop condition or a start condition of a new access is detected after driving the acknowledge bit an Interrupt flag is set and a status code of 0xAO is registered Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 45 Document Classification Proprietary June 25 2007 Preliminary UART Interface Functional Description Section 12 UART Interface 12 1 Functional Description The 88F5182 supports two U
264. e mode or in response to a data received read data in master mod write data in slave mode For a master to signal a TWSI target a read of last data the Marvell processor core must clear this bit generating no acknowledge bit on the bus For the slave to respond this bit must always be set back to 1 3 IFlg RW Interrupt Flag 0x0 If any of the status codes other than OxF8 are set the TWSI hardware sets the bit to 1 If set to 1 and TWSI interrupts are enabled through bit 7 an interrupt is asserted Cleared by a Marvell processor core write of 0 4 Stop RW Stop 0x0 When set to 1 the TWSI master initiates a stop condition on the bus The bit is set only It is cleared by TWSI hardware after a stop condition is driven on the bus 5 Start RW Start 0x0 When set to 1 the TWSI master initiates a start condition on the bus when the bus is free or a repeated start condition if the master already drives the bus The bit is set only It is cleared by TWSI hardware after a start condition is driven on the bus 6 TWSIEn RW TWSI Enable 0x0 If set to 1 the TWSI slave responds to calls to its slave address and to general calls if enabled If set to 0 TW SDA and TW SCK inputs are ignored The TWSI slave does not respond to any address on the bus Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 336 88F5182 marveL Open Source Com
265. e not updated If the non data FIS length is shorter than 7 DWORDS only the relevant reg isters are updated with the content of the FIS If the non data FIS length is longer than 7 DWORDS FIS DWO Register through FIS DW6 Register are updated with the content of the FIS The rest of FIS is dropped When at least one bit in this field is set and the corresponding bit in the FISWait4HostRdyEn field in the FIS Configuration Register Table 354 p 262 is enabled set to 1 the transport layer prevents assertion of the primitive H RDY and the reception of the next FIS 23 16 Reserved RWO Reserved 0x0 24 FISTxDone RWO This bit is set to 1 when the FIS transmission is done either aborted or 0x0 completed with H OK or R ERR 0 Frame transmission continues 1 Frame transmission completed either with H ERR or R OK or frame transmission aborted 25 FISTxErr RWO This bit is valid when bit 24 FISTxDone is set to 1 0x0 This bit is set to 1 when the FIS transmission is done bit 24 lt FISTxDone gt is set to 1 and one of the following occurs e FIS transmission is aborted due to collision with the received FIS e FlS transmission is completed with H ERR 0 Frame transmission was completed successful with H OK 1 Frame transmission was not completed successful Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 264 e 88F5182 E marveL Open
266. e state of the lt PErrEn gt bit in this Table 144 PCI Express Class Code and Revision ID Register Offset 0x40008 Configuration 0x8 Bits Field Type Description InitVal 7 0 RevID RO 88F5182 Revision Number 0x0 15 8 ProglF RO Register Level Programming Interface 0x0 23 16 SubClass RO 88F5182 Sub class Other Memory Controller 0x80 31 24 BaseClass RO 88F5182 Base Class Memory Controller 0x05 Table 145 PCI Express BIST Header Type and Cache Line Size Register Offset 0x4000C Configuration OxC Other BIST failed Bits Field Type Description InitVal 7 0 CacheLine RW 88F5182 Cache Line Size 0x00 15 8 Reserved RSVD Does not apply to PCI Express 0x0 This bit is hardwired to 0 23 16 HeadType RO 88F5182 Configuration Header Type 0x0 Type 0 single function configuration header 27 24 BISTComp RO BIST Completion Code 0x0 0x0 BIST passed 29 28 Reserved RSVD Reserved 0x0 30 BISTAct RO BIST Activate bit 0x0 BIST is not supported Doc No MV S400130 00 Rev 0 5 Page 149 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary PCI Express Interface Registers Table 145 PCI Express BIST Header Type and Cache Line Size Register Continued Offset 0x4000C Configuration 0xC Bits Field Type Description InitVal 31 BISTCap RO BIST Capable Bit 0x0 BIST is not supported T
267. e taken If the Tx DMA is enabled before it must be disabled through its command registers The CPU must verify that it is disabled by polling the TXQ Command register then the CPU must poll each port s Port Status register to verify that There is no transmission in progress TxInProg bit 7 is 0 ts Tx FIFO is empty lt TcFIFOEmp gt bit 10 is 1 Read the Port Serial Control register Disable the Serial port by writing a 0 to bit 0 lt PortEn gt of the Port Serial Control register Set the desired bits in the Port Serial Control register Enable the Serial port by writing a 1 to bit 0 lt PortEn gt of the Port Serial Control register Re enable the Tx DMAs according to their initialization sequence as necessary Table 393 Port Serial Control PSC Offset 0x7243C Bits Field Type Description InitVal PortEn RW Serial Port Enable 0x0 No frames will be received of transmitted while serial port is disabled 0 Serial Port is disabled 1 Serial Port is enabled NOTE Disabling the port should not happen during Tx DMA operation See guidelines above this table Link Duplex 802 3x Flow Control and Backpressure Force_Link_ RW Force Link status on port to Link UP state Pass 0x0 0 Do NOT Force Link Pass 1 Force Link pass AN_Duplex RW Enable Auto Negotiation for duplex mode 0x0 0 Enable 1 Disable NOTE Half Duplex mode is not supported in 1000 Mbps mode AN_F
268. e with initial value indicated RWO Read and Write O RW1 Read and Write 1 RWC Read Write Clear on Read All bits are readable and writable After reset or after the register is read the register field is cleared to zero SC Self Clear Writing a one to this register causes the desired function to be immediately executed then the register field is cleared to zero when the function is complete WO Write only Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 88 MSE sss MARvELL e Open Source Community Programmer s User Guide A 3 Internal Registers Address Map 88F5182 Internal registers reside in 1 MByte address space distributed into 64 KByte segments among the various 88F5182 modules as indicated in Table 32 Table 32 88F5182 Internal Registers Address Map Unit ID Unit Name Address Space Size Address Range Address Range in Hexadecimal 0 DDR registers 64 KByte 0 64K 0x00000 0x0FFFF 1 Device Bus registers 64 KByte 64K 128K 0x10000 0x1FFFF 2 Local to System Bridge 64 KByte 128K 192K 0x20000 0x2FFFF registers 3 PCI register 64 KByte 192K 256K 0x30000 0x3FFFF 4 PCI Express registers 64 KByte 256K 320K 0x40000 0x4FFFF 5 USB registers Port 0 64 KByte 320K 384K 0x50000 0x5FFFF 6 IDMA registers and 64 KByte 384K 448K 0x60000 0x6FFFF XOR registers 7 Gigabit Ethernet registers 64 KByte 448K 512K 0x70000 0x7FFFF
269. ead from MIB counter resets the value to 0 Offset Width Counter Name Description 0x48 32 MulticastFramesSent The number of good frames sent that had a Multicast destination MAC address NOTE This does NOT include 802 3 Flow Control messages as they are considered MAC Control messages NOR does it include packets with an Tx Error Event This counter counts frames of all sizes including frames smaller than the Minimal Frame Size and frames larger than the MRU 0x4C 32 BroadcastFramesSent The number of good frames sent that had a Broadcast destination MAC address This does not include 802 3 Flow Control frames NOR packets dropped due to excessive collision NOR packets with an Tx Error Event NOTE This counter counts frames of all sizes including frames smaller than the Minimal Frame Size and frames larger than the MRU 0x50 32 UnrecogMACControl The number of received MAC Control frames that have an opcode Received different than 00 01 0x58 32 GoodFCReceived The number of good flow control messages received 0x5C 32 BadFCReceived The number of bad flow control frames received 0x60 32 Undersize The number of undersize packets received 0x64 32 Fragments The number of fragments received 0x68 32 Oversize The number of oversize packets received Ox6C 32 Jabber The number of jabber packets received 0x70 32 MACRcvError The number of Rx Error events seen by the receive side of the MAC 0x74 32 BadCRC The number CRC error events 0x78 32
270. ed 0x0 Must be 0x0 28 SSBint RW PCI to CPU Ordering enable internal registers access 0x0 If set to 1 PCI to CPU ordering is maintained by hardware upon any PCI read access from any of the 88F5182 internal registers 31 29 Reserved RW Reserved 0x0 Must be 0x3 Table 216 PCI Mode Offset 0x30D00 Bits Field Type Description InitVal 3 0 Reserved RES Reserved 0x0 5 4 PciMode RW PCI Interface Mode of Operation Sampled at 0x0 Conventional PCI reset 0x1 Reserved 0x2 Reserved 0x3 Reserved NOTE Must not be changed after reset 7 6 Reserved RES Reserved 0x0 8 ExpRom RW Expansion ROM Active 0x0 When set to 1 the expansion ROM BAR is supported Read Only from PCI Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 184 88F5182 marveL Open Source Community Programmer s User Guide Table 216 PCI Mode Continued Offset 0x30D00 Bits Field Type Description InitVal 30 9 Reserved RES Reserved 0x0 31 PRst RO PCI Interface Reset Indication 0x1 Set to 0 as long as the PCI_RSTn pin is asserted Read Only Table 217 PCI Retry Offset 0x30C04 Bits Field Type Description InitVal 15 0 Reserved RES Reserved 0x0 23 16 RetryCtr RW Retry Counter 0x0 Specifies the number of times the 88F5182 retries a transaction before it quits Applies to th
271. ed RES Reserved 0x0 16 TimeoutEn RW Crossbar Arbiter Timer Enable Ox1 0 Enable 1 Disable 23 17 Reserved RES Reserved 0x0 25 24 CoalDis RW Coalescing Disable 0x0 When a bit in field lt CoalDis gt is set to 1 the completing indication of the corre sponding port is ignored in the following coalescing counters 1 Table 297 SATAHC Interrupt Coalescing Threshold Register on page 219 2 Table 298 SATAHC Interrupt Time Threshold Register on page 220 CoalDis 0 Bit 24 0 Coalescing enabled for port 0 1 Coalescing disable for port 0 CoalDis 1 bit 25 0 Coalescing enabled for port 1 1 Coalescing disable for port 1 31 26 Reserved RES Reserved 0x0 Table 295 SATAHC Request Queue Out Pointer Register Offset 0x80004 Bits Field Type Description InitVal 6 0 eRQQOPO RO EDMA Request Queue Out Pointer Port 0 0x0 This field reflects the value of bits 11 5 in the EDMA Request Queue Out Pointer Register see Table 317 on page 234 located in port 0 7 Reserved RES Reserved 0x0 14 8 eRQQOP1 RO EDMA Request Queue Out Pointer Port 1 0x0 This field reflects the value of bits 11 5 in the EDMA Request Queue Out Pointer Register located in port 1 15 Reserved RES Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 218 MARVELL 88F5182 Open Source Community Pro
272. ed out on the data pointed by SA 6 Source Address 6 word of the descriptor NOTE Relevant only on XOR operation mode disregarded in all other operation modes 7 Src7Cmd Specifies the type of operation to be carried out on the data pointed by SA 7 Source Address 7 word of the descriptor NOTE Relevant only on XOR operation mode Disregard in all other operation modes 29 8 Reserved Reserved 30 CRCLast Indicated last descriptor in a CRC 32 calculation chain 0 Not last descriptor in a CRC calculation chain 1 Last descriptor in a CRC calculation chain When closing the descriptor the XOR engine writes the CRC result to its CRC 32 Result word The next descriptor in the descriptor chain initiates a new CRC calculation If the source block is represented by one descriptor only it should be marked as last NOTE Relevant only in CRC operation mode 31 EODIntEn End Of Descriptor Interrupt Enable Specifies if the EOD interrupt is asserted upon closure of that descriptor 1 EOD Enabled 0 EOD Disabled Table 28 Descriptor Next Descriptor Address Word Bits Field Description 31 0 NDA Next descriptor address pointer XOR Mode NDA must be 64 byte aligned bits 5 0 must be 0x0 CRC DMA Mode NDA must be 32 byte aligned bits 4 0 must be 0x0 NDA field of the last descriptor of a descriptor chain must be NULL Table 29 Descriptor Byte Count Word Bit Field Description 23 0 ByteCoun
273. eeeeenee nennen nnn 267 REINER Vi eh ee 270 Offset 0x72000 Table 366 SML iini tie ee e e ah ahhh dee etteqi pe ite e nete ete diit edad o de hiis 270 Offset 0x72004 Table 367 Ethernet Unit Default Address EUIDA nennen trenreennren nennt 271 Offset 0x72008 Table 368 Ethernet Unit Default ID EUDIDN rennen rnnretren rre tnr inrer trennen 271 Offset 0x7200C Table 369 Ethernet Unit Reserved EU eene enne retener retener nnne tenentes 271 Offset 0x72014 Table 370 Ethernet Unit Interrupt Cause EU 272 Offset 0x72080 Table 371 Ethernet Unit Interrupt Mask EUIM nennen nretrt rennen rrr eren rennes 273 Offset 0x72084 Table 372 Ethernet Unit Error Address EUEA esee eene eren enne rnnt nne teretes 273 Offset 0x72094 Table 373 Ethernet Unit Internal Address Error EUIAE 00 eee ee eee cece cee eeee rece tees cena tees ease seeesaaeseeesaeseaeseaeeeaeeaaes 273 Offset 0x72098 Table 374 Ethernet Unit Port Pads Calibration EUPDCH eee eee eee cence tee e eens tees tees sees sees seneseeesaeseaeseaeeeaeeeaes 273 Offset 0x720A0 Table 375 Ethernet Unit Control EUG erect ttr ite tette Lone ce rc te n tre ne pedea 274 Offset 0x720B0 Table 376 Base Address EE 275 Offset BAO 0x72200 BA1 0x72208 BA2 0x72210 BA3 0x72218 BA4 0x72220 BAD 0x72228 Table 377 Size S ge de HM te Ur DE UNI UR e Ar RN RUDI RR SEE ERAS ERAS ERRUD 275 Offset SRO 0x72204 SR1 0x7220C SR2 0x72214
274. egister corresponding to PCI Express PCI interrupt is used to generate an interrupt towards the host The host is connected to 88F5182 through the interface defined by bit lt EndPointIF gt in the CPU Configuration Register Table 55 p 99 The INTA interrupt or MSI is routed to host according to this bit value Y Notes e See Table 33 CPU Register Map on page 90 See Table 17 5 88F5182 Interrupt Controller Scheme on page 61 17 4 Doorbell Interrupt When 88F5182 functions as Endpoint a doorbell mechanism is provided to communicate between Marvell processor core and the external host The 88F5182 supports 32 bit doorbell interrupt register from host to Marvell CPU core See Table 72 Host to CPU Doorbell Register on page 107 and Table 73 Host to CPU Doorbell Mask Register on page 107 The 88F5182 supports 32 bit doorbell interrupt register from Marvell CPU core to host See Table 74 CPU to Host Doorbell Register on page 108 and Table 75 CPU to Host Doorbell Mask Register on page 108 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 60 MSE sss marveL Open Source Community Programmer s User Guide 17 5 88F5182 Interrupt Controller Scheme Figure 15 88F5182 Interrupt Controller Scheme UNIT O Interrupt Cause Reg Interrupt Mask Reg UNIT 1 Interrupt Cause
275. eiving a PCI Express 0x0 reset indication from the PCI Express Endpoint interface as configured in bit lt EndPointIF gt in the CPU Configuration Register see Table 55 on page 99 1 WDRstOutEn RW If set to 1 the 88F5182 asserts RSTOUTn upon watchdog timer expiration 0x0 See Table 71 CPU Watchdog Timer Register on page 107 2 SoftRstOutEn RW If set to 1 the 88F5182 asserts RSTOUTn upon SW reset 0x0 See Table 58 System Soft Reset Register on page 101 31 3 Reserved RO Reserved 0x0 Read only Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 100 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 58 System Soft Reset Register Offset 0x2010C Bits Field Type Description InitVal 0 SystemSoftRst RW When SW set this bit to 1 and bit lt SoftRstOutEn gt is set to 1 in the 0x0 RSTOUTn Mask Register the 88F5182 asserts the RSTOUTn pin 31 1 Reserved RSVD Reserved 0x0 Table 59 Local to System Bridge Interrupt Cause Register Offset 0x20110 NOTE A cause bit is set upon an error condition occurrence Writing a 0 value clears the bit Writing a 1 value has no affect Bits Field Type Description InitVal 0 CPUSelfint RWC This bit is set when bit lt Selflnt gt is set to 1 in CPU Control and Status Reg 0x0 ister 1 CPUTimerOIntR RWC CPU Timer 0 Interrupt eq 0x0 Th
276. eld Type Description InitVal 31 16 Base RW Base Address 0x1000 See the Window0 Base Register Table 307 Window2 Control Register Offset 0x80050 Offset 0x80060 Bits Field Type Description InitVal 0 WinEn RW Window2 Enable 0x1 See the Window0 Control Register Table 303 p 223 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 See the Window0 Control Register 15 8 Attr RW Target specific attributes depending on the target interface 0x0B See the Window0 Control Register 31 16 Size RW Window Size OxOFFF See the Window0 Control Register Table 308 Window Base Register Offset 0x80054 Bits Field Type Description InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x2000 See the Window0 Base Register Table 309 Window3 Control Register Bits Field Type Description InitVal 0 WinEn RW Windows Enable 0x1 See the Window0 Control Register Table 303 p 223 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 See the Window0 Control Register Doc No MV S400130 00 Rev 0 5 Page 225 Copyright O 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Serial ATA Host Controller SATAHC Registers Table 309 Window3 Control Register Con
277. en ree tren nenne 135 Offset 0x41824 Table 117 PCI Express Window0 Remap Hegtsier A 135 Offset 0x4182C Table 118 PCI Express Window1 Control Register rennen nennen nenne 136 Offset 0x41830 Table 119 PCI Express Window1 Base Register re nrtren rennen nenne 136 Offset 0x41834 Table 120 PCI Express Window1 Remap Register teen ren ritenere rennen 136 Offset 0x4183C Table 121 PCI Express Window Control Hegtsier A 137 Offset 0x41840 Table 122 PCI Express Window2 Base Register esssssssssssesseeeesennenneeneeneenren rennen enrrneren rennes 137 Offset 0x41844 Table 123 PCI Express Window2 Remap Hegtsier A 137 Offset 0x4184C Table 124 PCI Express Window3 Control Hegtsier A 138 Offset 0x41850 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 68 88F5182 marveL Open Source Community Programmer s User Guide Table 125 PCI Express Window3 Base Register rennen nennen 138 Offset 0x41854 Table 126 PCI Express Window3 Remap Register sss rennen nren nennen 138 Offset 0x4185C Table 127 PCI Express Window4 Control Register A 139 Offset 0x41860 Table 128 PCI Express Window4 Base Register rennen reet rennen 139 Offset 0x41864 Table 129 PCI Express Window4 Remap Register A 139 Offset 0x4186C Table 130 PCI Express Window5 Control Register A 140 Offset 0x41880 Table 131
278. en retener n nernnnenneen 211 Offset 0x14 Table 286 FCL P2P l O Base Address diet etd iret niti fanc RU bres ko Lat do ED pua Ro agn 211 Offset 0x20 Table 287 PCI Internal Registers I O Mapped Base Address 212 Offset 0x24 A 8 Serial ATA Host Controller SATAHC Registers cccesssseeeeeeeseeeeeeenseeeeeeeenees 213 Table 294 SATAHC Configuration Hegister AAA 218 Offset 0x80000 Table 295 SATAHC Request Queue Out Pointer Hegieter ENEE 218 Offset 0x80004 Table 296 SATAHC Response Queue In Pointer Heoleter enne 219 Offset 0x80008 Table 297 SATAHC Interrupt Coalescing Threshold Heiser 219 Offset 0x8000C Table 298 SATAHC Interrupt Time Threshold Register essent 220 Offset 0x80010 Table 299 SATAHC Interrupt Cause Register sssessssssssseseeeseeeeenne nennen tenter rentre eene tenen 220 Offset 0x80014 Table 300 Reserved Register c icessisccesssvsecnssensonvagceaaivsoesasieeees anes sasuveecasesacevangaidaaiceasetuvedslbaateviadasottassesistioancecneens 222 Offset 0x80018 Table 301 SATAHC Main Interrupt Cause Register ee cece eee eee eee eeeeeeee eens seas seas seeeseaeseaeseeesaeseeseaeeeaeseaeeeaees 222 Offset 0x80020 Table 302 SATAHC Main Interrupt Mask Register A 223 Offset 0x80024 Table 202 Window0 Control Register oarenien anaid aaa a aaa aa aaaea t aa iadaa di aai 223 Offset 0x80030 Table 304 Window0 Base Hegister cene r
279. eout 0x0 15 PCIErr RO PCI error 0x0 16 USBBr RO USB bridge Port 0 or 1 error 0x0 17 USBCnto RO USB Port 0 controller interrupt 0x0 18 GbERx RO GbE receive interrupt 0x0 19 GbETx RO GbE transmit interrupt 0x0 20 GbEMisc RO GbE miscellaneous interrupt 0x0 21 GbESum RO GbE summary 0x0 22 GbEErr RO GbE error 0x0 23 DMAErr RO DMA or XOR error 0x0 24 IDMAO RO IDMA ChannelO completion 0x0 25 IDMA1 RO IDMA Channel completion 0x0 26 IDMA2 RO IDMA Channel2 completion 0x0 27 IDMA3 RO IDMA Channel3 completion 0x0 28 SecurityInterrup RO Security accelerator interrupt indication t 0x0 29 Satalnterrupt RO Serial ATA interrupt indication 0x0 30 XORO RO XOR engine 0 completion interrupt indication 0x0 31 XOR1 RO XOR engine 1 completion interrupt indication 0x0 Doc No MV S400130 00 Rev 0 5 Page 103 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers Table 62 Main IRQ Interrupt Mask Register Offset 0x20204 Bits Field Type Description InitVal 31 0 Mask RW Mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of Marvell processo core IRQ interrupt line It does not affect the setting of bits in the Cause register Table 63 Main FIQ Interrupt Mask Register Offset 0x20208 Bits Field Type Description InitVal 31 0 Mask RW M
280. eption of interrupt emulation messages Bits Field Type Description InitVal 0 Reserved RSVD Reserved 0x0 1 MDis RWOC Attempt to generate a PCI transaction while the master is disabled 0x0 2 Reserved RWOC Reserved 0x0 3 ErrwrToReg RWOC Erroneous write attempt to PCI Express internal register 0x0 Set when an erroneous write request to PCI Express internal register is received either from the PCI Express EP set or from the internal bus bit 64 set 4 HitDfltWinErr RWOC Hit Default Window Error 0x0 7 5 Reserved RSVD Reserved 0x0 8 CorErrDet RWOC Correctable Error Detected 0x0 Indicates status of correctable errors detected by 88F5182 9 NFErrDet RWOC Non Fatal Error Detected 0x0 Indicates status of Non Fatal errors detected by 88F5182 Doc No MV S400130 00 Rev 0 5 Page 131 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 113 PCI Express Interrupt Cause Continued Offset 0x41900 NOTE AN bits except bits 27 24 are Read Write Clear only A cause bit sets upon an event occurrence A write of 0 clears the bit A write of 1 has no affect Bits 24 27 are set and cleared upon reception of interrupt emulation messages Bits Field Type Description InitVal 10 FErrDet RWOC Fatal Error Detected 0x0 Indicates status of Fatal errors detected by 88F51
281. er 24 Acc2NextExt RW Acc2Next Extension 0x1 The MSB of the Acc2Next parameter 25 ALE2WrExt RW ALE2Wr Extension 0x1 The MSB of the ALE2Wr parameter 26 WrLowExt RW WrLow Extension 0x1 The MSB of the WrLow parameter 27 WrHighExt RW WrHigh Extension 0x1 The MSB of the WrHigh parameter 29 28 BadrSkew RW Cycles gap between BAdr toggle to read data sample 0x0 This is useful when interfacing sync burst SRAM 0x0 No gap default setting 0x1 One cycle gap 0x2 Two cycle gaps 0x3 Reserved 31 30 Reserved RW Must be 0x2 Table 514 Device Bank1 Parameters Register Doc No MV S400130 00 Rev 0 5 Page 349 Offset 0x10460 Bits Field Type Description InitVal 31 0 Various RW These fields function as in Device Banko Ox8FCF FFFF Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Device Controller Registers Table 515 Device Bank2 Parameters Register Offset 0x10464 Bits Field Type Description InitVal 31 0 Various RW These fields function as in Device Banko Ox8FCF FFFF Table 516 Boot Device Parameters Register Offset 0x1046C Bits Field Type Description InitVal 31 0 Various RW These fields function as in Device Banko Ox8F F FFFF 1 The boot device width bits 21 20 are sampled at reset see the Pins Sample Configuration in the 88F5182 88F5182 based Storage Networking Platforms Datas
282. er Block Registers Map on page 215 When EDMA is enabled the transport layer ignores the value of this bit and assume a value of 1 This bit must be cleared before the host issues any PIO commands 25 LinkRstEn RW 0x0 When this bit is set to 1 and when bit lt RST gt is set to 1 in the ATA status reg ister see Table 291 Shadow Register Block Registers Map on page 215 in the middle of data FIS reception the link layer responds with a SYNC primi tive to reception of data FIS When the transport layer receives SYNC in the back channel in response it sends the Control FIS with the lt SRST gt bit set to 1 When this bit is cleared to 0 and when bit lt RST gt is set to 1 in the ATA status register in a middle of data FIS reception the transport layer drops the data of the incoming FIS When the incoming data FIS completes it sends the Con trol FIS with the lt SRST gt bit set to 1 26 CmdRetxDs RW 0x0 When this bit is cleared to 0 and Register Host to Device FIS transmission was not completed successfully as indicated by the FISTxDone field and the lt FISTxErr gt field in the FIS Interrupt Cause Register Table 355 p 264 the transport layer retransmits the Register Host to Device FIS When this bit is set to 1 and Register Host to Device FIS transmission was not completed successfully as indicated by fields lt FISTxDone gt and lt FISTXErr gt the transport layer does not retransmit the Regi
283. er mii ebrii 27 Table 8 GROB DW5 ATA Command eieiei NEEN EES og eager obe ako oce dE 27 Table 9 CRQOBIDWO ATA Command ne RH raaraa ae a E reaa E e AE Aare MAR RRA IR P aas E EA ais 28 Table 10 CRQB DW7 ATA Commande 28 Table 11 ePRD Table Data Structure Map 29 Table 12 ePRD DWORD O0 cere dr ree core Hee RE Ye DECR e ee Are 29 Table 13 RR DINNER DE Aueren ee de t ete eet er at reu t pie up eet 30 Table 142 ePRD DWORD 2 eel et ee e e eet de e AC e 30 Tables PRD DWORBD S 5ziRnunnSdenuunenaltentties ee 30 Table 16 EDMA CRPB Data Structure Map 31 Table 17 CRPB ID e EE 31 Table 18 CRPB Response Flags Register nennen nenne nnnnen rnnt nnne 32 Table 19 CRPB Time Stamp Register ener neret enne trennen tenente 32 Table 20 Acronyms Abbreviations and Definitions ennemis 37 Table 21 Setting the Baud Rate Heite 42 Table 22 UART Pin Assignments e nente phe E e RETE UAM RENE RRR RM ERES 46 Table 23 Device Controller Pin Assignments nennen nennen nnne nennen nnne nnne 47 Table 24 IDMA Descriptor Definitions AAA 51 Table 25 Descriptor Status Word Definition ccccccceseeccecenceeeeneeeeeeneeeseaeeescceeenneeeseaeeessaeeeseaaeeseneessseeeeoes 55 Table 26 Descriptor CRC 32 Result Word Definition eesessssssssesseeeeeeeen enne 55 Table 27 Descriptor Command Word Detiniton eene nennen 55 Table 28 Descriptor Next Descriptor Address Word AAA 56 Table 29 Des
284. erface Control Register Port 0 0x82344 Port 1 0x84344 Table 350 p 256 Serial ATA Interface Test Control Register Port 0 0x82348 Port 1 0x84348 Table 351 p 258 Serial ATA Interface Status Register Port 0 0x8234C Port 1 0x8434C Table 352 p 259 Vendor Unique Register Port 0 0x8235C Port 1 0x8435C Table 353 p 261 FIS Configuration Register Port 0 0x82360 Port 1 0x84360 Table 354 p 262 FIS Interrupt Cause Register Port 0 0x82364 Port 1 0x84364 Table 355 p 263 FIS Interrupt Mask Register Port 0 0x82368 Port 1 0x84368 Table 356 p 265 FIS DWO Register Port 0 0x82370 Port 1 0x84370 Table 357 p 265 FIS DW1 Register Port 0 0x82374 Port 1 0x84374 Table 358 p 265 FIS DW2 Register Port 0 0x82378 Port 1 0x84378 Table 359 p 266 FIS DW3 Register Port 0 0x8237C Port 1 0x8437C Table 360 p 266 FIS DW4 Register Port 0 0x82380 Port 1 0x84380 Table 361 p 266 FIS DW5 Register Port 0 0x82384 Port 1 0x84384 Table 362 p 266 FIS DW6 Register Port 0 0x82388 Port 1 0x84388 Table 363 p 266 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 217 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers A 8 7 SATAHC Arbiter Registers Table 294 SATAHC Configuration Register Offset 0x80000 Bits Field Type Description InitVal 7 0 Timeout RW SATAHC interface Crossbar Arbiter Timeout Preset Value OxFF 15 8 Reserv
285. ersnenscessceessessaeesscessescenssessessoesczeneess 316 Offset OXODD78 Table 437 DES Data Out High Register c cccccesessccsscesssecesssscnssssenseseseessesseeosnesscesstecssesnecesscesesscestseeetsssonsansessess 316 Offset OX9ODD7C Table 438 DES Data Buffer Low Register nennen nenne nennen trennen tentent 316 Offset OXODD70 Table 439 DES Data Buffer High Register nne nnnm reete nnne 316 Offset OX9DD74 Table 440 DES Initial Value Low Register eese nennen mentre nnne rentre tenete 316 Offset OXODD40 Table 441 DES Initial Value High Register eesseesesseeeeeeeneeneeneennne nennen menn enne tette enne 317 Offset 0x9DD44 Table 442 DES KeyO0 Low Register re tinh err tte Eee RE nat neti ERR inne 317 Offset OXODD48 Table 443 DES Key0 High Register nitentem rre Ere tds eee ER En IIR YER ER ESAE Pene p uo Eee Ee dae Renan 317 Offset Ox9DD4C Table 444 DES Key1 Low Reglister irte een tren tele er de sees er ta aco ted irte ob ede ter Food ee dg 317 Offset OX9DD50 Table 445 DES Key1 High Register ien tinet tnim eiit cous ite theo ba inei te eo Raps tees oe aa Ee Ep ae EEN 317 Offset OX9DD54 Table dap DES Key2 Low Register eie e eret entr tatc eres EFE eU IS REIS FECE PLEX ENEE EERSTEN 318 Offset OX9DD60 Table 447 DES Key2 High Register isisiccc ciscsccesissecsecectusienescesusdecasdscescestveuedacnsseasbessansvocseccueadadoeesisideescenuses Poe
286. escriptors 64 KB Mode 16 MB Mode Remaind BC Byte Count Byte Count Source Address Source Address Destination Address Destination Address Next Descriptor Pointer Next Descriptor Pointer Table 24 IDMA Descriptor Definitions IDMA Descriptor Definition Byte Count Number of bytes of data to transfer The maximum number of bytes to which the IDMA controller can be configured transfer is 64 KB 1 16 bit register in 64 KB descriptor mode or 16 MB 1 24 bit register in the 16 MB descriptor mode This register decrements at the end of every burst of transmitted data from the source to the destination When the byte count register is 0 the IDMA transaction is finished or terminated Source Address Bits 31 0 of the IDMA source address According to the setting of the Channel Control register this register either increments or holds the same value Destination Address Bits 31 0 of the IDMA destination address According to the setting of the Channel Control register this register either increments or holds the same value Pointer to the Next Bits 31 0 of the IDMA Next Descriptor address for chained operation Descriptor The descriptor must be 16 sequential bytes located at 16 bytes aligned address bits 3 0 are 0 NOTE This descriptor is used only used when the channel is configured to Chained mode Doc No MV S400130
287. eserved 7 TM RW Test Mode 0x0 0x0 Normal operation 0x1 Test mode 8 DLL RW Reset DLL 0x0 0x0 Normal operation 0x1 Reset DLL 11 9 WR RW For DDR2 SDRAM Write recovery for auto precharge DDR2 NOTE Auto precharge is not supported 0x2 For DDR1 SDRAM Reserved must be set to 0x0 DDR1 0x0 12 PD RW Active power down exit time 0x0 0 Fast exit 1 Slow exit Must be 0x0 NOTE Active power down is not supported for DDR2 SDRAM 13 Reserved RW Reserved 0x0 31 14 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 119 Document Classification Proprietary June 25 2007 Preliminary Table 96 DDR SDRAM Controller Registers Extended DDR SDRAM Mode Register Offset 0x01420 NOTE If configured to DDR1 SDRAM bits 13 2 are not relevant and must be set to 0x0 Bits Field Type Description InitVal 0 DLL RW DDR SDRAM DLL Enable 0x0 0 Enable 1 Disable 1 DS RW DDR SDRAM Drive Strength 0x0 0 Normal 1 Reduced 2 Rtt 0 RW DDR2 SDRAM Rtt 1 0 is ODT Control DDR2 0x0 ODT disable Ox1 0x1 75 ohm termination DDR1 0x2 150 ohm termination 0x0 0x3 Reserved Refer to the Design Considerations for this product DDR1 SDRAM Reserved must be set to 0x0 5 3 AL RW DDR2 SDRAM Additive Latency DDR2 Must be 0x0 0x0 NOTE Additive Latency is not supported DDR1 DDR1 SDRAM Reserved must be set to 0x0 0x0 6 Rtt 1 RW DDR2 SDRAM See lt Rit 0 gt
288. eshold for Urgent is 16 240 entries 128 1920 byte 31 5 Reserved RO Reserved 0x0 Table 403 Port Tx FIFO Urgent Threshold PTFUT Offset 0x72474 Bits Field Type Description InitVal 3 0 Reserved RW Must be 0 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 294 e 88F5182 marveL Open Source Community Programmer s User Guide Table 403 Port Tx FIFO Urgent Threshold PTFUT Continued Offset 0x72474 Bits Field Type Description InitVal 17 4 IPGIntTx RW Tx frame IPG between interrupt counter and enable 0x0 This field provides a way to force a delay from the last Port Interrupt Cause Extend ICE TxBuffer interrupt Table 399 on page 292 from any of the queues to the next TxBuffer interrupt from any of the queues The ICE bits still reflect the new interrupt but this masking is reflected by potentially not propagating to the chip main interrupt cause register This provides a way for interrupt coalescing on receive packet events The time is calculated in multiples of 64 clock cycles Valid values are 0 no delay between packets to CPU the counter is effec tively disabled through Ox3FFF 1 048 544 clock cycles 31 18 Reserved RO Read Only 0x0 Table 404 Port Rx Minimal Frame Size PMFS Offset 0x7247C Bits Field Type Desc
289. ess Capability Register Continued Offset 0x40060 Configuration 0x60 Bits Field Type Description InitVal 29 25 IntMsgNum RO Interrupt Message Number 0x0 This bit is hardwired to 0 31 30 Reserved RSVD Reserved 0x0 Table 163 PCI Express Device Capabilities Register Offset 0x40064 Configuration 0x64 Bits Field Type Description InitVal 2 0 MaxPldSizeSup RO Maximum Payload Size Supported 0x0 128B MPS support 5 3 Reserved RO Reserved 0x0 These bits are hardwired to 0 8 6 EPLOsAccLat RO Endpoint LOs Acceptable Latency 0x2 This field indicates the amount of latency that can be absorbed by the 88F5182 due to the transition from LOs to LO 0 Under64ns Less than 64 ns 1 64to128ns 64 ns 128 ns 2 128to256ns 128 ns 256 ns 3 256to512ns 256 ns 512 ns 4 512nstotus 512 ns 1 us 5 1to2us 1 us 2 us 6 2to4us 2 us 4 us 7 Above4us more than 4 us 11 9 EPL1AccLat RO Endpoint L1 Acceptable Latency 0x0 This field indicates the amount of latency that can be absorbed by the 88F5182 due to the transition from L1 to LO The current value specifies less than 1 us 12 AttButPrs RO Attention Button Present 0x0 0x0 Not Implemented Attention button is not implemented on the card module 0x1 Implemented Attention button is implemented on the card module 13 AttlndPrs RO Attention Indicator Present 0x0 0 Not Implemented Attention indicat
290. etraite renti tecti entbi tne slice dones edd oed Ee ENEE ENNEN ENEE 224 Offset 0x80034 Table 305 Window Control Reglster enceinte tice kie Iota o ELE R o EE RR E EU EA PR e FEE SE xa cha REX Ra SERGE en 224 Offset 0x80040 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 75 Document Classification Proprietary June 25 2007 Preliminary Table 306 Table 307 Table 308 Table 309 Table 310 Table 311 Table 312 Table 313 Table 314 Table 315 Table 316 Table 317 Table 318 Table 319 Table 320 Table 321 Table 322 Table 323 Table 324 Table 325 Table 326 Table 327 Table 328 Table 329 List of Registers Window Base Register E telis 224 Offset 0x80044 Window Control F egister co AER acts ARRA ECRIRE EUER NER ERO CE s BURN ERES dE AER 225 Offset 0x80050 Windowe Base Register E Se EES 225 Offset 0x80054 Windows Control e EE 225 Offset 0x80060 Windows Base Register eese nennen nennen tnnt enne treten 226 Offset 0x80064 EDMA Configuration Register ek ENEE 226 Offset Port 0 0x82000 Port 1 0x84000 SR Nid EE 230 Offset Port 0 0x82004 Port 1 0x84004 EDMA Interrupt Error Cause Heiser 230 Offset Port 0 0x82008 Port 1 0x84008 EDMA Interrupt Error Mask Heiser 233 Offset Port 0 0x8200C Port 1 0x8400C EDMA Request Queue Base Address High Register 233 Offset Port 0
291. evice on the PCI Express port acts as a loopback master and a loopback indication is received 27 PexSlvDis RO Slave Disable Scrambling Indication Scrmb 0x0 This field sets when the opposite device on the PCI Express port acts as a disable scrambling master and a scrambling disabled indication is received 31 28 Reserved RSVD Reserved 0x0 Table 138 PCI Express Completion Timeout Register Offset 0x41A10 Bits Field Type Description InitVal 15 0 ConfCmpToThrshld RW Completion Timeout Threshold 0x2710 This field controls the size of the completion timeout interval The NP request is cleared from MCT within 0 100 of the timeout value NOTE Timescale 256 symbol time 1 us Initial Value 0x2710 represents a 10 ms value 10 000 decimal 0x0 Disabled No timeout mechanism on N P TLPs Minimum Value 40 40 us Maximum Value 25K 25 ms 31 16 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 144 88F5182 marveL Open Source Community Programmer s User Guide Table 139 PCI Express Flow Control Register Offset 0x41A20 Bits Field Type Description InitVal 7 0 ConfPhlnitFc RW Posted Headers Flow Control Credit Initial Value 0x0 15 8 ConfNphinitFe RW Non Posted Headers Flow Control Credit Initial Value 0x8 23 16 ConfChlnitFc RW Comp
292. f Ox1F i e it waits for the EDMA to acknowledge reception of the current FIS before enabling the link layer to response with H RDY for the next FIS 0 Do not wait for host ready 1 Wait for host ready The function of each bit in this field is FISWait4RdyEn 0 Register Device to Host FIS lt FISWait4RdyEn gt 1 SDB FIS is received with lt N gt bit cleared to 0 lt FIlSWait4RdyEn gt 2 DMA Activate FIS lt FlSWait4RdyEn gt 3 DMA Setup EIS FISWait4RdyEn 4 Data FIS first DW FISWait4RdyEn 5 Data FIS entire FIS FISWait4RgyEn 7 6 Reserved This field identifies whether the transport layer waits for the upper layer host to acknowledge reception of the current FIS before enabling the link layer to response with DH RDY for the next FIS 0 Do not wait for host ready 1 Wait for host ready The function of each bit in this field is FISWait4HostRdyEn 0 Register Device to Host FIS with ERR or lt DF gt bit set to 1 FISWait4HostRdyEn 1 SDB FIS is received with lt N gt bit set to 1 FISWait4HostRdyEn 2 SDB FIS is received with ERR bit set to 1 FISWait4HostRdyEn 3 BIST activate FIS FISWait4HostRdyEn 4 PIO Setup FIS FISWait4HostRdyEn 5 Data FIS with Link error FISWait4HostRdyEn 6 Unrecognized FIS type FISWait4HostRdyEn 7 Any FIS 16 FISDMAActive SyncResp RW 0x0 This bit identifies whether the transport layer responses with a sin
293. fetching is enabled 15 4 Reserved RSVD Reserved 0x0 31 16 Base Reserved RSVD Base address 0x0000 Defined according to Table 108 PCI Express BAR1 Control Register Indi cates a 64 KByte up to 4 GByte address space Corresponds to address bits 31 16 Table 149 PCI Express BAR1 High Register Offset 0x4001C Configuration 0x1C Bits Field Type Description InitVal 31 0 Base RW Base address 0x0 Corresponds to address bits 63 32 Table 150 PCI Express BAR2 Register Offset 0x40020 Configuration 0x20 Bits Field Type Description InitVal 0 Space RO Memory Space Indicator 0x0 2 1 Type RO BAR Type 0x2 BAR can be located in 64 bit memory address space 3 Prefetch RO Prefetch Enable 0x1 Indicates that pre fetching is enabled 15 4 Reserved RSVD Reserved 0x0 31 16 Base Reserved RSVD Base address OxF000 Defined according to Table 109 PCI Express BAR2 Control Register Indi cates 64 KByte up to 4 GByte address space Corresponds to address bits 31 16 Doc No MV S400130 00 Rev 0 5 Page 151 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 151 PCI Express BAR2 High Register Offset 0x40024 Configuration 0x24 Type Description InitVal 31 0 Base RW Base address 0x0 Corresponds to address bits 63 32 Table 152 PCI Express
294. ge Generation Enable 0x0 0 Disabled 1 Enabled NOTE Sticky bit not initialized by hot reset 12 9 PMDataSel RW Data Select 0x0 This 4 bit field is used to select which data is to be reported through the lt PMDataScale gt and lt PMData gt fields of this register 14 18 PMDataScale RO Data Scale 0x0 Indicated the scaling factor to be used when interpreting the value of the lt PMDatas field of this register The read value depends on the setting of the lt PMDataSels field of this register 15 PMEStat RW PME Status 0x0 Write 1 to clear NOTE Sticky bit not initialized by hot reset 23 16 Reserved RSVD Does not apply to PCI Express 0x0 This field must be hardwired to 0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 154 88F5182 marveL Open Source Community Programmer s User Guide Table 157 PCI Express Power Management Control and Status Register Continued Offset 0x40044 Configuration 0x44 Bits Field Type Description InitVal 31 24 PMData RO State Data 0x0 This field is used to report the state dependent data requested by the lt PMDataSel gt field of this register The value of this field is scaled by the value reported by the lt PMDataScale gt field of this register Table 158 PCI Express MSI Message Control Register Offset 0x40050 Configuration 0x50
295. gle SYNC primitive after the DMA activates FIS reception 0 Normal response 1 Response with single SYNC primitive Must be set to 1 when bit eEDMAFBS field in the EDMA Configuration Register Table 311 p 227 is set to 1 17 FlSUnrecType Cont RW 0x0 When this bit is set the transport layer state machine ignores incoming FIS with unrecognized FIS type 0 When an unrecognized FIS type is received the transport layer goes into error state and asserts a protocol error 1 When an unrecognized FIS type is received the transport layer does not go into error state and does not assert a protocol error 31 18 Reserved RES 0x0 Reserved Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 262 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 355 FIS Interrupt Cause Register Offset Port 0 0x82364 Port 1 0x84364 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Name Type Description InitVal 7 0 FISWait4Rdy RWO This field indicates the reception of the following FISs 0x0 FISWait4Rdy 0 Register Device to Host FIS lt FlSWait4Rdy gt 1 SDB FIS is received with lt N gt bit cleared to 0 lt FlSWait4Rdy gt 2 DMA Activate FIS lt FlSWait4Rdy gt
296. grammer s User Guide Table 295 SATAHC Request Queue Out Pointer Register Continued Offset 0x80004 Bits Field Type Description InitVal 31 16 Reserved RES Reserved 0x0 Table 296 SATAHC Response Queue In Pointer Register Offset 0x80008 Bits Field Type Description InitVal 6 0 eRPQIPO RO EDMA Response Queue In Pointer Register Port 0 0x0 This field reflects the value of bits 9 3 in the EDMA Response Queue In Pointer Register see Table 319 on page 234 located in port 0 7 Reserved RES Reserved 0x0 14 8 eRPQIP1 RO EDMA Response Queue In Pointer Register Port 1 0x0 This field reflects the value of bits 9 3 in the EDMA Response Queue In Pointer Register located in port 1 15 Reserved RES Reserved 0x0 31 16 Reserved RES Reserved 0x0 Table 297 SATAHC Interrupt Coalescing Threshold Register Offset 0x8000C Bits Field Type InitVal Description 7 0 SAICOALT RW 0x0 SATA Interrupt Coalescing Threshold This field provides a way to minimize the number of interrupts to off load the CPU It defines the number of SaCrpbXDone indications before asserting the lt SalntCoal gt field in the SATAHC Interrupt Cause Register Table 299 p 221 Once the accumulated number of SaCrpbXDone indications provided by both SATAHC ports reaches the SAICOALT value lt SalntCoal gt interrupt is asserted When SalntCoal is negated or when SATAHC I
297. has completed Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 259 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 352 Serial ATA Interface Status Register Continued Offset Port 0 0x8234C Port 1 0x8434C Copyright 2007 Marvell June 25 2007 Preliminary Bits Field Type Description InitVal 13 VendorUgErr RO Vendor Unique FIS Transmission Error 0x0 This bit indicates if the Vendor Unique FIS transmission has completed suc cessfully This bit is valid when field lt VendorUqDns gt of this register is set 0 Vendor Unique FIS transmission has completed successfully 1 Vendor Unique FIS transmission has completed with error 14 MBistRdy RO Memory BIST Ready 0x1 This bit indicates when the memory BIST test is completed 0 Memory BIST test is not completed 1 Memory BIST test is completed 15 MBistFail RO Memory BIST Fail 0x0 This bit indicates if the memory BIST test passed It is valid when field lt MBistRdy gt of this register is set 0 Pass 1 Fail 16 AbortCommand RO Abort Command 0x0 This bit indicates if the transport has aborted a command as a response to collision with incoming FIS 0 Command was not aborted 1 Command was aborted NOTE This bit is cleared when the ClearStatus field in the Serial ATA Interface Control Register Table 350 p 258 17 LBPass RO
298. heet and the initial value for bits 23 22 is 11 Table 517 NAND Flash Control Register Offset 0x104E8 Bits Field Type Description InitVal 0 NFBoot RW Defines if DEV_BootCEn is connected to NAND Flash SAR 0 Not connected to NAND Flash 1 Connected to NAND Flash Sample at reset 1 NFActCEnBoot RW If both lt NFBoot gt and lt NFActCEnBoot gt bits are set to 1 DEV_BootCEn is SAR forced to 0 This bit is used for CE care NAND Flash Sample at reset 2 NFO RW Defines if CEn 0 is connected to NAND Flash 0x0 0 Not connected to NAND Flash 1 Connected to NAND Flash 3 NFActCEnO RW If both lt NFO gt and lt NFActCEn0 gt bits are set to 1 DEV CEn 0 is forced to 0x0 0 This bit is used for CE care NAND Flash 0 Regardless of lt NFO gt value DEV CEn 0 is not forced to 0 1 If lt NFO gt is set to 1 DEV CEn 0 is forced to 0 4 NF1 RW See lt NFO gt description 0x0 5 NFActCEn1 RW See lt NFActCEn0 gt description 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 350 MARVELL e 88F5182 E Open Source Community Programmer s User Guide Table 517 NAND Flash Control Register Offset 0x104E8 Bits Field Type Description InitVal 6 NF2 RW See lt NFO gt description 0x0 7 NFActCEn2 RW See lt NFActCEn0 gt description 0x0 8 NFISD RW NA
299. hen FIS transmission is aborted due to collision with Rx traffic 30 26 LinkDataTxErr RWO Link Data Transmit Error 0x0 This field indicates when a data FIS is transmitted with errors Bit 0 of this field i e bit 26 of this register is set to 1 when a SATA CRC error occurs Bit 1 of this field is set to 1 when an internal FIFO error occurs Bit 2 of this field is set to 1 when the Link Layer is reset to Idle state by the reception of SYNC primitives from the device Bit 3 of this field is set to 1 when the Link Layer accepts a DMAT primitive from the device Bit 4 of this field is set to 1 to indicate when FIS transmission is aborted due to collision with Rx traffic 31 TransProtErr RWO Transport Protocol Error 0x0 This bit is set when a control FIS is received with a non transient transport protocol error This bit is set when a Link error indication is set during reception of a DMA PIO data frame or control frame e when the Link Layer is reset to Idle state by the reception of SYNC primitives from the device During control frame reception bit 15 in this register is also set to 1 During data frame reception bit 19 in this register is also set to 1 Control frame is too short or too long ncorrect FIS type e Illegal transfer count on a PIO transaction Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprieta
300. his bit must be set to 0 Table 146 PCI Express BARO Internal Register Offset 0x40010 Configuration 0x10 Bits Field Type Description InitVal 0 Space RO Memory Space Indicator 0x0 2 1 Type RO BAR Type 0x2 BAR can be located in 64 bit memory address space 3 Prefetch RO Prefetch Enable 0x1 Indicates that pre fetching is enabled 19 4 Reserved RSVD Reserved 0x0 31 20 Base RW Internal register memory Base Address 0xD00 Indicates a 1 MByte address space Corresponds to address bits 31 20 Table 147 PCI Express BARO Internal High Register Offset 0x40014 Configuration 0x14 Bits Field Type Description InitVal 31 0 Base RW Base address 0x0 Corresponds to address bits 63 32 Table 148 PCI Express BAR1 Register Offset 0x40018 Configuration 0x18 Bits Field Type Description InitVal 0 Space RO Memory Space Indicator 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary MARVELL 88F5182 Open Source Community Programmer s User Guide Table 148 PCI Express BAR1 Register Continued Offset 0x40018 Configuration 0x18 Bits Field Type Description InitVal 2 1 Type RO BAR Type 0x2 BAR can be located in 64 bit memory address space 3 Prefetch RO Prefetch Enable 0x1 Indicates that pre
301. ial ATA Host Controller SATAHC Registers Table 341 LTMode Register Continued Offset Port 0 0x8230C Port 1 0x8430C Bits Name Type Description InitVal 13 8 Reserved RW Reserved 0x0 NOTE Perform a read modify write access to this field to avoid the con tents being changed 14 Reserved RW Reserved 0x0 16 15 Reserved RW Reserved 0x1 NOTE Perform a read modify write access to this field to avoid the con tents being changed 18 17 Reserved RW Reserved 0x0 NOTE Perform a read modify write access to this field to avoid the con tents being changed 20 19 Reserved RW Reserved 0x0 NOTE Perform a read modify write access to this field to avoid the con tents being changed 23 21 Reserved RW Reserved 24 Reserved RW Reserved 0x1 NOTE Perform a read modify write access to this field to avoid the con tents being changed 31 25 Reserved RW Reserved Table 342 PHY Mode 3 Register Offset Port 0 0x82310 Port 1 0x84310 NOTE This register must be fully written on every write access to any of its fields Bits Name Type Description InitVal 1 0 Reserved RES Reserved 0x2 4 2 SQ RW Squelch Detector Threshold 0x2 000 50 mV peak to peak 001 100 mV peak to peak 010 150 mV peak to peak default 011 200 mV peak to peak 100 250 mV peak to peak 101 300 mV peak to peak 110 350 mV peak to peak 111 400 mV peak to peak Copyright 2007 Mar
302. ication for a detailed description Bits Name Type Description InitVal 3 0 DET RW This field controls the host adapter device detection and interface initializa 0x4 tion 0000 No device detection or initialization action requested 0001 Perform interface communication initialization sequence to establish communication 0100 Disable the Serial ATA interface and put the PHY in offline mode All other values are reserved Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 248 88F5182 marveL Open Source Community Programmer s User Guide Table 340 SControl Register Continued Offset Port 0 0x82308 Port 1 0x84308 NOTE See the Serial ATA specification for a detailed description Bits Name Type Description InitVal 7 4 SPD RW This field represents the highest allowed communication speed the inter 0x0 face is able to negotiate 0000 No speed negotiation restrictions 0001 Limit speed negotiation to a rate not greater than Generation 1 com munication rate 0010 Limit speed negotiation to a rate not greater than Generation 2 com munication rate All other values are reserved 11 8 IPM RW This field represents the enabled interface power management states that 0x0 can be invoked via the Serial ATA interface power management capabili ties 0000 No interface power management
303. ide Table 181 PCI Error Report Register Map Register Offsets Page PCI SERRn Mask 0x30C28 Table 243 p 194 PCI Interrupt Cause 0x31D58 Table 244 p 195 PCI Interrupt Mask 0x31D5C Table 245 p 196 PCI Error Address Low 0x31D40 Table 246 p 197 PCI Error Address High 0x31D44 Table 247 p 197 PCI Error Command 0x31D50 Table 248 p 197 Table 182 PCI Configuration Function 0 Register Map Register Offsets Page PCI Device and Vendor ID 0x00 Table 249 p 198 PCI Status and Command 0x04 Table 250 p 198 PCI Class Code and Revision ID 0x08 Table 251 p 200 PCI BIST Header Type Initial Value Latency 0x0C Table 252 p 200 Timer and Cache Line PCI CSn 0 Base Address Low 0x10 Table 253 p 201 PCI CSn 0 Base Address High 0x14 Table 254 p 201 PCI CSn 1 Base Address Low 0x18 Table 255 p 202 PCI CSn 1 Base Address High 0x1C Table 256 p 202 PCI Internal Registers Memory Mapped Base 0x20 Table 257 p 202 Address Low PCI Internal Registers Memory Mapped Base 0x24 Table 258 p 202 Address High PCI Subsystem Device and Vendor ID 0x2C Table 259 p 203 PCI Expansion ROM Base Address Register 0x30 Table 260 p 203 PCI Capability List Pointer Register 0x34 Table 261 p 203 PCI Interrupt Pin and Line 0x3C Table 262 p 203 PCI Power Management 0x40 Table 263 p 204 PCI Power Management Control and Status 0x44 Table 264 p 205
304. idth gt OR Example SDRAM_Configuration lt Dwidth gt Where Global Control represents the register name and lt Dwidth gt represents the register field name Register field bits are enclosed in brackets Example Field 1 0 Register addresses are represented in hexadecimal format Example 0x0 Reserved The contents of the register are reserved for internal use only or for future use Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 10 88F5182 marveL Open Source Community Programmer s User Guide Section 1 Overview The Marvell 88F5182 is a high performance highly integrated Storage Networking System Engine based on Marvell proprietary ARMv5TE compliant CPU core Figure 1 is a block diagram of the 88F5182 interfaces Figure 1 88F5182 Interface Block Diagram Marvell CPU Local bus Bridge System Bus Memory Controller eo 5585 E SATA II IDMA PCI Express prias with Xor GPPs with PCI Gigabit To integrated Crypto UART X2 intergrated 32 bit Ethernet bred PHYs graphic TWSI SERDES port port X 2 ports Engine Device X 1 port X 2 ports The 88F5182 incorporates the following functions interfaces Marvell Processor Marvell ARM9te compliant core Core DDR SDRAM Memory Controller PCI Express
305. ield i e bit 17 of this register is set to 1 when a SATA CRC error occurs Bit 1 of this field is set to 1 when an internal FIFO error occurs Bit 2 of this field is set to 1 when the Link Layer is reset to Idle state by the reception of SYNC primitives from the device Bit 3 of this field is set to 1 when Link state errors coding errors or run ning disparity errors occur during FIS reception Doc No MV S400130 00 Rev 0 5 Page 231 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 313 EDMA Interrupt Error Cause Register Continued Offset Port 0 0x82008 Port 1 0x84008 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 25 21 LinkCtlTxErr RWO Link Control Transmit Error 0x0 This field indicates when a control FIS is transmitted with errors Bit 0 of this field i e bit 21 of this register is set to 1 when a SATA CRC error occurs Bit 1 of this field is set to 1 when an internal FIFO error occurs Bit 2 of this field is set to 1 when the Link Layer is reset to Idle state by the reception of SYNC primitives from the device Bit 3 of this field is set to 1 when the Link Layer accepts a DMAT primitive from the device Bit 4 of this field is set to 1 to indicate w
306. ield Type Description InitVal 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 See Section 2 2 PCI Express Address Map on page 13 15 8 Attr RW Target specific attributes depending on the target interface OxOE See Section 2 2 PCI Express Address Map on page 13 31 16 Size RW Window Size OxOFFF Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as a sequence of 1 s followed by a sequence of 0 s The number of 1 s specifies the size of the window in 64 KByte granularity A value of OxOFFF specifies 256 MByte Table 116 PCI Express Window0 Base Register Offset 0x41824 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x0000 Used with the lt Size gt field to set the address window size and location Corresponds to transaction address 31 16 Table 117 PCI Express Window0 Remap Register Offset 0x4182C Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Used with the Size field to specifies address bits 31 0 to be driven to the target interface Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 135 Document Classification Propriet
307. ield Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap OxE8000000 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 205 DevCSn 2 Base Address Remap Offset Ox30D58 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap OxF0000000 Table 206 BootCSn Base Address Remap Offset 0x30D54 Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap OxF8000000 Table 207 P2P Mem0 Base Address Remap Low Offset Ox30D5C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap 0x80000000 Table 208 P2P Mem0 Base Address Remap High Offset Ox30D60 Bits Field Type Description InitVal 31 0 P2PORemap RW P2P Mem BAR Remap Address 0x0 Table 209 P2P I O Base Address Remap Offset Ox30D6C Bits Field Type Description InitVal 31 0 Various RW Same as CSn 0 Base Address Remap 0xC0000000 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 178 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 210 Expansion ROM Base Address Remap Offset Ox30F38 Bits Field Type Description
308. ification the maximum supported TW SCK frequency is 100 kHz Fast mode where TW SCK frequency is 400 kHz is not supported 11 2 TWSI Master Operation The Marvell processor core can initiate TWSI master read and write transactions via TWSI registers as described in the following sections 11 2 1 Master Write Access A master write access consists of the following steps 1 The Marvell processor core sets the Start bit in the TWSI Control register see Table 495 on page 336 to 1 The TWSI master then generates a start condition as soon as the bus is free sets an Interrupt flag and sets the Status register to 0x8 2 The Marvell processor core writes 7 bit address plus a write bit to the TWSI Data register see Table 494 on page 336 and clears Interrupt flag for the TWSI master interface to drive the slave address on the bus The target slave responds with acknowledge This causes an Interrupt flag to be set and a status code of 0x18 is registered in the Status register If the target TWSI device has an 10 bit address the Marvell processor core needs to write the remainder 8 bit address bits to the Data register The Marvell processor core then clears the Interrupt flag for the master to drive this address on the bus The target device responds with acknowledge causing an Interrupt flag to be set and status code of OxDO be registered in the TWSI Status register see Table 496 on page 338 3 The Marvell processor core writes data by
309. ignored 0 The EDMA is idle 1 The EDMA is active 1 eDsEDMA SC Disable EDMA 0x0 This bit is self negated When this bit is set to 1 the EDMA aborts the current Command and then clears eEnEDMA bit 0 If the EDMA operation is aborted during command execution the host SW must set lt eAtaRst gt bit 2 to recover 2 eAtaRst RW ATA Device Reset 0x0 When this bit is set to 1 Serial ATA transport link and physical layers are reset All Serial ATA Interface Registers see Table 293 Serial ATA Inter face Registers Map on page 217 are reset except the Serial ATA Inter face Configuration Register and the OOB COMRESET signal is sent to the device after configuring the DET field in the SControl Register Table 340 p 248 Host must not read write Serial ATA Interface Registers If Host initiates a read write to Serial ATA Interface Registers when this bit is set the transaction gets stuck until EDMA IORdy Timeout Register expires 0 Normal operation 1 Device reset e Whenthis bit is set and EDMA is enabled lt eEnEDMAs is set to 1 the EDMA operation must be aborted set lt eDSEDMAs to 1 e When this bit is set and the Basic DMA is enabled the Start field in the Basic DMA Command Register Table 331 p 241 is set to 1 the Basic DMA operation must be aborted clear Start to 0 3 Reserved RW Reserved 0x0 4 eEDMAFrz RW EDMA Freeze 0x0 When this bit is set EDMA does not pull new commands from CRQB If co
310. in the response queue 0 Anew CRPB was not placed in the response queue 12A new CRPB was placed in the response queue When EDMA is disabled Field lt eEnEDMAs is cleared This field is set when the Basic DMA in port 1 completes the data trans fer clears field lt BasicDMAActive gt and moves to idle state 0 Basic DMA has not completed the data transfer 1 Basic DMA completed the data transfer 3 2 Reserved RES 0x0 Reserved 4 SalntCoal RWO 0x0 7 5 Reserved RES 0x0 1 Cause for Interrupt Coalescing occurs SATA Interrupt Coalescing This bit is set When the accumulated number of lt SaCrpbXDone gt indications from the ports that participate in the coalescing mechanism according to the setting of the CoalDis field in the SATAHC Configuration Register Table 294 p 218 since the last Salnt Coal negation reaches the value set in the SATAHC Interrupt Coalescing Threshold Register or When the time from first lt SaCrpbXDone gt assertion after lt SalntCoal gt negation reaches the value set in the SATAHC Interrupt Time Threshold Register 0 Cause for Interrupt Coalescing did not occur Reserved 8 SaDevlnterruptO RWO 0x0 SATA Device Interrupt Port 0 This bit is set if field lt eEnEDMAs is cleared and the ATA interrupt line in port 0 is active 0 The ATA interrupt line in port 0 was not active 1 The ATA interrupt line in port O was active 9 SaDevinterrupt1 RW
311. indow in 64 KByte granularity e g a value of OxOOFF specifies 256 16 MByte NOTE A value of 0x0 specifies 64 KByte size Table 304 Window0 Base Register Offset 0x80034 Bits Field Type Description InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x0000 Used with the lt Size gt field to set the address window size and location Corresponds to transaction address 31 16 Table 305 Window1 Control Register Offset 0x80040 Bits Field Type Description InitVal 0 WinEn RW Window1 Enable 0x1 See the Window0 Control Register Table 303 p 223 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 See the Window0 Control Register 15 8 Attr RW Target specific attributes depending on the target interface 0x0D See the Window0 Control Register 31 16 Size RW Window Size OxOFFF See the Window0 Control Register Table 306 Window1 Base Register Offset 0x80044 Bits Field Type Description InitVal 15 0 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 224 MARV e ELL 88F5182 Open Source Community Programmer s User Guide Table 306 Window1 Base Register Continued Offset 0x80044 Bits Fi
312. ing bit in Local to Sys tem Bridge Interrupt Mask Register 1 Host2CPUDoor RO Doorbell interrupt bell 0x0 This bit is set when at least one bit is set in Host to CPU Doorbell Register and is not masked by the corresponding bit in Host to CPU Doorbell Mask Register 2 CPU2HostDoor RO Doorbell interrupt bell 0x0 This bit is set when at least one bit is set in CPU to Host Doorbell Register and is not masked by the corresponding bit in CPU to Host Doorbell Mask Register 3 UARTO RO UARTO interrupt 0x0 4 UART1 RO UART1 Interrupt 0x0 5 TWSI RO TWSI interrupt 0x0 6 GPIO7_0 RO GPIO 7 0 interrupt 0x0 7 GPIO15 8 RO GPIO 15 8 interrupt 0x0 8 GPIO23 16 RO GPIO 23 16 interrupt 0x0 9 GPIO25 24 RO GPIO 25 24 interrupt 0x0 10 PEXOErr RO PCI Express error 0x0 11 PEXOINT RO PCI Express INTA B C and D message 0x0 12 USBCnt1 RO USB Port 1 controller interrupt 0x0 13 Reserved RO Reserved 0x0 Read only Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 102 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 61 Main Interrupt Cause Register Continued Offset 0x20200 NOTE All bits are read only To clear an interrupt software must access the Local Interrupt Cause registers Bits Field Type Description InitVal 14 DEVErr RO Device bus error DEV_READY tim
313. inters are implemented as indexes and each entry in the queue is a fixed length the pointer can be converted to an address using the formula Entry address Queue Base address entry length pointer value The request queue is the interface that the CPU software uses to queue ATA DMA commands as a request for a data transaction between the system memory and the device Each entry in the request queue is 32 bytes in length consisting of a command tag the EDMA parameters and the ATA device command to initiate the device and to perform the data transaction The response queue is the interface that the EDMA uses to notify the CPU software that a data transaction between the system memory and the device has completed Each entry in the response queue is 8 bytes in length consisting of the command tag and the response flags Figure 3 Command Request Queue 32 Entries NOTE Field lt eEDMAQueLen gt 0 in EDMA Configuration Register Entry Byte Entry Byte Number Number Number Number 0 Empty 0 0 CRQB 0 In Out 1 32 1 32 Pointer aliad Pointer GROB In 2 64 2 64 Empty Pointer ue Empty 6 ut 3 Empty 96 3 CRQB 96 a Pointer 4 Empty 128 4 CRQB 128 e Empty e e CRQB e e e e e 31 Empty 1024 31 CRQB 1024 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 22 e 88F5182 E marveL Open Source Commu
314. ion this field will NA contains the low bits of the DES result Table 437 DES Data Out High Register Offset OXx9DD7C Bits Field Type Description InitVal 31 0 DataOutHi RO When the DES or the Triple DES completes the calculation this field will NA contains the high bits of the DES result Table 438 DES Data Buffer Low Register Offset 0x9DD70 Bits Field Type Description InitVal 31 0 DataBufLo WO The host writes data blocks of low words to be encrypted decrypted to this 0x0 register Table 439 DES Data Buffer High Register Offset Ox9DD74 Bits Field Type Description InitVal 31 0 DataBufHi WO The host writes data blocks of high words to be encrypted decrypted to this 0x0 register Table 440 DES Initial Value Low Register Offset Ox9DD4O Bits Field Type Description InitVal 31 0 DESIVLo RW Contains low bits of the Initial Value in CBC mode This register is ignored in 0x0 ECB mode Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 316 88F5182 marveL Open Source Community Programmer s User Guide Table 441 DES Initial Value High Register Offset 0x9DD44 Bits Field Type Description InitVal 31 0 DESIVHi RW Contains high bits of the Initial Value in CBC mode This register is ignored in 0x0
315. is bit was cleared 25 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 247 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 338 SError Register Continued Offset Port 0 0x82304 Port 1 0x84304 NOTE A write of 1 clears the bits in this register A write of 0 has no affect Bits Name Type Description InitVal 26 X RW Exchanged 0x0 When set to 1 this bit indicates that device presence has changed since the last time this bit was cleared The means by which the implementation determines that the device presence has changed is vendor specific This bit may be set anytime a PHY reset initialization sequence occurs as determined by reception of the COMINIT signal whether in response to a new device being inserted a COMRESET having been issued or power up 31 27 Reserved RES Reserved 0x0 Table 339 SError Interrupt Mask Register Offset Port 0 0x82340 Port 1 0x84340 Bits Field Type Description InitVal 31 0 eSErrintMsk RW SError Interrupt Mask Bits 0x019C0 Each of these bits checks the corresponding bit in SError Register 000 Table 338 p 246 and if these bits are disabled 0 they mask the inter rupt 0 Mask 1 Do not mask Table 340 SControl Register Offset Port 0 0x82308 Port 1 0x84308 NOTE See the Serial ATA specif
316. is bit is set when field lt CPUTimer0 gt in CPU Timer 0 Register reaches 0 2 CPUTimer1intR RWC CPU Timer 1 Interrupt eq 0x0 This bit is set when field lt CPUTimer1 gt in CPU Timer 1 Register reaches 0 3 CPUWDTimerln RWC CPU Watchdog Timer Interrupt tReq 0x0 This bit is set when field lt CPUWDTimer gt in CPU Watchdog Timer Register reaches 0 31 4 Reserved RWC Reserved 0x0 Table 60 Local to System Bridge Interrupt Mask Register Offset 0x20114 Bits Field Type Description InitVal 3 0 Mask RW There is a mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of interrupt pins It does not affect the setting of bits in the Cause register 31 4 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 101 Document Classification Proprietary June 25 2007 Preliminary Local to System Bridge Registers A 4 3 Main Interrupt Controller Registers Table 61 Main Interrupt Cause Register Offset 0x20200 NOTE All bits are read only To clear an interrupt software must access the Local Interrupt Cause registers Bits Field Type Description InitVal 0 Bridge RO Local to System Bridge interrupt 0x0 This bit is set when at least one bit is set in Local to System Bridge Interrupt Cause Register and is not masked by the correspond
317. is con nected clear this bit to 0 NO WD When bit 16 lt eEDMAFBSs in this register is set to 1 the Basic DMA ignores the value of this bit and a value of 1 is assumed 31 27 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 229 Document Classification Proprietary June 25 2007 Preliminary Table 312 EDMA Timer Register 0x82004 Port 1 0x84004 Offset Port 0 Serial ATA Host Controller SATAHC Registers Bits Field Type Description InitVal 31 0 eTimer RW EDMA Timer 0x0 This 32 bit counter is increment every 16 clocks when the EDMA is enabled e the lt eEnEDMAs field in the EDMA Command Register Table 321 p 236 is set to 1 When EDMA command is completed the content of this register is written into the command response queue This data may be used to estimate the command execution time Table 313 EDMA Interrupt Error Cause Register Offset Port 0 0x82008 Port 1 0x84008 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 1 0 Reserved RWO Reserved 0x0 2 eDevErr RWO EDMA Device Error 0x0 This bit is set to 1 when 1 The EDMA is enabled i e field lt eEnEDMAs is set to 1 and 2 Register Device to Host FIS Frame Information Structure or Set Device Bits FIS is re
318. ister Continued Offset 0x01498 Bits Field Type Description InitVal 31 8 Reserved RO Reserved 0x0 Table 102 DDR2 SDRAM ODT Control Register Offset 0x0149C Bits Field Type Description InitVal 3 0 ODTRd RW DDR Controller UO buffer ODT control for read transactions 0x0 Bit 0 if set to 1 internal ODT is asserted during read from DDR SDRAM bank 0 Bit 1 if set to 1 internal ODT is asserted during read from DDR SDRAM bank 1 Bit 2 if set to 1 internal ODT is asserted during read from DDR SDRAM bank 2 Bit 3 if set to 1 internal ODT is asserted during read from DDR SDRAM bank 3 Refer to the Design Considerations for this product 7 4 ODTWr RW DDR Controller UO buffer ODT control for write transactions 0x0 Bit 0 if set to 1 internal ODT is asserted during write to DDR SDRAM bank 0 Bit 1 if set to 1 internal ODT is asserted during write to DDR SDRAM bank 1 Bit 2 if set to 1 internal ODT is asserted during write to DDR SDRAM bank 2 Bit 3 if set to 1 internal ODT is asserted during write to DDR SDRAM bank 3 Refer to the Design Considerations for this product 9 8 ODTEn RW DDR Controller I O buffer ODT Enable 0x0 0x0 0x2 internal ODT assertion de assertion is controlled by lt ODTRd gt ODTWr fields 0x1 Internal ODT is never active 0x3 Internal ODT is always active Refer to the Design Considerations for this product 11 10 ODTSel
319. ister PCI Express MSI Message Control Register 0x40050 Table 158 p 155 PCI Express MSI Message Address Register 0x40054 Table 159 p 155 PCI Express MSI Message Address High Register 0x40058 Table 160 p 156 PCI Express MSI Message Data Register 0x4005C Table 161 p 156 PCI Express Capability Register 0x40060 Table 162 p 156 PCI Express Device Capabilities Register 0x40064 Table 163 p 157 PCI Express Device Control Status Register 0x40068 Table 164 p 158 PCI Express Link Capabilities Register 0x4006C Table 165 p 161 PCI Express Link Control Status Register 0x40070 Table 166 p 161 PCI Express Advanced Error Report Header Register 0x40100 Table 167 p 163 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 128 88F5182 marveL Open Source Community Programmer s User Guide Table 107 PCI Express Register Map Table Continued Register Name Offset Table amp Page PCI Express Uncorrectable Error Status Register 0x40104 Table 168 p 163 PCI Express Uncorrectable Error Mask Register 0x40108 Table 169 p 165 PCI Express Uncorrectable Error Severity Register 0x4010C Table 170 p 165 PCI Express Correctable Error Status Register 0x40110 Table 171 p 165 PCI Express Correctable Error Mask Register 0x40114 Table 172 p 166 PCI Express Advanced Error Capability and Control Regis 0x40118 Table 173 p 167
320. isters Table 492 TWSI Slave Address Offset 0x11000 Bits Field Type Description InitVal 0 GCE RW General Call Enable 0x0 If set to 1 the TWSI slave interface responds to general call accesses 7 SAddr RW Slave address 0x0 For a 7 bit slave address bits 7 1 are the slave address For a 10 bit address SAddr 7 3 must be set to 11110 and SAdadr 2 1 stands for the two MSB bits 9 8 of the 10 bit address 31 8 Reserved RO Reserved 0x0 Table 493 TWSI Extended Slave Address Offset 0x11010 Bits Field Type Description InitVal 7 0 SAddr RW Bits 7 0 of the 10 bit slave address 0x0 31 8 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell June 25 2007 Preliminary Page 335 Document Classification Proprietary Table 494 TWSI Data Offset 0x11004 Two Wire Serial Interface TWSI Registers Bits Field Type Description InitVal 7 0 Data RW Data Address byte to be transmitted by the TWSI master or slave or data 0x0 byte received In the case of the Address byte bit 0 is the Read Write Command bit 31 8 Reserved RO Reserved 0x0 Table 495 TWSI Control Offset 0x11008 Bits Field Type Description InitVal 1 0 Reserved RO Reserved 0x0 2 ACK RW Acknowledge 0x0 When set to 1 the TWSI drives an acknowledge bit on the bus in response to a received address slav
321. isters Table 545 XOR Engine Interrupt Cause XEICR Offset 0x60930 Bit Field Type Description InitVal 0 EODO CO End of Descriptor Asserted when the XOR Engine finished the transfer 0x0 of the current descriptor operation byteCount 0 Software can con trol EOD interrupt assertion per descriptor through EODIntEn bit in the Command field of the descriptor 1 EOCO CO End of Chain Asserted when the XOR Engine finished transfer of cur 0x0 rent descriptor operation and it is currently the last in the descriptor chain byteCount 0 and XENDPZNULL Also asserted upon end of chain processing due to error condition 2 StoppedO CO XOR Engine completed stopping routine after receiving stop command 0x0 setting XEstop It has entered Inactive state 3 PausedO CO XOR Engine completed Pausing routine after receiving pause com 0x0 mand setting XEpause It has entered paused state 4 AddrDecodeO CO Failed address decoding Address is not in any window or matches 0x0 more than one window 5 AccProt0 CO Access Protect Violation 0x0 Trying to access an address in a window in which access is not allowed 6 WrProtO CO Write Protect violation 0x0 Trying to write to a window which is write protected 7 OwnErrO CO Descriptor Ownership Violation 0x0 Attempt to access the descriptor owned by the CPU 8 IntParityErrO CO Parity error caused by erroneous internal buffer read 0x0 Doc No MV S400
322. it 20 Arb bit 21 BIST bit 24 lt PMG gt bit 25 and lt PRST gt bit 26 see Table 243 PCI SERRn Mask on page 194 Table 244 PCI Interrupt Cause Offset 0x31D58 NOTE All bits are Read Write Clear only A cause bit sets upon error event occurrence A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 23 0 Cause RWC Cause bit per event as described in the SERRn Mask register 0x0 24 BIST RWC PCI BIST Interrupt 0x0 25 PMG RWC PCI Power Management Interrupt 0x0 Doc No MV S400130 00 Rev 0 5 Page 195 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 244 PCI Interrupt Cause Continued Offset 0x31D58 NOTE All bits are Read Write Clear only A cause bit sets upon error event occurrence A write of 0 clears the bit A write of 1 has no affect Bits Field Type Description InitVal 26 PRST RWC PCI Reset Assert 0x0 31 27 Sel RWC Specifies the error event currently being reported in the Error Address 0x0 registers 0x0 Reserved 0x1 SWrPerr 0x2 SRdPerr 0x3 Reserved 0x4 Reserved 0x5 MWrPerr 0x6 MRdPerr 0x7 Reserved 0x8 MMabort 0x9 MTabort OxA Reserved OxB MRetry OxC Reserved OxD Reserved OxE Reserved OxF Reserved 0x10 Reserved 0x11 STabort 0x12 Reserved 0x13 Reserved 0x14 Reserved
323. it is cleared in the command regis ter When this bit is read as a 0 all data transferred form the drive during the previous Basic DMA is visible in system memory unless the Basic DMA command was aborted This bit is set when the start bit is written to the command register This bit is cleared when The last transfer for the region is performed where EOT for that region is set in the region descriptor OR e The lt eEDMAFBSs field in the EDMA Configuration Register Table 311 p 227 is set and a complete FIS is received or a com plete FIS is transmitted OR The start bit is cleared in the command register When the lt eEarlyCompletionEn gt field in the EDMA Configuration Register Table 311 p 228 is set this bit is cleared as soon as last data leaves the DMA When field lt eEarlyCompletionEn gt is cleared and this bit is read as a 0 all data transferred form the drive in a read transaction during the previous Basic DMA is visible in system memory unless the Basic DMA command was aborted 0 The DMA is in idle state 1 The DMA is active 1 BasicDMAError RO This bit is valid when bit 0 lt BasicDMAActive gt in this register is cleared 0x0 This bit is set when an error is encounters or when the DMA halts abnor mally 0 No error 1 Error 2 BasicDMA RO This bit is valid when bit 0 lt BasicDMAActive gt in this register is cleared Paused 0x0 This bit is set when Bit lt eEDMAFBSs is set and Bit 0 lt BasicDMAAct
324. it words 010 Burst is limited to 4 64 bit words 011 Burst is limited to 8 64 bit words 100 Burst is limited to 16 64 bit words NOTE This field effects only data transfers Descriptor fetch is done always with 4LW burst size Must not be changed other values degrade performance However a larger value is optimal for DDR SDRAM performance 31 25 Reserved RO Read Only 0x0 Table 389 IP Differentiated Services CodePoint 0 to Priority DSCPO Offset 0x72420 Bits Field Type Description InitVal 29 0 TOS Q 29 0 RW The Priority queue mapping of received frames with DSCP values 0 corre 0x0 sponding to TOS Q 2 0 through 9 corresponding to TOS Q 29 27 NOTE The initial value means that ToS does not effect queue decisions 31 30 Reserved RO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 282 88F5182 marveL Open Source Community Programmer s User Guide Table 390 IP Differentiated Services CodePoint 1 to Priority DSCP1 Offset 0x72424 Bits Field Type Description InitVal 29 0 TOS Q 59 30 RW The Priority queue mapping of received frames with DSCP values 10 corre 0x0 sponding to TOS_Q 32 30 through 19 corresponding to TOS_Q 59 57 NOTE The initial value means that ToS does not effect queue decisions 31 30 Reserved RO Reserved 0x0
325. iter Operation 0x0 0 Disable 1 Enable Table 221 PCI P2P Configuration Offset 0x31D14 Bits Field Type Description InitVal 15 0 Reserved RW Reserved OxFF Must be OxFF 23 16 BusNumber RW The number of the PCI bus to which the PCI interface is connected 0x0 28 24 DevNum RW The Device number of the PCI interface 0x0 31 29 Reserved RES Reserved 0x0 Table 222 PCI Access Control Base 0 Low Offset 0x31E00 Bits Field Type Description InitVal 0 En RW Access control window enable 0x0 0 Disable 1 Enable 3 1 Reserved RW Reserved 0x0 4 AccProt RW Access Protect 0x0 0 PCI access to this region is allowed 1 PCI access to this region is forbidden 5 WrProt RW Write Protect 0x0 0 PCI write is to this region is allowed 1 PCI write to this region is forbidden 7 6 PCISwap RW PCI Slave Data Swap Control 0x0 00 Byte Swap 01 No swapping 10 Both byte and word swap 11 Word swap Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 187 Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 222 PCI Access Control Base 0 Low Continued Offset 0x31E00 Bits Field Type Description InitVal 9 8 RdMBurst RW Read Maximum Burst 0x0 Specifies the maximum read burst size for a single transaction between a PCI slave and the other interfaces 00 32 bytes 01 64 bytes 10 128 by
326. ive gt is cleared and e The last transfer for the region is not yet performed or EOT for that region is not set in the region descriptor This bit is cleared when Bit 0 lt BasicDMAActive gt is cleared and e The last transfer for the region is performed where EOT for that region is set in the region descriptor OR The start bit is cleared in the command register 0 The DMA is in idle state 1 The DMA is paused Doc No MV S400130 00 Rev 0 5 Page 243 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 332 Basic DMA Status Register Continued Offset Port 0 0x82228 Port 1 0x84228 Bits Field Type Description InitVal 3 BasicDMALast RO This bit is valid when bit 0 lt BasicDMAActive gt in this register is cleared 0x0 This bit is set when e Field xeEDMAFBS is set and Field lt BasicDMAActive gt is cleared and e EOT for that region is set in the region descriptor This bit is cleared when Field lt BasicDMAActive gt is cleared and e EOT for that region is cleared in the region descriptor 0 DMA halts before the last data region 1 DMA halts in the last data region 31 4 Reserved RES Reserved 0x0 Table 333 Descriptor Table Low Base Address Register Offset Port 0 0x8222C Port 1 0x8422C NOTE Enhanced Physical Region Descriptors are in use to enable 64 bit memory a
327. knowledge continues until the TWSI master ends the transaction with a stop condition In case of read access following the TWSI slave address acknowledge the TWSI slave drives 8 bit data and the master responds with acknowledge This read access 8 bit data followed by acknowledge continues until the TWSI master ends the transaction by responding with no acknowledge to the last 8 bit data followed by a stop condition A target slave that cannot drive valid read data right after it received the address can insert wait states by forcing TW SCK low until it has valid data to drive on the TW SDA line A master is allowed to combine two transactions After the last data transfer it can drive a new start condition followed by a new slave address rather than driving a stop condition Combining transactions guarantees that the master does not loose arbitration to some other TWSI master The TWSI interface master and slave activities are handled by Marvell core access to internal registers plus the interrupt interface TWSI examples are shown in Figure 7 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 40 88F5182 marveL Open Source Community Programmer s User Guide Figure 7 TWSI Examples Data Transfer Sequence SDA yy j Start Valid GE Stop Condition Data y Condition Change Sequential Read S t First Data Last Data
328. l Pads Calibration Register Offset 0x014C0 Bits Field Type Description InitVal 5 0 DrvN RW Pad Driving N Strength 0x0 Refer to the Design Considerations for this product NOTE Only applicable when auto calibration is disabled 11 6 DrvP RW Pad Driving P Strength 0x0 Refer to the Design Considerations for this product NOTE Only applicable when auto calibration is disabled 13 12 DriveStrength RW Drive Strength 0x0 This field defines the output drive strength For DDR2 SDRAM The value is 0x3 For DDR1 SDRAM The value is 0x1 1544 Reserved RO Read Only 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 121 Document Classification Proprietary June 25 2007 Preliminary DDR SDRAM Controller Registers Table 98 DDR SDRAM Address Control Pads Calibration Register Continued Offset 0x014C0 Bits Field Type Description InitVal 16 TuneEn RW Set to 1 enables the auto calibration of pad driving strength 0x1 22 17 LockN RO When auto calibration is enabled represents the final N locked value of the 0x0 driving strength Read Only Refer to the Design Considerations for this product 28 23 LockP RO When auto calibration is enabled represents the final P locked value of the 0x0 driving strength Read Only Refer to the Design Considerations for this product 30 29 Reserved RO Read Only 0x0 31 WrEn RW Write Enable 0x0 0 Register is read only except for bit
329. l Register ec ceecsesesssceeeeenseseeseeeeseeeeeeeaeseneeaaeseaeesaeeenessaesaeeseeseeneeesaeeeeneaaeeseneneseentees Offset 0x20000 Table 35 tele RE EE ER Offset 0x20004 Table 36 Window0 Remap Low Register eese enne nenne nennen 92 Offset 0x20008 Table 37 Window0 Remap High Register teneret renrenretnre trennen nnneetre nnne n nre 92 Offset 0x2000C Table 38 Window1 Control Register ccssccsssessssessceseessneesceceseessensneesccescesscesscesscessnseseesaeeesessossssasenaeecesesneontses 92 Offset 0x20010 Table 39 Window Base Register nece rient stt e do EH VIP FEES e EE PLoS aa Ea Epod en e FOR iae ue 93 Offset 0x20014 Table 40 Window1 Remap Low Heotsier ku 93 Offset 0x20018 Table 41 Window1 Remap High Register trenneenrennretneenren rettet rnse tenerse nns 93 Offset 0x2001C Table 42 Window2 Control Register eerie tenet ete tei re Cosa E EE rhe EE Fee etta etr eov dee Enden 94 Offset 0x20020 Table43 Window2 Base Register tet nsi ttis stare Rl UR Vor dea ERN PE Se REEL a Fade ead keen 94 Offset 0x20024 Table 44 Window3 Control Register eite rte nennen ba reet ates n IDE EYE Y EL ERR ERR ERE ee Pe ERE TR ele 94 Offset 0x20030 Table 45 Window3 ET 95 Offset 0x20034 Table 46 Window4 Control Register kee 95 Offset 0x20040 Table 47 Window4 Base Register nennen enne trennen nennen entente nennen 95 Offset 0x20044 Table
330. l starting address of a data region in System memory Must be set to 0 Table 5 CRQB DW2 Control Flags Offset 0x08 Bits Field Description 0 cDIR CRQB Direction of Data Transaction 0 System memory to Device 1 Device to system memory 5 1 cDeviceQueTag CRQB Device Queue Tag This field contains the Queued commands used as tags attached to the command provided to the drive 11 6 Reserved Reserved Must be 0 15 12 cPMport PM Port Transmit This field specifies the Port Multiplier PM port bits 11 8 in DWO of the FIS header inserted into the FISs transmission associate to this command 16 cPRDMode CRQB PRD Mode This bit defines how the physical data that resides in the system memory is described 0 PRD tables are being used lt cPRD 31 0 gt and lt cPRD 63 32 gt provide the ePRD table starting address 1 Single data region cPRD 31 0 and lt cPRD 63 32 gt provide its starting address lt cDataRegionByteCount gt provides its length 23 17 cHostQueTag CRQB Host Queue Tag This 7 bit field contains the host identification of the command 31 24 Reserved Reserved Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 26 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 6 CRQB DW3 Data Region Byte Coun
331. l to System Bridge Registers Table 47 Window4 Base Register Continued Offset 0x20044 Bits Field Type Description InitVal 31 16 Base RW Base Address 0xC801 See the Window0 Base Register Table 48 Window5 Control Register Offset 0x20050 Bits Field Type Description InitVal 0 win en RW Window5 Enable 0x0 See the Window0 Control Register Table 34 p 91 3 1 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 See the Window0 Control Register Table 34 p 91 15 8 Attr RW Target specific attributes depending on the target interface 0x0 See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size 0x0 See the Window0 Control Register Table 34 p 91 Table 49 Window5 Base Register Offset 0x20054 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x0 See the Window0 Base Register Table 50 Window6 Control Register Offset 0x20060 Bits Field Type Description InitVal 0 win en RW Window6 Enable 0x1 See the Window0 Control Register Table 34 p 91 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary e 88F5182 marveL Open Source Community Programmer s User Guide
332. lassification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 265 PCI VPD Address Continued Offset 0x48 Bits Field Type Description InitVal 31 Flag RW Flag Flipped by System or 88F5182 during VPD Access 0x0 On VPD writes system sets the flag to 1 indicating VPD write is required The 88F5182 clears the flag to indicate that the VPD write is done data from the VPD Data register was written to memory On VPD reads the system sets the flag to 0 indicating VPD read is required The 88F5182 sets the flag to 1 when the read is done data has been read from memory and put in VPD Data register Table 266 PCI VPD Data Offset Ox4C Bits Field Type Description InitVal 31 0 Data RW VPD Data 0x0 Table 267 PCI MSI Message Control Offset 0x50 Bits Field Type Description InitVal 7 0 CapID RW Capability ID 0x5 NOTE Read only from PCI 15 8 NextPtr RW Next Item Pointer 0x68 NOTE Read only from PCI 16 MSIEn RW MSI Enable 0x0 0 Disable The 88F5182 generates a PCI interrupt 1 Enabled The 88F5182 generates MSI messages instead of interrupts 19 17 MultiCap RW Multiple Messages Capable 0x0 The 88F5182 is capable of driving a single message NOTE Read only from PCI 22 20 MultiEn RW Multiple Messages Enable 0x0 The number of messages the system allocates to the 88F5182 must be smaller or equal to MultiCap
333. ld Type Description InitVal 15 0 PECapID RO Extended Capability ID 0x1 The current value of this field identifies the Advanced Error Reporting capa bility 19 16 CapVer RO Capability Version 0x1 31 20 NextPtr RO Next Item Pointer 0x0 This field indicates the last item in the extended capabilities linked list Table 168 PCI Express Uncorrectable Error Status Register Offset 0x40104 Configuration 0x104 NOTE AU fields in this register are sticky not initialized or modified by hot reset All fields in this register except for reserved fields are SC write 1 to clear A write of 0 has no affect Bits Field Type Description InitVal 3 0 Reserved RSVD Reserved 0x0 4 DLPrtErr SC Data Link Protocol Error Status 0x0 NOTE Hot sticky bit not initialized by hot reset 11 5 Reserved RSVD Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 163 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 168 PCI Express Uncorrectable Error Status Register Continued Offset 0x40104 Configuration 0x104 NOTE AN fields in this register are sticky not initialized or modified by hot reset All fields in this register except for reserved fields are SC write 1 to clear A write of 0 has no affect Bits Field Type Description InitVal 12 RPsnTlpErr SC Poisoned TLP Status
334. lds in this register are Read Only Bits Field Type Description InitVal 31 0 NCQ RW See Table 327 EDMA NCQO Done TCQ0 Outstanding Status Register Done 127 96 0x0 on page 240 TCQOutstand A 8 9 Basic DMA Registers Table 331 Basic DMA Command Register Offset Port 0 0x82224 Port 1 0x84224 Bits Field Type Description InitVal 0 Start RW Basic DMA operation is enabled by setting this bit to 1 0x0 Basic DMA operation begins when this bit is detected changing from a 0 to a 1 The Basic DMA transfers data between the ATA device and memory only when this bit is set The Basic DMA operation can be halted by writing a 0 to this bit All state information is lost when a 0 is written The Basic DMA operation cannot be stopped and then resumed This bit is intended to be reset by the CPU after the data transfer is completed If a Basic DMA operation is aborted during command execution to the drive the host software must set lt eAtaRst gt bit 2 to recover 2 1 Reserved RW Reserved 0x0 3 Read RW This bit sets the direction of the Basic DMA transfer 0x0 0 Basic reads are performed Read from system memory and store in the device 1 Basic writes are performed Load from the device and write to system memory This bit must not be changed when the Basic DMA is active 7 4 Reserved RW Reserved 0x0 8 DRegionValid RW This bit indicates if the DataRegionByteCount field 31 16 i
335. le Page XOR Engine Control Registers XOR Engine Channel Arbiter XECHAR 0x60900 Table 542 p 366 XOR Engine 0 1 Configuration XExCR XOR Engine 0 1 Activation XExACTR XORO 0x60910 XOR1 0x60914 XORO 0x60920 XOR1 0x60924 Table 543 p 366 Table 544 p 368 XOR Engine Interrupt Registers XOR Engine Interrupt Cause XEICR 0x60930 Table 545 p 369 XOR Engine Interrupt Mask XEIMR 0x60940 Table 546 p 370 XOR Engine Error Cause XEECR 0x60950 Table 547 p 371 XOR Engine Error Address XEEAR 0x60960 Table 548 p 371 XOR Engine Descriptor Registers XOR Engine 0 1 Next Descriptor Pointer XEXNDPR XORO 0x60B00 XOR1 0x60B04 Table 549 p 372 XOR Engine 0 1 Current Descriptor Pointer XExCDPR XORO 0x60B10 XOR1 0x60B14 Table 550 p 372 XOR Engine 0 1 Byte Count XExBCR XORO 0x60B20 XOR1 0x60B24 Table 551 p 372 XOR Engine Address Decoding Registers XOR Engine 0 1 Window Control XExWCR XORO 0x60B40 XOR1 0x60B44 Table 552 p 372 XOR Engine Base Address XEBARx Copyright 2007 Marvell June 25 2007 Preliminary XEBARO 0x60B50 XEBAR 1 0x60B54 XEBAR2 0x60B58 XEBARS 0x60B5C XEBAR4 0x60B60 XEBAR5 0x60B64 XEBAR6 0x60B68 XEBAR7 0x60B6C Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 364 Table 553 p 374 88F5182 MARVELL Table 541 XOR Engi
336. le 556 XOR Engine 0 1 Address Override Control XExAOCR Continued Offset XEOAOCR 0x60BAO0 XE1AOCR 0x60BA4 Bit Field Type Description InitVal 21 SA7OvrEn RW Override Source Address 7 Control 0x0 23 22 SA7OvrPtr RW Override Source Address 7 Pointer 0x0 NOTE Valid only if SA7OvrEn is set 24 DAOvrEn RW Override Destination Address Control 0x0 0x0 No Override 0x1 Override is enabled 26 25 DAOvrPtr RW Override Destination Address Pointer 0x0 Specifies the register from which the override parameters will be taken 0x0 Target and attributes are taken from XEBARO Address 63 32 taken from XEHARRO 0x1 Target and attributes are taken from XEBAR1 Address 63 32 taken from XEHARR1 0x2 Target and attributes are taken from XEBAR2 Address 63 32 taken from XEHARR2 0x3 Target and attributes are taken from XEBARG Address 63 32 taken from XEHARR3 NOTE Valid only if DAOvrEn is set 27 NDAOvrEn RW Override Next Descriptor Address Control 0x0 0x0 No Override 0x1 Override is enabled 29 28 NDAOvrPtr RW Override Next Descriptor Address Pointer 0x0 Specifies the register from which the override parameters will be taken 0x0 Target and attributes are taken from XEBARO Address 63 32 taken from XEHARRO 0x1 Target and attributes are taken from XEBAR1 Address 63 32 taken from XEHARR1 0x2 Target and attributes are taken from XEBAR2 Address 63 32 taken from XEHARR2 0x3 Targe
337. le FIFOs Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 343 Document Classification Proprietary June 25 2007 Preliminary Table 506 FIFO Control Register FCR Continued UART Interface Registers Offset UART 0 0x12008 UART 1 0x12108 Bits Field Type Description InitVal 1 RxFIFOReset WO Receive FIFO reset 0x0 0 Do not flush data from the receive FIFO 1 Flush data from the receive FIFO 2 TxFIFOReset WO Transmit FIFO reset 0x0 0 Do not flush data from the transmit FIFO 1 Flush data from the transmit FIFO 3 DMAMode WO DMA mode 0x0 0 Single transfer DMA mode 0 1 Multi transfer DMA mode 1 5 4 Reserved RSVD Reserved 0x0 7 6 RxTrigger WO Receive Trigger 0x0 00 1 byte in FIFO 01 4 bytes in FIFO 10 8 bytes in FIFO 11 2 14 bytes FIFO 31 8 Reserved RSVD Reserved Table 507 Line Control Register LCR Offset UART 0 0x1200C UART 1 0x1210C Bits Field Type Description InitVal 1 0 WLS RW Number of bits per character 0x0 00 5 bits 01 6 bits 10 7 bits 11 8 bits 2 Stop RW Stop bits transmitted 0x0 0 1 bit 1 2 bits 3 PEN RW Parity enable 0x0 0 Parity disabled 1 Parity enabled 4 EPS RW Even or odd parity select 0x0 0 Odd parity 1 Even parity 5 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classifi
338. les is inserted after the data transaction from the system memory to the drive completes and before it issues a new command to the drive 0 Disabled No delay is inserted before command retransmission 1 Enabled A delay is inserted before command retransmission Table 326 EDMA Halt Conditions Register Offset Port 0 0x82060 Port 1 0x84060 Bits Field Type Description InitVal 31 0 eHaltMask RW EDMA halts when any bit is set to 1 in the EDMA Interrupt Error Cause OxFC1EOE1F Register Table 313 p 230 and is not masked by the corresponding bit in this field 0 Mask 1 Do not mask Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 239 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 327 EDMA NCQ0 Done TCQ0 Outstanding Status Register Offset Port 0 0x82094 Port 1 0x84094 NOTE When the EDMA is disabled the fields in this register are Read Only Bits Field Type Description InitVal 31 0 NCQDone RW When in NCQ mode NCQ Completion Status TCQOut 0x0 Each bit represents a completed NCQ command corresponding to the host stand 31 0 command ID When set the NCQ command corresponding to the host com mand ID has been completed but not yet updated in the host response queue in system memory CRPB When in TCQ mode TCQ Outstanding Commands Status Each bit represents an outstanding c
339. letion Headers Flow Control Credit Initial Value 0x0 Infinite 31 24 ConfFc RW Flow Control Update Timeout UpdateTo 0x78 This field controls the Flow Control update interval period NOTE Timescale 64 symbol time 256 ns 0x0 Disabled No timeout mechanism on update FC Minimum Value 120 30 us Maximum Value 180 45 us NOTE When extended sync is enabled the check threshold should be configured to 120 us 120 30 us Table 140 PCI Express Acknowledge Timers 1X Register Offset 0x41A40 Bits Field Type Description InitVal 15 0 AckLatTOX1 RW Acknowledge Latency Timer Timeout Value for 1X Link 0x4 Used when the PHY link width Auto Negotiation result is 1X NOTE Timescale symbol_time 4 ns Minimum Value 4 4 symbol times Maximum Value 237 237symbol times 31 16 AckRplyTOX1 RW Acknowledge Replay Timer Timeout Value for 1X 0x320 NOTE Timescale symbol_time 4 ns Initial value 0x320 represents a 800 symbol times timeout Minimum Value 711 711 symbol times Maximum Value 64K 1 64K 1 symbol times Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 145 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 141 PCI Express TL Control Register Offset 0x41AB0 Type Description InitVal 31 0 Reserved RSVD Reserved 0x0 A 6 6 PCI Express Configuration Header Registers
340. ly 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 271 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 370 Ethernet Unit Interrupt Cause EUIC Offset 0x72080 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 0 EtherlntSum RO Ethernet Unit Interrupt Summary 0x0 This bit is a logical OR of the unmasked bits 12 1 in the register 1 Parity RW Parity Error 0x0 Effect on Tx DMA operation If a parity error occurs on the first descriptor fetch the DMA stops and disables the queue If it is on a non first descriptor the Tx DMA in addition asserts the Tx Error interrupt If it is on a packet s data the Tx DMA continues with the transmission but does not ask to gener ate CRC at the end of the packet Effect on Rx DMA operation If a parity error occurs on the first descriptor fetch the DMA stops and disables the queue If it is on a non first descriptor the Rx_DMA in addition asserts the Rx Error interrupt 2 Address RW This bit is set if an Ethernet DMA violates a window access protection Violation 0x0 3 Address RW This bit is set if an Ethernet DMA address does not match any of the Ether NoMatch 0x0 net address decode windows 4 SMIdone RW SMI Command Done 0x0 Indicates the SMI completed a MII management command either read o
341. ment Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 291 Shadow Register Block Registers Map Continued Bits Bits Bits Bits Offset Table Page 31 24 23 16 15 8 7 0 Reserved Reserved Reserved Device LBA Port 0 0x8210C Port 1 0x8410C see Low register ATA ATAPI Reserved Reserved Reserved Device LBA Port 0 0x82110 Port 1 0x84110 Specification Mid register Reserved Reserved Reserved Device LBA Port 0 0x82114 Port 1 0x84114 High register Reserved Reserved Reserved Device Device Port 0 0x82118 Port 1 0x84118 Head Device register Reserved Reserved Reserved Device Com Port 0 0x8211C Port 1 0x8411C mand Status register Reserved Reserved Reserved Device Control Port 0 0x82120 Port 1 0x84120 Alternate Status register A 8 5 Basic DMA Registers Map Table 292 Basic DMA Register Map Register Offset Table Page Basic DMA Command Register Port 0 0x82224 Port 1 0x84224 Table 331 p 241 Basic DMA Status Register Port 0 0x82228 Port 1 0x84228 Table 332 p 243 Descriptor Table Low Base Address Register Port 0 0x8222C Port 1 0x8422C Table 333 p 244 Descriptor Table High Base Address Register Port 0 0x82230 Port 1 0x84230 Table 334 p 244 Data Region Low Address Register Port 0 0x82234 Port 1 0x84234 Table 335 p 245
342. mmands are pending in EDMA cache these commands are sent to the drive regardless to this bit value 0 Pull new commands from CRQB and insert them into the drive 1 Do not Pull new commands from CRQB Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 236 88F5182 marveL Open Source Community Programmer s User Guide Table 321 EDMA Command Register Continued Offset Port 0 0x82028 Port 1 0x84028 Bits Field Type Description InitVal 31 5 Reserved RES Reserved 0x0 Table 322 EDMA Test Control Register Offset Port 0 0x8202C Port 1 0x8402C Bits Field Type Description InitVal 0 eOddPry RW EDMA Odd Parity 0x0 This bit is used for debug of internal parity mechanism When this bit is set and a write transaction to internal memory is performed odd parity bit is calculated When this bit is cleared and a write transaction to internal memory is per formed even parity bit is calculated During a read transaction from internal memory the even parity bit is always calculated 0 Even bit parity is inserted during the write transaction to internal memory 1 Odd bit parity is inserted during the write transaction to internal memory 1 eLoopBack RW EDMA Loopback Mode 0x0 When this bit is set to 1 the EDMA loopback mode is enabled and the SATA is reset When store operation to th
343. mmer s User Guide e Authentication MD5 SHA engine Each of these engines has separate registers for data control and operation modes Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 39 Document Classification Proprietary June 25 2007 Preliminary Two Wire Serial Interface TWSI Functional Description Section 11 Two Wire Serial Interface TWSI 11 1 Functional Description The 88F5182 provides full Two Wire Serial Interface TWSI support It can act as master generating read write requests and as a slave responding to read write requests It fully supports a multiple TWSI masters environment clock synchronization bus arbitration The TWSI interface can be used for various applications It can be used to control other TWSI on board devices to read DIMM SPD ROM and for serial ROM initialization For more details see the Reset Pins and Configuration section in the 88F5182 88F5182 based Storage Networking Platforms Datasheet The TWSI port consists of two open drain signals e TW SCK Serial Clock TW SDA Serial address data The TWSI master starts a transaction by driving a start condition followed by a 7 or 10 bit slave address and a read write bit indication The target TWSI slave responds with acknowledge In case of a write access R W bit is 0 following the TWSI slave acknowledge the master drives 8 bit data and the slave responds with acknowledge This write access 8 bit data followed by ac
344. munity Programmer s User Guide Table 495 TWSI Control Continued Offset 0x11008 Bits Field Type Description InitVal 7 IntEn RW Interrupt Enable 0x0 When set to 1 an interrupt is generated each time the interrupt flag is set 31 8 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 337 Document Classification Proprietary June 25 2007 Preliminary S Note Status and Baud Rate registers share the same offset When being read this register functions as Status register When written it acts as Baud Rate register Two Wire Serial Interface TWSI Registers Table 496 TWSI Status Offset 0x1100C Bits Field Type InitVal Description 7 0 Stat RO OxF8 TWSI Status 0x00 Bus error 0x08 Start condition transmitted 0x10 Repeated start condition transmitted 0x18 Address write bit transmitted acknowledge received 0x20 Address write bit transmitted acknowledge not received 0x28 Master transmitted data byte acknowledge received 0x30 Master transmitted data byte acknowledge not received 0x38 Master lost arbitration during address or data transfer 0x40 Address read bit transmitted acknowledge received 0x48 Address read bit transmitted acknowledge not received 0x50 Master received read data acknowledge transmitted 0x58 Master received read data acknowledge not transmitted 0x60
345. must be set to 1 Bits Field Type Description InitVal 7 0 DivLatchHigh WO The DLH Divisor Latch High register in conjunction with DLL Divisor 0x0 Latch Low register forms a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART It is accessed by first setting the DivLatchRdWrt bit in the Line Control Register LCR The output baud rate is equal to the input clock frequency divided by sixteen times the value of the baud rate divisor baud clock frequency 16 divisor 31 8 Reserved RSVD Reserved Table 505 Interrupt Identity Register IIR Offset UART 0 0x12008 UART 1 0x12108 Bits Field Type Description InitVal 3 0 InterruptID RO Interrupt ID 0x0 0000 Modem Status Changed 0001 No interrupt pending 0010 THR empty 0100 Received Data available 0110 Receiver Status 1100 Character Time Out 5 4 Reserved RO Reserved 0x0 7 6 FIFOEn RO FIFO Enable 0x0 00 FIFOs are disabled default in FIFO mode 11 FIFOs are enabled 31 8 Reserved RSVD Reserved Table 506 FIFO Control Register FCR Offset UART 0 0x12008 UART 1 0x12108 Bits Field Type Description InitVal 0 FIFOEn WO Enable transmit and receive FIFOs This register controls the read and 0x0 write data FIFO operation and the mode of operation for the DMA signals UAO CTSn UA1 CTSn UAO RTSn and UA1 RTSn 0 Disable FIFOs 1 Enab
346. n in XOR DMA ECC and Memlnit modes updated after every write action in CRC mode updated after every calculation operation A 16 4 XOR Engine Address Decoding Registers Table 552 XOR Engine 0 1 Window Control XExWCR Offset XORO 0x60B40 XOR1 0x60B44 Bits Field Type Description 0 WinOen RW Window0 Enable 0x0 0x0 Window 0 is disabled 0x1 Window 0 is enabled 1 Winten RW Window1 Enable 0x0 2 Win2en RW Window2 Enable 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 372 88F5182 marveL Open Source Community Programmer s User Guide Table 552 XOR Engine 0 1 Window Control XExWCR Continued Offset XORO 0x60B40 XOR1 0x60B44 Bits Field Type Description 3 Win3en RW Window3 Enable 0x0 4 Win4en RW Window4 Enable 0x0 5 Win5en RW Window5 Enable 0x0 6 Win6en RW Window6 Enable 0x0 7 Win7en RW Window7 Enable 0x0 15 8 Reserved RO Reserved 0x0 17 16 WinOacc RW Window0 Access control 0x3 0x0 No access allowed 0x1 Read Only 0x2 Reserved 0x3 Full access read or write In case of write protect violation e g write data to a read only region an interrupt is set and the transaction is not driven to the target interface 19 18 Wintacc RW Window1 access control 0x3 21 20 Win2acc RW Win
347. n InitVal 14 DTEAdvert RW DTE advertise 0x0 The value of this bit is written to bit 9 10 of the 1000BaseT PHY device after power up or detection of a link failure 16 15 Reserved RW Reserved 0x0 19 17 MRU RW The Maximal Receive Packet Size 0x1 0 Accept packets up to 1518 bytes in length 1 Accept packets up to 1522 bytes in length 2 Accept packets up to 1552 bytes in length 3 Accept packets up to 9022 bytes in length 4 Accept packets up to 9192 bytes in length 5 Accept packets up to 9700 bytes in length 6 7 Reserved NOTE Modes 3 5 are supported only when operating in 1000 Mbps mode Receiving 9700 byte frames is supported only during 1000 Mbps operation Receiving frames over 2 KB during 100 Mbps operation may result in overrun underrun in some cases 20 Reserved RW Reserved 0x0 21 Set_FullDx RW Half Full Duplex Mode 0x1 0 Port works in Half Duplex mode 1 Port works in Full Duplex mode NOTE This bit is meaningless when the PSCR s AN Duplex bit is set to enable 22 SetFCEn RW Enable receiving and transmitting of 802 3x Flow Control frames in full 0x1 duplex Or enabling of backpressure in half duplex 0 Disabled 1 Enabled NOTE This bit is meaningless when this PSCR AN FC is set to enable 23 SetGMIISpeed RW 0 Port works at 10 100 Mbps 0x1 1 Port works at 1000 Mbps NOTE This bit is meaningless when lt ANSpeed gt is set to enable 24 SetMIISpeed RW If Speed Auto Negotiation
348. n InitVal 7 0 BISTPattern RW BIST Pattern 0x0 Test pattern refer to bits 15 8 of the first DWORD of the BIST Activate FIS 8 BISTMode RW BIST mode 0x0 Test direction 0 BIST Activate FIS Receiver mode 1 BIST Activate FIS Transmitter mode 9 BISTEn RW BIST Test enable On the assertion of the signal BIST mode starts 0x0 0 Disabled 1 Enabled 10 BISTResult RO BIST Test Pass 0x0 0 Passed 1 Failed 15 11 Reserved RES Reserved 0x0 NOTE Perform a read modify write access to this field to avoid the con tents being changed 22 16 Reserved RES Reserved 0x0 31 23 Reserved RES Reserved 0x1 NOTE Perform a read modify write access to this field to avoid the con tents being changed Doc No MV S400130 00 Rev 0 5 Page 253 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 347 BIST DW1 Register Offset Port 0 0x82338 Port 1 0x84338 Bits Name Type Description InitVal 31 0 BistDw1 WO In BIST mode 0x0 The lt BISTEns gt field in the BIST Control Register Table 346 p 253 is set to 1 This field is the second DWORD of the BIST Activate FIS In PHY Loopback mode The lt LBEnable gt field in the Serial ATA Interface Test Control Register Table 351 p 258 is set to 1 This field is the high DWORD 63 32 of the user specified loopback pattern of the BIST Activate FIS Table
349. n There are also abnormal cases such as the slave not responding with acknowledge or arbitration loss Each of these cases is reported in the Status register and needs to be handled by Marvell processor core 11 3 TWSI Slave Operation The TWSI slave interface can respond to a read access driving read data back to the master that initiated the transaction or respond to write access receiving write data from the master The two cases are described in the following sections 11 3 1 Slave Read Access Upon detecting a new address driven on the bus with read bit indication the TWSI slave interface compares the address against the address programmed in the Slave Address register If it matches the slave responds with acknowledge It also sets the Interrupt flag and sets status code to 0xA8 S Note If the TWSI slave address is 10 bit the Interrupt flag is set and status code changes only after receiving and identify address match also on the 2nd address byte The Marvell processor core now must write new read data to the Data register and clears the Interrupt flag causing TWSI slave interface to drive the data on the bus The master responds with acknowledge causing an Interrupt flag to be set and status code of OxB8 to be registered in the Status register If the master does not respond with acknowledge the Interrupt flag is set status code Of 0xCO is registered and TWSI slave interface returns back to idle state If th
350. n Endpoint mode the interrupts can be forwarded also to the Endpoint PCI Express interface The 88F5182 includes two general purpose 32 bit wide timers and a single 32 bit wide watchdog timer The 88F5182 internal architecture is optimized for high performance applications Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 12 e 88F5182 marveL Open Source Community Programmer s User Guide Section 2 Address Map The 88F5182 has a fully programmable address map There is a separate address map for each of the device master interfaces Each interface includes programmable address windows that allow it to access any of the 88F5182 resources Marvell processor core address map e PCI Express address map e PCI address map e SATA address map e Ethernet Controller address map e USB address map e DMAs address map e XOR address map N Note Although each master has independent address windows when a resource is used by multiple masters all masters must use the same address map for this resource This means that all masters use the identical address window for each resource 2 1 Marvell Processor Core Address Map The Marvell processor core interface address map consists of eight programmable address windows for the different interfaces and additional four dedicated windows for the DDR interface See Appendix A 4 1 CPU Address Map Registers on page
351. n Pointer Register Offset Port 0 0x82020 Port 1 0x84020 Bits Field Type Description InitVal 2 0 Reserved RES Reserved 0x0 7 3 eRpQIP RW EDMA Response Queue In Pointer 0x0 The EDMA response queue in pointer is updated increment by the EDMA each time a command execution is completed and a new CRPB is moved from the EDMA internal memory to the response queue by the EDMA The system driver compares the EDMA Response Queue In Pointer with the EDMA Response Queue Out Pointer to determine if there is a CRPB in the response queue that needs processing Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 234 MARVELL e 88F5182 Open Source Community Programmer s User Guide Table 319 EDMA Response Queue In Pointer Register Continued 0x82020 Port 1 0x84020 Offset Port 0 Bits Field Type Description InitVal 9 8 eRpQIP RW Function of this field depends on lt eEDMAQueLen gt 0x0 lt eEDMAQueLen gt 0 This field is reserved lt eEDMAQueLen gt 1 This field serve as EDMA Response Queue In Pointer 6 5 31 10 Reserved RES Reserved 0x0 Table 320 EDMA Response Queue Out Pointer Register Offset Port 0 0x82024 Port 1 0x84024 Bits Field Type Description InitVal 2 0 Reserved RES Reserved 0x0 7 3 eRPQOP RW EDMA Response Queue Out Pointer 0x0
352. n RW Unsupported Request UR Reporting Enable 0x0 0 Disabled UR related error messages are masked Status bit is not masked 1 Enabled UR related error messages enabled In Root Complex mode reporting of errors is internal to status registers only An external error message must not be generated therefore always write 0x0 NOTE UR related error messages are still enabled when URRepEn 0 if SErrEn bit in Table 143 PCI Express Command and Status Register is set NOTE 4 EnRO RO Enable Relaxed Ordering 0x0 88F5182 never sets the Relaxed Ordering attribute in transactions it initiates as a requester Hardwired to 0x0 7 5 MaxPldSz RW Maximum Payload Size 0x0 The maximum payload size supported is 128B refer to bit lt MaxPldSize Sup in the Table 163 PCI Express Device Capabilities Register 0x0 128B Other Reserved 9 8 Reserved RO Reserved 0x0 These bits are hardwired to 0 10 Reserved RSVD Reserved 0x0 11 EnNS RO Enable No Snoop 0x0 88F5182 never sets the No Snoop attribute in transactions it initiates as a requester Hardwired to 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 159 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 164 PCI Express Device Control Status Register Continued Offset 0x40068 Configuration 0x68 Bits Field Type
353. n mode and re activated This also applies if the XOR engine channel finished the operation reached End Of Chain without being stopped by the software Again the engine re enters an inac tive state and can be configured to another operation mode and re activated After paused by software the XOR engine channel suspends the current operation at the earliest opportunity Upon activating the channel again it resumes executing the same operation y Notes The two XOR engine channels are independent in their operation modes The only exception is that both engines must not be configured to ECC or Memlnit operation modes These modes share hardware resources Attempting to change the channels operation mode during a pause will result in unexpected behavior 15 2 Descriptor Chain 15 2 1 Descriptor Format The XOR engine descriptor format supports 32 bit addressing In XOR mode the descriptor consists of sixteen 32 bit words which totals the 64B size of each descriptor In CRC and DMA modes only the upper 32B of the descriptor is needed Therefore the descriptor consists of eight 32 bit words totalling to a 32B size for each descriptor see Figure 14 By fetching a descriptor from memory the XOR engine gets all the information about the next operation to be per formed When the XOR engine finishes the operation associated with a descriptor it closes the descriptor by updating the status word This means the operation completed su
354. n operation modes e XOR calculation Mode XOR e iSCSI CRC32C Calculation Mode CRC e DMA Operation Mode DMA Memory initialization Mode Meminit e Memory ECC error cleanup mode ECC The XOR engine has two independent channels Each channel can be configured to one of the operation modes at a time The operation mode is defined through the OperationMode field in the XOR Engine 0 1 Configura tion XExCR Table 543 p 366 bits 2 0 In the XOR CRC and DMA operation modes the XOR engine is con trolled by chain descriptors and responds to similar activation scheme These modes differ only in the interpretation of the chain descriptor fields In ECC and Memlnit modes the XOR engine responds to different activation schemes It is controlled by programming internal registers directly On all operation modes XOR engine uses the same address decoding scheme Upon startup the two XOR engine channels are in an inactive state and can be configured to any operation mode XOR CRC DMA Meminit or ECC After being configured the XOR engine channel can be activated It can be stopped or paused by software at any time After stopped by software the engine re enters inactive state and can Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 52 88F5182 marveL Open Source Community Programmer s User Guide be configured to another operatio
355. n the Column 1 of the AES result Table 474 AES Decryption Data In Out Column 0 Register Offset OX9DDEC Bits Field Type Description InitVal 31 0 AesDecDatCol0 RW At first this field contains column 0 of the input data block to be decrypted NA When the AES completes the calculation this field will contain the Column 0 of the AES result Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 326 88F5182 marveL Open Source Community Programmer s User Guide Table 475 AES Decryption Key Column 3 Register Offset Ox9DDDO Bits Field Type Description InitVal 31 0 AesDecKeyCol3 RW Contains Column 3 of the AES decryption key 0x0 Table 476 AES Decryption Key Column 2 Register Offset 0x9DDD4 Bits Field Type Description InitVal 31 0 AesDecKeyCol2 DW Contains Column 2 of the AES decryption key 0x0 Table 477 AES Decryption Key Column 1 Register Offset 0x9DDD8 Bits Field Type Description InitVal 31 0 AesDecKeyCol1 RW Contains Column 1 of the AES decryption key 0x0 Table 478 AES Decryption Key Column 0 Register Offset OX9DDDC Bits Field Type Description InitVal 31 0 AesDecKeyCol0 RW Contains Column 0 of the AES decryption key 0x0 Doc No MV S400130 00 Rev 0 5 Page 327 Copyright
356. n this register 0x0 the Data Region Low Address Register Table 335 p 245 and the Data Region High Address Register Table 336 p 245 are valid and to be used by the DMA 0 Data Region is not valid 1 Data Region is valid This bit must not be changed when the Basic DMA is active Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 241 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 331 Basic DMA Command Register Continued Offset Port 0 0x82224 Port 1 0x84224 Bits Field Type Description InitVal 9 DataRegionLast RW This bit is valid only if bit B lt DRegionValid gt is set to 1 0x0 This bit indicates if the data region described by the lt DataRegionByte Count gt field 31 16 in this register Data Region Low Address Register and Data Region High Address Register are the last data region to be trans ferred 0 Not last data region 1 Last data region to be transferred in the PRD table This bit must not be changed when the Basic DMA is active 10 ContFromPrev RW This bit indicates if the Basic DMA needs to continue from the point where it 0x0 stopped on its previous transaction or if it needs to load a new PRD table The Basic DMA ignores the value of this bit if the lt BasicDMAPauseds gt field in the Basic DMA Status Register Table 332 p 243 is cleared to 0 anda new PRD table is loaded 0 Load
357. n1 RW Window1 access control the same as WinO access control 0x3 5 4 Win2 RW Window2 access control the same as WinO access control 0x3 7 6 Win3 RW Window3 access control the same as WinO access control 0x3 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 276 88F5182 marveL Open Source Community Programmer s User Guide Table 380 Ethernet Port Access Protect EPAP Continued Offset 0x72294 Bits Field Type Description InitVal 9 8 Win4 RW Window4 access control the same as WinO access control 0x3 11 10 Wind RW Window5 access control the same as WinO access control 0x3 31 12 Reserved RO Reserved 0x0 A 9 2 Port Control Registers Table 381 Port Configuration PxC Offset 0x72400 Bits Field Type Description InitVal 0 UPM RW Unicast Promiscuous mode 0x0 0 Normal mode Unicast frames are received only if the destination address is found in the DA filter table and DA is matched against the port DA MAC Address base 1 Promiscuous mode Unicast unmatched frames are received in the Rx queue 3 1 RXQ RW Default Rx Queue 0x0 Is the Default Rx Queue for not matched Unicast frames when UPM bit is set It is also the default Rx Queue for all MAC broadcast except for ARP broadcast that has a different field for default queue if receiving them is
358. nEn RW Window Enable 0x1 1 BarMap RW Mapping To BAR 0x0 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 15 8 Attr RW Target specific attributes depending on the target interface 0x0B 31 16 Size RW Window Size OxOFFF Table 122 PCI Express Window2 Base Register Offset 0x41844 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x2000 Table 123 PCI Express Window2 Remap Register Offset 0x4184C Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 151 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 137 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 124 PCI Express Window3 Control Register Offset 0x41850 Bits Field Type Description InitVal 0 WinEn RW Window Enable 0x1 Window is disabled by default 1 BarMap RW Mapping To BAR 0x0 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window
359. nd aries the user should set El only in the last descriptor 7 1 Reserved RW Reserved 0x0 8 TxError RW Tx Resource Error 0x0 Indicates a Tx resource error event during packet transmission from the queue 15 9 Reserved RW Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 292 88F5182 marveL Open Source Community Programmer s User Guide Table 399 Port Interrupt Cause Extend ICE Continued Offset 0x72464 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 16 PhySTC RW PHY Status Change 0x0 Indicates a status change reported by the PHY connected to this port If there is any change in the link speed duplex mode or flow control capa bility as it is detected by the MDIO interface with the PHY this interrupt will be set This interrupt is set regardless of the actual changes in the status register since Auto Negotiation might be set to disabled on some of the parameters 17 Reserved RO Reserved 0x0 18 RxOVR RW Rx Overrun 0x0 Indicates an overrun event that occurred during reception of a packet 19 TxUdr RW Tx Underrun 0x0 Indicates an underrun event that occurred during transmission of packet from either queue 20 LinkChange RW Link State Change 0x0 This bit is set by upon a change
360. ne Register Map Continued Open Source Community Programmer s User Guide Register Offset Table Page XOR Engine Size Mask XESMRx XESMRO 0x60B70 XESMR 1 0x60B74 XESMR2 0x60B78 XESMR3 0x60B7C XESMR4 0x60B80 XESMRS5 0x60B84 XESMR6 0x60B88 XESMR7 0x60B8C Table 554 p 374 XOR Engine High Address Remap XEHARRx XEHARRO 0x60B9 seme 0x60B9 Se 0x60B9 Songs 0x60B9 C Table 555 p 374 XOR Engine 0 1 Address Override Control XExAOCR XEOAOCR 0x60BA 0 XE1AOCR 0x60BA 4 Table 556 p 375 XOR Engine ECC Memlnit Registers XOR Engine 0 1 Destination Pointer XExDPRO XOR Engine 0 1 Block Size XExBSR XORO 0x60BBO0 XOR1 0x60BB4 XORO 0x60BCO XOR1 0x60BC4 Table 557 p Table 558 p 377 377 XOR Engine Timer Mode Control XETMCR 0x60BD0 Table 559 p 377 XOR Engine Timer Mode Initial Value XETMIVR 0x60BD4 Table 560 p 378 XOR Engine Timer Mode Current Value XETMCVR 0x60BD8 Table 561 p 378 XOR Engine Initial Value Low XEIVRL 0x60BE0 Table 562 p 378 XOR Engine Initial Value High XEIVRH 0x60BE4 Table 563 p 379 Doc No MV S400130 00 Rev 0 5 Page 365 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary XOR Engine Registers A 16 1 XOR Engine Control Registers Table 542 XOR Engine Channel Arbiter XECHAR
361. nes 259 Offset Port 0 0x8234C Port 1 0x8434C Vendor lee UN TE E 261 Offset Port 0 0x8235C Port 1 0x8435C Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 77 Document Classification Proprietary June 25 2007 Preliminary Table 354 Table 355 Table 356 Table 357 Table 358 Table 359 Table 360 Table 361 Table 362 Table 363 List of Registers See IER E EE 262 Offset Port 0 0x82360 Port 1 0x84360 FIS Interrupt Cause Heglster e eee tet deerit vou n oN Deu qe Dae geed eere Oen NEES Ed 263 Offset Port 0 0x82364 Port 1 0x84364 FIS nterrupt Mask Register kee EE SNE een 265 Offset Port 0 0x82368 Port 1 0x84368 EDALE tero EIEI E n tre Op EP SERERE ERE MT p ETE 265 Offset Port 0 0x82370 Port 1 0x84370 FS DWilBlegister sese alos tex bet tock e bd eege ee eebe 265 Offset Port 0 0x82374 Port 1 0x84374 SIBI PARCI 266 Offset Port 0 0x82378 Port 1 0x84378 AE e EEO EE ETAT T REO REOR Ek 266 Offset Port 0 0x8237C Port 1 0x8437C FIS DWA Reglister nire REOR DOE RR Git qure i ee Pd petu 266 Offset Port 0 0x82380 Port 1 0x84380 EIS a lege ed ceni ee EE ee ri cid d 266 Offset Port 0 0x82384 Port 1 0x84384 FIS DW6 Register tse itte npe ad cene nce ER AE ei dial ero are eene dits 266 Offset Port 0 0x82388 Port 1 0x84388 A 9 Gigabit Ethernet Controller Registers eeeeeeeeeeeeeeeee
362. new PRD table 1 Continue from the PRD table associated with its previous DMA transac tion This bit must not be changed when the Basic DMA is active 15 11 Reserved RW Reserved 0x0 31 16 DataRegion RW Data Region Byte Count ByteCount 0x0 This field indicates the count of the data region in bytes Bit 0 is force to 0 There is a 64 KB maximum A value of 0 indicates 64 KB The data in the buffer must not cross the boundary of the 32 bit address space that is the 32 bit high address of all data in the buffer must be identical This field value is updated by the DMA and indicates the completion status of the DMA when the BasicDMAActive field in the Basic DMA Status Register Table 332 p 243 is cleared to 0 The host must not write to this bit when the Basic DMA is active Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 242 MARVELL e 88F5182 E Open Source Community Programmer s User Guide Table 332 Basic DMA Status Register 0x82228 Port 1 0x84228 Offset Port 0 Bits Field Type Description InitVal 0 BasicDMAAc RO This bit is set when the start bit is written to the command register tive 0x0 This bit is cleared when the last transfer for the region is performed where EOT for that region is set in the region descriptor or a complete FIS is trans ferred It is also cleared when the start b
363. nitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 140 88F5182 marveL Open Source Community Programmer s User Guide Table 133 PCI Express Default Window Control Register Offset 0x418B0 Bits Field Type Description InitVal 3 0 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x0 15 8 Attr RW Target specific attributes depending on the target interface 0x0 31 16 Reserved RSVD Reserved 0x0 Table 134 PCI Express Expansion ROM Window Control Register Offset 0x418CO Bits Field Type Description InitVal 3 0 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x1 15 8 Attr RW Target specific attributes depending on the target interface OxOF 31 16 Reserved RSVD Reserved 0x0 Table 135 PCI Express Expansion ROM Window Remap Register Offset 0x418C4 Bits Field Type Description InitVal 0 RemapEn RW Remap Enable Bit 0x0 0 Disabled Remap disabled 1 Enabled Remap enabled 15 1 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Ad
364. nity Programmer s User Guide Table 420 USB 2 0 Bridge Register Map Continued Port0 0x50300 0x503FF Port1 0xA0300 0xA03FF Register Offset Page USB 2 0 Window2 Control Register Port0 0x50340 Table 430 p 310 Port1 0xA0340 USB 2 0 Window2 Base Register Pom 0x50344 Table 431 p 311 Port1 0xA0344 USB 2 0 Window3 Control Register Pont 0x50350 Table 432 p 311 Port1 0xA0350 USB 2 0 Window3 Base Register Port0 0x50354 Table 433 p 311 Port1 0xA0354 Table 421 USB 2 0 PHY Register Map Port0 0x50400 Port1 0xA0300 Register Offset Page USB 2 0 Power Control Register Pont 0x50400 Table 434 p 312 Port1 0xA0400 A 10 1 USB 2 0 Bridge Control and Status Registers Table 422 USB 2 0 Bridge Control Register Offset Port 0x50300 Port1 0xA0300 Bits Field Type Description InitVal 3 0 Reserved RO Reserved 0x0 7 4 Reserved RW Reserved 0x0 31 8 Reserved RES Reserved 0x0 A 10 2 USB 2 0 Bridge Interrupt and Error Registers Table 423 USB 2 0 Bridge Interrupt Cause Register Offset Port0 0x50310 Port1 0xA0310 Bit Field Type Description InitVal 0 AddrDecErr RWC Address Decoding Error 0x0 Asserted upon address decoding error Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 307 Document Classification Proprietary June 25 2007 Preliminary USB 2 0 Registers
365. nity Programmer s User Guide Figure 4 Command Response Queue 32 Entries NOTE Field lt eEDMAQueLen gt 0 in EDMA Configuration Register Entry Byte Byte Number Number Number 0 Empty 0 CRPB 0 In Out Pointer 1 Empy 8 Geier CRPB 8 In 2 16 16 Empty Pointer Empty 3 Empty 24 CRPB 24 4 4 Empty 32 CRPB 32 e Empty e CRPB e CRPB e Empty e e 31 Empty 256 CRPB 256 Figure 5 Command Request Queue 128 Entries NOTE Field lt eEDMAQueLen gt 1 in EDMA Configuration Register Entry Byte Byte Number Number Number 0 Empty 0 CRQB 0 In Out 1 32 32 Pointer Empty Pointer grop In 2 64 64 Empty Pointer Empty 3 Empty 96 CRQB 96 a 4 Empty 128 4 CRQB 128 e Empty e e CRQB e e e LJ Soe e e Pn e e e 127 Empty 4096 127 CRQB 4096 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 23 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation Figure 6 Command Response Queue 128 Entries NOTE Field lt eEDMAQueLen gt 1 in EDMA Configuration Register Entry Byte Entry Byte Number Number Number Number 0 Empty 0 0 CRPB 0 In gt Out Pointer 1 Empty 8 Pointer 1 CRPB 8 In 2 16 2 16 Empty Pointer Set Empty Out 3 Empty 24 3 CRPB 24 a Pointer 4 Empty 32 4 CRPB 32 e Empty 9 pre e gre E
366. niversal Asynchronous Receiver Transmitter UART ports One of the UART ports is multiplexed on the MPP port For complete information regarding the UART refer to the Synopsis DW 16550 specification The UART is integrated into the device to support data input output operations for peripheral devices connected through a standard UART interface The UART includes the following features e Synchronous interface e FIFO mode permanently selected for transmit and receive operations e Modem control functions CTSn RSTn 12 2 UART Interface Pin Assignment The 88F5182 supports the UART interface through the UAO 1 TXD and UAO 1 RXD pins and provides modem control functions through the UAO 1 CTSn and UAO 1 RTSn pins Table 22 shows the signal names on the 88F5182 and the description of the pins Table 22 UART Pin Assignments Pin Name Type Description UAO TX o The UAO TX signals are the serial data output to the modem data set or UA TX peripheral device The UAO 1 TX signals are set high when the reset is applied UAO RX The UAO 1 RX signals are the serial data input from the modem data set or UA1 RX peripheral device UAO CTSn CLEAR TO SEND When low these pins indicate that the receiving UART is UA1 CTSn ready to receive data When the receiving UART de asserts UAO 1 CTSn high the transmitting UART should stop transmission to prevent overflow of the receiving UART buffer The UAO 1 CTSn signals are a modem status input wh
367. nnen enne 326 Offset OXODDE8 Table 474 AES Decryption Data In Out Column 0 Register ssssssssssseseee eene nennen nnne nnns 326 Offset OXODDEC Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 82 88F5182 marveL Open Source Community Programmer s User Guide Table 475 AES Decryption Key Column 3 Register rennen rennen nne 327 Offset OXODDDO Table 476 AES Decryption Key Column 2 Register nennen neret nennen 327 Offset OX9ODDD4 Table 477 AES Decryption Key Column 1 Register eee retenti nnne 327 Offset Ox9DDD8 Table 478 AES Decryption Key Column 0 Register nennen rennen neret nennen 327 Offset OXODDDC Table 479 AES Decryption Key Column 7 Register nennen ren en retrennret nennen 328 Offset Ox9DDCO Table 480 AES Decryption Key Column 6 Register nennen trennen neret nennen 328 Offset Ox9DDC4 Table 481 AES Decryption Key Column 5 Register A 328 Offset Ox9DDC8 Table 482 AES Decryption Key Column 4 Register rentre neret nennen 328 Offset Ox9DDCC Table 483 AES Decryption Command Hegister tnnt tnatttnknnatEnatEnttnnatnnennannnananaenen nnna 329 Offset Ox9DDFO Table 484 Security Accelerator Command Register c eee ee eee eeee cee eeae cess seas sees teaeseaeseaeseaeseeesaeseeseaeeeseseaeeeaees 329 Offset Ox9DE00 Table 485 Security Accelerator Descriptor Pointer Session 0 Register
368. nt Capability Version 0x2 20 19 Reserved RSVD Does not apply to PCI Express 0x0 This field must be hardwired to 0 21 DSI RO Device Specific Initialization 0x0 88F5182 does not requires device specific initialization 24 22 AuxCur RO Auxiliary Current Requirements 0x0 Doc No MV S400130 00 Rev 0 5 Page 153 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 156 PCI Express Power Management Capability Header Register Continued Offset 0x40040 Configuration 0x40 Bits Field Type Description InitVal 25 D1Sup RO This bit indicates whether the device supports D1 Power Management state 0x0 The 88F5182 does not support D1 state 26 D2Sup RO This bit indicates whether the device supports D2 Power Management state 0x0 The 88F5182 does not support D2 state 31 27 PMESup RO This field indicates whether the device supports PM Event generation 0x00 The 88F5182 does not support the PMEn pin Table 157 PCI Express Power Management Control and Status Register Offset 0x40044 Configuration 0x44 Bits Field Type Description InitVal 1 0 PMState RW Power State 0x0 This field controls the Power Management state of the 88F5182 The device supports all Power Management states 0 DO 1 D1 2 D2 3 D3 7 2 Reserved RSVD Reserved 0x0 8 PMEEn RW PM_PME Messa
369. nt transferred 1 Transfer terminated before the whole byte count was transferred 31 Own RW Ownership Bit 0x0 When running in 16M descriptor mode this bit indicates whether the descriptor is owned by the CPU 0 or the IDMA engine 1 0 CPU owned 1 IDMA engine owned 1 When running in 64K descriptor mode and when closing the descriptor the IDMA writes to bits 31 16 the left byte count to be Copyright 2007 Marvell June 25 2007 Preliminary transferred Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 354 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 526 Channel IDMA Source Address Register Offset Channel 0 0x60810 Channel 1 0x60814 Channel 2 0x60818 Channel 3 0x6081C Bits Field Type Description 31 0 SrcAdd RW Bits 31 0 of the IDMA source address 0x0 Table 527 Channel IDMA Destination Address Register Offset Channel 0 0x60820 Channel 1 0x60824 Channel 2 0x60828 Channel 3 0x6082C Bits Field Type Description 31 0 DestAdd RW Bits 31 0 of the IDMA destination address 0x0 Table 528 Channel Next Descriptor Pointer Register Offset Channel 0 0x60830 Channel 1 0x60834 Channel 2 0x60838 Channel 3 0x6083C Bits Field Type Description 31 0 NextDescPtr RW Bits 31 0 of the IDMA next descriptor address 0x0 The address must be 32 byte aligned bits 3 0 must be 0
370. nterrupt Cause IC Continued Offset 0x72460 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 16 RxErrorQueue RW Rx Resource Error in Priority Queue 1 indicates a Rx resource error event 5 0x0 in receive priority queue 5 17 RxErrorQueue RW Rx Resource Error in Priority Queue 2 indicates a Rx resource error event 6 0x0 in receive priority queue 6 18 RxErrorQueue RW Rx Resource Error in Priority Queue 3 indicates a Rx resource error event 7 0x0 in receive priority queue 7 19 TxEnd RW Tx End indicates that the Tx DMA stopped processing the queue after a stop 0x0 command DISQ or that it reached the end of the descriptor chain through a null pointer or not owned descriptor 30 20 Reserved RW Reserved 0x0 31 EtherlntSum RO Ethernet Interrupt Summary 0x0 This bit is a logical OR of the unmasked bits 30 0 in the Interrupt Cause register of the port Table 399 Port Interrupt Cause Extend ICE Offset 0x72464 NOTE Write 0 to clear interrupt bits Writing 1 does not effect the interrupt bits Bits Field Type Description InitVal 0 TxBuffer RW Tx Buffer 0x0 Indicates a Tx buffer returned to CPU ownership or that the port finished transmission of a Tx frame NOTE This bit is set upon closing any Tx descriptor which has its El bit set In order to limit the interrupts to frame rather than buffer bou
371. nterrupt Coalescing Thresh old Register is written the interrupts counter is cleared 0 Assertion of SaCrpbXDone causes an immediate assertion of lt SalntCoal gt n lt SalntCoal gt assertion is provided for every n SaCrpbXDone asser tion 31 8 Reserved RES 0x0 Reserved Doc No MV S400130 00 Rev 0 5 Page 219 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 298 SATAHC Interrupt Time Threshold Register Offset 0x80010 Bits Field Type Description InitVal 23 0 SAITMTH RW SATA Interrupt Time Threshold 0x0 This field provides a way to ensure maximum delay between lt SaCrpbXDone gt assertion and assertion of lt SalntCoal gt even if the number of lt SaCrpbXDone gt indications did not reach the lt SAICOALT gt value When SalntCoal is negated or when the SATAHC Interrupt Time Threshold Register is written the down counter is cleared A new count is enabled in the assertion of the next SaCrpbXDone indication 0 Assertion of lt SaCrpbXDone gt causes an immediate assertion of lt SalntCoal gt n Up to n internal clocks between assertion of lt SaCrpbXDone gt and assertion of lt SalntCoal gt 31 24 Reserved RES Reserved 0x0 Table 299 SATAHC Interrupt Cause Register Offset 0x80014 NOTE A corresponding cause bit is set every time that an in
372. o MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 161 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 166 PCI Express Link Control Status Register Continued Offset 0x40070 Configuration 0x70 Bits Field Type Description InitVal 2 Reserved RSVD Reserved 0x0 3 RCB RW Read Completion Boundary 0x1 0 64b 1 128B NOTE This bit has no effect on the device behavior Completions are always returned with 128B read completion boundary 4 LnkDis RW Link Disable 0x0 NOTE If configured as an Endpoint this field is reserved and has no affect Activation procedure 1 Set this bit to trigger link disable 2 Poll lt DLDown gt de assertion Table 137 PCI Express Status Register bit 0 ensure the link is disabled 3 Clear the bit to exit to detect and enable the link again 5 RetrnLnk RW Retrain Link 0x0 This bit forces the device to initiate link retraining Always returns 0 when read NOTE If configured as an Endpoint this field is reserved and has no affect 6 CmnClkCfg RW Common Clock Configuration 0x0 When set by SW this bit indicates that both devices on the link use a distrib uted common reference clock 7 ExtdSnc RW Extended Sync 0x0 When set this bit forces extended transmission of 4096 FTS ordered sets followed by a single skip ordered set in exit from LOs and extra 1024 TS1 at exit from L1 NOTE This bit is used f
373. o 0x0 0x0 17 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 351 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Table 518 Device Interface Control Continued Device Controller Registers Offset 0x104CO Bits Field Type Description InitVal 19 18 Reserved RO Must be 3 0x3 31 20 Reserved RO Reserved 0x0 Table 519 Device Interrupt Cause Offset 0x104D0 NOTE All cause bits are clear only They are set upon error condition cleared upon a value write of 0 Writing a value of 1 has no affect Bits Field Type Description InitVal 0 Reserved RWO Reserved 0x0 1 DRdyErr RWO Ready Timer Expired 0x0 31 2 Reserved RES Reserved 0x0 Table 520 Device Interrupt Mask Register Offset 0x104D4 Bits Field Type Description InitVal 0 Reserved RO Reserved 0x0 1 Mask RW Mask bit per each cause bit 0x0 0 Interrupt is masked 1 Interrupt is enabled Mask only affects the assertion of interrupt pins It does not affect the setting of bits in the Cause register 31 2 Reserved RES Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 352 e 88F5182 E MARVELL A 15 Table 521 IDMA Descriptor Register Map Open Source Community Programmer s User Guide IDM
374. o USB 2 0 ports each with an embedded USB 2 0 PHY The USB 2 0 interface can act either as a USB high speed peripheral device or as a USB host controller It is fully compliant with the Universal Serial Bus Specification Revision 2 0 USB 2 0 Each USB 2 0 interface contains a single dual role controller that can act as a host or a peripheral controller aka USB controller A bridge connects the controller to the internal Crossbar interface aka USB bridge The USB 2 0 port contains an embedded USB 2 0 PHY aka USB PHY allowing a significant saving in the number device pins and the size of the board The PHY supports both host and peripheral modes 9 1 Functional Description The USB 2 0 interface supports A single USB 2 0 port acting as either a peripheral or a host e Embedded USB 2 0 PHY USB 2 0 host controller features e EHCI compliant as a host Asa host supports direct connection to all peripheral device types Low Speed LS Full Speed FS High Speed HS USB 2 0 peripheral features e USB 2 0 compliant peripheral controller Asa peripheral connecting to all host types HS FS and hubs e Four independent endpoints support control interrupt bulk and isochronous data transfers Embedded USB 2 0 PHY features e 480 Mbps High Speed HS 12 Mbps FS FS only and LS only 1 5 Mbps serial data transmission rates e SYNC EOP generation and checking e Data and clock recovery from serial stream on the U
375. o byte swap 1 Byte swap 28 9 Reserved RES Reserved 0x0 29 WriteAllow RW This bit indicates that the host can write data to the engine 0x1 0 Write not allowed 1 Write allowed 30 AllTermination RW This bit indicates to the host that the encryption calculation has been com 0x1 pleted and that the encryption parameters may be updated and data may be written 31 Termination RO This bit is set by the engine to indicate completion of a DES calculation pro 0x1 cess Any write to the encryption engine will clear this bit A 11 2 SHA 1 and MD5 Interface Registers Table 449 SHA 1 MD5 Data In Register Offset Ox9DD38 Bits Field Type Description InitVal 31 0 Dataln WO Words of the 512 bit hash block should be written to this register 0x0 With each write the data in this field is pushed into the authentication engine s 16 word FIFO Table 450 SHA 1 MD5 Bit Count Low Register Offset 0x9DD20 Bits Field Type Description InitVal 31 0 BitCntLo WO Fourteenth word of data in the array 0x0 This register is accessed only when automatic padding is needed Table 451 SHA 1 MD5 Bit Count High Register Offset Ox9DD24 Bits Field Type Description InitVal 31 0 BitCntHi WO Fifteenth word of data in the array 0x0 This register is accessed only when automatic padding is needed Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 319 Document Cla
376. ocation within the range of 4 GB space Must be programed from LSB to MSB as sequence of 1s followed by sequence of 0s The number of 1s specifies the size of the window in 64 KB granularity e g a value of OxOOff speci fies 256x64k 16 MB Table 555 XOR Engine High Address Remap XEHARRx Offset XEHARRO 0x60B90 XEHARR1 0x60B94 XEHARR2 0x60B98 XEHARR3 0x60B9C Bit Field Type Description InitVal 31 0 Remap RW Remap Address 0x0 Specifies address bits 63 32 to be driven to the target interface Only relevant for target interfaces that supports more than 4 GB address space When using target interface that do not support more than 4GB address space this register must be cleared 1 High Address Remap Register N corresponds to Base Address register N respectively Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 374 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 556 XOR Engine 0 1 Address Override Control XEXAOCR Offset XEOAOCR 0x60BA0 XE1AOCR 0x60BA4 Bit Field Type Description InitVal 0 SAOOvrEn RW Override Source Address 0 Control 0x0 0x0 No Override 0x1 Override is enabled 2 1 SAO0OvrPtr RW Override Source Address 0 Pointer 0x0 Specifies the register from which the override parameters
377. odePoint 2 to Priority DSCP2 DSCP3 DSCP4 DSCP5 283 Offset DSCP2 0x72428 DSCP3 0x7242C DSCP4 0x72430 DSCP5 0x72434 Table 392 IP Differentiated Services CodePoint 6 to Priority DSCP6 00 eee eee e eee eeee tees teas tees teaeeeeteaeeeaees 283 Offset 0x72438 Table 393 Port Serial Control PSC ccissss ccvsctetesascostactuendsesescavusde dastanesvetdecen izes soensegesdastooanddbvsdaddeetuviesssoenasdedastibantactebed 284 Offset 0x7243C Table 394 VLAN Priority Tag to Priority VPT2P Nun 287 Offset 0x72440 Table 395 Ethernet Port Status PS EE 287 Offset 0x72444 Table 396 Transmit Queue Command TQO eese eene nnne enne tne treten reete enne neret 289 Offset 0x72448 Table 397 Maximum Transmit Unit MTU eccentric tne cute nb ager tbe Paene sean 290 Offset 0x72458 Table 398 Port Intermupt Cause IG iiie eiecti rtr ete eri eee eerte teste et EENS EES Stra Zen 290 Offset 0x72460 Table 399 Port Interrupt Cause Extend ICE seen ennt rentre enne 292 Offset 0x72464 Table 400 Port Interrupt Mask PM error tenere tercer cused aree reir rer e eee Ye Ee ee ke tees 294 Offset 0x72468 Table 401 Port Extend Interrupt Mask PEIM sssssssssseseseesenneeneenneen nennen rennen ret rennen rrenretnnen 294 Offset 0x7246C Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 79 Document Classifica
378. ogrammer s User Guide Section 4 PCI Express Interface The PCI Express interface is a x1 Root Complex This interface has the following features PCI Express Base 1 0a compatible Root Complex port Can be configured also as an Endpoint port Embedded PCI Express PHY based on proven Marvell SERDES technology x1 link width 2 5 GHz signalling Lane polarity inversion support Replay buffer Maximum payload size of 128 bytes Single Virtual Channel VC 0 Ingress and egress flow control Extended Tag support Interrupt emulation message support Power management LOs Rx and SW L1 support Advanced Error Reporting AER capability support Single function device configuration header Message Signaled Interrupts MSI capability support as an Endpoint Power Management PM capability support as an Endpoint Expansion ROM support Programmable address map Doc No MV S400130 00 Rev 0 5 Page 17 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary PCI Interface Functional Description Section 5 PCI Interface 5 1 Functional Description The PCI interface runs up to 66 MHz It supports a 32 bit bus operation It also supports 64 bit addressing It can act as host bridge translating CPU transactions to PCI memory I O and configuration cycles It can also act as PCI Endpoint responding to host configuration cycles and having access to all of the chip internal registers It also
379. om Read command to de asserting of the internal D 0x6 ODT signal to the DDR SDRAM controller I O buffer The same as topr orr 31 20 Reserved RO Reserved 0x0 Table 90 DDR2 SDRAM Timing High Register Offset 0x0147C Bits Field Type Description InitVal 3 0 topT ON WR RW The number of cycles from Write command to the assertion of M ODT 0x0 signal Value 0 means one cycle before write command value of 1 means the same cycle as write command value 2 means one cycle latter and so on Value depends on DDR SDRAM CL and taonp timing parameters For CL 3 and tAOND 2 set loODT ON WR to 0 7 4 lopr OFF WR RW The number of cycles from Write command to de asserting M ODT signal 0x3 Value depends on DDR SDRAM CL and taorp timing parameters For CL 3 and taorp 2 5 set topr opt wn to 0x3 11 8 topt on crt w RW The number of cycles from Write command to the assertion of the internal R 0x3 ODT signal to the DDR SDRAM controller UO buffer Same as tODT_ON_CTL_WR 15 12 topr orF en RW The number of cycles from Write command to de asserting of the internal WR 0x6 ODT signal to the DDR SDRAM controller UO buffer Same as lopr oFF CT WR 31 16 Reserved RO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 116 88F5182 marveL Open Source Community Programmer s User Guide Table 91 DDR
380. ommand Response Queue 128 Entries on page 24 Each 8 byte command response entry consists of command ID response flags and a timestamp see Table 16 EDMA CRPB Data Structure Map on page 31 The CRPB data structure described in Table 2 EDMA CRQB Data Structure Map on page 25 is written by the EDMA 7 2 3 5 EDMA Command Response Block CRPB Data Table 16 provides a map of the EDMA command response block data structure tables Table 16 EDMA CRPB Data Structure Map Register Offset Table Page CRPB ID Register 0x00 Table 17 p 31 CRPB Response Flags Register 0x02 Table 18 p 32 CRPB Time Stamp Register 0x04 Table 19 p 32 Table 17 CRPB ID Register Offset 0x00 Bits Field Description 6 0 cHostQueTag CRPB ID In queued DMA commands these bits are used as a tag This field contains the host identification of the command These bits are copied from field cHostQueTag of Table 5 CRQB DW2 Control Flags on page 26 15 7 Reserved Reserved Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 31 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation Table 18 CRPB Response Flags Register Offset 0x02 Bits Field Description 6 0 cEdmasSts CRPB EDMA Status This field contains a copy of the EDMA Interrupt Error Cause Register see Table 313 on page 230 bits 6
381. ommand corresponding to the host command ID When set the command was sent to the device but it has not yet completed and updated in the host response queue in system memory CRPB EDMA sets the corresponding bit when sent a new command EDMA clears the corresponding bit when the command is completed and updated in the host response queue in system memory CRPB Table 328 EDMA NCQ1 Done TCQ1 Outstanding Status Register Offset Port 0 0x82098 Port 1 0x84098 NOTE When the EDMA is disabled the fields in this register are Read Only Bits Field Type Description InitVal 31 0 NCQDone RW See Table 327 EDMA NCQO Done TCQ0 Outstanding Status Register TCQOut 0x0 on page 240 stand 63 32 Table 329 EDMA NCQ2 Done TCQ2 Outstanding Status Register Offset Port 0 0x8209C Port 1 0x8409C NOTE When the EDMA is disabled the fields in this register are Read Only Bits Field Type Description InitVal 31 0 NCQ RW See Table 327 EDMA NCQO Done TCQ0 Outstanding Status Register Done 95 64 0x0 on page 240 TCQOutstand Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 240 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 330 EDMA NCQ3 Done TCQ3 Outstanding Status Register Offset Port 0 0x820A0 Port 1 0x840A0 NOTE When the EDMA is disabled the fie
382. on InitVal 31 0 Various RES Same as in PCI Access Control Size 0 RW 0x0 Table 234 PCI Access Control Base 4 Low Offset Ox31E40 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 Low RES 0x0 Table 235 PCI Access Control Base 4 High Offset Ox31E44 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 High 0x0 Table 236 PCI Access Control Size 4 Offset 0x31E48 Bits Field Type Description InitVal 31 0 Various RES Same as in PCI Access Control Size 0 RW 0x0 Doc No MV S400130 00 Rev 0 5 Page 191 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary PCI Interface Registers Table 237 PCI Access Control Base 5 Low Offset 0x31E50 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 Low RES 0x0 Table 238 PCI Access Control Base 5 High Offset Ox31E54 Bits Field Type Description InitVal 31 0 Various RW Same as in Access Control Base 0 High 0x0 Table 239 PCI Access Control Size 5 Offset 0x31E58 Bits Field Type Description InitVal 31 0 Various RES Same as in PCI Access Control Size 0 RW 0x0 A 7 3 PCI Configuration Access Registers S Note PCI Configuration Address PC
383. or Table Base High Address 0x04 Table 4 p 26 CRQB DW2 Control Flags 0x08 Table 5 p 26 CRQB DW3 Data Region Byte Count 0x0C Table 6 p 27 CRQB DW4 ATA Command 0x10 Table 7 p 27 CRQB DW5 ATA Command 0x14 Table 8 p 27 CRQB DW6 ATA Command 0x18 Table 9 p 28 CRQB DW7 ATA Command 0x1C Table 10 p 28 Table 3 _CRQB DWO cPRD Descriptor Table Base Low Address Offset 0x00 Bits Field Description 31 0 cPRD 31 0 CRQB ePRD When cPRDModes is cleared to 0 The CPU at initialization should construct a ePRD table in memory This table contains consecutive descriptors that describe the data buffers allocated in memory for this command This DWORD contains bit 31 4 of the physical starting address of this table Bits 3 0 must be 0x0 When cPRDModes is set to 1 This DWORD contains bits 31 1 of the physical starting address of a data region in system memory Bit 0 must be 0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 25 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation Table 4 _CRQB DW1 cPRD Descriptor Table Base High Address Offset 0x04 Bits Field Description 31 0 cPRD 63 32 CRQB ePRD When cPRDModes is cleared to 0 This DWORD contains bits 63 32 of the physical starting address of a PRD table in System memory When cPRDModes is set to 1 This DWORD contains bits 63 32 of the physica
384. or count down 0x0 Controls the time period between executions of subsequent sections ECC cleanup It specifies the number of Tclk cycles between subsequent sec tions cleanup If timer expires before current section cleanup has ended it will be disregarded NOTE Valid only if one of the XOR Engine channels is in ECC timer mode Table 561 XOR Engine Timer Mode Current Value XETMCVR Offset Ox60BD8 Bit Field Type Description InitVal 31 0 TimerCrntVal RO ECC timer mode Current value 0x0 NOTE Valid only if one of the XOR Engine channels is in ECC timer mode Table 562 XOR Engine Initial Value Low XEIVRL Offset Ox60BEO Bit Field Type Description InitVal 31 0 InitValL RW LSB of Initial Value to be written cyclically to target block in Memlnit mode 0x0 Mapped to bits 31 00 of initial value This register is shared between the two XOR Engine channels The XOR Engine will compose a 64 bit Initial Value out of InitValL and InitValH registers and write it cyclically to the target block Target block can be of any alignment NOTE Valid only on Memlnit modes 1 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 378 88F5182 marveL Open Source Community Programmer s User Guide Table 563 XOR Engine Initial Value High XEIVRH Offset Ox60BE4 Bit Field
385. or device controller pin assignment S Note All output signals are driven with the rising edge of TCLK and all inputs are sampled with the rising edge of TCLK 13 2 Device Interface Pin Assignment Table 23 provides a list of the Device interface pins and describes their function Table 23 Device Controller Pin Assignments Pin Name Type Description DEV CEn 2 0 O Device Bus Chip Enable correspond to bank 2 0 DEV BootCEn O Device Bus Chip Enable correspond to Boot Bank DEV OEn O Device Bus Output Enable DEV WEn 1 0 O Device Bus Write Enable DEV_ALE 1 0 O Device Bus Address Latch Enable correspond to ALE 0 DEN D 8 0 t s O Device Bus Multiplexed Address Data bus DEV_D 15 9 t s O Device Bus Data bus DEV_A 2 0 O Device Bus Address DEV_READY O Device Ready DEV_BURSTn DEV_LASTn O Device Burst Device last Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 47 Document Classification Proprietary June 25 2007 Preliminary Device Controller Interface Device Interface Block Diagram 13 3 Device Interface Block Diagram Figure 8 provides a diagram of the Device block Figure 8 Device Block Diagram Example DEV ALE 0 A 26 15 Up to 512 MByte Device DEV ALE 1 DEV A 2 0 DEV D 15 9 DEV D 8 DEV D T7 0 DEV OEn DEV WEn 0 WEn 0 DEV WEn 1 WEn 1 DEV CEn CEn S Note In the figures that follow the signal names appe
386. or half duplex operation mode e RGMII mode non delay Transmit functions Zero padding for short frames less than 64 Bytes Long frames transmission limited only by external memory size Checksum on transmit frames for frames up to 1 5 KB Programmable values for Inter Packet Gap and Blinder timers CRC generation programmable per frame Backoff algorithm execution Error reporting Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 34 88F5182 marveL Open Source Community Programmer s User Guide e Receive functions Address filtering modes 16 Unicast Unicast promiscuous mode reception receptions of Unicast frames even those not matched in the DA filter 256 IP Multicast 256 Multicast Broadcast Broadcast reject mode Automatic discard of error frames smaller than the programmable minimum frame size Reception of long frames Programmable legal frame size is up to 9700 bytes Note Frames larger than the limit are actually received however they are mark in the descriptor as Oversize errors CRC checking Error reporting Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 35 Document Classification Proprietary June 25 2007 Preliminary USB 2 0 Interface Functional Description Section 9 USB 2 0 Interface The 88F5182 supports tw
387. or is not implemented on the card module 1 Implemented Attention indicator is implemented on the card module Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 157 Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 163 PCI Express Device Capabilities Register Continued Offset 0x40064 Configuration 0x64 Bits Field Type Description InitVal 14 PwrlndPrs RO Power Indicator Present 0x0 0 Not Implemented Power indicator is not implemented on the card module 1 Implemented Power indicator is implemented on the card module 17 15 Reserved RSVD Reserved 0x0 25 18 CapSPLVal RO Captured Slot Power Limit Value 0x0 27 26 CapSPLScl RO Captured Slot Power Limit Scale 0x0 31 28 Reserved RSVD Reserved 0x0 Table 164 PCI Express Device Control Status Register Offset 0x40068 Configuration 0x68 Bits Field Type Description InitVal 0 CorErrRepEn RW Correctable Error Reporting Enable 0x0 0 Disabled ERR COR error messages are masked Status bit is not masked 1 Enabled ERR COR error messages enabled In Root Complex mode reporting of errors is internal to status registers only An external error message must not be generated therefore always write 0x0 NOTE ERR_NONFATAL error messages are still enabled when this field is 0 if the lt SErrEn gt bit in the Table 143
388. or test and measurement 15 8 Reserved RSVD Reserved 0x0 19 16 LnkSpd RO Link Speed 0x1 This field indicates the negotiated link speed The current value indicates 2 5 Gbps 25 20 NegLnkWdth RO Negotiated Link Width This field indicates the negotiated link width 12X1 Other Reserved This field is initialized by the hardware NOTE This field is only valid once the link is up 26 Reserved RO Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 162 88F5182 marveL Open Source Community Programmer s User Guide Table 166 PCI Express Link Control Status Register Continued Offset 0x40070 Configuration 0x70 Bits Field Type Description InitVal 27 LnkTrn RO Link Training 0x0 This bit indicates that link training is in progress or that 1b was written to the Retrain Link bit but Link training has not yet begun This bit is cleared once link training is complete 28 SItCIkCfg RO Slot Clock Configuration 0x1 0 Independent The 88F5182 uses an independent clock irrespective of the presence of a reference clock on the connector 1 Reference The 88F5182 uses the reference clock that the platform provides 31 29 Reserved RSVD Reserved 0x0 Table 167 PCI Express Advanced Error Report Header Register Offset 0x40100 Configuration 0x100 Bits Fie
389. ording to SectionSizeCtrl value and the ECC timer will be enabled Upon expiration of the timer one section will be processed When the timer expires in the second time the next sec tion will be processed and so on until all the target block is processed The XOR Engine will than start cleaning the target block all over again In order to stop the operation XEstop must be set 1 Timer Mode Enabled 0 Timer Mode Disabled the ECC timer will be activated upon setting XEstart of a channel which is in ECC timer operation mode NOTE Valid only on ECC mode 7 1 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Page 377 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary XOR Engine Registers Table 559 XOR Engine Timer Mode Control XETMCR Continued Offset Ox60BDO Bit Field Type Description InitVal 12 8 SectionSizeCtrl RW Section size control 0x0 Specifies the section size for ECC timer mode operation actual section size in bytes 2 SectionSizeCtrl Minimum Value 7 section size of 128B Maximum Value 31 section size of 2GB Must be less than Block Size XEBSR Reserved values 0 6 NOTE Valid only on ECC timer mode 31 13 Reserved RO Reserved 0x0 Table 560 XOR Engine Timer Mode Initial Value XETMIVR Offset 0x60BD4 Bit Field Type Description InitVal 31 0 TimerlnitVal RW ECC timer mode initial value f
390. ort includes an IEEE 802 3 compliant 10 100 1000 Mbps MAC that supports GMII MII and RGMII interfaces with an external PHY SERDES device The port speed duplex and 802 3 flow control can be auto negotiated according to IEEE standards 802 3u and 802 3x Backpressure is supported for half duplex mode when operating at 10 100 Mb speeds Each port supports MIB counters The receive port includes a dedicated MAC DA Destination Address with address filtering of up to 16 Unicast MAC addresses 256 IP Multicast addresses and 256 Multicast Broadcast address The receive port may also detect Layer2 frame type encapsulation as well as common Layer3 and Layer4 protocols IP checksum Transmission Control Protocol TCP checksum and User Datagram Protocol UDP checksum are always checked on received traffic and may be generated for transmitted traffic This capability increases performance significantly by off loading these operations from the CPU Jumbo frames are also supported Each port includes eight dedicated receive DMA queues and one dedicated transmit DMA queue plus two dedicated DMA engines one for receive and one for transmit that operate concurrently Each queue is managed by buffer descriptors that are chained together and managed by the software Memory space may be mapped using configurable address windows to fetch write buffer data and descriptors to any of the other interfaces of the device Queue classification on received traffic
391. ose condition can be tested by the host processor or by the UART when in Autoflow mode UAO RTSn REQUEST TO SEND When low these pins informs the remote device that the UA1 RTSn UART is ready to receive data S Note For more information refer to Section A 13 UART Interface Registers on page 340 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 46 e 88F5182 E marveL Open Source Community Programmer s User Guide Section 13 Device Controller Interface 13 1 Functional Description The 88F5182 Device controller interface supports up to four banks of devices Each bank supports up to 512 MBytes of address space Each bank has its own timing parameters register Bank width can be programmed to 8 or 16 bits Bank timing parameters can be programmed to support different device types e g sync burst SRAM Flash ROM I O Controllers The four chip selects are typically separated into three individual chip selects and one chip select for a boot device The boot device bank is the same as any of the other banks except that the core boots from the boot device and its default width is sampled at reset The device controller multiplexes the address and data buses The interface latches the address into latches to support up to 512 MBytes of address space The interface supports any size access up to 128 bytes See Table 23 f
392. oses 0 No loopback 1 Loopback 31 5 Reserved RSVD Reserved Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 345 Document Classification Proprietary June 25 2007 Preliminary UART Interface Registers Table 509 Line Status Register LSR Offset UART 0 0x12014 UART 1 0x12114 Bits Field Type Description InitVal 0 DataRxStat RO Receive buffer status 0x0 0 No characters in the receive buffer or FIFO 1 Receive buffer or FIFO contains at least one character A read operation of the Receiver Buffer Register clears this bit This bit is cleared when the Receive Buffer Register RBR Register Table 500 p 341 is read 1 OverRunErr ROC Overrun Error 0x0 0 No overrun 1 Overrun error has occurred 2 ParErr ROC Parity Error 0x0 This bit indicates a parity error in the receiver if the lt PEN gt bit in the Line Control Register LCR Register Table 507 p 344 is set In the FIFO mode since the parity error is associated with a character received it is revealed when the character with the bad parity comes to the head of the FIFO 3 FrameErr ROC Frame Error 0x0 The FE bit flags a framing error in the receiver A framing error occurs when the receiver does not detect a valid STOP bit in the received data In the FIFO mode since the framing error is associated with a character received it is revealed when the character with the framing error comes to the head of the FIFO
393. ot driven to the target interface 3 2 Win1 RW Window1 access control 0x3 5 4 Win2 RW Window2 access control 0x3 7 6 Win3 RW Window3 access control 0x3 9 8 Win4 RW Window4 access control 0x3 11 10 Win5 RW Window5 access control 0x3 13 12 Win6 RW Window6 access control 0x3 15 14 Win7 RW Window7 access control 0x3 31 16 Reserved RO Read only 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 357 Document Classification Proprietary June 25 2007 Preliminary IDMA Controller Interface Registers A 15 3 IDMA Channel Control Registers Table 535 Channel Control Low Register Offset Channel 0 0x60840 Channel 1 0x60844 Channel 2 0x60848 Channel 3 0x6084C Bits Field Type Description 2 0 DstBurstLimit RW 000 8 Bytes 0x0 001 16 Bytes 010 Reserved 011 32 Bytes 100 128 Bytes 101 Reserved 110 Reserved 111 64 Bytes 3 SrcHold RW Source Hold 0x0 0 Increment source address 1 Hold in the same value 4 Reserved RW Reserved 0x0 5 DestHold RW Destination Hold 0x0 0 Increment destination address 1 Hold in the same value 8 6 SrcBurstLimit RW Burst Limit in Each IDMA Access 0x0 000 8 Bytes 001 16 Bytes 010 Reserved 011 32 Bytes 100 128 Bytes 101 Reserved 110 Reserved 111 64 Bytes 9 ChainMode RW Chained Mode 0x0 0 Chained mode 1 Non Chained mode 10 IntMode RW Interrupt Mode 0x0 0 Interrupt asserted every time the IDMA byte count
394. plex Gigabit Ethernet GbE port It can be configured to a 10 100 Mbps MII interface or a 10 100 1000 Mbps RGMII GMII interface This is useful for higher throughput interfacing to the Marvell Fast Ethernet switches The 88F5182 integrates two USB 2 0 high speed ports each with an embedded PHY They can be configured to either host ports or peripheral ports The 88F5182 integrates a Cryptographic Engine and Security Accelerator to support data encryption and authentication It also contains a dedicated DMA to feed data from the local SRAM into the arithmetic hardware The 88F5182 includes a single Two Wire Serial Interface TWSI port The UART Interface consists of two UART ports The 88F5182 includes a 16 bit Device interface The 88F5182 incorporates four IDMA engines Each IDMA engine has the capability to transfer data between any interface The 88F5182 incorporates two additional XOR DMA engines useful for Redundant Array of Independent Disks RAID applications Each XOR DMA runs on a linked list of descriptors It can read from up to eight sources perform bitwise XOR between the eight sources and writes the result to a destination The sources and destination can reside in any of the 88F5182 interfaces The 88F5182 contains 26 bit general purpose lOs The 88F5182 includes an advanced interrupt controller which handles interrupts from all of the various sources and forwards them to the Marvell processor core When working i
395. ports four cache line size values 4 words 16 bytes 8 words 32 bytes 16 words 64 bytes and 32 words 128 bytes Setting the cache line size to any other value is treated as if cache line size is set to 0 A Dual Address Cycles DAC transaction is carried out if the requested address is beyond 4 GByte address bits 63 32 are not 0 The 88F5182 PCI master performs configuration read write cycles Interrupt Acknowledge cycles or Special cycles using the Config Address and Config Data registers For full details on generating these transactions The master consists of 512 bytes of posted write data buffer and 512 bytes of read buffer It can absorb up to four 128 byte write transactions plus four 128 byte read transactions The PCI master posted write buffer in the 88F5182 permits the initiator to complete the write even if the PCI bus is busy The posted data is written to the target PCI device when the PCI bus becomes available The read buffer absorbs the incoming data from PCI Read and Write buffers implementation guarantees that there are no wait states inserted by the master S Note PCI IRDYn is never de asserted in the middle of a transaction 5 3 PCI Target Operation The 88F5182 responds to the following PCI cycles as a target device e Memory Read e Memory Write e Memory Read Line e Memory Read Multiple e Memory Write and Invalidate e O Read e WO Write Configuration Read Configuration Write e
396. ption 38 Section 11 Two Wire Serial Interface TWSI eeeeecceeeeeeeeeeeenee 40 11 4 Functional eet LTE 40 DI TWSI Master Operation zcs iet eter e ER He eere E M C E RECO RR Sue ERU c 43 11 8 TWSI Slave Operation 44 Section 12 DART Interface iiio cete etur in esi elec ease tal 46 12 1 Functional Descriptors nennen nnne enne en nennen sin nn nnne sienten nens 46 12 2 UART Interface Pin Aesionmenmt A 46 Section 13 Device Controller Interface eese eene nnn 47 13 1 Functional RL e Le EE 47 13 2 Device Interface Pin Aesionment AAA 47 13 3 Device Interface Block Diagram sssseseeeenenneeenee eene nennen nennen 48 13 4 Address Multiplexirig hee tere eebe p ette tees 49 13 5 NAND Flash Controller Implementation 49 Section 14 IDMA Gontroll r ien ee t entcdt eiusd ee 50 144 Functional et Le 50 14 2 DMA Descriptors giereg t diese EES e tete ne eo ere de EE deeper ue te eet de e de eae 50 Section 15 XOR e UO 52 15 1 Theory f Operation eta el ee ai a ae derer 52 15 27 Descriptor EE EE 53 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 4 MSE sss marveL Open Source Community Programmer s User Guide Section 16 General Purpose I O Port Interface ceeeeeeeeeeeeeeees 58 Section 17 Interrupt Controlle
397. ption InitVal 4 0 PhyAd 0 RW PHY device address 0x8 14 5 Reserved RW Reserved 0x0 31 15 Reserved RO Reserved 0x0 Table 366 SMI Offset 0x72004 Bits Field Type Description InitVal 15 0 Data RW Management for SMI READ operation Two transactions are required 1 N A management write to the SMI register where lt Opcode gt 1 lt PhyAd gt lt RegAd gt with the Data having any value 2 management read from the SMI register When reading back the SMI register the Data is the addressed PHY register contents if the ReadValid bit 27 is 1 The Data remains unde fined as long as ReadValid is 0 Management for SMI WRITE operation One Management transaction is required Management write to the SMI register with lt Opcode gt 0 lt PhyAd gt lt RegAd gt with the Data to be written to the addressed PHY regis ter 20 16 PhyAd RW PHY device address 0x0 25 21 RegAd RW PHY device register address 0x0 26 Opcode RW 0 Write 0x1 1 Read 27 ReadValid RO 1 Indicates that the Read operation for the addressed RegAd register has 0x0 completed and that the data is valid on the lt Data gt field 28 Busy RO 1 Indicates that an operation is in progress and that the CPU should not 0x0 write to the SMI register during this time 31 29 N A RW These bits should be driven 0x0 during any write to the SMI register 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25
398. queues and a single transmit queue Receive Transmit buffer management is by buffer descriptor linked lists Buffers and descriptors can reside throughout the entire device memory space A Transmit Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 33 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Interface Port Features buffer of any byte alignment and any size above 8 bytes is supported The Receive Buffers must be 64 bit aligned The core frequency assumption is a minimum of 83 MHz in gigabit operation Frame type encapsulation detection is available on Layer 2 for Bridge Protocol Data Unit BPDU VLAN programmable VLAN ethertype Ethernet v2 LLC SNAP on Layer 3 for IPv4 according to Ethertype other no MPLS or IPv6 detection and on Layer 4 only over IPv4 for Transmission Control Protocol TCP User Datagram Protocol UDP and other Frame enqueueing is according to DA VLAN 802 1p IP ToS using the highest priority counts Frame enqueueing is OR captured according to the protocol type for TCP UDP ARP or BPDU Frames smaller than the programmable minimum frame size are automatically discarded Reception and transmission of long frames up to 9700 bytes are supported The frame type encapsulation method errors and checksums are reported in the buffer descriptor Automatic IP header 32 bit alignment is done in memory by adding 2 bytes at the beginning of each frame Th
399. r ccr rnt tnu ntn nnnc rini tn nnnm nnmnnn 59 17 4 Functional D SCriptlOn E 59 17 2 Local Interrupt Cause and Mask Registers nennen 59 17 3 Main Interrupt Cause and Mask Registers nennen nnne 60 1724A Doorbell Interr pt ice eene edet cette delenit ie Lope LEER EE eee 60 17 5 88F5182 Interrupt Controller Gcheme eene nnns 61 Section 18 TNS me anatia 62 18 1 Functional Description tette naa eint C E ede added ed ee eine 62 18 2 32 bit wide Timets ehe T RR FERRE YERRE RR REN ERR Rep eges 62 18 3 Watchdog RU EE 62 Appendix A 88F5182 Register Sel ecce ernannt inei in nuni nona ERR nnmnnn mnnn 88 Appendix B REVISION HISIUOFV csin icio roii nada ipit i MAE ERE ENEE GEREENT FLU AKA 388 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 5 Document Classification Proprietary June 25 2007 Preliminary List of Tables List of Tables Table 1 88F5182 Default Address Map cceccccesececeeececeeceeseseneneseeeeeneneesneceeeseneeseseeeseseaeseseseneeeeeensaeeseeeeess 14 Table 2 EDMA CRQB Data Structure Map AE 25 Table 3 CRQB DWO cPRD Descriptor Table Base Low Address 25 Table 4 CRQB DW1 cPRD Descriptor Table Base High Address 26 Table 5 CRQB DW2 Conttol Flags eege tee tee cit E EE Let UD GELT Cen alia t 26 Table 6 CRQB DW3 Data Region Byte Count sss 27 Table 7 CRQB DW4 ATA Command eiii aet
400. r write that was initiated by the CPU writing to the SMI register 5 Count_wa RW Counters Wrap Around Indication 0x0 MIB Counter WrapAround Interrupt is set if one of the MIB counters wrapped around passed 32 bits 6 Reserved RO Reserved 0x0 7 Internal RW Internal Address Error is set when there is an access to an illegal offset of AddrError 0x0 the internal registers When set the Internal Address Error register locks the address that caused the error 8 Reserved RO Reserved 0x0 9 Porto DPErr RW Port Internal data path parity error detected 0x0 11 10 Reserved RW Reserved 0x0 12 TopDPErr RW G Top Internal data path parity error detected 0x0 31 13 Reserved RO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 272 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 371 Ethernet Unit Interrupt Mask EUIM Offset 0x72084 Bits Field Type Description InitVal 12 0 Various RW Mask bits for Unit Interrupt Cause register 0x0 0 Mask 1 Do not mask 31 13 Reserved RO Reserved 0x0 Table 372 Ethernet Unit Error Address EUEA Offset 0x72094 Bits Field Type Description InitVal 31 0 Error Address RO Locks the address if there is an address violation of the DMA such as 0x0 Multiple Address window hit No Hit Access Violations The Address is lo
401. ransmitted to the PCI E port Write 1 to clear 26 25 Reserved RSVD Does not apply to PCI Express 0x0 These bits are hardwired to 0 27 STarAbort SC Signaled Target Abort 0x0 This bit is set when the 88F5182 as a completer target completes a trans action as a Completer Abort Write 1 to clear 28 RTAbort SC Received Target Abort 0x0 This bit is set when the 88F5182 as a requester master receives a com pletion with the status Completer Abort Write 1 to clear 29 RMAbort SC Received Master Abort 0x0 This bit is set when the 88F5182 as a requester master receives a com pletion with the status Unsupported Request Write 1 to clear 30 SSysErr SC Signalled System Error 0x0 This bit is set when the 88F5182 sends an ERR FATAL or ERR NONFATAL message This bit is not set if the lt SErrEn gt field in this register is de asserted Write 1 to clear Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 148 88F5182 marveL Open Source Community Programmer s User Guide Table 143 PCI Express Command and Status Register Continued Offset 0x40004 Configuration 0x4 register Write 1 to clear Bits Field Type Description InitVal 31 DetParErr SC Detected Parity Error 0x0 This bit is set when the 88F5182 receives a poisoned TLP NOTE The bit is set regardless of th
402. right 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 92 e 88F5182 E MARVELL Open Source Community Programmer s User Guide Table 38 Window1 Control Register Continued Offset 0x20010 Bits Field Type Description InitVal 15 8 Attr RW Target specific attributes depending on the target interface 0x59 See the Window0 Control Register Table 34 p 91 31 16 Size RW Window Size Ox1FFF See the Window0 Control Register Table 34 p 91 Table 39 Window1 Base Register Offset 0x20014 NOTE If the remap function for this register is not used the Remap field in the Window1 Remap Low Register must be set to same value as the Base field in this register Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0xA000 See the Window0 Base Register Table 40 Window1 Remap Low Register Offset 0x20018 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0xA000 See the Window0 Remap Low Register Table 41 Window1 Remap High Register Offset 0x2001C Bits Field Type Description InitVal 31 0 RemapHigh RW Remap Address 0x0 See the Window0 Remap High Register Doc No MV S400130 00 Rev 0 5 Page 93 Copyright 2007 Marvell Document Classification
403. ription InitVal 1 0 RxMFS 1 0 RO Read Only 0x0 6 2 RxMFS 6 2 RW Contains the Receive Minimal Frame Size in bytes 0x10 Valid Range of RxMFS 6 2 is OxXA 0x10 Corre RxMFS 40 44 48 52 56 60 64 bytes spond ing to 64 bytes 31 7 Reserved RO Read Only 0x0 Table 405 Port Rx Discard Frame Counter PxDFC Offset 0x72484 Bits Field Type Description InitVal 31 0 Rx RO Number of frames that were discarded because of a resource error Discard 31 0 0x0 This register is reset every time the CPU reads from it Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 295 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 406 Port Overrun Frame Counter POFC Offset 0x72488 Bits Field Type Description InitVal 31 0 Rx RO Number of frames that were received and overrun Overrun 31 0 0x0 This register is reset every time the CPU reads from it Table 407 Port Internal Address Error EUIAE Offset 0x72494 Bits Field Type Description InitVal 8 0 InternalAddress RO Locks the relevant internal address bits bit 12 and bits 9 2 if there is an 0x0 address violation of unmapped access to the port registers The Address is locked until the register is read 31 9 Reserved RO Reserved 0x0 Table 408 Ethernet Current Receive Descriptor Pointers CRDP Offset
404. rnal completer initiates a split completion and detects an error the unit samples and locks the split completion address and not the original address Table 247 PCI Error Address High Offset 0x31D44 Bits Field Type Description InitVal 31 0 ErrAddr RO PCI address bits 63 32 are latched as a result of an error latched in the 0x0 Interrupt Cause Register Upon address latched no new address can be registered due to another error until the Address Low register is being read An error which is masked in the Interrupt Mask Register will not set this register NOTE Applicable only when running DAC cycle Table 248 PCI Error Command Offset 0x31D50 Bits Field Type Description InitVal 3 0 ErrCmd RO PCI Command bits 3 0 are latched as a result of an error latched in the 0x0 Interrupt Cause Register When latched no new command can be registered due to another error until the Address Low register is being read An error which is masked in the Interrupt Mask Register will not set this register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 197 Document Classification Proprietary June 25 2007 Preliminary PCI Interface Registers Table 248 PCI Error Command Continued Offset 0x31D50 Bits Field Type Description InitVal 4 DAC RO If set to 1 indicates that the transaction latched in the error registers is a
405. rnet Controller Registers N Notes e If the Ethernet Unit Control EUC register s Pot PW bits 18 is set to 0 deactivated the specific port s registers can not be accessed An attempt to read from a deactivated port s registers will cause a system hang Allinterrupt cause registers are write 0 to clear meaning that writing 1 value has no effect while writing O resets the relevant bit in the register Table 364 Ethernet Unit Global Registers Map Description Offset Table Page Ethernet Unit Global Registers PHY Address 0x72000 Table 365 p 270 SMI 0x72004 Table 366 p 270 Ethernet Unit Default Address EUDA 0x72008 Table 367 p 271 Ethernet Unit Default ID EUDID 0x7200C Table 368 p 271 Ethernet Unit Reserved EU 0x72014 Table 369 p 271 Ethernet Unit Interrupt Cause EUIC 0x72080 Table 370 p 272 Ethernet Unit Interrupt Mask EUIM 0x72084 Table 371 p 273 Ethernet Unit Error Address EUEA 0x72094 Table 372 p 273 Ethernet Unit Internal Address Error EUIAE 0x72098 Table 373 p 273 Ethernet Unit Port Pads Calibration EUPCR 0x720A0 Table 374 p 273 Ethernet Unit Control EUC 0x720B0 Table 375 p 274 Base Address BAO 0x72200 Table 376 p 275 BA1 0x72208 BA2 0x72210 BAS 0x72218 BA4 0x72220 BAR 0x72228 Size S SRO 0x72204 Table 377 p 275 SR1 0x7220C SR2 0x72214 SR3 0x7221C SR4 0x72224 SR5 0x7222C High Address Remap HA HARRO 0x72280 Table 378 p 276 HAR
406. rrupting device downstream Relevant for Root Complex only 25 26 RcvIntB RevintC RO 0x0 RO 0x0 IntB status Reflects IntB Interrupt message emulation status Set when IntB_Assert message received Cleared when IntB_Deassert message received or upon link failure sce nario Dl_down NOTE This bit is not RWOC as some other bits in this register since it is cleared by the interrupting device downstream Relevant for Root Complex only IntC status Reflects IntC Interrupt message emulation status Set when Int Assert message received Cleared when IntC_Deassert message received or upon link failure sce nario DI down NOTE This bit is not RWOC as some other bits in this register since it is cleared by the interrupting device downstream Relevant for Root Complex only Doc No MV S400130 00 Rev 0 5 Page 133 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary PCI Express Interface Registers Table 113 PCI Express Interrupt Cause Continued Offset 0x41900 NOTE AN bits except bits 27 24 are Read Write Clear only A cause bit sets upon an event occurrence A write of 0 clears the bit A write of 1 has no affect Bits 24 27 are set and cleared upon reception of interrupt emulation messages Bits Field Type Description InitVal 27 RevintD RO IntDn status 0x0 Reflects IntD Interrupt message emulation status Set when In
407. rts the PCI_PMEn Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 204 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 264 PCI Power Management Control and Status Offset 0x44 Bits Field Type Description InitVal 1 0 PState RW Power State 0x0 00 DO 01 DI 10 D2 11 D3 hot 7 2 Reserved RW Read only 0x0 8 PME_EN RW PCI_PMEn Pin Assertion Enable 0x0 12 9 DSel RW Data Select 0x0 14 13 DScale RW Data Scale 0x0 NOTE Read only from PCI 15 PME Stat RW PCI PMEn Pin Status 0x0 CPU set only by writing 1 PCI clear only by writing 1 When set to 1 the 88F5182 asserts PCI PMEn pin 23 16 P2P RW Power Management Status and Control for P2P Bridge 0x0 NOTE Read only from PCI 31 24 Data RW State Data 0x0 NOTE Read only from PCI Table 265 PCI VPD Address Offset 0x48 Bits Field Type Description InitVal 7 0 CapID RW Capability ID 0x3 NOTE Read only from PCI 15 8 NextPtr RW Next Item Pointer 0x50 NOTE Read only from PCI 30 16 Addr RW VPD Address 0x0 Points to the location of the VPD structure in memory NOTE The 88F5182 also implements remapping of the high address bits through the PCI Address Decoding Control register Doc No MV S400130 00 Rev 0 5 Page 205 Copyright 2007 Marvell Document C
408. ry Page 232 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 314 EDMA Interrupt Error Mask Register Offset Port 0 0x8200C Port 1 0x8400C Bits Field Type Description InitVal 31 0 elntErrMsk RW EDMA Interrupt Error Mask Bits 0x0 Each of these bits checks the corresponding bit in the EDMA Interrupt Error Cause Register Table 313 p 230 and if these bits are set 0 they mask the interrupt 0 Mask 1 Do not mask Table 315 EDMA Request Queue Base Address High Register Offset Port 0 0x82010 Port 1 0x84010 Type Description InitVal eRqQBA 63 32 The EDMA Request Queue Base Address corresponds to bits 63 32 D Table 316 EDMA Request Queue In Pointer Register Offset Port 0 0x82014 Port 1 0x84014 Bits Field Type Description InitVal 4 0 Reserved RES Reserved 0x0 9 5 eRqQIP RW EDMA Request Queue In Pointer 0x0 The EDMA request queue in pointer is written increment by the system driver to indicate that a new CRQB has been placed on the request queue The EDMA compares the EDMA Request Queue In Pointer to the EDMA Request Queue Out Pointer to determine when the request queue is empty If there are CRQBs in the request queue then when the EDMA is ready it process the commands 11 10 eRqQIP RW Function of this field depends on the lt eEDMAQueLens field in the EDMA eRqQBA 0x0 Configuration Register Table 311 p 228 lt eE
409. s Table 428 USB 2 0 Window1 Control Register Continued 0x50330 Port1 0xA0330 Offset Port Bits Field Type Function InitVal 7 4 Target RW Specifies the target interface associated with this window 0x0 See Section 2 10 Default Address Map on page 14 15 8 Attr RW Specifies the target interface attributes associated with this window 0x0 See Section 2 10 Default Address Map on page 14 31 16 Size RW Window Size 0x0 Used with the Base register to set the address window size and location Must be programmed from LSB to MSB as sequence of 1 s followed by sequence of 0 s The number of 1 s specifies the size of the window e g a value of OxOOFF specifies 256x64k 16 MB Table 429 USB 2 0 Window1 Base Register 0x50334 Port1 0xA0334 Offset Port Bits Field Type Function InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x0 Used with the size field to set the address window size and location Corresponds to transaction address 31 16 Table 430 USB 2 0 Window2 Control Register Offset Port0 0x50340 Porti 0xA0340 Bits Field Type Function InitVal 0 win en RW Window0 Enable 0x0 0x0 Window is disabled 0x1 Window is enabled 3 1 Reserved RES Reserved 0x0 7 4 Target RW Specifies the target interface associated with this window 0x0 See Section 2 10 Default Address Map on page 14 15 8 Attr RW
410. s a t r JX IN o t r w p mS n o Address a c k Combined Access s s t t Last Data S a a t r r A o t rw t rw p ls E C o k Address Address a e L Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 41 Document Classification Proprietary June 25 2007 Preliminary Two Wire Serial Interface TWSI Functional Description 11 1 1 TWSI Slave Addressing The TWSI slave interface supports both 7 bit and 10 bit addressing The slave address is programmed by the TWSI Slave Address register see Table 492 on page 335 and TWSI Extended Slave Address register see Table 493 on page 335 When the TWSI receives a 7 bit address after a start condition it compares it against the value programmed in the Slave Address register and if it matches it responds with acknowledge If the received 7 address bits are 11110xx meaning that it is an 10 bit slave address the TWSI compares the received 10 bit address with the 10 bit value programmed in the TWSI Slave Address Table 492 p 335 and TWSI Extended Slave Address Table 493 p 335 registers and if it matches it responds with acknowledge The TWSI interface also support slave response to general call transactions If the lt GCE gt bit in the TWSI Slave Address register is set to 1 the TWSI also responds to the general call address 0x0 11 1 2 TWSI Data An 8 bit TWSI Data Table 494 p 336 register is used both in master and slave modes In master mode the Marvell
411. s 256x64k 16 MB Table 532 High Address Remap x Register Offset Register 0 0x60A60 Register 1 0x60A64 Register 2 0x60A68 Register 3 Ox60A6C Bits Field Type Description 31 0 Remap RW Remap Address 0x0 Specifies address bits 63 32 to be driven to the target interface Only relevant for target interfaces that supports more than 32 bit addressing 1 Remap 0 corresponds to Base Address register 0 Remap 1 to Base Address register 1 Remap 2 to Base Address register 2 and Remap 3 to Base Address register 3 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 356 88F5182 marveL Open Source Community Programmer s User Guide Table 533 Base Address Enable Register Offset 0x60A80 Bits Field Type Description 7 0 En RW Address Window Enable OxFF Bit per window If set to 0 the corresponding address window is enabled 31 8 Reserved RO Read only 0x0 Table 534 Channelx Access Protect Register Offset Channel 0 0x60A70 Channel 1 0x60A74 Channel 2 0x60A78 Channel 3 0x60A7C Bits Field Type Description 1 0 Wino RW Window0 Access control 0x3 0x0 No access allowed 0x1 Read Only 0x2 Reserved 0x3 Full access read or write In case of access violation e g write data to a read only region an interrupt is set and the transaction is n
412. s Control Register 0x41A00 Table 136 p 142 PCI Express Status Register 0x41A04 Table 137 p 143 PCI Express Completion Timeout Register 0x41A10 Table 138 p 144 PCI Express Flow Control Register 0x41A20 Table 139 p 145 PCI Express Acknowledge Timers 1X Register 0x41A40 Table 140 p 145 PCI Express TL Control Register 0x41AB0 Table 141 p 146 PCI Express Configuration Header Registers PCI Express Device and Vendor ID Register 0x40000 Table 142 p 146 PCI Express Command and Status Register 0x40004 Table 143 p 146 PCI Express Class Code and Revision ID Register 0x40008 Table 144 p 149 PCI Express BIST Header Type and Cache Line Size 0x4000C Table 145 p 149 Register PCI Express BARO Internal Register 0x40010 Table 146 p 150 PCI Express BARO Internal High Register 0x40014 Table 147 p 150 PCI Express BAR1 Register 0x40018 Table 148 p 150 PCI Express BAR1 High Register 0x4001C Table 149 p 151 PCI Express BAR2 Register 0x40020 Table 150 p 151 PCI Express BAR2 High Register 0x40024 Table 151 p 152 PCI Express Subsystem Device and Vendor ID 0x4002C Table 152 p 152 PCI Express Expansion ROM BAR Register 0x40030 Table 153 p 152 PCI Express Capability List Pointer Register 0x40034 Table 154 p 153 PCI Express Interrupt Pin and Line Register 0x4003C Table 155 p 153 PCI Express Power Management Capability Header 0x40040 Table 156 p 153 Register PCI Express Power Management Control and Status 0x40044 Table 157 p 154 Reg
413. s bits controls whether the decryption key is calculated in the engine prior 0x0 to the data decryption 0 No decryption key calculation 1 Decryption key calculation 3 Reserved RES Reserved 0x0 4 DataByteSwap RW This bit controls whether data byte swap is activated on input 0x0 0 No byte swap 1 Byte swap 7 5 Reserved RES Reserved 0x0 8 OutByteSwap RW This bit controls whether byte swap is activated for output 0x0 0 No byte swap 1 Byte swap 30 9 Reserved RES Reserved 0x0 31 Termination RO This bit is set by the engine to indicate completion of a AES calculation pro 0x1 cess Any write to the decryption engine will clear this bit A 11 5 Security Accelerator Registers Table 484 Security Accelerator Command Register Offset Ox9DE00 Bits Field Type Description InitVal 0 EnSecurityAcclO RW Setting this bit activates session 0 of the accelerator After operation 0x0 completion this bit is cleared to zero by the hardware Writing zero to this bit has no effect Security acceleration assures in order execution and completion If session 0 is activated before session 1 by setting this bit before bit lt EnSecurityAccl1 gt the Security acceleration always execute session 0 before session 1 0 Session 0 is idle 1 Session 0 is set to active Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 329 Document Classification Proprietary June 25
414. s cache line size 0x00 15 8 LatTimer RW Specifies in units of PCI clock cycles the latency timer value of the 0x0 88F5182 Used by the PCI master when acting as a requester 23 16 HeadType RW Specifies Configuration Header Type Initial Value InitVal 0x80 NOTE Read only from PCI Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Page 200 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 252 PCI BIST Header Type Initial Value Latency Timer and Cache Line Continued Offset OxOC Bits Field Type Description InitVal 27 24 BISTComp RW BIST Completion Code 0x0 Written by the CPU upon BIST completion NOTE Read only from PCI 29 28 Reserved RES Reserved 0x0 30 BISTAct RW BIST Activate bit 0x0 Set to 1 by PCI to activate BIST Cleared by CPU upon BIST completion 31 BISTCap RW BIST Capable Bit 0x1 NOTE Read Only from PCI Table 253 PCI CSn 0 Base Address Low Offset 0x10 Bits Field Type Description InitVal 0 MemSpace RO Memory Space Indicator 0x0 2 1 Type RW BAR Type Initial Value InitVal 0x2 Located anywhere in 64 bit address space NOTE Read only from PCI 3 Prefetch RW Prefetch Enable 0x1 NOTE Read only from PCI 11 4 Reserved RES Read only 0x0 31 12 Base RW Base address Corresponds to address bits 3
415. s the 88F5182 to perform a Configuration or Special cycle on the PCI bus Table 242 PCI Interrupt Acknowledge Offset 0x30C34 Bits Field Type Description InitVal 31 0 IntAck RO A CPU read access to this register forces an interrupt acknowledge 0x0 cycle on the PCI bus A 7 4 PCI Error Report Registers Doc No MV S400130 00 Rev 0 5 Page 193 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary Table 243 PCI SERRn Mask Offset 0x30C28 NOTE 88F5182 only asserts PCI SERRn if the PCI Status and Command register s SErrEn bit 8 is enabled see Table 250 on page 198 PCI Interface Registers Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Bits Field Type Description InitVal 0 DPErr RW If set to 1 asserts PCI_SERRn upon internal data path error detection in 0x0 the PCI interface 1 SWrPerr RW If set to 1 asserts PCI SERRn upon PCI slave detection of bad write 0x0 data parity 2 SRdPerr RW If set to 1 asserts PCI SERRn upon a PCI PERRn response to read 0x0 data driven by the PCI slave 4 3 Reserved RES Reserved 0x0 5 MWrPerr RW If set to 1 asserts PCI SERRn upon a PCI PERRn response to write 0x0 data driven by the PCI master 6 MRdPerr RW If set to 1 asserts PCI SERRn upon a bad data parity detection during 0x0 a PCI master read transaction or
416. s the contents of the Cylinder High LBA High Current register of the Shadow Register Block Doc No MV S400130 00 Rev 0 5 Page 27 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Il Host Controller SATAHC EDMA Operation Table 8 CRQB DW5 ATA Command Continued Offset 0x14 Bits Field Description 31 24 Device Head This field contains the contents of the Device Head Device register of the Shadow Register Block Table 9 CRQB DW6 ATA Command Offset 0x18 Bits Field Description 7 0 Sector Number This field contains the contents of the Sector Number Exp LBA Low Previous register Exp of the Shadow Register Block see Table 291 on page 215 15 8 Cylinder Low This field contains the contents of the Cylinder Low Exp LBA Mid Previous register of Exp the Shadow Register Block 23 16 Oylinder High This field contains the contents of the Cylinder High Exp LBA High Previous register Exp of the Shadow Register Block 31 24 Features Exp This field contains the contents of the Features Exp Features Previous register of the Shadow Register Block Table 10 CRQB DW7 ATA Command Offset Ox1C Bits Field Description 7 0 Sector Count This field contains the contents of the Sector Count Sector Count Current register of the Shadow Register Block see Table 2
417. sed to prevent contention between read and write data driven from two different devices same parameter for read after write and write after read 0 One cycle 1 Two cycles 2 3 Reserved 9 8 tRFC RW Extension MSB of trrc bits 3 0 0x0 11 10 twow RW Minimum Gap between Write to Write to different DDR SDRAM devices 0x0 Value 0 means no gap value 1 means one cycle gap and so on 31 12 Reserved RO Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 115 Document Classification Proprietary June 25 2007 Preliminary DDR SDRAM Controller Registers Table 89 DDR2 SDRAM Timing Low Register Offset 0x01428 Bits Field Type Description InitVal 3 0 Reserved RW Reserved 0x5 7 4 topT_ON_RD RW The number of cycles from Read command to the assertion of M_ODT 0x0 signal Value 0 means same cycle as read command value of 1 means one cycle later and so on This value depends on DDR SDRAM CL and taonp timing parameters For CL 3 and taonp 2 set topr ow to 0 11 8 lopT OFF RD RW The number of cycles from Read command to de asserting M ODT signal 0x3 Value depends on DDR SDRAM CL and top timing parameters For CL 3 and taoFD 2 5 set topT_OFF to 0x3 15 12 topt on cru R RW The number of cycles from Read command to the assertion of the internal D 0x3 ODT signal to the DDR SDRAM controller I O buffer The same as topr on 19 16 topt_oFF_cTL_R RW The number of cycles fr
418. ser Guide DDR SDRAM Timing Low Register Continued Offset 0x01408 NOTE The default values fit DDR2 400 speed grade Change these timing parameters according to the DDR SDRAM type and operating frequency Bits Field Type Description InitVal 19 16 twrr RW Write Command to Read Command 0x1 Value 0 means one cycle value of 1 means two cycles and so on 23 20 tras RW Minimum Row Active Time active to precharge 0x8 Value 0 means one cycle value of 1 means two cycles and so on 27 24 tarp RW Activate Bank A to Activate Bank B 0x1 Value 0 means one cycle value of 1 means two cycles and so on 31 28 ere RW Read Command to Precharge 0x1 Value 0 means one cycle value of 1 means two cycles and so on NOTE Must be set to 0x1 two cycles when using DDR1 Table 88 DDR SDRAM Timing High Register Offset 0x0140C Bits Field Type Description InitVal 3 0 tRFC RW Refresh Command Period OxD Value 0 means one cycle value of 1 means two cycles and so on 5 4 tror RW Minimum Gap Between DDR SDRAM Read Accesses 0x0 This timing parameter is not part of the JEDEC standard It is used to prevent contention between read data driven from two different DDR SDRAM devices DIMMs 0 One cycle 1 Two cycles 2 3 Reserved 7 6 tRew_weR RW Minimum Gap Between DDR SDRAM Read and Write Accesses 0x0 This timing parameter is not part of the JEDEC standard It is u
419. ses and their associate IDMA operation When the IDMA is configured to copy the outcome of the security accelerator process back to the DDR that is when the lt Ch0ActivatelDMAs gt field in the Security Accelerator Configuration Register Table 487 p 331 is set to 1 AccAndIDMAIntO is set to 1 after the IDMA completes copying the data back to the DDR When the IDMA is NOT configured to copy the outcome of the security accelerator process back to the DDR that is when the lt Ch0ActivatelDMAs field in the Security Accelerator Configuration Register Table 487 p 331 is set to 0 lt AccAndIDMAIntO gt is set after the security accelerator completes the process and data is valid in the local SRAM 8 AccAndIDMAInt1 RWO 0x0 31 9 Reserved RES 0x0 Acceleration and IDMA Interrupt 1 This bit is set to 1 when the entire security accelerator process is completed including both encryption authentication processes and their associate IDMA operation Reserved When the IDMA is configured to copy the outcome of the security accelerator process back to the DDR that is when the lt Ch1ActivatelDMA gt field in the Security Accelerator Configuration Register Table 487 p 331 is set to 1 lt AccAndIDMAInt1 gt is set to 1 after the IDMA completes copying the data back to the DDR When the IDMA is NOT configured to copy the outcome of the security accelerator process back to the DDR that is when the lt Ch1Activatel
420. set 1542 MPPSel11 RW MPP11 Select Sample See field MPPSel8 at reset 19 16 MPPSel12 RW MPP12 Select Sample See field MPPSel8 at reset 23 20 MPPSel13 RW MPP13 Select Sample See field MPPSel8 at reset 27 24 MPPSel14 RW MPP14 Select Sample See field MPPSel8 at reset 31 28 MPPSel15 RW MPP15 Select Sample See field MPPSel8 at reset Table 576 MPP Control 2 Register Offset 0x10050 Bits Field Type Description InitVal 3 0 MPPSel16 RW MPP 16 Select Sample See the MPP Function Summary table in the 88F5182 88F5182 based at reset Storage Networking Platforms Datasheet 7 4 MPPSel17 RW MPP17 Select Sample See field MPPSel16 at reset Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 385 Document Classification Proprietary June 25 2007 Preliminary Pins Multiplexing Interface Registers Table 576 MPP Control 2 Register Continued Offset 0x10050 Bits Field Type Description InitVal 11 8 MPPSel18 RW MPP18 Select Sample See field MPPSel16 at reset 1542 MPPSel19 RW MPP19 Select Sample See field MPPSel16 at reset 31 16 Reserved RES Reserved 0x0 Table 577 Device Multiplex Control Register Offset 0x10008 Bits Field Type Description InitVal 31 0 Reserved RES Reserved Ox03FFO NOTE Must be OxO3FF0000 000 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 20
421. set OXODDAC Table 462 AES Encryption Key Column 3 Register nennen nnne nennen enne nnns 323 Offset OX9DD90 Table 463 AES Encryption Key Column 2 Register nnne ennt nene erret renes nnns 323 Offset OX9DD94 Table 464 AES Encryption Key Column 1 Register sssssssssssesseneeneenereneeneeenrenrenr enne nren nenne 324 Offset OX9DD98 Table 465 AES Encryption Key Column 0 Register nennen nnne nenne nnne n renes 324 Offset OX9DD9C Table 466 AES Encryption Key Column 7 Register ssssssssssssssssesseneeeenrenneenerenrenrenren nennen nenne 324 Offset OX9DD80 Table 467 AES Encryption Key Column 6 Register ec cece eeeeeeeee cess tees eeneteeeseeeseeesaeesaeeseeeseneseeesaesnaeseaeeeaeeaaes 324 Offset OX9DD84 Table 468 AES Encryption Key Column 5 Register A 325 Offset OX9DD88 Table 469 AES Encryption Key Column 4 Register sssssssssssssseeseeeeenneenereneeenenen ren rtr en rentrer 325 Offset OX9DD8C Table 470 AES Encryption Command Register nennen nnne nnns en rne e nnns en rnn innen nnns 325 Offset OXODDBO Table 471 AES Decryption Data In Out Column 3 Register ssssssssssseseeseseee eene nene 326 Offset OXODDEO Table 472 AES Decryption Data In Out Column 2 Register esssssssssssseseseeeeenneeen nene enne 326 Offset OXODDE4 Table 473 AES Decryption Data In Out Column 1 Register esssssssssseseeseseeee eene ne
422. ss Registers Enable 0x30C3C Table 198 p 175 CSn 0 Base Address Remap 0x30C48 Table 199 p 176 CSn 1 Base Address Remap 0x30D48 Table 200 p 177 CSn 2 Base Address Remap 0x30C4C Table 201 p 177 CSn 3 Base Address Remap 0x30D4C Table 202 p 177 DevCSn 0 Base Address Remap 0x30C50 Table 203 p 177 DevCSn 1 Base Address Remap 0x30D50 Table 204 p 177 DevCSn 2 Base Address Remap 0x30D58 Table 205 p 178 BootCSn Base Address Remap 0x30D54 Table 206 p 178 P2P Mem0 Base Address Remap Low 0x30D5C Table 207 p 178 P2P Mem0 Base Address Remap High 0x30D60 Table 208 p 178 P2P I O Base Address Remap 0x30D6C Table 209 p 178 Expansion ROM Base Address Remap 0x30F38 Table 210 p 179 DRAM BAR Bank Select 0x30C1C Table 211 p 179 PCI Address Decode Control 0x30D3C Table 212 p 179 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 169 Document Classification Proprietary June 25 2007 Preliminary Table 179 PCI Control Register Map PCI Interface Registers Table 180 PCI Configuration Access Register Map Register Offsets Page PCI DLL Control 0x31D20 Table 213 p 180 PCI MPP Pads Calibration 0x31D1C Table 214 p 181 PCI Command 0x30C00 Table 215 p 182 PCI Mode 0x30D00 Table 216 p 184 PCI Retry 0x30C04 Table 217 p 185 PCI Discard Timer 0x30D04 Table 218 p 185 MSI Trigger Timer 0x30C38 Table 219 p 186 PCI Arbiter Control 0x31D00 Table 2
423. ssage Signal Interrupts MSI are memory write requests and as such are disabled in accordance to this bit Messages and completions are transmitted to the PCI Express regardless of the setting of this bit 53 Reserved RSVD Does not apply to PCI Express devices 0x0 This bit is hardwired to 0 6 PErrEn RW Parity Error Enable 0x0 This bit controls the ability of the 88F5182 to respond to poisoned data errors as a requestor master on the PCI Express port Controls MasDataPerr status bit assertion in PCMDSTT register 0 Disabled MasDataPerr assertion is disabled 1 Enabled MasDataPerr assertion is enabled NOTE The setting of this bit does not affect the DetectedPErr status bit 7 Reserved RSVD Does not apply to PCI Express 0x0 This bit is hardwired to 0 8 SErrEn RW This bit controls the ability of the 88F5182 to report fatal and non fatal errors 0x0 to the Root Complex This bit affects both assertion of SSysErr status bit 30 in this register and uncorrectable error message generation 0 Disabled SSysErr assertion is disabled 1 Enabled SSysErr assertion is enabled In addition uncorrectable error messages generation is enabled NOTE PCI Express uncorrectable error messages are reported if enabled either through this bit or through bits NFErrRepEn or FErrRepEn in Table 164 PCI Express Device Control Status Register 9 Reserved RSVD Does not apply to PCI Express 0x0 This bit is hardwired to 0 10 Int
424. sse 298 Offset Q0 0x72700 Q1 0x72710 Q2 0x72720 Q3 0x72730 Q4 0x72740 Q5 0x72750 Q6 0x72760 Q7 0x72770 Transmit Queue Token Bucket Configuration TQxTBO ssssssssssssssseeeeeeeeenren nnne 298 Offset QO 0x72704 Q1 0x72714 Q2 0x72724 Q3 0x72734 Q4 0x72744 Q5 0x72754 Q6 0x72764 Q7 0x72774 Transmit Queue Arbiter Configuration TOSAC nennen nennen teres 299 Offset Q0 0x72708 Q1 0x72718 Q2 0x72728 Q3 0x72738 Q4 0x72748 Q5 0x72758 Q6 0x72768 Q7 0x72778 Destination Address Filter Special Multicast Table DEGMT 299 Offset 0x 73400 0x734FC Destination Address Filter Other Multicast Table DFUT sse 300 Offset 0x73500 0x735FC Destination Address Filter Unicast Table DFUT ssssesseeeenneennenenen eene 301 Offset 0x73600 0x7360C MAG MIB CGOUMTEFS iniiai eaa 302 Offset 0x73000 0x7307C A 10 USB 2 0 Registers Table 422 USB 2 0 Bridge Control Register nen rennenretnreenren rennen rennes 307 Offset Port 0x50300 Port1 0xA0300 Table 423 USB 2 0 Bridge Interrupt Cause Register sse nennen nenne 307 Offset Port0 0x50310 Port1 0xA0310 Table 424 USB 2 0 Bridge Interrupt Mask Register A 308 Offset Port0 0x50314 Port1 0xA0314 Table 425 USB 2 0 Bridge Error Address Register AAA 308 Offset Port0 0x5031C Port 0xA031C Table 426 USB 2 0 Window0 Control Register A 309 Offset
425. ssification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers Table 452 SHA 1 MD5 Initial Value Digest A Register Offset Ox9DDOO Bits Field Type InitVal Description 31 0 IVDigA RW IV A contains the first word of the Initial Value and Digest A contains 0x67452301 the first word of the digest Table 453 SHA 1 MD5 Initial Value Digest B Register Offset 0x9DD04 Bits Field Type InitVal Description 31 0 IVDigB RW IV B contains the second word of the Initial Value and Digest B con OxEFCDABS89 tains the second word of the digest Table 454 SHA 1 MD5 Initial Value Digest C Register Offset Ox9DDO08 Bits Field Type InitVal Description 31 0 IVDigC RW IV C contains the third word of the Initial Value and Digest C con Ox98BADCFE tains the third word of the digest Table 455 SHA 1 MD5 Initial Value Digest D Register Offset OX9DDOC Bits Field Type InitVal Description 31 0 IVDigD RW IV D contains the fourth word of the Initial Value and Digest D con 0x10325476 tains the fourth word of the digest Table 456 SHA 1 Initial Value Digest E Register Offset Ox9DD10 Bits Field Type InitVal Description 31 0 IVDigE RW IV E contains the fifth word of the Initial Value and Digest E contains 0xC3D2E1F0 the fifth word of the digest NOTE This register is only used in SHA 1 since
426. ster essent enn 155 Offset 0x40050 Table 159 PCI Express MSI Message Address Register sssssssssseeeeeeeene ener entren 155 Offset 0x40054 Table 160 PCI Express MSI Message Address High Register nens 156 Offset 0x40058 Table 161 PCI Express MSI Message Data Register 156 Offset 0x4005C Table 162 PCI Express Capability Register Aren 156 Offset 0x40060 Table 163 PCI Express Device Capabilities Register sese eene 157 Offset 0x40064 Table 164 PCI Express Device Control Status Register sssssssssssesseseeeeeenenrenrenren nennen 158 Offset 0x40068 Table 165 PCI Express Link Capabilities Register nennen nenne 161 Offset 0x4006C Table 166 PCI Express Link Control Status Hegieier AA 161 Offset 0x40070 Table 167 PCI Express Advanced Error Report Header Heiser 163 Offset 0x40100 Table 168 PCI Express Uncorrectable Error Status Register 163 Offset 0x40104 Table 169 PCI Express Uncorrectable Error Mask Register A 165 Offset 0x40108 Table 170 PCI Express Uncorrectable Error Severity Register eee eeee ce eeeee cere seas sens seeeseeeeeeeseeesaeeeaeeegeeaaes 165 Offset 0x4010C Table 171 PCI Express Correctable Error Status Register 0 0 cece cece cece cece teeeeeee cesses sage seaeseeeseeeseteaeseaeeeaeeges 165 Offset 0x40110 Table 172 PCI Express Correctable Error Mask Register 166 Offset 0x40114 Copyright 2007 Mar
427. ster Host to Device FIS When the EDMA is enabled this bit value is ignored and assumed to be 1 EDMA retransmits the Register Host to Device FIS 31 27 Reserved RES 0x0 Reserved Table 350 Serial ATA Interface Control Register Offset Port 0 0x82344 Port 1 0x84344 NOTE When field lt eEnEDMAs is set this register must not be written If this register is written when field lt eEnEDMAs is set the write transaction will cause unpredictable behavior Bits Field Type Description InitVal 3 0 PMportTx RW Port Multiplier Transmit 0x0 This field specifies the Port Multiplier bits 11 8 in DWO of the FIS header of any transmitted FIS 7 4 Reserved RW Reserved 0x0 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 256 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 350 Serial ATA Interface Control Register Continued Offset Port 0 0x82344 Port 1 0x84344 NOTE When field lt eEnEDMAs is set this register must not be written If this register is written when field lt eEnEDMAs is set the write transaction will cause unpredictable behavior Bits Field Type Description InitVal 8 VendorUqMd RW Vendor Unique mode 0x0 This bit is set to 1 to indicate that the next FIS going to be transmitted is a Vendor Unique FIS Only when this bit is set th
428. t Offset 0x0C Bits Field Description 15 0 cDataRegionBy Data Region Byte Count teCount When cPRDModes is cleared to 0 This field is reserved When cPRDModes is set to 1 This field contains the count of the region in bytes Bit 0 is force to 0 There is a 64 KB maximum A value of 0 indicates 64 KB The data in the buffer must not cross the boundary of the 32 bit address space that is the 32 bit high address of all data in the buffer must be identical 31 16 Reserved Reserved S Note The naming of the fields in the next four tables complies with the Serial ATA convention The corresponding name according to the ATA convention appears in parentheses Table 7 CRQB DW4 ATA Command Offset 0x10 Bits Field Description 15 0 Reserved Reserved 23 16 Command This field contains the contents of the Command register of the Shadow Register Block see Table 291 on page 215 31 24 Features This field contains the contents of the Features Features Current register of the Shadow Register Block Table 8 CRQB DW5 ATA Command Offset 0x14 Bits Field Description 7 0 Sector Number This field contains the contents of the Sector Number LBA Low Current register of the Shadow Register Block see Table 291 on page 215 15 8 Oylinder Low This field contains the contents of the Cylinder Low LBA Mid Current register of the Shadow Register Block 23 16 Oylinder High This field contain
429. t Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 355 FIS Interrupt Cause Register Continued Offset Port 0 0x82364 Port 1 0x84364 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Name Type Description InitVal 15 8 FISWait4HostR RWO This field indicates the reception of the following FISs dy 0x0 FISWait4HostRdy 0 Register Device to Host FIS with ERR bit set to 1 FISWait4HostRdy 1 SDB FIS is received with lt N gt bit set to 1 FISWait4HostRdy 2 SDB FIS is received with ERR bit set to 1 FISWait4HostRdy 3 BIST activates FIS FISWait4HostRdy 4 PIO Setup FIS FISWait4HostRdy 5 Data FIS with Link error FISWait4HostRdy 6 Unrecognized FIS type FISWait4HostRdy 7 Any FIS 0 No interrupt indication 1 Corresponding interrupt occurs For any FIS other than data FIS the corresponding bit is set when the FIS is received from the link layer without an error that is FIS DWO Register through FIS DW6 Register are updated with the content of the FIS up to the FIS length For the data FIS the corresponding bit is set when the entire FIS is received from the link layer if a link error occurs Only the FIS DWO Regis ter is updated with the content of the FIS FIS DW1 Register through FIS DW6 Register ar
430. t XOR mode Size of source and destination blocks in bytes CRC mode Size of source block part represented by the descriptor DMA mode Size of source and destination block in bytes Minimum blocks size 16B Maximum blocks size 16MB 1 31 24 Reserved Reserved Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 56 88F5182 marveL Open Source Community Programmer s User Guide Table 30 Descriptor Destination Address Word Bits Field Description 31 0 DA Destination Block address pointer XOR Mode Destination Block address pointer CRC mode Not used DMA mode Destination Block address pointer Table 31 Descriptor Source Address SN Words Bits Field Description 31 0 SA 0 source block 0 address pointer Source XOR Mode Source Block 0 address pointer Address 0 CRC mode Address pointer to part of source block represented by the descriptor DMA Mode Source Block address pointer 31 0 SA N source block N address pointer N 1 7 XOR mode Source Block N address pointer Source CRC mode Not used Address N DMA mode Not used Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 57 Document Classification Proprietary June 25 2007 Preliminary General Purpose UO Port Interface Section 16 General Purpose I O Port Interface The 88F5
431. t and attributes are taken from XEBARG Address 63 32 taken from XEHARR3 NOTE Valid only if NDAOvrEn is set 31 30 Reserved RES Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 376 88F5182 marveL Open Source Community Programmer s User Guide A 16 5 XOR Engine ECC Meminit Registers Table 557 XOR Engine 0 1 Destination Pointer XExDPRO Offset XORO 0x60BBO XOR1 0x60BB4 Bit Field Type Description InitVal 31 0 DstPtr RW Points to target block of ECC Memlnit operations 0x0 NOTE Valid only on ECC Memlnit modes Table 558 XOR Engine 0 1 Block Size XExBSR Offset XORO 0x60BCO XOR1 0x60BC4 Bit Field Type Description InitVal 31 0 BlockSize RW Size of Block in bytes for ECC or Memlnit Operation Along with XEODPR 0x0 or XE1DPR Destination pointer registers defines the target block for those operations Minimum value 128B Maximum Value 4GB The value 0x00000000 stands for 4GB block size Block must not cross 4GB boundary NOTE Valid only on ECC Meminit modes Table 559 XOR Engine Timer Mode Control XETMCR Offset Ox60BDO Bit Field Type Description InitVal 0 TimerEn RW Enable Timer Mode 0x0 Enables triggering ECC operation with timer If Enabled the target block will be divided to Sections acc
432. t is set forced to 0 when ForceLinkFail 0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 287 Document Classification Proprietary June 25 2007 Preliminary Gigabit Ethernet Controller Registers Table 395 Ethernet Port Status PS Continued Offset 0x72444 Bits Field Type Description InitVal Duplex 2 FullDx RW Half Full Duplex mode Deter 0 Port works in Half Duplex mode mined 1 Port works in Full Duplex mode by Auto This bit may change in any time when the AN Duplex bit is set to enable Negotia When AN Duplex in clear disabled this bit is set by the management in tion for PSCR Set FullDx duplex Read Only mode if NOTE Half Duplex is not supported in 1000 Mbps the Port Control regis ter s AN Du plex bit is enabled 802 3x Flow Control and Backpressure 3 EnFC RO NOTE Set by Flow Control Auto Negotiation if PSCR AN FC is enabled Enables receiving 802 3x Flow Control frames in full duplex mode 0 Disabled 1 Enabled If Port Control register s AN FC bit is enabled then each time that Auto Negotiation is performed on the GMII MII RGMII interface the value in the lt EnFC gt bit may change 4 GMIISpeed RO NOTE Determined by Auto Negotiation for speed mode when AN Speed is enabled 0 Port works in 10 100 Mbps mode 1 Port works in 1000 Mbps mode If the lt ANSpeed gt bit is enabled
433. t to the initiator When the port functions as an initiator in Target mode operation this bit is set when a DMA Activate FIS is received to activate the write data transac tion from the initiator to the target This bit is cleared when the DMA completes the data transaction associated with the command 0 Transport layer does not send DMA data FISs 1 Transport layer keeps sending multiple DMA data FISs until the data transaction associated with the command is completed 23 47 Reserved RES Reserved 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 257 Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 350 Serial ATA Interface Control Register Continued Offset Port 0 0x82344 Port 1 0x84344 NOTE When field lt eEnEDMAs is set this register must not be written If this register is written when field lt eEnEDMAs is set the write transaction will cause unpredictable behavior Bits Field Type Description InitVal 24 ClearStatus SC Status Self Clear 0x0 This bit clears bits 16 30 and 31 in the Serial ATA Interface Status Register see Table 352 on page 259 0 Does not clear bits 1 Clears the bits 25 SendSftRst SC Self Negate 0x0 When this bit is set to 1 the transport layer sends Register Host to Device control FIS to the device 31 26 Reserved RES Reserved 0x0
434. tD_Assert message received Cleared when IntD_Deassert message received or upon link failure sce nario DI down NOTE This bit is not RWOC as some others bit in this register since it is cleared by the interrupting device downstream Relevant for Root Complex only 31 28 Reserved RSVD Reserved 0x0 Table 114 PCI Express Interrupt Mask Offset 0x41910 Bits Field Type Description InitVal 31 0 Mask RW Mask bit per cause bit If a bit is set to 1 the corresponding event is 0x0 enabled Mask does not affect setting of the Interrupt Cause register bits it only affects the assertion of the interrupt NOTE Bits 23 20 are sticky bits not initialized by reset A 6 4 PCI Express Address Window Control Registers Table 115 PCI Express Window0 Control Register Offset 0x41820 Bits Field Type Description InitVal 0 WinEn RW Window0 Enable Ox1 0 Disabled Window is disabled 1 Enabled Window is enabled 1 BarMap RW Mapping to BAR 0x0 0 BAR1 Window is mapped to BAR1 1 BAR2 Window is mapped to BAR2 3 2 Reserved RSVD Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 134 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 115 PCI Express Window0 Control Register Continued Offset 0x41820 Bits F
435. tO 0x50104 Port1 0xA0104 HCCPARAMS Port0 0x50108 Port1 0xA0108 Reserved PortO 0x5010C 0x5011F Port1 0XA010C 0xA011F DCIVERSION Port0 0x50120 Port1 0xA0120 Reserved Port0 0x50122 Port1 0xA0122 DCCPARAMS PortO 0x50124 Port1 0xA0124 Reserved Pom 0x50128 0x5013C Port1 0xA0128 0xA013C USBCMD Port0 0x50140 Port1 0xA0140 USBSTS PortO 0x50144 Port1 0xA0144 USBINTR PortO 0x50148 Port1 0xA0148 FRINDEX Port0 0x5014C Port1 0xA014C Reserved Pont 0x50150 Porti 0xA0150 PERIODICLISTBASE Device Addr PortO 0x50154 Port1 0xA0154 ASYNCLISTADDR Endpointlist Addr Port0 0x50158 Port1 0xA0158 TTCTRL Port0 0x5015C Port1 OxA015C BURSTSIZE Port0 0x50160 Port1 0xA0160 TXFILLTUNING PortO 0x50164 Port1 0xA0164 Doc No MV S400130 00 Rev 0 5 Page 305 Document Classification Proprietary Copyright 2007 Marvell June 25 2007 Preliminary USB 2 0 Registers Table 419 USB 2 0 Controller Register Map Offsets Port0 0x50000 0x502FF Porti 0xA0000 0xA02FF Continued Register Offset TXTTFILLTUNING Port0 0x50168 Porti 0xA0168 N A Pom 0x5016C Port1 0xA016C N A PortO 0x50170 0x5017C Port1 0xA0170 0xA017C CONFIGFLAG Port0 0x50180 Porti 0xA0180 PORTSC1 PortO 0x50184 Port1 0xA0184 OTGSC PortO 0x501A4 Port1 0xA01A4 USBMODE PortO 0x501A8 Port1 0xA01A8 ENPDTSETUPSTAT Pott 0x501AC Port1 OxA01AC ENDPTPRIME PortO 0x
436. taeseaeeeaeeeaes 101 Offset 0x20110 Table 60 Local to System Bridge Interrupt Mask Register ee cee ee eee eee e ee eeee teas seas eeaeeeeeeeaeseaeesaeseaeseaeeeaeeeaes 101 Offset 0x20114 Table 61 Main Interrupt Cause Hegieier ee ee ee cece eceeeeeeeeeee see teretenetretrreenr etre eren rennes 102 Offset 0x20200 Table 62 Main IRQ Interrupt Mask Register A 104 Offset 0x20204 Table 63 Main FIQ Interrupt Mask Register 0 0 0 0 ccc cece eee e eee ceeeeeeeeeaeeseeeeaeesaeesaaeseeesaeesaeeseeeseaesaeesaeseaeeeaeeeaeeages 104 Offset 0x20208 Table 64 Endpoint Interrupt Mask Register A 104 Offset 0x2020C Table 65 CPU Timers Control Register eet cene eret nete Fart eon ede Se be bea edens 105 Offset 0x20300 Table 66 CPU TimerO Reload Register seessessseeseeeeeeenene nennen nennen nnne temer terere nns 105 Offset 0x20310 Table 67 GPU Timer 0 Registon anieri spein re tnter et dien oec ore Ver i epis rende te ate e ee SES 106 Offset 0x20314 Table 68 CPU Timer Reload Register sese ENEE 106 Offset 0x20318 Table 69 GPU imer Register ne cte tt retenti tob te ett n Poen te ade oett ee Ree pn 106 Offset 0x2031C Table 70 CPU Watchdog Timer Reload Heoisier A 106 Offset 0x20320 Table 71 GCPU Watchdog Timer Register iecit tee titer eret bU aderarii eee decernat 107 Offset 0x20324 Table 72 Host to CPU Doorbell Register A 107 Offset 0x20400 T
437. te to the TWSI Data register and then clears Interrupt flag for the TWSI master interface to drive the data on the bus The target slave responds with acknowledge causing Interrupt flag to be set and status code of 0x28 be registered in the Status register The Marvell processor core continues this loop of writing new data to the Data register and clear Interrupt flag as long as it needs to transmit write data to the target 4 After the last data transmit the Marvell processor core may terminate the transaction or restart a new transaction To terminate the transaction the Marvell processor core sets the Control register s Stop bit and then clears the Interrupt flag causing the TWSI master to generate a stop condition on the bus and go back to idle state To restart a new transaction the Marvell processor core sets the TWSI Control register s Start bit and clears the Interrupt flag causing TWSI master to generate a new start condition y Note This sequence describes a normal operation There are also abnormal cases such as a slave not responding with acknowledge or arbitration loss Each of these cases is reported in the TWSI Status register and needs to be handled by the Marvell processor core 11 2 2 Master Read Access A master read access consists of the following steps 1 Generate a start condition exactly the same as in the case of write access see Section 11 2 1 Master Write Access 2 Drive 7 or 10 bit slave
438. ter Offset 0x4006C Configuration 0x6C Bits Field Type Description InitVal 3 0 MaxLinkSpd RO Maximum Link Speed 0x1 The current value identifies the 2 5 Gbps link 9 4 MaxLnkWath RO Maximum Link Width 0x1 The current value identifies a X1 link 11 10 AspmSup RO Active State Link PM Support 0x1 The current value identifies LOs Entry Support 14 12 LOsExtLat RO LOs Exit Latency 0x2 The time required by the 88F5182 to transition its Rx lanes from LOs to LO 0 Under64ns Less than 64 ns 1 64to128ns 64 ns 128 ns 2 128t0256ns 128 ns 256 ns 3 256t0512ns 256 ns 512 ns 4 512nsto1us 512 ns 1 us 5 1to2us 1 us 2 us 6 2to4us 2 us 4 us 7 Reserved 17 15 Reserved RSVD Reserved 0x7 23 18 Reserved RSVD Reserved 0x0 31 24 PortNum RO Port Number 0x0 Controls the PCI Express port number as advertised in the link training pro cess In Endpoint mode indicates the PCI Express port number as was adver tised by the Root Complex during the link training process Table 166 PCI Express Link Control Status Register Offset 0x40070 Configuration 0x70 Bits Field Type Description InitVal 1 0 AspmCnt RW Active State Link PM Control 0x0 This field controls the level of active state PM supported on the link 0 Disabled Disabled 1 LOSupport LOs entry supported 2 Reserved 3 LOL1Support LOs and L1 entry supported Doc N
439. terrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type InitVal Description SaCrpbODone DMAODone RWO 0x0 SATA CRPB 0 Done Basic DMA 0 Done When EDMA is enable The lt eEnEDMA gt field in the EDMA Command Register Table 321 p 236 This field is set when the EDMA in port 0 places a new CRPB in the response queue 0 Anew CRPB was not placed in the response queue 1 Anew CRPB was placed in the response queue When EDMA is disabled Field eEnEDMA is cleared This field is set when the Basic DMA in port 0 completes the data trans fer clears field lt BasicDMAActive gt and move to idle state 0 Basic DMA has not completed the data transfer 1 Basic DMA completed the data transfer Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 220 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 299 SATAHC Interrupt Cause Register Continued Offset 0x80014 NOTE A corresponding cause bit is set every time that an interrupt occurs A write of 0 clears the bit A write of 1 has no affect Bits Field Type InitVal Description 1 SaCrpb1Done RWO DMA1Done 0x0 SATA CRPB 1 Done Basic DMA 1 Done When EDMA is enable Field lt eEnEDMAs is set This field is set when the EDMA in port 1 places a new CRPB
440. tes 11 Reserved 11 10 RdSize RW Typical PCI Read Transaction Size 0x0 Defines the amount of data the slave prefetches from the target unit 00 32 bytes 01 64 bytes 10 128 bytes 11 256 bytes NOTE If the transaction address hits a non prefetchable space prefetch bit of the BAR is cleared the slave reads a single data regardless of the setting of this field 31 12 Base RW Access Control Base Address 0x0 Corresponds to address bits 31 12 Table 223 PCI Access Control Base 0 High Offset 0x31E04 Bits Field Type Description InitVal 31 0 Base RW Base Address High 0x0 Corresponds to address bits 63 32 Table 224 PCI Access Control Size 0 Offset 0x31E08 Bits Field Type Description InitVal 3 0 Reserved RW Reserved 0x0 4 AggrWM1 RW Aggressive Prefetch Water Mark 1 0x0 0 The 88F5182 drives read data on the bus as soon as it has one 256 byte read buffer valid 1 The 88F5182 drives read data on the bus as soon as it has two 256 byte read buffers valid Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 188 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 224 PCI Access Control Size 0 Continued Offset 0x31E08 Bits Field Type Description InitVal 7 5 AggrWM2 RW Aggressive
441. that would cause a life threatening situation if any such products failed Do not use Marvell products in these types of equipment or applications With respect to the products described herein the user or recipient in the absence of appropriate U S government authorization agrees 1 Not to re export or release any such information consisting of technology software or source code controlled for national security reasons by the U S Export Control Regulations EAR to a national of EAR Country Groups D 1 or E 2 2 Not to export the direct product of such technology or such software to EAR Country Groups D 1 or E 2 if such technology or software and direct products thereof are controlled for national security reasons by the EAR and 3 In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant not to export to EAR Country Groups D 1 or E 2 the direct product of the plant or major component thereof if such direct product is controlled for national security reasons by the EAR or is subject to controls under the U S Munitions List USML At all times hereunder the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information Copyright Marvell International Ltd All rights reserved Marvell the Marvell logo Moving Forward Faster
442. the packet and pad it to 448 bit size with zeros Then the host adds a double word 64 bits that contains the length After that the chunk is ready for processing by the engine Packets may be of arbitrary length up to 2 64 bits They are broken into 512 bit chunks The last chunk of the packet is padded to 448 bits as described above and 64 bits representing packet length are added to make a 512 bit block Prior to writing the first chunk of a packet the host must select the Initial mode 0 in the command register After the first chunk is processed all the proceed ing chunks of the packet must be processed using Continue mode 1 In Ini tial mode the engine starts processing the data block using the initial values of the algorithm In Continue mode the results of the previous calculation are used The user may want to share the engine for multiple packet signature calcula tions That is done by calculating a chunk or chunks of a specific packet read ing the intermediate digest and saving the digest in a memory Then it is possible to start to process another packet To continue processing the first packet the host must write the intermediate digest that was saved in the memory to the initial values registers and continue packet processing in Con tinue mode NOTE When the host wants to use initial values other than the ones defined by the algorithm Continue mode must be selected Doc No MV S400130 00 Rev 0 5 Page 321
443. tinued Offset 0x80060 Bits Field Type Description InitVal 15 8 Attr RW Target specific attributes depending on the target interface 0x07 See the Window0 Control Register 31 16 Size RW Window Size OxOFFF See the Window0 Control Register Table 310 Window3 Base Register Offset 0x80064 Bits Field Type Description InitVal 15 0 Reserved RES Reserved 0x0 31 16 Base RW Base Address 0x3000 See the Window0 Base Register A 8 8 EDMA Registers Table 311 EDMA Configuration Register Offset Port 0 0x82000 Port 1 0x84000 Bits Field Type Description InitVal 4 0 Reserved RW Reserved Ox1F 5 eSATANatvCm RW EDMA SATA Native Command Queuing dQue 0x0 When EDMA uses SATA Native Command Queuing this bit must be set to 1 When this bit is set bit 9 eQue is ignored 0 Native Command Queuing is not in use 1 Native Command Queuing is in use 7 6 Reserved RW Reserved 0x0 8 eRdBSz RW EDMA Burst Size 0x0 This bit sets the maximum burst size initiated by the DMA to the Mbus This bit is related to read operation 0 128B 1 Reserved NOTE This field must be set to 0 9 eQue RW EDMA Queued 0x0 When EDMA uses queued DMA commands this bit must be set to 1 0 Non Queued DMA commands are in use 1 Only Queued DMA commands are in use Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Cl
444. tion Proprietary June 25 2007 Preliminary Table 402 Table 403 Table 404 Table 405 Table 406 Table 407 Table 408 Table 409 Table 410 Table 411 Table 412 Table 413 Table 414 Table 415 Table 416 Table 417 Table 418 List of Registers Port Rx FIFO Urgent Threshold PRFUT sssesesseeeseeeeeeneenren nennen nretere neret en rre nren nenne 294 Offset 0x72470 Port Tx FIFO Urgent Threshold PTFUT neret tnter nh eb nae edens 294 Offset 0x72474 Port Rx Minimal Frame Size PME 295 Offset 0x7247C Port Rx Discard Frame Counter PxDFO sss retener enne tren rennes 295 Offset 0x72484 Port Overrun Frame Counter POFO 00 cc eee cece eee eeae teas sees seaeeeaeeeaeeeaeseaeseaeeeaeseaeseaeeeaseaeseaeseaeeeaeeaaee 296 Offset 0x72488 Port Internal Address Error EUIAE eese enne nennen 296 Offset 0x72494 Ethernet Current Receive Descriptor Pointers CDD 296 Offset Q0 0x7260C Q1 0x7261C Q2 0x7262C Q3 0x7263C Q4 0x7264C Q5 0x7265C Q6 0x7266C Q7 0x7267C Receive Queue Command RQO sessi nnne nnen nennen nre 297 Offset 0x72680 Transmit Current Served Descriptor Pointer sesssssssesseeeeeeneeneenen nennen 298 Offset 0x72684 Transmit Current Queue Descriptor Pointer TCQDP nennen 298 Offset Q0 0x726C0 Transmit Queue Token Bucket Counter TQXTBC
445. to bits 31 24 of byte count field 0 Disable 1 Enable NOTE Enable in chain mode only Disable when a new chain is begun by directly programming the first descriptor of the chain into the channel registers instead of fetching the descriptor from memory using the lt FetchND gt bit 13 19 18 Reserved RW Reserved 0x0 Must be 0x0 20 Abr RW Channel Abort 0x0 When the software sets this bit to 1 the IDMA aborts in the middle The bit is cleared by the IDMA hardware 22 21 SAddrOvr RW Override Source Address 0x0 00 No override 01 Source interface and attributes are taken from BAR 1 10 Source interface and attributes are taken from BAR 2 11 Source interface and attributes are taken from BAR 3 24 23 DAddrOvr RW Override Destination Address 0x0 00 No override 01 Destination interface and attributes are taken from BAR 1 10 Destination interface and attributes are taken from BAR 2 11 Destination interface and attributes are taken from BAR 3 26 25 NAddrOvr RW Override Next Descriptor Address 0x0 00 No override 01 Next descriptor interface and attributes are taken from BAR 1 10 Next descriptor interface and attributes are taken from BAR 2 11 Next descriptor interface and attributes are taken from BAR 3 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary IDMA Controller Interface Registers Table 535 Channel Control Low Register Continued Offset Channel 0 0x6084
446. to board timing simulation results 11 7 Reserved RO Reserved 0x0 12 CIk1Drv RW M CLK OUT Drive 0x1 0 M_CLK_OUT 1 and M CLK OUTn 1 are high z 12M CLK OUT 1 and M CLK OUTn 1 are driven normally NOTE When not using M_CLK_OUT 1 set it to high z 13 Reserved RO Reserved 0x0 17 14 Reserved RO Reserved 0x0 18 LockEn RW CPU Lock Enable 0x1 0 Disable 1 Enable 23 19 Reserved RO Reserved 0x0 27 24 StBurstDel RW Number of sample stages on StartBurstln 0x3 Program StBurstDel based on CL registered non buffered DIMM 31 28 Reserved RO Reserved 0x0 Table 87 DDR SDRAM Timing Low Register Offset 0x01408 NOTE The default values fit DDR2 400 speed grade Change these timing parameters according to the DDR SDRAM type and operating frequency Bits Field Type Description InitVal 3 0 Reserved RO Reserved 0x0 7 4 trep RW Activate to Command 0x2 Value 0 means one cycle value of 1 means two cycles and so on 11 8 tap RW Precharge Period precharge to active 0x2 Value 0 means one cycle value of 1 means two cycles and so on 15 12 twn RW Write Command to Precharge 0x2 Value 0 means one cycle value of 1 means two cycles and so on Copyright O 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 114 MARVELL Table 87 88F5182 Open Source Community Programmer s U
447. tor Pointer Session 1 Register Offset Ox9DE14 Bits Field Type Description InitVal 15 0 SecurityAcclDesc RW Security accelerator descriptor pointer for session 1 DWORD aligned Ptr1 0x0 Bits 16 17 18 29 30 and 31 are reserved and are assumed to be and are as 0 regardless of programming 31 116 Reserved RW Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 330 88F5182 MARVELL Open Source Community Programmer s User Guide Table 487 Security Accelerator Configuration Register Offset Ox9DEOS8 Bits Field Type Description InitVal 0 StopOnDecodeDi RW Controls whether the engine stops when digest error in decode gestErr 0x1 0 Do not stop on digest decode error 1 Stop on digest decode error 1 Reserved RW Must be 0 0x0 6 2 Reserved RES Reserved 0x0 7 ChOWaitForIDMA RW Channel 0 Wait for IDMA 0x0 When set to 1 Security channel 0 is activated only when bit 4 channel 0 lt Own gt field in the Interrupt Cause Register Table 537 p 360 is set to 1 8 Ch1WaitForIDMA RW Channel 1 Wait for IDMA 0x0 When set to 1 Security accelerator channel 1 is activated only when bit 12 channel 1 Own field in the Interrupt Cause Register Table 537 p 360 is set to 1 9 ChOActivatelDMA RW Channel 0 Activation for IDMA 0x0 When set to 1 Security acceler
448. trol High Register 0x01434 Table 104 p 125 DDR SDRAM Interface Mbus Timeout Register 0x01438 Table 105 p 126 DDR SDRAM MMask Register 0x014BO Table 106 p 126 Doc No MV S400130 00 Rev 0 5 Page 109 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary DDR SDRAM Controller Registers The base and size of a base address register may be changed only when that base address register is disabled A 5 1 DDR SDRAM Controller Address Decode Registers Table 77 CS 0 n Base Address Register Offset 0x01500 Bits Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved 0x0 31 24 Base RW CS 0 Base Address 0x00 Corresponds to Marvell processor core address bits 31 24 Table 78 CS 0 n Size Register Offset 0x01504 Bits Field Type Description InitVal 0 En RW Window Enable 0x1 0 Disable 1 Enable 15 1 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved OxFF 31 24 Size RW CS 0 n Bank Size OxOF Corresponds to Base Address bits 31 24 Must be programmed from LSB to MSB as a sequence of 1 s followed by a sequence of 0 s Table 79 CS 1 n Base Address Register Offset 0x01508 Bits Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved 0x0 31 24 Base RW CS 1 Base Address 0x10 Corresponds to Marvell processor core address bits 31 24
449. ueue is a circular queue FIFO whose location is configured by the EDMA Request Queue In Pointer Register Table 316 p 233 and the EDMA Request Queue Out Pointer Register Table 317 p 234 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 24 MARVELL 88F5182 E Open Source Community Programmer s User Guide e A queue is empty when Request Queue Out pointer reaches to the Request Queue In pointer A queue is full when Request Queue In pointer is written with the same value as the Request Queue Out pointer A full queue contains 128 32 entries as configured in field lt eEDMAQueLen gt e A queue contains N entries when the Request Queue Out pointer is N less than the Request Queue In pointer taking into account the wraparound condition See Figure 3 Command Request Queue 32 Entries on page 22 and Figure 5 Command Request Queue 128 Entries on page 23 Each 32 byte EDMA Command Request Block CRQB entry consists of EDMA parameters and commands for the ATA device The CRQB data structure is written by the CPU Table 2 provides a map of the CRQB data structure registers 7 2 3 2 EDMA Command Request Block CRQB Data Table 2 EDMA CRQB Data Structure Map Register Offset Page CRQB DWO0 cPRD Descriptor Table Base Low Address 0x00 Table 3 p 25 CRQB DW1 cPRD Descript
450. ult 0x0 value 31 4 Reserved RO Reserved 0x0 Table 94 DDR SDRAM Operation Control Register Offset 0x0142C Bits Field Type Description InitVal 1 0 CS RW DDR SDRAM chip select 0x0 Defines to which DDR SDRAM bank to issue the EMRS1 command This is useful for setting different ODT values for different DDR SDRAM banks 0x0 M CSn 0 0x1 M CSn 1 0x2 M CSn 2 0x3 M CSn 3 31 2 Reserved RO Reserved 0x0 Table 95 DDR SDRAM Mode Register Offset 0x0141C NOTE If configured to DDR1 SDRAM bits 11 9 are not relevant and must be set to 0x0 Bits Field Type Description InitVal 2 0 BL RW Burst Length 0x2 Must be set to 0x2 burst length of 4 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 118 88F5182 marveL Open Source Community Programmer s User Guide Table 95 DDR SDRAM Mode Register Continued Offset 0x0141C NOTE If configured to DDR1 SDRAM bits 11 9 are not relevant and must be set to 0x0 Bits Field Type Description InitVal 3 BT RW Burst Type 0x0 Must be set to 0x0 sequential burst 6 4 CL RW CAS Latency 0x3 For DDR1 SDRAM 0x2 CL 2 0x3 CL 3 0x4 CL 4 0x5 CL 1 5 0x6 CL 2 5 0x0 0x1 0x7 Reserved For DDR2 SDRAM 0x3 CL 3 0x4 CL 4 0x5 2 CL 5 0x0 0x2 0x6 0x7 R
451. ument Classification Proprietary Local to System Bridge Registers Table 35 Window0 Base Register Offset 0x20004 NOTE If the remap function for this register is not used the Remap field in the Window0 Remap Low Register must be set to same value as the Base field in this register Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Base RW Base Address 0x8000 Used with the lt Size gt field to set the address window size and location Corresponds to transaction address 31 16 Table 36 Window0 Remap Low Register Offset 0x20008 Bits Field Type Description InitVal 15 0 Reserved RSVD Reserved 0x0 31 16 Remap RW Remap Address 0x8000 Used with the Size field to specifies address bits 31 0 to be driven to the target interface Table 37 Window0 Remap High Register Offset 0x2000C Bits Field Type Description InitVal 31 0 RemapHigh RW Remap Address 0x0 Specifies address bits 63 32 to be driven to the target interface Table 38 Window1 Control Register Offset 0x20010 Bits Field Type Description InitVal 0 win_en RW Window1 Enable 0x1 See the Window0 Control Register Table 34 p 91 3 1 Reserved RSVD Reserved 0x0 7 4 Target RW Specifies the unit ID target interface associated with this window 0x3 See the Window0 Control Register Table 34 p 91 Copy
452. une 25 2007 Preliminary DDR SDRAM Controller Registers Table 83 CS 3 n Base Address Register Offset 0x01518 Bits Field Type Description InitVal 15 0 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved 0x0 31 24 Base RW CS 3 Base Address 0x30 Corresponds to Marvell processor core address bits 31 24 Table 84 CS 3 n Size Register Offset 0x0151C Bits Field Type Description InitVal 0 En RW Window Enable 0x1 0 Disable 1 Enable 15 1 Reserved RO Reserved 0x0 23 16 Reserved RW Reserved OxFF 31 24 Size RW CS 3 n Bank Size OxOF Corresponds to Base Address bits 31 24 Must be programmed from LSB to MSB as a sequence of 1 s followed by a sequence of 0 s A 5 2 DDR SDRAM Control Registers Table 85 DDR SDRAM Configuration Register Offset 0x01400 Bits Field Type Description InitVal 13 0 Refresh RW Refresh interval count value 0x0400 15 14 Dwidth RW 0x0 Reserved 0x2 0x1 16 bit DDR SDRAM interface 0x2 32 bit DDR SDRAM interface 0x3 Reserved Copyright 2007 Marvell June 25 2007 Preliminary Document Classification Proprietary Doc No MV S400130 00 Rev 0 5 Page 112 88F5182 marveL Open Source Community Programmer s User Guide Table 85 DDR SDRAM Configuration Register Continued Offset 0x01400 Bits Field Type Description InitVal 16 Dtype RW DDR SDRAM Typ
453. upon any of the error events interrupts address miss access protection write protection ownership violation Once the address is latched no new address is latched until the register is read NOTE No address will be latched where the respective interrupt is masked disabled See Table 538 Interrupt Mask Register on page 361 Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 362 88F5182 marveL Open Source Community Programmer s User Guide Table 540 Error Select Register Offset 0x608CC Bits Field Type Description 4 0 Sel RW Specifies the error event currently reported in the Error Address register 0x0 0x0 Reserved 0x1 AddrMissO 0x2 AccProtO 0x3 WrProtO 0x4 OwnO 0x5 0x7 Reserved 0x8 Reserved 0x9 AddrMiss1 OxA AccProt1 OxB WrProt1 OxC Own1 OxD OxF Reserved 0x10 Reserved 0x11 AddrMiss2 0x12 AccProt2 0x13 WrProt2 0x14 Own2 0x15 0x17 Reserved 0x18 Reserved 0x19 AddrMiss3 0x1A AccProt3 0x1B WrProt3 0x1C Own3 0x1D 0x1F Reserved Read Only 31 5 Reserved RO Read only 0x0 Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 363 Document Classification Proprietary June 25 2007 Preliminary A 16 XOR Engine Registers Table 541 XOR Engine Register Map XOR Engine Registers Register Offset Tab
454. uration Register Continued Offset Port 0 0x82000 Port 1 0x84000 Bits Field Type Description InitVal 25 Reserved RW Reserved 0x0 26 eDMAFBS RW Port Multiplier FIS Based Switching mode 0x0 When cleared to 0 the Basic DMA continues the data transfer until the end of the PRD table Then it clears field lt BasicDMAActive gt clears field lt BasicDMAPaused gt and halts These two fields are in the Basic DMA Status Register Table 332 p 243 When this field is set to 1 the Basic DMA stops on the FIS boundary During a write command the Basic DMA 1 Completes the 8 KB FIS transmission to the drive Max frame transmission size can be change by the TransFrm Siz field in the Serial ATA Interface Test Control Register Table 351 p 259 Clears lt BasicDMAActive gt Sets lt BasicDMAPauseds if the command was not completed Halts uring a read command the Basic DMA Completes the data transfer associates with a single FIS reception If field lt eEarlyCompletionEn gt is set it waits for data visible in the system memory 3 Clears lt BasicDMAActive gt 4 Sets lt BasicDMAPaused gt if command was not completed 5 Halts 0 FIS based Switching mode disabled Basic DMA stops on a command PRD boundary 1 FIS Based Switching mode enabled Basic DMA stops on a FIS boundary NOTE This bit must be set to 1 when FIS based switching mode is used For the best Performance when a single drive
455. urrent Queue Descriptor Pointer TCQDP QO 0x726C0 Table 411 p 298 Transmit Queue Token Bucket Counter TQxTBC NOTE Transmit Queues 1 7 are reserved QO 0x72700 Q1 0x72710 Q2 0x72720 Q3 0x72730 Q4 0x72740 Q5 0x72750 Q6 0x72760 Q7 0x72770 Table 412 p 298 Transmit Queue Token Bucket Configuration TQxTBC NOTE Transmit Queues 1 7 are reserved QO 0x72704 Q1 0x72714 Q2 0x72724 Q3 0x72734 Q4 0x72744 Q5 0x72754 Q6 0x72764 Q7 0x72774 Table 413 p 298 Transmit Queue Arbiter Configuration TQxAC NOTE Transmit Queues 1 7 are reserved QO 0x72708 Q1 0x72718 Q2 0x72728 Q3 0x72738 Q4 0x72748 Q5 0x72758 Q6 0x72768 Q7 0x72778 Table 414 p 299 Destination Address Filter Special Multicast Table DFSMT 0x 73400 0x734FC Table 415 p 299 Destination Address Filter Other Multicast Table DFUT 0x73500 0x735FC Table 416 p 300 Destination Address Filter Unicast Table DFUT 0x73600 0x7360C Table 417 p 301 MAC MIB Counters 0x73000 0x7307C Description under Appendix A 9 3 Port MIB Counter Register on page 302 Doc No MV S400130 00 Rev 0 5 Page 269 Document Classification Proprietary Copyright O 2007 Marvell June 25 2007 Preliminary Gigabit Ethernet Controller Registers A 9 1 Gigabit Ethernet Unit Global Registers Table 365 PHY Address Offset 0x72000 Bits Field Type Descri
456. us Interrupt flag is kept 0 31 8 Reserved RO 0x0 Reserved Copyright 2007 Marvell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 338 88F5182 marveL Open Source Community Programmer s User Guide Table 497 TWSI Baud Rate Offset 0x1100C Bits Field Type Description InitVal 2 0 N WO See exact frequency calculation in the TWSI section 0x4 Write only 6 3 M WO See exact frequency calculation in the TWSI section 0x4 Write only 31 7 Reserved RO Reserved 0x0 Table 498 TWSI Soft Reset Offset 0x1101C Bits Field Type Description InitVal 31 0 Rst WO Write Only 0x0 Write to this register resets the TWSI logic and sets all TWSI registers to their reset values Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 339 Document Classification Proprietary June 25 2007 Preliminary A 13 UART Interface Registers UART Interface Registers N Note A number of UART registers share the same offsets see Table 499 In addition to writing to these register addresses lt DivLatchRdWrt gt bit 7 of the Line Control Register LCR Register Table 507 p 344 must be set cleared as follows Set lt DivLatchRdWrt gt to address the Divisor Latch Low DLL Register and Divisor Latch High DLH Register e Clear lt DivLatchRdWrt gt to address th
457. us in a read is limited to 128B bits 8 lt eRdBSz gt and 11 lt eRdBSzExt gt in this register are both 0 the value of the lt eCutThroughEn gt bit is ignored and the cut though operation is disabled 0 Store and forward 1 Cut through Doc No MV S400130 00 Rev 0 5 Page 227 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Serial ATA Host Controller SATAHC Registers Table 311 EDMA Configuration Register Continued Offset Port 0 0x82000 Port 1 0x84000 Bits Field Type Description InitVal 18 eEarlyComple RW This bit enables Basic DMA Early completion tionEn 0x0 When this bit is set to 1 Basic DMA Early completion is enabled The DMA completes operation when all data is transferred from the drive to the Mbus and it updates the following bits immediately instead of waiting for this data to be visible in the system memory e The BasicDMAActive field in the Basic DMA Status Register Table 332 p 243 is cleared to 0 e When EDMA is disabled Bits 3 0 lt DMAxDone gt in the SATAHC Interrupt Cause Register Table 299 p 220 is set to 1 Regardless to this bit value when EDMA is enabled the EDMA ensures all data is visible in system memory and only then it sets bit lt SaCrpbxDone gt in the EDMA Interrupt Error Cause Register Table 313 p 230 When EDMA controls the Basic DMA it is recommended to set this bit to 1 When the CPU controls the Basi
458. value 0x0 to this field on every access 29 DisSwap RW Hot Swap detection 0x0 0 On 1 Off When hot swapping no COMRESET COMINIT will be sent 30 Reserved RES Reserved 0x0 NOTE Must write the value 0x0 to this field on every access 31 OOBBypass RW Out of band bypass 0x0 PHY Ready method selection 0 Normal 1 Bypass OOB handshake and force PhyRdy Doc No MV S400130 00 Rev 0 5 Page 251 Copyright 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary Table 344 PHY Mode 1 Register Offset Port 0 0x8232C Port 1 0x8432C NOTE This register must be fully written on every write access to any of its fields Serial ATA Host Controller SATAHC Registers Bits Name Type Description InitVal 31 0 Reserved RES Reserved 0x0 NOTE Must write the value 32h 40550520 to this field on every access Table 345 PHY Mode 2 Register Offset Port 0 0x82330 Port 1 0x84330 NOTE This register must be fully written on every write access to any of its fields Bits Name Type Description InitVal 4 0 Reserved Reserved NOTE Must write the value 5h OF to this field on every access 7 5 TxPre RW Transmitter Pre emphasis 0x2 000 1 0 00Z 1 001 1 0 05Z 1 010 1 0 10Z 1 011 1 0 15Z 1 100 1 0 20Z 1 101 1 0 25Z 1 110 1 0 30Z 1 111 1 0 35Z 1 10 8 TxAmp RW Transmitter Differential Amplitude 0x4 000 l 4 mA V 200 mVp p 0
459. vell June 25 2007 Preliminary Doc No MV S400130 00 Rev 0 5 Document Classification Proprietary Page 250 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 342 PHY Mode 3 Register Continued Offset Port 0 0x82310 Port 1 0x84310 NOTE This register must be fully written on every write access to any of its fields Bits Name Type Description InitVal 31 5 Reserved RES Reserved 0x0 NOTE Must write the value 27h 5815601 to this field on every access Table 343 PHY Mode 4 Register Offset Port 0 0x82314 Port 1 0x84314 NOTE This register must be fully written on every write access to any of its fields Bits Name Type Description InitVal 1 0 PhylntConfPara RW PHY Internal Configuration Parameter 0x2 Must initialize 0x01 to this field 17 2 Reserved RES Reserved 0x0 NOTE Must write the value 16h 0001 to this field on every access 20 18 HotPlugTimer RW Delay to Disconnect Hot Plug 0x011 000 2ms 001 4ms 010 10ms 011 16 ms Default 100 32 ms 101 2 64 ms 110 2 128 ms 111 2 256 ms 24 21 Reserved RW Reserved 0x0 NOTE Must write the value 4h O to this field on every access 25 PortSelector RW Port Selector 0x0 0 Port Selector function is off 1 A 0 to 1 transition of this bit will cause Port Selector protocol based OOB sequence to be sent 28 26 Reserved RES Reserved 0x0 NOTE Must write the
460. vell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 70 88F5182 marveL Open Source Community Programmer s User Guide Table 173 PCI Express Advanced Error Capability and Control Register sese 167 Offset 0x40118 Table 174 PCI Express Header Log First DWORD Register A 167 Offset 0x4011C Table 175 PCI Express Header Log Second DWORD Register essen 168 Offset 0x40120 Table 176 PCI Express Header Log Third DWORD Register nennen 168 Offset 0x40124 Table 177 PCI Express Header Log Fourth DWORD Heotster AAA 168 Offset 0x40128 A 7 PCI Interface Registers cccsecessseeceseeeesseeeeeneeeeeseaesenseeeeseaaesnseeaessnaesenseeesesnaeeneneaes 169 Table 187 Gan DIE 173 Offset 0x30C08 Sleigh 173 Offset 0x30D08 Table 189 CSn 2 BAR SIZ e 173 Offset OX80COC Table 190 CSS BAR SIZE E 173 Offset OXS0DOC Table 191 RER EE 174 Offset 0x30C10 Table 192 Re OR BE 174 Offset 0x30D10 Table 193 DevGSn 2 BAR RE 174 Offset 0x30D18 Table t94 Boot CSQm BAR E 174 Offset 0x30D14 Eo mulie M 174 Offset 0x30D1C Table 196 P2P I O BAR Size inii iie need added EELER oa nevis Mane die esl
461. ware by clearing XEactive bit and asserting the stopped interrupt NOTE Setting XEstop when XOR Engine is inactive or paused will be disregarded 2 XEpause WO 0 Clearing this bit has no meaning and will be disregarded by XOR 0x0 Engine 1 XOR Engine Pause When the software sets this bit it pauses the relevant XOR Engine channel XOR Engine will suspend at the earliest opportunity refer to Pause Operation section After entering paused state XOR Engine will signal the software by clearing XEactive bit and asserting the paused interrupt 3 XErestart WO XOR Engine Restart after Pause Control 0x0 0 Clearing this bit has no meaning and will be disregarded by the XOR Engine 1 The XOR Engine restart after pause Setting this bit after the XOR Engine channel enters the pause state re activates the channel and resumes the suspended operation execution Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 368 MARVELL 88F5182 Open Source Community Programmer s User Guide Table 544 XOR Engine 0 1 Activation XEXACTR Offset XORO 0x60920 XOR1 0x60924 Bits Field Type Description InitVal 5 4 XEstatus RO XOR Engine Status indication 0x0 0 Channel not active 1 Channel active 2 Channel paused 3 Reserved 31 6 Reserved RO Reserved 0x0 A 16 2 XOR Engine Interrupt Reg
462. x TCP checksum mode 0x1 0 Calculate without pseudo header 1 Calculation include pseudo header 31 26 Reserved RO Reserved 0x0 Table 382 Port Configuration Extend PxCX Offset 0x72404 Bits Field Type Description InitVal 0 Reserved RO Reserved 0x0 1 Span RW Spanning Tree packets capture enable 0x0 0 BPDU packets are treated as normal Multicast packets 1 BPDU packets are trapped and sent to the Port Configuration register BPDU queue 2 Reserved RO Reserved 0x0 31 3 Reserved RO Reserved 0x0 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 278 88F5182 marveL Open Source Community Programmer s User Guide Table 383 MII Serial Parameters Offset 0x72408 Bits Field Type Description InitVal 1 0 JAM LENGTH RW These two bits determine the JAM Length in Back Pressure as follows 0x3 00 12K bit times 01 24K bit times 10 32K bit times 11 48K bit times NOTE These bits can only be changed when lt PortEn gt field is set to 0 in the Port Control Register Port is disabled 6 2 JAM IPG RW These five bits determine the JAM IPG The step is 4 bit times The 0x8 JAM IPG gt varies between 4 and 124 bit times NOTE These bits can only be changed when lt PortEn gt field is set to 0 in the Port Control Register Port is disabled The JAM IPG gt bit cannot be
463. x0 Table 529 Channel Current Descriptor Pointer Register Offset Channel 0 0x60870 Channel 1 0x60874 Channel 2 0x60878 Channel 3 0x6087C Bits Field Type Description 31 0 CDPTRO0 1 2 3 RW Bits 31 0 of the address from which the current descriptor was fetched 0x0 Doc No MV S400130 00 Rev 0 5 Page 355 Copyright O 2007 Marvell Document Classification Proprietary June 25 2007 Preliminary IDMA Controller Interface Registers A 15 2 IDMA Address Decoding Registers Table 530 Base Address Register x Offset BARO 0x60A00 BAR1 0x60A08 BAR2 0x60A10 BAR3 0x60A18 BAR4 0x60A20 BAR5 0x60A28 BAR6 0x60A30 BAR7 0x60A38 Bits Field Type Description 3 0 Target RW Target unit ID 0x0 Specifies the target interface associated with this window 0x0 DRAM 0x1 Devices 0x2 Reserved 0x3 PCI 0x3 Reserved 0x4 PCI Express 0x5 Tunit SRAM Other values Reserved 7 4 Reserved RO Reserved 0x0 15 8 Attr RW Specifies target unit specific attributes 0x0 31 16 Base RW Window Base Address 0x0 Table 531 Size Register x Offset SRO 0x60A04 SR1 0x60A0C SR2 0x60A14 SR3 0x60A1C SR4 0x60A24 SR5 0x60A2C SR6 0x60A34 SR7 0x60A3C Bits Field Type Description 15 0 Reserved RO Reserved 0x0 31 16 Size RW Window Size 0x0 The number of 1s specifies the size of the window in 64 KB granularity e g a value of 0x00ff specifie
464. x1101C Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 83 Document Classification Proprietary June 25 2007 Preliminary A 13 Table 500 Table 501 Table 502 Table 503 Table 504 Table 505 Table 506 Table 507 Table 508 Table 509 Table 510 Table 511 A 14 Table 513 Table 514 Table 515 Table 516 Table 517 Table 518 Table 519 Table 520 A 15 Table 525 Table 526 List of Registers UART Interface Registers eeeeeseeeeseeeeeeeeee eene nnne enne nnne nn nnnm n annee nnn nnns 340 Receive Buffer Register RBR iet c Ue nete es 341 Offset UART 0 0x12000 UART 1 0x12100 Transmit Holding Register T HB eir et Ee ede cade PR e ead PORE Leu dag 341 Offset UART 0 0x12000 UART 1 0x12100 Divisor Lateh Low DLL Register 2 2 eiie entrer retener enero eet 342 Offset UART 0 0x12000 UART 1 0x12100 Interrupt Enable Register IEFi n rtt etre rene e cuss e Dni peer ect rr dee EES 342 Offset UART 0 0x12004 UART 1 0x12104 Divisor Latch High DLH Register sse nennen rennen rretnr et rretr enne 343 Offset UART 0 0x12004 UART 1 0x12104 Interrupt Identity Register IIR kan 343 Offset UART 0 0x12008 UART 1 0x12108 FIFO Control Register FOR aree osse E esr aeter eode tra defe 343 Offset UART 0 0x12008 UART 1 0x12108 Line Control Register ECH eret ERE NEE EEN R
465. x84040 Table 325 p 239 EDMA Halt Conditions Register Port 0 0x82060 Port 1 0x84060 Table 326 p 239 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 214 MHZ sss MARVELL Open Source Community Programmer s User Guide Table 290 EDMA Registers Map Continued Register Offset Table Page Register EDMA NCQO Done TCQO Outstanding Status Port 0 0x82094 Port 1 0x84094 Table 327 p 240 Register EDMA NCQ1 Done TCQ1 Outstanding Status Port 0 0x82098 Port 1 0x84098 Table 328 p 240 Register EDMA NCQ2 Done TCQ2 Outstanding Status Port 0 0x8209C Port 1 0x8409C Table 329 p 240 Register EDMA NCQ3 Done TCQ3 Outstanding Status Port 0 0x820AQ Port 1 0x840A0 Table 330 p 241 A 8 4 Shadow Register Block Registers Map Table 291 Shadow Register Block Registers Map Bits Bits Bits Bits Offset Table Page 31 24 23 16 15 8 7 0 Reserved Reserved Device PIO Data register Port 0 0x82100 Port 1 0x84100 see ATA Reserved Reserved Reserved Device Port 0 0x82104 Port 1 0x84104 lee specification Features Fea tures Current Error register Reserved Reserved Reserved Device Sector Port 0 0x82108 Port 1 0x84108 Count Sector Count Current register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 215 Docu
466. y Column 1 Register Ox9DDD8 Table 477 p 327 AES Decryption Key Column 0 Register Ox9DDDC Table 478 p 327 AES Decryption Key Column 7 Register Ox9DDCO Table 479 p 328 AES Decryption Key Column 6 Register Ox9DDC4 Table 480 p 328 AES Decryption Key Column 5 Register Ox9DDC8 Table 481 p 328 AES Decryption Key Column 4 Register Ox9DDCC Table 482 p 328 AES Decryption Command Register Ox9DDFO Table 483 p 329 Security Accelerator Registers Security Accelerator Command Register 0x9DE00 Table 484 p 329 Security Accelerator Descriptor Pointer Session 0 Regis 0x9DE04 Table 485 p 330 ter Security Accelerator Descriptor Pointer Session 1 Regis 0x9DE14 Table 486 p 330 ter Security Accelerator Configuration Register 0x9DE08 Table 487 p 331 Security Accelerator Status Register Ox9DEOC Table 488 p 331 Interrupt Cause Registers Cryptographic Engines and Security Accelerator Inter O0x9DE20 Table 489 p 332 rupt Cause Register Cryptographic Engines and Security Accelerator Inter 0x9DE24 Table 490 p 334 rupt Mask Register Doc No MV S400130 00 Rev 0 5 Copyright 2007 Marvell Page 315 Document Classification Proprietary June 25 2007 Preliminary Cryptographic Engine and Security Accelerator Registers A 11 1 DES Engine Registers Table 436 DES Data Out Low Register Offset Ox9DD78 Bits Field Type Description InitVal 31 0 DataOutLo RO When the DES or the Triple DES completes the calculat
467. y accelerator session 0 termination clear indication The 0x0 interrupt is set when the Security accelerator session 0 completes its opera tion NOTE Cleared this bit before writing 1 to lt EnSecurityAcclO gt field in the Security Accelerator Command Register Table 484 p 329 6 Accint1 RWO This bit is the Security accelerator session 1 termination clear indication The 0x0 interrupt is set when the Security accelerator session 1 completes its opera tion NOTE Cleared this bit before writing 1 to lt EnSecurityAccl1 gt field in the Security Accelerator Command Register Table 484 p 330 Copyright 2007 Marvell Doc No MV S400130 00 Rev 0 5 June 25 2007 Preliminary Document Classification Proprietary Page 332 e 88F5182 E marveL Open Source Community Programmer s User Guide Table 489 Cryptographic Engines and Security Accelerator Interrupt Cause Register Continued Offset Ox9DE20 NOTE The cryptographic engine has a dedicated Interrupt Cause register This register is set by events occurring in the engine Clearing this register s bits is done by writing O to the cause bits Writing 1 to a bit has no effect This register is shared by the DES and the Authentication engine Bits Field Type InitVal Description 7 AccAndIDMAIntO RWO 0x0 Acceleration and IDMA Interrupt 0 This bit is set to 1 when the entire security accelerator process is completed including both encryption authentication proces

88F5182 Open Source Community Programmers' User Guide

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